NC7SZ373P6X - APTINA IMAGING - Datasheet.Directory

January, 2021 − Rev. 2

1Publication Order Number:

NC7SZ373/D

TinyLogic UHS D-Type

Latch with 3-STATE Output

NC7SZ373

Description

The NC7SZ373 is a single positive edge−triggered D−type CMOS

Lach with 3−STATE output from ON Semiconductor’s Ultra High

Speed Series of TinyLogic in the space saving SC70 6−lead package.

The device is fabricated with advanced CMOS technology to achieve

ultra high speed with high output drive while maintaining low static

power dissipation over a very broad VCC operating range. The device

is specified to operate over the 1.65 V to 5.5 V VCC range. The inputs

and output are high impedance when VCC is 0 V. Inputs tolerate

voltages up to 5.5 V independent of VCC operating voltage. The latch

appears transparent to the data when Latch Enable (LE) is HIGH.

When LE is LOW, the data that meets the setup time is latched. The

output tolerates voltages above VCC in the 3−STATE condition.

Features

•Space Saving SC−88 6−Lead Package

•Ultra Small MicroPak™ Leadless Package

•Ultra High Speed: tPD = 2.6 ns Typ into 50 pF at 5 V VCC

•High Output Drive: ±24 mA at 3 V VCC

•Broad VCC Operating Range: 1.65 V to 5.5 V

•Matches the Performance of LCX when Operated at 3.3 V VCC

•Power Down High Impedance Inputs / Output

•Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation

•Patented Noise / EMI Reduction Circuitry Implemented

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Figure 1. Logic Symbol

IEEC / IEC

OE See detailed ordering, marking and shipping information in the

package dimensions section on page 7 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

www.onsemi.com

SC−88

CASE 419B−02

SIP6 1.45x1.0

CASE 127EB

D4KK

XYZ

D4, Z73 = Specific Device Code

KK = 2−Digit Lot Run Traceability Code

XY = 2−Digit Date Code Format

Z = Assembly Plant Code

M = Date Code*

G= Pb−Free Package

Pin 1

Z73M

(Note: Microdot may be in either location)

*Date Code orientation and/or position may

vary depending upon manufacturing location.

NC7SZ373

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Connection Diagrams

Figure 2. SC−88 (Top View)

(Top View) AAA

Pin One

LE 1 6 OE

GND 2 5 VCC

D 3 4 Q

LE OE

GND VCC

Figure 3. Pin 1 Orientation

Figure 4. MicroPak (Top Through View)

AAA = Product Code Top Mark − see ordering code

NOTE: Orientation of Top Mark determines Pin One location.

Read the top product code mark left to right, Pin One

is the lower left pin (see diagram).

PIN DESCRIPTIONS

Pin Name Description

D Data Input

CP Latch Enable Input

OE Output Enable Input

QLatch Output

FUNCTION TABLE

Inputs Output

LE D OE Q

H L L L

H H L H

L X L Qn−1

X X H Z

H = HIGH Logic Level X = Immaterial

L = LOW Logic Level Z = HIGH Impedance

Qn−1 = Previous state prior to HIGH−to−LOW transition of latch

enable

NC7SZ373

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ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min Max Unit

VCC Supply Voltage −0.5 +6.5 V

VIN DC Input Voltage −0.5 +6.5 V

VOUT DC Output Voltage −0.5 +6.5 V

IIK DC Input Diode Current VIN < 0 V − −50 mA

IOK DC Output Diode Current VOUT < 0 V − −50 mA

IOUT DC Output Source / Sink Current −±50 mA

ICC / IGND DC VCC / GND Current −±50 mA

TSTG Storage Temperature Range −65 +150 °C

TJJunction Temperature under Bias −150 °C

TLJunction Lead Temperature (Soldering, 10 Seconds) −260 °C

PDPower Dissipation in Still Air SC−88 −332 mW

MicroPak −812

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Conditions Min Max Unit

VCC Supply Voltage Operating 1.65 5.5 V

Supply Voltage Data Retention 1.5 5.5

VIN Input Voltage 0 5.5 V

VOUT Output Voltage Active State 0 VCC V

3−STATE 0 5.5 V

tr, tfInput Rise and Fall Time VCC = 1.8 V, 2.5 V ±0.2 V 0 20 ns/V

VCC = 3.3 V ±0.3 V 0 10

VCC = 5.5 V ±0.5 V 0 5

TAOperating Temperature −40 +85 °C

qJA Thermal Resistance SC−88 −377 °C/W

MicroPak −154

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

1. Unused inputs must be held HIGH or LOW. They may not float.

NC7SZ373

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DC ELECTICAL CHARACTERISTICS

Symbol Parameter VCC (V) Conditions

TA = +25°C TA = −40 to +85°C

Unit

Min Typ Max Min Max

VIH HIGH Level Control

Input Voltage

1.65 to 1.95 0.65 VCC − − 0.65 VCC −V

2.3 to 5.5 0.7 VCC − − 0.7 VCC −

VIL LOW Level Control

Input Voltage

1.65 to 1.95 − − 0.35 VCC −0.35 VCC V

2.3 to 5.5 − − 0.3 VCC −0.3 VCC

VOH HIGH Level Control

Output Voltage

1.65 VIN = VIH

or VIL

IOH = −100 mA 1.55 1.65 −1.55 −V

1.8 1.7 1.8 −1.7 −

2.3 2.2 2.3 −2.2 −

3.0 2.9 3.0 −2.9 −

4.5 4.4 4.5 −4.4 −

1.65 IOH = −4 mA 1.24 1.52 −1.29 −

2.3 IOH = −8 mA 1.9 2.15 −1.9 −

3.0 IOH = −16 mA 2.4 2.8 −2.4 −

3.0 IOH = −24 mA 2.3 2.68 −2.3 −

4.5 IOH = −32 mA 3.8 4.2 −3.8 −

VOL LOW Level Control

Output Voltage

1.65 VIN = VIH

or VIL

IOL = 100 mA−0.0 0.08 −0.0 V

1.8 −0.0 0.1 −0.1

2.3 −0.0 0.1 −0.1

3.0 −0.0 0.1 −0.1

4.5 −0.0 0.1 −0.1

1.65 IOL = 4 mA −0.08 0.24 −0.24

2.3 IOL = 8 mA −0.10 0.3 −0.3

3.0 IOL = 16 mA −0.15 0.4 −0.4

3.0 IOL = 24 mA −0.22 0.55 −0.55

4.5 IOL = 32 mA −0.22 0.55 −0.55

IIN Input Leakage

Current

1.65 to 5.5 0 ≤ VIN ≤ 5.5 V − − ±0.1 −±1.0 mA

IOZ 3−STATE Output

Leakage

1.65 to 5.5 VIN = VIL or VIH

0 ≤ VOUT ≤ 5.5 V

− − ±0.5 −±5.0 mA

IOFF Power Off Leakage

Current

0.0 VIN or VOUT = 5.5 V − − 1.0 −10 mA

ICC Quiescent Supply

Current

1.65 to 5.5 VIN = 5.5 V, GND − − 1.0 −10 mA

NC7SZ373

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AC ELECTRICAL CHARACTERISTICS

Symbol Parameter VCC (V) Conditions

TA = +25°C TA = −40 to +85°C

Min Typ Max Min Max Unit

tPLH

tPHL

Propagation Delay

D to Q

1.65 CL = 15 pF, RD = 1 MW,

S1 = Open

(Figures 5, 7)

−9.0 15.0 −16.0 ns

1.8 −6.1 10.0 −10.5

2.5 ±0.2 −3.6 6.5 −6.8

3.3 ±0.3 −2.7 4.6 −5.0

5.0 ±0.5 −2.0 3.4 −3.7

3.3 ±0.3 CL = 50 pF, RD = 500 W

S1 = Open

(Figures 5, 7)

−3.3 5.5 −6.2

5.0 ±0.5 −2.6 4.3 −4.8

tPLH

tPHL

Propagation Delay

LE to Q

1.65 CL = 15 pF, RD = 1 MW,

S1 = Open

(Figures 5, 7)

−9.0 1.45 −15.0 ns

1.8 −6.0 9.6 −10.0

2.5 ±0.2 −3.5 6.1 −6.6

3.3 ±0.3 −2.6 4.4 −4.8

5.0 ±0.5 −2.0 3.2 −3.5

3.3 ±0.3 CL = 50 pF, RD = 500 W,

S1 = Open

(Figures 5, 8)

−3.3 5.3 −6.2

5.0 ±0.5 −2.6 4.2 −4.6

tPZL

tPZH

Output Enable Time 1.65 CL = 50 pF, VI = 2 x VCC,

RU, RD = 500 W,

S1 = GND for tPZH

S1 = VI for tPZL

(Figures 5, 8)

−9.0 13.5 −14.6 ns

1.8 −6.0 9.0 −9.5

2.5 ±0.2 −3.7 6.0 −6.6

3.3 ±0.3 −2.8 5.0 −5.3

5.0 ±0.5 −2.2 3.7 −3.9

tPLZ

tPHZ

Output Disable Time 1.65 CL = 50 pF, VI = 2 x VCC,

RU, RD = 500 W,

S1 = GND for tPHZ

S1 = VI for tPLZ

(Figures 5, 8)

−7.7 12.0 −13.0 ns

1.8 −5.1 8.0 −8.5

2.5 ±0.2 −3.5 6.0 −6.3

3.3 ±0.3 −2.8 4.5 −4.7

5.0 ±0.5 −2.3 3.7 −3.9

tSSetup Time, D to LE 2.5 ±0.2 CL = 50 pF, RD = 500 W,

S1 = Open

(Figures 5, 9)

− − − 2.0 −ns

3.3 ±0.3 − − − 1.5 −

5.0 ±0.5 − − 1.5 −

tHHold Time, D to LE 2.5 ±0.2 CL = 50 pF, RD = 500 W,

S1 = Open

(Figures 5, 9)

− − − 1.5 −ns

3.3 ±0.3 − − − 1.5 −

5.0 ±0.5 − − − 1.5 −

tWPulse Width, LE 2.5 ±0.2 CL = 50 pF, RD = 500 W,

S1 = Open

(Figures 5, 9)

− − − 3.0 −ns

3.3 ±0.3 − − − 3.0 −

5.0 ±0.5 − − − 3.0 −

NC7SZ373

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CAPACITANCE (TA = +25°C, f = 1 MHz)

Symbol Parameter Condition Typ Max Units

CIN Input Capacitance VCC = Open, VIN = 0 V or VCC 3−pF

COUT Output Capacitance VCC = 3.3 V, VIN = 0 V or VCC 4−pF

CPD Power Dissipation Capacitance

(Note 2)

VCC = 3.3 V

VCC = 5.0 V

−

2. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at

no output loading and operating at 50% duty cycle. (See Figure 6)

CPD is related to ICCD dynamic operating current by the expression: ICCD = (CPD) (VCC) (fIN) + (ICCstatic).

AC Loading and Waveforms

CL includes load and stray capacitance

Input PRR = 1.0 MHz, tW = 500 ns.

Figure 5. AC Test Circuit

D Input = AC Waveform; tr = tf = 1.8 ns;

D Input PRR = 10 MHz; Duty Cycle = 50%.

VCC

Figure 6. ICCD Test Circuit

VCC

CLRD

OUTPUT

Figure 7. AC Waveforms

LE Input

D Input

Q Output

Figure 8. AC Waveforms

VIN

OPEN

GND

Figure 9. AC Waveforms

NC7SZ373

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ORDERING INFORMATION

Device Top Mark Packages Shipping†

NC7SZ373P6X Z73 6−Lead SC70, EIAJ SC88, 1.25 mm Wide 3000 / Tape & Reel

NC7SZ373L6X D4 6−Lead MicroPak, 1.00 mm Wide 5000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MicroPak is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

SIP6 1.45X1.0

CASE 127EB

ISSUE O

DATE 31 AUG 2016

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98AON13590G

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

SIP6 1.45X1.0

SC−88/SC70−6/SOT−363

CASE 419B−02

ISSUE Y

DATE 11 DEC 2012

SCALE 2:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-

SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.

4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF

THE PLASTIC BODY AND DATUM H.

5. DATUMS A AND B ARE DETERMINED AT DATUM H.

6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE

LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.

7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN

EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-

TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OF THE FOOT.

Cddd M

123

654

XXXMG

XXX = Specific Device Code

M = Date Code*

G= Pb−Free Package

GENERIC

MARKING DIAGRAM*

STYLES ON PAGE 2

DIM MIN NOM MAX

MILLIMETERS

A−−− −−− 1.10

A1 0.00 −−− 0.10

ddd

b0.15 0.20 0.25

C0.08 0.15 0.22

D1.80 2.00 2.20

−−− −−− 0.043

0.000 −−− 0.004

0.006 0.008 0.010

0.003 0.006 0.009

0.070 0.078 0.086

MIN NOM MAX

INCHES

0.10 0.004

E1 1.15 1.25 1.35

e0.65 BSC

L0.26 0.36 0.46

2.00 2.10 2.20

0.045 0.049 0.053

0.026 BSC

0.010 0.014 0.018

0.078 0.082 0.086

(Note: Microdot may be in either location)

*Date Code orientation and/or position may

vary depending upon manufacturing location.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.65

0.66

DIMENSIONS: MILLIMETERS

0.30

PITCH

2.50

RECOMMENDED

TOP VIEW

SIDE VIEW END VIEW

bbb H

SEATING

PLANE

DETAIL A E

A2 0.70 0.90 1.00 0.027 0.035 0.039

L2 0.15 BSC 0.006 BSC

aaa 0.15 0.006

bbb 0.30 0.012

ccc 0.10 0.004

A-B D

aaa C

2X 3 TIPS

aaa H D

PLANE

DETAIL A

GAGE

ccc C

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42985B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

SC−88/SC70−6/SOT−363

STYLE 1:

PIN 1. EMITTER 2

2. BASE 2

3. COLLECTOR 1

4. EMITTER 1

5. BASE 1

6. COLLECTOR 2

STYLE 3:

CANCELLED

STYLE 2:

CANCELLED

STYLE 4:

PIN 1. CATHODE

2. CATHODE

3. COLLECTOR

4. EMITTER

5. BASE

6. ANODE

STYLE 5:

PIN 1. ANODE

2. ANODE

3. COLLECTOR

4. EMITTER

5. BASE

6. CATHODE

STYLE 6:

PIN 1. ANODE 2

2. N/C

3. CATHODE 1

4. ANODE 1

5. N/C

6. CATHODE 2

STYLE 7:

PIN 1. SOURCE 2

2. DRAIN 2

3. GATE 1

4. SOURCE 1

5. DRAIN 1

6. GATE 2

STYLE 8:

CANCELLED

STYLE 11:

PIN 1. CATHODE 2

2. CATHODE 2

3. ANODE 1

4. CATHODE 1

5. CATHODE 1

6. ANODE 2

STYLE 9:

PIN 1. EMITTER 2

2. EMITTER 1

3. COLLECTOR 1

4. BASE 1

5. BASE 2

6. COLLECTOR 2

STYLE 10:

PIN 1. SOURCE 2

2. SOURCE 1

3. GATE 1

4. DRAIN 1

5. DRAIN 2

6. GATE 2

STYLE 12:

PIN 1. ANODE 2

2. ANODE 2

3. CATHODE 1

4. ANODE 1

5. ANODE 1

6. CATHODE 2

STYLE 13:

PIN 1. ANODE

2. N/C

3. COLLECTOR

4. EMITTER

5. BASE

6. CATHODE

STYLE 14:

PIN 1. VREF

2. GND

3. GND

4. IOUT

5. VEN

6. VCC

STYLE 15:

PIN 1. ANODE 1

2. ANODE 2

3. ANODE 3

4. CATHODE 3

5. CATHODE 2

6. CATHODE 1

STYLE 17:

PIN 1. BASE 1

2. EMITTER 1

3. COLLECTOR 2

4. BASE 2

5. EMITTER 2

6. COLLECTOR 1

STYLE 16:

PIN 1. BASE 1

2. EMITTER 2

3. COLLECTOR 2

4. BASE 2

5. EMITTER 1

6. COLLECTOR 1

STYLE 18:

PIN 1. VIN1

2. VCC

3. VOUT2

4. VIN2

5. GND

6. VOUT1

STYLE 19:

PIN 1. I OUT

2. GND

3. GND

4. V CC

5. V EN

6. V REF

STYLE 20:

PIN 1. COLLECTOR

2. COLLECTOR

3. BASE

4. EMITTER

5. COLLECTOR

6. COLLECTOR

STYLE 22:

PIN 1. D1 (i)

2. GND

3. D2 (i)

4. D2 (c)

5. VBUS

6. D1 (c)

STYLE 21:

PIN 1. ANODE 1

2. N/C

3. ANODE 2

4. CATHODE 2

5. N/C

6. CATHODE 1

STYLE 23:

PIN 1. Vn

2. CH1

3. Vp

4. N/C

5. CH2

6. N/C

STYLE 24:

PIN 1. CATHODE

2. ANODE

3. CATHODE

4. CATHODE

5. CATHODE

6. CATHODE

STYLE 25:

PIN 1. BASE 1

2. CATHODE

3. COLLECTOR 2

4. BASE 2

5. EMITTER

6. COLLECTOR 1

STYLE 26:

PIN 1. SOURCE 1

2. GATE 1

3. DRAIN 2

4. SOURCE 2

5. GATE 2

6. DRAIN 1

STYLE 27:

PIN 1. BASE 2

2. BASE 1

3. COLLECTOR 1

4. EMITTER 1

5. EMITTER 2

6. COLLECTOR 2

STYLE 28:

PIN 1. DRAIN

2. DRAIN

3. GATE

4. SOURCE

5. DRAIN

6. DRAIN

STYLE 29:

PIN 1. ANODE

2. ANODE

3. COLLECTOR

4. EMITTER

5. BASE/ANODE

6. CATHODE

SC−88/SC70−6/SOT−363

CASE 419B−02

ISSUE Y

DATE 11 DEC 2012

STYLE 30:

PIN 1. SOURCE 1

2. DRAIN 2

3. DRAIN 2

4. SOURCE 2

5. GATE 1

6. DRAIN 1

Note: Please refer to datasheet for

style callout. If style type is not called

out in the datasheet refer to the device

datasheet pinout or pin assignment.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

98ASB42985B

DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

SC−88/SC70−6/SOT−363

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

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ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

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