ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 12-Bit, 1-GSPS Analog-to-Digital Converter Check for Samples: ADS5400-SP FEATURES * 1 * * * * * * * * * * * 1-GSPS Sample Rate 12-Bit Resolution 2.1 GHz Input Bandwidth SFDR = 65 dBc at 1.2 GHz SNR = 57 dBFS at 1.2 GHZ 7 Clock Cycle Latency Interleave Friendly: Internal Adjustments for Gain, Phase and Offset 1.5 - 2 VPP Differential Input Voltage, Programmable LVDS-Compatible Outputs, 1 or 2 Bus Options Total Power Dissipation: 2.2 W On-Chip Analog Buffer 100-Pin Ceramic Nonconductive Tie-Bar Package Military Temperature Range (-55C to 125C Tcase) Processed Per Internal QML Class V Assembly/Test Flow QML Class V Qualified, SMD 5962-09240 * * * APPLICATIONS * * * * * * Test and Measurement Instrumentation Ultra-Wide Band Software-Defined Radio Data Acquisition Power Amplifier Linearization Signal Intelligence and Jamming Radar DESCRIPTION The ADS5400 is a 12-bit, 1-GSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply, while providing LVDS-compatible digital outputs. The analog input buffer isolates the internal switching of the track and hold from disturbing the signal source. The simple 3-stage pipeline provides extremely low latency for time critical applications. Designed for the conversion of signals up to 2 GHz of input frequency at 1 GSPS, the ADS5400 has outstanding low noise performance and spurious-free dynamic range over a large input frequency range. The ADS5400 is available in a 100-Pin Ceramic Nonconductive Tie-Bar Package. The combination of the ceramic package and moderate power consumption of the ADS5400 allows for operation without an external heatsink. The ADS5400 is built on Texas Instrument's complementary bipolar process (BiCom3) and is specified over the full military temperature range (-55C to 125C Tcase). BLOCK DIAGRAM ADS5400 CLKINP RESETP (SYNCINP) RESETN (SYNCINN) CLOCK DIVIDE CLKINN INP 12 BUFFER CLKOUTAP 12-bit ADC (3 stage pipeline) CLKOUTAN INN 12 BUS A OUTA [0-11]P OUTA[0-11]N VCM VREF SCLK SDIO SDO SDENB OVRAP (SYNCOUTAP ) REFERENCE GAIN ADJUST OVER RANGE DETECTOR, SYNC and DEMUX OVRAN (SYNCOUTAN) CLKOUTBP CLKOUTBN PHASE ADJUST CONTROL ENEXTREF ENPWD ENA1BUS 12 BUS B OFFSET ADJUST OUTB[0-11]P OUTB[0-11]N OVRBP (SYNCOUTBP) TEMP SENSOR OVRBN (SYNCOUTBN) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2012, Texas Instruments Incorporated ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. PACKAGE/ORDERING INFORMATION (1) PACKAGE (2) TEMPERATURE ORDERABLE PART NUMBER TOP-SIDE MARKING ADS5400MHFSV 5962-0924001VXC ADS5400MHFS-V -55C to 125C Tcase 5962-0924001VXC CFP-HFS 25C (1) (2) (3) ADS5400HFSMPR ADS5400HFS/EM (3) EVAL ONLY For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, standard packaging quanities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are tested to a temperature rating of 25C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of -55C to 125C or operating life. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage VALUE UNIT AVDD5 to GND 6 V AVDD3 to GND 5 V DVDD3 to GND 5 V 0.5 to 4.5 V -0.3 to (AVDD5 + 0.3) V continuous AC signal 1.25 to 3.75 V continuous DC signal 1.75 to 3.25 V voltage difference between pin and ground 0.5 to 4.5 V voltage difference between pins, common mode at AVDD5/2 continuous AC signal 1.1 to 3.9 V continuous DC signal 2 to 3 V AINP, AINN to GND (2) AINP to AINN voltage difference between pin and ground voltage difference between pins, common mode at AVDD5/2 (2) CLKINP, CLKINN to GND CLKINP to CLKINN (2) (2) RESETP, RESETN to GND RESETP to RESETN (2) Data/OVR Outputs to GND voltage difference between pin and ground voltage difference between pins (2) short duration -0.3 to (AVDD5 + 0.3) V continuous AC signal 1.1 to 3.9 V continuous DC signal 2 to 3 V (2) SDENB, SDIO, SCLK to GND (2) -0.3 to (DVDD3 + 0.3) voltage difference between pin and ground ENA1BUS, ENPWD, ENEXTREF to GND (2) -0.3 to (AVDD3 + 0.3) V -0.3 to (AVDD5 + 0.3) Operating case temperature range -55 to 125 C Maximum junction temperature, TJ 150 C Storage temperature range ESD, human-body model (HBM) (1) (2) -65 to 150 C 2 kV Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime is available upon request. Valid when supplies are within recommended operating range. 2 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 THERMAL CHARACTERISTICS (1) PARAMETER TEST CONDITIONS RJA RJC (1) (2) (3) JESD51-2 and JESD51-3 (2) MIL-STD-883 Test Method 1012 (3) TYP UNIT 21.81 C/W 0.849 C/W This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly underneath the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI typically recommends an 11,9 mm2 board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad must be electrically at ground potential. RJA is the thermal resistance from the junction to ambient. RJC is the thermal resistance from the junction to case. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT Analog supply voltage, AVDD5 4.75 5 5.25 V Analog supply voltage, AVDD3 3.135 3.3 3.465 V Digital supply voltage, DVDD3 3.135 3.3 3.465 V SUPPLIES ANALOG INPUT Full-scale differential input range VCM 1.52 Input common mode 2 AVDD5/2 Vpp V DIGITAL OUTPUT Differential output load 5 pF CLOCK INPUT CLK input sample rate (sine wave) 100 1000 Clock amplitude, differential 0.6 1.5 Clock duty cycle TC 45% Operating case temperature -55 50% MSPS Vpp 55% 125 C 3 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS Typical values at TA = 25C, minimum and maximum values over full temperature range TC,MIN = -55C to TC,MAX = 125C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1-dBFS differential input, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT ANALOG INPUTS Full-scale differential input range Programmable VCM Common-mode input Self-biased to AVDD5 / 2 RIN Input resistance, differential (dc) CIN Input capacitance CMRR Common-mode rejection ratio 1.52 2 VPP AVDD5/2 V 100 Estimated to ground from each AIN pin, excluding soldered package 4.3 pF Common mode signal = 125 MHz 40 dB INTERNAL REFERENCE VOLTAGE VREF Reference voltage 1.98 2 2.02 V DYNAMIC ACCURACY Resolution No missing codes 12 DNL Differential linearity error fIN = 125 MHz -1 0.4 2.5 LSB INL Integral non- linearity error fIN = 125 MHz -4.5 1.5 4.5 LSB Offset error default is trimmed near 0mV -2.5 0 2.5 Offset temperature coefficient Bits 0.02 Gain error 5 Gain temperature coefficient mV mV/C %FS 0.03 %FS/C POWER SUPPLY (1) I(AVDD5) I(AVDD3) I(DVDD3) 5-V analog supply current (Bus A and B active) 220 245 mA 5-V analog supply current (Bus A active) 225 255 mA 3.3-V analog supply current (Bus A and B active) 205 234 mA 226 242 mA 136 154 mA 3.3-V digital supply current (Bus A active) 72 85 Total power dissipation (BUS A and B active) 2.2 2.5 W Total power dissipation (Bus A active) 2 2.3 W 13 50 mW 3.3-V analog supply current (Bus A active) 3.3-V digital supply current (Bus A and B active) Total power dissipation fIN = 125 MHz, fS = 1 GSPS ENPWD = logic High (sleep enabled) Wake-up time from sleep PSRR Power-supply rejection ratio 1MHz injected to each supply, measured without external decoupling mA 1.8 ms 50 dB DYNAMIC AC CHARACTERISTICS SNR (1) Signal-to-noise ratio fIN = 125 MHz 54 58.5 fIN = 600 MHz 53.5 58.3 fIN = 850 MHz 53 58 fIN = 1200 MHz 57.6 fIN = 1700 MHz 55.7 dBFS All power values assume LVDS output current is set to 3.5mA. 4 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS (continued) Typical values at TA = 25C, minimum and maximum values over full temperature range TC,MIN = -55C to TC,MAX = 125C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1-dBFS differential input, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER SFDR HD2 Spurious-free dynamic range Second harmonic MIN TYP fIN = 125 MHz TEST CONDITIONS/NOTES 62 72 fIN = 600 MHz 60 70 fIN = 850 MHz 56 62.7 fIN = 1200 MHz 65.7 fIN = 1700 MHz 56 fIN = 125 MHz 62 fIN = 600 MHz 60 75 fIN = 850 MHz 56 62.5 fIN = 1200 MHz Third harmonic SINAD Total Harmonic Distortion Signal-to-noise and distortion Two-tone SFDR ENOB Effective number of bits (using SINAD in dBFS) RMS idle-channel noise 78 fIN = 600 MHz 60 72 fIN = 850 MHz 56 75 fIN = 1200 MHz 70 fIN = 1700 MHz 63 fIN = 125 MHz 62 80 fIN = 600 MHz 60 79 56 79 dBc dBc 66 64 fIN = 125 MHz 60 71.7 fIN = 600 MHz 58 67 fIN = 850 MHz 55 66.5 fIN = 1200 MHz 63.8 fIN = 1700 MHz 55.7 fIN = 125 MHz 53 57 fIN = 600 MHz 52.4 56.8 fIN = 850 MHz 50.8 55.8 fIN = 1200 MHz 56.6 fIN = 1700 MHz 52.7 fIN1 = 247.5 MHz, fIN2 = 252.5 MHz, each tone at -7 dBFS 74.6 fIN1 = 247.5 MHz, fIN2 = 252.5 MHz, each tone at -11 dBFS 77.9 fIN1 = 1197.5 MHz, fIN2 = 1202.5 MHz, each tone at -7 dBFS 68.3 fIN1 = 1197.5 MHz, fIN2 = 1202.5 MHz, each tone at -11 dBFS 73.7 dBc dBFS dBFS fIN = 125 MHz 8.52 9.55 fIN = 600 MHz 8.42 9.29 fIN = 850 MHz 8.16 9.23 Inputs tied to common-mode dBc 56 62 fIN = 1700 MHz THD dBc 78 fIN = 125 MHz Worst harmonic/spur (other than HD2 fIN = 850 MHz and HD3) fIN = 1200 MHz UNIT 66 fIN = 1700 MHz HD3 MAX Bits 1.41 LSB rms 60.2 dBFS 5 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com SWITCHING CHARACTERISTICS Typical values at TA = 25C, Min and Max values over full temperature range TC,MIN = -55C to TC,MAX = 125C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT 247 350 454 mV 1.125 1.25 1.375 175 350 0.1 1.25 LVDS DIGITAL OUTPUTS (DATA, OVR/SYNCOUT, CLKOUT) VOD Differential output voltage () VOC Common mode output voltage Terminated 100 differential V LVDS DIGITAL INPUTS (RESET) VID Differential input voltage () VIC Common mode input voltage RIN Input resistance CIN Input capacitance Each input pin Each pin to ground mV 2.4 V 100 3.7 pF DIGITAL INPUTS (SCLK, SDIO, SDENB) VIH High level input voltage 2 AVDD3 + 0.3 VIL Low level input voltage 0 0.8 IIH High level input current IIL CIN V V 1 A Low level input current 1 A Input capacitance 2.9 pF DIGITAL INPUTS ( ENEXTREF, ENPWD, ENA1BUS) VIH High level input voltage 2 AVDD5 + 0.3 VIL Low level input voltage 0 0.8 IIH High level input current IIL Low level input current CIN Input capacitance ~40k internal pull-down V V 125 A 20 A 2.9 pF DIGITAL OUTPUTS (SDIO, SDO) VOH High level output voltage IOH = 250 A VOL Low level output voltage IOL = 250 A 2.8 V 0.4 V 190 CLOCK INPUTS RIN Differential input resistance CLKINP, CLKINN Input capacitance Estimated to ground from each CLKIN pin, excluding soldered packaged CIN 100 130 4.8 pF TIMING CHARACTERISTICS (1) Typical values at TA = 25C, Min and Max values over full temperature range TC,MIN = -55C to TC,MAX = 125C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER ta TEST CONDITIONS/NOTES MIN Aperture delay Aperture jitter, rms Uncertainty of sample point due to internal jitter sources Bus A, using Single Bus Mode Latency (1) TYP MAX UNIT 250 ps 125 fs 7 Bus A, using Dual Bus Mode Aligned 7.5 Bus B, using Dual Bus Mode Aligned 8.5 Bus A and B, using Dual Bus Mode Staggered 7.5 Cycles Timing parameters are specified by design or characterization, but not production tested. 6 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 TIMING CHARACTERISTICS(1) (continued) Typical values at TA = 25C, Min and Max values over full temperature range TC,MIN = -55C to TC,MAX = 125C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT LVDS OUTPUT TIMING (DATA, CLKOUT, OVR/SYNCOUT) (2) tCLK Clock period tCLKH Clock pulse duration, high Assuming worst case 45/55 duty cycle 0.45 tCLKL Clock pulse duration, low Assuming worst case 55/45 duty cycle 0.45 tPD-CLKDIV2 Clock propagation delay CLKIN rising to CLKOUT rising in divide by 2 mode 1200 tPD-CLKDIV4 Clock propagation delay CLKIN rising to CLKOUT rising in divide by 4 mode 1200 tPD-ADATA Bus A data propagation delay tPD-BDATA Bus B data propagation delay 1 10 ns ns ns ps ps 1400 ps 1400 ps CLKIN falling to Data Output transition Setup time, single bus mode Data valid to CLKOUT edge, 50% CLKIN duty cycle 290 (tCLK/2) - 185 ps tH-SBM Hold time, single bus mode CLKOUT edge to Data invalid, 50% CLKIN duty cycle 410 (tCLK/2) - 65 ps tSU-DBM Setup time, dual bus mode Data valid to CLKOUT edge, 50% CLKIN duty cycle 550 tCLK - 425 ps tH-DBM Hold time, dual bus mode CLKOUT edge to Data invalid, 50% CLKIN duty cycle 1150 tCLK + 175 ps tr LVDS output rise time tf LVDS output fall time tSU-SBM (3) Measured 20% to 80% 400 ps 400 ps LVDS INPUT TIMING (RESETIN) tRSU RESET setup time RESETP going HIGH to CLKINP going LOW 325 tRH RESET hold time CLKINP going LOW to RESETP going LOW 325 RESET input capacitance Differential RESET input current ps ps 1 pF 1 A SERIAL INTERFACE TIMING tS-SDENB Setup time, serial enable SDENB falling to SCLK rising 20 ns tH-SDENB Hold time, serial enable SCLK falling to SENDB rising 25 ns tS-SDIO Setup time, SDIO SDIO valid to SCLK rising 10 ns tH-SDIO Hold time, SDIO SCLK rising to SDIO transition 10 fSCLK Frequency tSCLK SCLK period 100 ns tSCLKH Minimum SCLK high time 40 ns tSCLKL Minimum SCLK low time 40 tr Rise time 10pF 10 ns tf Fall time 10pF 10 ns Data output delay Data output (SDO/SDIO) delay after SCLK falling, 10pF load tDDATA (2) (3) ns 10 75 MHz ns ns LVDS output timing measured with a differential 100 load placed ~4 inches from the ADS5400. Measured differential load capacitance is 3.5pF. Measurement probes and other parasitics add ~1pF. Total approximate capacitive load is 4.5pF differential. All timing parameters are relative to the device pins, with the loading as stated. In single bus mode at 1GSPS (1ns clock), the minimum output setup/hold times over process and temperature provide a minimum 700ps of data valid window, with 300ps of uncertainity. 7 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com INTERLEAVING ADJUSTMENTS Typical values at TA = 25C, Min and Max values over full temperature range TMIN = -55C to TMAX = 125C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET ADJUSTMENTS Resolution LSB magnitude DNL Differential linearity error INL Integral Non-Linearity error Recommended Min Offset Setting Recommended Max Offset Setting 9 at full scale range of 2VPP Bits 120 V -2.5 2.5 LSB -3 3 LSB from default offset value, to maintain AC performance -8 mV 8 mV GAIN ADJUSTMENTS Resolution 12 LSB magnitude Bits 120 V DNL Differential linearity error -4 -1.2, +0.5 4 LSB INL Integral Non-Linearity error -8 -2, +1 8 LSB Min Gain Setting 1.52 VPP Max Gain Setting 2 VPP INPUT CLOCK FINE PHASE ADJUSTMENT Resolution 6 LSB magnitude DNL Differential linearity error INL Integral Non-Linearity error Bits 116 -2 -2.5 Max Fine Clock Skew setting fs 2.5 LSB 4 LSB 7.4 ps INPUT CLOCK COARSE PHASE ADJUSTMENT Resolution 5 LSB magnitude Bits 2.4 ps DNL Differential linearity error -1 1 LSB INL Integral Non-Linearity error -1 5 LSB Max Coarse Clock Skew setting 73 8 ps Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Timing Diagrams DIFFERENTIAL ANALOG INPUT (INP-INN) N Aperture delay N+1 ta N+2 Sample N and RESET pulse captured here N output tCLKH N+1 output tCLKL CLKINP tRSU RESETP tRH CLKOUT is reset after 3.5 CLKIN cycles (+ tPD-CLKDIV2 ) tPD-CLKDIV2 Phase 0: CLKOUT in desired CLKOUTAP state after power up Phase 1: misaligned by 1 clock after power up tPD-ADATA tsu Latency of N and SYNCOUTA are matched to 7 CLKIN cycles N-1 DATA BUS A SYNCOUTA (OVRA pins) If SYNC mode is enabled, the OVRA pins become SYNCOUTA pins th N N+1 N+2 Sync Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTA transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit. Bus B is not active in single bus mode. Figure 1. Single Bus Mode 9 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com Timing Diagrams (continued) Sample N and RESET pulse captured here N, N+1 output N+1 CLKINP tRSU RESETP tRH CLKOUT is reset after 3.5 CLKIN cycles (+ tPD-CLKDIV2 ) tPD-CLKDIV2 CLKOUTAP CLKOUTBP Phase 0: CLKOUT in desired state after power up Phase 1: misaligned by 1 clock after power up tPD-BDATA tsu Latency of N and SYNCOUTB are matched to 8.5 CLKIN cycles DATA BUS B The phase of data shown prior to reset matches CLKOUT in phase 0 SYNCOUTB (OVRB pins) If SYNC mode is enabled, the OVRB pins become SYNCOUTB pins DATA BUS A The phase of data shown prior to reset matches CLKOUT in phase 0 Latency of N+1 is 7.5 CLKIN cycles th N N+2 Sync N+1 N+3 tPD-ADATA Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit. Figure 2. Dual Bus Mode - Aligned, CLKOUT Divide By 2 10 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Timing Diagrams (continued) Sample N and RESET pulse captured here N output N+1 N+1 output CLKINP tRSU tRH CLKOUT is reset after 3.5 CLKIN cycles (+ tPD-CLKDIV2 ) RESETP tPD-CLKDIV2 Phase 0: CLKOUT in desired state after power up CLKOUTAP Phase 1: misaligned by 1 clock after power up Phase 0: CLKOUT in desired state after power up CLKOUTBP Phase 1: misaligned by 1 clock after power up tPD-BDATA tsu Latency of N and SYNCOUTB are matched to 7.5 CLKIN cycles DATA BUS B The phase of data shown prior to reset matches CLKOUT in phase 0 If SYNC mode is enabled, the OVRB pins become SYNCOUTB pins SYNCOUTB (OVRB pins) DATA BUS A The phase of data shown prior to reset matches CLKOUT in phase 0 Latency of N+1 is 7.5 CLKIN cycles th N N+2 Sync N+1 N+3 tPD-ADATA Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit. Figure 3. Dual Bus Mode - Staggered, CLKOUT Divide By 2 11 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com Timing Diagrams (continued) Sample N and RESET pulse captured here N, N+1 output N+1 CLKINP tRSU RESETP tRH tPD-CLKDIV4 CLKOUT is reset after 7.5 CLKIN cycles (+ tPD-CLKDIV4 ) Phase 0: CLKOUT in desired state after power up CLKOUTAP CLKOUTBP Phase 1: misaligned by 1 clock after power up Phase 2: misaligned by 2 clocks after power up Phase 3: misaligned by 3 clocks after power up tPD-BDATA Latency of N and SYNCOUTB are matched to 8.5 CLKIN cycles tsu th DATA BUS B SYNCOUTB (OVRB pins) DATA BUS A The phase of data shown prior to reset matches CLKOUT in phase 0 If SYNC mode is enabled, the OVRB pins become SYNCOUTB pins The phase of data shown prior to reset matches CLKOUT in phase 0 Latency of N+1 is 7.5 CLKIN cycles N Sync N+1 tPD-ADATA Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit. Figure 4. Dual Bus Mode - Aligned, CLKOUT Divide By 4 12 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Timing Diagrams (continued) Sample N and RESET pulse captured here N output N+1 sampled N+1 output CLKINP tRSU tRH CLKOUTA is reset after 7.5 CLKIN cycles (+ tPD-CLKDIV4 ) RESETP tPD-CLKDIV4 Phase 0: CLKOUT in desired state after power up Phase 1: misaligned by 1 clock after power up CLKOUTAP Phase 2: misaligned by 2 clocks after power up Phase 3: misaligned by 3 clocks after power up CLKOUTB is reset after 6.5 CLKIN cycles (+ tPD-CLKDIV4 ) tPD-CLKDIV4 Phase 0: CLKOUT in desired state after power up Phase 1: misaligned by 1 clock after power up CLKOUTBP Phase 2: misaligned by 2 clocks after power up Phase 3: misaligned by 3 clocks after power up tPD-BDATA Latency of N and SYNCOUTB are matched to 7.5 CLKIN cycles DATA BUS B The phase of data shown prior to reset matches CLKOUTB in phase 0 If SYNC mode is enabled, the OVRB pins become SYNCOUTB pins SYNCOUTB (OVRB pins) DATA BUS A The phase of data shown prior to reset matches CLKOUTA in phase 0 Latency of N+1 is 7.5 CLKIN cycles tsu th N+2 N Sync N+1 tPD-ADATA Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit. Figure 5. Dual Bus Mode - Staggered, CLKOUT Divide By 4 13 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com 1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 ADS5400 (TOP VIEW) 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 54 22 23 53 Thermal Pad = AGND 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 DA11P DA11N DA10P DA10N DA9P DA9N DA8P DA8N DA7P DA7N DGND DVDD3 DA6P DA6N CLKOUTAP CLKOUTAN DA5P DA5N DA4P DA4N DA3P DA3N DA2P DA2N DGND CLKOUTBN CLKOUTBP DB5N DB5P DB4N DB4P DB3N DB3P DB2N DB2P DB1N DB1P DVDD3 DGND DB0N DB0P OVRBN OVRBP OVRAN OVRAP DA0N DA0P DA1N DA1P DVDD3 29 51 28 52 25 27 24 26 AVDD5 AVDD3 AGND CLKINP CLKINN AGND AVDD3 AGND AVDD3 RESETN RESETP DB11N DB11P DB10N DB10P DB9N DB9P DB8N DB8P DB7N DB7P DB6N DB6P DVDD3 DGND 100 AGND AVDD5 AGND AVDD5 AGND AINN AINP AGND AVDD5 AGND AVDD5 VCM AGND VREF AVDD5 AVDD3 AGND ENEXTREF ENPWD ENA1BUS SDO SDIO SCLK SDENB AVDD5 PIN CONFIGURATION 14 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Table 2. PIN FUNCTIONS PIN NAME AINP, AINN NO. 94, 95 AVDD5 1, 76, 86, 90, 92, 97, 99 AVDD3 2, 7, 9, 85 DESCRIPTION Analog differential input signal (positive, negative). Includes 100- differential load on-chip. Analog power supply (5 V) Analog power supply (3.3 V) DVDD3 24, 38, 50, 64 AGND 3, 6, 8, 84, 88, 91, 93, 96, 98, 100 Analog Ground DGND 25, 39, 51, 65 Digital Ground CLKINP, CLKINN DA0N, DA0P 4, 5 46, 47 Output driver power supply (3.3 V) Differential input clock (positive, negative). Includes 160- differential load on-chip. Bus A, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output) DA1N-DA10N, 48-49, 52-59, 62-63, Bus A, LVDS digital output pairs (bits 1- 10) DA1P-DA10P 66-73 DA11N, DA11P 74, 75 Bus A, LVDS digital output pair, most-significant bit (MSB) CLKOUTAN, CLKOUTAP 60, 61 Bus A, Clock Output (Data ready), LVDS output pair DB0N, DB0P 40, 41 Bus B, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output) DB1N-DB10N, DB1P-DB10P 14-23, 28-37 Bus B, LVDS digital output pairs (bits 1- 10) DB11N, DB11P 12, 13 Bus B, LVDS digital output pair, most-significant bit (MSB) CLKOUTBN, CLKOUTBP 26, 27 Bus B, Clock Output (Data ready), LVDS output pair OVRAN, OVRAP 44, 45 Bus A, Overrange indicator LVDS output. A logic high signals an analog input in excess of the fullscale range. Becomes SYNCOUTA when SYNC mode is enabled in register 0x05. OVRBN, OVRBP 42, 43 Bus B, Overrange indicator LVDS output. A logic high signals an analog input in excess of the fullscale range. Becomes SYNCOUTB when SYNC mode is enabled in register 0x05. 10, 11 Digital Reset Input, LVDS input pair. Inactive if logic low. When clocked in a high state, this is used for resetting the polarity of CLKOUT signal pair(s). If SYNC mode is enabled in register 0x05, this input also provides a SYNC time-stamp with the data sample present when RESET is clocked by the ADC, as well as CLKOUT polarity reset. Includes 100- differential load on-chip. RESETN, RESETP SCLK 78 Serial interface clock. SDIO 79 Bi-directional serial interface data in 3-pin mode (default) for programming/reading internal registers. In 4-pin interface mode (reg 0x01), the SDIO pin is an input only. SDO 80 Uni-directional serial interface data in 4-pin mode (reg 0x01) provides internal register settings. The SDO pin is in high-impedance state in 3-pin interface mode (default). SDENB 77 Active low serial data enable, always an input. Use to enable the serial interface. Internal 100k pull-up resistor. VREF 87 Reference voltage input (2V nominal). A 0.1F capacitor to AGND is recommended, but not required. ENA1BUS 81 (1) Enable single output bus mode (2-bus mode is default), active high. This pin is logic OR'd with addr 0x02h bit<0>. ENPWD 82 (1) Enable Powerdown, active high. Places the converter into power-saving sleep mode when high. This pin is logic OR'd with addr 0x05h bit<6>. ENEXTREF 83 (1) Enable External Reference Mode, active high. Device uses an external voltage reference when high. This pin is logic OR'd with addr 0x05h bit<2>. 89 Analog input common mode voltage, Output (for DC-coupled applications, nominally 2.5V). A 0.1F capacitor to AGND is recommended, but not required. VCM (1) This pin contains an internal ~40k pull-down resistor, to ground. 15 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com SERIAL INTERFACE The serial port of the ADS5400 is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of ADS5400. It is compatible with most synchronous transfer formats and can be configured as a 3 or 4 pin interface in register 0x01h. In both configurations, SCLK is the serial interface input clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes, depending on the data length to be transferred (1-4 bytes). The first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to transfer the data. Table 3 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle. Table 3. Instruction Byte of the Serial Interface MSB Bit Description R/W [N1:N0] 7 R/W LSB 6 N1 5 N0 4 A4 3 A3 2 A2 1 A1 0 A0 Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from ADS5400 and a low indicates a write operation to the ADS5400. Identifies the number of data bytes to be transferred per Table 4 below. Data is transferred MSB first. Table 4. Number of Transferred Bytes Within One Communication Frame [A4:A0] N1 N0 Description 0 0 Transfer 1 Byte 0 1 Transfer 2 Bytes 1 0 Transfer 3 Bytes 1 1 Transfer 4 Bytes Identifies the address of the register to be accessed during the read or write operation. For multibyte transfers, this address is the starting address. Note that the address is written to the ADS5400 MSB first and counts down for each byte. Figure 6 shows the serial interface timing diagram for a ADS5400 write operation. SCLK is the serial interface clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in. Input data to ADS5400 is clocked on the rising edges of SCLK. 16 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Instruction Cycle Data Transfer Cycle (s) SDENB SCLK SDIO r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 tS (SDENB) D5 D4 D3 D2 D1 D0 tSCLK SDENB SCLK SDIO tSCLKL th (SDIO) tSCLKH tS (SDIO) Figure 6. Serial Interface Write Timing Diagram Figure 7 shows the serial interface timing diagram for a ADS5400 read operation. SCLK is the serial interface clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO is data out from ADS5400 during the data transfer cycle(s), while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from ADS5400 during the data transfer cycle(s). At the end of the data transfer, SDO will output low on the final falling edge of SCLK until the rising edge of SDENB when it will 3-state. Instruction Cycle Data Transfer Cycle(s) SDENB SCLK SDIO r/w N1 N0 - A3 A2 A1 SDO A0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 3 pin Configuration Output 4 pin Configuration Output SDENB SCLK SDIO SDO Data n Data n-1 td (Data) Figure 7. Serial Interface Read Timing Diagram 17 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com Serial Register Map Table 5 gives a summary of all the modes that can be programmed through the serial interface. Table 5. Summary of Functions Supported by Serial Interface REGISTER ADDRESS IN HEX Address REGISTER FUNCTIONS BIT 7 BIT 6 BIT 5 00 01 BIT 1 BIT 0 SPI Reset 0 0 0 Clock Divider Single or Dual Bus 0 Analog Offset bit<8> Stagger Output 0 Fine Clock Phase Adjustment bits<5:0> 04 continued...Analog Offset Control bits<7:0> Temp Sensor Powerdown Data output mode 1 Sync Mode Data Format LVDS termination Reference LVDS current 07 0000 0000 08 Die temperature bits<7:0> 09 BIT 2 Coarse Clock Phase Adjustment bits<4:0> 03 06 BIT 3 3 or 4-pin SPI continued...Analog Gain Adjustment bits<3:0> 02 05 BIT 4 Analog Gain Adjustment bits<11:4> 000 0000 Memory error 0A 0000 0000 0B-16 addresses not implemented, writes have no effect, reads return 0x00 17 DIE ID<7:0> 18 DIE ID<15:8> 19 DIE ID<23:16> 1A DIE ID<31:24> 1B DIE ID<39:32> 1C DIE ID<47:40> 1D DIE ID<55:48> 1E DIE ID<63:56> 1F Die revision indicator<7:0> 18 Force LVDS outputs Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Description of Serial Registers Each register function is explained in detail below. Table 6. Serial Register 0x00 (Read or Write) Address (hex) BIT 7 BIT 6 BIT 5 0x00 Defaults BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 Analog Gain Adjustment bits<11:4> 0 BIT <7:0> 0 0 0 0 Analog gain adjustment (most significant 8 bits of a 12 bit word) All 12-bits in this adjustment in address 0x00 and 0x01 set to 0000 0000 0000 = fullscale analog input 2.0VPP All 12-bits in this adjustment in address 0x00 and 0x01 set to 1111 1111 1111 = fullscale analog input 1.52VPP Step adjustment resolution is 120V. Can be used for one-time setting or continual calibration of analog signal path gain. Table 7. Serial Register 0x01 (Read or Write) Address (hex) BIT 7 0x01 Defaults BIT 6 BIT 5 BIT 4 Analog Gain Adjustment bits<3:0> 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 3 or 4-pin SPI SPI Reset 0 0 0 0 0 0 BIT <0:1> RESERVED 0 set to 0 if writing this register 1 do not set to 1 BIT <2> SPI Register Reset 0 altered register settings are kept 1 resets all SPI registers to defaults (self clearing) BIT <3> Set SPI mode to 3- or 4-pin 0 3-pin SPI (read/write on SDIO, SDO not used) 1 4-pin SPI (SDIO is write, SDO is read) BIT <7:4> Analog gain adjustment continued (least significant 4 bits of a 12bit word) All 12-bits in this adjustment in address 0x00 and 0x01 set to 0000 0000 0000 = fullscale analog input 2VPP All 12-bits in this adjustment in address 0x00 and 0x01 set to 1111 1111 1111 = fullscale analog input 1.52VPP Step adjustment resolution is 120V. Can be used for one-time setting or continual calibration of analog signal path gain. 19 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com Table 8. Serial Register 0x02 (Read or Write) Address (hex) BIT 7 0x02 Defaults BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Coarse Clock Phase Adjustment bits<4:0> 0 0 0 0 0 BIT 1 BIT 0 0 Clock Divider Single or Dual Bus 0 0 0 BIT <0> Single or Dual Bus Output Selection 0 dual bus output (A and B) 1 single bus output (A) BIT <1> Output Clock Divider 0 CLKOUT equals CLKIN divide by 4 (not available in single bus mode) 1 CLKOUT equals CLKIN divide by 2 BIT <2> RESERVED 0 set to 0 if writing this register 1 do not set to 1 BIT <7:3> Input Clock Coarse Phase Adjustment Use as a coarse adjustment of input clock phase. The 5-bit adjustment provides a step size of ~2.4ps across a range from code 00000 = 0 ps to code 11111 = 73ps. Table 9. Serial Register 0x03 (Read or Write) Address (hex) BIT 7 BIT 6 0x03 Defaults BIT <0> BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 Analog Offset bit<8> 0 factory set Fine Clock Phase Adjustment bits<5:0> 0 0 0 0 0 0 Analog Offset control (most significant bit of 9-bit word) All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000 0000 = -30mV (TBD) All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111 1111 = +30mV (TBD) Step adjustment resolution is 120V (or 1/4 LSB). Adjustments can be used for calibration of analog signal path offset (for instance offset error induced outside of the ADC) or to match multiple ADC offsets. The default setting for this register is factory set to provide ~0mV of ADC offset in the output codes and is unique for each device. BIT <1> RESERVED 0 set to 0 if writing this register 1 do not set to 1 BIT <7:2> Fine Clock Phase Adjustment Use as a fine adjustment of the input clock phase. The 6-bit adjustment provides a step resolution of ~116fs across a range from code 000000 = 0ps to code 111111 = 7.4ps. Can be used in conjuction with Coarse Clock Phase Adjustment in address 0x02. 20 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Table 10. Serial Register 0x04 (Read or Write) Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 0x04 Analog Offset Control bits<7:0> Defaults factory set BIT <7:0> BIT 2 BIT 1 BIT 0 Analog Offset control continued (least significant bits of 9-bit word) All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000 0000 = -30mV (TBD) All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111 1111 = +30mV (TBD) Step adjustment resolution is 120uV (or 1/4 LSB). Adjustments can be used for calibration of analog signal path offset (for instance offset error induced outside of the ADC) or to match multiple ADC offsets. The default setting for this register is factory set to provide ~0mV of ADC offset in the output codes and is unique for each device. Performance of the ADC is not specified across the entire offset control range. Some performance degradation is expected as larger offsets are programmed. Table 11. Serial Register 0x05 (Read or Write) Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0x05 Temp Sensor Powerdown reserved Sync Mode Data Format Reference Stagger Output Defaults 0 0 1 0 0 0 0 BIT <0> RESERVED 0 set to 0 if writing this register 1 do not set to 1 BIT <1> Stagger Output Bus 0 Output bus A and B aligned 1 Output bus A and B staggered (see timing diagrams) BIT <2> Enable External Reference 0 Enable internal reference 1 Enable external reference BIT <3> Set Data Output Format 0 Enable offset binary 1 Enable two's complement BIT <4> Set Sync Mode 0 Disable data synchronization mode 1 Enable data synchronization mode When enabled, the OVR pin(s) are replaced with SYNC output signal(s). The SYNC output signal is time-aligned with the output data matching the corresponding input sample and RESET input pulse 21 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 BIT <5> www.ti.com RESERVED 0 1 set to 1 if writing this register BIT <6> Powerdown 0 device active 1 device in low power mode (sleep mode) BIT <7> Temperature Sensor 0 temperature sensor inactive 1 temperature sensor active, independent of powerdown bit in Bit<6>, allows reading of temp sensor while the rest of the ADC is in sleep mode Table 12. Serial Register 0x06 (Read or Write) Address (hex) 0x06 Defaults BIT 7 BIT 6 Data output mode 0 0 BIT 5 BIT 4 BIT 3 LVDS termination 0 0 BIT 2 LVDS current 0 BIT 0 Force LVDS outputs 1 BIT <0:1> Force LVDS outputs 00 and 01 normal operating mode (LVDS is outputting sampled data bits) 10 forces the LVDS outputs to all logic zeros (data and clock out) - for level check 11 forces the LVDS outputs to all logic ones (data and clock out) - for level check BIT <3:2> Set LVDS output current 00 2.5mA 01 3.5mA (default) 10 4.5mA 11 5.5mA BIT <5:4> Set Internal LVDS termination differential resistor (for LVDS outputs only) 00 and 01 no internal termination 10 internal 200 resistor selected 11 internal 100 resistor selected BIT <7:6> Control Data Output Mode 00 normal mode (LVDS is outputting sampled data bits) 01 scrambled output mode (D11:D1 is XOR'd with D0) 10 output data is replaced with PRBS test pattern (7-bit sequence) 11 output data is replaced with toggling test pattern (all 1s, then all 0s, then all 1s, etc.....on all bits) 22 BIT 1 0 0 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Table 13. Serial Register 0x08 (Read only) Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 0x08 Die temperature bits<7:0> Defaults depends on reading from temperature sensor BIT <7:0> BIT 1 BIT 0 Die temperature readout if enabled in register 0x05. To obtain the die temperature in Celsius, convert the 8-bit word to decimal and subtract 78. <7:0> = 0x00 = 00000000, measured temperature is 0-78 = -78C <7:0> = 0x73 = 01110011, measured temperature is 115 - 78 = 37C <7:0> = 0xAF, measured temperature is 175 - 78 = 97C Table 14. Serial Register 0x09 (Read only) Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0x09 000 0000 Memory error Defaults 000 0000 0 BIT <7:1> RESERVED set to 0 if writing this register do not set to 1 BIT <0> Memory Error Indicator Registers 0x00 through 0x07 have multiple redundancy. If any copy disagrees with the others, an error is flagged in this bit. This is for systems that require the highest level of assurance that the device remains programmed in the proper state and indication of an error if something changes unexpectedly. Table 15. Serial Register 0x0A (Read only) Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 0x0A 0000 0000 Defaults 0000 0000 BIT <7:0> BIT 2 BIT 1 BIT 0 RESERVED set to 0 if writing this register do not set to 1 23 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com Table 16. Serial Register 0x17 through 0x1E (Read only) Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 0x17 - 0x1E Die ID Defaults factory set BIT <7:0> BIT 2 BIT 1 BIT 0 BIT 1 BIT 0 Die Identification Bits Each of these eight registers contains 8-bits of a 64-bit unique die identifier. Table 17. Serial Register 0x1F (Read only) Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 0x1F Die Revision Number Defaults factory set BIT <7:0> BIT 2 Die revision Provides design revision information. 24 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 TYPICAL CHARACTERISTICS Typical plots at TA = 25C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5-VPP differential clock, (unless otherwise noted) SPECTRAL PERFORMANCE FFT FOR 250-MHz INPUT SIGNAL SPECTRAL PERFORMANCE FFT FOR 0.9-GHz INPUT SIGNAL 0 0 ENOB = 9.52 Bits, SFDR = 71.39 dBc, SINAD = 58.99 dBFS, SNR = 59.40 dBFS, THD = 69.44 dBc -10 -20 -20 -30 Amplitude - dB Amplitude - dB -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 0 50 100 150 200 250 300 350 400 450 500 -100 0 100 150 200 250 300 350 400 450 500 f - Frequency - MHz Figure 8. Figure 9. SPECTRAL PERFORMANCE FFT FOR 1.3-GHz INPUT SIGNAL SPECTRAL PERFORMANCE FFT FOR 1.7-GHz INPUT SIGNAL 0 ENOB = 9.02 Bits, SFDR = 61.36 dBc, SINAD = 55.76 dBFS, SNR = 57.39 dBFS, THD = 60.81 dBc -10 -20 -10 -20 -30 ENOB = 8.59 Bits, SFDR = 57.39 dBc, SINAD = 52.98 dBFS, SNR = 56.02 dBFS, THD = 55.96 dBc -30 Amplitude - dB Amplitude - dB 50 f - Frequency - MHz 0 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 ENOB = 9.23 Bits, SFDR = 66.57 dBc, SINAD = 57.09 dBFS, SNR = 58.46 dBFS, THD = 62.76 dBc -10 0 50 100 150 200 250 300 350 400 450 500 -100 0 50 100 150 200 250 300 350 400 450 500 f - Frequency - MHz f - Frequency - MHz Figure 10. Figure 11. 25 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5-VPP differential clock, (unless otherwise noted) DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY 2 1 AIN = -0.05 dBFS, fIN = 100.33 MHz, fs = 1 GSPS 0.6 AIN = -0.05 dBFS, fIN = 100.33 MHz, fs = 1 GSPS 1.5 INL - Integral Nonlinearity - LSB DNL - Differential Nonlinearity - LSB 0.8 0.4 0.2 0 -0.2 -0.4 -0.6 1 0.5 0 -0.5 -1 -1.5 -0.8 -1 0 512 -2 0 1024 1536 2048 2560 3072 3584 4096 ADC Output Code 512 1024 1536 2048 2560 3072 3584 4096 ADC Output Code Figure 12. Figure 13. AC PERFORMANCE vs INPUT AMPLITUDE (801.13-MHz INPUT SIGNAL) AC PERFORMANCE vs INPUT AMPLITUDE (247.5-MHz AND 252.5-MHz TWO-TONE INPUT SIGNAL) 120 2F2-F1 (dBFS) 2F1-F2 (dBFS) 100 100 SFDR (dBFS) 80 Performance - dB Performance - dB SNR (dBFS) 60 40 SFDR (dBC) SNR (dBC) 20 fIN = 801.13 MHz, fs = 1 GSPS, 16k FFT 0 -20 -90 -80 -70 -60 -50 -40 -30 -20 Input Amplitude - dBFS -10 80 Worst Spur (dBFS) 60 40 Worst Spur (dBc) fs = 1 GSPS, fIN1 = 247.5 MHz, fIN2 = 252.5 MHz 20 0 0 -87 -77 Figure 14. -67 -57 -47 -37 -27 Input Amplitude - dBFS -17 -7 Figure 15. 26 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) AC PERFORMANCE vs INPUT AMPLITUDE (1197.5-MHz AND 1202.5-MHz TWO-TONE INPUT SIGNAL) 120 2F2-F1 (dBFS) 2F1-F2 (dBFS) 100 100 AC Performance - dB AC PERFORMANCE vs INPUT AMPLITUDE (747.5-MHz AND 752.5-MHz TWO-TONE INPUT SIGNAL) 120 2F2-F1 (dBFS) 2F1-F2 (dBFS) 80 Worst Spur (dBFS) 60 40 Worst Spur (dBc) fs = 1 GSPS, fIN1 = 747.5 MHz, fIN2 = 752.5 MHz 20 0 -87 SFDR - Spurious-Free Dynamic Range - dBc 74 -77 -67 -57 -47 -37 -27 Input Amplitude - dBFS -17 40 Worst Spur (dBc) fs = 1 GSPS, fIN1 = 1197.5 MHz, fIN2 = 1202.5 MHz -77 -67 -57 -47 -37 -27 Input Amplitude - dBFS Figure 17. SFDR vs AVDD5 ACROSS TEMPERATURE SNR vs AVDD5 ACROSS TEMPERATURE TA = 85C -17 -7 60 TA = 0C TA = 55C TA = -40C T = -55C A TA = -20C TA = -40C TA = -55C TA = 100C 68 66 fIN = 100.33 MHz, fs = 1 GSPS 4.8 60 0 -87 -7 TA = 25C 64 4.7 Worst Spur (dBFS) Figure 16. 72 70 80 20 SNR - Signal-to-Noise Ratio - dBFS Performance - dB Typical plots at TA = 25C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5-VPP differential clock, (unless otherwise noted) TA = 125C 4.9 5 5.1 5.2 5.3 AVDD - Supply Voltage - V 5.4 5.5 TA = -20C TA = 25C 59.5 59 TA = 55C TA = 85C 58.5 TA = 0C TA = 100C TA = 125C 58 fIN = 100.33 MHz, fs = 1 GSPS 57.5 4.7 4.8 Figure 18. 4.9 5 5.1 5.2 5.3 AVDD - Supply Voltage - V 5.4 5.5 Figure 19. 27 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5-VPP differential clock, (unless otherwise noted) SFDR vs AVDD3 ACROSS TEMPERATURE SNR vs AVDD3 ACROSS TEMPERATURE 61 TA = 100C 73 TA = 85C TA = 55C 71 TA = -20C TA = -40C T = 0C A TA = 25C 69 TA = -55C 67 fIN = 100.33 MHz, fs = 1 GSPS 65 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 3.55 3.6 AVDD - Supply Voltage - V TA = 0C 59 TA = 55C TA = 85C TA = 100C TA = 125C 58 SFDR vs DVDD3 ACROSS TEMPERATURE SNR vs DVDD3 ACROSS TEMPERATURE TA = 25C 60 TA = -40C TA = -20C TA = 85C TA = 100C TA = 125C TA = -55C fIN = 100.33 MHz, fs = 1 GSPS 64 3.1 TA = -55C TA = 0C 68 3 TA = -55C Figure 21. 72 66 TA = -20C 60 Figure 20. TA = 55C 70 TA = 25C TA = -40C 57 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 3.55 3.6 AVDD - Supply Voltage - V SNR - Signal-to-Noise Ratio - dBFS SFDR - Spurious-Free Dynamic Range - dBc 74 fIN = 100.33 MHz, fs = 1 GSPS TA = 125C SNR - Signal-to-Noise Ratio - dBFS SFDR - Spurious-Free Dynamic Range - dBc 75 3.2 3.3 3.4 DVDD - Supply Voltage - V 3.5 3.6 TA = -40C TA = -20C 59.5 59 TA = 55C TA = 0C TA = 85C TA = 100C TA = 25C 58.5 TA = 125C 58 57.5 57 fIN = 100.33 MHz, fs = 1 GSPS 3 Figure 22. 3.1 3.2 3.3 3.4 DVDD - Supply Voltage - V 3.5 3.6 Figure 23. 28 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5-VPP differential clock, (unless otherwise noted) SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY 1000 fS - Sampling Frequency - MHz 900 800 700 600 500 400 300 1900 2100 1900 2100 1700 1500 1300 1200 1100 1000 900 800 750 700 650 600 550 500 450 400 350 300 250 230 170 130 100 50 10 200 fIN - Input Frequency- MHz 50-52 52-54 56-58 54-56 58-60 SNR - dBFS Figure 24. SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY 1000 fS - Sampling Frequency - MHz 900 800 700 600 500 400 300 1700 1500 1300 1200 1100 1000 900 800 750 700 650 600 550 500 450 400 350 300 250 230 170 130 100 50 10 200 fIN - Input Frequency- MHz 50-55 55-60 60-65 65-70 70-75 75-80 SFDR - dBc Figure 25. 29 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5-VPP differential clock, (unless otherwise noted) NORMALIZED GAIN RESPONSE vs INPUT FREQUENCY 3 fs = 1 GSPS, Normalized Gain Response - dB Measurement every 50 MHz 0 -3 -6 -9 -12 10M 100M 1G fIN - Input Frequency - Hz 5G Figure 26. 30 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 APPLICATION INFORMATION Theory of Operation The ADS5400 is a 12-bit, 1-GSPS, monolithic pipeline ADC. Its bipolar transistor analog core operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible digital outputs. The conversion process is initiated by the falling edge of the external input clock. At the sampling instant, the differential input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of 7 - 8.5 clock cycles (output mode dependent), after which the output data is available as a 12-bit parallel word, coded in offset binary or two's complement format. The user can select to accept the data at the full sample rate using one bus (bus A, latency 7 cycles), or demultiplex the data into two buses (bus A and B, latency 7.5 or 8.5 cycles) at half rate. A serial peripheral interface (SPI) is provided for adjusting operational modes, as well as for calibrations of analog gain, analog offset and clock phase for inter-leaving multiple ADS5400. Die temperature readout using the SPI is provided. SYNC and RESET modes exist for synchronizing output data across multiple ADS5400. Input Configuration The analog input for the ADS5400 consists of an analog pseudo-differential buffer followed by a bipolar transistor track-and-hold (see Figure 27). The integrated analog buffer isolates the source driving the input of the ADC from sampling glitches on the T&H and allows for the integration of a 100- differential input resistor. The input common mode is set internally through a 500- resistor connected from half of the AVDD5 supply voltage to each of the inputs. The parasitic package capacitance shown is with the package unsoldered. Once soldered, depending on the board characteristics, one can expect another ~1pF at the analog input pins, which is board dependent. ADS5400 AVDD5 Bipolar Transistor Buffer ~5.25 nH Bond Wire AINP ~0.75 pF Package ~0.2 pF Bondpad 0.3 pF 500 W Analog Inputs AGND AVDD5 ~5.25 nH Bond Wire 112 W 2.5 V 500 W AGND Sample and Hold st 1 Stage Of Pipeline 0.3 pF AINN ~0.75 pF Package ~0.2 pF Bondpad Bipolar Transistor Buffer AGND Figure 27. Analog Input Equivalent Circuit For a full-scale differential input, each of the differential lines of the input signal swing symmetrically between 2.5 V + 0.5 V and 2.5 V - 0.5 V. This means that each input has a maximum signal swing of 1 VPP for a total differential input signal swing of 2 VPP. The maximum fullscale range can be programmed from 1.5-2Vpp using the SPI. The maximum swing is determined by the internal reference voltage generator and the fullscale range set using the SPI, eliminating the need for any external circuitry for this purpose. The analog gain adjustment has a resolution of 12-bits across the 1.5-2VPP range, providing for fine calibration of analog gain mismatches across multiple ADS5400 signal chains, primarily for interleaving. 31 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com The ADS5400 obtains optimum performance when the analog inputs are driven differentially. The circuit in Figure 28 shows one possible configuration using an RF transformer. Datasheet performance, especially at >1GHz input frequency, can only be obtained with a carefully designed differential drive path to the ADC. R0 Z0 50 W 50 W AIN R 100 W AC Signal Source ADS5400 AIN 1:1 Figure 28. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer Voltage Reference The 2V voltage reference is provided internal to the ADS5400. A VCM (voltage common mode) pin is provided as an output for use in dc-coupled applications, equal to the AVDD5 supply divided by 2. This provides the analog input common mode voltage to a driving circuit so that the common mode is setup properly. Some systems may prefer the use of an external voltage reference. This mode can be enabled by pulling the ENEXTREF pin high. In this mode, an external reference can be driven onto the VREF pin, which is normally expecting 2V. Analog Input Over-Range Recovery Error An over-range condition occurs if the analog input voltage exceeds the full-scale range of the converter (0dBFS). To test recovery from an over-range, the ADC analog input is injected with a sinusoidal input frequency exactly at CLKIN/4 (a four-point sinusoid at the digital outputs). The four sample points of each period occur at the top, midscale, bottom and mid-scale of the sinusoid (clipped by the ADC when over-ranged to all 0s or all 1s). Once the amplitude exceeds 0dBFS, the top and bottom of the sinusoidal input becomes out of range, while the mid-scale point is always in-range and measureable with ADC output codes. The graph in Figure 29 indicates the amount of error from the expected mid-scale value of 2048 that occurs after negative over-range (bottom of sinusoid) and positive over-range (top of sinusoid). This equates to the amount of error in a valid sample 1 clock cycle after an over-range occurs, as a function of input amplitude. 25 After Positive Over-range 200MSPS (5ns) 20 After Negative Over-range 400MSPS (2.5ns) 15 Mid-Scale Code Error - % After Positive Over-range 1GSPS (1ns) 10 5 0 -5 -10 -15 After Positive Over-range 400MSPS (2.5ns) -20 -25 -1 0 1 After Negative Over-range 1GSPS (1ns) 2 3 After Negative Over-range 200MSPS (5ns) 4 5 6 Analog Input Amplitude - dBFS G023 Figure 29. Recovery Error 1 Clock Cycle After Over-Range vs Input Amplitude 32 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Clock Inputs The ADS5400 clock input can be driven with either a differential clock signal or a single-ended clock input. The equivalent clock input circuit can be seen in Figure 30. In low-input-frequency applications, where jitter may not be a big concern, the use of a single-ended clock (as shown in Figure 31) could save cost and board space without much performance tradeoff. When clocked with this configuration, it is best to connect CLK to ground with a 0.01-F capacitor, while CLK is ac-coupled with a 0.01-F capacitor to the clock source, as shown in Figure 31. ADS5400 AVDD5 ~7.2 nH Bond Wire 10 W CLKINP ~1.5 pF Package ~0.2 pF Bondpad 400 W 200 W GND 0.25 pF Internal Clock Buffer AVDD5V/2 AVDD5 0.25 pF ~7.2 nH Bond Wire 400 W GND CLKINN ~1.5 pF Package 10 W ~0.2 pF Bondpad GND Figure 30. Clock Input Circuit Square Wave or Sine Wave CLK 0.01 mF ADS5400 CLK 0.01 mF Figure 31. Single-Ended Clock 33 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 65 fIN = 10.05 MHz fIN = 10.05 MHz 75 fIN = 100.33 MHz 70 fIN = 601.13 MHz SNR - Signal-to-Noise Ratio - dBFS SFDR - Spurious-Free Dynamic Range - dBc 80 www.ti.com fIN = 901.13 MHz 65 60 fIN = 801.13 MHz 55 fIN = 1498.50 MHz 50 60 fIN = 801.13 MHz 55 fIN = 901.13 MHz fIN = 1498.50 MHz 50 45 45 fs = 1 GSPS fs = 1 GSPS 40 0 0.2 0.4 0.6 0.8 Clock Amplitude - Vp-p 1 fIN = 100.33 MHz fIN = 601.13 MHz 1.2 40 0 0.2 0.4 0.6 0.8 Clock Amplitude - Vp-p 1 1.2 Figure 32. ADS5400 SFDR vs Differential Clock Figure 33. ADS5400 SNR vs Differential Clock Level Level The characterization of the ADS5400 is typically performed with a 1.5 VPP differential clock, but the ADC performs well with a differential clock amplitude down to ~400mVPP (200mV swing on both CLK and CLK), as shown in Figure 32 and Figure 33. For jitter-sensitive applications, the use of a differential clock has some advantages at the system level and is strongly recommended. The differential clock allows for common-mode noise rejection at the printed circuit board (PCB) level. With a differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency applications because the board level clock jitter is superior. Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. At high analog input frequencies, the sampling process is sensitive to jitter. At slow clock frequencies, a small amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR degradation due to the uncertainty in the sampling point associated with a slow slew rate. Figure 34 demonstrates a recommended method for converting a single-ended clock source into a differential clock; it is similar to the configuration found on the evaluation board and was used for much of the characterization. See also Clocking High Speed Data Converters (SLYT075) for more details. Clock Source 0.1 mF CLK ADS5400 CLK Figure 34. Differential Clock The common-mode voltage of the clock inputs is set internally to 2.5 V using internal 400 resistors (see Figure 30). It is recommended to use ac coupling in the clock path, but if this scheme is not possible, the ADS5400 features good tolerance to clock common-mode variation, as shown in Figure 35 and Figure 36. The internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided. 34 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 65 fIN = 901.13 MHz fIN = 100.33 MHz 75 SNR - Signal-to-Noise Ratio - dBFS SFDR - Spurious-Free Dynamic Range - dBc 80 70 65 fIN = 601.13 MHz 60 fIN = 1498.5 MHz 55 50 fIN = 601.13 MHz 60 fIN = 100.33 MHz fIN = 1498.5 MHz 55 fIN = 901.13 MHz 50 45 45 fS = 1 GSPS 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 fS = 1 GSPS 40 0.0 0.5 1.0 Clock Common Mode - V 1.5 2.0 2.5 3.0 3.5 Clock Common Mode - V G016 Figure 35. ADS5400 SFDR vs Clock Common Mode G017 Figure 36. ADS5400 SNR vs Clock Common Mode To understand how to determine the required clock jitter, an example is useful. The ADS5400 is capable of achieving 58.7 dBFS SNR at 850 MHz of analog input frequency. To achieve SNR at 850 MHz, the external clock source rms jitter must be at least 210fs when combined with the 125fs of internal aperture jitter in order for the total rms jitter to be 244fs. A summary of maximum recommended rms clock jitter as a function of analog input frequency is provided in Table 18 (using 125fs of internal aperture jitter). The equations used to create the table are also presented. Table 18. Recommended RMS Clock Jitter INPUT FREQUENCY (MHz) MEASURED SNR (dBc) TOTAL JITTER (fs rms) MAXIMUM EXT CLOCK JITTER (fs rms) 125 58.1 1585 1580 600 57.8 318 342 850 57.7 244 210 1200 56.6 196 151 1700 54.7 172 119 Equation 1 and Equation 2 are used to estimate the required clock source jitter. SNR (dBc) = -20 x LOG10 (2 x p x fIN x jTOTAL) 2 (1) 2 1/2 jTOTAL = (jADC + jCLOCK ) (2) where: jTOTAL = the rms summation of the clock and ADC aperture jitter; jADC = the ADC internal aperture jitter which is located in the data sheet; jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and fIN = the analog input frequency. Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates. For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC Devices. Recommended clock distribution chips (CDCs) are the TI CDC7005 and CDCM7005. Depending on the jitter requirements, a band pass filter (BPF) is sometimes required between the CDC and the ADC. If the insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the clock source amplitude is too low to begin with, an inexpensive amplifier can be placed between the CDC and the BPF. 35 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com Figure 37 represents a scenario where an LVPECL output is used from a TI CDCM7005 with the clock signal path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult to estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter provided by the CDC is still not adequate. The total jitter at the CDCM7005 output depends heavily on the phase noise of the VCXO selected. If it is determined that the jitter from the CDCM7005 with a VCXO is sufficient without further conditioning, it is possible to clock the ADS5400 directly from the CDCM7005 using differential LVPECL outputs (see the CDCM7005 data sheet for the exact schematic). A careful analysis of the required jitter and of the components involved is recommended before determining the proper approach. Low Jitter Clock Distribution Board Master Reference Clock ( High or Low Jitter) 10 MHz AMP and /or BPF optional , depending on jitter requirements REF LVPECL AMP SAW XFMR 1000 MHz CLKIN CLKIN ADC 1000 MHz (To Transmit DAC ) 125 MHz (To DSP ) Low Jitter Oscillator 250 MHz (To FPGA ) 1000 MHz VCO TI ADS5400 LVPECL or LVCMOS CDC (Clock Distribution Chip) Ex : TI CDCM7005 To Other This is a general block diagram example: Consult the datasheet of the CDCM7005 for proper schematic and for specifications regarding allowable input and output frequency and amplitude ranges . Figure 37. Clock Source Diagram 36 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Digital Outputs Output Bus and Clock Options The ADS5400 has two buses, A and B. Using register 0x02, a single or dual bus output can be selected. In single-bus mode, bus A is used at the full clock rate, while in two-bus mode, data is multiplexed at half the clock rate on A and B. While in single bus mode, CLKOUTA will be at frequency CLKIN/2 and a DDR interface is achieved. In two-bus mode, CLKOUTA/CLKOUTB can be either at frequency CLKIN/2 or CLKIN/4, providing options for an SDR or DDR interface. The ADC provides 12 LVDS-compatible data outputs (D11 to D0; D11 is the MSB and D0 is the LSB), a data-ready signal (CLKOUT), and an over-range indicator (OVR) on each bus. It is recommended to use the CLKOUT signal to capture the output data of the ADS5400. Both two's complement and offset binary are available output formats, in register 0x05. The capacitive loading on the digital outputs should be minimized. Higher capacitance shortens the data-valid timing window. The values given for timing were obtained with an estimated 3.5-pF of differential parasitic board capacitance on each LVDS pair. Reset and Synchronization Referencing the timing diagrams starting in Figure 1, the polarity of CLKOUT with respect to the sample N data output transition is undetermined because of the unknown startup logic level of the clock divider that generates the CLKOUT signal, whether in frequency CLKIN/2 or CLKIN/4 mode. The polarity of CLKOUT could invert when power is cycled off/on. If a defined CLKOUT polarity is required, the RESET input pins are used to reset the clock divider to a known state after power on with a reset pulse. A RESET is not commonly required when using only one ADS5400 because a one sample uncertainty at startup is not usually a problem. NOTE: initial samples capture RESET = HIGH on the rising edge of CLKINP. This is being corrected for final samples and will reflect the diagram as drawn, with RESET = HIGH captured on falling edge of CLKINP. In addition to CLKOUT alignment using RESET, a synchronization mode is provided in register 0x05. In this mode, the OVR output becomes the SYNCOUT. The SYNCOUT will indicate which sample was present when the RESET input pulse was captured in a HIGH state. The OVR indicator is not available when sync mode is enabled. In single bus mode, only SYNCOUTA is used. In dual bus mode, only SYNCOUTB is used. LVDS Differential source loads of 100 and 200 are provided internal to the ADS5400 and can be implemented using register 0x06 (as well as no internal load). Normal LVDS operation expects 3.5mA of current, but alternate values of 2.5, 4.5, and 5.5mA are provided to save power or improve the LVDS signal quality when the environment provides excessive loading. Over Range The OVR output equals a logic high when the 12-bit output word attempts to exceed either all 0s or all 1s. This flag is provided as an indicator that the analog input signal exceeded the full-scale input limit set in register 0x00 and 0x01 ( gain error). The OVR indicator is provided for systems that use gain control to keep the analog input signal within acceptable limits. The OVR pins are not available when the sychronization mode is enabled, as they become the SYNCOUT indicator. Data Scramble In normal operation, with this mode disabled, the MSBs have similar energy to the analog input fundamental frequency and can in some instances cause board interference. A data scramble mode is available in register 0x06. In this mode, bits 11-1 are XOR'd with bit 0 (the LSB). Because of the random nature of the LSB, this has the effect of randomizing the data pattern. To de-scramble, perform the opposite operation in the digital chip after receiving the scrambled data. 37 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com Test Patterns Determining the closure of timing or validating the digital interface can be difficult in normal operation. Therefore, test patterns are available in register 0x06. One pattern toggles the outputs between all 1s and all 0s. Another pattern generates a 7-bit PRBS (pseudo-random bit sequence). In dual bus mode, the toggle mode could be in the same phase on bus A and B (bus A and B outputting 1s or 0s together), or could be out of phase (bus A outputting 1s while bus B outputs 0s). The start phase cannot be controlled. The PRBS output sequence is a standard 27-1 pseudo-random sequence generated by a feedback shift register where the two last bits of the shift register are exclusive-OR'ed and fed back to the first bit of the shift register. The standard notation for the polynomial is x7 + x6 + 1. The PRBS generator is not reset, so there is no initial position in the sequence. The pattern may start at any position in the repeating 127-bit long pattern and the pattern repeats as long as the PRBS mode is enabled. The data pattern from the PRBS generator is used for all of the LVDS parallel outputs, so when the pattern is `1' then all of the LVDS outputs are outputting `1' and when the pattern is `0' then all of the LVDS drivers output `0'. To determine if the digital interface is operating properly with the PRBS sequence, the user must generate the same sequence in the receiving device, and do a shift-andcompare until a matching sequence is confirmed. Die Identification and Revision A unique 64-bit die indentifier code can be read from registers 0x17 through 0x1E. An 8-bit die revision code is available in register 0x1F. Die Temperature Sensor In register 0x05, the die temperature sensor can be enabled. The sensor is power controlled independently of global powerdown, so that it and the SPI can be used to monitor the die temperature even when the remainder of the ADC is in sleep mode. Register 0x08 is used to read values which can be mapped to the die temperature. The exact mapping is detailed in the register map. Care should be taken not to exceed a maximum die temperature of 150C for prolonged periods of time in order to maintain the life of the device. Interleaving Gain Adjustment A signal gain adjustment is available in registers 0x00 and 0x01. The allowable fullscale range for the ADC is 1.52 - 2VPP and can be set with 12-bit adjustment resolution across this range. For equal up/down gain adjustment of the system and ADC gain mismatches, a nominal starting point of 1.75VPP could be programmed, in which case 250mV of adjustment range would be provided. Offset Adjustment Analog offset adjustment is available in register 0x03 and 0x04. This provides 30mV of adjustment range with 9bit adjustment resolution of 120uV per step. At production test, the default code for this register setting is set to a value that provides 0mV of ADC offset. For optimum spectral performance, it is not recommended to use more than 8mV adjustment from the default setting Input Clock Coarse Phase Adjustment Coarse adjustment is available in register 0x02. The typical range is approximately 73 ps with a resolution of 2.4ps. Input Clock Fine Phase Adjustment Fine adjustment is available in register 0x03. The typical range is approximately 7.4 ps with a resolution of 116fs. 38 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 Power Supplies The ADS5400 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5 and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched supplies generate more noise components that can be coupled to the ADS5400. The PSRR value and the plot shown in Figure 38 were obtained without bulk supply decoupling capacitors. When bulk (0.1 F) decoupling capacitors are used, the board-level PSRR is much higher than the stated value for the ADC. The power consumption of the ADS5400 does not change substantially over clock rate or input frequency as a result of the architecture and process. PSRR - Power Supply Rejection Ratio - dB 100 90 DVDD3 80 70 60 50 40 30 AVDD5 AVDD3 20 10 0 0.01 0.1 1 10 100 Frequency - MHz G022 Figure 38. PSRR versus Supply Injected Frequency 39 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com Layout Information The evaluation board provides a guideline of how to lay out the board to obtain the maximum performance from the ADS5400. General design rules, such as the use of multilayer boards, single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors, should be applied. The input traces should be isolated from any external source of interference or noise, including the digital outputs as well as the clock traces. The clock signal traces should also be isolated from other signals, especially in applications where low jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when considering the heat dissipation of the device. The thermal heat sink should be soldered to the board. Check with factory for ADS5400 EVM User Guide for the evaluation board schematic. 40 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP www.ti.com SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the lowfrequency value Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay Clock Pulse Duration/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse duration) to the period of the clock signal, expressed as a percentage. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSB. Common-Mode Rejection Ratio (CMRR) CMRR measures the ability to reject signals that are presented to both analog inputs simultaneously. The injected common-mode frequency level is translated into dBFS, the spur in the output FFT is measured in dBFS, and the difference is the CMRR in dB. Effective Number of Bits (ENOB) ENOB is a measure in units of bits of a converter's performance as compared to the theoretical limit based on quantization noise ENOB = (SINAD - 1.76)/6.02 (3) Gain Error Gain error is the deviation of the ADC actual input full-scale range from its ideal value, given as a percentage of the ideal input full-scale range. Integral Nonlinearity (INL) INL is the deviation of the ADC transfer function from a best-fit line determined by a least-squares curve fit of that transfer function. The INL at each analog input value is the difference between the actual transfer function and this best-fit line, measured in units of LSB. Offset Error Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode. Power-Supply Rejection Ratio (PSRR) PSRR is a measure of the ability to reject frequencies present on the power supply. The injected frequency level is translated into dBFS, the spur in the output FFT is measured in dBFS, and the difference is the PSRR in dB. The measurement calibrates out the benefit of the board supply decoupling capacitors. Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and in the first five harmonics. P SNR + 10log 10 S PN (4) SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's fullscale range. 41 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP ADS5400-SP SLAS669C - SEPTEMBER 2010 - REVISED AUGUST 2012 www.ti.com Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD + 10log 10 PN ) PD (5) SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's fullscale range. Temperature Drift Temperature drift (with respect to gain error and offset error) specifies the change from the value at the nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters over the whole temperature range divided by TMIN - TMAX. Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first five harmonics (PD). P THD + 10log 10 S PD (6) THD is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion (IMD3) IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power of the worst spectral component at either frequency 2f1 - f2 or 2f2 - f1). IMD3 is given in units of either dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. 42 Copyright (c) 2010-2012, Texas Instruments Incorporated Product Folder Links: ADS5400-SP PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty 5962-0924001VXC ACTIVE CFP HFS 100 ADS5400HFS/EM PREVIEW CFP HFS 100 ADS5400MHFSV ACTIVE CFP HFS 100 1 1 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) TBD Call TI Call TI -55 to 125 TBD AU N / A for Pkg Type 25 Only TBD Call TI Call TI -55 to 125 Device Marking (4/5) (5962- ~ ADS5400MHFSV) 0924001VXC ADS5400MHFS-V ADS5400HFS/EM EVAL ONLY (5962- ~ ADS5400MHFSV) 0924001VXC ADS5400MHFS-V (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS5400-SP : * Catalog: ADS5400 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2013, Texas Instruments Incorporated