REFERENCE
INP
INN
CLKINP
CLKINN
SCLK
SDIO
SDO
CLKOUTAP
CLKOUTAN
OUTB[0-11]P
OUTB[0-11]N
ADS
BLOCKDIAGRAM
5400
CLOCK
DIVIDE
12-bit ADC
(3 stagepipeline)
VCM
VREF OVERRANGE
DETECTOR,
SYNCand
DEMUX
12
OUTA[0-11]P
OUTA[0-11]N
12
12
OVRBP (SYNCOUTBP)
OVRBN (SYNCOUTBN)
RESETP (SYNCINP)
RESETN (SYNCINN)
SDENB
BUFFER
CLKOUTBP
CLKOUTBN
OVRAP (SYNCOUTAP)
OVRAN (SYNCOUTAN)
ENEXTREF
ENPWD
ENA1BUS
CONTROL
TEMP SENSOR
OFFSET ADJUST
PHASE ADJUST
GAIN ADJUST
BUS A
BUSB
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
12-Bit, 1-GSPS Analog-to-Digital Converter
Check for Samples: ADS5400-SP
1FEATURES • 100-Pin Ceramic Nonconductive Tie-Bar
Package
• 1-GSPS Sample Rate • Military Temperature Range
• 12-Bit Resolution (–55°C to 125°C Tcase)
• 2.1 GHz Input Bandwidth • Processed Per Internal QML Class V
• SFDR = 65 dBc at 1.2 GHz Assembly/Test Flow
• SNR = 57 dBFS at 1.2 GHZ • QML Class V Qualified, SMD 5962-09240
• 7 Clock Cycle Latency
• Interleave Friendly: Internal Adjustments for APPLICATIONS
Gain, Phase and Offset • Test and Measurement Instrumentation
• 1.5 - 2 VPP Differential Input Voltage, • Ultra-Wide Band Software-Defined Radio
Programmable • Data Acquisition
• LVDS-Compatible Outputs, 1 or 2 Bus Options • Power Amplifier Linearization
• Total Power Dissipation: 2.2 W • Signal Intelligence and Jamming
• On-Chip Analog Buffer • Radar
DESCRIPTION
The ADS5400 is a 12-bit, 1-GSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and
3.3-V supply, while providing LVDS-compatible digital outputs. The analog input buffer isolates the internal
switching of the track and hold from disturbing the signal source. The simple 3-stage pipeline provides extremely
low latency for time critical applications. Designed for the conversion of signals up to 2 GHz of input frequency at
1 GSPS, the ADS5400 has outstanding low noise performance and spurious-free dynamic range over a large
input frequency range.
The ADS5400 is available in a 100-Pin Ceramic Nonconductive Tie-Bar Package. The combination of the
ceramic package and moderate power consumption of the ADS5400 allows for operation without an external
heatsink. The ADS5400 is built on Texas Instrument's complementary bipolar process (BiCom3) and is specified
over the full military temperature range (–55°C to 125°C Tcase).
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. PACKAGE/ORDERING INFORMATION(1)
TEMPERATURE PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING
ADS5400MHFSV 5962-0924001VXC
–55°C to 125°C Tcase ADS5400MHFS-V
5962-0924001VXC
CFP-HFS ADS5400HFS/EM(3)
25°C ADS5400HFSMPR EVAL ONLY
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, standard packaging quanities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(3) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are
tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts
are not warranted for performance over the full MIL specified temperature range of -55°C to 125°C or operating life.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
AVDD5 to GND 6 V
Supply voltage AVDD3 to GND 5 V
DVDD3 to GND 5 V
AINP, AINN to GND(2) voltage difference between pin and ground 0.5 to 4.5 V
short duration –0.3 to (AVDD5 + 0.3) V
voltage difference between
AINP to AINN (2) pins, common mode at continuous AC signal 1.25 to 3.75 V
AVDD5/2 continuous DC signal 1.75 to 3.25 V
CLKINP, CLKINN to GND (2) voltage difference between pin and ground 0.5 to 4.5 V
voltage difference between continuous AC signal 1.1 to 3.9 V
CLKINP to CLKINN (2) pins, common mode at continuous DC signal 2 to 3 V
AVDD5/2
RESETP, RESETN to GND (2) voltage difference between pin and ground –0.3 to (AVDD5 + 0.3) V
continuous AC signal 1.1 to 3.9 V
voltage difference between
RESETP to RESETN (2) pins continuous DC signal 2 to 3 V
Data/OVR Outputs to GND (2) –0.3 to (DVDD3 + 0.3)
SDENB, SDIO, SCLK to GND(2) –0.3 to (AVDD3 + 0.3)
voltage difference between pin and ground V
ENA1BUS, ENPWD, ENEXTREF –0.3 to (AVDD5 + 0.3)
to GND(2)
Operating case temperature range –55 to 125 °C
Maximum junction temperature, TJ150 °C
Storage temperature range –65 to 150 °C
ESD, human-body model (HBM) 2 kV
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime is available upon
request.
(2) Valid when supplies are within recommended operating range.
2Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
THERMAL CHARACTERISTICS(1)
PARAMETER TEST CONDITIONS TYP UNIT
RθJA JESD51-2 and JESD51-3 (2) 21.81 °C/W
RθJC MIL-STD-883 Test Method 1012(3) 0.849 °C/W
(1) This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package.
To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly
underneath the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package
is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it
that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI
typically recommends an 11,9 mm2 board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads
away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device
within recommended operating conditions. This pad must be electrically at ground potential.
(2) RθJA is the thermal resistance from the junction to ambient.
(3) RθJC is the thermal resistance from the junction to case.
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT
SUPPLIES
Analog supply voltage, AVDD5 4.75 5 5.25 V
Analog supply voltage, AVDD3 3.135 3.3 3.465 V
Digital supply voltage, DVDD3 3.135 3.3 3.465 V
ANALOG INPUT
Full-scale differential input range 1.52 2 Vpp
VCM Input common mode AVDD5/2 V
DIGITAL OUTPUT
Differential output load 5 pF
CLOCK INPUT
CLK input sample rate (sine wave) 100 1000 MSPS
Clock amplitude, differential 0.6 1.5 Vpp
Clock duty cycle 45% 50% 55%
TCOperating case temperature –55 125 °C
Copyright © 2010–2012, Texas Instruments Incorporated 3
Product Folder Links: ADS5400-SP
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
Typical values at TA= 25°C, minimum and maximum values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input,
and 1.5 VPP differential clock (unless otherwise noted)
PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT
ANALOG INPUTS
Full-scale differential input range Programmable 1.52 2 VPP
VCM Common-mode input Self-biased to AVDD5 / 2 AVDD5/2 V
RIN Input resistance, differential (dc) 100 Ω
Estimated to ground from each AIN pin,
CIN Input capacitance 4.3 pF
excluding soldered package
CMRR Common-mode rejection ratio Common mode signal = 125 MHz 40 dB
INTERNAL REFERENCE VOLTAGE
VREF Reference voltage 1.98 2 2.02 V
DYNAMIC ACCURACY
Resolution No missing codes 12 Bits
DNL Differential linearity error fIN = 125 MHz -1 ±0.4 2.5 LSB
INL Integral non- linearity error fIN = 125 MHz -4.5 ±1.5 4.5 LSB
Offset error default is trimmed near 0mV –2.5 0 2.5 mV
Offset temperature coefficient 0.02 mV/°C
Gain error ±5 %FS
Gain temperature coefficient 0.03 %FS/°C
POWER SUPPLY(1)
5-V analog supply current (Bus A and 220 245 mA
B active)
I(AVDD5) 5-V analog supply current (Bus A 225 255 mA
active)
3.3-V analog supply current (Bus A 205 234 mA
and B active)
I(AVDD3) 3.3-V analog supply current (Bus A 226 242 mA
active) fIN = 125 MHz,
fS= 1 GSPS
3.3-V digital supply current 136 154 mA
(Bus A and B active)
I(DVDD3) 3.3-V digital supply current 72 85
(Bus A active) mA
Total power dissipation 2.2 2.5 W
(BUS A and B active)
Total power dissipation 2 2.3 W
(Bus A active)
Total power dissipation ENPWD = logic High (sleep enabled) 13 50 mW
Wake-up time from sleep 1.8 ms
1MHz injected to each supply,
PSRR Power-supply rejection ratio 50 dB
measured without external decoupling
DYNAMIC AC CHARACTERISTICS
fIN = 125 MHz 54 58.5
fIN = 600 MHz 53.5 58.3
SNR Signal-to-noise ratio fIN = 850 MHz 53 58 dBFS
fIN = 1200 MHz 57.6
fIN = 1700 MHz 55.7
(1) All power values assume LVDS output current is set to 3.5mA.
4Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA= 25°C, minimum and maximum values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input,
and 1.5 VPP differential clock (unless otherwise noted)
PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT
fIN = 125 MHz 62 72
fIN = 600 MHz 60 70
SFDR Spurious-free dynamic range fIN = 850 MHz 56 62.7 dBc
fIN = 1200 MHz 65.7
fIN = 1700 MHz 56
fIN = 125 MHz 62 78
fIN = 600 MHz 60 75
HD2 Second harmonic fIN = 850 MHz 56 62.5 dBc
fIN = 1200 MHz 66
fIN = 1700 MHz 56
fIN = 125 MHz 62 78
fIN = 600 MHz 60 72
HD3 Third harmonic fIN = 850 MHz 56 75 dBc
fIN = 1200 MHz 70
fIN = 1700 MHz 63
fIN = 125 MHz 62 80
fIN = 600 MHz 60 79
Worst harmonic/spur (other than HD2 fIN = 850 MHz 56 79 dBc
and HD3) fIN = 1200 MHz 66
fIN = 1700 MHz 64
fIN = 125 MHz 60 71.7
fIN = 600 MHz 58 67
THD Total Harmonic Distortion fIN = 850 MHz 55 66.5 dBc
fIN = 1200 MHz 63.8
fIN = 1700 MHz 55.7
fIN = 125 MHz 53 57
fIN = 600 MHz 52.4 56.8
SINAD Signal-to-noise and distortion fIN = 850 MHz 50.8 55.8 dBFS
fIN = 1200 MHz 56.6
fIN = 1700 MHz 52.7
fIN1 = 247.5 MHz, fIN2 = 252.5 MHz, 74.6
each tone at –7 dBFS
fIN1 = 247.5 MHz, fIN2 = 252.5 MHz, 77.9
each tone at –11 dBFS
Two-tone SFDR dBFS
fIN1 = 1197.5 MHz, fIN2 = 1202.5 MHz, 68.3
each tone at –7 dBFS
fIN1 = 1197.5 MHz, fIN2 = 1202.5 MHz, 73.7
each tone at –11 dBFS
fIN = 125 MHz 8.52 9.55
Effective number of bits (using
ENOB fIN = 600 MHz 8.42 9.29 Bits
SINAD in dBFS) fIN = 850 MHz 8.16 9.23
1.41 LSB rms
RMS idle-channel noise Inputs tied to common-mode 60.2 dBFS
Copyright © 2010–2012, Texas Instruments Incorporated 5
Product Folder Links: ADS5400-SP
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
SWITCHING CHARACTERISTICS
Typical values at TA= 25°C, Min and Max values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock
(unless otherwise noted)
PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT
LVDS DIGITAL OUTPUTS (DATA, OVR/SYNCOUT, CLKOUT)
VOD Differential output voltage (±) 247 350 454 mV
Terminated 100 Ωdifferential
VOC Common mode output voltage 1.125 1.25 1.375 V
LVDS DIGITAL INPUTS (RESET)
VID Differential input voltage (±) 175 350 mV
Each input pin
VIC Common mode input voltage 0.1 1.25 2.4 V
RIN Input resistance 100 Ω
CIN Input capacitance Each pin to ground 3.7 pF
DIGITAL INPUTS (SCLK, SDIO, SDENB)
VIH High level input voltage 2 AVDD3 + 0.3 V
VIL Low level input voltage 0 0.8 V
IIH High level input current ±1 μA
IIL Low level input current ±1 μA
CIN Input capacitance 2.9 pF
DIGITAL INPUTS ( ENEXTREF, ENPWD, ENA1BUS)
VIH High level input voltage 2 AVDD5 + 0.3 V
VIL Low level input voltage 0 0.8 V
IIH High level input current 125 μA
~40kΩinternal pull-down
IIL Low level input current 20 μA
CIN Input capacitance 2.9 pF
DIGITAL OUTPUTS (SDIO, SDO)
VOH High level output voltage IOH = 250 µA 2.8 V
VOL Low level output voltage IOL = 250 µA 0.4 V
CLOCK INPUTS
RIN Differential input resistance CLKINP, CLKINN 100 130 190 Ω
Input capacitance Estimated to ground from each
CIN CLKIN pin, excluding soldered 4.8 pF
packaged
TIMING CHARACTERISTICS(1)
Typical values at TA= 25°C, Min and Max values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock
(unless otherwise noted)
PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT
taAperture delay 250 ps
Uncertainty of sample point due to internal jitter
Aperture jitter, rms 125 fs
sources
Bus A, using Single Bus Mode 7
Bus A, using Dual Bus Mode Aligned 7.5
Latency Cycles
Bus B, using Dual Bus Mode Aligned 8.5
Bus A and B, using Dual Bus Mode Staggered 7.5
(1) Timing parameters are specified by design or characterization, but not production tested.
6Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
TIMING CHARACTERISTICS(1) (continued)
Typical values at TA= 25°C, Min and Max values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock
(unless otherwise noted)
PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT
LVDS OUTPUT TIMING (DATA, CLKOUT, OVR/SYNCOUT)(2)
tCLK Clock period 1 10 ns
tCLKH Clock pulse duration, high Assuming worst case 45/55 duty cycle 0.45 ns
tCLKL Clock pulse duration, low Assuming worst case 55/45 duty cycle 0.45 ns
CLKIN rising to CLKOUT rising in divide by 2 1200
tPD-CLKDIV2 Clock propagation delay ps
mode
CLKIN rising to CLKOUT rising in divide by 4 1200
tPD-CLKDIV4 Clock propagation delay ps
mode
Bus A data propagation
tPD-ADATA 1400 ps
delay CLKIN falling to Data Output transition
Bus B data propagation
tPD-BDATA 1400 ps
delay Data valid to CLKOUT edge, 50% CLKIN duty
tSU-SBM (3) Setup time, single bus mode 290 (tCLK/2) - 185 ps
cycle
CLKOUT edge to Data invalid, 50% CLKIN duty
tH-SBM Hold time, single bus mode 410 (tCLK/2) - 65 ps
cycle
Data valid to CLKOUT edge, 50% CLKIN duty
tSU-DBM Setup time, dual bus mode 550 tCLK - 425 ps
cycle
CLKOUT edge to Data invalid, 50% CLKIN duty
tH-DBM Hold time, dual bus mode 1150 tCLK + 175 ps
cycle
trLVDS output rise time 400 ps
Measured 20% to 80%
tfLVDS output fall time 400 ps
LVDS INPUT TIMING (RESETIN)
tRSU RESET setup time RESETP going HIGH to CLKINP going LOW 325 ps
tRH RESET hold time CLKINP going LOW to RESETP going LOW 325 ps
RESET input capacitance Differential 1 pF
RESET input current ±1 µA
SERIAL INTERFACE TIMING
tS-SDENB Setup time, serial enable SDENB falling to SCLK rising 20 ns
tH-SDENB Hold time, serial enable SCLK falling to SENDB rising 25 ns
tS-SDIO Setup time, SDIO SDIO valid to SCLK rising 10 ns
tH-SDIO Hold time, SDIO SCLK rising to SDIO transition 10 ns
fSCLK Frequency 10 MHz
tSCLK SCLK period 100 ns
tSCLKH Minimum SCLK high time 40 ns
tSCLKL Minimum SCLK low time 40 ns
trRise time 10pF 10 ns
tfFall time 10pF 10 ns
Data output (SDO/SDIO) delay after SCLK
tDDATA Data output delay 75 ns
falling, 10pF load
(2) LVDS output timing measured with a differential 100Ωload placed ~4 inches from the ADS5400. Measured differential load capacitance
is 3.5pF. Measurement probes and other parasitics add ~1pF. Total approximate capacitive load is 4.5pF differential. All timing
parameters are relative to the device pins, with the loading as stated.
(3) In single bus mode at 1GSPS (1ns clock), the minimum output setup/hold times over process and temperature provide a minimum
700ps of data valid window, with 300ps of uncertainity.
Copyright © 2010–2012, Texas Instruments Incorporated 7
Product Folder Links: ADS5400-SP
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
INTERLEAVING ADJUSTMENTS
Typical values at TA= 25°C, Min and Max values over full temperature range TMIN = –55°C to TMAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET ADJUSTMENTS
Resolution 9 Bits
LSB magnitude at full scale range of 2VPP 120 µV
DNL Differential linearity error -2.5 2.5 LSB
INL Integral Non-Linearity error -3 3 LSB
Recommended Min Offset -8 mV
Setting from default offset value, to maintain AC
performance
Recommended Max Offset 8 mV
Setting
GAIN ADJUSTMENTS
Resolution 12 Bits
LSB magnitude 120 µV
DNL Differential linearity error -4 -1.2, 4 LSB
+0.5
INL Integral Non-Linearity error -8 -2, +1 8 LSB
Min Gain Setting 1.52 VPP
Max Gain Setting 2 VPP
INPUT CLOCK FINE PHASE ADJUSTMENT
Resolution 6 Bits
LSB magnitude 116 fs
DNL Differential linearity error -2 2.5 LSB
INL Integral Non-Linearity error -2.5 4 LSB
Max Fine Clock Skew setting 7.4 ps
INPUT CLOCK COARSE PHASE ADJUSTMENT
Resolution 5 Bits
LSB magnitude 2.4 ps
DNL Differential linearity error -1 1 LSB
INL Integral Non-Linearity error -1 5 LSB
Max Coarse Clock Skew 73 ps
setting
8Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
CLKINP
RESETP CLKOUT isresetafter 3.5 CLKINcycles (+ tPD-CLKDIV2 )
Phase 0: CLKOUT indesired
stateafterpowerup
Phase 1: misalignedby
1 clockafterpowerup
tPD-CLKDIV2
tRSU tRH
DATA BUS A N
SYNCOUTA
(OVRA pins) Sync
SampleNandRESET pulse
capturedhere
CLKOUTAP
IfSYNCmodeisenabled,
theOVRA pinsbecomeSYNCOUTA pins
LatencyofNandSYNCOUTA arematchedto 7 CLKINcycles
t
tsu
th
PD-ADATA
N+1N-1
tCLKL
tCLKH
N
ta
N+1
DIFFERENTIAL
ANALOGINPUT
(INP-INN) Aperture
delay
N+2
N+2
N
output
N+1
output
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Timing Diagrams
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTA transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit. Bus B is not active in single bus mode.
Figure 1. Single Bus Mode
Copyright © 2010–2012, Texas Instruments Incorporated 9
Product Folder Links: ADS5400-SP
CLKINP
RESETP
Phase 0: CLKOUT indesired
stateafterpowerup
Phase 1: misalignedby 1
clockafterpowerup
tPD-CLKDIV2
CLKOUTAP
CLKOUTBP
DATA BUSB
SYNCOUTB
(OVRBpins) Sync
N
SampleNandRESET
pulsecapturedhere
tPD-BDATA
CLKOUT isresetafter 3.5 CLKINcycles (+ tPD-CLKDIV2 )
N+2
N+1 N+3
DATA BUS A
IfSYNCmodeisenabled,
theOVRBpinsbecomeSYNCOUTBpins
LatencyofN+1 is 7.5 CLKINcycles
LatencyofNandSYNCOUTBarematchedto 8.5 CLKINcycles
tPD-ADATA
N+1
ThephaseofdatashownpriortoresetmatchesCLKOUT inphase 0
ThephaseofdatashownpriortoresetmatchesCLKOUT inphase 0
tRSU tRH
N, N+1
output
tsu
th
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
Timing Diagrams (continued)
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit.
Figure 2. Dual Bus Mode - Aligned, CLKOUT Divide By 2
10 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
CLKINP
RESETP
CLKOUTAP
DATA BUSB
SYNCOUTB
(OVRBpins) Sync
N
CLKOUT isresetafter 3.5 CLKINcycles (+ tPD-CLKDIV2 )
DATA BUS A N+1
N+2
CLKOUTBP
LatencyofN+1 is 7.5 CLKINcycles tPD-ADATA
N+1
tPD-CLKDIV2
tPD-BDATA
N+3
ThephaseofdatashownpriortoresetmatchesCLKOUT inphase 0
IfSYNCmodeisenabled,
theOVRBpinsbecomeSYNCOUTBpins
ThephaseofdatashownpriortoresetmatchesCLKOUT inphase 0
SampleNandRESET
pulsecapturedhere
LatencyofNandSYNCOUTBarematchedto 7.5 CLKINcycles
Phase 0: CLKOUT indesired
stateafterpowerup
Phase 1: misalignedby 1
clockafterpowerup
Phase 0: CLKOUT indesired
stateafterpowerup
Phase 1: misalignedby 1
clockafterpowerup
tRSU
N
output N+1
output
tRH
tsu
th
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Timing Diagrams (continued)
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit.
Figure 3. Dual Bus Mode - Staggered, CLKOUT Divide By 2
Copyright © 2010–2012, Texas Instruments Incorporated 11
Product Folder Links: ADS5400-SP
CLKINP
RESETP
tRSU tRH
DATA BUSB
SYNCOUTB
(OVRBpins)
IfSYNCmodeisenabled,
theOVRBpinsbecomeSYNCOUTBpins Sync
N
CLKOUTAP
CLKOUTBP
tPD-CLKDIV4
tPD-BDATA
Phase 0: CLKOUT indesired
stateafterpowerup
Phase 1: misalignedby 1
clockafterpowerup
Phase 2: misalignedby 2
clocksafterpowerup
Phase 3: misalignedby 3
clocksafterpowerup
N+1
DATA BUS A
LatencyofN+1is7.5CLKINcycles tPD-ADATA
CLKOUT isresetafter 7.5 CLKINcycles (+ tPD-CLKDIV4 )
ThephaseofdatashownpriortoresetmatchesCLKOUT inphase 0
ThephaseofdatashownpriortoresetmatchesCLKOUT inphase 0
SampleNandRESET
pulsecapturedhere N+1 N, N+1
output
LatencyofNandSYNCOUTBarematchedto8.5 CLKINcycles
th
tsu
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
Timing Diagrams (continued)
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit.
Figure 4. Dual Bus Mode - Aligned, CLKOUT Divide By 4
12 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
CLKINP
RESETP tPD-CLKDIV4
tRSU tRH
CLKOUTAP
DATA BUSB
SYNCOUTB
(OVRBpins)
DATA BUS A N+1
N+2
CLKOUTA isresetafter 7.5 CLKINcycles (+ tPD-CLKDIV4 )
SampleNandRESET
pulsecapturedhere
N+1
sampled
Phase 0: CLKOUT indesired
stateafterpowerup
Phase 1: misalignedby 1
clockafterpowerup
Phase 2: misalignedby 2
clocksafterpowerup
Phase 3: misalignedby 3
clocksafterpowerup
CLKOUTBP
Phase 0: CLKOUT indesired
stateafterpowerup
Phase 1: misalignedby 1
clockafterpowerup
Phase 2: misalignedby 2
clocksafterpowerup
Phase 3: misalignedby 3
clocksafterpowerup
LatencyofN+1 is 7.5 CLKINcycles tPD-ADATA
IfSYNCmodeisenabled,
theOVRBpinsbecomeSYNCOUTBpins
LatencyofNandSYNCOUTBarematchedto 7.5 CLKINcycles
ThephaseofdatashownpriortoresetmatchesCLKOUTBinphase 0
ThephaseofdatashownpriortoresetmatchesCLKOUTA inphase 0
tPD-CLKDIV4
N
Sync
CLKOUTBisresetafter 6.5 CLKINcycles (+ tPD-CLKDIV4 )
N
output
N+1
output
th
tsu
PD-BDATA
t
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Timing Diagrams (continued)
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit.
Figure 5. Dual Bus Mode - Staggered, CLKOUT Divide By 4
Copyright © 2010–2012, Texas Instruments Incorporated 13
Product Folder Links: ADS5400-SP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
1 0 0
9 9
9 8
9 7
9 6
9 5
9 4
9 3
9 2
9 1
9 0
8 9
8 8
8 7
8 6
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AVDD5
AVDD3
AGND
CLKINP
CLKINN
AGND
AGND
RESETN
RESETP
DVDD3
DGND
DA11P
DA11N
DA10P
DA10N
DA9P
DA9N
DA8P
DA8N
DA7P
DA7N
DGND
DVDD3
DA6P
DA6N
CLKOUTAP
CLKOUTAN
DA5P
DA5N
DA4P
DA4N
DA3P
DA3N
DA2P
DA2N
DGND
ThermalPad= AGND
AVDD3
AVDD3
AGND
AVDD5
AINN
AGND
AVDD5
AGND
AINP
AGND
AVDD5
AGND
AVDD5
VCM
AGND
VREF
AVDD5
AVDD3
AGND
ENEXTREF
ENPWD
ENA1BUS
SDO
SDIO
SCLK
SDENB
AVDD5
CLKOUTBN
CLKOUTBP
DB5N
DB5P
DB4P
DB4N
DB3P
DB3N
DB2P
DB2N
DB1P
DB1N
DVDD3
DGND
DB0P
DB0N
OVRBN
OVRBP
OVRAN
OVRAP
DA0P
DA0N
DA1P
DA1N
DVDD3
ADS5400
(TOP VIEW)
DB11N
DB11P
DB10N
DB10P
DB9N
DB9P
DB8N
DB8P
DB7N
DB7P
DB6N
DB6P
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
PIN CONFIGURATION
14 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Table 2. PIN FUNCTIONS
PIN DESCRIPTION
NAME NO.
AINP, AINN 94, 95 Analog differential input signal (positive, negative). Includes 100-Ωdifferential load on-chip.
1, 76, 86, 90, 92,
AVDD5 Analog power supply (5 V)
97, 99
AVDD3 2, 7, 9, 85 Analog power supply (3.3 V)
DVDD3 24, 38, 50, 64 Output driver power supply (3.3 V)
3, 6, 8, 84, 88, 91,
AGND Analog Ground
93, 96, 98, 100
DGND 25, 39, 51, 65 Digital Ground
CLKINP, 4, 5 Differential input clock (positive, negative). Includes 160-Ωdifferential load on-chip.
CLKINN
DA0N, DA0P 46, 47 Bus A, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
DA1N–DA10N, 48-49, 52-59, 62-63, Bus A, LVDS digital output pairs (bits 1- 10)
DA1P-DA10P 66-73
DA11N, 74, 75 Bus A, LVDS digital output pair, most-significant bit (MSB)
DA11P
CLKOUTAN, 60, 61 Bus A, Clock Output (Data ready), LVDS output pair
CLKOUTAP
DB0N, DB0P 40, 41 Bus B, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
DB1N–DB10N, 14-23, 28-37 Bus B, LVDS digital output pairs (bits 1- 10)
DB1P-DB10P
DB11N, 12, 13 Bus B, LVDS digital output pair, most-significant bit (MSB)
DB11P
CLKOUTBN, 26, 27 Bus B, Clock Output (Data ready), LVDS output pair
CLKOUTBP
OVRAN, Bus A, Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-
44, 45
OVRAP scale range. Becomes SYNCOUTA when SYNC mode is enabled in register 0x05.
OVRBN, Bus B, Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-
42, 43
OVRBP scale range. Becomes SYNCOUTB when SYNC mode is enabled in register 0x05.
Digital Reset Input, LVDS input pair. Inactive if logic low. When clocked in a high state, this is used
RESETN, for resetting the polarity of CLKOUT signal pair(s). If SYNC mode is enabled in register 0x05, this
10, 11
RESETP input also provides a SYNC time-stamp with the data sample present when RESET is clocked by
the ADC, as well as CLKOUT polarity reset. Includes 100-Ωdifferential load on-chip.
SCLK 78 Serial interface clock.
Bi-directional serial interface data in 3-pin mode (default) for programming/reading internal registers.
SDIO 79 In 4-pin interface mode (reg 0x01), the SDIO pin is an input only.
Uni-directional serial interface data in 4-pin mode (reg 0x01) provides internal register settings. The
SDO 80 SDO pin is in high-impedance state in 3-pin interface mode (default).
Active low serial data enable, always an input. Use to enable the serial interface. Internal 100kΩ
SDENB 77 pull-up resistor.
Reference voltage input (2V nominal). A 0.1μF capacitor to AGND is recommended, but not
VREF 87 required.
Enable single output bus mode (2-bus mode is default), active high. This pin is logic OR'd with addr
ENA1BUS 81(1) 0x02h bit<0>.
Enable Powerdown, active high. Places the converter into power-saving sleep mode when high. This
ENPWD 82(1) pin is logic OR'd with addr 0x05h bit<6>.
Enable External Reference Mode, active high. Device uses an external voltage reference when high.
ENEXTREF 83(1) This pin is logic OR'd with addr 0x05h bit<2>.
Analog input common mode voltage, Output (for DC-coupled applications, nominally 2.5V). A 0.1μF
VCM 89 capacitor to AGND is recommended, but not required.
(1) This pin contains an internal ~40kΩpull-down resistor, to ground.
Copyright © 2010–2012, Texas Instruments Incorporated 15
Product Folder Links: ADS5400-SP
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
SERIAL INTERFACE
The serial port of the ADS5400 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of ADS5400. It is compatible with most synchronous transfer formats and can be configured as
a 3 or 4 pin interface in register 0x01h. In both configurations, SCLK is the serial interface input clock and
SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in and data
out. For 4 pin configuration, SDIO is data in only and SDO is data out only.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,
depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle which
identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to
transfer the data. Table 3 indicates the function of each bit in the instruction cycle and is followed by a detailed
description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.
Table 3. Instruction Byte of the Serial Interface
MSB LSB
Bit 7 6 5 4 3 2 1 0
Description R/W N1 N0 A4 A3 A2 A1 A0
R/W Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from ADS5400 and a low indicates a write operation to the ADS5400.
[N1:N0] Identifies the number of data bytes to be transferred per Table 4 below. Data is transferred MSB
first.
Table 4. Number of Transferred Bytes Within One
Communication Frame
N1 N0 Description
0 0 Transfer 1 Byte
0 1 Transfer 2 Bytes
1 0 Transfer 3 Bytes
1 1 Transfer 4 Bytes
[A4:A0] Identifies the address of the register to be accessed during the read or write operation. For multi-
byte transfers, this address is the starting address. Note that the address is written to the
ADS5400 MSB first and counts down for each byte.
Figure 6 shows the serial interface timing diagram for a ADS5400 write operation. SCLK is the serial interface
clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in.
Input data to ADS5400 is clocked on the rising edges of SCLK.
16 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
SDENB
SCLK
SDIO
SDO
SDENB
SCLK
SDIO
SDO
InstructionCycle DataTransferCycle(s)
r/w N1 N0 - A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0
D7 D6 D5 D4 D3 D2 D1 D0 0
3pinConfigurationOutput
4pinConfigurationOutput
Datan Datan-1
t (Data)
d
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Figure 6. Serial Interface Write Timing Diagram
Figure 7 shows the serial interface timing diagram for a ADS5400 read operation. SCLK is the serial interface
clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in
during the instruction cycle. In 3 pin configuration, SDIO is data out from ADS5400 during the data transfer
cycle(s), while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from ADS5400 during
the data transfer cycle(s). At the end of the data transfer, SDO will output low on the final falling edge of SCLK
until the rising edge of SDENB when it will 3-state.
Figure 7. Serial Interface Read Timing Diagram
Copyright © 2010–2012, Texas Instruments Incorporated 17
Product Folder Links: ADS5400-SP
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
Serial Register Map
Table 5 gives a summary of all the modes that can be programmed through the serial interface.
Table 5. Summary of Functions Supported by Serial Interface
REGISTER
ADDRESS REGISTER FUNCTIONS
IN HEX
Address BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00 Analog Gain Adjustment bits<11:4>
3 or 4-pin
01 continued...Analog Gain Adjustment bits<3:0> SPI Reset 0 0
SPI Clock Single or Dual
02 Coarse Clock Phase Adjustment bits<4:0> 0 Divider Bus
Analog Offset
03 Fine Clock Phase Adjustment bits<5:0> 0 bit<8>
04 continued...Analog Offset Control bits<7:0>
Data Stagger
05 Temp Sensor Powerdown 1 Sync Mode Reference 0
Format Output
06 Data output mode LVDS termination LVDS current Force LVDS outputs
07 0000 0000
08 Die temperature bits<7:0>
09 000 0000 Memory error
0A 0000 0000
0B-16 addresses not implemented, writes have no effect, reads return 0x00
17 DIE ID<7:0>
18 DIE ID<15:8>
19 DIE ID<23:16>
1A DIE ID<31:24>
1B DIE ID<39:32>
1C DIE ID<47:40>
1D DIE ID<55:48>
1E DIE ID<63:56>
1F Die revision indicator<7:0>
18 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Description of Serial Registers
Each register function is explained in detail below.
Table 6. Serial Register 0x00 (Read or Write)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x00 Analog Gain Adjustment bits<11:4>
Defaults 0 0 0 0 0 0 0 0
BIT <7:0> Analog gain adjustment (most significant 8 bits of a 12 bit word)
All 12-bits in this adjustment in address 0x00 and 0x01 set to 0000
0000 0000 = fullscale analog input 2.0VPP
All 12-bits in this adjustment in address 0x00 and 0x01 set to 1111
1111 1111 = fullscale analog input 1.52VPP
Step adjustment resolution is 120µV.
Can be used for one-time setting or continual calibration of analog
signal path gain.
Table 7. Serial Register 0x01 (Read or Write)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x01 Analog Gain Adjustment bits<3:0> 3 or 4-pin SPI SPI Reset 0 0
Defaults 0 0 0 0 0 0 0 0
BIT <0:1> RESERVED
0 set to 0 if writing this register
1 do not set to 1
BIT <2> SPI Register Reset
0 altered register settings are kept
1 resets all SPI registers to defaults (self clearing)
BIT <3> Set SPI mode to 3- or 4-pin
0 3-pin SPI (read/write on SDIO, SDO not used)
1 4-pin SPI (SDIO is write, SDO is read)
BIT <7:4> Analog gain adjustment continued (least significant 4 bits of a 12-
bit word)
All 12-bits in this adjustment in address 0x00 and 0x01 set to 0000
0000 0000 = fullscale analog input 2VPP
All 12-bits in this adjustment in address 0x00 and 0x01 set to 1111
1111 1111 = fullscale analog input 1.52VPP
Step adjustment resolution is 120µV.
Can be used for one-time setting or continual calibration of analog
signal path gain.
Copyright © 2010–2012, Texas Instruments Incorporated 19
Product Folder Links: ADS5400-SP
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
Table 8. Serial Register 0x02 (Read or Write)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Single or
0x02 Coarse Clock Phase Adjustment bits<4:0> 0 Clock Divider Dual Bus
Defaults 0 0 0 0 0 0 0 0
BIT <0> Single or Dual Bus Output Selection
0 dual bus output (A and B)
1 single bus output (A)
BIT <1> Output Clock Divider
0 CLKOUT equals CLKIN divide by 4 (not available in single bus mode)
1 CLKOUT equals CLKIN divide by 2
BIT <2> RESERVED
0 set to 0 if writing this register
1 do not set to 1
BIT <7:3> Input Clock Coarse Phase Adjustment
Use as a coarse adjustment of input clock phase. The 5-bit adjustment
provides a step size of ~2.4ps across a range from code 00000 = 0 ps
to code 11111 = 73ps.
Table 9. Serial Register 0x03 (Read or Write)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Analog Offset
0x03 Fine Clock Phase Adjustment bits<5:0> 0 bit<8>
Defaults 0 0 0 0 0 0 0 factory set
BIT <0> Analog Offset control (most significant bit of 9-bit word)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000
0000 = -30mV (TBD)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111
1111 = +30mV (TBD)
Step adjustment resolution is 120µV (or 1/4 LSB). Adjustments can be
used for calibration of analog signal path offset (for instance offset
error induced outside of the ADC) or to match multiple ADC offsets.
The default setting for this register is factory set to provide ~0mV of
ADC offset in the output codes and is unique for each device.
BIT <1> RESERVED
0 set to 0 if writing this register
1 do not set to 1
BIT <7:2> Fine Clock Phase Adjustment
Use as a fine adjustment of the input clock phase. The 6-bit
adjustment provides a step resolution of ~116fs across a range from
code 000000 = 0ps to code 111111 = 7.4ps. Can be used in conjuction
with Coarse Clock Phase Adjustment in address 0x02.
20 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Table 10. Serial Register 0x04 (Read or Write)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x04 Analog Offset Control bits<7:0>
Defaults factory set
BIT <7:0> Analog Offset control continued (least significant bits of 9-bit
word)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000
0000 = -30mV (TBD)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111
1111 = +30mV (TBD)
Step adjustment resolution is 120uV (or 1/4 LSB). Adjustments can be
used for calibration of analog signal path offset (for instance offset
error induced outside of the ADC) or to match multiple ADC offsets.
The default setting for this register is factory set to provide ~0mV of
ADC offset in the output codes and is unique for each device.
Performance of the ADC is not specified across the entire offset
control range. Some performance degradation is expected as larger
offsets are programmed.
Table 11. Serial Register 0x05 (Read or Write)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Stagger
0x05 Temp Sensor Powerdown reserved Sync Mode Data Format Reference 0
Output
Defaults 0 0 1 0 0 0 0 0
BIT <0> RESERVED
0 set to 0 if writing this register
1 do not set to 1
BIT <1> Stagger Output Bus
0 Output bus A and B aligned
1 Output bus A and B staggered (see timing diagrams)
BIT <2> Enable External Reference
0 Enable internal reference
1 Enable external reference
BIT <3> Set Data Output Format
0 Enable offset binary
1 Enable two's complement
BIT <4> Set Sync Mode
0 Disable data synchronization mode
1 Enable data synchronization mode
When enabled, the OVR pin(s) are replaced with SYNC output
signal(s). The SYNC output signal is time-aligned with the output data
matching the corresponding input sample and RESET input pulse
Copyright © 2010–2012, Texas Instruments Incorporated 21
Product Folder Links: ADS5400-SP
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
BIT <5> RESERVED
0
1 set to 1 if writing this register
BIT <6> Powerdown
0 device active
1 device in low power mode (sleep mode)
BIT <7> Temperature Sensor
0 temperature sensor inactive
1 temperature sensor active, independent of powerdown bit in Bit<6>,
allows reading of temp sensor while the rest of the ADC is in sleep
mode
Table 12. Serial Register 0x06 (Read or Write)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x06 Data output mode LVDS termination LVDS current Force LVDS outputs
Defaults 0 0 0 0 0 1 0 0
BIT <0:1> Force LVDS outputs
00 and 01 normal operating mode (LVDS is outputting sampled data bits)
10 forces the LVDS outputs to all logic zeros (data and clock out) - for
level check
11 forces the LVDS outputs to all logic ones (data and clock out) - for
level check
BIT <3:2> Set LVDS output current
00 2.5mA
01 3.5mA (default)
10 4.5mA
11 5.5mA
BIT <5:4> Set Internal LVDS termination differential resistor (for LVDS
outputs only)
00 and 01 no internal termination
10 internal 200Ωresistor selected
11 internal 100Ωresistor selected
BIT <7:6> Control Data Output Mode
00 normal mode (LVDS is outputting sampled data bits)
01 scrambled output mode (D11:D1 is XOR'd with D0)
10 output data is replaced with PRBS test pattern (7-bit sequence)
11 output data is replaced with toggling test pattern (all 1s, then all 0s,
then all 1s, etc.....on all bits)
22 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Table 13. Serial Register 0x08 (Read only)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x08 Die temperature bits<7:0>
Defaults depends on reading from temperature sensor
BIT <7:0> Die temperature readout
if enabled in register 0x05. To obtain the die temperature in Celsius,
convert the 8-bit word to decimal and subtract 78.
<7:0> = 0x00 = 00000000, measured temperature is 0-78 = -78°C
<7:0> = 0x73 = 01110011, measured temperature is 115 - 78 = 37°C
<7:0> = 0xAF, measured temperature is 175 - 78 = 97°C
Table 14. Serial Register 0x09 (Read only)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x09 000 0000 Memory error
Defaults 000 0000 0
BIT <7:1> RESERVED
set to 0 if writing this register
do not set to 1
BIT <0> Memory Error Indicator
Registers 0x00 through 0x07 have multiple redundancy. If any copy
disagrees with the others, an error is flagged in this bit. This is for
systems that require the highest level of assurance that the device
remains programmed in the proper state and indication of an error if
something changes unexpectedly.
Table 15. Serial Register 0x0A (Read only)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x0A 0000 0000
Defaults 0000 0000
BIT <7:0> RESERVED
set to 0 if writing this register
do not set to 1
Copyright © 2010–2012, Texas Instruments Incorporated 23
Product Folder Links: ADS5400-SP
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
Table 16. Serial Register 0x17 through 0x1E (Read only)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x17 - 0x1E Die ID
Defaults factory set
BIT <7:0> Die Identification Bits
Each of these eight registers contains 8-bits of a 64-bit unique die
identifier.
Table 17. Serial Register 0x1F (Read only)
Address (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0x1F Die Revision Number
Defaults factory set
BIT <7:0> Die revision
Provides design revision information.
24 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
0 50 100 150 200 250 300 350 400 450 500
f-Frequency-MHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Amplitude-dB
ENOB=8.59Bits,
SFDR=57.39dBc,
SINAD=52.98dBFS,
SNR=56.02dBFS,
THD=55.96dBc
0 50 100 150 200 250 300 350 400 450 500
f-Frequency-MHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Amplitude-dB
ENOB=9.02Bits,
SFDR=61.36dBc,
SINAD=55.76dBFS,
SNR=57.39dBFS,
THD=60.81dBc
0 50 100 150 200 250 300 350 400 450 500
f-Frequency-MHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Amplitude-dB
ENOB=9.23Bits,
SFDR=66.57dBc,
SINAD=57.09dBFS,
SNR=58.46dBFS,
THD=62.76dBc
0 50 100 150 200 250 300 350 400 450 500
f-Frequency-MHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Amplitude-dB
ENOB=9.52Bits,
SFDR=71.39dBc,
SINAD=58.99dBFS,
SNR=59.40dBFS,
THD=69.44dBc
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS
Typical plots at TA= 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
FFT FOR 250-MHz INPUT SIGNAL FFT FOR 0.9-GHz INPUT SIGNAL
Figure 8. Figure 9.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE
FFT FOR 1.3-GHz INPUT SIGNAL FFT FOR 1.7-GHz INPUT SIGNAL
Figure 10. Figure 11.
Copyright © 2010–2012, Texas Instruments Incorporated 25
Product Folder Links: ADS5400-SP
-90 -80 -70 -60 -50 -40 -30 -20 -10 0
Input Amplitude-dBFS
SFDR(dBFS)
SNR(dBFS)
SFDR(dBC)
SNR(dBC)
f =801.13MHz,
f =1GSPS,
16kFFT
IN
s
-20
0
20
40
60
80
100
Performance-dB
0
20
40
60
80
100
120
-87 -77 -67 -57 -47 -37 -27 -17 -7
2F2-F1(dBFS)
2F1-F2(dBFS)
WorstSpur(dBFS)
WorstSpur(dBc)
Input Amplitude-dBFS
Performance-dB
f =1GSPS,
s
f =247.5MHz,
f =252.5MHz
IN1
IN2
0 512 1024 1536 2048 2560 3072 3584 4096
ADC Output Code
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
DNL - Differential Nonlinearity - LSB
A = -0.05 dBFS,
f = 100.33 MHz,
f = 1 GSPS
IN
IN
s
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 512 1024 1536 2048 2560 3072 3584 4096
ADC Output Code
INL - Integral Nonlinearity - LSB
A = -0.05 dBFS,
f = 100.33 MHz,
f = 1 GSPS
IN
IN
s
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Typical plots at TA= 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITY
Figure 12. Figure 13.
AC PERFORMANCE AC PERFORMANCE
vs vs
INPUT AMPLITUDE INPUT AMPLITUDE
(801.13-MHz INPUT SIGNAL) (247.5-MHz AND 252.5-MHz TWO-TONE INPUT SIGNAL)
Figure 14. Figure 15.
26 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
AV -SupplyVoltage-V
DD
T =-40°C
A
T =-20°C
A
T =85°C
AT =0°C
A
T =100°C
A
T =-55°C
A
T =25°C
A
T =125°C
A
T =55°C
A
64
66
68
70
72
74
SFDR-Spurious-FreeDynamicRange-dBc
f =100.33MHz,
f =1GSPS
IN
s
T =85°C
A
T =0°C
A
T =55°C
A
T =-20°C
AT =25°C
A
T =-55°C
A
T =100°C
A
T =125°C
A
f =100.33MHz,
f =1GSPS
IN
s
4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
AV -SupplyVoltage-V
DD
T =-40°C
A
57.5
58
58.5
59
59.5
60
SNR-Signal-to-NoiseRatio-dBFS
-87 -77 -67 -57 -47 -37 -27 -17 -7
Input Amplitude-dBFS
0
20
40
60
80
100
120
Performance-dB
f =1GSPS,
s
f =747.5MHz,
f =752.5MHz
IN1
IN2
2F2-F1(dBFS) 2F1-F2(dBFS)
WorstSpur(dBFS)
WorstSpur(dBc)
2F2-F1 (dBFS) 2F1-F2 (dBFS)
Worst Spur (dBFS)
Worst Spur (dBc)
-87 -77 -67 -57 -47 -37 -27 -17 -7
Input Amplitude - dBFS
0
20
40
60
80
100
120
AC Performance - dB
f = 1 GSPS,
s
f = 1197.5 MHz,
f = 1202.5 MHz
IN1
IN2
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Typical plots at TA= 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
AC PERFORMANCE AC PERFORMANCE
vs vs
INPUT AMPLITUDE INPUT AMPLITUDE
(747.5-MHz AND 752.5-MHz TWO-TONE INPUT SIGNAL) (1197.5-MHz AND 1202.5-MHz TWO-TONE INPUT SIGNAL)
Figure 16. Figure 17.
SFDR SNR
vs vs
AVDD5 ACROSS TEMPERATURE AVDD5 ACROSS TEMPERATURE
Figure 18. Figure 19.
Copyright © 2010–2012, Texas Instruments Incorporated 27
Product Folder Links: ADS5400-SP
3 3.1 3.2 3.3 3.4 3.5 3.6
T =85°C
A
T =0°C
A
T =55°C
A
T =-20°C
A
T =25°C
A
T =-55°C
A
T =100°C
A
T =125°C
A
DV -SupplyVoltage-V
DD
64
66
68
70
72
74
SFDR-Spurious-FreeDynamicRange-dBc
T =-40°C
A
f =100.33MHz,
f =1GSPS
IN
s
57
57.5
58
58.5
59
59.5
60
3 3.1 3.2 3.3 3.4 3.5 3.6
T =85°C
A
T =0°C
AT =55°C
A
T =-20°C
A
T =25°C
A
T =-55°C
A
T =100°C
A
T =125°C
A
f =100.33MHz,
f =1GSPS
IN
s
DV -SupplyVoltage-V
DD
SNR-Signal-to-NoiseRatio-dBFS
T =-40°C
A
57
58
59
60
61
3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 3.55 3.6
T =85°C
A
T =0°C
A
T =55°C
A
T =-20°C
A
T =25°C
A
T =-55°C
A
T =100°C
AT =125°C
A
f =100.33MHz,
f =1GSPS
IN
s
AV -SupplyVoltage-V
DD
SNR-Signal-to-NoiseRatio-dBFS
T =-40°C
A
65
67
69
71
73
75
3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 3.55 3.6
T =85°C
A
T =0°C
A
T =55°C
A
T =-20°C
A
T =25°C
A
T =-55°C
A
T =100°C
A
T =125°C
A
f =100.33MHz,
f =1GSPS
IN
s
AV -SupplyVoltage-V
DD
SFDR-Spurious-FreeDynamicRange-dBc
T =-40°C
A
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Typical plots at TA= 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
SFDR SNR
vs vs
AVDD3 ACROSS TEMPERATURE AVDD3 ACROSS TEMPERATURE
Figure 20. Figure 21.
SFDR SNR
vs vs
DVDD3 ACROSS TEMPERATURE DVDD3 ACROSS TEMPERATURE
Figure 22. Figure 23.
28 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
50-55 55-60 60-65 65-70 70-75 75-80
SFDR-dBc
200
300
400
500
600
700
800
900
1000
f -SamplingFrequency-MHz
S
f -InputFrequency-MHz
IN
50
10
100
130
170
230
250
300
350
400
450
500
550
600
650
700
750
800
900
1000
1100
1200
1300
1500
1700
1900
2100
50-52 52-54 54-56 56-58 58-60
SNR-dBFS
f -InputFrequency-MHz
IN
50
10
100
130
170
230
250
300
350
400
450
500
550
600
650
700
750
800
900
1000
1100
1200
1300
1500
1700
1900
2100
200
300
400
500
600
700
800
900
1000
f -SamplingFrequency-MHz
S
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS (continued)
Typical plots at TA= 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY
Figure 24.
SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY
Figure 25.
Copyright © 2010–2012, Texas Instruments Incorporated 29
Product Folder Links: ADS5400-SP
-12
-9
-6
-3
0
3
10M 100M 1G 5G
f - Input Frequency - Hz
IN
Normalized Gain Response - dB
f = 1 GSPS,
Measurement every 50 MHz
s
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Typical plots at TA= 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
NORMALIZED GAIN RESPONSE
vs
INPUT FREQUENCY
Figure 26.
30 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
Bipolar
Transistor
Buffer
AINP
AVDD5
AINN
AGND
ADS5400
AGND
AGND
Analog
Inputs
Bipolar
Transistor
Buffer
~0.75 pF
Package
~0.2 pF
Bondpad
~5.25 nH Bond Wire
AVDD5
~0.75 pF
Package
~0.2 pF
Bondpad
Sample and
Hold
1 Stage
Of Pipeline
st
~5.25 nH Bond Wire
2.5 V
500 W
112 W
0.3 pF
500 W
0.3 pF
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
APPLICATION INFORMATION
Theory of Operation
The ADS5400 is a 12-bit, 1-GSPS, monolithic pipeline ADC. Its bipolar transistor analog core operates from 5-V
and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible digital outputs. The
conversion process is initiated by the falling edge of the external input clock. At the sampling instant, the
differential input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially
converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block.
Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock
cycle. This process results in a data latency of 7 - 8.5 clock cycles (output mode dependent), after which the
output data is available as a 12-bit parallel word, coded in offset binary or two's complement format.
The user can select to accept the data at the full sample rate using one bus (bus A, latency 7 cycles), or
demultiplex the data into two buses (bus A and B, latency 7.5 or 8.5 cycles) at half rate. A serial peripheral
interface (SPI) is provided for adjusting operational modes, as well as for calibrations of analog gain, analog
offset and clock phase for inter-leaving multiple ADS5400. Die temperature readout using the SPI is provided.
SYNC and RESET modes exist for synchronizing output data across multiple ADS5400.
Input Configuration
The analog input for the ADS5400 consists of an analog pseudo-differential buffer followed by a bipolar transistor
track-and-hold (see Figure 27). The integrated analog buffer isolates the source driving the input of the ADC from
sampling glitches on the T&H and allows for the integration of a 100-Ωdifferential input resistor. The input
common mode is set internally through a 500-Ωresistor connected from half of the AVDD5 supply voltage to
each of the inputs. The parasitic package capacitance shown is with the package unsoldered. Once soldered,
depending on the board characteristics, one can expect another ~1pF at the analog input pins, which is board
dependent.
Figure 27. Analog Input Equivalent Circuit
For a full-scale differential input, each of the differential lines of the input signal swing symmetrically between 2.5
V + 0.5 V and 2.5 V – 0.5 V. This means that each input has a maximum signal swing of 1 VPP for a total
differential input signal swing of 2 VPP. The maximum fullscale range can be programmed from 1.5-2Vpp using
the SPI. The maximum swing is determined by the internal reference voltage generator and the fullscale range
set using the SPI, eliminating the need for any external circuitry for this purpose. The analog gain adjustment has
a resolution of 12-bits across the 1.5-2VPP range, providing for fine calibration of analog gain mismatches across
multiple ADS5400 signal chains, primarily for interleaving.
Copyright © 2010–2012, Texas Instruments Incorporated 31
Product Folder Links: ADS5400-SP
Analog Input Amplitude − dBFS
−25
−20
−15
−10
−5
0
5
10
15
20
25
−1 0 1 2 3 4 5 6
Mid-Scale Code Error − %
G023
After Positive
Over-range
1GSPS (1ns)
After Negative
Over-range
1GSPS (1ns)
After Positive
Over-range
400MSPS (2.5ns)
After Positive
Over-range
200MSPS (5ns)
After Negative
Over-range
400MSPS (2.5ns)
After Negative
Over-range
200MSPS (5ns)
R
50
0
W
Z
50
0
W
ADS5400
AIN
AIN
R
100 W
ACSignal
Source
1:1
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
The ADS5400 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 28 shows one possible configuration using an RF transformer. Datasheet performance, especially at
>1GHz input frequency, can only be obtained with a carefully designed differential drive path to the ADC.
Figure 28. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
Voltage Reference
The 2V voltage reference is provided internal to the ADS5400. A VCM (voltage common mode) pin is provided
as an output for use in dc-coupled applications, equal to the AVDD5 supply divided by 2. This provides the
analog input common mode voltage to a driving circuit so that the common mode is setup properly. Some
systems may prefer the use of an external voltage reference. This mode can be enabled by pulling the
ENEXTREF pin high. In this mode, an external reference can be driven onto the VREF pin, which is normally
expecting 2V.
Analog Input Over-Range Recovery Error
An over-range condition occurs if the analog input voltage exceeds the full-scale range of the converter (0dBFS).
To test recovery from an over-range, the ADC analog input is injected with a sinusoidal input frequency exactly at
CLKIN/4 (a four-point sinusoid at the digital outputs). The four sample points of each period occur at the top, mid-
scale, bottom and mid-scale of the sinusoid (clipped by the ADC when over-ranged to all 0s or all 1s). Once the
amplitude exceeds 0dBFS, the top and bottom of the sinusoidal input becomes out of range, while the mid-scale
point is always in-range and measureable with ADC output codes. The graph in Figure 29 indicates the amount
of error from the expected mid-scale value of 2048 that occurs after negative over-range (bottom of sinusoid) and
positive over-range (top of sinusoid). This equates to the amount of error in a valid sample 1 clock cycle after an
over-range occurs, as a function of input amplitude.
Figure 29. Recovery Error 1 Clock Cycle After Over-Range vs Input Amplitude
32 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
CLK
ADS5400
CLK
SquareWaveor
SineWave
0.01 Fm
0.01 Fm
ADS5400
AVDD5
Internal
Clock
Buffer
GND
GND
GND
AVDD5
~7.2 nH Bond Wire
~7.2 nH Bond Wire
~1.5 pF
Package
~0.2 pF
Bondpad
~1.5 pF
Package
~0.2 pF
Bondpad
400 W
AVDD5V/2
200 W
CLKINN
400 W
10 W
0.25 pF
0.25 pF
10 W
CLKINP
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Clock Inputs
The ADS5400 clock input can be driven with either a differential clock signal or a single-ended clock input. The
equivalent clock input circuit can be seen in Figure 30. In low-input-frequency applications, where jitter may not
be a big concern, the use of a single-ended clock (as shown in Figure 31) could save cost and board space
without much performance tradeoff. When clocked with this configuration, it is best to connect CLK to ground
with a 0.01-μF capacitor, while CLK is ac-coupled with a 0.01-μF capacitor to the clock source, as shown in
Figure 31.
Figure 30. Clock Input Circuit
Figure 31. Single-Ended Clock
Copyright © 2010–2012, Texas Instruments Incorporated 33
Product Folder Links: ADS5400-SP
CLK
ADS5400
CLK
0.1 Fm
Clock
Source
40
45
50
55
60
65
70
75
80
0 0.2 0.4 0.6 0.8 1 1.2
Clock Amplitude-Vp-p
f =10.05MHz
IN
f =601.13MHz
IN
f =100.33MHz
IN
f =801.13MHz
IN
f =1498.50MHz
IN
f =901.13MHz
IN
SFDR-Spurious-FreeDynamicRange-dBc
f =1GSPS
s
40
45
50
55
60
65
0 0.2 0.4 0.6 0.8 1 1.2
Clock Amplitude-Vp-p
f =10.05MHz
IN f =100.33MHz
IN f =601.13MHz
IN
f =901.13MHz
IN
f =801.13MHz
IN
f =1498.50MHz
IN
f =1GSPS
s
SNR-Signal-to-NoiseRatio-dBFS
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
Figure 32. ADS5400 SFDR vs Differential Clock Figure 33. ADS5400 SNR vs Differential Clock
Level Level
The characterization of the ADS5400 is typically performed with a 1.5 VPP differential clock, but the ADC
performs well with a differential clock amplitude down to ~400mVPP (200mV swing on both CLK and CLK), as
shown in Figure 32 and Figure 33. For jitter-sensitive applications, the use of a differential clock has some
advantages at the system level and is strongly recommended. The differential clock allows for common-mode
noise rejection at the printed circuit board (PCB) level. With a differential clock, the signal-to-noise ratio of the
ADC is better for jitter-sensitive, high-frequency applications because the board level clock jitter is superior.
Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. At
high analog input frequencies, the sampling process is sensitive to jitter. At slow clock frequencies, a small
amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR degradation due to the
uncertainty in the sampling point associated with a slow slew rate. Figure 34 demonstrates a recommended
method for converting a single-ended clock source into a differential clock; it is similar to the configuration found
on the evaluation board and was used for much of the characterization. See also Clocking High Speed Data
Converters (SLYT075) for more details.
Figure 34. Differential Clock
The common-mode voltage of the clock inputs is set internally to 2.5 V using internal 400Ωresistors (see
Figure 30). It is recommended to use ac coupling in the clock path, but if this scheme is not possible, the
ADS5400 features good tolerance to clock common-mode variation, as shown in Figure 35 and Figure 36. The
internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal
should be provided.
34 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
j =(j +j )
TOTAL ADC CLOCK
2 1/22
SNR(dBc)=-20xLOG10(2x xf xj )pIN TOTAL
Clock Common Mode − V
40
45
50
55
60
65
70
75
80
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
SFDR − Spurious-Free Dynamic Range − dBc
G016
fS = 1 GSPS
fIN = 1498.5 MHz
fIN = 601.13 MHz
fIN = 100.33 MHz fIN = 901.13 MHz
Clock Common Mode − V
40
45
50
55
60
65
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
SNR − Signal-to-Noise Ratio − dBFS
G017
fS = 1 GSPS
fIN = 1498.5 MHz
fIN = 901.13 MHz
fIN = 100.33 MHz
fIN = 601.13 MHz
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Figure 35. ADS5400 SFDR vs Clock Common Mode Figure 36. ADS5400 SNR vs Clock Common Mode
To understand how to determine the required clock jitter, an example is useful. The ADS5400 is capable of
achieving 58.7 dBFS SNR at 850 MHz of analog input frequency. To achieve SNR at 850 MHz, the external
clock source rms jitter must be at least 210fs when combined with the 125fs of internal aperture jitter in order for
the total rms jitter to be 244fs. A summary of maximum recommended rms clock jitter as a function of analog
input frequency is provided in Table 18 (using 125fs of internal aperture jitter). The equations used to create the
table are also presented.
Table 18. Recommended RMS Clock Jitter
INPUT FREQUENCY MEASURED SNR TOTAL JITTER MAXIMUM EXT CLOCK JITTER
(MHz) (dBc) (fs rms) (fs rms)
125 58.1 1585 1580
600 57.8 318 342
850 57.7 244 210
1200 56.6 196 151
1700 54.7 172 119
Equation 1 and Equation 2 are used to estimate the required clock source jitter.
(1)
(2)
where:
jTOTAL = the rms summation of the clock and ADC aperture jitter;
jADC = the ADC internal aperture jitter which is located in the data sheet;
jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
fIN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034,Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices. Recommended clock distribution chips (CDCs) are the TI CDC7005 and CDCM7005. Depending on the
jitter requirements, a band pass filter (BPF) is sometimes required between the CDC and the ADC. If the
insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the clock source amplitude is
too low to begin with, an inexpensive amplifier can be placed between the CDC and the BPF.
Copyright © 2010–2012, Texas Instruments Incorporated 35
Product Folder Links: ADS5400-SP
ADC
TI ADS5400
CLKIN
CLKIN
VCO
REF
CDC
(ClockDistributionChip)
Ex : TICDCM7005
LVPECL
or
LVCMOS
1000 MHz (To TransmitDAC)
125 MHz (ToDSP )
250 MHz (ToFPGA )
ToOther
BoardMaster
ReferenceClock
(HighorLowJitter)
10 MHz
1000 MHz
1000 MHz
LowJitterOscillator
SAW
LVPECL XFMR
AMP
Thisisageneralblockdiagramexample: ConsultthedatasheetoftheCDCM7005 forproperschematic
andforspecificationsregardingallowableinputandoutputfrequencyandamplituderanges.
AMP and /orBPFoptional , dependingonjitterrequirements
LowJitterClockDistribution
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
Figure 37 represents a scenario where an LVPECL output is used from a TI CDCM7005 with the clock signal
path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult to estimate and
requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost amplifier because of
insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter provided by the CDC
is still not adequate. The total jitter at the CDCM7005 output depends heavily on the phase noise of the VCXO
selected. If it is determined that the jitter from the CDCM7005 with a VCXO is sufficient without further
conditioning, it is possible to clock the ADS5400 directly from the CDCM7005 using differential LVPECL outputs
(see the CDCM7005 data sheet for the exact schematic). A careful analysis of the required jitter and of the
components involved is recommended before determining the proper approach.
Figure 37. Clock Source Diagram
36 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Digital Outputs
Output Bus and Clock Options
The ADS5400 has two buses, A and B. Using register 0x02, a single or dual bus output can be selected. In
single-bus mode, bus A is used at the full clock rate, while in two-bus mode, data is multiplexed at half the clock
rate on A and B. While in single bus mode, CLKOUTA will be at frequency CLKIN/2 and a DDR interface is
achieved. In two-bus mode, CLKOUTA/CLKOUTB can be either at frequency CLKIN/2 or CLKIN/4, providing
options for an SDR or DDR interface. The ADC provides 12 LVDS-compatible data outputs (D11 to D0; D11 is
the MSB and D0 is the LSB), a data-ready signal (CLKOUT), and an over-range indicator (OVR) on each bus. It
is recommended to use the CLKOUT signal to capture the output data of the ADS5400. Both two's complement
and offset binary are available output formats, in register 0x05.
The capacitive loading on the digital outputs should be minimized. Higher capacitance shortens the data-valid
timing window. The values given for timing were obtained with an estimated 3.5-pF of differential parasitic board
capacitance on each LVDS pair.
Reset and Synchronization
Referencing the timing diagrams starting in Figure 1, the polarity of CLKOUT with respect to the sample N data
output transition is undetermined because of the unknown startup logic level of the clock divider that generates
the CLKOUT signal, whether in frequency CLKIN/2 or CLKIN/4 mode. The polarity of CLKOUT could invert when
power is cycled off/on. If a defined CLKOUT polarity is required, the RESET input pins are used to reset the
clock divider to a known state after power on with a reset pulse. A RESET is not commonly required when using
only one ADS5400 because a one sample uncertainty at startup is not usually a problem.
NOTE: initial samples capture RESET = HIGH on the rising edge of CLKINP. This is being corrected for final
samples and will reflect the diagram as drawn, with RESET = HIGH captured on falling edge of CLKINP.
In addition to CLKOUT alignment using RESET, a synchronization mode is provided in register 0x05. In this
mode, the OVR output becomes the SYNCOUT. The SYNCOUT will indicate which sample was present when
the RESET input pulse was captured in a HIGH state. The OVR indicator is not available when sync mode is
enabled. In single bus mode, only SYNCOUTA is used. In dual bus mode, only SYNCOUTB is used.
LVDS
Differential source loads of 100Ωand 200Ωare provided internal to the ADS5400 and can be implemented using
register 0x06 (as well as no internal load). Normal LVDS operation expects 3.5mA of current, but alternate values
of 2.5, 4.5, and 5.5mA are provided to save power or improve the LVDS signal quality when the environment
provides excessive loading.
Over Range
The OVR output equals a logic high when the 12-bit output word attempts to exceed either all 0s or all 1s. This
flag is provided as an indicator that the analog input signal exceeded the full-scale input limit set in register 0x00
and 0x01 (± gain error). The OVR indicator is provided for systems that use gain control to keep the analog input
signal within acceptable limits. The OVR pins are not available when the sychronization mode is enabled, as they
become the SYNCOUT indicator.
Data Scramble
In normal operation, with this mode disabled, the MSBs have similar energy to the analog input fundamental
frequency and can in some instances cause board interference. A data scramble mode is available in register
0x06. In this mode, bits 11-1 are XOR'd with bit 0 (the LSB). Because of the random nature of the LSB, this has
the effect of randomizing the data pattern. To de-scramble, perform the opposite operation in the digital chip after
receiving the scrambled data.
Copyright © 2010–2012, Texas Instruments Incorporated 37
Product Folder Links: ADS5400-SP
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
Test Patterns
Determining the closure of timing or validating the digital interface can be difficult in normal operation. Therefore,
test patterns are available in register 0x06. One pattern toggles the outputs between all 1s and all 0s. Another
pattern generates a 7-bit PRBS (pseudo-random bit sequence).
In dual bus mode, the toggle mode could be in the same phase on bus A and B (bus A and B outputting 1s or 0s
together), or could be out of phase (bus A outputting 1s while bus B outputs 0s). The start phase cannot be
controlled.
The PRBS output sequence is a standard 27-1 pseudo-random sequence generated by a feedback shift register
where the two last bits of the shift register are exclusive-OR’ed and fed back to the first bit of the shift register.
The standard notation for the polynomial is x7+ x6+ 1. The PRBS generator is not reset, so there is no initial
position in the sequence. The pattern may start at any position in the repeating 127-bit long pattern and the
pattern repeats as long as the PRBS mode is enabled. The data pattern from the PRBS generator is used for all
of the LVDS parallel outputs, so when the pattern is ‘1’ then all of the LVDS outputs are outputting ‘1’ and when
the pattern is ‘0’ then all of the LVDS drivers output ‘0’. To determine if the digital interface is operating properly
with the PRBS sequence, the user must generate the same sequence in the receiving device, and do a shift-and-
compare until a matching sequence is confirmed.
Die Identification and Revision
A unique 64-bit die indentifier code can be read from registers 0x17 through 0x1E. An 8-bit die revision code is
available in register 0x1F.
Die Temperature Sensor
In register 0x05, the die temperature sensor can be enabled. The sensor is power controlled independently of
global powerdown, so that it and the SPI can be used to monitor the die temperature even when the remainder
of the ADC is in sleep mode. Register 0x08 is used to read values which can be mapped to the die temperature.
The exact mapping is detailed in the register map. Care should be taken not to exceed a maximum die
temperature of 150°C for prolonged periods of time in order to maintain the life of the device.
Interleaving
Gain Adjustment
A signal gain adjustment is available in registers 0x00 and 0x01. The allowable fullscale range for the ADC is
1.52 - 2VPP and can be set with 12-bit adjustment resolution across this range. For equal up/down gain
adjustment of the system and ADC gain mismatches, a nominal starting point of 1.75VPP could be programmed,
in which case ±250mV of adjustment range would be provided.
Offset Adjustment
Analog offset adjustment is available in register 0x03 and 0x04. This provides ±30mV of adjustment range with 9-
bit adjustment resolution of 120uV per step. At production test, the default code for this register setting is set to a
value that provides 0mV of ADC offset. For optimum spectral performance, it is not recommended to use more
than ±8mV adjustment from the default setting
Input Clock Coarse Phase Adjustment
Coarse adjustment is available in register 0x02. The typical range is approximately 73 ps with a resolution of
2.4ps.
Input Clock Fine Phase Adjustment
Fine adjustment is available in register 0x03. The typical range is approximately 7.4 ps with a resolution of 116fs.
38 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
Frequency − MHz
0
10
20
30
40
50
60
70
80
90
100
PSRR − Power Supply Rejection Ratio − dB
G022
0.01 0.1 1 10010
DVDD3
AVDD3
AVDD5
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
Power Supplies
The ADS5400 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power
supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched
supplies generate more noise components that can be coupled to the ADS5400. The PSRR value and the plot
shown in Figure 38 were obtained without bulk supply decoupling capacitors. When bulk (0.1 μF) decoupling
capacitors are used, the board-level PSRR is much higher than the stated value for the ADC. The power
consumption of the ADS5400 does not change substantially over clock rate or input frequency as a result of the
architecture and process.
Figure 38. PSRR versus Supply Injected Frequency
Copyright © 2010–2012, Texas Instruments Incorporated 39
Product Folder Links: ADS5400-SP
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
Layout Information
The evaluation board provides a guideline of how to lay out the board to obtain the maximum performance from
the ADS5400. General design rules, such as the use of multilayer boards, single ground plane for ADC ground
connections, and local decoupling ceramic chip capacitors, should be applied. The input traces should be
isolated from any external source of interference or noise, including the digital outputs as well as the clock
traces. The clock signal traces should also be isolated from other signals, especially in applications where low
jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when considering
the heat dissipation of the device. The thermal heat sink should be soldered to the board. Check with factory for
ADS5400 EVM User Guide for the evaluation board schematic.
40 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
SNR +10log10 PS
PN
ADS5400-SP
www.ti.com
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-
frequency value
Aperture Delay
The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling
occurs
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
Clock Pulse Duration/Duty Cycle
The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse
duration) to the period of the clock signal, expressed as a percentage.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. DNL is the deviation
of any single step from this ideal value, measured in units of LSB.
Common-Mode Rejection Ratio (CMRR)
CMRR measures the ability to reject signals that are presented to both analog inputs simultaneously. The
injected common-mode frequency level is translated into dBFS, the spur in the output FFT is measured in dBFS,
and the difference is the CMRR in dB.
Effective Number of Bits (ENOB)
ENOB is a measure in units of bits of a converter's performance as compared to the theoretical limit based on
quantization noise
ENOB = (SINAD – 1.76)/6.02 (3)
Gain Error
Gain error is the deviation of the ADC actual input full-scale range from its ideal value, given as a percentage of
the ideal input full-scale range.
Integral Nonlinearity (INL)
INL is the deviation of the ADC transfer function from a best-fit line determined by a least-squares curve fit of that
transfer function. The INL at each analog input value is the difference between the actual transfer function and
this best-fit line, measured in units of LSB.
Offset Error
Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode.
Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of the ability to reject frequencies present on the power supply. The injected frequency level
is translated into dBFS, the spur in the output FFT is measured in dBFS, and the difference is the PSRR in dB.
The measurement calibrates out the benefit of the board supply decoupling capacitors.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc
and in the first five harmonics.
(4)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-
scale range.
Copyright © 2010–2012, Texas Instruments Incorporated 41
Product Folder Links: ADS5400-SP
THD +10log10 PS
PD
SINAD +10log10 PS
PN)PD
ADS5400-SP
SLAS669C –SEPTEMBER 2010–REVISED AUGUST 2012
www.ti.com
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding dc.
(5)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-
scale range.
Temperature Drift
Temperature drift (with respect to gain error and offset error) specifies the change from the value at the nominal
temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters over the whole
temperature range divided by TMIN – TMAX.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to the power of the first five harmonics (PD).
(6)
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3)
IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1– f2or 2f2– f1). IMD3 is given in units of either dBc (dB to carrier) when the
absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the
fundamental is extrapolated to the converter’s full-scale range.
42 Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: ADS5400-SP
PACKAGE OPTION ADDENDUM
www.ti.com 6-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-0924001VXC ACTIVE CFP HFS 100 1 TBD Call TI Call TI -55 to 125 (5962- ~
ADS5400MHFSV)
0924001VXC
ADS5400MHFS-V
ADS5400HFS/EM PREVIEW CFP HFS 100 TBD AU N / A for Pkg Type 25 Only ADS5400HFS/EM
EVAL ONLY
ADS5400MHFSV ACTIVE CFP HFS 100 1 TBD Call TI Call TI -55 to 125 (5962- ~
ADS5400MHFSV)
0924001VXC
ADS5400MHFS-V
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Nov-2013
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5400-SP :
•Catalog: ADS5400
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated