Summary
Atmel's SAM4L series is a member of a family of Flash microcontrollers based
on the high performance 32-bit ARM Cor tex-M4 RISC processor running at fre-
quencies up to 48MHz.
The SAM4L series embeds state-of-the-ar t picoPower technology for ultra-low
power consumption. Combined power control techniques are used to bring
active current consumption down to 90µA/MHz. The device allows a wide range
of options between functionality and power consumption, giving the user the
ability to reach the lowest possible power consumption with the feature set
required for the application. The WAIT and RETENTION modes provide full logic
and RAM retention, associated with fast wake-up capability (<1.5µs) and a very
low consumption of, respectively, 3 µA and 1.5 µA. In addition, WAIT mode sup-
ports SleepWalking features. In BACKUP mode , CPU, peripherals and RAM are
powered off and, while consuming less than 0.9µA wit h external interrupt wake -
up supported.
The SAM4L series off er s a wide range of peripherals su ch as segment LCD con-
tro ller, embedded har dware ca pacitive touc h (QTouch), USB de vice & embedded
host, 128-bit AES and audio interfaces in addition to high speed serial peripher-
als such as USART, SPI and I2C. Additionally the Peripheral Event System and
SleepWalking allows the peripherals to communicate directly with each other
and make intelligent decisions and decide to wake-up the system on a qualified
events on a peripheral level; such as I2C address match or and ADC threshold.
Features
•Core
– ARM® CortexTM-M4 running at up to 48MHz
– Memory Protection Unit (MPU)
–Thumb
®-2 instruction set
•picoPower® Technology for Ultra-low Power Consumption
– Active mode downto 90µA/MHz with configurable voltage scaling
– High perform an c e and efficiency: 28 co re m a rk /mA
– Wait mode downto 3µA with fast wake-up time (<1.5µs) supporting SleepWalking
– Full RAM and Logic Retention mode downto 1.5µA with fast wake-up time (<1.5µs)
– Ultra low power Backup mode with/without RTC downto 1,5/0.9µA
•Memories
– From 128 to 512Kbytes embedded Flash, 64-bit wide access,
• 0 wait-state capability up to 24MHz
– up to 64Kbytes embedded SRAM
•System Functions
– Embedded vo ltage linear and switching regulator for single supply operation
– Two Power- on-Reset and Two Brown-out Detectors (BOD)
– Quartz or ceramic resonator oscillators: 0.6 to 30MHz main power with Failure
Detection and low power 32.768 kHz for RTC or device clock
– High precision 4/8/12MHz factory trimmed internal RC oscillator
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– High speed 80MHz internal RC oscillator
– Low power 32kHz internal RC oscillator
– PLL up to 240MHz for device cloc k and for USB 42023GS–03/2014
ATSAM---e
ARM-based
Flash MCU
SAM4L Series
Summary
2
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
– Digital Frequency Locked Loop (DFLL) with wide input range
– Up to 16 peripheral DMA (PDCA) channels
•Peripherals
– USB 2.0 Device and Embedded Host: 12 Mbps, up to 8 bidirectiona l Endpoints and Mult i-packet Ping-pong Mode. On-
Chip Transceiver
– Liquid Crystal Display (LCD) Module with Capacity up to 40 Segments and up to 4 Common Terminals
– One USART with ISO7816, IrDA®, RS-485, SPI, Manchester and LIN Mode
– Three USART with SPI Mode
– One PicoUART for extended UART wake-up capabilities in all sleep modes
– Windowed Watchdog Timer (WDT)
– Asynchronous Timer (AST) with Real-time Clock Capability, Counter or Calendar Mode Supported
– Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
– Six 16-bit Timer/Counter (TC) Channels with capture, waveform, compare and PWM mode
– One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals
– Four Master and Two Slave Two-wire Interfaces (TW I), up to 3.4Mbit/s I2C-compatible
– One Advanced Encryption System (AES) with 128-bit key length
– One 16-channel ADC 300Ksps (ADC) with up to 12 Bits Resolution
– One DAC 500Ksps (DACC) with up to 10 Bits Resolution
– Four Analog Comparators (ACIFC) with Optional Window Detection
– Capacitive Touch Module (CATB) supporting up to 32 buttons
– Audio Bitstream DAC (ABDACB) Suitable for Stereo Audio
– Inter-IC Soun d (IISC) Con troller, Compliant with Inter-IC Sound (I2S) Specification
– Peripheral Event System for Direct Peripheral to Peripheral Communication
– 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
– Random generator (TRNG)
– Parallel Capture Module (PARC)
– Glue Logic Controller (GLOC)
•I/O
– Up to 75 I/O lines with external interrupt capability (edge or level sensitivity), debo uncing, glitch filtering and slew-rate
control
– Up to Six High-drive I/O Pins
•Single 1.68-3.6V Power Supply
•Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball VFBGA, 7x7 mm, pitch 0.65 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pa d QFN 9x9 mm, pitch 0.5 mm
– 64-ball WLCSP, 4,314x4,434 mm, pitch 0.5 mm for SAM4LC4/2 and SAM4LS4/2 series
– 64-ball WLCSP, 5,270x5,194 mm, pitch 0.5 mm for SAM4LC8 and SAM4LS8 series
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm
3
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
1. Description Atmel's SAM4L series is a member of a family of Flash microcontrollers based on the high per-
formance 32 -b it ARM Cort ex -M 4 RISC processor runn in g at fr eq ue n cies up to 48MHz.
The processor implements a M emory Protection Unit (MPU) and a fast a nd flexible interru pt con-
troller for supporting modern and real-time operating systems.
The ATSAM4L8/L4/L2 embeds state-of-the-art picoPower technology for ultra-low power con-
sumption. Combined power con trol techniques are used to bring active current consumpt ion
down to 90µA/MHz. The device allows a wide range of options between functionality and power
consumption, giving the user the ability to reach the lowest possible power consumption with the
feature set required for the application. On-chip regulator improves power efficiency when used
in swichting mode with an external inductor or can be used in linear mode if application is noise
sensitive.
The ATSAM4L8/L4/L2 supports 4 power saving strategies. The SLEEP mode put the CPU in
idle mode and offers different sub-modes which automatically switch off/on bus clocks, PLL,
oscillators. The WAIT and RETENTION modes provide full logic and RAM retention, associated
with fast wake-up capability (<1.5µs) and a very low consumption of, respectively, 3 µA and 1.5
µA. In addition, WAIT mode suppo rts Sleep Walkin g feat ures. In BACKUP mode, CPU, periphe r-
als and RAM are powered off an d, while con suming less t han 0. 5µA, the device is able to wake-
up from external interrupts.
The ATSAM4L8/L4/L2 incorporates on-chip Flash tightly coupled to a low power cache
(LPCACHE) for active consumption optimization and SRAM memories for fast access.
The LCD controller is intended for monochrome passive liquid crystal display (LCD) with up to 4
Common terminals an d up to 40 Segments terminals. Ded icated Low Power Waveform, Con-
trast Control, Extended Interrupt Mode, Selectable Frame Frequency and Blink functionality are
supported to offload the CPU, reduce interrupts and reduce power consumption. The controller
includes integrated LCD bu ffers and integrated power supply voltage.
The low-power and high per forma nce capacitive t ouch module ( CATB) is int rodu ced t o meet the
demand for a low power capacitive touch solution that could be used to handle buttons, sliders
and wheels. The CATB provides excellent signal performance, as well as autonomous touch
and proximity detection for up to 32 sensors. This solution includes an advance d sequencer in
addition to an hardware filtering unit.
The Advanced Encryption Standard module (AESA) is compliant with the FIPS (Federal Infor-
mation Processing Standard) Publication 197, Advanced Encryption Standard (AES), which
specifies a symmetric block cipher that is used to encrypt and decrypt electronic data. Encryp-
tion is the transformation of a usable message, called the plaintext, into an unreadable form,
called the ciphertext. On the ot he r ha nd, decryption is the transformation that recovers the plain-
text from the ciphertext. AESA supports 128 bits cryptographic key sizes.
The Peripheral Direct Memory Access (DMA) controller enables data transfers between periph-
erals and memories without processor involvement. The Peripheral DMA controller drastically
reduces processing overhead when transferring continuous and large data streams.
The Peripheral Event System (PES) allows peripherals to receive, react to, and send peripheral
events without CPU intervention. Asynchronous interrupts allow advanced peripheral operation
in low power modes.
The Power Manager (PM) improves design flexibility and security. The Power Manager supports
SleepWalking functionality, by which a module can be selectively activated based on peripheral
4
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
events, even in sleep modes where the module clock is stopped. Power monitoring is supported
by on-chip Power-on Reset (POR18, POR33), Brown-out Detectors (BOD18, BOD33). The
device features several oscillators, such as Phase Locked Loop (PLL), Digital Frequency
Locked Loop (DFLL), Oscillator 0 (OSC0), Internal RC 4,8,12MHz osc illator (RCFAST), system
RC oscillator (RCSYS), Internal RC 80MHz, Internal 32kHz RC and 32kHz Crystal Oscillator.
Either of these oscillators can be used as source for the system clock. The DFLL is a program-
mable internal oscillator from 40 to 150MHz. It can be tuned to a high accuracy if an accurate
reference clock is running, e.g. the 32kHz crystal oscillator.
The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the so ft-
ware. This allows the device to recover from a condition that has caused the system to be
unstable.
The Asynchronous Timer (AST) combined with the 32kHz crystal oscillator supports powerful
real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in
counter or calendar mode.
The Frequency Meter (FREQM ) allows accurate mea suring of a clock freq uency by comparing it
to a known reference clock.
The Full-speed USB 2.0 device and embed ded host interface (USBC) supports several USB
classes at the same time utilizing the rich end-point configuration.
The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-
pendently programmed to perform frequency measurement, event counting, interval
measurement, pulse gen eration, delay timing, and pulse width modulation.
The ATSAM4L8/L4/L2 also features many communication interfaces, like USART, SPI, or TWI,
for communication intensive applications. The USART supports different communication modes,
like SPI Mode and LIN Mode.
A general purpose 16-channel ADC is provided, as well as four analog comparators (ACIFC).
The ADC can operate in 12-bit mode at full speed. The analog comparators can be paired to
detect when the sensing voltage is within or outside the defined reference window.
Atmel offers the QTouch Library for embedding capacitive touch buttons, sliders, and wheels
functionality. The patented charge-transfer signal acquisition offers robust sensing and includes
fully debounced reporting of touch keys as well as Adjacent Key Suppression® (AKS®) technol-
ogy for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows
you to explore, develop, and debug your own touch applications.
The Audio Bitstream DAC (ABDACB) converts a 16-bit sample value to a digital bitstream with
an average value proportional to the sample value. Two channels are supported, making the
ABDAC particularly suitable for stereo audio.
The Inter-IC Sound Controller (IISC) provides a 5-bit wide, bidirectional, synchronous, digital
audio link with external audio devices. The controller is compliant with the Inter-IC Sound (I2S)
bus specification.
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42023GS–SAM–03/2014
ATSAM4L8/L4/L2
2. Overview
2.1 Block Diagram
Figure 2-1. Block Diagram
BIASL,BIASH
CAPH,CAPL
ASYNCHRONOUS
TIMER
PERIPHERAL
DMA
CONTROLLER
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
S
MM
SM
EXTERNAL INTERRUPT
CONTROLLER
HIGH SPEED
BUS MATRIX
GENERALPURPOSE I/Os
GENERAL PURPOSE I/Os
PA
PB
PC EXTINT[8..1]
NMI
PA
PB
PC
SPI
DMA
MISO, MOSI
NPCS[3..0]
USART0
USART1
USART2
USART3
DMA
RXD
TXD
CLK
RTS, CTS
WATCHDOG
TIMER
SCK
JTAG &
Serial Wire
TDO
TDI
TMS
CONFIGURATION REGISTERS BUS
S
ARM Cortex-M4 Processor
Fmax 48 MHz
In-Circuit
Emulator
NVIC
TWI MASTER 0
TWI MASTER 1
TWI MASTER 2
TWI MASTER 3
DMA
TWI SLAVE 0
TWI SLAVE 1
DMA
RESET
CONTROLLER
SLEEP
CONTROLLER
CLOCK
CONTROLLER
TCK
TWCK
TWD
TWCK
TWD
USBC
8 EndPoints
DMA
INTER-IC SOUND
CONTROLLER
AUDIO BITSTREAM
DAC
DMA
ABDAC[1..0]
ABDACN[1..0]
ISCK
IWS
ISDI
ISDO
IMCK
CLK
M
S
DM
DP
SYSTEM CONTROL
INTERFACE
GCLK[3:0]
VDDCORE
VDDOUT
RCSYS
XIN0
XOUT0
OSC0
DFLL
RC32K
PLL
GCLK_IN[1:0]
S
MEMORY PROTECTION UNIT
Instruction/
Data System
System
TAP
HSB-PB
BRIDGE D
S
POWER MANAGER
RESETN
BACKUP
SYSTEM
CONTROL
INTERFACE
BACKUP
REGISTERS
CAPACITIVE TOUCH
MODULE
BACKUP
POWER MANAGER
LDO/
SWITCHING
REGULATOR
DMA
SENSE[69..0]
DIS
GLUE LOGIC
CONTROLLER
IN[7..0]
OUT[1..0]
TIMER/COUNTER 0
TIMER/COUNTER 1 A[2..0]
B[2..0]
CLK[2..0]
FREQUENCY METER
16-CHANNEL
12-bit ADC
INTERFACE
DMA
TRIGGER
AD[14..0]
ADVREFP
AC INTERFACE
ACREFN
ACAN[3..0]
ACAP[3..0]
HSB-PB
BRIDGE C
RCFAST PARALLEL CAPTURE
CONTROLLER
S
BACKUP DOMAIN
PCCK
DMA
32-BIT CRC
CALCULATION UNIT
VDDIN
TRUE RANDOM
GENERATOR
10-bit DAC
INTERFACE
DMA
DACOUT
PICOUARTRXD
PCEN1,PCEN2
PCDATA[7..0]
LCD
CONTROLLER
SEG[39..0]
COM[3..0]
DMA
128-bit
AES S
DMA
FLASH
CONTROLLER
LOW POWER CACHE
512/256/128 KB
FLASH
HRAM
CONTROLLER
64/32 KB
RAM
System
Management
Access Port
RC80M
XIN32
XOUT32
OSC32
PERIPHERAL EVENT CONTROLLER
PAD_EVT[3..0]
GENERIC
CLOCK
6
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
2.2 Configuration Summary
Table 2-1. Sub Series Summary
Feature ATSAM4LC ATSAM4LS
SEGMENT LCD Yes No
AESA Yes No
USB Device + Host Device Only
Table 2-2. ATSAM4LC Configuration Summary
Feature ATSAM4LC8/4/2C ATSAM4LC8/4/2B ATSAM4LC8/4/2A
Number of Pins 100 64 48
Max Frequency 48MHz
Flash 512/256/128KB
SRAM 64/32/32KB
SEGMENT LCD 4x40 4x23 4x13
GPIO 75 43 27
High-dri ve pins 6 3 1
External Interrupts 8 + 1 NMI
TWI 2 Masters + 2 Masters/Slaves 1 Master + 1
Master/Slave
USART 4 3 in LC sub series
4 in LS sub series
PICOUART 1 0
Peripheral DMA Channels 16
AESA 1
Peripheral Event System 1
SPI 1
Asynchronous Timers 1
Timer/Counter Channels 6 3
Paralle l Capture Inputs 8
Frequency Meter 1
Watchdog Timer 1
Power Manager 1
Glue Logic LUT 2 1
7
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
.
Oscillators
Digital Frequency Locked Loop 20-150MHz (DFLL)
Phase Locked Loop 48-240M Hz (PLL)
Cr ystal Oscillator 0.6-30MHz (OSC0)
Crystal Oscillator 32kHz (OSC32K)
RC Oscillator 80MHz (RC80M)
RC Oscillator 4,8,12MHz (RCFAST)
RC Oscillator 115kHz (RCSYS)
RC Oscillator 32kHz (RC32 K)
ADC 15-channel 7-channel 3-channel
DAC 1-channel
Analog Comparators 4 2 1
CATB Sensors 32 32 26
USB 1
Audio Bitstream DAC 1
IIS Controller 1
Packages TQFP/VFBGA TQFP/QFN/
WLCSP TQFP/QFN
Table 2-3. ATSAM4LS Configuration Summary
Feature ATSAM4LS8/4/2C ATSAM4LS8/4/2B ATSAM4LS8/4/2A
Number of Pins 100 64 48
Max Frequency 48MHz
Flash 512/256/128KB
SRAM 64/32/32KB
SEGMENT LCD NA
GPIO 80 48 32
High-dri ve pins 6 3 1
External Interrupts 8 + 1 NMI
TWI 2 Masters + 2 Masters/Slaves 1 Master + 1
Master/Slave
USART 4 3 in LC sub series
4 in LS sub series
PICOUART 1 0
Peripheral DMA Channels 16
AESA 1
Peripheral Event System 1
SPI 1
Asynchronous Timers 1
Table 2-2. ATSAM4LC Configuration Summary
Feature ATSAM4LC8/4/2C ATSAM4LC8/4/2B ATSAM4LC8/4/2A
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42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Timer/Counter Channels 6 3
Paralle l Capture Inputs 8
Frequency Meter 1
Watchdog Timer 1
Power Manager 1
Glue Logic LUT 2 1
Oscillators
Digital Frequency Locked Loop 20-150MHz (DFLL)
Phase Locked Loop 48-240M Hz (PLL)
Cr ystal Oscillator 0.6-30MHz (OSC0)
Crystal Oscillator 32kHz (OSC32K)
RC Oscillator 80MHz (RC80M)
RC Oscillator 4,8,12MHz (RCFAST)
RC Oscillator 115kHz (RCSYS)
RC Oscillator 32kHz (RC32 K)
ADC 15-channel 7-channel 3-channel
DAC 1-channel
Analog Comparators 4 2 1
CATB Sensors 32 32 26
USB 1
Audio Bitstream DAC 1
IIS Controller 1
Packages TQFP/VFBGA TQFP/QFN/
WLCSP TQFP/QFN
Table 2-3. ATSAM4LS Configuration Summary
Feature ATSAM4LS8/4/2C ATSAM4LS8/4/2B ATSAM4LS8/4/2A
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42023GS–SAM–03/2014
ATSAM4L8/L4/L2
3. Package and Pinout
3.1 Package
The device pins are multip lexed with peripheral f unctions as described in Sectio n 3.2 ”Per ipheral
Multiplexing on I/O lines” on page 19.
3.1.1 ATSAM4LCx Pinout
Figure 3-1. ATSAM4LC TQFP100 Pinout
PC001
PC012
PC023
PC034
PA005
PA016
GND7
VDDIO8
PC049
PC0510
PC0611
PA0212
RESET_N13
VDDCORE14
GND15
VDDOUT16
VDDIN17
TCK18
PA0319
PB0020
PB0121
PB0222
PB0323
PA0424
PA0525
XIN3226
XOUT3227
PB0428
PB0529
PA0630
PA0731
ADVREFN32
GNDANA33
ADVREFP34
VDDANA35
PC0736
PC0837
PC0938
PC1039
PC1140
PC1241
PC1342
PC1443
PA0844
PB0645
PB0746
PA0947
PA1048
PA1149
PA1250
PB1175
PB1074
PB0973
PB0872
PC2371
PC2270
PC2169
PC2068
PA1767
PA1666
PA1565
PA1464
PA1363
PC1962
PC1861
PC1760
PC1659
PC1558
VLCDIN57
GND56
BIASL55
BIASH54
VLCD53
CAPL52
CAPH51
PA18 76
PA19 77
PA20 78
PC24 79
PC25 80
PC26 81
PC27 82
PC28 83
PC29 84
PC30 85
PC31 86
VDDIO 87
VDDIO 88
PB12 89
PB13 90
PA21 91
PA22 92
PB14 93
PB15 94
PA23 95
PA24 96
VDDIO 97
PA25 98
PA26 99
GND 100
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42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Figure 3-2. ATSAM4LC VFBGA100 Pinout
1098765
4
32
1
A
B
C
D
E
F
G
H
J
K
VDD
CORE
VDDOUT
PA05 GND VDDINPA04 PC00GNDVDDIOPA02
XIN32
XOUT32PB04
PB05
PA06
PA07
GNDANA
AD
VREFP
PC07
PC08
PC09
PC10
PC11
PC12 PC13
PC14 PA08 PB06
PB07
PA09
PA10 PA11
PA12
CAPH
CAPL
VLCD BIASH
BIASL
GND VLCDIN
PC15 PC16
PC17
PC18
PC19
PA13
PA14
PA15
PA16
PA17 PC20
PC21
PC22
PC23
PB08 PB09 PB10
PB11 PA18
PA19
PA20
PC24
PC25
PC26
PC27
PC28
PC29 PC30 PC31
VDDIO
VDDIO
PB12 PB13 PA21 PA22
PB14 PB15PA23 PA24
VDDIO
PA25
PA26
GND
PC01PC02
PC03 PA00PA01
PC04 PC05
PC06
RESET_N
TCKPA03
PB00
PB01
PB02
PB03
AD
VREFN
VDDANA
11
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Figure 3-3. ATSAM4LC WLCSP64 Pinout
8765
4
32
1
A
B
C
D
E
F
G
H
CAPLPA09PB04 AD
VREFP VDDANAGNDANA PA12CAPH
XIN32
PB01VDDIN
PB03
PA05
PA04PB00
PA03
TCK
PB02
VDD
CORE
PB05
RESET_N
PA02 PB14
GND PA26 PA24
VDDIO
PA22
PA25 PA23 PB15
PA00
PA21
PA01
VDDIO PA20 PB11
PA19 PA18 PA17
PB10 PA16 VLCDIN
PB09 PA15 GND
PA14 BIASLPB08
BIASHPA13
PA11 VLCD
PA07 PB07
PA10PB06PA08XOUT32
PB12
PB13
PA06
VDDOUT
GND
12
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Figure 3-4. ATSAM4LC TQFP64/QFN64 Pinout
PA001
PA012
PA023
RESET_N4
VDDCORE5
GND6
VDDOUT7
VDDIN8
TCK9
PA0310
PB0011
PB0112
PB0213
PB0314
PA0415
PA0516
XIN3217
XOUT3218
PB0419
PB0520
PA0621
PA0722
GNDANA23
ADVREFP24
VDDANA25
PA0826
PB0627
PB0728
PA0929
PA1030
PA1131
PA1232
PB1148
PB1047
PB0946
PB0845
PA1744
PA1643
PA1542
PA1441
PA1340
VLCDIN39
GND38
BIASL37
BIASH36
VLCD35
CAPL34
CAPH33
PA18 49
PA19 50
PA20 51
VDDIO 52
PB12 53
PB13 54
PA21 55
PA22 56
PB14 57
PB15 58
PA23 59
PA24 60
VDDIO 61
PA25 62
PA26 63
GND 64
13
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Figure 3-5. ATSAM4LC TQFP48/QFN48 Pinout
PA001
PA012
PA023
RESET_N4
VDDCORE5
GND6
VDDOUT7
VDDIN8
TCK9
PA0310
PA0411
PA0512
XIN3213
XOUT3214
PA0615
PA0716
GNDANA17
ADVREFP18
VDDANA19
PA0820
PA0921
PA1022
PA1123
PA1224
PA1736
PA1635
PA1534
PA1433
PA1332
VLCDIN31
GND30
BIASL29
BIASH28
VLCD27
CAPL26
CAPH25
PA18 37
PA19 38
PA20 39
VDDIO 40
PA21 41
PA22 42
PA23 43
PA24 44
VDDIO 45
PA25 46
PA26 47
GND 48
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42023GS–SAM–03/2014
ATSAM4L8/L4/L2
3.1.2 ATSAM4LSx Pinout
Figure 3-6. ATSAM4LS TQFP100 Pinout
PC001
PC012
PC023
PC034
PA005
PA016
GND7
VDDIO8
PC049
PC0510
PC0611
PA0212
RESET_N13
VDDCORE14
GND15
VDDOUT16
VDDIN17
TCK18
PA0319
PB0020
PB0121
PB0222
PB0323
PA0424
PA0525
XIN3226
XOUT3227
PB0428
PB0529
PA0630
PA0731
ADVREFN32
GNDANA33
ADVREFP34
VDDANA35
PC0736
PC0837
PC0938
PC1039
PC1140
PC1241
PC1342
PC1443
PA0844
PB0645
PB0746
PA0947
PA1048
PA1149
PA1250
PB1175
PB1074
PB0973
PB0872
PC2371
PC2270
PC2169
PC2068
PA1767
PA1666
PA1565
PA1464
PA1363
PC1962
PC1861
PC1760
PC1659
PC1558
PA3157
PA3056
VDDIO55
GND54
PA2953
PA2852
PA2751
PA18 76
PA19 77
PA20 78
PC24 79
PC25 80
PC26 81
PC27 82
PC28 83
PC29 84
PC30 85
PC31 86
VDDIO 87
VDDIO 88
PB12 89
PB13 90
PA21 91
PA22 92
PB14 93
PB15 94
PA23 95
PA24 96
VDDIO 97
PA25 98
PA26 99
GND 100
15
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Figure 3-7. ATSAM4LS VFBGA100 Pinout
1098765
4
32
1
A
B
C
D
E
F
G
H
J
K
VDD
CORE
VDDOUT
PA05 GND VDDINPA04 PC00GNDVDDIOPA02
XIN32
XOUT32PB04
PB05
PA06
PA07
GNDANA
AD
VREFP
PC07
PC08
PC09
PC10
PC11
PC12 PC13
PC14 PA08 PB06
PB07
PA09
PA10 PA11
PA12
PA27
PA28
PA29 GND
VDDIO
PA30 PA31
PC15 PC16
PC17
PC18
PC19
PA13
PA14
PA15
PA16
PA17 PC20
PC21
PC22
PC23
PB08 PB09 PB10
PB11 PA18
PA19
PA20
PC24
PC25
PC26
PC27
PC28
PC29 PC30 PC31
VDDIO
VDDIO
PB12 PB13 PA21 PA22
PB14 PB15PA23 PA24
VDDIO
PA25
PA26
GND
PC01PC02
PC03 PA00PA01
PC04 PC05
PC06
RESET_N
TCKPA03
PB00
PB01
PB02
PB03
AD
VREFN
VDDANA
16
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Figure 3-8. ATSAM4LS WLCSP64 Pinout
17
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Figure 3-9. ATSAM4LS TQFP64/QFN64 Pinout
PA001
PA012
PA023
RESET_N4
VDDCORE5
GND6
VDDOUT7
VDDIN8
TCK9
PA0310
PB0011
PB0112
PB0213
PB0314
PA0415
PA0516
XIN3217
XOUT3218
PB0419
PB0520
PA0621
PA0722
GNDANA23
ADVREFP24
VDDANA25
PA0826
PB0627
PB0728
PA0929
PA1030
PA1131
PA1232
PB1148
PB1047
PB0946
PB0845
PA1744
PA1643
PA1542
PA1441
PA1340
PA3139
PA3038
VDDIO37
GND36
PA2935
PA2834
PA2733
PA18 49
PA19 50
PA20 51
VDDIO 52
PB12 53
PB13 54
PA21 55
PA22 56
PB14 57
PB15 58
PA23 59
PA24 60
VDDIO 61
PA25 62
PA26 63
GND 64
18
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Figure 3-10. ATSAM4LS TQFP48/QFN48 Pinout
See Section 3.3 ”Signals Description” on page 31 for a description of the various peripheral
signals.
Refer to ”Electrical Char acteristics” on page 9 9 for a description of the electrical properties of the
pin types used.
PA001
PA012
PA023
RESET_N4
VDDCORE5
GND6
VDDOUT7
VDDIN8
TCK9
PA0310
PA0411
PA0512
XIN3213
XOUT3214
PA0615
PA0716
GNDANA17
ADVREFP18
VDDANA19
PA0820
PA0921
PA1022
PA1123
PA1224
PA1736
PA1635
PA1534
PA1433
PA1332
PA3131
PA3030
VDDIO29
GND28
PA2927
PA2826
PA2725
PA18 37
PA19 38
PA20 39
VDDIO 40
PA21 41
PA22 42
PA23 43
PA24 44
VDDIO 45
PA25 46
PA26 47
GND 48
19
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
3.2 Peripheral Multiplexing on I/O lines
3.2.1 Multiplexed Signals
Each GPIO line can be a ssigned to on e of the p eripheral functions. The following tab les (Section
3-1 ”100-pin GPIO Controller Function Multiplexing” on page 19 to Section 3-4 ”48-pin GPIO
Controller Function Multiplexing” on page 28) de scribes t he p eriphe ra l signals multip lexed to the
GPIO lines.
Peripheral fun ct i on s tha t ar e no t re le va n t in som e pa rt s of th e fam ily ar e gr ey -shaded.
For description of differents Supply voltage source, refer to the Section 6. ”Power and Startup
Considerations” on page 46.
Table 3-1. 100-pin GPIO Controller Function Multiplexing (Sheet 1 of 4)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
QFN VFBGA QFN VFBGA ABCDEFG
5 B9 5 B9 PA00 0 VDDIO
6 B8 6 B8 PA01 1 VDDIO
12 A7 12 A7 PA02 2 VDDIN S CIF
GCLK0 SPI
NPCS0 C AT B
DIS
19 B3 19 B3 PA03 3 VDDIN SPI
MISO
24 A2 24 A2 PA04 4 VDDANA A D C I F E
AD0 U S A R T 0
CLK EIC
EXTINT2 G L O C
IN1 C AT B
SENSE0
25 A1 25 A1 PA05 5 VDDANA A D C I F E
AD1 U S A R T 0
RXD EIC
EXTINT3 G L O C
IN2 A D C I F E
TRIGGER CAT B
SENSE1
30 C3 30 C3 PA06 6 VDDANA DAC C
VOUT U S A R T 0
RTS EIC
EXTINT1 G L O C
IN0 AC I F C
ACAN0 C AT B
SENSE2
31 D3 31 D3 PA07 7 VDDANA A D C I F E
AD2 U S A R T 0
TXD EIC
EXTINT4 G L O C
IN3 AC I F C
ACAP0 C AT B
SENSE3
44 G2 44 G2 PA08 8 LCDA U S A R T 0
RTS T C0
A0 PEVC
PAD EVT0 G L O C
OUT0 LCDCA
SEG23 CAT B
SENSE4
47 F5 47 F5 PA09 9 LCDA U S A R T 0
CTS TC0
B0 PEVC
PAD EVT1 PA R C
PCDATA0 LCDCA
COM3 C AT B
SENSE5
48 H2 48 H2 PA10 10 LCDA U S A R T 0
CLK TC0
A1 PEVC
PAD EVT2 PA R C
PCDATA1 LCDCA
COM2 C AT B
SENSE6
49 H3 49 H3 PA11 11 LCDA U S A R T 0
RXD TC0
B1 PEVC
PAD EVT3 PA R C
PCDATA2 LCDCA
COM1 C AT B
SENSE7
50 J2 50 J2 PA12 12 LCDA U S A R T 0
TXD TC0
A2 PA RC
PCDATA3 LCDCA
COM0 C AT B
DIS
63 H5 63 H5 PA13 13 LCDA U S A R T 1
RTS T C0
B2 SPI
NPCS1 PA R C
PCDATA4 LCDCA
SEG5 CAT B
SENSE8
64 K7 64 K7 PA14 14 LCDA U S A R T 1
CLK TC0
CLK0 SP I
NPCS2 PA R C
PCDATA5 LCDCA
SEG6 CAT B
SENSE9
65 G5 65 G5 PA15 15 LCDA U S A R T 1
RXD TC0
CLK1 SP I
NPCS3 PA R C
PCDATA6 LCDCA
SEG7 CAT B
SENSE10
20
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
66 J7 66 J7 PA16 16 LCDA U S A R T 1
TXD TC0
CLK2 EI C
EXTINT1 PA RC
PCDATA7 LCDCA
SEG8 CAT B
SENSE11
67 H6 67 H6 PA17 17 LCDA U S A R T 2
RTS A B DAC B
DAC0 EI C
EXTINT2 PA RC
PCCK LCDCA
SEG9 CAT B
SENSE12
76 K10 76 K10 PA18 18 LCDA U S A R T 2
CLK A B DA C B
DACN0 EIC
EXTINT3 PA RC
PCEN1 LCDCA
SEG18 CAT B
SENSE13
77 J10 77 J10 PA19 19 LCDA U S A R T 2
RXD A B D AC B
DAC1 EI C
EXTINT4 PA RC
PCEN2 SCI F
GCLK0 LCDCA
SEG19 CAT B
SENSE14
78 H10 78 H10 PA20 20 LCDA U S A R T 2
TXD A B D AC B
DACN1 EIC
EXTINT5 G L O C
IN0 SCI F
GCLK1 LCDCA
SEG20 CAT B
SENSE15
91 E9 91 E9 PA21 21 LCDC SPI
MISO U S A R T 1
CTS EI C
EXTINT6 G L O C
IN1 T W IM 2
TWD LCDCA
SEG34 CAT B
SENSE16
92 E10 92 E10 PA22 22 LCDC SPI
MOSI U S A R T 2
CTS EI C
EXTINT7 G L O C
IN2 T W IM 2
TWCK LCDCA
SEG35 CAT B
SENSE17
95 D6 95 D6 PA23 23 LCDC SPI
SCK T W I M S 0
TWD EI C
EXTINT8 G L O C
IN3 SCI F
GCLK IN0 LCDCA
SEG38 CAT B
DIS
96 D10 96 D10 PA24 24 LCDC SPI
NPCS0 T W I M S 0
TWCK G L O C
OUT0 SCI F
GCLK IN1 LCDCA
SEG39 CAT B
SENSE18
98 D9 98 D9 PA25 25 VDDIO U S B C
DM U S A R T 2
RXD C AT B
SENSE19
99 C9 99 C9 PA26 26 VDDIO U S B C
DP U S A R T 2
TXD C AT B
SENSE20
51 K1 PA27 27 LCDA SPI
MISO II SC
ISCK A B DA C B
DAC0 G L OC
IN4 U S A R T 3
RTS C AT B
SENSE0
52 J1 PA28 28 LCDA SPI
MOSI II SC
ISDI A B DA C B
DACN0 G L O C
IN5 U S A R T 3
CTS C AT B
SENSE1
53 K2 PA29 29 LCDA SPI
SCK II SC
IWS A B DA C B
DAC1 G L OC
IN6 U S A R T 3
CLK C AT B
SENSE2
56 K4 PA30 30 LCDA SPI
NPCS0 II SC
ISDO A B DA C B
DACN1 G L O C
IN7 U S A R T 3
RXD C AT B
SENSE3
57 K5 PA31 31 LCDA SPI
NPCS1 II SC
IMCK A B DA C B
CLK G L O C
OUT1 U S A R T 3
TXD C AT B
DIS
20 J3 20 J3 PB00 32 VDDIN T W I M S 1
TWD U S A R T 0
RXD C AT B
SENSE21
21 D5 21 D5 PB01 33 VDDIN T W I M S 1
TWCK U S A R T 0
TXD EIC
EXTINT0 C AT B
SENSE22
22 E5 22 E5 PB02 34 VDDANA A D C I F E
AD3 U S A R T 1
RTS A B DAC B
DAC0 I IS C
ISCK AC I F C
ACBN0 C AT B
SENSE23
23 C4 23 C4 PB03 35 VDDANA A D C I F E
AD4 U S A R T 1
CLK A B D A C B
DACN0 I IS C
ISDI AC I F C
ACBP0 C AT B
DIS
28 C1 28 C1 PB04 36 VDDANA A D C I F E
AD5 U S A R T 1
RXD A B DA C B
DAC1 I IS C
ISDO DAC C
EXT TRIG0 C AT B
SENSE24
29 B1 29 B1 PB05 37 VDDANA A D C I F E
AD6 U S A R T 1
TXD A B DA C B
DACN1 I IS C
IMCK C AT B
SENSE25
45 G3 45 G3 PB06 38 LCDA U S A R T 3
RTS G L O C
IN4 II SC
IWS LCDCA
SEG22 CAT B
SENSE26
46 H1 46 H1 PB07 39 LCDA U S A R T 3
CTS G L O C
IN5 TC 0
A0 LCDCA
SEG21 CAT B
SENSE27
Table 3-1. 100-pin GPIO Controller Function Multiplexing (Sheet 2 of 4)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
QFN VFBGA QFN VFBGA ABCDEFG
21
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
72 G6 72 G6 PB08 40 LCDA U S A R T 3
CLK G L O C
IN6 TC 0
B0 LCDCA
SEG14 CAT B
SENSE28
73 G7 73 G7 PB09 41 LCDA U S A R T 3
RXD P E V C
PAD EVT2 G L O C
IN7 TC 0
A1 LCDCA
SEG15 CAT B
SENSE29
74 G8 74 G8 PB10 42 LCDA U S A R T 3
TXD P E V C
PAD EVT3 G L O C
OUT1 TC 0
B1 SCI F
GCLK0 LCDCA
SEG16 CAT B
SENSE30
75 K9 75 K9 PB11 43 LCDA U S A R T 0
CTS SPI
NPCS2 TC 0
A2 SCI F
GCLK1 LCDCA
SEG17 CAT B
SENSE31
89 E7 89 E7 PB12 44 LCDC U S A R T 0
RTS SPI
NPCS3 PEVC
PAD EVT0 T C0
B2 SCI F
GCLK2 LCDCA
SEG32 CAT B
DIS
90 E8 90 E8 PB13 45 LCDC U S A R T 0
CLK SP I
NPCS1 PEVC
PAD EVT1 T C0
CLK0 SCIF
GCLK3 LCDCA
SEG33 CAT B
SENSE0
93 D7 93 D7 PB14 46 LCDC U S A R T 0
RXD SPI
MISO T W I M3
TWD TC 0
CLK1 SCIF
GCLK IN0 LCDCA
SEG36 CAT B
SENSE1
94 D8 94 D8 PB15 47 LCDC U S A R T 0
TXD SPI
MOSI T W I M3
TWCK TC 0
CLK2 SCIF
GCLK IN1 LCDCA
SEG37 CAT B
SENSE2
1 A10 1 A10 PC00 64 VDDIO SPI
NPCS2 U S A R T 0
CLK TC 1
A0 C AT B
SENSE3
2 C8 2 C8 PC01 65 VDDIO SPI
NPCS3 U S A R T 0
RTS TC1
B0 C AT B
SENSE4
3 C7 3 C7 PC02 66 VDDIO SPI
NPCS1 U S A R T 0
CTS U S A R T 0
RXD TC 1
A1 C AT B
SENSE5
4 B7 4 B7 PC03 67 VDDIO SPI
NPCS0 EIC
EXTINT5 U S A R T 0
TXD TC 1
B1 C AT B
SENSE6
9 C5 9 C5 PC04 68 VDDIO SPI
MISO EIC
EXTINT6 TC1
A2 C AT B
SENSE7
10 C6 10 C6 PC05 69 VDDIO SPI
MOSI EIC
EXTINT7 TC1
B2 C AT B
DIS
11 B6 11 B6 PC06 70 VDDIO SPI
SCK EIC
EXTINT8 TC1
CLK0 C AT B
SENSE8
36 F2 36 F2 PC07 71 VDDANA A D C I F E
AD7 U S A R T 2
RTS PEVC
PAD EVT0 T C1
CLK1 C AT B
SENSE9
37 E3 37 E3 PC08 72 VDDANA A D C I F E
AD8 U S A R T 2
CLK PEVC
PAD EVT1 T C1
CLK2 U S A R T 2
CTS C AT B
SENSE10
38 F1 38 F1 PC09 73 VDDANA A D C I F E
AD9 U S A R T 3
RXD A B DA C B
DAC0 I IS C
ISCK AC I F C
ACAN1 C AT B
SENSE11
39 D4 39 D4 PC10 74 VDDANA A D C I F E
AD10 U S A R T 3
TXD A B DA C B
DACN0 I IS C
ISDI AC I F C
ACAP1 C AT B
SENSE12
40 E4 40 E4 PC11 75 VDDANA A D C I F E
AD11 U S A R T 2
RXD PEVC
PAD EVT2 C AT B
SENSE13
41 F3 41 F3 PC12 76 VDDANA A D C I F E
AD12 U S A R T 2
TXD A B DA C B
CLK II SC
IWS C AT B
SENSE14
42 F4 42 F4 PC13 77 VDDANA A D C I F E
AD13 U S A R T 3
RTS A B DAC B
DAC1 I IS C
ISDO AC I F C
ACBN1 C AT B
SENSE15
43 G1 43 G1 PC14 78 VDDANA A D C I F E
AD14 U S A R T 3
CLK A B D A C B
DACN1 I IS C
IMCK AC I F C
ACBP1 C AT B
DIS
58 J5 58 J5 PC15 79 LCDA TC 1
A0 G L O C
IN4 LCDCA
SEG0 CAT B
SENSE16
Table 3-1. 100-pin GPIO Controller Function Multiplexing (Sheet 3 of 4)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
QFN VFBGA QFN VFBGA ABCDEFG
22
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
59 J6 59 J6 PC16 80 LCDA TC 1
B0 G L O C
IN5 LCDCA
SEG1 CAT B
SENSE17
60 H4 60 H4 PC17 81 LCDA T C1
A1 G L O C
IN6 LCDCA
SEG2 CAT B
SENSE18
61 K6 61 K6 PC18 82 LCDA T C1
B1 G L O C
IN7 LCDCA
SEG3 CAT B
SENSE19
62 G4 62 G4 PC19 83 LCDA TC 1
A2 G L O C
OUT1 LCDCA
SEG4 CAT B
SENSE20
68 H7 68 H7 PC20 84 LCDA T C1
B2 LCDCA
SEG10 CAT B
SENSE21
69 K8 69 K8 PC21 85 LCDA T C1
CLK0 PA R C
PCCK LCDCA
SEG11 CAT B
SENSE22
70 J8 70 J8 PC22 86 LCDA TC 1
CLK1 PA R C
PCEN1 LCDCA
SEG12 CAT B
SENSE23
71 H8 71 H8 PC23 87 LCDA T C1
CLK2 PA R C
PCEN2 LCDCA
SEG13 CAT B
DIS
79 J9 79 J9 PC24 88 LCDB U S A R T 1
RTS EIC
EXTINT1 PEVC
PAD EVT0 PA R C
PCDATA0 LCDCA
SEG24 CAT B
SENSE24
80 H9 80 H9 PC25 89 LCDB U S A R T 1
CLK EI C
EXTINT2 PEVC
PAD EVT1 PA R C
PCDATA1 LCDCA
SEG25 CAT B
SENSE25
81 G9 81 G9 PC26 90 LCDB U S A R T 1
RXD EIC
EXTINT3 PEVC
PAD EVT2 PA R C
PCDATA2 S C IF
GCLK0 LCDCA
SEG26 CAT B
SENSE26
82 F6 82 F6 PC27 91 LCDB U S A R T 1
TXD EIC
EXTINT4 PEVC
PAD EVT3 PA R C
PCDATA3 S C IF
GCLK1 LCDCA
SEG27 CAT B
SENSE27
83 G10 83 G10 PC28 92 LCDB U S A R T 3
RXD SPI
MISO G L O C
IN4 PA RC
PCDATA4 S C IF
GCLK2 LCDCA
SEG28 CAT B
SENSE28
84 F7 84 F7 PC29 93 LCDB U S A R T 3
TXD SPI
MOSI G L O C
IN5 PA RC
PCDATA5 S C IF
GCLK3 LCDCA
SEG29 CAT B
SENSE29
85 F8 85 F8 PC30 94 LCDB U S A R T 3
RTS SPI
SCK G L O C
IN6 PA RC
PCDATA6 S C IF
GCLK IN0 LCDCA
SEG30 CAT B
SENSE30
86 F9 86 F9 PC31 95 LCDB U S A R T 3
CLK SP I
NPCS0 G L O C
OUT1 PA RC
PCDATA7 S C IF
GCLK IN1 LCDCA
SEG31 CAT B
SENSE31
Table 3-1. 100-pin GPIO Controller Function Multiplexing (Sheet 4 of 4)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
QFN VFBGA QFN VFBGA ABCDEFG
Table 3-2. 64-pin GPIO Controller Function Multiplexing (Sheet 1 of 3)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
QFP
QFN QFP
QFN ABCDEFG
11PA000VDDIO
22PA011VDDIO
3 3 PA02 2 VDDIN SC I F
GCLK0 SP I
NPCS0 C AT B
DIS
10 10 PA03 3 VDDIN SPI
MISO
23
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
15 15 PA04 4 VDDANA A D C I F E
AD0 U S A R T 0
CLK EIC
EXTINT2 G L O C
IN1 C AT B
SENSE0
16 16 PA05 5 VDDANA A D C I F E
AD1 U S A R T 0
RXD EIC
EXTINT3 G L O C
IN2 ADCIFE
TRIGGER CAT B
SENSE1
21 21 PA06 6 VDDANA DAC C
VOUT U S A R T 0
RTS E IC
EXTINT1 G L O C
IN0 AC I FC
ACAN0 C AT B
SENSE2
22 22 PA07 7 VDDANA A D C I F E
AD2 U S A R T 0
TXD EIC
EXTINT4 G L O C
IN3 AC I FC
ACAP0 C AT B
SENSE3
26 26 PA08 8 LCDA U S A R T 0
RTS T C0
A0 P E V C
PAD EVT0 G L O C
OUT0 LCDCA
SEG23 C AT B
SENSE4
29 29 PA09 9 LCDA U S A R T 0
CTS TC 0
B0 P E V C
PAD EVT1 PA R C
PCDATA0 LCDCA
COM3 C AT B
SENSE5
30 30 PA10 10 LCDA U S A R T 0
CLK TC 0
A1 P E V C
PAD EVT2 PA R C
PCDATA1 LCDCA
COM2 C AT B
SENSE6
31 31 PA11 11 LCDA U S A R T 0
RXD TC 0
B1 P E V C
PAD EVT3 PA R C
PCDATA2 LCDCA
COM1 C AT B
SENSE7
32 32 PA12 12 LCDA U S A R T 0
TXD TC 0
A2 PAR C
PCDATA3 LCDCA
COM0 C AT B
DIS
40 40 PA13 13 LCDA U S A R T 1
RTS T C0
B2 SPI
NPCS1 PAR C
PCDATA4 LCDCA
SEG5 C AT B
SENSE8
41 41 PA14 14 LCDA U S A R T 1
CLK TC 0
CLK0 SPI
NPCS2 PAR C
PCDATA5 LCDCA
SEG6 C AT B
SENSE9
42 42 PA15 15 LCDA U S A R T 1
RXD TC 0
CLK1 SPI
NPCS3 PAR C
PCDATA6 LCDCA
SEG7 C AT B
SENSE10
43 43 PA16 16 LCDA U S A R T 1
TXD TC 0
CLK2 EI C
EXTINT1 PA R C
PCDATA7 LCDCA
SEG8 C AT B
SENSE11
44 44 PA17 17 LCDA U S A R T 2
RTS A B D A C B
DAC0 EI C
EXTINT2 PA R C
PCCK LCDCA
SEG9 C AT B
SENSE12
49 49 PA18 18 LCDA U S A R T 2
CLK A B DA C B
DACN0 EIC
EXTINT3 PA R C
PCEN1 LCDCA
SEG18 C AT B
SENSE13
50 50 PA19 19 LCDA U S A R T 2
RXD A B DA C B
DAC1 EI C
EXTINT4 PA R C
PCEN2 SCI F
GCLK0 LCDCA
SEG19 C AT B
SENSE14
51 51 PA20 20 LCDA U S A R T 2
TXD A B DA C B
DACN1 EIC
EXTINT5 G L O C
IN0 SCI F
GCLK1 LCDCA
SEG20 C AT B
SENSE15
55 55 PA21 21 LCDC SPI
MISO U S A R T 1
CTS EIC
EXTINT6 G L O C
IN1 T W I M2
TWD LCDCA
SEG34 C AT B
SENSE16
56 56 PA22 22 LCDC SPI
MOSI U S A R T 2
CTS EIC
EXTINT7 G L O C
IN2 T W I M2
TWCK LCDCA
SEG35 C AT B
SENSE17
59 59 PA23 23 LCDC SPI
SCK T W I M S 0
TWD EI C
EXTINT8 G L O C
IN3 SCI F
GCLK IN0 LCDCA
SEG38 C AT B
DIS
60 60 PA24 24 LCDC SPI
NPCS0 T W I M S 0
TWCK G L O C
OUT0 S CIF
GCLK IN1 LCDCA
SEG39 C AT B
SENSE18
62 62 PA25 25 VDDIO U S B C
DM U S A R T 2
RXD C AT B
SENSE19
63 63 PA26 26 VDDIO U S B C
DP U S A R T 2
TXD C AT B
SENSE20
Table 3-2. 64-pin GPIO Controller Function Multiplexing (Sheet 2 of 3)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
QFP
QFN QFP
QFN ABCDEFG
24
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
33 PA27 27 LCDA SPI
MISO II SC
ISCK A B D AC B
DAC0 G L O C
IN4 U S A R T 3
RTS C AT B
SENSE0
34 PA28 28 LCDA SPI
MOSI II SC
ISDI A B D AC B
DACN0 G L O C
IN5 U S A R T 3
CTS C AT B
SENSE1
35 PA29 29 LCDA SPI
SCK II SC
IWS A B D AC B
DAC1 G L O C
IN6 U S A R T 3
CLK C AT B
SENSE2
38 PA30 30 LCDA SPI
NPCS0 IISC
ISDO A B D AC B
DACN1 G L O C
IN7 U S A R T 3
RXD C AT B
SENSE3
39 PA31 31 LCDA SPI
NPCS1 IISC
IMCK A B D AC B
CLK G L O C
OUT1 U S A R T 3
TXD C AT B
DIS
11 11 PB00 32 VDDIN T W I M S 1
TWD U S A R T 0
RXD C AT B
SENSE21
12 12 PB01 33 VDDIN T W I M S 1
TWCK U S A R T 0
TXD EIC
EXTINT0 C AT B
SENSE22
13 13 PB02 34 VDDANA A D C I F E
AD3 U S A R T 1
RTS A B D A C B
DAC0 IISC
ISCK AC I FC
ACBN0 C AT B
SENSE23
14 14 PB03 35 VDDANA A D C I F E
AD4 U S A R T 1
CLK A B D AC B
DACN0 II SC
ISDI AC I FC
ACBP0 C AT B
DIS
19 19 PB04 36 VDDANA A D C I F E
AD5 U S A R T 1
RXD A B D AC B
DAC1 IISC
ISDO DAC C
EXT TRIG0 CAT B
SENSE24
20 20 PB05 37 VDDANA A D C I F E
AD6 U S A R T 1
TXD A B D AC B
DACN1 II SC
IMCK C AT B
SENSE25
27 27 PB06 38 LCDA U S A R T 3
RTS G L OC
IN4 IIS C
IWS LCDCA
SEG22 C AT B
SENSE26
28 28 PB07 39 LCDA U S A R T 3
CTS G L O C
IN5 TC0
A0 LCDCA
SEG21 C AT B
SENSE27
45 45 PB08 40 LCDA U S A R T 3
CLK G L O C
IN6 TC0
B0 LCDCA
SEG14 C AT B
SENSE28
46 46 PB09 41 LCDA U S A R T 3
RXD PEVC
PAD EVT2 G L O C
IN7 TC0
A1 LCDCA
SEG15 C AT B
SENSE29
47 47 PB10 42 LCDA U S A R T 3
TXD PEVC
PAD EVT3 G L O C
OUT1 TC 0
B1 SCI F
GCLK0 LCDCA
SEG16 C AT B
SENSE30
48 48 PB11 43 LCDA U S A R T 0
CTS SP I
NPCS2 TC 0
A2 SCI F
GCLK1 LCDCA
SEG17 C AT B
SENSE31
53 53 PB12 44 LCDC U S A R T 0
RTS S PI
NPCS3 P E V C
PAD EVT0 T C0
B2 SCI F
GCLK2 LCDCA
SEG32 C AT B
DIS
54 54 PB13 45 LCDC U S A R T 0
CLK SPI
NPCS1 P E V C
PAD EVT1 T C0
CLK0 SC IF
GCLK3 LCDCA
SEG33 C AT B
SENSE0
57 57 PB14 46 LCDC U S A R T 0
RXD SPI
MISO T W IM 3
TWD TC 0
CLK1 SC IF
GCLK IN0 LCDCA
SEG36 C AT B
SENSE1
58 58 PB15 47 LCDC U S A R T 0
TXD SPI
MOSI T W IM 3
TWCK TC0
CLK2 SC IF
GCLK IN1 LCDCA
SEG37 C AT B
SENSE2
Table 3-2. 64-pin GPIO Controller Function Multiplexing (Sheet 3 of 3)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
QFP
QFN QFP
QFN ABCDEFG
25
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Table 3-3. 64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 1 of 3)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
WLCSP WLCSP ABCDEFG
G4 G4 PA00 0 VDDIO
G5 G5 PA01 1 VDDIO
F3 F3 PA02 2 VDDIN SCI F
GCLK0 SPI
NPCS0 C AT B
DIS
E2 E2 PA03 3 VDDIN SPI
MISO
D3 D3 PA04 4 VDDANA A D C I F E
AD0 U S A R T 0
CLK EI C
EXTINT2 G L O C
IN1 C AT B
SENSE0
C3 C3 PA05 5 VDDANA A D C I F E
AD1 U S A R T 0
RXD EIC
EXTINT3 G L O C
IN2 A D C I F E
TRIGGER CAT B
SENSE1
C4 C4 PA06 6 VDDANA DAC C
VOUT U S A R T 0
RTS EIC
EXTINT1 G L O C
IN0 AC I F C
ACAN0 C AT B
SENSE2
C5 C5 PA07 7 VDDANA A D C I F E
AD2 U S A R T 0
TXD EIC
EXTINT4 G L O C
IN3 AC I F C
ACAP0 C AT B
SENSE3
B4 B4 PA08 8 LCDA U S A R T 0
RTS T C0
A0 PEVC
PAD EVT0 G L O C
OUT0 LCDCA
SEG23 CAT B
SENSE4
A5 A5 PA09 9 LCDA U S A R T 0
CTS TC0
B0 PEVC
PAD EVT1 PA R C
PCDATA0 LCDCA
COM3 C AT B
SENSE5
B6 B6 PA10 10 LCDA U S A R T 0
CLK TC0
A1 PEVC
PAD EVT2 PA R C
PCDATA1 LCDCA
COM2 C AT B
SENSE6
B7 B7 PA11 11 LCDA U S A R T 0
RXD TC0
B1 PEVC
PAD EVT3 PA R C
PCDATA2 LCDCA
COM1 C AT B
SENSE7
A8 A8 PA12 12 LCDA U S A R T 0
TXD TC0
A2 PA RC
PCDATA3 LCDCA
COM0 C AT B
DIS
C7 C7 PA13 13 LCDA U S A R T 1
RTS T C0
B2 SPI
NPCS1 PA R C
PCDATA4 LCDCA
SEG5 CAT B
SENSE8
D7 D7 PA14 14 LCDA U S A R T 1
CLK TC0
CLK0 SP I
NPCS2 PA R C
PCDATA5 LCDCA
SEG6 CAT B
SENSE9
E7 E7 PA15 15 LCDA U S A R T 1
RXD TC0
CLK1 SP I
NPCS3 PA R C
PCDATA6 LCDCA
SEG7 CAT B
SENSE10
F7 F7 PA16 16 LCDA U S A R T 1
TXD TC0
CLK2 EI C
EXTINT1 PA RC
PCDATA7 LCDCA
SEG8 CAT B
SENSE11
G8 G8 PA17 17 LCDA U S A R T 2
RTS A B DAC B
DAC0 EI C
EXTINT2 PA RC
PCCK LCDCA
SEG9 CAT B
SENSE12
G7 G7 PA18 18 LCDA U S A R T 2
CLK A B DA C B
DACN0 EIC
EXTINT3 PA RC
PCEN1 LCDCA
SEG18 CAT B
SENSE13
G6 G6 PA19 19 LCDA U S A R T 2
RXD A B D AC B
DAC1 EI C
EXTINT4 PA RC
PCEN2 SCI F
GCLK0 LCDCA
SEG19 CAT B
SENSE14
H7 H7 PA20 20 LCDA U S A R T 2
TXD A B D AC B
DACN1 EIC
EXTINT5 G L O C
IN0 SCI F
GCLK1 LCDCA
SEG20 CAT B
SENSE15
H5 H5 PA21 21 LCDC S PI
MISO U S A R T 1
CTS EI C
EXTINT6 G L O C
IN1 T W IM 2
TWD LCDCA
SEG34 CAT B
SENSE16
F5 F5 PA22 22 LCDC SP I
MOSI U S A R T 2
CTS EI C
EXTINT7 G L O C
IN2 T W IM 2
TWCK LCDCA
SEG35 CAT B
SENSE17
26
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
H3 H3 PA23 23 LCDC S PI
SCK T W I M S 0
TWD EIC
EXTINT8 G L O C
IN3 SCI F
GCLK IN0 LCDCA
SEG38 CAT B
DIS
G3 G3 PA24 24 LCDC SPI
NPCS0 T W I M S 0
TWCK G L O C
OUT0 SCI F
GCLK IN1 LCDCA
SEG39 CAT B
SENSE18
H2 H2 PA25 25 VDDIO U SB C
DM U S A R T 2
RXD C AT B
SENSE19
G2 G2 PA26 26 VDDIO U S B C
DP U S A R T 2
TXD C AT B
SENSE20
A7 PA27 27 LCDA SPI
MISO II SC
ISCK A B DA C B
DAC0 G L O C
IN4 U S A R T 3
RTS C AT B
SENSE0
A6 PA28 28 LCDA SPI
MOSI II SC
ISDI A B DA C B
DACN0 G L O C
IN5 U S A R T 3
CTS C AT B
SENSE1
B8 PA29 29 LCDA SPI
SCK II SC
IWS A B DA C B
DAC1 G L O C
IN6 U S A R T 3
CLK C AT B
SENSE2
E8 PA30 30 LCDA SPI
NPCS0 II SC
ISDO A B DA C B
DACN1 G L O C
IN7 U S A R T 3
RXD CAT B
SENSE3
F8 PA31 31 LCDA SPI
NPCS1 II SC
IMCK A B DA C B
CLK G L O C
OUT1 U S A R T 3
TXD C AT B
DIS
D2 D2 PB00 32 VDDIN T W I M S 1
TWD U S A R T 0
RXD C AT B
SENSE21
C2 C2 PB01 33 VDDIN T W I M S 1
TWCK U S A R T 0
TXD EIC
EXTINT0 C AT B
SENSE22
E3 E3 PB02 34 VDDANA A D C I F E
AD3 U S A R T 1
RTS A B DAC B
DAC0 IISC
ISCK AC I F C
ACBN0 C AT B
SENSE23
B1 B1 PB03 35 VDDANA A D C I F E
AD4 U S A R T 1
CLK A B DAC B
DACN0 I IS C
ISDI AC I F C
ACBP0 C AT B
DIS
A1 A1 PB04 36 VDDANA A D C I F E
AD5 U S A R T 1
RXD A B DA C B
DAC1 IISC
ISDO DAC C
EXT TRIG0 C AT B
SENSE24
D4 D4 PB05 37 VDDANA A D C I F E
AD6 U S A R T 1
TXD A B DA C B
DACN1 I IS C
IMCK C AT B
SENSE25
B5 B5 PB06 38 LCDA U S A R T 3
RTS G L O C
IN4 II SC
IWS LCDCA
SEG22 CAT B
SENSE26
C6 C6 PB07 39 LCDA U S A R T 3
CTS G L O C
IN5 TC 0
A0 LCDCA
SEG21 CAT B
SENSE27
D6 D6 PB08 40 LCDA U S A R T 3
CLK G L O C
IN6 TC 0
B0 LCDCA
SEG14 CAT B
SENSE28
E6 E6 PB09 41 LCDA U S A R T 3
RXD P E V C
PAD EVT2 G L O C
IN7 TC 0
A1 LCDCA
SEG15 CAT B
SENSE29
F6 F6 PB10 42 LCDA U S A R T 3
TXD P E V C
PAD EVT3 G L O C
OUT1 TC0
B1 SCI F
GCLK0 LCDCA
SEG16 CAT B
SENSE30
H8 H8 PB11 43 LCDA U S A R T 0
CTS SPI
NPCS2 TC 0
A2 SCI F
GCLK1 LCDCA
SEG17 CAT B
SENSE31
D5 D5 PB12 44 LCDC U S A R T 0
RTS SPI
NPCS3 PEVC
PAD EVT0 T C0
B2 SCI F
GCLK2 LCDCA
SEG32 CAT B
DIS
Table 3-3. 64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 2 of 3)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
WLCSP WLCSP ABCDEFG
27
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
E5 E5 PB13 45 LCDC U S A R T 0
CLK SP I
NPCS1 PEVC
PAD EVT1 T C0
CLK0 SCIF
GCLK3 LCDCA
SEG33 CAT B
SENSE0
F4 F4 PB14 46 LCDC U S A R T 0
RXD SPI
MISO T W I M3
TWD TC 0
CLK1 SCIF
GCLK IN0 LCDCA
SEG36 CAT B
SENSE1
H4 H4 PB15 47 LCDC U S A R T 0
TXD SPI
MOSI T W I M 3
TWCK TC 0
CLK2 SCIF
GCLK IN1 LCDCA
SEG37 CAT B
SENSE2
Table 3-3. 64-pin GPIO Controller Function Multiplexing for WLCSP package (Sheet 3 of 3)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
WLCSP WLCSP ABCDEFG
28
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Table 3-4. 48-pin GPIO Controller Function Multiplexing (Sheet 1 of 2)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
ABCDEFG
1 1 PA00 0 VDDIO
2 2 PA01 1 VDDIO
3 3 PA02 2 VDDIN SC I F
GCLK0 SPI
NPCS0 CAT B
DIS
10 10 PA03 3 VDDIN SPI
MISO
11 11 PA04 4 VDDANA A D C I F E
AD0 U S A R T 0
CLK EIC
EXTINT2 G L O C
IN1 C AT B
SENSE0
12 12 PA05 5 VDDANA A D C I F E
AD1 U S A R T 0
RXD EIC
EXTINT3 G L O C
IN2 A D C I F E
TRIGGER C AT B
SENSE1
15 15 PA06 6 VDDANA DAC C
VOUT U S A R T 0
RTS E IC
EXTINT1 G L O C
IN0 AC IF C
ACAN0 C AT B
SENSE2
16 16 PA07 7 VDDANA A D C I F E
AD2 U S A R T 0
TXD EIC
EXTINT4 G L O C
IN3 AC IF C
ACAP0 C AT B
SENSE3
20 20 PA08 8 LCDA U S A R T 0
RTS TC0
A0 PEVC
PAD EVT0 G L O C
OUT0 L C D C A
SEG23 CAT B
SENSE4
21 21 PA09 9 LCDA U S A R T 0
CTS TC 0
B0 PEVC
PAD EVT1 PARC
PCDATA0 L C D C A
COM3 C AT B
SENSE5
22 22 PA10 10 LCDA U S A R T 0
CLK TC 0
A1 PEVC
PAD EVT2 PARC
PCDATA1 L C D C A
COM2 C AT B
SENSE6
23 23 PA11 11 LCDA U S A R T 0
RXD TC 0
B1 PEVC
PAD EVT3 PARC
PCDATA2 L C D C A
COM1 C AT B
SENSE7
24 24 PA12 12 LCDA U S A R T 0
TXD TC 0
A2 PARC
PCDATA3 L C D C A
COM0 C AT B
DIS
32 32 PA13 13 LCDA U S A R T 1
RTS TC0
B2 SPI
NPCS1 PARC
PCDATA4 L C D C A
SEG5 CAT B
SENSE8
33 33 PA14 14 LCDA U S A R T 1
CLK TC 0
CLK0 SPI
NPCS2 PARC
PCDATA5 L C D C A
SEG6 CAT B
SENSE9
34 34 PA15 15 LCDA U S A R T 1
RXD TC 0
CLK1 SPI
NPCS3 PARC
PCDATA6 L C D C A
SEG7 CAT B
SENSE10
35 35 PA16 16 LCDA U S A R T 1
TXD TC 0
CLK2 EIC
EXTINT1 PARC
PCDATA7 L C D C A
SEG8 CAT B
SENSE11
36 36 PA17 17 LCDA U S A R T 2
RTS A B DAC B
DAC0 EI C
EXTINT2 PARC
PCCK L C D C A
SEG9 CAT B
SENSE12
37 37 PA18 18 LCDA U S A R T 2
CLK A B DA C B
DACN0 EIC
EXTINT3 PARC
PCEN1 L C D C A
SEG18 CAT B
SENSE13
38 38 PA19 19 LCDA U S A R T 2
RXD A B D A C B
DAC1 EI C
EXTINT4 PARC
PCEN2 SCI F
GCLK0 L C D C A
SEG19 CAT B
SENSE14
39 39 PA20 20 LCDA U S A R T 2
TXD A B DA C B
DACN1 EIC
EXTINT5 G L O C
IN0 SCIF
GCLK1 L C D C A
SEG20 CAT B
SENSE15
41 41 PA21 21 LCDC SPI
MISO U S A R T 1
CTS EI C
EXTINT6 G L O C
IN1 T W IM 2
TWD L C D C A
SEG34 CAT B
SENSE16
42 42 PA22 22 LCDC SPI
MOSI U S A R T 2
CTS EI C
EXTINT7 G L O C
IN2 T W IM 2
TWCK L C D C A
SEG35 CAT B
SENSE17
43 43 PA23 23 LCDC SPI
SCK T W I M S 0
TWD EI C
EXTINT8 G L O C
IN3 SCIF
GCLK IN0 L C D C A
SEG38 CAT B
DIS
29
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
3.2.2 Peripheral Function s
Each GPIO line can be assigned to one of several peripheral functions. The following table
describes how the various peripheral functions are selected. The last listed function has priority
in case multiple functions ar e enabled on the same pin.
3.2.3 JTAG Port Connections
If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O
Controller configuration.
44 44 PA24 24 LCDC SPI
NPCS0 T W I M S 0
TWCK G L O C
OUT0 SCI F
GCLK IN1 L C D C A
SEG39 CAT B
SENSE18
46 46 PA25 25 VDDIO USB C
DM U S A R T 2
RXD C AT B
SENSE19
47 47 PA26 26 VDDIO USB C
DP U S A R T 2
TXD C AT B
SENSE20
25 PA27 27 LCDA SPI
MISO II SC
ISCK A B DA C B
DAC0 G L O C
IN4 U S A R T 3
RTS C AT B
SENSE0
26 PA28 28 LCDA SPI
MOSI II SC
ISDI A B DA C B
DACN0 G L O C
IN5 U S A R T 3
CTS C AT B
SENSE1
27 PA29 29 LCDA SPI
SCK IISC
IWS A B DA C B
DAC1 G L O C
IN6 U S A R T 3
CLK CAT B
SENSE2
30 PA30 30 LCDA SPI
NPCS0 II SC
ISDO A B DA C B
DACN1 G L O C
IN7 U S A R T 3
RXD C AT B
SENSE3
31 PA31 31 LCDA SPI
NPCS1 II SC
IMCK A B DA C B
CLK G L O C
OUT1 U S A R T 3
TXD CAT B
DIS
Table 3-4. 48-pin GPIO Controller Function Multiplexing (Sheet 2 of 2)
ATSAM4LC
ATSAM4LS
Pin
GPIO
Supply
GPIO Functions
ABCDEFG
Table 3-5. Peripheral Functions
Function Description
GPIO Controller Function multiplexing GPIO and GPIO peripheral selection A to H
JTAG por t connections JTAG debug port
Oscillators OSC0
Table 3-6. JTAG Pinout
48-pin
Packages 64-pin
QFP/QFN 64-pin
WLSCP 100-pin
QFN 100-ball
VFBGA Pin
Name JTAG
Pin
10 10 E2 19 B3 PA03 TMS
43 59 H3 95 D6 PA23 TDO
44 60 G3 96 D10 PA24 TDI
99F218B4TCKTCK
30
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
3.2.4 ITM Trace Conn ections
If the ITM trace is enabled, the ITM will take control over the pin PA23, irrespectively of the I/O
Controller configu ration. The Serial Wire Trace signal is available on pin PA23
3.2.5 Osc illator Pinout
The oscillators are not mapped to the normal GPIO functions and their muxings are controlled
by registers in the System Contro l Interface (SCIF) or Backup System Control Interface (BSCIF ).
Refer to the Section 15. ”System Control In terface (SCIF) ” on page 308 and Section 15. ”Backup
System Control Inter face (BSCIF)” on page 308 for more information about this.
Table 3-7. Oscillator Pinout
48-pin Packages
64-pin QFN/QFP
64-pin WLCSP
100-pin Packages
100-ball VFBGA
Pin Name Oscillator Pin
11G45B9 PA00 XIN0
13 17 B2 26 B2 XIN32 XIN32
2 2 G5 6 B8 PA01 XOUT0
14 18 B3 27 C2 XOUT32 XOUT32
31
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
3.3 Signals Description
The following table gives details on signal names classified by peripheral.
Table 3-8. Signal Descriptions List (Sheet 1 of 4)
Signal Name Function Type Active
Level Comments
Au dio Bitstream DAC - ABDACB
CLK D/A clock output Output
DAC1 - DAC0 D/A bitstream outputs Output
DACN1 - DACN0 D/A invert ed bitstream outputs Output
Analog Comparator Interface - ACIFC
ACAN1 - ACAN0 Analog Comparator A negative references Analog
ACAP1 - ACAP0 Analog Comparator A positive references Analog
ACBN1 - ACBN0 Analog Comparator B negative references Analog
ACBP1 - ACBP0 Analog Comparator B positive references Analog
ADC controller interface - ADCIFE
AD14 - AD0 Analog inputs Analog
ADVREFP Positive voltage reference Analog
TRIGGER External trigger Input
Backup System Control Interface - BSCIF
XIN32 32 kHz Crystal Oscillator Input Analog/
Digital
XOUT32 32 kHz Cr ystal Oscillator Output Analog
Capacitive Touch Module B - CATB
DIS Capacitive discharge line Output
SENSE31 - SENSE0 Capacitive sense lines I/O
DAC Controller - DACC
DAC external trigger DAC external trigger Input
DAC voltage output DAC voltage output Analog
Enhanced Debug Port For ARM Products - EDP
TCK/SWCLK JTAG / SW Debug Cloc k Input
TDI JTAG Debug Data In Input
TDO/TRACESWO JTAG Debug Data Out / SW Trace Out Output
TMS/SWDIO JTAG Debug Mode Select / SW Data I/O
External Interrupt Controller - EIC
EXTINT8 - EXTINT0 External interrupts Input
Glue Logic Con troller - GLOC
IN7 - IN0 Lookup Tables Inputs Input
OUT1 - OUT0 Lookup Tables Outputs Output
32
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Inter-IC Sound (I2S) Contro ller - IISC
IMCK I2S Master Clock Output
ISCK I2S Serial Clock I/O
ISDI I2S Serial Data In Input
ISDO I2S Serial Data Out Output
IWS I2S W ord Select I/O
LCD Controller - LCDCA
BIASL Bias voltage (1/3 VLCD) Analog
BIASH Bias voltage (2/3 VLCD) Analog
CAPH High voltage end of flying capacitor Analog
CAPL Low vo ltage end of flying capacitor Analog
COM3 - COM0 Common terminals Analog
SEG39 - SEG0 Segment terminals Analog
VLCD Bias voltage Analog
Parallel Capture - PARC
PCCK Clock Input
PCDATA7 - PCDATA0 Data lines Input
PCEN1 Data enable 1 Input
PCEN2 Data enable 2 Input
Peripheral Event Controller - PEVC
PAD_EVT3 -
PAD_EVT0 Event Inputs Input
Power Manager - PM
RESET_N Reset Input Low
System Control Interface - SCIF
GCLK3 - GCLK0 Generic Clock Outputs Output
GCLK_IN1 - GCLK_IN0 Generic Clock Inputs Input
XIN0 Crystal 0 Input Analog/
Digital
XOUT0 Crystal 0 Output Analog
Serial Peripheral Interface - SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
NPCS3 - NPCS0 SPI Peripheral Chip Selects I/O Low
SCK Clock I/O
Timer/Counter - TC0, TC1
Table 3-8. Signal Descriptions List (Sheet 2 of 4)
Signal Name Function Type Active
Level Comments
33
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
A0 Channel 0 Li n e A I/O
A1 Channel 1 Li n e A I/O
A2 Channel 2 Li n e A I/O
B0 Channel 0 Li n e B I/O
B1 Channel 1 Li n e B I/O
B2 Channel 2 Li n e B I/O
CLK0 Channel 0 External Clock Input Input
CLK1 Channel 1 External Clock Input Input
CLK2 Channel 2 External Clock Input Input
Two-wire In terface - TWIMS0, TWIMS1 , TWIM2, TWIM3
TWCK Two-wire Serial Clock I/O
TWD Two-wire Serial D ata I/O
Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3
CLK Clock I/O
CTS Clear To Send Input Low
RT S Request To Send Output Low
RXD Receive Data Input
TXD Transmit Data Output
USB 2.0 Interface - USBC
DM USB Full Speed Interface Data - I/O
DP USB Full Speed Interface Data + I/O
Power
GND Ground Ground
GNDANA Analog Ground Ground
VDDANA Analog Power Supply Power
Input 1.68V to 3.6V
VDDCORE Core Power Supply Power
Input 1.68V to 1.98V
VDDIN Voltage Regulator Input Power
Input 1.68V to 3.6V
VDDIO I/O Pads Power Supply Power
Input
1.68V to 3.6V. VDDIO must
always be equal to or lower than
VDDIN.
VDDOUT Voltage Regulator Output Power
Output 1.08V to 1.98V
General Purpose I/O
Table 3-8. Signal Descriptions List (Sheet 3 of 4)
Signal Name Function Type Active
Level Comments
34
42023GS–SAM–03/2014
ATSAM4L8/L4/L2
Note: 1. See “Power and Startup Considerations” section.
3.4 I/O Line Considerations
3.4.1 SW/JTAG Pins
The JTAG pins switch to the JTAG functions if a rising edge is detected on TCK low after the
RESET_N pin has been released. The TMS, and TDI pins have pull-up resistors when used as
JTAG pins. The TCK pin always has pull-up enabled during reset. The JTAG pins can be used
as GPIO pins and multip lexed with peripherals when the JTAG is disabled. Ref er to Section
3.2.3 ”JTAG Port Connections” on page 29 for the JTAG port connections.
For more details, refer to Section 1.1 ”Enhanced Debu g Port (EDP)” on page 3.
3.4.2 RESET_N Pin
The RESET_N pin is a schmitt input and integr ates a permanent pull-up resistor to VDDIN. As
the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in
case no reset from the system needs to be applied to the product.
3.4.3 TWI Pins
When these pins ar e u sed f or TWI , th e p ins ar e ope n-dr ain outpu ts wit h sle w-rate limitat ion and-
inputs with inputs with spike-f iltering. When u sed as GPIO-pins or used fo r other perip herals, the
pins have the same characteristics as GPIO pins.
3.4.4 GPIO Pins All the I/O lines integrate a pull-up/pull-down resistor and slew rate controller. Programming
these features is performed independently for each I/O line through the GPIO Contro llers. After
reset, I/O lines default as inputs with pull-up and pull-down resistors disabled and slew rate
enabled.
3.4.5 High-dr ive Pins
The six pins PA02, PB00, PB01, PC04, PC05 and PC06 have hig h-drive output capabilities.
Refer to Section 9.6.2 ”High-drive I/ O Pin : PA0 2, PC0 4, PC05, PC06 ” o n page 11 5 for electrical
characteristics.
3.4.6 USB Pins When these pins are used for USB, the pins are behaving according to the USB specification.
When used as GPIO pins or used for other peripherals, the pins have th e same behavior as
other normal I/O pins, but the ch aracteristics ar e different . Refer to Sectio n 9.6.3 ”USB I/O Pin :
PA25, PA26” on page 116 for electrical characteristics.
These pins are compliant to USB standard only when VDDIO power supply is 3.3V nominal.
PA31 - PA00 Parallel I/O Controller I/O Port A I/O
PB15 - PB00 Parallel I/O Con tro ller I/O Port B I/O
PC31 - PC00 Parallel I/O Controller I/O Port C I /O
Table 3-8. Signal Descriptions List (Sheet 4 of 4)
Signal Name Function Type Active
Level Comments
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3.4.7 ADC Input Pins
These pins are regular I/O pins powered from the VDDANA.
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4. Cortex-M4 processor and core peripherals
4.1 Cortex-M4 The Cortex-M4 processor is a high performance 32-bit processor designed for the microcon-
troller market. It offers significant benefits to developers, including:
•outstanding processing per formance combined with fast interrup t handling
•enhanced system debug with extensive breakpoint and trace capabilities
•efficient processor core, system and memories
•ultra-lo w power consumption with integrated sleep modes
•platform security robustness, with integrated memory protection uni t (MPU).
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor
delivers exceptional power efficiency through an efficient instruction set and extensively opti-
mized design, providing high-end processing hard ware including a range of single-cycle and
SIMD multiplication and multiply-wi th-accumulate capabilities, saturating arithmetic and dedi-
cated hardwa re divis ion .
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M4 processor implements a version of the
Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced
program memory requireme nts. The Cortex-M4 instruction set provides the exceptional perfor-
mance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit
microcontrollers.
The Cortex-M4 processor closely integrates a configurable Nested Vectored Interrupt Controller
(NVIC), to deliver industry-leading interru pt performance. The NVIC includes a non-maskable
interrupt (NMI) , an d p rovid es up to 8 0 inte rr upt p rio rity levels. Th e t igh t integ ratio n o f th e proces-
NVIC
Debug
Access
Port
Memory
protection unit
Serial
Wire
viewer
Bus matrix
Code
interface
SRAM and
peripheral interface
Data
watchpoints
Flash
patch
Cortex-M4
processor
Processor
core
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sor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically
reducing the interrupt latency. This is achieved through the hardware stacking of registers, and
the ability to suspend load-multiple and store-multiple operations. In terrupt handlers do not
require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain
optimization also significantly re duces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep mod es, that include a deep
sleep function enabling the entire device to be rapidly powered down while still retaining pro-
gram state.
4.2 System level interface
The Cortex-M4 processor provides multiple interfaces using AMBA® technology to provide high
speed, low latency memory accesses. It supports unaligned data accesses and implements
atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe
Boolean data handling.
The Cortex-M4 pr ocessor has an me mory pr otectio n unit (M PU) that provid es fine g rain me mory
control, enabling applications to utilize multiple privilege levels, separating and protecting code,
data and stack on a task-by-task basis. Such requirements are becoming critical in many
embedded applications such as automot ive.
4.3 Integrated configurable debug
The Cortex-M4 processor implements a complete hardware debug solution. This provides high
system visibility of the processor and memory through either a traditional JTAG port or a 2-pin
Serial Wire Debug (SWD) port tha t is ideal for microcon trollers and other small p ackage devices.
For system trace the processor integrates an Instrumentation Tra ce Macrocell (ITM) along side
data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system
events these generate, a Serial Wire View er (SWV) can export a stream of software-generated
messages, data trace, and profiling information through a single pin.
The Flash Patch and Breakpoint Unit (FPB) provides 8 hardware breakpoint comparators that
debuggers can use. The compar ators in the FPB also provide remap functions of up to 8 words
in the program code in the CODE memory region. This enables applications stored on a non-
erasable, ROM-base d microcontr oller to be p atched if a small p rogrammable memory, for e xam-
ple flash, is available in the device. During initialization, the application in ROM detects, from the
programmable memory, whethe r a patch is required. If a patch is required, the application pro-
grams the FPB to remap a number of addresses. When those addresses are accessed, the
accesses are redirected to a remap table specified in the FPB configuration, which means the
program in the non-modifiable ROM can be patched.
A specific Peripheral Debug (PDBG) register is implemented in the Private Peripheral Bus
address map. This register allows the user to configure the behavior of some modules in debug
mode.
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4.4 Cor tex-M4 processor fe atures and benefits summary
•tight integration of system peripherals reduces area and development costs
•Thumb instruction set combines high code density with 32-bit performance
•code-patch ability for ROM system updates
•power control optimization of system components
•integrated sleep modes for low power consumption
•fast code execution permits slow er processor clock or increases sleep mode time
•hardware division and fast digita l-signal-processing orientated multiply accumu late
•saturating arithmetic for signal processing
•deterministic, high-performance interrupt handling for time-critical applications
•memory protection uni t (MPU) for safety-critical app lications
•extensive debug and trace capabilities:
– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging,
tracing, and co de profiling.
4.5 Cortex-M4 core peripherals
These are:
Nested Vectored Interrupt Controller
The NVIC is an embedded interrupt controller that supports low latency interrupt processing.
System control block
The System cont rol block (SCB) is the programmers model interface to the processor. It pro-
vides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
System timer
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating Sys-
tem (RTOS) tick timer or as a simple counter.
Memory protection unit
The Memory protection unit (MPU) improves system reliability by defining the memory attributes
for different memo ry r eg ions. It pr ovides up to eigh t diff erent reg ions, and an op tional pr edefined
background region.
The complete Cortex-M4 User Guide can be found on the ARM web site:
http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf
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4.6 Cortex-M4 implementations options
This table provides the specific configuration options implemented in the SAM4L series
Table 4-1. Co rtex-M4 imple m en ta tio n op tio ns
4.7 Cortex-M4 Interrupts map
The table below shows how the interrupt request signals are connected to the NVIC.
Option Implementation
Inclusion of MPU yes
Inclusion of FPU No
Number of interrupts 80
Number of priority bits 4
Inclusion of the WIC No
Embedded Trace Macrocell No
Sleep mode instr uction Only WFI supported
Endianness Little Endian
Bit-banding No
SysTick timer Yes
Register reset values No
Table 4-2. Interrupt Request Signal Map (Sheet 1 of 3)
Line Module Signal
0 Flash Controller HFLASHC
1 Peripheral DMA Controller PDCA 0
2 Peripheral DMA Controller PDCA 1
3 Peripheral DMA Controller PDCA 2
4 Peripheral DMA Controller PDCA 3
5 Peripheral DMA Controller PDCA 4
6 Peripheral DMA Controller PDCA 5
7 Peripheral DMA Controller PDCA 6
8 Peripheral DMA Controller PDCA 7
9 Peripheral DMA Controller PDCA 8
10 Peripheral DMA Controller PDCA 9
11 Peripheral DMA Controller PDCA 10
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12 Peripheral DMA Controller PDCA 11
13 Peripheral DMA Controller PDCA 12
14 Peripheral DMA Controller PDCA 13
15 Peripheral DMA Controller PDCA 14
16 Peripheral DMA Controller PDCA 15
17 CRC Calculation Unit CRCCU
18 USB 2.0 Interface USBC
19 Peripheral Event Controller PEVC TR
20 Peripheral Event Controller PEVC OV
21 Advanced Encryption Standard AESA
22 Power Manager PM
23 System Control Interface SCIF
24 Frequency Meter FREQM
25 General-Purpose Input/Output Controller GPIO 0
26 General-Purpose Input/Output Controller GPIO 1
27 General-Purpose Input/Output Controller GPIO 2
28 General-Purpose Input/Output Controller GPIO 3
29 General-Purpose Input/Output Controller GPIO 4
30 General-Purpose Input/Output Controller GPIO 5
31 General-Purpose Input/Output Controller GPIO 6
32 General-Purpose Input/Output Controller GPIO 7
33 General-Purpose Input/Output Controller GPIO 8
34 General-Purpose Input/Output Controller GPIO 9
35 General-Purpose Input/Output Controller GPIO 10
36 General-Purpose Input/Output Controller GPIO 11
37 Backup Power Manager BPM
38 Backup System Control Interface BSCIF
39 Asynchronous Timer AST ALARM
40 Asynchronous Timer AST PER
41 Asynchronous Timer AST OVF
42 Asynchronous Timer AST READY
43 Asynchronous Timer AST CLKREADY
44 Watchdog Timer WDT
45 External Interrupt Controller EIC 1
46 External Interrupt Controller EIC 2
47 External Interrupt Controller EIC 3
Table 4-2. Interrupt Request Signal Map (Sheet 2 of 3)
Line Module Signal
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48 External Interrupt Controller EIC 4
49 External Interrupt Controller EIC 5
50 External Interrupt Controller EIC 6
51 External Interrupt Controller EIC 7
52 External Interrupt Controller EIC 8
53 Inter-IC Sound (I2S) Controller IISC
54 Serial Peripheral Interface SPI
55 Timer/Counter TC00
56 Timer/Counter TC01
57 Timer/Counter TC02
58 Timer/Counter TC10
59 Timer/Counter TC11
60 Timer/Counter TC12
61 Two-wire Master Interface TWIM0
62 Two-wire Slave Interface TWIS0
63 Two-wire Master Interface TWIM1
64 Two-wire Slave Interface TWIS1
65 Universal Synchronous Asynchronous
Receiver Transmitter USART0
66 Universal Synchronous Asynchronous
Receiver Transmitter USART1
67 Universal Synchronous Asynchronous
Receiver Transmitter USART2
68 Universal Synchronous Asynchronous
Receiver Transmitter USART3
69 ADC controller interface ADCIFE
70 DAC Controller DACC
71 Analog Comparator Interface ACIFC
72 Audio Bitstream DAC ABDACB
73 True Random Number Generator TRNG
74 Paralle l Capture PARC
75 Capacitive Touch Module B CATB
77 Two-wire Master Interface TWIM2
78 Two-wire Master Interface TWIM3
79 LCD Controller A LCDCA
Table 4-2. Interrupt Request Signal Map (Sheet 3 of 3)
Line Module Signal
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4.8 Peripheral Debug
The PDBG register controls the behavior of asynchronous peripherals when the device is in
debug mode.When the corresponding bit is set, that peripheral will be in a frozenstate in debug
mode.
4.8.1 Peripheral Debug
Name: PDBG
Access Type: Read/Write
Address: 0xE0042000
Reset Value: 0x00000000
• WDT: Watchdog PDBG bit
WDT = 0: The WDT counter is not frozen during debug operation.
WDT = 1: The WDT counter is frozen during debug operation when Core is halted
• AST: Asynchronous Timer PDBG bit
AST = 0: The AST prescaler and counter is not frozen during debug operation.
AST = 1: The AST prescaler and counter is frozen during debug operation when Core is halted.
• PEVC: PEVC PDBG bit
PEVC= 0: PEVC is not frozen during debug operation.
PEVC= 1: PEVC is frozen during debug operation when Core is halted.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - - PEVC AST WDT
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5. Memories
5.1 Product Mapping
Figure 5-1. ATSAM4L8/L4/L2 Pro duct Mapping
System
Reserved
Reserved
HRAMC1
Global Memory Space
Peripherals
Code
Internal Flash
Reserved
0x00000000
0x00800000
0x1FFFFFFF
Code
SRAM
Undefined
Peripherals
Reserved
0x00000000
0x20000000
0x40000000
0x60000000
0xFFFFFFFF
0x22000000
0x5FFFFFFF
SRAM
HRAMC0
Reserved
0x20000000
0x20010000
0x21000000
0x210007FF
0x21FFFFFF
Peripheral
Bridge A
Reserved
Peripheral
Bridge B
Peripheral
Bridge C
Peripheral
Bridge D
AESA
0x400E0000
0x400F0000
0x40100000
0x400B0000
0x400A0000
0x40000000
0x400B0100
System Controller
TWIM2
CATB
DACC
Reserved
Reserved
I2SC
SPI
Reserved
TC0
TC1
TWIMS0
TWIMS1
USART0
USART1
USART2
USART3
Reserved
ADCIFE
ACIFC
Reserved
GLOC
ABDACB
TRNG
PARC
Reserved
0x40000000
0x40004000
0x40008000
0x4000C000
0x40010000
0x40014000
0x40018000
0x4001C000
0x40020000
0x40024000
0x40028000
0x4002C000
0x40030000
0x40034000
0x40038000
0x4003C000
0x40040000
0x40044000
0x40060000
0x40064000
0x40068000
0x4006C000
0x40070000
0x40074000
0x40078000
TWIM3
0x4007C000
0x40080000
LCDCA
Reserved
0x40084000
0x4009FFFF
PICOUART
Peripheral Bridge C
PM
SCIF
CHIPID
FREQM
GPIO
Reserved
BPM
BSCIF
AST
WDT
EIC
Reserved
0x400E0000
0x400E0740
0x400E0800
0x400E0C00
0x400E1000
0x400E1800
0x400F0000
0x400F0400
0x400F0800
0x400F0C00
0x400F1000
0x400F1400
Peripheral Bridge D
0x400FFFFF
0x400F1800
0x400EFFFF
Peripheral Bridge B
FLASHCALW
HMATRIX
SMAP
CRCCU
PICOCACHE
Reserved
0x400A0000
0x400A0400
0x400A1000
0x400A2000
0x400A3000
0x400A4000
0x400A5000
PDCA
USBC
PEVC
0x400A6000
0x400A6400
0x400AFFFF
Peripheral Bridge A
ITM
DWT
FPB
Reserved
SCS
Reserved
TPIU
Reserved
External PPB
ROM Table
0xE0000000
0xE0000000
0xE0001000
0xE0002000
0xE0003000
0xE000E000
0xE000F000
0xE0040000
0xE0041000
0xE0042000
0xE00FF000
0xE0100000
Reserved
0xFFFFFFFF
System
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5.2 Embedded Memories
•Internal high-speed flash
– 512Kbytes (ATSAM4Lx8)
– 256Kbytes (ATSAM4Lx4)
– 128Kbytes (ATSAM4Lx2)
• Pipelined flash architecture, allowing burst reads from sequential flash locations, hidin g
penalty of 1 wait state access
• Pipelined flash architecture typically reduces the cycle penalty of 1 wait state operation
compared to 0 wait state operation
• 100 000 write cycles, 15-year data retention capability
• Sector lock capabilities, bootloader protection, security bit
• 32 fuses, erased during chip erase
• User page for data to be preserved during chip erase
•Internal high-speed SRAM, single-cycle access at full speed
– 64Kbytes (ATSAM4Lx8)
– 32Kbytes (ATSAM4Lx4, ATSAM4Lx2)
5.3 Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remap ped in any way, not even during boot. Th e 32-bit physical address spac e is
mapped as follows:
Table 5-1. ATSAM4L8/L4/L2 Physical Memory Map
Memory Start Address Size Size
ATSAM4Lx4 ATSAM4Lx2
Embedded Flash 0x00000000 25 6Kbytes 128Kbytes
Embedded SRAM 0x20000000 32Kbytes 32Kbytes
Cache SRAM 0x21000000 4Kbytes 4Kbytes
Peripheral Br idge A 0x40000000 64Kbytes 64Kbytes
Peripheral Bridge B 0x400A0000 64Kbytes 64Kbytes
AESA 0x400B0000 256 bytes 256 bytes
Peripheral Bridge C 0x400E0000 64Kbytes 64Kbytes
Peripheral Bridge D 0x400F0000 64Kbytes 64Kbytes
Memory Start Address Size
ATSAM4Lx8
Embedded Flash 0x00000000 51 2Kbytes
Embedded SRAM 0x20000000 64Kbytes
Cache SRAM 0x21000000 4Kbytes
Peripheral Bridge A 0x40000000 64Kbytes
Peripheral Br idge B 0x400A0000 64Kbytes
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AESA 0x400B0000 256 bytes
Peripheral Br idge C 0x400E0000 64Kbytes
Peripheral Bridge D 0x400F0000 64Kbytes
Memory Start Address Size
ATSAM4Lx8
Table 5-2. Flash Memory Parameters
Device Flash Size (FLASH_PW) Number of Pages (FLASH_P)Page Size (FLASH_W)
ATSAM4Lx8 512Kbytes 1024 512 bytes
ATSAM4Lx4 256Kbytes 512 512 bytes
ATSAM4Lx2 128Kbytes 256 512 bytes
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6. Power and Startup Considerations
6.1 Power Domain Overview
Figure 6-1. ATSAM4LS Power Domain Diagram
ASYNCHRONOUS TIMER
EXTERNAL INTERRUPT
CONTROLLER
WATCHDOG
TIMER
BACKUP
POWER MANAGER
BACKUP SYSTEM
CONTROL INTERFACE
OSC32K
RC32K
BACKUP
REGISTERS
SYSTEM
CONTROL INTERFACE
POWER MANAGER FREQUENCY
METER
GPIO
POR33
BOD33
BOD18
STARTUP
LOGIC
POR18
PLL
DFLL
RCSYS
PERIPHERAL BRIDGE C
PERIPHERALS
PERIPHERAL BRIDGE A
AHB PERIPHERALS
PERIPHERAL BRIDGE B
BUS MATRIX
CORTEX M4
CPU
FLASHPDCA RAM
PERIPHERAL BRIDGE D
CORE DOMAIN
VDDANA DOMAIN
BACKUP DOMAIN
VDDANA GNDANA
MPOSC
AD0-AD14
ADVREF
AC0A-AC3A
AC0B-AC3B
XIN32
XOUT32
EXTINT0-EXTINT8
USBC
ANALOG
COMPARATORS
ADC
RCFAST
RC80M
VDDIN
GND
VDDOUT
VDDCORE
DUAL OUTPUT
TRIMMABLE
VOLTAGE
REGULATOR
BUCK/LDOn
(PA02)
DAC
DACOUT
VDDIO GND
VDDIO DOMAIN
GPIOs
USB
PADS
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Figure 6-2. ATSAM4LC Power Domain Diagram
ASYNCHRONOUS TIMER
EXTERNAL INTERRUPT
CONTROLLER
WATCHDOG
TIMER
BACKUP
POWER MANAGER
BACKUP SYSTEM
CONTROL INTERFACE
OSC32K
RC32K
BACKUP
REGISTERS
SYSTEM
CONTROL INTERFACE
POWER MANAGER FREQUENCY
METER
GPIO
POR33
BOD33
BOD18
STARTUP
LOGIC
POR18
PLL
DFLL
RCSYS
PERIPHERAL BRIDGE C
PERIPHERALS
PERIPHERAL BRIDGE A
AHB PERIPHERALS
PERIPHERAL BRIDGE B
BUS MATRIX
CORTEX M4
CPU
FLASHPDCA RAM
PERIPHERAL BRIDGE D
CORE DOMAIN
VDDANA DOMAIN
BACKUP DOMAIN
VDDANA GNDANA
MPOSC
AD0-AD14
ADVREF
AC0A-AC3A
AC0B-AC3B
XIN32
XOUT32
EXTINT0-EXTINT8
USBC
ANALOG
COMPARATORS
ADC
RCFAST
RC80M
VDDIN
GND
VDDOUT
VDDCORE
DUAL OUTPUT
TRIMMABLE
VOLTAGE
REGULATOR
BUCK/LDOn
(PA02)
DAC
DACOUT
VLCDIN GND
LCDA DOMAIN
GPIOs
LCD
VPUMP
CAPH
CAPL
BIASH
BIASL
VLCD
VDDIO
LCDB DOMAIN
GPIOs
VDDIO
GPIOs
LCDC DOMAIN
VDDIO GND
VDDIO DOMAIN
GPIOs
USB
PADS
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6.2 Power Supplies
The ATSAM4L8/L4/L2 has several types of power supply pins:
• VDDIO: Powers I/O lines, the general purpose oscillator (OSC), the 80MHz integrated RC
oscillator (RC80M) . Voltage is 1.68V to 3.6V.
• VLCDIN: (ATSAM4LC only) Powers the LCD voltage pump. Voltage is 1.68V to 3.6V.
• VDDIN: Powers the int ernal voltage regulator. Voltage is 1.68V to 3.6V.
• VDDANA: Pow ers the ADC, the DAC, the Analog Comparators, the 32kHz oscillator
(OSC32K), the 32kHz integrated RC oscillator (RC32K)and the Brown-out detectors (BOD18
and BOD33). Voltage is 1.68V to 3.6V nominal.
• VDDCORE: Powers the core, memories, peripherals, the PLL, the DFLL, the 4MHz
integrated RC oscillator (RCFAST) and the 115kHz integrated RC oscillator (RCSYS).
– VDDOUT is the output voltage of the regulator and must be connected with or
without an inductor to VDDCORE.
The ground pins GND are common to VDDCORE, VDDIO, and VDDIN. The ground pin for
VDDANA is GNDANA.
For decoupling recommendations for the different power supplies, refer to the schematic
document.
6.2.1 Voltage Regula tor
An embedded voltage reg ulator supplies all the digital logic in the Core and the Backup power
domains.
The regulator has two functionnal mode depending of BUCK/LDOn (PA02) pin value. When this
pin is low, the regulator is in linear mode and VDDOUT must be connected to VDDCORE exter-
nally. When this pin is high, it behaves as a switching regulator and an inductor must be placed
between VDDOUT and VDDCORE. The value of this pin is sampled during the power-up phase
when the Power On Reset 33 reaches VPOT+ (Section 9.9 ”Analog Characteristics” on page 129 )
Its output voltag es in the Core domain (VCORE) and in the Backup doma in (VBKUP) are always
equal except in Backup mode where the Core domain is not powered (VCORE=0). The Backup
domain is always powered. Th e voltage regulator features three dif ferent modes:
• Normal mode: the regulator is configured as linear or switching regulator. It can support all
different Run and Sleep modes .
• Low Power (LP) mode: the regulator consumes little static current. It can be used in W ait
modes.
• Ultra Lo w P o wer (ULP) mode: the regula tor consumes v ery little static current . It is dedicated
to Retention and Backup modes. In Backup mode, the regulator only supplies the backup
domain.
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6.2.2 Typical Powering Schematics
The ATSAM4L8/L4/L2 supports the Single supply mode from 1.68V to 3.6V. Depending on the
input voltage range and on the final application frequency, it is recommended to use the follow-
ing table in order to choose the most efficient power strategy
Figure 6-3. Efficient power strategy:
N/A Possible but
not efficient
1.68V 1.80V 2.00V 2.30V 3.60V
Optimal power efficiency
Linear Mode
(BUCK/LDOn
(PA02) =0)
Optimal power efficiency Possible but not efficient
Switching Mode
(BUCK/LDOn
(PA02) =1)
FCPUMAX 12MHz
PowerScaling PS1(1)
Up to 36MHz In PS0
Up to 12MHz in PS1
Up to 48MHz in PS2
ALL
VDDIN Voltage
Typical power
consumption in
RUN mode
100µA/MHz @ FCPU=12MHz(PS1) @ VVDDIN=3.3V
180µA/MHz @ FCPU=48MHz(PS2) @ VVDDIN=3.3V
212µA/MHz @ FCPU=12MHz(PS1)
306µA/MHz @ FCPU= 48MHz(PS2)
Typical power
consumption in
RET mode
1.5µA
Note 1. The SAM4L boots in PS0 on RCSYS(115kHz), then the application must switch to
PS1 before running on higher frequency (<12MHz)
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The inter nal re gulator is connec ted to the VDDIN pin and its output VDDOUT feeds VDDCORE
in linear mode or throug h an induct or in switching mode. Figur e 6-4 shows the po w er schematics
to be used. All I/O lines will be powered by the same power (VVDDIN=VVDDIO=VVDDANA).
Figure 6-4. Single Supply Mode
6.2.3 LCD Power Modes
6.2.3.1 Principle LCD lines is powered using the device internal volt age sour ces provided by t he LCDPWR block.
When enabled, the LCDPWR blocks will generate the VLCD, BIASL, BIASH voltages.
LCD pads are splitted into three clusters that can be powered independently namely clusters A,
B and C. A cluster can either be in GPI O mode or in LCD mode.
When a cluster is in GPIO mode, its VDDIO pin must be powered externally. None of its GPIO
pin can be used as a LCD line
When a cluster is in LCD mode, each clusters VDDIO pin can be either forced externally (1.8-
3.6V) or unconnected (nc). GPIOs in a cluster are not available when it is in LCD mode. A clus-
ter is set in LCD mode by the LCDCA controller when it is enabled depending on the number of
segments configured. The LCDPWR block is powered by the VLCDIN pin inside cluster A
When LCD feature is not used, VLCDIN must be always powered (1.8-3.6V). VLCD, CAPH,
CAPL, BIASH, BIASL can be left unconnected in this case
VDDIN
VDDIO
VDDANA
VDDCORE
REGULATOR
ADC, DAC, AC0/1,
RC32K, OSC32K,
BOD18, BOD33
RC80M, OSC,
Core domain: CPU,
Peripherals, RAM, Flash,
RCSYS, PLL, DFLL,
RCFAST
Backup domain:
AST, WDT, EIC,
BPM, BSCIF
Main Supply
(1.68V-3.6V)
VDDOUT
BUCK/LDOn
(PA02)
VLCDIN LCD VPUMP
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Figure 6-5. LCD clusters in the device
6.2.3.2 Internal LCD Voltage
In this mode the LCD voltages are internally generated. Depending of the number of segments
required by the application, LCDB and LDCC clusters VDDIO pin must be unconnected (nc) or
1
2
3
4
5
6
GND
7
VDDIO
8
9
10
11
12
13
14
GND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GNDANA
33
34
VDDANA
35
36
37
38
39
40
41
42
43
44
45
46
47
COM2
48
COM1
49
COM0
50
SEG1775
SEG1674
SEG1573
SEG1472
SEG1371
SEG1270
SEG1169
SEG1068
SEG967
SEG866
SEG765
SEG664
SEG563
SEG462
SEG361
SEG260
SEG159
SEG058
VLCDIN57
GND56
BIASL55
BIASH54
VLCD53
CAPL52
CAPH51
SEG18 76
SEG19 77
SEG20 78
SEG24 79
SEG25 80
SEG26 81
SEG27 82
SEG28 83
SEG29 84
SEG30 85
SEG31 86
VDDIO 87
VDDIO 88
SEG32 89
SEG33 90
SEG34 91
SEG35 92
SEG36 93
SEG37 94
SEG38 95
SEG39 96
97
98
99
GND 100
VDDOUT
VDDIN
VDDCORE
COM3
SEG21
SEG22
SEG23
1
2
3
4
VDDCORE5
GND6
VDDOUT7
VDDIN8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GNDANA
23
24
VDDANA
25
26
27
28
29
SEG14
30
SEG13
31
SEG12
32
SEG848
SEG747
SEG646
SEG545
SEG444
SEG343
SEG242
SEG141
SEG040
VLCDIN39
GND38
BIASL37
BIASH36
VLCD35
CAPL34
CAPH33
SEG9 49
SEG10 50
SEG11 51
VDDIO 52
53
54
55
56
57
58
59
60
VDDIO 61
62
63
GND 64
COM3
COM2
COM1
COM0
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
1
2
3
4
VDDCORE5
GND6
VDDOUT7
VDDIN8
9
10
11
12
13
14
15
16
GNDANA17
18
VDDANA19
SEG820
COM321
COM222
COM123
COM024
SEG436
SEG335
SEG234
SEG133
SEG032
VLCDIN31
GND30
BIASL29
BIASH28
VLCD27
CAPL26
CAPH25
SEG5 37
SEG6 38
SEG7 39
VDDIO 40
SEG9 41
SEG10 42
SEG11 43
SEG12 44
VDDIO 45
46
47
GND 48
TQFP48/QFN48
TQFP64/QFN64
TQFP100
LCDA CLUSTERLCDB CLUSTERLCDC CLUSTER
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connected to an external voltage source (1.8-3.6V). LCDB cluster is not available in 64 and 48
pin packages
Table 6-1. LCD powering when using the internal voltage pump
Package Segments
in use VDDIO
LCDB VDDIO
LCDC
100-pin packages
[1,24] 1.8-3.6V 1.8-3.6V
[1, 32] nc 1.8-3.6V
[1, 40] nc nc
64-pin packages [1,15] - 1.8-3.6V
[1, 23] -nc
48-pin packages [1,9] - 1.8-3.6V
[1,13] -nc
VLCDIN
GND
GPIOs
LCD
VPUMP
CAPH
CAPL
BIASH
BIASL
VLCD
VDDIO
LCDB DOMAIN
GPIOs
VDDIO
GPIOs
LCDC DOMAIN
Switch onSwitch on
nc
nc
1.8–3.6V
VLCDIN
GND
GPIOs
LCD
VPUMP
CAPH
CAPL
BIASH
BIASL
VLCD
VDDIO
LCDB DOMAIN
GPIOs
VDDIO
GPIOs
LCDC DOMAIN
Switch onSwitch off
nc
1.8–3.6V
VLCDIN
GND
GPIOs
LCD
VPUMP
CAPH
CAPL
BIASH
BIASL
VLCD
VDDIO
LCDB DOMAIN
GPIOs
VDDIO
GPIOs
LCDC DOMAIN
Switch offSwitch off
1.8–3.6V
1.8–3.6V
LCDA DOMAIN LCDA DOMAIN LCDA DOMAIN
1.8–3.6V
Up to 4x40 segments
No GPIO in LCD
clusters
Up to 4x32 segments
Up to 8 GPIOs in
LCDC clusters
Up to 4x24 segments
Up to 16 GPIOs in
LCDB & LCDC
clusters
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6.2.4 Power-up Sequence
6.2.4.1 Maximum Rise Rate
To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values
described in Table 9-3 on page 100.
6.2.4.2 Minimum Rise Rate
The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply
requires a minimum rise rate for the VDDIN power supply.
See Table 9-3 on page 100 for the minimum rise rate value.
If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-
ply is met, the following configuration can be use d:
• A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.6 V.
6.3 Startup Considerations
This section summarizes the bo ot sequence of the ATSAM 4L8/ L4/L2. Th e behavior after po wer-
up is controlled by the Power Manager. For specific details, refer to Section 9. ”Power Manager
(PM)” on page 677.
6.3.1 Starting of Clocks
After power-up, the device will be held in a reset state by the power-up circuitry for a short time
to allow the power to stabilize throughout the device. After reset, the device will use the System
RC Oscillator (RCSYS) as clock source. Refer to Section 9. ”Electrical Characteristics” on page
99 for the frequency for this oscillator.
On system start-up, the DFLL and the PLLs are disabled. Only the necessary clocks are active
allowing software execution. Refer to Section 3-6 ”Maskable Module Clocks in AT32UC3B.” on
page 24 to know the list of peripheral clock running.. No clocks have a divided frequency; all
parts of the system receive a clock with the same frequency as the System RC Oscillator.
6.3.2 Fetching of Initia l Inst ruc t ions
After reset has been released, the Cortex M4 CPU starts fetching PC and SP values from the
reset address, which is 0x00000000. Refer to the ARM Architecture Reference Manual for more
information on CPU startup. This address points to the first address in the internal Flash.
The code read from the internal flash is free to configure the clock system and clock sources.
6.4 Power-on-Reset, Brownout and Supply Monitor
The SAM4L embeds four features to monitor, warm, and/or reset the device:
• POR33: Power-on-Reset on VDDANA
• BOD33: Brownout detector on VDDANA
• POR18: Power-on-Reset on VDDCORE
• BOD18: Bro wnout detector on VDDCORE
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Figure 6-6. Supply Monitor Schematic
6.4.1 Power-on-Reset on VDDANA
POR33 monitors VDDANA. It is always activated and monitors voltage at startup but also during
all the Power Save Mode . If VDDANA go es below t he t hresho ld volt age, the e nt ire chip i s reset.
6.4.2 Brownout Detector on VDDANA
BOD33 monitors VDDANA. Refer to Section 15. ”Backup System Control Interface (BSCIF)” on
page 308to get more details.
6.4.3 Power-on-Reset on VDDCORE
POR18 monitors the internal VDDCORE. Refer to Sectio n 15. ” Backup System Co ntrol I nterface
(BSCIF)” on page 308 to get more details.
6.4.4 Brownout Detector on VDDCORE
Once the device is startup, the BOD18 monitors the internal VDDCORE. Refer to Section 15.
”Backup System Cont rol Interface (BSCIF)” on page 308 to get more details.
POR33
BOD33
BOD18
VDDANA GNDANA
VDDANA
POR18
DUAL OUTPUT
TRIMMABLE
VOLTAGE
REGULATOR VDDCORE
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7. Low Power Techniques
The ATSAM4L8/L4/L2 suppor ts multiple power configurations to allow the user to optimize its
power consumption in different use cases. The Backup Power Manager (BPM) implements dif-
ferent solutions to reduce the power consumption:
• The Power Sa ve modes intended to reduce the logic activit y and to adapt the power
configuration. See ”Power Save Modes” on page 55.
• The Power Scaling intended to scale the power configuration (voltage scaling of the
regulator). See ”Power Scaling” on page 60.
These two techniques can be combined together.
Figure 7-1. Power Scaling and Power Save Mode Overview
7.1 Power Save Modes
Refer to Section 6. ”Power and Startup Considerations” on page 46 to get definition of the core
and the backup dom ains.
SLEEP1
WAIT1
RET1
BKUP1
RUN1
POWER SCALING
Max frequency = 36Mhz
Normal Speed Flash
Nominal Voltage
BPM.PMCON.PS=0
Max frequency = 12Mhz
Normal Speed Flash
Reduced Voltage
BPM.PMCON.PS=1
RESET
RUN
SLEEP0
WAIT0
RET0
BKUP0
RUN0
SLEEP
CPU Clock OFF
4 sub-modes
WAIT
All Clocks OFF
SleepWalking
RETENTION
All Clocks OFF
Full chip retention
BACKUP
Core Domain OFF
POWER SAVE MODES
Max frequency = 48Mhz
High Speed Flash
Nominal Voltage
BPM.PMCON.PS=2
SLEEP2
WAIT2
RET2
BKUP2
RUN2
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At power-up or after a reset, the ATSAM4L8/L4/L2 is in the RUN0 mode. Only the necessary
clocks are enabled allowin g software execution. T he Power Manager (PM) can be used to adjust
the clock frequencies and to enable and disable the peripheral clocks.
When the CPU is entering a Power Save Mode, the CPU stops executing code. The user can
choose between four Power Save Modes to optimize power consumption:
• SLEEP mode: the Cortex-M4 core is stopped, optionally some clocks are stopped,
peripherals are kept running if enabled by the user.
• WAIT mode: all clock sources are stopped, the core and all the peripherals are stopped
except the modules running with the 32kHz clock if enabled. This is the lowest power
configuration where SleepWalking is supported.
• RETENTION mode: similar to the WAIT mode in terms of clock activity. This is the lowest
power configuration where the logic is retained.
• BACKUP mode: the Core domain is powered off, the Backup domain is kept powered.
A wake up source exits the system to the RUN mode from which the Power Save Mode was
entered.
A reset source always exits the system from the Power Save Mode to t he RUN0 mode.
The configuration of the I/O lines are maintained in all Power Save Modes. Refer to Section 9.
”Backup Power Manager (BPM)” on page 677.
7.1.1 SLEEP mode The SLEEP mode allows power optimization with the fastest wake up time.
The CPU is stopped. To furth er reduce power consumption, the user can switch off modules-
clocks and synchronous clock sources through the BPM.PMCON.SLEEP field (See Table 7-1 ).
The required mo dules will be halted regardless of the bit sett ings of the mask registers in the
Power Manager (PM.AHBMASK, PM.APBxMASK).
Notes: 1. from modules with clock running.
2. OSC32K and RC32K will only remain operationa l if pre-enabled.
7.1.1.1 Entering SLEEP mode
The SLEEP mode is entered by executing the WFI instruction.
Additionally, if the SLEEPONEXIT bit in the Cortex-M4 System Control Register (SCR) is set,
the SLEEP mode will also be entered wh en the Cortex-M4 exits the lowest priority ISR. This
Table 7-1. SLEEP mode Configuration
BPM.PSAVE.SLEEP CPU
clock AHB
clocks APB cloc ks
GCLK
Clock sources:
OSC, RCFAST,
RC80M, PLL,
DFLL RCSYS OSC32K
RC32K(2) Wake up Sources
0 Stop Run Run Run Run Run Any interrupt
1 Stop Stop Run Run Run Run Any interrupt(1)
2 Stop Stop Stop Run Run Run Any interrupt(1)
3 Stop Stop Stop Stop Run Run Any interrupt(1)
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mechanism can b e useful for applica tions that only require the p rocessor to run when a n inter-
rupt occurs.
Before entering the SLEEP mode, the user must configure:
• the SLEEP mode configuration field (BPM.PMCON.SLEEP), Refer to Table 7-1.
• the SCR.SLEEPDEEP bit to 0. (See the Power Management section in the ARM Cortex-M4
Processor chapter).
• the BPM.PMCON.RET bit to 0.
• the BPM.PMCON.BKUP bit to 0.
7.1.1.2 Exiting SLEEP mode
The NVIC wakes the system up when it detects any non-masked interrupt with sufficient prior ity
to cause exception entry. The system goes back to the RUN mode from which the SLEEP mode
was entered. The CPU and affected modules are restar ted. Note that even if an interr upt is
enabled in SLEEP mode, it will not tr igge r if the source module is not clocked.
7.1.2 WAIT Mode and RETENTION Mode
The WAIT and RETENTION modes allow achieving very low power consumption while main-
taining the Core domain powered-on. Internal SRAM and registers contents of the Core domain
are preserved.
In these modes, all clocks are stopped except the 32kHz clocks (OSC32K, RC32K) which are
kept running if enabled.
In RETENTION mode, the SleepWalking feature is not supporte d and must not be used.
7.1.2.1 Entering WAIT or RETENTION Mode
The WAIT or RETENTION modes are entered by executing the WFI instruction with the follow-
ing settings:
• set the SCR.SLEEPDEEP bit to 1. (See the Power Management section in the ARM Cortex-
M4 Processor chapter).
• set the BPM.PSAVE.BKUP bit to 0.
• set the BPM.PMCON.RET bit to RETENTION or WAIT mode.
SLEEPONEXIT feature is also available. See ”Entering SLEEP mode” on page 56.
7.1.2.2 Exiting WAIT or RETENTION Mode
In WAIT or RETENTION modes, synchronous clocks are stopped preventing interrupt sources
from triggering. To wakeup the system, asynchronous wake up sources (AST, EIC, USBC ...)
should be enabled in the peripheral (refer to the documentation of the peripheral). The
PM.AWEN (Asynchronous Wake Up Enable) register should also be enabled for all peripheral
except for EIC and AST.
When the enabled asynchronous wake up event occurs and the system is waken-up, it will gen-
erate either:
• an interrupt on the PM WAKE interrupt line if enabled (Refer to Section 9. ”Power Manager
(PM)” on page 677). In that case, the PM.WCAUSE register indicates the wakeup source.
• or an interrupt direct ly from the peripheral if enabled (Refer to the section of the peripheral).
When waking up, the system goes back to the RUN mode mode from which the WAIT or
RETENTION mode was entered.
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7.1.3 BACKUP ModeThe BACKUP mode allows achieving the lowest power consumption possible in a system which
is performing perio dic wake-ups to perform tasks but not requiring fast startup time.
The Core domain is powered-off. The internal SRAM and register contents of the Core domain
are lost. The Backup domain is kept powered-on. The 32kHz clock (RC32K or OSC32K) is kept
running if enabled to feed modules that require clocking.
In BACKUP mode, the configuration of the I/O lines is preserved. Refer to Section 9. ”Backup
Power Manager (BPM)” on page 677 to have more details.
7.1.3.1 Entering BACKUP Mode
The Backup mode is entered by using the WFI instruction with the following settings:
• set the SCR.SLEEPDEEP bit to 1. (See the Power Management section in the ARM Cortex-
M4 Processor chapter).
• set the BPM.PSAVE.BKUP bit to 1.
7.1.3.2 Exiting BACKUP Mode
Exit from BACKUP mode happens if a reset occurs or if an enabled wake up event occurs.
The reset sources are:
• BOD33 reset
• BOD18 reset
• WDT reset
• External reset in RESET_N pin
The wake up sources are:
• EIC lines (level transition only)
• BOD33 interrupt
• BOD18 interrupt
• AST alarm, periodic, o verflow
• WDT interrupt
The RC32K or OSC32K should be used as clock source for modules if required. The
PMCON.CK32S is used to select one of these two 32kHz clock sources.
Exiting the BACKUP mode is triggered by:
• a reset source: an internal reset sequence is performed according to the reset source. Once
VDDCORE is stable and has t he correct value according to RUN0 mode , the interna l reset is
released and program execution starts. The corresponding reset source is flagged in the
Reset Cause register (RCAUSE) of the PM.
• a wak e up source: the Bac ku p domain is not reset . An internal reset is generated to the Cor e
domain, and the system s wi tches back to the pr eviou s R UN mode. Once VDDCORE is stable
and has the correct value, the internal reset in the Core domain is released and program
execution starts. The BKUP bit is set in the Reset Cause re gis te r (RCAUSE) of the PM. It
allows the user to discriminate between the reset cause and a wake up cause from the
BACKUP mode. The wake up cause can be found in the Backup Wake up Cause register
(BPM.BKUPWCAUSE).
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7.1.4 Wakeup Time
7.1.4.1 Wakeup Time From SLEEP Mode
The latency depends on th e clock sources wake up time. If the clock sources are not stopped,
there is no latency to wake the clocks up.
7.1.4.2 Wakeup Time From WAIT or RETENTION Mode
The wake up latency consists of:
• the switching time from the low power configuration to the RUN mode power configuration.
By default, the switching time is completed when all the voltage regulation system is ready.
To speed-up t h e st artu p t ime, t he user can se t th e F ast Wake up bit in BPM .PMCON r eg ist e r.
• the wake up time of the RC oscillator used to start the system up. By default, the RCSYS
oscillator is used to startup the system. The user can use another clock source (RCFAST for
example) to speed up the startup time by configuring the PM.FASTWKUP register. Refer to
Section 9. ”Power Manager (PM)” on page 677.
• the Flash memory wake up time.
To have the shortest wakeup time, the user should:
- set the BPM.PMCON.FASTWKUP bit.
- configure the PM.FASTSLEEP.FASTRCOSC field to use the RCFAST main clock.
- enter the WAIT or RETENTION mode
Upon a wakeup, this is required to keep the main clock connected to RCFAST until the voltage
regulation system is fully ready (when BPM.ISR.PSOK bit is one). During this wakeup period,
the FLASHCALW module is automatically configured to operate in “1 wait state mode”.
7.1.4.3 Wake time from BACKUP mode
It is equal to the Core domain logic reset latency (similar to the reset latency caused by an exter-
nal reset in RESET_N pin) added to the time required for the voltage regulation system to be
stabilized.
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7.1.5 Power Save Mode Summary Table
The following table shows a su mmary of the main Power Save modes:
7.2 Power ScalingThe Power Scaling technique consists of adjusting the internal regulator output voltage (voltage
scaling) to reduce the power consumption. Accordin g to the requirements in terms of perfor-
mance, operating modes, and current consumption, the user can select the Power Scaling
configuration that fits the best with it s application.
The Power Scaling config uration field (PMCON.PS) is provided in the Backup Power Manager
(BPM) module.
In RUN mode, the user can adjust on the fly the Power Scaling configuration
The Figure 7.1 summarizes the different com bination of the Power Scaling config uration which
can be applied according t o the Power Save Mode.
Power scaling from a current power configuration to a new power configuration is done by halt-
ing the CPU execution
Power scaling occurs after a WFI instruction. The system is halted unt il the new power configu-
ration is stabilized. After handling the PM interrupt, the system resumes from WFI.
To scale the power, the fo llowing sequenc e is requ i re d:
• Check the BPM.SR.PSOK bit to make sure the current power configuration is stabilized.
Table 7-2. Power Save mode Configuration Summary
Mode Mode Entry Wake up sources Core
domain Backup
domain
SLEEP WFI
SCR.SLEEPDEEP bit = 0
BPM.PMCON.BKUP bit = 0 Any interrupt
CPU clock OFF
Other clocks OFF depending
on the BPM.PMCON.SLEEP
field
see ”SLEEP mode” on page
56
Clocks OFF depending on
the BPM.PMCON.SLEEP
field
see ”SLEEP mode” on page
56
WAIT
WFI
SCR.SLEEPDEEP bit = 1
BPM.PMCON.RET bit = 0
BPM.PMCON.BKUP bit = 0
PM WAKE interrupt All clocks are OFF
Core domain is retained
All clocks are OFF except
RC32K or OSC32K if
running
RETENTION
WFI
SCR.SLEEPDEEP bit = 1
BPM.PMCON.RET bit = 1
BPM.PMCON.BKUP bit = 0
PM WAKE interrupt All clocks are OFF
Core domain is retained
All clocks are OFF except
RC32K or OSC32K if
running
BACKUP WFI
+ SCR.SLEEPDEEP bit = 1
+ BPM.PMCON.BKUP bit = 1
EIC interrupt
BOD33, BOD18 interrupt
and reset
AST alarm, periodic,
overflow
WDT interrupt and reset
external reset on RESET_N
pin
OFF (not powered) All clocks are OFF except
RC32K or OSC32K if
running
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• Set the clock frequency to be supported in both power configurations.
• Set the high speed read mode of the FLASH to be supported in both power scaling
configurations
– Only relevant when entering or exiting BPM.PMCON.PS=2
• Configure the BPM.PMCON.PS field to the new power conf iguration.
• Set the BPM.PMCON.PSCREQ bit to one.
• Disable all the interrupts except the PM WCAUSE interrupt and enable only the PSOK
asynchronous event in the AWEN register of PM.
• Execute the WFI instruction.
• WAIT for PM interrupt.
The new power configuration is reached when the system is waken up by the PM interrupt
thanks to the PSOK event.
By default, all features are available in all Power Scaling modes. However some specific fea-
tures are not available in PS1 (BPM.PMCON.PS=1) mode :
–USB
–DFLL
–PLL
– Programming/Erasing in Flash
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8. Debug and Test
8.1 Features •IEEE1149.1 compliant JTAG Debug Port
•Serial Wire Debug Port
•Boundary-Scan chain on all digital pins for board-level testing
•Direct memory access and programming capabilities through debu g ports
•Flash Patch and Breakpoint (FPB) unit fo r implementing breakpoints and code patches
•Data Watchpoint and Trace (DWT) un it for implementing watchpoints, data tracing, and system
profiling
•Instrumentation Trace Macrocell (ITM) for support of printf style debugg ing
•Chip Erase c om m an d an d status
•Unlimited Flash User page read access
•Cortex-M4 core reset source
•CRC32 of any memory accessible through the bus matrix
•Debugger Hot Plugging
8.2 Overview Debug and test features are made available to external tools by:
• The Enhanced Debug Port (EDP) embedding:
– a Serial Wire Debug Port (SW-DP) part of the ARM coresight architecture
– an IEEE 1149.1 JTAG Debug Debug Port (JTAG-DP) part of the ARM coresight
architecture
– a supplementary IEEE 1149.1 JTAG TAP machine that implements the boundary
scan feature
• The System Manager Acces Port (SMAP) providing unlimited flash User page read access,
CRC32 of any memory accessible through the bus matrix and Cortex-M4 core reset services
• The AHB Access Port (AHB-AP) providing Direct memory access, programming capabilities
and standard debugging functions
• The Instrumentation Trace macrocell part of the ARM coresight architecture
For more information on ARM debug components, please refer to:
• ARMv7-M Architecture Reference Manual
• ARM Debug Interface v5.1 Architecture Specification document
• ARM CoreSight Architecture Specification
• ARM ETM Architecture Specification v3.5
• ARM Cortex-M4 Technical Reference Manual
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8.3 Block diagram
Figure 8-1. Debug and Test Block Diagram
note: Boxes with a plain corner are SAM4L specific.
8.4 I/O Lines Description
Refer to Section 1.1.4 ”I/O Lines Description” on page 4.
SWJ-DP
AHB-AP
TCK
RESET_N
RESET
CONTROLLER
BSCAN-TAP
TDO
TDI
TMS
POR
Boundary
scan
SMAP Core reset request SMAP
ENHANCED
DEBUG PORT
DAP Bus
Hot_plugging
JTAG-FILTER
AHB
CORTEX-M4
NVICFPB DWT ITM
Core
Instr Data
Private peripheral Bus (PPB)
TPIU
PORT
MUXING
HTOP
APB
AHB
Cortex-M4 Core reset
AHB
M
M
S
Chip Erase
EDP Core reset request
System Bus Matrix
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8.5 Product dependencies
8.5.1 I/O Lines Refe r to Section 1.1.5.1 ”I/O Lines” on page 5.
8.5.2 Power management
Refer to Section 1.1.5.2 ”Power Management” on page 5.
8.5.3 Clocks Re fe r to Section 1.1.5.3 ”Clocks” on page 5.
8.6 Core debug Figure 8-2 shows the Debug Architect ure u sed in t he SAM4L . The Corte x-M4 em beds fo ur func-
tional units fo r debug:
• FPB (Flash Patch Breakpoint)
• DWT (Data Watchpoint and Trace)
• ITM (Instrumentation Trace Macrocell)
• TPIU (Trace Port Interface Unit)
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP
Emulators/Pro bes and debuggin g tool vendo rs for Cortex-M 4 based microc ontrollers . For furth er
details on SWJ-DP see the Cort ex-M4 technical refere nce manual.
Figure 8-2. Debug Architecture
8.6.1 FPB (Flash Patch Breakpoint)
The FPB:
• Implements hardware breakpoints
• Patches (on the fly) code and data being fetched by the Cortex-M4 core from code space
with data in the system space. Definition of code and system spaces can be found in the
System Address Map section of the ARMv7-M Architecture Reference Manual.
4 watchpoints
PC sampler
data address sampler
data sampler
interrupt trace
CPU statistics
DWT
6 breakpoints
FPB
software trace
32 channels
time stamping
ITM
SWD/JTAG
SWJ-DP
SWO trace
TPIU
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The FPB unit contains:
• Two liter al comparator s f or matching agai nst literal load s from Code space , and remapping to
a corresponding area in System space.
• Six instruction comparators for matching against instruction fetches from Code space and
remapping to a co rresponding area in System space.
• Alternatively, comparat ors can also be configured to generate a Breakpoint instruction to the
processor core on a match.
8.6.2 DWT (Data Watchpoint and Trace)
The DWT contains four comparators which can be configured to gene rate the following:
• PC sampling packets at set intervals
• PC or Data watchpoint packets
• Watchpoint event to halt core
The DWT contains counters for the items that follow:
• Clock cycle (CYCCNT)
• Folded instructions
• Load Store Unit (LSU) operations
• Sleep Cycles
• CPI (all instruction cycles except for the first cycle)
• Interrupt overhead
8.6.3 ITM (Instrumentation Trace Macrocell)
The ITM is an application driven trace source that supports printf style debugging to trace Oper -
ating System (O S) and application events, and emits diagnostic system in formation. The ITM
emits trace information as packets which can be generated by three different sources with sev-
eral priority levels:
•Software trace: This can be done thanks to the printf style deb ugging. F o r more inf ormation,
refer to Section “How to Configure the ITM: ”.
•Hardware trace: The ITM emits packets generated by the DWT.
•Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit
counter to generate the timestamp.
How to Configure the ITM:
The following example describes how to output trace data in asynchronous trace mode.
• Configure th e TPIU for asynchronous trace mode (refer to Section “5.4.3. How to Configure
the TPIU”)
• Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the
Lock Access Register (Address: 0xE0000FB0)
• Write 0x00010015 into th e Trace Control Register:
–Enable ITM
– Enable Synchronization packets
– Enable SWO behavior
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– Fix the ATB ID to 1
• Write 0x1 into the Trace Enable Register:
– Enable the Stimulus por t 0
• Write 0x1 into the Trace Privilege Register:
– Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will
result in the corresponding stimulus port being accessible in user mode.)
• Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macro-
cell (ITM).
The TPIU formats and transmits tr ace data of f-chip at fr equencies asynchrono us to the core.
Asynchronous Mode:
The TPIU is configured in asynchronous mode, trace data are outp ut using the single TRA C-
ESWO pin. The TRACESWO sig na l is mult iplexed wit h t he TDO sig na l of the JT AG Deb ug Po rt.
As a consequence, asynchronous trace mode is only available when the Serial Wire Debug
mode is selected since TDO signal is used in JTAG debug mode.
Two encoding format s are available for the single pin output:
• Manchester encoded stream. This is the reset value.
• NRZ_based UART byte structure
5.4.3. How to Configure the TPIU
This example on ly co nce r ns the asynchron o us trace mode.
• Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to
enable the use of tr ace and debug blocks.
• Write 0x2 into the Selected Pin Protocol Register
– Select the Serial Wire Output – NRZ
• Write 0x100 into the Formatter and Flush Control Register
• Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the
baud ra te of th e a s yn chro nou s ou tp ut ( th is can be do ne au tomat i cally by the deb ugg ing t ool ).
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8.7 Enhanced Debug Port (EDP)
Rev.: 1.0.0.0
8.7.1 Features •IEEE1149.1 compliant JTAG debug port
•Serial Wire Debug Port
•Boundary-Scan chain on all digital pins for board-level testing
•Debugger Hot-Plugging
•SMAP core reset request source
8.7.2 Overview The enhanced debug port embeds a standard ARM debug port plus some specific hardware
intended for testability and activation of the debug port features. All the information related to the
ARM Debug Interface implementation can be found in the ARM Debug Interface v5.1 Architec-
ture Specification document.
It features:
• A single Deb ug P ort (SWJ-DP), that pro vides the e xternal ph ysical connection to the in terf ace
and supports two DP implementations:
– the JTAG Debug Port (JTAG-DP)
– the Serial Wire Debug Port (SW-DP)
• A supplementary JTAG TAP (BSCAN-TAP) connected in parallel with the JTAG-DP that
implements the bo und ary scan instructions deta ile d in
• A JTA G-FILTER module that monitors TCK and RESET_N pins to handle specific features
like the detection of a debugger hot-plugging and the request of re set of the Cortex-M4 at
startup.
The JTAG-FILTER module detects the presence o f a debugger. When pre sent, JTAG pins are
automatically assig ned to the Enhanced Debug Port(EDP). If the SWJ-DP is switched to the SW
mode, then TDI and TDO alt ernate functions are rele ased. The JTAG-FILTER also implements a
CPU halt mechanism. When triggered, the Cor tex-M4 is maintained under reset after the exter-
nal reset is released to prevent any system corruption during later programmation operat ions.
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8.7.3 Block Diagram
Figure 8-3. Enhanced Debug Port Block Diagram
8.7.4 I/O Lin es Description
TCK
RESET_N
TDO
TDI
TMS
boundary_scan
JTAG-FILTER EDP Core reset request
ENHANCED DEBUG PORT
DAP Bus
SW-DP
SWJ-DP
JTAG-DP
BSCAN-TAP
traceswo
swclk
swdio
tdo
tck
tms
tdi
tdo
tck
tms
tdi
tck
reset_n
test_tap_sel
Table 8-1. I/ O Lin es Descr ip tion
Name JTAG Debug Port SWD De bug Port
Type Description Type Description
TCK/SWCLK I Debug Clock I Serial Wire Clock
TDI I Debug Data in - NA
TDO/TRACESWO O Debug Data Out O Trace asynchronous Data Out
TMS/SWDIO I Debug Mode Select I/O Serial Wire Input/Output
RESET_N I Reset I Reset
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8.7.5 Product Dependencies
8.7.5.1 I/O Lines The TCK pin is dedicated to the EDP. The other debug po rt pins def ault af ter reset to their GPIO
functionality and are automatically reassigned to the JTAG functionalities on detection of a
debugger. In serial wire mode, TDI and TDO can be used as GPIO functions. Note that in serial
wire mode TDO can be used as a single pin trace output.
8.7.5.2 Power Management
When a debugger is present, the connection is kept alive allowing debug operations. As a side
effect, the power is never turned off. The hot plugging functionality is always available except
when the system is in BACKUP Power Save Mode.
8.7.5.3 Clocks The SWJ-DP uses the external TCK pin as its clock source. This clock must be provided by the
external JTAG master device.
Some of the JTAG Instructions are used to access an Access Port (SMAP or AHB-AP). These
instructions require the CPU clock to be running.
If the CPU clock is not pres ent because the CPU is in a Power Save Mode where t his clock is
not provided, the Power Manager(PM) will automatically restore the CPU clock on detection of a
debug access.
The RCSYS clock is used as CPU clock when the external reset is applied to ensure correct
Access Port operations.
8.7.6 Module Initialization
This module is enabled as soon as a TCK falling edge is detected when RESET_N is not
asserted (refer to Section 8.7.7 below). Moreover, the module is synchronously reseted as long
as the TAP machine is in the TEST_LOGIC_RESET (TLR) state. It is advised asserting TMS at
least 5 TCK clock periods after the debugger has been detected to ensure the module is in the
TLR state prior to any operation. This module also has the ability to maintain the Cortex-M4
under rese t (refer to the Section 8.7.8 ”SMAP Core Reset Request Source” on page 70).
8.7.7 Debugger Hot Plugging
The TCK pin is dedicated to the EDP. After reset has been released, the EDP detects that a
debugger has been attached when a TCK falling edge arises.
Figure 8-4. Debugger Hot Plugging Detection Timings Diagram
TCK
RESET_N
Hot_plugging
TCK
RESET_N
Hot Plugging
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The Debug Port pins assignation is then forced to the EDP function even if they were already
assigned to another module. This allows to connect a debugger at any time without reseting the
device. The connection is non-intrusive meaning that the chip will continue its execution without
being disturbed . Th e CPU can of cour se be halte d lat er on by issuin g Cor te x- M4 OCD fe atures.
8.7.8 SMAP Core Reset Request Source
The EDP has the ability to send a request to the SMAP for a C ortex-M4 Core reset. The proce-
dure to do so is to hold TCK low until RESET_N is released. This mechanism aims at halting the
CPU to prevent it from changing the system configuration while the SMAP is operating.
Figure 8-5. SMAP Core Reset Request Timings Diagram
The SMAP can de-assert th e core reset requ est for this oper ation, ref er to Section 2.8.8 ”Cort ex-
M4 Core Reset Source” on page 57.
8.7.9 SWJ-DP The Cortex-M4 embeds a SWJ-DP Debug port which is the standard CoreSight™ debug port. It
combines Serial Wire Debug Port (SW- DP), fro m 2 to 3 pins and JTAG debug Por t(JTAG- DP), 5
pins.
By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables JTAG-DP and enables SW-DP.
When the EDP has been switched t o Serial Wire m ode, TDO/ TRACESWO can be used f or trace
(for more information refer to the section below). The asynchronous TRACE output (TRAC-
ESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not
JTAG-DP.
The SWJ-DP provides access to the AHB-AP and SMAP access ports which have the following
APSEL value:
Ref er to the ARM Debug Interface v5.1 Architecture Specification for more details on SWJ-DP.
reset request
TCK
RESET_N
EDP
C ore reset request
Figure 8-6. Access Ports APSEL
Acces Port (AP) APSEL
AHB-AP 0
SMAP 1
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8.7.10 SW-DP and JTAG-DP Selection Mechanism
After reset, the SWJ-DP is in JTAG mode but it can be switched to the Serial Wire mode. Debug
port selection mechanism is done by sending specific SWDIOTMS sequence. T he JTAG-DP is
selected by default after reset.
• Switch from JTAG-DP to SW-DP. The sequence is:
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit seque nce on SWDIOTMS = 011110 01111 00111 (0x79 E7 MSB firs t)
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
• Switch from SWD to JTAG. The sequence is:
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 00111100111001 11 (0x3CE7 MSB
first)
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Note that the BSCAN-TAP is not available when the debug port is switched to Serial Mode.
Boundary scan instructions are not available.
8.7.11 JTAG-DP and BSCAN-TAP Selection Mechanism
After the DP h as been en ab led, t h e BSCAN-TAP a nd th e JT AG-DP r un simultan eo usly has long
as the SWJ-DP remains in JTAG mode. Each TAP captures simultaneously the JTAG instruc-
tions that are shifted. If an instruction is recognized by the BSCAN-TAP, then the BSCAN-TAP
TDO is selected instead of the SWJ-DP TDO. TDO select ion changes dynamically depending on
the current instruction held in the BSCAN-TAP instruction register.
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8.7.12 JTAG Instructions Summary
The implemented JTAG instruct ions are shown in the table below.
Table 8-2. Implemented JTAG instructions list
IR instru ction
value Instruction Description availability
when
protected Component
b0000 EXTEST Select boundary-scan chain as da ta register for
testing circuitry external to
the device. yes
BSCAN-TAP
b0001 SAMPLE_PRELOAD Take a snapshot of external pin values without
affecting system operation. yes
b0100 INTEST Select boundary-scan chain for internal testing of the
device. yes
b0101 CLAMP Bypass device through Bypass register, while driving
outputs from boundary-scan regi ster. yes
b1000 ABOR T ARM JTA G-DP Instruction yes
SWJ-DP
(in JTAG mode)
b1010 DPACC ARM JTAG-DP Instruction yes
b1011 APACC ARM JTAG-DP Instruction yes
b1100 - Reserved yes
b1101 - Reserved yes
b1110 IDCODE ARM JTA G-DP Instruction yes
b1111 BYPASS Bypass this device through the bypass register. yes
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8.7.13 Security Restrict ion s
The SAM4L provide a security restrictions mechanism to lock access to the device. The device
in the protected state when the Flash Security Bit is set. Refer to section Flash Controller for
more details.
When the device is in the protected sta te the AHB-AP is locked. Full access to the AHB-AP is re-
enabled when the protected state is released by issuing a Chip Erase comma nd. Note that the
protected state will read as programmed only after the system has been reseted.
8.7.13.1 Notation Table 8-4 on page 73 shows bit patterns to be shifted in a format like "p01". Each character cor-
responds to one bit, and eight bits are grouped together for readability. The least significant bit is
always shifted first, and the most significant bit shifted last. The symbols used are shown in
Table 8-3.
In many cases, it is not required to shift all bits through the data register. Bit patterns are shown
using the full width of the shift register, but the suggested or required bits are emphasized using
bold text. I.e. give n the pat tern "01010101 xxxxxxxx xxxxxxx x xxxxxxxx", the shift register is 32
bits, but the test or debug unit may choose to shift only 8 bits "01010101".
The following describes how to interpret the fields in the instruction description tables:
Table 8-3. Symbol Description
Symbol Description
0 Constant low value - always reads as zero.
1 Constant high value - always reads as one.
p The chip protected state.
x A don’t care bit. Any value can be shifted in, and output data should be ignored.
e An error bit. Read as one if an error occurred, or zero if not.
b A busy bit. Read as one if the SMAP was busy, or zero if it was not.
s Startup done bit. Read as one if the system has started-up correctly.
Table 8-4. Inst ruction Descript ion
Instruction Description
IR input value
Shows the bit pattern to shift into IR in the Shift-IR state in order to select this
instruction. The pattern is show both in binary and in hexadecimal form f or
convenience.
Example: 1000 (0x8)
IR output value Shows the bit pattern shifted out of IR in the Shi ft-IR state when this instruction is
active.
Example: p00s
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8.7.14 JTAG Instructions
Refer to the ARM Debug Interface v5.1 Architecture Specification for more details on ABORT,
DPACC, APACC and IDCODE instructions.
8.7.14.1 EXTEST This instruction selects the b oun da ry-scan chai n as Da ta Re giste r for te sting circui try ex te rnal to
the chip package. The contents of the latched outputs of the boundary-scan chain is driven out
as soon as the JTAG IR-register is loaded with the EXTEST inst ruction.
Starting in Run-Test/Idle, the EXTEST instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-I R: The data from the boundary-scan chain is applied to the output pins.
5. Return to Run-Test/Idle.
6. Select the DR Scan pat h.
7. In Capture-DR: The data on the external pins is sampled into the boundary-scan chain.
8. In Shift-DR: Th e bo un d ary-scan chain is shifte d by the TCK input.
9. In Update-DR: Th e data from the scan chain is applied to the output pins.
10. Return to Run-Test/Idle.
8.7.14.2 SAMPLE_PRELOAD
This instruction takes a snap-shot of the input/output pins without affecting the system operation,
and pre-loading the scan chain without updating the DR-latch. The boundary-scan chain is
selected as Data Regi ster.
Starting in Run-Test/Idle, the Device Identification register is accessed in the following way:
DR Size Shows the number of bits in the data register chain whe n this instruction is active.
Example: 32 bits
DR input value Show s which bit pattern to shift into the data register in the Shift-DR state when this
instruction is active.
DR output value Shows the bit pattern shifted out of the data register in the Shift-DR state when this
instruction is active.
Table 8-4. Inst ruction Descript ion (Continued)
Instruction Description
Table 8-5. EXTEST Details
Instructions Details
IR input value 0000 (0x0)
IR output value p00s
DR Size Depending on boundary-scan chain, see BSDL-file.
DR input value Depending on boundary-scan chain, see BSDL-file.
DR output value Depending on boundary-scan chain, see BSDL-file.
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1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan pat h.
6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan
chain.
7. In Shift-DR: Th e bo un d ary-scan chain is shifted by the TCK input.
8. Return to Run-Test/Idle.
8.7.14.3 INTEST
This instruction selects the boundary-scan chain as Data Register for testing internal logic in the
device. The logic in puts are determined b y the boundary-scan chain, and the logic outputs are
captured by t he bounda ry-scan chain. The device output pins are driven f rom the boundary-scan
chain.
Starting in Run-Test/Idle, the INTEST instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-IR: The data from the bo undary-scan chain is applied to the internal logic
inputs.
5. Return to Run-Test/Idle.
6. Select the DR Scan pat h.
7. In Capture-DR: The data on the internal logic is sampled into the boundary-scan chain.
8. In Shift-DR: Th e bo un d ary-scan chain is shifte d by the TCK input.
9. In Update-DR: The data from the boundary-scan chain is applied to internal logic inputs.
10. Return to Run-Test/Idle.
Table 8-6. SAMPLE_PRELOAD Details
Instructions Details
IR input value 0001 (0x1)
IR output value p00s
DR Size Depending on boundary-scan chain, see BSDL-file.
DR input value Depending on boundary-scan chain, see BSDL-file.
DR output value Depending on boundary-scan chain, see BSDL-file.
Table 8-7. INTEST Deta ils
Instructions Details
IR input value 0100 (0x4)
IR output value p001
DR Size Depending on boundary-scan chain, see BSDL-file.
DR input value Depending on boundary-scan chain, see BSDL-file.
DR output value Depending on boundary-scan chain, see BSDL-file.
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8.7.14.4 CLAMP
This instruction selects the Bypass register as Data Register. The device output pins are driven
from the boundary-scan chain.
Starting in Run- Test/Idle, the CLAMP instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-I R: The data from the boundary-scan chain is applied to the output pins.
5. Return to Run-Test/Idle.
6. Select the DR Scan pat h.
7. In Capture-DR: A logic ‘0’ is loaded into the Bypass Register.
8. In Shift-DR: Data is scanned from TDI to TDO through the Bypass register.
9. Return to Run-Test/Idle.
Table 8-8. CLAMP Details
Instructions Details
IR input value 0101 (0x5)
IR output value p00s
DR Size 1
DR input value x
DR output value x
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8.8 AHB-AP Access Port
The AHB-AP is a Memory Access Port (MEM-AP) as defined in the ARM Debug Interface v5
Architecture Specification. The AHB-AP provides access to all memory and registers in the sys-
tem, including processor registers through the System Control Space (SCS). System access is
independent of the processor status. Either SW-DP or SWJ-DP is used to access the AHB-AP.
The AHB-AP is a master into the Bus Matrix. Transactions are made using the AHB-AP pro-
grammers model (please refer to the ARM Cortex-M4 Technical Reference Manual), which
generates AHB-Lite transactions into the Bus Matrix. The AHB-AP does not perform back-to-
back transactions on the bus, so all transactions are non-sequential. The AHB-AP can perform
unaligned and bit-ban d transactions. The Bus Matrix handle s these. The AHB-AP transactions
are not subject to MPU lookups. AHB-AP transactions bypass the FPB, and so the FPB cannot
remap AHB-AP transactions. AHB-AP tra nsactions are little-endian .
Note that while an external reset is applied, AHB-AP accesses are not possible. In addition,
access is denied when the protected state is set. In order to discard the protected state, a chip
erase operation is necessary.
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8.9 System Manager Access Port (SMAP)
Rev.: 1.0.0.0
8.9.1 Features •Chi p Era s e c om m and and status
•Cortex-M4 core reset source
•32-bit Cyclic Redundancy check of any memory accessible through the bus matrix
•Unlimited Flash User page read access
•Chip identification register
8.9.2 Overview The SMAP pr ovides memory- rel ated services a nd also Cor tex-M4 core r eset co nt rol t o a d ebu g-
ger through the Debug Port. This makes possible to halt the CPU and program the device after
reset.
8.9.3 Block Diagram
Figure 8-7. SMAP Block Diagram
8.9.4 Initializing the Module
The SMAP can be accessed only if the CPU clock is running and the SWJ-DP has been acti-
vated by issuing a CDBGPW RUP request. For more details , refer to the ARM Debug Interfa ce
v5.1 Architecture Specification.
Then it must be enabled by writing a one to the EN bit of the CR register (CR.EN) before writing
or reading other registers. If the SMAP is not enabled it will discard any read or write operation.
8.9.5 Stopping the Module
To stop the module, the user must write a one to the DIS bit of the CR register (CR.DIS). All the
user interface and internal registers will be cleared and the internal clock will be stopped.
SMAP Core reset request
DAP Bus
System
Bus Matrix
AHB
chip_erase Flash
Controller
AHB
SMAP
Ahb_Master
Core
DAP
Interface
Reset
Controller
PM
Cortex-M4 core reset
System reset
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8.9.6 Security Considerations
In protected state this module may access sensible information located in the device memories.
To avoid any risk of sensible data extraction from the module registers, all operations are non
interruptible except by a disable co mmand triggered by writing a one to CR.DIS. Issuing this
command clears all the interface and internal registers.
Some registers have some special protection:
• It is not possible to read or write the LENGTH register when t he part is protected.
• In addition, when the part is protected and an operation is ongoing, it is not possible to read
the ADDR and DATA registers. O nce an opera tion has started, the user has to wait until it has
terminated by polling t he DONE field in the Status Register (SR. DONE).
8.9.7 Chip Erase The Chip erase operation consists in:
1. clearing all the vol atile memories in the system
2. clearing the whole flash array
3. clearing the protected state
No proprietary or sensitive information is left in volatile memories once the protected state is
disabled.
This feature is operat ed by writing a one to the CE bit of the Contro l Register (CR.CE). When the
operation completes, SR.DONE is asserted.
8.9.8 Cortex-M4 Core Reset Source
The SMAP processes the EDP Core hold reset requ ests (Refer to Section 1.1.8 ”SMAP Core
Reset Request Source” on page 6). When requested, it instructs the Power Manager to hold the
Cortex-M4 core under reset.
The SMAP can de-assert the core reset request if a one is written to the Hold Core Reset bit in
the Status Clear Register (SCR.HCR). This has the effect of releasing the CPU from its reset
state. To assert again this signal, a new reset sequence with TCK tied low must be issued.
Note that clearing HCR with this module is only possible when it is enabled, for more inf ormation
refer to Section 8.9.4 ” Initializing the Module” on page 78. Also note that asserting RESET_N
automatically clears HCR.
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8.9.9 Unlimited Flash User Page Read Access
The SMAP can access the User page even if the protected state is set. Prior to operate such an
access, the user should check that the module is not busy by checking that SR.STATE is equal
to zerp. Once the offset of the word to access inside the page is written in ADDR.ADDR, the
read operation can be initiated by writing a one in CR.FSPR. The SR.STATE field will indicate
the FSPR state. Addresses written to ADDR.ADDR must be world aligned. Failing to do so will
result in unpredictable behavior. The result can be read in the DATA register as soon as
SR.DONE rises. The ADDR field is used as an offset in the page, bits outside a page boundary
will be silently discarded. The ADDR register is automatically incremented at the end of the read
operation making possible to dump consecutive words without writing the next offset into
ADDR.ADDR.
8.9.10 32-bit Cyclic Redundancy Check (CRC)
The SMAP unit provides support for calculati ng a Cyclic Redundancy Check (CRC) value for a
memory area. The a lgor it hm used is t he indust ry stand ar d CRC32 algor ith m u sing th e gen erat or
polynomial 0xEDB88320.
8.9.10.1 Starting CRC Calculation
To calculate CRC for a memory range, the start address must be written into the ADDR register,
and the size of the memory range into the LENGTH register. Both the start address and the
length must be word aligned.
The initial value used for the CRC calculation must be written to the DATA register. This value
will usually be 0xFFFFFFFF, but can be e.g. the result of a previous CRC calculation if generat-
ing a common CRC of separate memory blocks.
Once completed, the calculated CRC value can be read out of the DATA register. The read
value must be inverted to match st andard CR C32 imple menta tions, or kept non- inverte d if used
as starting point for subsequent CRC calculations.
If the device is in protected stat e, it is only possible to calculate the CRC of the whole flash arr ay.
In most cases this area will be the entire onboard nonvolatile memory. The ADDR, LENGTH,
and DATA registers will be forced to predefined values once the CRC operation is started, and
user-written values ar e igno red. Th is allows t he us er to ver if y the con te nts of a pr ot ected d evice.
The actual test is started by writing a one in CR.CRC. A running CRC operation can be can-
celled by disabling the module (write a one in CR.DIS). This has the effect of resetting the
module. The module has to be restarted by issuing an enable command (write a one in CR.EN).
8.9.10.2 Interpreting the Results
The user should monitor the SR register (Refer to Section 8.9.11.2 ”Status Register” on page
83). When the operation is completed SR.DONE is set. Then the SR.BERR and SR.FAIL must
be read to ensure that no bus error nor functional error occured.
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8.9.11 SMAP User Interface
Note: 1. The reset value for this register is device specific. Refer to the Module Configuration section at the end of this chapter.
2. CR.MBIST is ignored
3. SCR.HCR is ignored
4. Access is not allowed when an operation is ongoing
Table 8-9. SMAP Register Memory Map
Offset Register Register Name Access
(unprotected) Access
(protected) Reset
0x0000 Control Register CR Write-Only Write-Only (partial)(2) 0x00000000
0x0004 Status Register SR Read-Only Read-Only 0x00000000
0x0008 Status Clear Register SCR Write-Only Write-Only (partial)(3) 0x00000000
0x000C Address Register ADDR Read/Write Read/Write (partial)(4) 0x00000000
0x0010 Length Register LENGTH Read/Write denied 0x00000000
0x0014 Data Register DATA Read/Write Read/Write (partial)(4) 0x00000000
0x0028 VERSION Register VERSION Read-Only Read-Only -(1)
0x00F0 Chip ID Register CIDR Read-Only Read-Only -(1)
0x00F4 Chip ID Extension Register EXID Read-Only Read-Only -(1)
0x00FC AP Identification register IDR Read-Only Read-Only 0x003E0000
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8.9.11.1 Control Register
Name: CR
Access Type: Write-Only
Offset: 0x00
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
• CE: Chip Erase
Writing a one to this bit triggers the FLASH Erase All (EA) operation which clears all volatile memories, the whole flash array, the
general purpose fuses and the protected state. The Status register DONE field indicates the comp letion of the operation.
Reading this bit always returns 0
• FSPR: Flash User Page Read
Writing a one to this bit triggers a read operation in the User page. The word pointed by the ADDR register in the page is read
and written to the DATA register. ADDR is post incremented allowing a burst of reads without modifying ADDR. SR.DONE must
be read high prior to reading the DATA register.
Reading this bit always returns 0
• CRC: Cyclic Redundancy Code
Writing a one triggers a CRC calculation over a memory area defined by the ADDR and LENGTH registers. Reading this bit
always returns 0
Note: This feature is restri cted while in protected state
•DIS: Disable
Writing a one to this bit disables the module. Disabling the module resets the whole module immediately.
• EN: Enable
Writing a one to this bit enables the module.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - CE FSPR CRC DIS EN
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8.9.11.2 Status Register
Name: SR
Access Type: Read-Only
Offset: 0x04
Reset Value: 0x00000000
•STATE: State
• DBGP: Debugger present
1: A debugger is present (TCK falling edge detected)
0: No debugger is present
•PROT: Protected
1: The protected state is set. The only way to overcome this is to issue a Chip Erase command.
0: The protected state is not set
• EN: Enabled
1: The block is in ready for operation
0: the block is disabled. Write operations are not possible until the block is enabled by writing a one in CR.EN.
•LCK: Lock
1: An operation could not be performed because chip pr otected state is on.
0: No security issues have been detected sincle last clear of this bit
• FAIL: Fa ilure
1: The requested operation failed
0: No failure has been detected sincle last clear of this bit
• BERR: Bus Error
1: A bus error occured due to the unability to access part of the requested memory area.
31 30 29 28 27 26 25 24
----- STATE
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-----DBGPPROTEN
76543210
- - - LCK FAIL BERR HCR DONE
Value State Description
0IDLE Idle state
1CE Chip erase operation is ongoing
2CRC32 CRC32 operation is ongoing
3FSPR Flash User Page Read
4-7 - reserved
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0: No bus error has been detected sincle last clear of this bit
• HCR: Hold Core reset
1: The Cortex-M4 core is held under reset
0: The Corte x-M4 core is not held under reset
• DONE: Operation done
1: At least one operation has ter mi nated since last clear of this field
0: No operation has terminated since last clear of this field
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8.9.11.3 Status Clear Register
Name: SCR
Access Type: Write-Only
Offset: 0x08
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit clears the corresponding SR bit
Note: Writing a one to bit HCR while the chip is in protected state has no effect
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - LCK FAIL BERR HCR DONE
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8.9.11.4 Address Register
Name: ADDR
Access Type: Read/Write
Offset: 0x0C
Reset Value: 0x00000000
• ADDR: Address Value
Addess values are always world aligned
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR - -
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8.9.11.5 Length Register
Name: LENGTH
Access Type: Read/Write
Offset: 0x10
Reset Value: 0x00000000
• LENGTH: Le ng th Value, Bits 1-0 ar e always zero
31 30 29 28 27 26 25 24
LENGTH
23 22 21 20 19 18 17 16
LENGTH
15 14 13 12 11 10 9 8
LENGTH
76543210
LENGTH - -
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8.9.11.6 Data Register
Name: DATA
Access Type: Read/Write
Offset: 0x14
Reset Value: 0x00000000
• DATA: Generic data register
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
76543210
DATA
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8.9.11.7 Module Version
Name: VERSION
Access Type: Read-Only
Offset: 0x28
Reset Value: -
• VARIANT: Variant number
Reserved. No functionality associated.
• VERSION: Version number
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- VARIANT
15 14 13 12 11 10 9 8
---- VERSION
76543210
VERSION
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8.9.11.8 Chip Identificati on Reg iste r
Name: CIDR
Access Type: Read-Only
Offset: 0xF0
Reset Value: -
Note: Refer to section CHIPID for more information on this register.
31 30 29 28 27 26 25 24
EXT NVPTYP ARCH
23 22 21 20 19 18 17 16
ARCH SRAMSIZ
15 14 13 12 11 10 9 8
NVPSIZ2 NVPSIZ
76543210
EPROC VERSION
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8.9.11.9 Chip Identification Extension Register
Name: EXID
Access Type: Read-Only
Offset: 0xF4
Reset Value: -
Note: Refer to section CHIPID for more information on this register.
31 30 29 28 27 26 25 24
EXID
23 22 21 20 19 18 17 16
EXID
15 14 13 12 11 10 9 8
EXID
76543210
EXID
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8.9.11.10 Ide ntification Register
Name: IDR
Access Type: Read-Only
Offset: 0xFC
Reset Value: -
• REVISION: Revision
• CC: JEP-106 Continuation Code
Atmel continuation code is 0x0
• IC: JEP-106 Identity Code
Atmel identification code is 0x1F
• CLSS: Class
0: This AP is not a Memory Access P ort
1: This AP is a Memory Access Port
• APID: AP Identification
• APIDV: AP Identification Variant
For more informatio n about this register, refer to the ARM Debug Interface v5.1 Architecture
Specification document.
31 30 29 28 27 26 25 24
REVISION CC
23 22 21 20 19 18 17 16
IC CLSS
15 14 13 12 11 10 9 8
Reserved
76543210
APID APIDV
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8.10 Available Features in Protected State
Table 8-10. Features av ailablility when in protected state
Feature Provider Availability when protected
Hot plugging EDP yes
System bus R/W Access AHB-AP no
Flash User Page read access SMAP yes
Core Hold Reset clear from the SMAP interface SMAP no
CRC32 of any memory accessible through the bus matrix SMAP restricted (limited to the entire flash array)
Chip Erase SMAP yes
IDCODE SMAP yes
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8.11 Functional Description
8.11.1 Debug Environment
Figure 8-8 shows a complete debug environment example. The SWJ-DP interface is used for
standard debugging functions, such as downloading code and single-stepping through the pro-
gram and viewing core and peripheral registers.
Figure 8-8. Application Debug Environment Example
8.11.2 Test Environment
Figure 8-9 shows a test environ ment e xample (JTAG Boundar y scan). Te st vectors a re sent and
interpreted by the teste r. In this example, the “board in test” is designed using a number of
JTAG-compliant devices. These devices can be connected to form a sing le scan chain.
SAM4
Host Debugger
PC
SAM4-based Application Board
SWJ-DP
Connector
SWJ-DP
Emulator/Probe
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Figure 8-9. Application Test Environment Example
8.11.3 How to initialize test and debug features
To enable the JTAG pins a falling edge event must be detected on the TCK pin at any time after
the RESET_N pin is released.
Certain operations requires that the system is prevented from running code after reset is
released. This is done by holding low the T CK pin after the RESET_N is released . This makes
the SMAP assert the core_hold_reset signal that hold the Cortex-M4 core under reset.
To make the CPU run again, clear the CHR bit in the Status Register (SR.CHR) to de-assert the
core_hold_reset signal. Independent of the initial state of the TAP Controller, the Test-Logic-
Reset state can always be ent ered by h olding TM S high f or 5 T CK clock perio ds. This sequen ce
should always be applie d at the start of a JTAG session and after enabling the JTAG pins to
bring the TAP Cont roller into a def ined state b efore applyin g JTAG command s. Applying a 0 o n
TMS for 1 TCK period brings the TAP Controller to the Run-Test/Idle state, which is the starting
point for JTAG operations.
8.11.4 How to disable test and debug features
To disable the JTAG pins the TCK pin must be held high while RESET_N pin is released.
8.11.5 Typical JTAG sequence
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
8.11.5.1 Scanning in JTAG instruction
At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
Instruction Registe r - Shift-IR state. While in this state, shift the 4 bits of the JTAG instructions
into the JTAG instruction register from the TDI input at the rising edge of TCK. The TMS input
must be held low during input of the 4 LSBs in order to remain in the Shift-IR state. The JTAG
Instruction selects a particular Data Register as path between TDI and TDO and cont rols the cir-
cuitry surroundin g the selected Data Register.
Chip 2
Chip n
Chip 1
SAM4
SAM4-based Application Board In Test
JTAG
Connector
Tester
Test Adaptor
JTAG
Probe
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Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched
onto the par allel output from the shif t register path in the Update -IR state. The Exit-IR, Pa use-IR,
and Exit2-IR states are only used for navigating the state machine.
Figure 8-10. Scanning in JTAG instruction
8.11.5.2 Scanning in/out data
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data
Register - Shift-DR state. While in this state, upload the selected Data Register (selected by the
present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge
of TCK. In order to remain in the Shift-DR state, the T MS input m ust b e he ld low. Wh ile t he Da ta
Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the
Capture-DR state is shif ted out on the TDO pin.
Apply the TMS sequence 1, 1, 0 to re-enter the Ru n-Test/Idle state. If the selected Data Register
has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR,
Pause-DR, and Exit2-DR states are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered betwe en selecting
JTAG instruction and using Data Registers.
8.11.6 Boundary-Scan
The Boundary-Scan chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by
the TDI/TDO signals to form a long shift register. An external controller sets up the devices to
drive values at their output pins, and observe the input values received from other devices. The
controller compares the received data with the expected result. In this way, Boundary-Scan pro-
vides a mechanism for testing interconnections and integrity of components on Printed Circuits
Boards by using the 4 TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-
LOAD, and EXTEST can be used for testing the Printed Circuit Board. Initial scanning of the
data register path will show the ID-code of the device, since IDCODE is the default JTAG
instruction. It may be desirable to have the device in reset during test mode. If not reset, inputs
to the device may be d etermined by the scan operations, and the internal software may be in an
undetermined state when exiting the test mode. Entering reset, the outputs of any Port Pin will
instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed,
the BYPASS instruction can be issued to make the shortest possible scan chain through the
device. The device can be set in the reset state by pulling the external RESET_N pin low.
The EXTEST instruction is used for sampling external pins and lo ading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial value s to the scan r ing, to avoid da maging the board when issuing the EXT EST
TCK
TAP State TLR RTI SelDR SelIR CapIR ShIR Ex1IR UpdIR RTI
TMS
TDI Instruction
TDO ImplDefined
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instruction for the first tim e. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins duri ng normal operation of the part.
When using the JTAG interface for Boundary-Scan, the JTAG TCK clo ck is independent of the
internal chip clock, which is not required to run.
NOTE: For pins connected to 5V lines care should be taken to not drive the pins to a logic one
using boundary scan, as this will create a current flowing from the 3,3V driver to the 5V pullup on
the line. Optionally a series resistor can be added between the line and the pin to reduce the
current.
8.11.7 Flash Programming typical procedure
Flash programming is performed by operating Flash controller commands. The Flash controller
is connected to the system bus matrix and is then controllable from the AHP-AP. The AHB-AP
cannot write the FLASH page buffer while the core_hold_reset is asserted. The AHB-AP cannot
be accessed when the device is in protected state. It is important to ensure that the CPU is
halted prior to operating any flash programming operation to prevent it from corrupting the sys-
tem configuration. The recommended sequence is shown below:
1. At power up, RESET_N is driven low by a debugger. The on-chip regulator holds the
system in a POR state until the input supply is above the POR threshold. The system
continues to be held in this static state until the internally regulated supplies have
reached a safe operating.
2. PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash
Clock, and any Bus Clocks that do not have clock gate control). Internal resets are
maintained due to the external reset.
– The Debug Port (DP) and Access Ports (AP) receives a clock and leave the reset
state,
3. The debugger maintains a low level on TCK and release RESET_N.
– The SMAP asserts the core_hold_reset signal
4. The Cortex-M4 core remains in reset state, meanwhile the rest of the sys tem is
released.
5. The debugger th en configu res the NVIC t o catch the Corte x-M4 core reset v e ctor f e tch.
For more information on how to program the NVIC, refer to the ARMv7-M Architecture
Reference Manual.
6. The deb ugger writes a one in t he SMAP SCR.HCR to r elease the Cortex-M4 core reset
to make the system bus matrix accessible from the AHB-AP.
7. The Cortex-M4 core initializes the SP, then read the exception vector and stalls
8. Programming is available through the AHB-AP
9. After operation is completed, the chip can be restarted either by asserting RESET_N or
switching po w e r off /on or cle aring SCR.HCR. Make sure that the TCK pin is high when
releasing RESET _N no t to halt th e core.
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8.11.8 Chip erase typical procedure
The chip erase operation is triggered by writing a one in the CE bit in the Control Register
(CR.CE). This clears first all volatile memories in the system and second the whole flash array.
Note that the User page is not erased in this process. To ensure that the chip erase operation is
completed, check the DONE bit in the St atus Register (SR.DONE). Also note th at the chip e rase
operation depends on clocks and power management features that can be altered by the CPU.
It is important to ensure that it is stopped. The recommended sequence is shown below:
1. At power up, RESET_N is driven low by a debugger. The on-chip regulator holds the
system in a POR state until the input supply is above the POR threshold. The system
continues to be held in this static state until the internally regulated supplies have
reached a safe operating.
2. PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash
Clock, and any Bus Clocks that do not have clock gate control). Internal resets are
maintained due to the external reset.
– The debug port and access ports receives a clock and leave the reset state
3. The debugger maintains a low level on TCK and release RESET_N.
– The SMAP asserts the core_hold_reset signal
4. The Cortex-M4 core remains in reset state, meanwhile the rest of the sys tem is
released.
5. The Chip erase operat ion can be performed by issuing the SMAP Chip Erase com-
mand. In this case:
– volatile memories are cleared first
– followed by the clearing of the flash array
– followed by the clearing of the protected st ate
6. After opera tion is comp let ed, the ch ip m ust be restarted by either con troling RESET _N
or switching power off/on. Make sure that the TCK pin is high when releasing
RESET_N not to halt the core.
8.11.9 Setting the protected state
This is done by issuing a specific flash controller command, for more informatio n, refer to the
Flash Controller chapter and to section 8.11.7Flash Programming t ypical procedure97. The pro-
tected state is defined by a highly secure Flash builtin mechanism. Note that for this
programmation to propagate, it is required to reset the chip.
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9. Electrical Characteristics
9.1 Absolute Maximum Ratings*
9.2 Operating Conditions
All the electrical characteristics are applicable to the following conditions unless otherwise spec-
ified :
– operating voltage range 1,68V to 3,6V for VDDIN, VDDIO & VDDANA
– Power Scaling 0 and 2 modes
– operating temperature range: TA = -40°C to 85°C and for a junction temperature up
to TJ = 100°C.
Typical values are base on TA = 25°c and VDDIN,VDDIO,VDDANA = 3,3V unless otherwise
specified
9.3 Supply Characteristics
Refer to Section 6. ”Power and Startup Considerations” on page 46 for details about Power
Supply
Table 9-1. Absolute Maximum Ratings
Operating temperature..................................... -40°C to +85°C*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage temperature...................................... -60°C to +150°C
Voltage on input pins
with respect to ground ..........................-0.3V to VVDD (1)+0.3V
1. VVDD corresponds to either VVDDIN or VVDDIO, dependi ng on the supply for the pin. Refer to Section 3-5 on page 13 for details
Total DC output current on all I/O pins
VDDIO ......... ............................ ... ............................ .. ... 120 mA
Total DC output current on all I/O pins
VDDIN ........................................................................ 100 mA
Total DC output current on all I/O pins
VDDANA................. .............. ... .............. ... .............. .. ..... 50 mA
Maximum operating voltage VDDIO, VDDIN.................... 3.6V
Table 9-2. Supply Characteristic s
Symbol Conditions
Voltage
Min Max Unit
VVDDIO,
VVDDIN,
VVDDANA
PS1 (FCPU<=12MHz)
Linear mode 1.68
3.6 VPS0 & PS2 (FCPU>12MHz)
Linear mode 1.8
Switching mode 2.0 (1)
1. Below 2.3V, linear mode is more power efficient than switching mode.
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Table 9-3. Supply Rise Rates and Order (1)
VDDIO, VDDIN and VDDANA must be connected together and as a consequence, rise
synchronously
1. These val ues are based on characterization. These values are not covered by test limits in
production.
Symbol Parameter
Rise Rate
Min Max Unit Comment
VVDDIO DC supply peripheral I/Os 0.0001 2.5 V/µs
VVDDIN DC supply peripheral I/Os
and internal regulator 0.0001 2.5 V/µs
VVDDANA Analog supply voltage 0.0001 2.5 V/µs
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9.4 Maximum Clock Frequencies
Table 9-4. Maximum Clock Frequencies in Power Scaling Mode 0/2 and RUN Mode
Symbol Parameter Description Max Units
fCPU CPU clock frequency 48
MHz
fPBA PBA clock frequency 48
fPBB PBB clock frequency 48
fPBC PBC clock frequency 48
fPBD PBD clock frequency 48
fGCLK0 GCLK0 clock frequency DFLLIF main reference, GCLK0 pin 50
fGCLK1 GCLK1 clock frequency DFLLIF dithering and SSG reference ,
GCLK1 pin 50
fGCLK2 GCLK2 clock frequency AST, GCLK2 pin 20
fGCLK3 GCLK3 clock frequency CATB, GCLK3 pin 50
fGCLK4 GCLK4 clock frequency FLO and AESA 50
fGCLK5 GCLK5 clock frequency GLOC, TC0 and RC32KIFB_REF 80
fGCLK6 GCLK6 clock frequency ABDACB and IISC 50
fGCLK7 GCLK7 clock frequency USBC 50
fGCLK8 GCLK8 clock frequency TC1 and PEVC[0] 50
fGCLK9 GCLK9 clock frequency PLL0 and PEVC[1] 50
fGCLK10 GCLK10 clock
frequency ADCIFE 50
fGCLK11 GCLK11 clock
frequency Master generic clock. Can be used as
source for other generic clocks 150
fOSC0 OSC0 output frequen cy Oscillator 0 in crystal mode 30
Oscillator 0 in dig i ta l cl ock mode 50
fPLL PLL output frequency Phase Locked Loop 240
fDFLL DFLL output frequency Digital Frequency Locked Loop 220
fRC80M RC80M output
frequency Internal 80MHz RC Oscillator 80
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Table 9-5. Maximum Clock Frequencies in Power Scaling Mode 1 and RUN Mode
Symbol Parameter Description Max Units
fCPU CPU clock frequency 12
MHz
fPBA PBA clock frequency 12
fPBB PBB clock frequency 12
fPBC PBC clock frequency 12
fPBD PBD clock frequency 12
fGCLK0 GCLK0 clock frequency DFLLIF main reference, GCLK0 pin 16.6
fGCLK1 GCLK1 clock frequency DFLLIF dithering and SSGreference ,
GCLK1 pin 16.6
fGCLK2 GCLK2 clock frequency AST, GCLK2 pin 6.6
fGCLK3 GCLK3 clock frequency CATB, GCLK3 pin 17.3
fGCLK4 GCLK4 clock frequency FLO and AESA 16.6
fGCLK5 GCLK5 clock frequency GLOC, TC0 and RC32KIFB_REF 26.6
fGCLK6 GCLK6 clock frequency ABDACB and IISC 16.6
fGCLK7 GCLK7 clock frequency USBC 16.6
fGCLK8 GCLK8 clock frequency TC1 and PEVC[0] 16.6
fGCLK9 GCLK9 clock frequency PLL0 and PEVC[1] 16.6
fGCLK10 GCLK10 clock
frequency ADCIFE 16.6
fGCLK11 GCLK11 clock
frequency Master generic clock. Can be used as
source for other generic clocks 51.2
fOSC0 OSC0 output frequen cy Oscillator 0 in crystal mode 16
Oscillator 0 in dig i ta l cl ock mode 16
fPLL PLL output frequency Phase Locked Loop N/A
fDFLL DFLL output frequency Digital Frequency Locked Loop N/A
fRC80M RC80M output
frequency Internal 80MHz RC Oscillator N/A
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9.5 Power Consumption
9.5.1 Power Scaling 0 and 2
The values in Table 9-6 are measured values of power consumption under the following condi-
tions, except where noted:
• Operating conditions for power scaling mode 0 and 2
–V
VDDIN = 3.3V
– Power Scaling mode 0 is used for CPU frequencies under 36MHz
– Power Scaling mode 2 is used for CPU frequencies above 36MHz
• Wake up time from low power modes is measured from the edge of the wakeup signal to the
first instruction fetched in flash.
• Oscillators
– OSC0 (crystal oscillator) stopped
– OSC32K (32kHz crystal oscillator) running with ex ternal 32kHz crystal
– DFLL using OSC32K as reference and running at 48MHz
• Clocks
– DFLL used as main clock source
– CPU, AHB clocks undivided
– APBC and APBD clocks divided by 4
– APBA and APBB bridges off
– The followin g peripheral clocks running
• PM, SCIF, AST, FLASHCALW, APBC and APBD bridges
– All other peripheral clocks stopped
• I/Os are inactive with internal pull-up
• CPU is running on flash with 1 wait state
• Low power cache enabled
• BOD18 and BOD33 disabled
Table 9-6. ATSAM4L4/2 Current consumption and Wa keup time for power scaling mode 0 and 2
Mode Conditions TA
Typical
Wakeup Time Typ Max (1) Unit
RUN
CPU running a Fibon a cci al go rithm
Linear mode 25°C N/A 296 326
µA/MHz
85°C 300 332
CPU running a CoreMark algorithm
Linear mode 25°C N/A 320 377
85°C 326 380
CPU running a Fibon a cci al go rithm
Switching mode 25°C N/A 177 198
85°C 179 200
CPU running a CoreMark algorithm
Switching mode 25°C N/A 186 232
85°C 195 239
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SLEEP0 Switching mode 25°C 9 * Main clock
cycles 3817 4033
µA
85°C 3934 4174
SLEEP1 Switching mode 25°C 9 * Main clock
cycles + 500ns 2341 2477
85°C 2437 2585
SLEEP2 Switching mode 25°C 9 * Main clock
cycles + 500ns 1758 1862
85°C 1847 1971
SLEEP3 Linear mode
25°C
51 60
WAIT
OSC32K and AST running
Fast wake-up enable 1.5µs 5.9 8.7
OSC32K and AST stopped
Fast wake-up enable 4.7 7.6
RETENTION OSC32K running
AST running at 1kHz 1.5µs 3.1 5.1
AST and OSC32K stopped 2.2 4.2
BACKUP OSC32K running
AST running at 1kHz 1.5 3.1
AST and OSC32K stopped 0.9 1.7
1. These valu es are based on characterization. These values are not covered by test limits in production.
Table 9-6. ATSAM4L4/2 Current consumption and Wa keup time for power scaling mode 0 and 2
Mode Conditions TA
Typical
Wakeup Time Typ Max (1) Unit
Table 9-7. ATSAM4L8 Current consumption and Wakeup time for power scaling mode 0 and 2
Mode Conditions TA
Typical
Wakeup Time Typ Max (1) Unit
RUN
CPU running a Fibon a cci al go rithm
Linear mode 25°C N/A 319 343
µA/MHz
85°C 326 350
CPU running a CoreMark algorithm
Linear mode 25°C N/A 343 387
85°C 351 416
CPU running a Fibon a cci al go rithm
Switching mode 25°C N/A 181 198
85°C 186 203
CPU running a CoreMark algorithm
Switching mode 25°C N/A 192 232
85°C 202 239
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9.5.2 Power Scaling 1
The values in Table 34-7 are measured values of power consumption under the following condi-
tions, except where noted:
• Operating cond itions for power scaling mode 1
–V
VDDIN = 3.3V
• Wake up time from low power modes is measured from the edge of the wakeup signal to the
first instruction fetched in flash.
• Oscillators
– OSC0 (crystal oscillator) and OSC32K (32kHz crystal oscillator) stopped
– RCFAST Running at 12MHz
• Clocks
– RCFAST used as main clock source
– CPU, AHB clocks undivided
– APBC and APBD clocks divided by 4
– APBA and APBB bridges off
– The followin g peripheral clocks running
• PM, SCIF, AST, FLASHCALW, APBC and APBD bridges
SLEEP0 Switching mode 25°C 9 * Main clock
cycles 3817 4033
µA
85°C 4050 4507
SLEEP1 Switching mode 25°C 9 * Main clock
cycles + 500ns 2341 2477
85°C 2525 2832
SLEEP2 Switching mode 25°C 9 * Main clock
cycles + 500ns 1758 1862
85°C 1925 1971
SLEEP3 Linear mode
25°C
51 60
WAIT
OSC32K and AST running
Fast wake-up enable 1.5µs 6.7
OSC32K and AST stopped
Fast wake-up enable 5.5
RETENTION OSC32K running
AST running at 1kHz 1.5µs 3.9
AST and OSC32K stopped 3.0
BACKUP OSC32K running
AST running at 1kHz 1.5 3.1
AST and OSC32K stopped 0.9 1.7
1. These valu es are based on characterization. These values are not covered by test limits in production.
Table 9-7. ATSAM4L8 Current consumption and Wakeup time for power scaling mode 0 and 2
Mode Conditions TA
Typical
Wakeup Time Typ Max (1) Unit
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– All other peripheral clocks stopped
• I/Os are inactive with internal pull-up
• CPU is running on flash with 1 wait state
• Low power cache enabled
• BOD18 and BOD33 disabled
Table 9-8. ATSAM4L4/2 Current consumption and Wakeup time for power scaling mode 1
Mode Conditions TA
Typical
Wakeup Time Typ Max (1) Unit
RUN
CPU running a Fibon a cci al go rithm
Linear mode 25°C N/A 205 224
µA/MHz
85°C 212 231
CPU running a CoreMark algorithm
Linear mode 25°C N/A 213 244
85°C 230 270
CPU running a Fibon a cci al go rithm
Switching mode 25°C N/A 95 112
85°C 100 119
CPU running a CoreMark algorithm
Switching mode 25°C N/A 100 128
85°C 107 138
SLEEP0 Switching mode 25°C 9 * Main clock
cycles 527 627
µA
85°C 579 739
SLEEP1 Switching mode 25°C 9 * Main clock
cycles + 500ns 369 445
85°C 404 564
SLEEP2 Switching mode 25°C 9 * Main clock
cycles + 500ns 305 381
85°C 334 442
SLEEP3 Linear mode
25°C
46 55
WAIT
OSC32K and AST running
Fast wake-up enable 1.5µs 4.7 7.5
OSC32K and AST stopped
Fast wake-up enable 3.5 6.3
RETENTION OSC32K running
AST running at 1kHz 1.5µs 2.6 4.8
AST and OSC32K stopped 1.5 4
BACKUP OSC32K running
AST running at 1kHz 1.5 3.1
AST and OSC32K stopped 0.9 1.7
1. These valu es are based on characterization. These values are not covered by test limits in production.
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Table 9-9. ATSAM4L8 Current consumption and Wakeup time for power scaling mode 1
Mode Conditions TA
Typical
Wakeup Time Typ Max (1) Unit
RUN
CPU running a Fibon a cci al go rithm
Linear mode 25°C N/A 222 240
µA/MHz
85°C 233 276
CPU running a CoreMark algorithm
Linear mode 25°C N/A 233 276
85°C 230 270
CPU running a Fibon a cci al go rithm
Switching mode 25°C N/A 100 112
85°C 100 119
CPU running a CoreMark algorithm
Switching mode 25°C N/A 104 128
85°C 107 138
SLEEP0 Switching mode 25°C 9 * Main clock
cycles 527 627
µA
85°C 579 739
SLEEP1 Switching mode 25°C 9 * Main clock
cycles + 500ns 369 445
85°C 404 564
SLEEP2 Switching mode 25°C 9 * Main clock
cycles + 500ns 305 381
85°C 334 442
SLEEP3 Linear mode
25°C
46 55
WAIT
OSC32K and AST running
Fast wake-up enable 1.5µs 5.5
OSC32K and AST stopped
Fast wake-up enable 4.3
RETENTION OSC32K running
AST running at 1kHz 1.5µs 3.4
AST and OSC32K stopped 2.3
BACKUP OSC32K running
AST running at 1kHz 1.5 3.1
AST and OSC32K stopped 0.9 1.7
1. These valu es are based on characterization. These values are not covered by test limits in production.
Table 9-10. Typical Power Consumption running CoreMark on CPU clock sources (1)
Clock Source Conditions Regulator Frequency
(MHz) Typ Unit
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RCSYS
(MCSEL = 0) Power scaling mode 1
Switching
Mode
0.115 978
µA/MHz
OSC0
(MCSEL = 1)
Power scaling mode 1 0.5 354
12 114
Power scaling mode 0 12 228
30 219
OSC0
(MCSEL = 1)
Exter nal Clock
(MODE=0)
Power scaling mode 1 0.6 292
12 111
Power scaling mode 0 12 193
Power scaling mode 2 50 194
PLL
(MCSEL = 2) Power scaling mode 2
Input Freq = 4MHz from OSC0 40 188
50 185
DFLL
(MCSEL = 3)
Power scaling mode 0
Input Freq = 32kHz from OSC32K 20 214
Power scaling mode 2
Input Freq = 32kHz from OSC32K 50 195
RC1M
(MCSEL = 4) Power scaling mode 1 1 267
RCFAST
(MCSEL = 5) Power scaling mode 1
RCFAST frequency is configurable from 4 to 12MHz 4153
12 114
RC80M
(MCSEL = 6) Power scaling mode 2
fCPU = RC80M / 2 = 40MHz 40 211
1. These valu es are based on characterization. These values are not covered by test limits in production.
Table 9-10. Typical Power Consumption running CoreMark on CPU clock sources (1)
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Figure 9-1. Typical Power Consumption running Coremark (from above table)
Note: For variable frequency oscillators, linear interpolation between high and low settings
Figure 9-2. Measurement Schematic, Switching Mode
VDDIN
VDDOUT
VDDCORE
VDDIO
VDDANA
Amp 0
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9.5.3 Peripheral Power Consumption in Power Scaling mode 0 and 2
The values in Table 9-11 are measured values of power consumption under the following
conditions:
• Operating cond itions, internal core supply (Figure 9-2)
–V
VDDIN = 3.3V
–V
VDDCORE supplied by the internal regulator in switching mode
•T
A = 25°C
• Oscillators
– OSC0 (crystal oscillator) stopped
– OSC32K (32KHz crystal oscillator) running with external 32KHz crystal
– DFLL running at 48MHz with OSC32K as reference clock
• Clocks
– DFLL used as main clock source
– CPU, AHB, and PB clocks undivided
• I/Os are inactive with internal pull-up
• Flash enabled in high speed mode
• CPU in SLEEP0 mode
• BOD18 and BOD33 disabled
Consumption active is the added current consumptio n when the module clock is turned on.
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9.5.4 .Peripheral Power Consumption in Power Scaling mode 1
The values in Table 9-13 are measured values of power consumption under the following
conditions:
Table 9-11. Typical Current Consumption by Peripheral in Power Scaling Mode 0 and 2 (1)
1. These numbers are valid for the measured condition only and must not be extrapolated to other
frequencies
Peripheral Typ Consumption Active Unit
IISC 1.0
µA/MHz
SPI 1.9
TC 6.3
TWIM 1.5
TWIS 1.2
USART 8.5
ADCIFE(2) 3.1
DACC 1.3
ACIFC (2)
2. Includes the current consumption on VDDANA and ADVREFP.
3.1
GLOC 0.4
ABDACB 0.7
TRNG 0.9
PARC 0.7
CATB 3.0
LCDCA 4.4
PDCA 1.0
CRCCU 0.3
USBC 1.5
PEVC 5.6
CHIPID 0.1
SCIF 6.4
FREQM 0.5
GPIO 7.1
BPM 0.9
BSCIF 4.6
AST 1.5
WDT 1.4
EIC 0.6
PICOUART 0.3
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• Operating cond itions, internal core supply (Figure 9-2)
–V
VDDIN = 3.3V
–V
VDDCORE = 1.2 V, supplied by the internal regulator in switching mode
•T
A = 25°C
• Oscillators
– OSC0 (crystal oscillator) stopped
– OSC32K (32KHz crystal oscillator) running with external 32KHz crystal
– RCFAST running @ 12MHz
• Clocks
– RCFAST used as main clock source
– CPU, AHB, and PB clocks undivided
• I/Os are inactive with internal pull-up
• Flash enabled in normal mode
• CPU in SLEEP0 mode
• BOD18 and BOD33 disabled
Consumption active is the added current consumptio n when the module clock is turned on
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Table 9-12. Typical Current Consumption by Peripheral in Power Scaling Mode 1 (1)
1. These numbers are valid for the measured condition only and must not be extrapolated to other
frequencies
Peripheral Typ Consumption Active Unit
IISC 0.5
µA/MHz
SPI 1.1
TC 3.1
TWIM 0.8
TWIS 0.7
USART 4.4
ADCIFE(2) 1.6
DACC 0.6
ACIFC (2)
2. Includes the current consumption on VDDANA and ADVREFP.
1.6
GLOC 0.1
ABDACB 0.3
TRNG 0.3
PARC 0.3
CATB 1.5
LCDCA 2.2
PDCA 0.4
CRCCU 0.3
USBC 0.9
PEVC 2.8
CHIPID 0.1
SCIF 3.1
FREQM 0.2
GPIO 3.4
BPM 0.4
BSCIF 2.3
AST 0.8
WDT 0.8
EIC 0.3
PICOUART 0.2
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9.6 I/O Pin Characteristics
9.6.1 Normal I/O Pin
Table 9-13. Normal I/O Pin Characteristics (1)
1. VVDD corresponds to either VVDDIN or VVDDIO, dependi ng on the supply for the pin. Refer to Section 3-5 on page 13 for details
Symbol Parameter Conditions Min Typ Max Units
RPULLUP Pull-up resistance (2)
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization
40 kΩ
RPULLDOWN Pull-down resistance(2) 40 kΩ
VIL Input low-level voltage -0.3 0.2 * VVDD
V
VIH Input high-level voltage 0.8 * VVDD VVDD + 0.3
VOL Output low-level voltage 0.4
VOH Output high-level voltage VVDD - 0.4
IOL Output low-level current (3)
ODCR0=0 1.68V<VVDD<2.7V 0.8 mA
2.7V<VVDD<3.6V 1.6
ODCR0=1 1.68V<VVDD<2.7V 1.6 mA
2.7V<VVDD<3.6V 3.2
IOH Output high-lev el current(3)
ODCR0=0 1.68V<VVDD<2.7V 0.8 mA
2.7V<VVDD<3.6V 1.6
ODCR0=1 1.68V<VVDD<2.7V 1.6 mA
2.7V<VVDD<3.6V 3.2
tRISE Rise time(2)
OSRR0=0 ODCR0=0
1.68V<VVDD<2.7V,
load = 25pF
35 ns
OSRR0=1 45
OSRR0=0 ODCR0=0
2.7V<VVDD<3.6V,
load = 25pF
19 ns
OSRR0=1 23
tFALL Fall time(2)
OSRR0=0 ODCR0=0
1.68V<VVDD<2.7V,
load = 25pF
36 ns
OSRR0=1 47
OSRR0=0 ODCR0=0
2.7V<VVDD<3.6V,
load = 25pF
20 ns
OSRR0=1 24
FPINMAX Output frequency(2)
OSRR0=0 ODCR0=0, VVDD>2.7V
load = 25pF 17 MHz
OSRR0=1 15 MHz
OSRR0=0 ODCR0=1, VVDD>2.7V
load = 25pF 27 MHz
OSRR0=1 23 MHz
ILEAK Input leakage current(3) Pull-up resistors
disabled 0.01 1 µA
CIN Input capacitance(2) 5pF
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3. These valu es are based on characterization. These values are not covered by test limits in production
9.6.2 High-drive I/O Pin : PA02, PC04, PC05, PC06
Table 9-14. High-drive I/O Pin Characteristics (1)
Symbol Parameter Conditions Min Typ Max Units
RPULLUP Pull-up resistance (2) 40 kΩ
RPULLDOWN Pull-down resistance(2) 40 kΩ
VIL Input low-level voltage -0.3 0.2 * VVDD
V
VIH Input high-level voltage 0.8 * VVDD VVDD + 0.3
VOL Output low-level voltage 0.4
VOH Output high-level voltage VVDD - 0.4
IOL Output low-level current (3)
ODCR0=0 1.68V<VVDD<2.7V 1.8 mA
2.7V<VVDD<3.6V 3.2
ODCR0=1 1.68V<VVDD<2.7V 3.2 mA
2.7V<VVDD<3.6V 6
IOH Output high-lev el current(3)
ODCR0=0 1.68V<VVDD<2.7V 1.6 mA
2.7V<VVDD<3.6V 3.2
ODCR0=1 1.68V<VVDD<2.7V 3.2 mA
2.7V<VVDD<3.6V 6
tRISE Rise time(2)
OSRR0=0 ODCR0=0
1.68V<VVDD<2.7V,
Cload = 25pF
20 ns
OSRR0=1 40
OSRR0=0 ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
11 ns
OSRR0=1 18
tFALL Fall time(2)
OSRR0=0 ODCR0=0
1.68V<VVDD<2.7V,
Cload = 25pF
20 ns
OSRR0=1 40
OSRR0=0 ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
11 ns
OSRR0=1 18
FPINMAX Output frequency(2)
OSRR0=0 ODCR0=0, VVDD>2.7V
load = 25pF 22 MHz
OSRR0=1 17 MHz
OSRR0=0 ODCR0=1, VVDD>2.7V
load = 25pF 35 MHz
OSRR0=1 26 MHz
ILEAK Input leakage current(3) Pull-up resistor s dis abled 0.01 2 µA
CIN Input capacitance(2) 10 pF
1. VVDD corresponds to either VVDDIN or VVDDIO, dependi ng on the supply for the pin. Refer to Section 3-5 on page 13 for details
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization
3. These valu es are based on characterization. These values are not covered by test limits in production
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9.6.3 USB I/O Pin : PA25, PA26
9.6.4 TWI Pin : PA21, PA22, PA23, PA24, PB14, PB15
Table 9-15. USB I/O Pin Characteristics in GPIO configuration (1)
1. VVDD corresponds to either VVDDIN or VVDDIO, dependi ng on the supply for the pin. Refer to Section 3-5 on page 13 for details
Symbol Parameter Conditions Min Typ Max Units
RPULLUP Pull-up resistance (2)
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization
40 kΩ
RPULLDOWN Pull-down resistance(2) 40 kΩ
VIL Input low-level voltage -0.3 0.2 * VVDD
V
VIH Input high-level voltage 0.8 * VVDD VVDD + 0.3
VOL Output low-level voltage 0.4
VOH Output high-level voltage VVDD - 0.4
IOL Output low-level current (3)
3. These valu es are based on characterization. These values are not covered by test limits in production
ODCR0=0 1.68V<VVDD<2.7V 20 mA
2.7V<VVDD<3.6V 30
IOH Output high-lev el current(3) ODCR0=0 1.68V<VVDD<2.7V 20 mA
2.7V<VVDD<3.6V 30
FPINMAX Maximum frequency(2) ODCR0=0
OSRR0=0 load = 25pF 20 MHz
ILEAK Input leakage current(3) Pull-up resistors disabled 0.01 1 µA
CIN Input capacitance(2) 5pF
Table 9-16. TWI Pin Characteristics in TWI configuration (1)
Symbol Parameter Conditions Min Typ Max Units
RPULLUP Pull-up resistance (2) 40 kΩ
RPULLDOWN Pull-down resistance(2) 40 kΩ
VIL Input low-le vel voltage -0.3 0.3 * VVDD V
VIH Input high-level voltage 0.7 * VVDD VVDD + 0.3 V
VOL Output low-level voltage 0.4 V
IOL Output low-level current (3)
DRIVEL=0 0.5
mA
DRIVEL=1 1.0
DRIVEL=2 1.6
DRIVEL=3 3.1
DRIVEL=4 6.2
DRIVEL=5 9.3
DRIVEL=6 15.5
DRIVEL=7 21.8
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ICS Current Source(3)
DRIVEH=0 0.5
mA
DRIVEH=1 1
DRIVEH=2 1.5
DRIVEH=3 3
fMAX Max frequency(2) HsMode with Current source;
DRIVEx=3, SLEW=0
Cbus = 400pF, VVDD = 1.68V 3.5 6.4 MHz
tRISE Rise time(2) HsMode Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V 28 38 ns
tFALL Fall time(2)
Standard Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V 50 95
ns
HsMode Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V 50 95
1. VVDD corresponds to either VVDDIN or VVDDIO, dependi ng on the supply for the pin. Refer to Section 3-5 on page 13 for details
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization
3. These valu es are based on characterization. These values are not covered by test limits in production
Table 9-16. TWI Pin Characteristics in TWI configuration (1)
Symbol Parameter Conditions Min Typ Max Units
Table 9-17. TWI Pin Characteristics in GPIO configuration (1)
Symbol Parameter Conditions Min Typ Max Units
RPULLUP Pull-up resistance (2) 40 kΩ
RPULLDOWN Pull-up resistance(2) 40 kΩ
VIL Input low-level voltage -0.3 0.2 * VVDD V
VIH Input high-level voltage 0.8 * VVDD VVDD + 0.3 V
VOL Output low-level voltage 0.4 V
VOH Output high-level voltage VVDD - 0.4
IOL Output low-level current (3)
ODCR0=0 1.68V<VVDD<2.7V 1.8
mA
2.7V<VVDD<3.6V 3.5
ODCR0=1 1.68V<VVDD<2.7V 3.6
2.7V<VVDD<3.6V 6.8
IOH Output high-lev el current(3)
ODCR0=0 1.68V<VVDD<2.7V 1.8
mA
2.7V<VVDD<3.6V 3.5
ODCR0=1 1.68V<VVDD<2.7V 3.6
2.7V<VVDD<3.6V 6.8
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tRISE Rise time(2)
OSRR0=0 ODCR0=0
1.68V<VVDD<2.7V,
Cload = 25pF
18 ns
OSRR0=1 110
OSRR0=0 ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
10 ns
OSRR0=1 50
tFALL Fall time(2)
OSRR0=0 ODCR0=0
1.68V<VVDD<2.7V,
Cload = 25pF
19 ns
OSRR0=1 140
OSRR0=0 ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
12 ns
OSRR0=1 63
1. VVDD corresponds to either VVDDIN or VVDDIO, dependi ng on the supply for the pin. Refer to Section 3-5 on page 13 for details
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization
3. These valu es are based on characterization. These values are not covered by test limits in production
Table 9-17. TWI Pin Characteristics in GPIO configuration (1)
Symbol Parameter Conditions Min Typ Max Units
Table 9-18. Common TWI Pin Characteristics
Symbol Parameter Conditions Min Typ Max Units
ILEAK Input leakage current (1) Pull-up resistors disabled 0.01 1 µA
CIN Input capacitance(2) 5pF
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization
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9.6.5 High Drive TWI Pin : PB00, PB01
Table 9-19. High Drive TWI Pin Characteristics in TWI configuration (1)
1. VVDD corresponds to either VVDDIN or VVDDIO, dependi ng on the supply for the pin. Refer to Section 3-5 on page 13 for details
Symbol Parameter Conditions Min Typ Max Units
RPULLUP Pull-up resistance (2)
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization
PB00, PB01 40 kΩ
RPULLDOWN Pull-down resistance(2) 40 kΩ
VIL Input low-le vel voltage -0.3 0.3 * VVDD
V
VIH Input high-level voltage 0.7 * VVDD VVDD + 0.3
VOL Output low-level voltage 0.4
VOH Output high-level voltage VVDD - 0.4
IOL Output low-level current (3)
3. These valu es are based on characterization. These values are not covered by test limits in production
DRIVEL=0 0.5
mA
DRIVEL=1 1.0
DRIVEL=2 1.6
DRIVEL=3 3.1
DRIVEL=4 6.2
DRIVEL=5 9.3
DRIVEL=6 15.5
DRIVEL=7 21.8
ICS Current Source(2)
DRIVEH=0 0.5
mA
DRIVEH=1 1
DRIVEH=2 1.5
DRIVEH=3 3
fMAX Max frequency(2) HsMode with Current source;
DRIVEx=3, SLEW=0
Cbus = 400pF, VVDD = 1.68V 3.5 6.4 MHz
tRISE Rise time(2) HsMode Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V 28 38 ns
tFALL Fall time(2)
Standard Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V 50 95
ns
HsMode Mode, DRIVEx=3, SLEW=0
Cbus = 400pF, Rp = 440Ohm,
VVDD = 1.68V 50 95
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Table 9-20. High Driv e TW I Pin Characteristics in GPIO configuration (1)
Symbol Parameter Conditions Min Typ Max Units
RPULLUP Pull-up resistance (2) 40 kΩ
RPULLDOWN Pull-up resistance(2) 40 kΩ
VIL Input low-le vel voltage -0.3 0.2 * VVDD
V
VIH Input high-level voltage 0.8 * VVDD VVDD + 0.3
VOL Output low-level voltage 0.4
VOH Output high-level voltage VVDD - 0.4
IOL Output low-level current (3)
ODCR0=0 1.68V<VVDD<2.7V 3.4 mA
2.7V<VVDD<3.6V 6
ODCR0=1 1.68V<VVDD<2.7V 5.2 mA
2.7V<VVDD<3.6V 8
IOH Output high-lev el current(3)
ODCR0=0 1.68V<VVDD<2.7V 3.4 mA
2.7V<VVDD<3.6V 6
ODCR0=1 1.68V<VVDD<2.7V 5.2 mA
2.7V<VVDD<3.6V 8
tRISE Rise time(2)
OSRR0=0 ODCR0=0
1.68V<VVDD<2.7V,
Cload = 25pF
18 ns
OSRR0=1 110
OSRR0=0 ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
10 ns
OSRR0=1 50
tFALL Fall time(2)
OSRR0=0 ODCR0=0
1.68V<VVDD<2.7V,
Cload = 25pF
19 ns
OSRR0=1 140
OSRR0=0 ODCR0=0
2.7V<VVDD<3.6V,
Cload = 25pF
12 ns
OSRR0=1 63
1. VVDD corresponds to either VVDDIN or VVDDIO, dependi ng on the supply for the pin. Refer to Section 3-5 on page 13 for details
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization
3. These valu es are based on characterization. These values are not covered by test limits in production
Table 9-21. Common High Drive TWI Pin Characteristics
Symbol Parameter Conditions Min Typ Max Units
ILEAK Input leakage current (1) Pull-up resistors disabled 0.01 2 µA
CIN Input capacitance(1) 10 pF
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization
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9.7 Oscillator Characteristics
9.7.1 Osc ill at o r 0 (OSC0 ) C hara ct eris ti cs
9.7.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital cloc k is applied
on XIN.
9.7.1.2 Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected
between XIN and XOUT as shown in Figure 9-3. The user must choose a crystal oscillator
where the crystal lo ad capacitan ce CL is within the range given in the table. The exact value of CL
can be found in the crystal datasheet. The capacitance of the e xternal capacitors (CLEXT) can
then be computed as follows:
where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the
crystal.
Table 9-22. Digital Clock Characteristics
Symbol Parameter Conditions Min Typ Max Units
fCPXIN XIN clock frequency (1) 50 MHz
tCPXIN XIN clock duty cycle(1) 40 60 %
tSTARTUP Startup time N/A cycles
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
CLEXT 2C
LCSTRAY CSHUNT
––()=
Table 9-23. Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Crystal oscillator frequency (1) 0.6 30 MHz
ESR Crystal Equivalent Series Resistance (2)
f = 0.455MHz, CLEXT = 100pF
SCIF.OSCCTRL.GAIN = 0 17000
Ω
f = 2MHz, CLEXT = 20pF
SCIF.OSCCTRL.GAIN = 0 2000
f = 4MHz, CLEXT = 20pF
SCIF.OSCCTRL.GAIN = 1 1500
f = 8MHz, CLEXT = 20pF
SCIF.OSCCTRL.GAIN = 2 300
f = 16MHz, CLEXT = 20pF
SCIF.OSCCTRL.GAIN = 3 350
f = 30MHz, CLEXT = 18pF
SCIF.OSCCTRL.GAIN = 4 45
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Figure 9-3. Oscillator Connection
CLCrystal load capacitance(1) 618
pF
CSHUNT Crystal shunt capacitance(1) 7
CXIN Parasitic capacitor load(2) TQFP100 package 4.91
CXOUT Parasitic capacitor load(2) 3.22
tSTARTUP Startup time(1) SCIF.OSCCTRL.GAIN = 2 30 000 (3) cycles
IOSC Current consumption(1)
Active mode, f = 0.6MHz,
SCIF.OSCCTRL.GAIN = 0 30
µA
Active mode, f = 4MHz,
SCIF.OSCCTRL.GAIN = 1 130
Active mode, f = 8MHz,
SCIF.OSCCTRL.GAIN = 2 260
Active mode, f = 16MHz,
SCIF.OSCCTRL.GAIN = 3 590
Active mode, f = 30MHz,
SCIF.OSCCTRL.GAIN = 4 960
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
2. These valu es are based on characterization. These values are not covered by test limits in production.
3. Nominal crystal cycles.
Table 9-23. Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
CSHUNT
LM
RM
CM
CSTRAY
CLEXT
CLEXT
Xin
Xout
Crystal
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9.7.2 32kHz Crystal Oscillator (OSC32K) Char acteristics
Figure 9-3 and the equation above also applies to the 32kHz oscillator connection. The user
must choose a crystal oscillator where the crystal load capacitance CL is within the range given
in the table. The exact value of CL can then be found in the crystal datasheet.
Table 9-24. Digital Clock Characteristics
Symbol Parameter Conditions Min Typ Max Units
fCPXIN32 XIN32 clock frequency (1) 6MHz
XIN32 clock duty cycle(1) 40 60 %
tSTARTUP Startup time N/A cycles
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
Table 9-25. 32 k Hz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Crystal oscillator frequency 32 768 Hz
tSTARTUP Startup time (1) Rm = 100kΩ, CL = 12.5pF 30000 (2) cycles
CLCrystal load capacitance(1) 612.5
pF
CSHUNT Crystal shunt capacitance(1) 0.8 1.7
CXIN Parasitic capacitor load (3) TQFP100 package 3.4
CXOUT Parasitic capacitor load(3) 2.72
IOSC32K Current consumption(1) 350 nA
ESRXTAL
Crystal equivalent series
resistance(1)
f=32.768kHz
OSCCTRL32.MODE=1
Safety Factor = 3
OSCCTRL32.SELCURR=0
CL=6pF
28
kΩ
OSCCTRL32.SELCURR=4 72
OSCCTRL32.SELCURR=8 114
OSCCTRL32.SELCURR=15 313
OSCCTRL32.SELCURR=0
CL=9pF
14
kΩ
OSCCTRL32.SELCURR=4 36
OSCCTRL32.SELCURR=8 100
OSCCTRL32.SELCURR=15 170
Crystal equivalent series
resistance(3)
f=32.768kHz
OSCCTRL32.MODE=1
Safety Factor = 3
OSCCTRL32.SELCURR=4
CL=12.5pF
15.2
kΩ
OSCCTRL32.SELCURR=6 61.8
OSCCTRL32.SELCURR=8 101.8
OSCCTRL32.SELCURR=10 138.5
OSCCTRL32.SELCURR=15 228.5
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
2. Nominal crystal cycles.
3. These valu es are based on characterization. These values are not covered by test limits in production.
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9.7.3 Phase Locked Loop (PLL) Characteristics
9.7.4 Digital Frequency Locked Loop (DFLL) Characteristics
Table 9-26. Ph as e Lo cke d Loop Ch ar ac te rist ics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency (1)
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
PLL is not availabe in PS1 48 240 MHz
fIN Input frequency(1) 416
IPLL Current consumption(1) fout=80MHz 200 µA
fout=240MHz 500
tSTARTUP
Startup time, from enabling
the PLL until the PLL is
locked(1)
Wide Bandwidth mode disabled 8 µs
Wide Bandwidth mode enabled 30
Table 9-27. Digital Frequency Locked Loop Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency (1) DFLL is not availabe in PS1 20 150 MHz
fREF Reference frequency(1) 8 150 kHz
Accuracy(1)
FINE lock, fREF = 32kHz, SSG disab led (2) 0.1 0.5
%
A CCURATE lock, fREF = 32kHz, dither clk
RCSYS/2, SSG disabled(2) 0.06 0.5
FINE lock, fREF = 8-150kHz, SSG
disabled(2) 0.2 1
ACCURATE lock, fREF = 8-150kHz,
dither clk RCSYS/2, SSG disabled(2) 0.1 1
IDFLL Power consumption(1)
RANGE 0 96 to 220MHz
COARSE=0, FINE=0, DIV=0 430 509 545
µA
RANGE 0 96 to 220MHz
COARSE=31, FINE=255, DIV=0 1545 1858 1919
RANGE 1 50 to 110MHz
COARSE=0, FINE=0, DIV=0 218 271 308
RANGE 1 50 to 110MHz
COARSE=31, FINE=255, DIV=0 704 827 862
RANGE 2 25 to 55MHz
COARSE=0, FINE=0, DIV=1 140 187 226
RANGE 2 25 to 55MHz
COARSE=31, FINE=255, DIV=1 365 441 477
RANGE 3 20 to 30MHz
COARSE=0, FINE=0, DIV=1 122 174 219
RANGE 3 20 to 30MHz
COARSE=31, FINE=255, DIV=1 288 354 391
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9.7.5 32kHz RC Oscillator (RC32K) Characteristics
9.7.6 System RC Osci lla tor (RCSYS) Characteristics
tSTARTUP Startup time(1) Within 90% of final values 100 µs
tLOCK Lock ti me (1) fREF = 32kHz, FINE lock, SSG disabled(2) 600
fREF = 32kHz, ACCURATE lock, dithering
clock = RCSYS/2, SSG disabled(2) 1100
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
2. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the SCIF.DFLL0SSG register.
Table 9-28. 32kHz RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency (1)
1. These valu es are based on characterization. These values are not covered by test limits in production.
Calibrated against a 32.768kHz
reference
Temperature compensation disabled 20 32.768 44 kHz
IRC32K Current consumption (2)
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
Without temperature compensation 0 .5 µA
Temperature compensation enabled 2 µA
tSTARTUP Startup time(1) 1 cycle
Table 9-29. System RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency (1)
1. These valu es are based on characterization. These values are not covered by test limits in production.
Calibrated at 85°C 110 113.6 116 kHz
IRCSYS Current consumption (2)
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
12 µA
tSTARTUP Startup time(1) 25 38 63 µs
Duty Duty cycle(1) 49.6 50 50.3 %
Table 9-27. Digital Frequency Locked Loop Characteristics
Symbol Parameter Conditions Min Typ Max Unit
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9.7.7 1MHz RC Oscillator (RC1M) Characteristics
9.7.8 4/8/12 M Hz RC Osci lla tor (RCFAST) Characteristics
Table 9-30. RC1M Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency (1)
1. These valu es are based on characterization. These values are not covered by test limits in production.
0.91 1 1.12 MHz
IRC1M Current consumption (2)
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
35 µA
Duty Duty cycle(1) 48.6 49.9 54.4 %
Table 9-31. RC FAST Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency (1)
1. These valu es are based on characterization. These values are not covered by test limits in production.
Calibrated, FRANGE=0 4 4.3 4.6
MHzCalibrated, FRANGE=1 7.8 8.2 8.5
Calibrated, FRANGE=2 11.3 12 12.3
IRCFAST Current consumption (2)
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
Calibrated, FRANGE=0 90 110
µACalibrated, FRANGE=1 130 150
Calibrated, FRANGE=2 180 205
Duty Duty cycle(1)
Calibrated, FRANGE=0 48.8 49.6 50.1
%Calibrated, FRANGE=1 47.8 49.2 50.1
Calibrated, FRANGE=2 46.7 48.8 50.0
tSTARTUP Startup time(1) Calibrated, FRANGE=2 0.1 0.31 0.71 µs
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9.7.9 80MHz RC Oscillator (RC80M) Characteristics
9.8 Flash Characteristics
Table 9-33 gives the device maximum operating frequency dep ending on the number of flash
wait states and the flash read mode. The FWS bit in the FLASHCALW FCR register controls the
number of wait states used when accessing the fl ash memory.
Table 9-32. Internal 80MHz RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency (1)
1. These valu es are based on characterization. These values are not covered by test limits in production.
After calibration
Note that RC80M is not available in PS1 60 80 100 MHz
IRC80M Current consumption (2)
2. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
330 µA
tSTARTUP Startup time(1) 0.57 1.72 3.2 µs
Duty Duty cycle(2) 45 50 55 %
Table 9-33. Maximum Operating Frequency (1)
PowerScaling Mode Flash Read Mode Flash Wait
States Maximum Operating
Frequency Unit
0
Low power (HSDIS) +
Flash internal reference:
BPM.PMCON.FASTWKUP=1 112
MHz
Low power(HSDIS) 018
136
1
Low power (HSDIS) +
Flash internal reference:
BPM.PMCON.FASTWKUP=1 112
Low power (HSDIS) 08
112
2 High speed (HSEN) 024
148
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
Table 9-34. Fl as h Cha r act er istics (1)
Symbol Parameter Conditions Min Typ Max Unit
tFPP Page programming time
fCLK_AHB = 48MHz
4.38
ms
tFPE Page erase time 4.38
tFFP Fuse programming time 0.63
tFEA Full chip erase time (EA) 5.66
tFCE JTAG chip erase time (CHIP_ERASE) fCLK_AHB = 115kHz 304
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1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
Table 9-35. Flash Endurance and Data Retention (1)
Symbol Parameter Conditions Min Typ Max Unit
NFARRAY Array endurance (write/page) fCLK_AHB > 10MHz 100k cycles
NFFUSE General Purpose fuses endurance (write/bit) fCLK_AHB > 10MHz 10k
tRET Data retention 15 years
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
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9.9 Analog Characteristics
9.9.1 Voltage Regulator Characteristics
Table 9-36. VREG Electrical Characteristics in Linear and Switching Modes
Symbol Parameter Conditions Min Typ Max Units
IOUT
DC output curr ent (1)
Power scaling mode 0 & 2
1. These valu es are based on simulation. These values are not cov ered by test limits in production.
Low power mode (WAIT) 2000 3600 5600
µA
Ultra Low power mode
(RETENTION) 100 180 300
DC output curr ent(1)
Power scaling mode 1
Low power mode (WAIT) 4000 7000 10000
Ultra Low power mode
(RETENTION) 200 350 600
VVDDCORE DC output voltage All modes 1.9 V
Table 9-37. VREG Electrical Characteristics in Linear mode
Symbol Parameter Conditions Min Typ Max Units
VVDDIN Input voltage range IOUT=10mA 1.68 3.6
V
IOUT=50mA 1.8 3.6
VVDDCORE DC output voltage (1)
Power scaling mode 0 & 2
1. These valu es are based on characterization. These values are not covered by test limits in production.
IOUT = 0 mA 1.777 1.814 1.854
IOUT = 50 mA 1.75 1.79 1.83
IOUT DC output curren t (1) VVDDCORE > 1.65V 100 mA
Output DC load regulation(1)
Transient load regulation IOUT = 0 to 80mA,
VVDDIN = 3V -34 -27 -19 mV
Output DC regulation(1) IOUT = 80 mA,
VVDDIN = 2V to 3.6V 10 28 48 mV
IQQuescient current(1) IOUT = 0 mA
RUN and SLEEPx modes 88 107 128 µA
Table 9-38. External components requirements in Linear Mode
Symbol Parameter Technology Typ Units
CIN1 Input regulator capacitor 1 33 nF
CIN2 Input regulator capacitor 2 100
CIN3 Input regulator capacitor 3 10 µF
COUT1 Output regulator capacitor 1 100 nF
COUT2 Output regulator capacitor 2 Tantalum or MLCC
0.5<ESR<10Ω4.7 µF
Table 9-39. VREG Electrical Characteristics in Switching mode
Symbol Parameter Conditions Min Typ Max Units
VVDDIN Input voltage range VVDDCORE = 1.65V, IOUT=50mA 2.0 3.6
V
VVDDCORE DC output voltage (1)
Power scaling mode 0 & 2 IOUT = 0 mA 1.75 1.82 1.87
IOUT = 50 mA 1.66 1.71 1.79
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Note: 1. Refer to Section 6. on page 46.
IOUT DC output curren t (1) VVDDCORE > 1.65V 55 mA
Output DC load regulation(1)
Transient load regulation IOUT = 0 to 50mA,
VVDDIN = 3V -136 -101 -82 mV
Output DC regulation(1) IOUT = 50 mA,
VVDDIN = 2V to 3.6V -20 38 99 mV
IQQuescient current(1) VVDDIN = 2V, IOUT = 0 mA 97 18 6 546 µA
VVDDIN > 2.2V, IOUT = 0 mA 97 111 147
PEFF Power effi ci en cy(1) IOUT = 5mA, 50mA
Reference pow er n ot included 82.7 88.3 95 %
1. These valu es are based on characterization. These values are not covered by test limits in production.
Table 9-40. Decoupling Requirements in Switching Mode
Symbol Parameter Technology Typ Units
CIN1 Input regulator capacitor 1 33 nF
CIN2 Input regulator capacitor 2 100
CIN3 Input regulator capacitor 3 10 µF
COUT1 Output regulator capacitor 1 X7R MLCC 100 nF
COUT2 Output regulator capacitor 2 X7R MLCC (ex : GRM31CR71A475) 4.7 µF
LEXT External inductance (ex: Murata LQH3NPN220MJ0) 22 µH
RDCLEXT Serial resistance of LEXT 0.7 Ω
ISATLEXT Saturation current of LEXT 300 mA
Table 9-39. VREG Electrical Characteristics in Switching mode
Symbol Parameter Conditions Min Typ Max Units
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9.9.2 Powe r-on Reset 33 Cha r ac te ris tic s
Figure 9-4. POR33 Operating Prin ciple
9.9.3 Brown Out Detectors Characteristics
Table 9-41. POR33 Characteristics (1)
1. These valu es are based on characterization. These values are not covered by test limits in production.
Symbol Parameter Conditions Min Typ Max Units
VPOT+ Voltage threshold on VVDDIN rising 1.25 1.55 V
VPOT- Voltage threshold on VVDDIN falling 0.95 1.30
Reset VVDDIN
VPOT+
VPOT-
Time
Table 9-42. BOD18 Characteristics (1)
Symbol Parameter Conditions Min Typ Max Units
Step size, betw een adjacent va lues
in BSCIF.BOD18LEVEL(1) 10.1 mV
VHYST BOD hysteresis (1) T = 25°C340
tDET Detection time(1) Time with VVDDCORE <
BOD18.LEVEL necessary to
generate a reset signal 1.2 µs
IBOD Current consumption(1) on VDDIN 7.4 14 µA
on VDDCORE 7
tSTARTUP Startup time(1) 4.5 µs
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The values in Table 9-43 describe the values of the BOD33.LEVEL in the flash User Page fuses.
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
Table 9-43. BOD33.LEVEL Values
BOD33.LEVEL Value Min Typ Max Units
16 2.08
V
20 2.18
24 2.33
28 2.48
32 2.62
36 2.77
40 2.92
44 3.06
48 3.21
Table 9-44. BOD33 Characteristics (1)
Symbol Parameter Conditions Min Typ Max Units
Step size, betw een adjacent
va lues in BSCIF.BOD33LEVEL(1) 34.4 mV
VHYST Hysteresis(1) 45 170
tDET Detection time(1) Time with VDDIN < VTH necessary
to generate a reset signal µs
IBOD33 Current consumption(1) Normal mode 36 µA
tSTARTUP Startup time(1) Normal mode 6 µs
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
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9.9.4 Analog- to Digital Converter Characteristics
Figure 9-5. Maximum inpu t co mm o n mo d e volt age
Table 9-45. Operating conditions
Symbol Parameter Conditions Min Typ Max Units
Temperature range -40 +85 °C
Resolution (1)
1. These valu es are based on characterization. These values are not covered by test limits in production
Max 12 12 (2)
2. Single ended or using divide by two max resolution: 11 bits
Bit
Sampling clock (3)
3. These valu es are based on simulation. These values are not covered b y t es t lim i ts in pro d uct i on
Differential modes, Gain=1X 5 300 kHz
Unipolar modes, Gain=1X 5 250
fADC ADC clock frequency(3) Differential modes 0.03 1.8 MHz
Unipolar modes 0.03 1.5
TSAMPLEHOLD Sampling time(3) Differenti al modes 16.5 277 µs
Unipolar modes 16.5 333
Conversion rate(1) 1X gain, differential 300 kSps
Internal channel conversion
rate(3) VVDD/10, Bandgap and
Temperature channels 125 kSps
Conversion time (latency)
Differential mode (no windowing)
1X gain, (resolution/2)+gain (4)
4. See Figure 9-5
6
Cycles
2X and 4X gain 7
8X and 16X gain 8
32X and 64X gain 9
64X gain and unipolar 10
M AX in p u t co mm o n m o de v o lta g e
0
0.5
1
1.5
2
2.5
3
1.6 3.6
Vcc
ICMR
vc m _ vref= 3V
vc m _ vref= 1V
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Table 9-46. DC Charac teristics
Symbol Parameter Conditions Min Typ Max Units
VDDANA Supply voltage (1) 1.6 3.6 V
Reference range (2)
Differential mode 1.0 VDDANA
-0.6 VUnipolar and Window modes 1.0 1.0
Using divide by two function
(differential) 2.0 VDDANA
Absolute min, max input voltage(2) -0,1 VDDANA
+0.1 V
Start up time(2)
ADC with reference already
enabled 12 24 Cycles
No gain compensation
Reference buffer 5µs
Gain compensation
Reference buffer 60 Cycles
RSAMPLE Input channel source resistance(2) 0.5 kΩ
CSAMPLE Sampling capacitance(2) 2.9 3.6 4.3 pF
Reference input source resistance(2) Gain compensation 2 kΩ
No gain compensation 1 MΩ
ADC refe rence settling time(2) After changing
reference/mode (3) 5 60 Cycles
1. These valu es are based on characterization. These values are not covered by test limits in production
2. These valu es are based on simulation. These values are not covered b y t es t lim i ts in pro d uct i on
3. Requires refresh/flush otherwise conversion time (latency) + 1
Table 9-47. Differential mode, gain=1
Symbol Parameter Conditions Min Typ Max Units
Accuracy without compensation (1) 7ENOB
Accuracy after compensation(1) (INL, gain and offset) 11 ENOB
INL I ntegral Non Linearity (2) After calibration,
Gain compensation 1.2 1.7 LSBs
DNL Differential Non Linearity(2) After calibration 0.7 1.0 LSBs
Gain error (2)
Exter nal reference -5.0 -1.0 5.0
mV
VDDANA/1.6 -40 40
VDDANA/2.0 -40 40
Bandgap After calibration -30 30
Gain error drift vs voltage(1) External reference -2 2 mV/V
Gain error drift vs tempera tu re (1) After calibration + bandgap drift
If using onchip bandgap 0.08 mV/°K
Offset error (2)
Exter nal reference -5.0 5.0
mV
VDDANA/1.6 -10 10
VDDANA/2.0 -10 10
Bandgap After calibration -10 10
Offset error drift vs voltage(1) -4 4 mV/V
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Offset error drift vs temperature(1) 0.04 mV/°K
Conve rsi on range (2) Vin-Vip -Vref Vref V
ICMR(1) see
Figure
9-5
PSRR(1)
fvdd=1Hz, ext ADVREFP=3.0V
VVDD=3.6V 100 dB
fvdd=2MHz, e xt
ADVREFP=3.0V VVDD=3.6 50
DC supply current (2)
VDDANA=3.6V,
ADVREFP=3.0V 1.2 mA
VDDANA=1.6V,
ADVREFP=1.0V 0.6
1. These valu es are based on simulation only. These values are not covered by test limits in production or character ization
2. These v alues are based on characterization and not tested in production, and valid f or an input v oltage between 10% to 90% of
reference voltage.
Table 9-48. Unipolar mode, gain=1
Symbol Parameter Conditions Min Typ Max Units
Accuracy without compensation (1) 7ENOB
Accuracy after compensation(1) 11 ENOB
INL I ntegral Non Linearity (2)
After calibration Dynamic tests
No gain compensation ±3 LSBs
After calibration Dynamic tests
Gain compensation ±3
DNL Differential Non Linearity(2) After calibration ±2.8 LSBs
Gain error(2)
Exter nal reference -15 15
mV
VDDANA/1.6 -50 50
VDDANA/2.0 -30 30
Bandgap After calibration -10 10
Gain error drift vs voltage(1) External reference -8 8 mV/V
Gain error drift tempera ture(1) + bandgap drift If using
bandgap 0.08 mV/°K
Offset error(2)
Exter nal reference -15 15
mV
VDDANA/1.6 -15 15
VDDANA/2.0 -15 15
Bandgap After calibration -10 10
Offset error drift(1) -4 4 mV/V
Offset error drift temperature(1) 00.04mV/°K
Conversion range(1) Vin-Vip -Vref Vref V
ICMR(1) see
Figure
9-5
Table 9-47. Differential mode, gain=1
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9.9.4.1 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the
ADC in order to achieve maximum accuracy. Seen externally the ADC input consists of a resis-
tor ( ) and a cap acitor ( ). In a ddition, the source res istance ( ) must be
taken into account when calculating the required sample and hold time. Figure 9-6 shows th e
ADC input channel equivalent circuit.
Figure 9-6. ADC Input
To achieve n bits of accuracy, the capacitor must be charged at least to a voltage of
The minimum sampling t ime for a given can be found using this f o rmu la:
for a 12 bits accura cy :
where
PSRR(1) fVdd=100kHz, VDDIO=3.6V 62 dB
fVdd=1MHz, VDDIO=3.6V 49
DC supply current(1) VDDANA=3.6V 1 2 mA
VDDANA=1.6V,
ADVREFP=1.0V 11.3
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization.
2. These v alues are based on characterization and not tested in production, and valid f or an input v oltage between 10% to 90% of
reference voltage.
Table 9-48. Unipolar mode, gain=1
RSAMPLE
CSAMPLE
RSOURCE
RSOURCE
RSAMPLE
Analog Input
ADx CSAMPLE
VIN
VDDANA/2
CSAMPLE
VCSAMPLE V≥IN 12
n1+()–
–()×
tSAMPLEHOLD
RSOURCE
tSAMPLEHOLD RSAMPLE R+SOURCE
()CSAMPLE
()×n1+()2()ln××≥
tSAMPLEHOLD RSAMPLE R+SOURCE
()CSAMPLE
()×9×02,≥
tSAMPLEHOLD 1
2fADC×
------------------------=
137
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9.9.5 Digital to Analog Converter Characteristics
9.9.6 Analog Comparator Characteristics
Table 9-49. Operating conditions
Symbol Parameter Conditions Min Typ Max Units
Analog Supply Voltage (1)
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization
on VDDANA 2.4 3 3.6 V
Digital Supply Voltage(1) on VDDCORE 1.62 1.8 1.98 V
Resolution (2)
2. These valu es are based on characterization. These values are not covered by test limits in production
10 bits
Clock frequency(1) Cload = 50pF ; Rload = 5kΩ500 kHz
Load(1) CLoad 50 pF
RLoad 5 kΩ
INL I ntegral Non Linearity (1) Best fit-line method ±2 LSBs
DNL Differential Non Linearity (1) Best fit-line method -0.9 +1 LSBs
Zero Error (offset) (1) CDR[9:0] = 0 1 5 mV
Gain Error (1) CDR[9:0] = 1023 5 10 mV
Total Harmonic Distortion(1) 80% of VDDANA @ fin = 70kHz -56 7 dB
Delay to vout (1) CDR[9:0] = 512/ Cload = 50 pF
/ Rload = 5 kΩ 2µs
Startup time(1) CDR[9:0] = 512 5 9 µs
Output Voltage Range (ADVREFP < VDDANA –
100mV) is mandatory 0ADVREFP V
ADVREFP Voltage Range(1) (ADVREFP < VDDANA –
100mV) is mandatory 2.3 3.5 V
ADVREFN Voltage Range(1) ADVREFP = GND 0 V
Standby Current(1) On VDDANA 500 nA
On VDDCORE 100
DC Current consumption(1) On VDDANA (no Rload) 485 660 µA
On ADVREFP
(CDR[9:0] = 512) 250 295
Table 9-50. Analog Comparator Characteristics
Symbol Parameter Conditions Min Typ Max Units
Positive input voltage
range 0.1 VDDIO-0.1 V
Negative input voltage
range 0.1 VDDIO-0.1
Offset (1)
VACREFN =0.1V to VDDIO-0.1V,
h y steresis = 0 (2)
Fast mode -12 13 mV
VACREFN =0.1V to VDDIO-0.1V,
h y steresis = 0(2)
Low power mode -11 12 mV
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Hysteresis(1)
VACREFN =0.1V to VDDIO-0.1V,
h y steresis = 1(2)
Fast mode 10 55 mV
VACREFN =0.1V to VDDIO-0.1V,
h y steresis = 1(2)
Low power mode 10 68 mV
VACREFN =0.1V to VDDIO-0.1V,
h y steresis = 2(2)
Fast mode 26 83 mV
VACREFN =0.1V to VDDIO-0.1V,
h y steresis = 2(2)
Low power mode 19 91 mV
VACREFN =0.1V to VDDIO-0.1V,
h y steresis = 3(2)
Fast mode 43 106 mV
VACREFN =0.1V to VDDIO-0.1V,
h y steresis = 3(2)
Low power mode 32 136 mV
Propagation delay(1)
Changes for VACM=VDDIO/2
100mV Overdrive
Fast mode 67 ns
Changes for VACM=VDDIO/2
100mV Overdrive
Low power mode 315 ns
tSTARTUP Startup time(1)
Enable to ready delay
Fast mode 1.19 µs
Enable to ready delay
Low power mode 3.61 µs
IAC Channel current
consumption (3) Low power mode, no hysteresis 4.9 8.7 µA
Fast mode, no hysteresis 63 127
1. These valu es are based on characterization. These values are not covered by test limits in production
2. HYSTAC.CONFn.HYS field, refer to the Analog Comparator Interface chapter
3. These valu es are based on simulation. These values are not covered by test limits in production or characterization
Table 9-50. Analog Comparator Characteristics
Symbol Parameter Conditions Min Typ Max Units
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9.9.7 Liquid Crystal Display Controler characteristics
9.9.7.1 Liquid Crystal Controler supply current
The values in Table 9-52 are measured values of power consumption under the following condi-
tions, except where noted:
• T=25°C, WAIT mode, Low power waveform, Frame Rate = 32Hz from OSC32K
• Configuration: 4COMx40SEG, 1/4 Duty, 1/3 Bias, No anim ation
• All segments on, Load = 160 x 22pF between each COM and each SEG.
• LCDCA current based on ILCD = IWAIT(Lcd On) - IWAIT(Lcd Off)
Table 9-51. Liquid Cry stal Display Controler characteristics
Symbol Parameter Conditions Min Typ Max Units
SEG Segment Terminal Pins 40
COM Common Terminal Pins 4
fFrame LCD Frame Frequency FCLKLCD 31.25 512 Hz
CFlying Flying Capacitor 100 nF
VLCD LCD Regulated Voltages (1)
CFG.FCST=0
1. These valu es are based on simulation. These values are not covered by test limits in production or characterization
CFlying = 100nF
100nF on VLCD, BIAS2 and BIAS1 pins
3
VBIAS2 2*VLCD/3
BIAS1 VLCD/3
Table 9-52. Liquid Cry stal Display Controler supply current
Symbol Conditions Min Typ Max Units
ILCD
Internal voltage generation
CFG.FCST=0 VVDDIN = 3.6V 8.85
µA
VVDDIN = 1.8V 6.16
External bias
VLCD=3.0V VVDDIN = 3.3V 0.98
VVDDIN = 1.8V 1.17
140
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9.10 Timing Characteristics
9.10.1 RESET_N Timing
9.10.2 USART in SPI Mode Timing
9.10.2.1 Master mode
Figure 9-7. USART in SPI Master Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
Figure 9-8. USART in SPI Master Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and
CPHA= 0)
Table 9-53. RESE T_ N Wav ef or m Para me te rs (1)
1. These valu es are based on simulation. These values are not cov ered by test limits in production.
Symbol Parameter Conditions Min Max Units
tRESET RESET_N minimum pulse length 10 ns
USPI0 USPI1
MISO
SPCK
MOSI
USPI2
USPI3 USPI4
MISO
SPCK
MOSI
USPI5
141
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Notes: 1. These values are based on simulation. These va lues are not covered by test limits in production.
2. Where:
Table 9-54. USART0 in SPI Mode Timing, Master Mode(1)
Symbol Parameter Conditions Min Max Units
USPI0 MISO setup time before SPCK rises VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
123.2 + tSAMPLE(2)
ns
USPI1 MISO hold time after SPCK rises 24.74 -tSAMPLE(2)
USPI2 SPCK rising to MOSI delay 513.56
USPI3 MISO setup time before SPCK falls 125.99 + tSAMPLE(2)
USPI4 MISO hold time after SPCK falls 24.74 -tSAMPLE(2)
USPI5 SPCK falling to MOSI delay 516.55
Table 9-55. USART1 in SPI Mode Timing, Master Mode(1)
Symbol Parameter Conditions Min Max Units
USPI0 MISO setup time before SPCK rises VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
69.28 + tSAMPLE(2)
ns
USPI1 MISO hold time after SPCK rises 25.75 -tSAMPLE(2)
USPI2 SPCK rising to MOSI delay 99.66
USPI3 MISO setup time before SPCK falls 73.12 + tSAMPLE(2)
USPI4 MISO hold time after SPCK falls 28.10 -tSAMPLE(2)
USPI5 SPCK falling to MOSI delay 102.01
Table 9-56. USART2 in SPI Mode Timing, Master Mode(1)
Symbol Parameter Conditions Min Max Units
USPI0 MISO setup time before SPCK rises VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
69.09 + tSAMPLE(2)
ns
USPI1 MISO hold time after SPCK rises 26.52 -tSAMPLE(2)
USPI2 SPCK rising to MOSI delay 542.96
USPI3 MISO setup time before SPCK falls 72.55 + tSAMPLE(2)
USPI4 MISO hold time after SPCK falls 28.37 -tSAMPLE(2)
USPI5 SPCK falling to MOSI delay 544.80
Table 9-57. USART3 in SPI Mode Timing, Master Mode(1)
Symbol Parameter Conditions Min Max Units
USPI0 MISO setup time before SPCK rises VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
147.24 + tSAMPLE(2)
ns
USPI1 MISO hold time after SPCK rises 25.80 -tSAMPLE(2)
USPI2 SPCK rising to MOSI delay 88.23
USPI3 MISO setup time before SPCK falls 154.9 + tSAMPLE(2)
USPI4 MISO hold time after SPCK falls 26.89 -tSAMPLE(2)
USPI5 SPCK falling to MOSI delay 89.32
tSAMPLE tSPCK
tSPCK
2tCLKUSART
×
------------------------------------ 1
2
---
⎝⎠
⎛⎞
tCLKUSART
×–=
142
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Maximum SPI Frequency, Master Output
The maximum SPI master output frequency is given by the following formula:
Where is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. is
the maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the maxi-
mum frequency of t he pin s. is the maximum frequency o f the CL K_SPI. Refer t o th e SPI
chapter for a description of this clock.
Maximum SPI Frequency, Master Input
The maximum SPI master input frequency is given by the following formula:
Where is the MISO setup and hold time, USPI0 + USPI1 or USPI3 + USPI4 depending on
CPOL and NCPHA. is th e SPI slave response time. refer to the SPI slave datasheet for
. is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a
description of this clock.
9.10.2.2 Sla ve mode
Figure 9-9. USART in SPI Slave Mode w ith (CPOL = 0 an d CPHA= 1) or (CPOL= 1 and
CPHA= 0)
fSPCKMAX MIN fPINMAX 1
SPIn
------------ fCLKSPI 2×
9
-----------------------------
,(, )=
SPIn
fPINMAX
fCLKSPI
fSPCKMAX MIN 1
SPIn tVALID
+
------------------------------------fCLKSPI 2×
9
-----------------------------(,)=
SPIn
TVALID
TVALID
fCLKSPI
USPI7 USPI8
MISO
SPCK
MOSI
USPI6
143
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Figure 9-10. USART in SPI Slave Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
Figure 9-11. USART in SPI Slave Mode, NPCS Timing
USPI10 USPI11
MISO
SPCK
MOSI
USPI9
USPI14
USPI12
USPI15
USPI13
NSS
SPCK, CPOL=0
SPCK, CPOL=1
Table 9-58. USART0 in SPI mode Timing, Slave Mode(1)
Symbol Parameter Conditions Min Max Units
USPI6 SPCK falling to MISO delay
VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
740.67
ns
USPI7 M OSI setup time before SPCK rises 56.73 + tSAMPLE(2) +
tCLK_USART
USPI8 MOSI hold time after SPCK rises 45.18 -( tSAMPLE(2) +
tCLK_USART )
USPI9 SPCK rising to MISO delay 670.18
USPI10 MOSI setup time befo re SPCK falls 56.73 +( tSAMPLE(2) +
tCLK_USART )
USPI11 MOSI hold time after SPCK falls 45.18 -( tSAMPLE(2) +
tCLK_USART )
USPI12 NSS setup time before SPCK rises 688.71
USPI13 NSS hold time after SPCK falls -2.25
USPI14 NSS setup time before SPCK falls 688.71
USPI15 NSS hold time after SPCK rises -2.25
144
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Table 9-59. USART1 in SPI mode Timing, Slave Mode(1)
Symbol Parameter Conditions Min Max Units
USPI6 SPCK falling to MISO delay
VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
373.58
ns
USPI7 M OSI setup time before SPCK rises 4.16 + tSAMPLE(2) +
tCLK_USART
USPI8 MOSI hold time after SPCK rises 46.69 -( tSAMPLE(2) +
tCLK_USART )
USPI9 SPCK rising to MISO delay 373.54
USPI10 MOSI setup time befo re SPCK falls 4.16 +( tSAMPLE(2) +
tCLK_USART )
USPI11 MOSI hold time after SPCK falls 46.69 -( tSAMPLE(2) +
tCLK_USART )
USPI12 NSS setup time before SPCK rises 200.43
USPI13 NSS hold time after SPCK falls -16.5
USPI14 NSS setup time before SPCK falls 200.43
USPI15 NSS hold time after SPCK rises -16.5
Table 9-60. USART2 in SPI mode Timing, Slave Mode(1)
Symbol Parameter Conditions Min Max Units
USPI6 SPCK falling to MISO delay
VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
770.02
ns
USPI7 M OSI setup time before SPCK rises 136.56 + tSAMPLE(2) +
tCLK_USART
USPI8 MOSI hold time after SPCK rises 47.9 -( tSAMPLE(2) +
tCLK_USART )
USPI9 SPCK rising to MISO delay 570.19
USPI10 MOSI setup time befo re SPCK falls 136.73 +( tSAMPLE(2) +
tCLK_USART )
USPI11 MOSI hold time after SPCK falls 47.9 -( tSAMPLE(2) +
tCLK_USART )
USPI12 NSS setup time before SPCK rises 519.87
USPI13 NSS hold time after SPCK falls -1.83
USPI14 NSS setup time before SPCK falls 519.87
USPI15 NSS hold time after SPCK rises -1.83
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Notes: 1. These values are based on simulation. These va lues are not covered by test limits in production.
2. Where:
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave inpu t frequency is given by the following formula:
Where is the MOSI setup and hold time, USPI7 + USPI8 or USPI10 + USPI11 depending
on CPOL and NCPHA. is the maximum frequency of the CLK_SPI. Refer to the SPI
chapter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave out put frequency is given by the following formula:
Where is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA. is
the SPI master setup time. refer to the SPI master datasheet for . is the maxi-
mum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock.
is the maximum frequency of the SPI pins. refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
Table 9-61. USART3 in SPI mode Timing, Slave Mode(1)
Symbol Parameter Conditions Min Max Units
USPI6 SPCK falling to MISO delay
VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
593.9
ns
USPI7 M OSI setup time before SPCK rises 45.93 + tSAMPLE(2) +
tCLK_USART
USPI8 MOSI hold time after SPCK rises 47.03 -( tSAMPLE(2) +
tCLK_USART )
USPI9 SPCK rising to MISO delay 593.38
USPI10 MOSI setup time befo re SPCK falls 45.93 +( tSAMPLE(2) +
tCLK_USART )
USPI11 MOSI hold time after SPCK falls 47.03 -( tSAMPLE(2) +
tCLK_USART )
USPI12 NSS setup time before SPCK rises 237.5
USPI13 NSS hold time after SPCK falls -1.81
USPI14 NSS setup time before SPCK falls 237.5
USPI15 NSS hold time after SPCK rises -1.81
tSAMPLE tSPCK
tSPCK
2tCLKUSART
×
------------------------------------ 1
2
---+
⎝⎠
⎛⎞
tCLKUSART
×–=
fSPCKMAX MIN fCLKSPI 2×
9
-----------------------------1
SPIn
------------(,)=
SPIn
fCLKSPI
fSPCKMAX MIN fCLKSPI 2×
9
-----------------------------fPINMAX
,1
SPIn tSETUP
+
------------------------------------(,)=
SPIn
TSETUP
TSETUP
fCLKSPI
fPINMAX
146
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9.10.3 SPI Timing
9.10.3.1 Master mode
Figure 9-12. SPI Master Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
Figure 9-13. SPI Master Mode with (C POL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
Maximum SPI Frequency, Master Output
SPI0 SPI1
MISO
SPCK
MOSI
SPI2
SPI3 SPI4
MISO
SPCK
MOSI
SPI5
Table 9-62. SPI Timing, Master Mode(1)
Symbol Parameter Conditions Min Max Units
SPI0 MISO setup time before SPCK rises VVDDIO from
2.85V to 3.6V,
maximum
external
capacitor =
40pF
9
ns
SPI1 MISO hold time after SPCK rises 0
SPI2 SPCK rising to MOSI delay 9 21
SPI3 MISO setup time before SPCK falls 7.3
SPI4 MISO hold time after SPCK falls 0
SPI5 SPCK falling to MOSI delay 9 22
147
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The maximum SPI master output frequency is given by the following formula:
Where is the MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA. is the
maximum frequen cy of the SPI pins. refe r to the I/O Pin Charact eristics section fo r the maximum
frequency of the pins.
Maximum SPI Frequency, Master Input
The maximum SPI master input frequency is given by the following formula:
Where is the MISO setup and hold time, SPI0 + SPI1 or SPI3 + SPI4 depending on
CPOL and NCPHA. is the SPI slave response time. refer to the SPI slave datasheet for
.
9.10.3.2 Sla ve mode
Figure 9-14. SPI Slave Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
Figure 9-15. SPI Slave Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
fSPCKMAX MIN fPINMAX 1
SPIn
------------(,)=
SPIn
fPINMAX
fSPCKMAX 1
SPIn tVALID
+
------------------------------------=
SPIn
tVALID
tVALID
SPI7 SPI8
MISO
SPCK
MOSI
SPI6
SPI10 SPI11
MISO
SPCK
MOSI
SPI9
148
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Figure 9-16. SPI Slave Mode, NPCS Timing
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave inpu t frequency is given by the following formula:
Where is the MOSI se tup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depe nding on
CPOL and NCPHA. is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
ter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave out put frequency is given by the following formula:
SPI14
SPI12
SPI15
SPI13
NPCS
SPCK, CPOL=0
SPCK, CPOL=1
Table 9-63. SPI Timing, Slave Mode(1)
Symbol Parameter Conditions Min Max Units
SPI6 SPCK falling to MISO delay
VVDDIO from
2.85V to 3.6V,
maximum
external
capacitor =
40pF
19 47
ns
SPI7 MOSI setup time before SPCK rises 0
SPI8 MOSI hold time after SPCK rises 5.4
SPI9 SPCK rising to MISO delay 19 46
SPI10 MOSI setup time before SPCK falls 0
SPI11 MOSI hold time after SPCK falls 5.3
SPI12 NPCS setup time before SPCK rises 4
SPI13 NPCS hold time after SPCK falls 2.5
SPI14 NPCS setup time before SPCK fal ls 6
SPI15 NPCS hold time after SPCK rises 1.1
fSPCKMAX MIN fCLKSPI 1
SPIn
------------(,)=
SPIn
fCLKSPI
fSPCKMAX MIN fPINMAX 1
SPIn tSETUP
+
------------------------------------(, )=
149
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Where is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA. is the
SPI master setup time. refer to the SPI master datasheet for . is the maximu m
frequency of the SPI pins. refer to the I/ O Pin Characterist ics section for t he maximum f requency
of the pins.
9.10.4 TWIM/TWIS Timing
Figure 9-64 shows the TWI-bus timing requirements and the compliance of the device with
them. Some of these requirements (tr and tf) are met by the device without requiring user inter-
vention. Compliance with the other requireme nts (tHD-STA, tSU-STA, tSU-STO, tHD-DAT, tSU-DAT-TWI, tLOW-
TWI, tHIGH, and fTWCK) requires user intervention through appropriate programming of the relevant
TWIM and TWIS user interface registers. refer to the TWIM and TWIS sections for more
information.
Notes: 1. Standard mode: ; fast mode: .
SPIn
tSETUP
tSETUP
fPINMAX
Table 9-64. TWI-Bus Timing Requirements
Symbol Parameter Mode
Minimum Maximum
UnitRequirement Device Requirement Device
trTWCK and TWD rise time Standard(1) - 1000 ns
Fast(1) 20 + 0.1Cb300
tfTWCK and TWD fall time Standard - 300 ns
Fast 20 + 0. 1C b300
tHD-STA (Repeated) START hold time Standard 4 tclkpb -μs
Fast 0.6
tSU-STA (Repeated) START set-up time Standard 4.7 tclkpb -μs
Fast 0.6
tSU-STO STOP set-up time Standard 4.0 4tclkpb -μs
Fast 0.6
tHD-DAT Data hold time Standard 0.3(2) 2tclkpb 3.45() 15tprescaled + tclkpb μs
Fast 0.9()
tSU-DAT-TWI Data set-up time Standard 250 2tclkpb -ns
Fast 100
tSU-DAT --t
clkpb --
tLOW-TWI TWCK LOW period Standard 4.7 4tclkpb -μs
Fast 1.3
tLOW --t
clkpb --
tHIGH TWCK HIGH period Standard 4.0 8tclkpb -μs
Fast 0.6
fTWCK TWCK frequency Standard -100 kHz
Fast 400
1
12tclkpb
------------------------
fTWCK 100 kHz≤
fTWCK 100 kHz>
150
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2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK.
Notations:
Cb = total capacitance of one bus line in pF
tclkpb = period of TWI peripheral bus clock
tprescaled = period of TWI internal prescaled clock (see chapters on TWIM and TWIS)
The maximum tHD;DAT has only to be met if the device does no t stretch the LOW per iod (t LOW-TWI)
of TWCK.
9.10.5 JTAG Timing
Figure 9-17. JTAG Interface Signals
JTAG2
JTAG3
JTAG1
JTAG4
JTAG0
TMS/TDI
TCK
TDO
JTAG5
JTAG6
JTAG7 JTAG8
JTAG9
JTAG10
Boundary
Scan Inputs
Boundary
Scan Outputs
151
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Note: 1. These values are based on simulation. These values are not covered by test limits in production.
9.10.6 SWD Timing
Figure 9-18. SWD Interface Signals
Table 9-65. JTAG Timings(1)
Symbol Parameter Conditions Min Max Units
JTAG0 TCK Low Half-period
VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
21.8
ns
JTAG1 TCK High Half-period 8.6
JTAG2 TCK Period 30.3
JTAG3 TDI, TMS Setup before TCK High 2.0
JTAG4 TDI, TMS Hold after TCK High 2.3
JTAG5 TDO Hold Time 9.5
JTAG6 TCK Low to TDO Valid 21.8
JTAG7 Boundary Scan Inputs Setup Time 0.6
JTAG8 Boundary Scan Inputs Hold Time 6.9
JTAG9 Boundary Scan Outputs Hold Time 9.3
JTAG10 TCK to Boundary Scan Outputs Valid 32.2
Stop Park Tri State
AcknowledgeTri State Tri State
Parity StartData Data
Stop Park Tri State
AcknowledgeTri State
Start
Read Cycle
Write Cycle
Tos Thigh Tlow
Tis
Data Data Parity Tri State
Tih
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger
152
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Note: 1. These values are based on simulation. These values are not covered by test limits in production or characterization.
Table 9-66. SWD Timings(1)
Symbol Parameter Conditions Min Max Units
Thigh SWDCLK High period VVDDIO from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
10 500 000
ns
Tlow SWDCLK Low period 10 500 000
Tos SWDIO output skew to falling edge SWDCLK -5 5
Tis Input Setup time required between SWDIO 4 -
Tih Input Hold ti me required between SWDIO and
rising edge SWDCLK 1-
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10. Mechanical Characteristics
10.1 Thermal Considerations
10.1.1 Thermal Data Table 10-1 summarizes the thermal resistance data depending on the package.
10.1.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1.
2.
where:
•θJA = packa ge thermal resistance, Junction-to-ambient (°C/W), provided in Table 10-1.
•θJC = package thermal resistan ce, Junction-to-ca se thermal resistance (°C/W), provided in
Table 10-1.
•θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
•P
D = device power consumption (W) estimated from data provided in Section 9.5 on page 103 .
•T
A = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a
cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second
equation shou ld be used to compute the resulting average chip-junction temperature TJ in °C.
Table 10-1. Thermal Resistance Data
Symbol Parameter Condition Package Typ Unit
θJA Junction-to-ambient thermal resistance Still Air TQFP100 48.1 ⋅C/W
θJC Junction-to-case thermal resistance TQFP10 0 13.3
θJA Junction-to-ambient thermal resistance Still Air VFBGA100 31.1 ⋅C/W
θJC Junction-to-case thermal resistance VFBGA100 6.9
θJA Junction-to-ambient thermal resistance Still Air WLCSP64 26 .9 ⋅C/W
θJC Junction-to-case thermal resistance WLCSP6 4 0.2
θJA Junction-to-ambient thermal resista nce Still Air TQFP64 49.6 ⋅C/W
θJC Junction-to-case thermal resistance TQFP64 13.5
θJA Junction-to-ambient thermal resistance Still Air QFN64 22.0 ⋅C/W
θJC Junction-to-case thermal resistance QFN64 1.3
θJA Junction-to-ambient thermal resista nce Still Air TQFP48 51.1 ⋅C/W
θJC Junction-to-case thermal resistance TQFP48 13.7
θJA Junction-to-ambient thermal resistance Still Air QFN48 24.9 ⋅C/W
θJC Junction-to-case thermal resistance QFN48 1.3
TJTAPDθJA
×()+=
TJTAP(Dθ( HEATSINK
×θ
JC))++=
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10.2 Package Drawings
Figure 10-1. VFBGA-100 package drawing
Table 10-2. Device and Package Maximum Weight
120 mg
Table 10-3. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-4. Package Reference
JEDEC Drawing Reference N/A
JESD97 Classification E1
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Figure 10-2. TQFP-100 Package Drawing
Table 10-5. Device and Package Maximum Weight
500 mg
Table 10-6. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-7. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification E3
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Figure 10-3. WLCSP64 SAM4LC4/2 Package Drawing
Table 10-8. Device and Package Maximum Weight
14.8 mg
Table 10-9. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-10. Package Refe rence
JEDEC Drawing Reference MS-026
JESD97 Classification E1
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Figure 10-4. WLCSP64 SAM4LS4/2 Package Drawing
Table 10-11. Device and Package Maximum Weight
14.8 mg
Table 10-12. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-13. Package Refe rence
JEDEC Drawing Reference MS-026
JESD97 Classification E1
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Figure 10-5. WLCSP64 SAM4LC8 Package Drawin g
Table 10-14. Device and Package Maximum Weight
14.8 mg
Table 10-15. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-16. Package Refe rence
JEDEC Drawing Reference MS-026
JESD97 Classification E1
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Figure 10-6. WLCSP64 SAM4LS8 Package Drawing
Table 10-17. Device and Package Maximum Weight
14.8 mg
Table 10-18. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-19. Package Refe rence
JEDEC Drawing Reference MS-026
JESD97 Classification E1
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Figure 10-7. TQFP-64 Package Drawing
Table 10-20. Device and Package Maximum Weight
300 mg
Table 10-21. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-22. Package Refe rence
JEDEC Drawing Reference MS-026
JESD97 Classification E3
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Figure 10-8. QFN-64 Package Drawing
Note: The ex posed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.
Table 10-23. Device and Package Maximum Weight
200 mg
Table 10-24. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-25. Package Refe rence
JEDEC Drawing Reference MO-220
JESD97 Classification E3
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Figure 10-9. TQFP-48 (ATSAM4LC4/2 and ATSAM4LS4/2 Only) Package Drawing
Table 10-26. Device and Package Maximum Weight
140 mg
Table 10-27. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-28. Package Refe rence
JEDEC Drawing Reference MS-026
JESD97 Classification E3
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Figure 10-10. QFN-48 Package Drawing fo r ATSAM4LC4/2 and ATSAM4LS4/2
Note: The ex posed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.
Table 10-29. Device and Package Maximum Weight
140 mg
Table 10-30. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-31. Package Refe rence
JEDEC Drawing Reference MO-220
JESD97 Classification E3
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Figure 10-11. QFN-48 Package Drawing fo r ATSAM4LC8 and ATSAM4LS8
Note: The ex posed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.
Table 10-32. Device and Package Maximum Weight
140 mg
Table 10-33. Package Characteristics
Moisture Sensitivity Level MSL3
Table 10-34. Package Refe rence
JEDEC Drawing Reference MO-220
JESD97 Classification E3
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10.3 Soldering Profile
Table 10-35 gives the recommended soldering profile from J-STD-20.
A maximum of three reflow passes is allowed per component.
Table 10-35. Soldering Profile
Profile Feature Green Package
Average Ramp-up Rate (217°C to Peak) 3°C/s max
Preheat Temperature 175°C ±25°C 150-200°C
Time Maintained Above 217°C 60-150 s
Time within 5⋅C of Actual Peak Temperature 30 s
Peak Temperature Range 260°C
Ramp-down Rate 6°C/s max
Time 25⋅C to Peak Temperature 8 minutes max
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11. Ordering Information
Table 11-1. ATSAM4LC8 Sub Serie Ordering Information
Ordering Code Flash
(Kbytes) RAM
(Kbytes) Package Conditioning Package
Type Temperature Operating
Range
ATSAM4LC8CA-AU
512 64
TQFP100 Tray
Green Industrial -40°C to 85°C
ATSAM4LC8CA-AUR Reel
ATSAM4LC8CA-CFU VFBGA100 Tray
ATSAM4LC8CA-CFUR Reel
ATSAM4LC8BA-AU TQFP64 Tray
ATSAM4LC8BA-AUR Reel
ATSAM4LC8BA-MU QFN64 Tray
ATSAM4LC8BA-MUR Reel
ATSAM4LC8BA-UUR WLCSP64 Reel
ATSAM4LC8AA-MU QFN48 Tray
ATSAM4LC8AA-MUR Reel
Table 11-2. ATSAM4LC4 Sub Serie Ordering Information
Ordering Code Flash
(Kbytes) RAM
(Kbytes) Package Conditioning Package
Type Temperature Operating
Range
ATSAM4LC4CA-AU-ES
256 32
TQFP100
ES
Green
N/A
ATSAM4LC4CA-AU Tray Industrial -40°C to 85°C
ATSAM4LC4CA-AUR Reel
ATSAM4LC4CA-CFU VFBGA100 Tray Industrial -40°C to 85°C
ATSAM4LC4CA-CFUR Reel
ATSAM4LC4BA-AU-ES
TQFP64
ES N/A
ATSAM4LC4BA-AU Tray Industrial -40°C to 85°C
ATSAM4LC4BA-AUR Reel
ATSAM4LC4BA-MU-ES
QFN64
ES N/A
ATSAM4LC4BA-MU Tray Industrial -40°C to 85°C
ATSAM4LC4BA-MUR Reel
ATSAM4LC4BA-UUR WLCSP64 Reel Industrial -40°C to 85°C
ATSAM4LC4AA-AU-ES
TQFP48
ES N/A
ATSAM4LC4AA-AU Tray Industrial -40°C to 85°C
ATSAM4LC4AA-AUR Reel
ATSAM4LC4AA-MU-ES
QFN48
ES N/A
ATSAM4LC4AA-MU Tray Industrial -40°C to 85°C
ATSAM4LC4AA-MUR Reel
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Table 11-3. ATSAM4LC2 Sub Serie Ordering Information
Ordering Code Flash
(Kbytes) RAM
(Kbytes) Package Conditioning Package
Type Temperature Operating
Range
ATSAM4LC2CA-AU
128 32
TQFP100 Tray
Green Industrial -40°C to 85°C
ATSAM4LC2CA-AUR Reel
ATSAM4LC2CA-CFU VFBGA100 Tray
ATSAM4LC2CA-CFUR Reel
ATSAM4LC2BA-AU TQFP64 Tray
ATSAM4LC2BA-AUR Reel
ATSAM4LC2BA-MU QFN64 Tray
ATSAM4LC2BA-MUR Reel
ATSAM4LC2BA-UUR WLCSP64 Reel
ATSAM4LC2AA-AU TQFP48 Tray
ATSAM4LC2AA-AUR Reel
ATSAM4LC2AA-MU QFN48 Tray
ATSAM4LC2AA-MUR Reel
Table 11-4. ATSAM4LS8 Sub Serie Ordering Information
Ordering Code Flash
(Kbytes) RAM
(Kbytes) Package Conditioning Package
Type Temperature Operating
Range
ATSAM4LS8CA-AU
512 64
TQFP100 Tray
Green Industrial -40°C to 85°C
ATSAM4LS8CA-AUR Reel
ATSAM4LS8CA-CFU VFBGA100 Tray
ATSAM4LS8CA-CFUR Reel
ATSAM4LS8BA-AU TQFP64 Tray
ATSAM4LS8BA-AUR Reel
ATSAM4LS8BA-MU QFN64 Tray
ATSAM4LS8BA-MUR Reel
ATSAM4LS8BA-UUR WLCSP64 Reel
ATSAM4LS8AA-MU QFN48 Tray
ATSAM4LS8AA-MUR Reel
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Table 11-5. ATSAM4LS4 Sub Serie Ordering Information
Ordering Code Flash
(Kbytes) RAM
(Kbytes) Package Conditioning Package
Type Temperature Operating
Range
ATSAM4LS4CA-AU-ES
256 32
TQFP100
ES
Green
N/A
ATSAM4LS4CA-AU Tray Industrial -40°C to 85°C
ATSAM4LS4CA-AUR Reel
ATSAM4LS4CA-CFU VFBGA100 Tray Industrial -40°C to 85°C
ATSAM4LS4CA-CFUR Reel
ATSAM4LS4BA-AU-ES
TQFP64
ES N/A
ATSAM4LS4BA-AU Tray Industrial -40°C to 85°C
ATSAM4LS4BA-AUR Reel
ATSAM4LS4BA-MU-ES
QFN64
ES N/A
ATSAM4LS4BA-MU Tray Industrial -40°C to 85°C
ATSAM4LS4BA-MUR Reel
ATSAM4LS4BA-UUR WLCSP64 Reel Industrial -40°C to 85°C
ATSAM4LS4AA-AU-ES
TQFP48
ES N/A
ATSAM4LS4AA-AU Tray Industrial -40°C to 85°C
ATSAM4LS4AA-AUR Reel
ATSAM4LS4AA-MU-ES
QFN48
ES N/A
ATSAM4LS4AA-MU Tray Industrial -40°C to 85°C
ATSAM4LS4AA-MUR Reel
Table 11-6. ATSAM4LS2 Sub Serie Ordering Information
Ordering Code Flash
(Kbytes) RAM
(Kbytes) Package Conditioning Package
Type Temperature Operating
Range
ATSAM4LS2CA-AU
128 32
TQFP100 Tray
Green Industrial -40°C to 85°C
ATSAM4LS2CA-AUR Reel
ATSAM4LS2CA-CFU VFBGA100 Tray
ATSAM4LS2CA-CFUR Reel
ATSAM4LS2BA-AU TQFP64 Tray
ATSAM4LS2BA-AUR Reel
ATSAM4LS2BA-MU QFN64 Tray
ATSAM4LS2BA-MUR Reel
ATSAM4LS2BA-UUR WLCSP64 Reel
ATSAM4LS2AA-AU TQFP48 Tray
ATSAM4LS2AA-AUR Reel
ATSAM4LS2AA-MU QFN48 Tray
ATSAM4LS2AA-MUR Reel
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12. Errata
12.1 ATSAM4L4 /2 Rev. B & ATSAM4L8 Rev. A
12.1.1 General
PS2 mode is not supported by Engineering Samples
PS2 mode support is supported only by parts with calibration version higher than 0.
Fix/Workaround
The calibration version can be checked by reading a 32-bit word at address 0x0080020C.
The calibration version bitfield is 4-bit wide and located from bit 4 to bit 7 in this word. Any
value higher than 0 ensures that the part supports the PS2 mode
12.1.2 SCIF
PLLCOUNT value larger than zero can cause PLLEN glitch
Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-
nal during asynch ro no us wake up.
Fix/Workaround
The lock-masking mechanism for the PLL should not be used.
The PLLCOUNT field of the PLL Control Register should always be written to zero.
12.1.3 WDT
WDT Control Register does not have synchronization feed back
When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),
Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-
nizer is started to propagate the values to the WDT clcok domain. This synchronization
takes a finite amoun t of time, but only the status of the synch ronization of the EN bit is
reflected back to the user. Writing to the synchr onized fi elds during synchronization can lead
to undefined behavior.
Fix/Workaround
-When writing to the affected fields, the user m ust ensure a wait corresponding to 2 clock
cycles of both the WDT peripher al bus clock and the selected WDT clock source.
-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the
written value.
12.1.4 SPI
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault de tection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
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Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disab le t he SPI . To cont in ue the tr ansf er , ena ble the
SPI and PDCA.
SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
12.1.5 TC
Channel chaining skips first pulse for upper channel
When chaining two channels using the Block Mode Register, the first pulse of the clock
between the channels is skipped.
Fix/Workaround
Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle
for the upper channel. After the dummy cycle has been generated, indicated by the
SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real
values.
12.1.6 USBC
In USB host mode, entering suspend mode for low speed device can fail when the
USB freeze (USBCON.FRZCLK=1) is done just after UHCON.SOFE=0.
Fix/Workaround
When entering suspend mode (UHCON.SOFE is cleared), check that USBFSM.DRDSTATE
is not equal to three bef ore freezing the clock (USBCON.FRZCLK=1).
In USB host mode, the asynchronous attach detection (UDINT.HWUPI) can fail when
the USB clock freeze (USBCON.FRZCLK=1) is done just after setting the USB-
STA.VBUSRQ bit.
Fix/Workaround
After setting USBSTA.VBUSRQ bit, wait until the USBFSM register value is
‘A_WAIT_BCON’ before setting t he USBCON.FRZCLK bit.
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12.1.7 FLASHCALW
Corrupted data in flash may happen after flash page write operations.
After a flash page write operation, reading (data read or code fetch) in flash may fail. This
may lead to an expecption or to others errors derived from this corr upted read access.
Fix/Workaround
Before any flash page write o peration, each 64 -bit doublewo rds write in the page buffer must
preceded by a 64-bit doublewords write in the page buffer with 0xFFFFFFFF_FFFFFFFF
content at any address in the page. Note that special care is required when loading page
buffer, refe r to Section 2.5.9 ”Page Buffer Operations” on page 11 .
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13. Datasheet Revision History
Note that the referring page numbers in this section are referred to this document. The referring
revision in this section are referring to the document revision.
13.1 Rev. A – 09/12
13.2 Rev. B – 10/12
13.3 Rev. C – 02/13
13.4 Rev. D – 03/13
1. Initial revision.
1. Fixed ordering code
2. Changed BOD18CTRL and BOD33CTRL ACTION field from “Reserved” to ‘No action”
1. Fixed ball pitch for VFBGA100 pa ckage
2. Added VFBGA100 and WLCSP64 pinouts
3. Added Power Scaling Mode 2 for high frequency support
4. Minor update on several modules chapters
5. Major update on Electrical characteristic s
6. Updated errata
7. Fixed GPIO multiplexing pi n numbers
1. Removed WLCSP package information
2. Add ed errata text for detecting whether a part supports PS2 mode or not
3. Removed temperature sensor feature (not supported by production flow)
4. Fixed MUX selection on Posi tive ADC input channel table
5. Added information about TWI instances capabilities
6. Added some details on errata Corrupted data in flash may happen after flash page write
operations.171
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13.5 Rev. E – 07/13
13.6 Rev. F– 12/13
13.7 Rev. G– 03/14
1. Added ATSAM4L8 derivatives and WLCSP packages for AT SAM4L4/2
2. Add ed operating conditions details in Electrical Character istics Chapter
3. Fixed “Supply Rise Rates and Order”
4. Added number of USART available in sub-ser i es
5. Fixed IO line considerations for USB pins
6. Removed useless information about CPU local bus which is not implemented
7. Removed useless information about Modem support which is not implemented
8. Added information about unsupported features in Power Scaling mode 1
9. Fixe d SPI ti ming s
1. Fixed table 3-6 - TDI is connected to pin G3 in WLCSP package
2. Changed table 42-48 -ADCIFE Electricals in unipolar mode : PSRR & DC supply current
typical values
3. Fixed SPI timing characteristics
4. Fixed BOD33 typical step size value
1. Added WLCSP64 packages for SAM4LC8 and SAM4LS8 sub-series
2. Removed unsuppported SWAP feature in LCD module
3. Added mnimal value for ADC Reference range
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Table of Contents
Summary.................................................................................................... 1
Features..................................................................................................... 1
1 Description ............................................................................................... 3
2 Overview ................................................................................................... 5
2.1 Block Diagr am .................... ................ ... ................ ... .... ................ ... ... ...............5
2.2 Configuration Summary .....................................................................................6
3 Package and Pinout ................................................................................. 9
3.1 Packag e .... ...... ... ....... ...... ....... ...... ....... ...... ... ....... ...... ....... ...... ....... ...... ....... ... .....9
3.2 Peripheral Multiplexing on I/O lines .................................................................19
3.3 Signals Description ................... ... .... ................ ... ... ................ ... ................. ... ...3 1
3.4 I/O Line Co ns id e ra tio ns ............... .... ... ... ................ ... ................ ................. ... ...34
4 Cortex-M4 processor and core peripherals ......................................... 36
4.1 Cortex-M4 ........................................................................................................36
4.2 Syste m lev el inte r fac e .............. ................ ... ................. ... ................ ................3 7
4.3 Integrated configurable debug .........................................................................37
4.4 Cort ex -M 4 pr oc essor features an d be n ef its sum m ar y ........ ... ... .... ...................38
4.5 Cortex-M4 core periph e ra ls ... ... ... ................ .... ................ ... ................ ... ..........38
4.6 Cortex -M 4 im ple m en ta tio ns op tio ns ...... ................ ... .... ................ ... ... .............39
4.7 Cortex-M4 Interrup ts ma p ................ ... ................ ... ................ ... ................. ... ...39
4.8 Peripheral Debug .............................................................................................42
5 Memories ................................................................................................ 43
5.1 Product Mapping .............................................................................................43
5.2 Embedded Memories ......................................................................................44
5.3 Physic al Me m or y Ma p ................. .... ... ... ... ................ .... ................ ... ................4 4
6 Power and Startup Considerations ...................................................... 46
6.1 Power Domain Overview .................................................................................46
6.2 Power Supplies ................................................................................................48
6.3 Startup Considerations ....................................................................................53
6.4 Power-on-Reset, Brownout and Supply Monitor .............................................53
7 Low Power Techniques ......................................................................... 55
7.1 Power Save Modes .........................................................................................55
7.2 Power Scaling ..................................................................................................60
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8 Debug and Test ...................................................................................... 62
8.1 Features ..........................................................................................................62
8.2 Overvie w ...... ...... ....... ...... ....... ... ....... ...... ...... ....... ...... ....... ...... ....... ...... ... ....... ...62
8.3 Block diagr a m ................. .... ................ ... ................ ... .... ................ ... ................6 3
8.4 I/O Lines Descr ip tion ................... .... ... ... ................ ... ................ .... ... ................6 3
8.5 Product dependencies .....................................................................................64
8.6 Core debug ......................................................................................................64
8.7 Enhanced Debug Port (EDP) ..........................................................................67
8.8 AHB-AP Acce ss Por t ... ... .... ... ... ... .... ... ................ ... ... ................ .... ... ... .............77
8.9 Syste m Ma n age r Acce ss Por t (SM AP) ........ .... ... ... ................ ... .... ................ ...7 8
8.10 Available Features in Protected State ................... ... .... ... ................ ... ... .... ... ...93
8.11 Functional Description ........ ... ................ ... ... ................. ... ................ ... ... ..........94
9 Electrical Characteristics ...................................................................... 99
9.1 Abso lut e Ma xim u m Ra ting s* .............. ... ................ ... ................ .... ................ ...9 9
9.2 Opera tin g Co nd itio ns ................................ ... ................. ... ................ ................9 9
9.3 Suppl y Char acteristics . ... .... ................ ... ... ................ .... ... ................ ... ... ..........99
9.4 Maximum Clock Frequencies ........................................................................101
9.5 Power Consumption ......................................................................................103
9.6 I/O Pin Char act er istics ........ ... ... ................ ... .... ................ ... ... ................ .... ....114
9.7 Oscillator Characteristics ...............................................................................121
9.8 Flash Ch ar ac ter i st ic s ... ... .... ................ ... ................ ... ................ .... ................ .12 7
9.9 Analog Characteristics ...................................................................................129
9.10 Timing Characteristics ...................................................................................140
10 Mechanical Characteristics ................................................................. 153
10.1 Thermal Considerations ................................................................................153
10.2 Package Drawings ....... ... .... ... ................ ... ... ................. ... ... ................ ... ........154
10.3 Soldering Profile ............................................................................................165
11 Ordering Information ........................................................................... 166
12 Errata ..................................................................................................... 169
12.1 ATSAM4L4 /2 Rev. B & ATSAM4L8 Rev. A ..................................................169
13 Datasheet Revision History ................................................................ 172
13.1 Rev. A – 09/12 ...............................................................................................172
13.2 Rev. B – 10/12 ...............................................................................................172
13.3 Rev. C – 02/13 ...............................................................................................172
42023GS–SAM–03/2014
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13.4 Rev. D – 03/13 ...............................................................................................172
13.5 Rev. E – 07/13 ...............................................................................................173
13.6 Rev. F– 12/13 ................................................................................................173
13.7 Rev. G– 03/14 ...............................................................................................173
Table of Contents.................................................................................. 174