CD4094BCN - Fairchild Semiconductor

October 1987

Revised April 2002

CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs

CD4094BC

8-Bit Shift Register/Latch with 3-STATE Outputs

General Description

The CD4094BC consists of an 8-bit shift register and a

3-STATE 8-bit latch. Data is shifted serially through the

shift register on the positive transition of the clock. The out-

put of the l ast stage (QS) can b e used to cascade several

devices. Data on the Q S output is tra nsferred to a second

output, Q′S, on the following negative clock edge.

The output of ea ch stage of the shift regi ster feed s a latch,

which latches data on the negative edge of the STROBE

input. When STROBE is HIGH, data propagates through

the latch to 3-STATE output gates. These gates are

enabled when OUTPUT ENABLE is taken HIGH.

Features

■Wide supply voltage rang e: 3.0V to 18V

■High noise immunity: 0.45 VDD (typ.)

■Low power TTL compatibility:

Fan out of 2 driving 74L or 1 driving 74LS

■3-STATE outputs

Ordering Code:

Devices also available in Tape and Reel. Spe ci fy by append ing the suffix let t er “X” to the o rdering code.

Connection Diagram

Top View

Truth Table

X = Don't Care



= HIGH-to-LOW



= LOW-to-HIGH

Note 1: At the positiv e c lock edge, information in th e 7t h s hift regis t er stage is tr ansferre d t o Q8 and QS.

Order Number Package Number Package Description

CD4094BCWM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

CD4094BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Clock Output Strobe Data Parallel Outputs Serial Outputs

Enable Q1 QNQS

(Note 1) Q′Σ



0 X X Hi-Z Hi-Z Q7 No Change



0 X X Hi-Z Hi-Z No Change Q7



1 0 X No Change No Change Q7 No Change



1100Q

N−1 Q7 No Change



1111Q

N−1 Q7 No Change



1 1 1 No Change No Change No Change Q7

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CD4094BC

Block Diagram

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CD4094BC

Absolute Maximum Ratings(Note 2)

(Note 3) Recommended Operating

Conditions (Note 3)

Note 2: “Absolute Maximum Ratings” are those va lues beyond which t he

safety of th e device ca nnot be guaranteed; th ey are not meant to imply th at

the devices should be operated at these limits. The tables of “Recom-

mended Operating Conditions” and “Electrical Charac t eristics” pro v ide con-

ditions f or actual device o peration.

Note 3: VSS = 0V unles s ot herwise s pecified .

DC Electrical Characteristics (Note 3)

Note 4: IOH and IOL are test ed one ou tput at a tim e.

Supply Voltage (VDD)−0.5 to +18 VDC

Input Voltage (VIN)−0.5 to VDD +0.5 VDC

Stora ge Tem per atu re Range (TS)−65°C to +150°C

Power Di ssipa ti on (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds ) 260 °C

DC Supply Voltage (VDD)+3.0 to +15 VDC

Input Voltage (VIN) 0 to VDD VDC

Operating Temperature Range (TA)−55°C to +125°C

Symbol Parameter Conditions 55°C+25°C+125°CUnits

Min Max Min Typ Max Min Max

IDD Quiescent VDD = 5.0V 5.0 5.0 150 µADevice Current VDD = 10V 10 10 300

VDD = 15V 20 20 600

VOL LOW Level VDD = 5.0V 0.05 0 0.05 0.05 VOutput Voltage VDD = 10V |IO| ≤ 1.0 µA 0.05 0 0.05 0.05

VDD = 15V 0.05 0 0.05 0.05

VOH HIGH Level VDD = 5.0V 4.95 4.95 5.0 4.95 VOutput Voltage VDD = 10V |IO| ≤ 1 µA9.959.9510.09.95

VDD = 15V 14.95 14.95 15.0 14.95

VIL LOW Level VDD = 5.0V, VO = 0.5V or 4.5V 1.5 1.5 1.5 VInput Voltage VDD = 10V, VO = 1.0V or 9.0V 3.0 3.0 3.0

VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0

VIH HIGH Level VDD = 5.0V, VO = 0.5V or 4.5V 3.5 3.5 3.5 VInput Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 7.0

VDD = 15V, VO = 1.5V or 1 3.5V 11.0 11.0 11.0

IOL LOW Level VDD = 5.0V, VO = 0.4V 0.64 0.51 0.88 0.36 mAOutput Current VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9

(Note 4) VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4

IOH HIGH Level VDD = 5.0V, VO = 4.6V −0.64 −0.51 0.88 −0.36 mAOutput Current VDD = 10V, VO = 9.5V −1.6 −1.3 2.25 −0.9

(Note 4) VDD = 15V, VO = 13.5V −4.2 −3.4 8.8 −2.4

IIN Input Current VDD = 15V, V IN = 0V −0.1 −0.1 −1.0 µA

VDD = 15V, VIN = 15V 0.1 0.1 1.0

IOZ 3-STATE Output VDD = 15V, V IN = 0V or 15V 0.3 ±0.3 ±9µA

Leakage Current

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CD4094BC

AC Electrical Characteristics (Note 5)

TA = 25°C, CL = 50 pF

Note 5: AC Parameters are guara nt eed by DC c orrelat ed testing.

Symbol Parameter Conditions Min Typ Max Units

tPHL, tPLH Propagation Delay VDD = 5.0V 300 600 nsClock to QSVDD = 10V 125 250

VDD = 15V 95 190

tPHL, tPLH Propagation Delay VDD = 5.0V 230 460 nsClock to Q′ΣVDD = 10V 110 220

VDD = 15V 75 150

tPHL, tPLH Propagation Delay Clock VDD = 5.0V 420 840 nsto Parallel Out VDD = 10V 195 390

VDD = 15V 135 270

tPHL, tPLH Propagation Delay Strobe VDD = 5.0V 290 580 nsto Parallel Out VDD = 10V 145 290

VDD = 15V 100 200

tPHZ Propagation Delay HIGH VDD = 5.0V 140 280 nsLevel to HIGH Impedance VDD = 10V 75 150

VDD = 15V 55 110

tPLZ Propagation De lay LOW VDD = 5.0V 140 280 nsLevel to HIGH Impedance VDD = 10V 75 150

VDD = 15V 55 110

tPZH Propagati on Delay HIGH VDD = 5.0V 140 280 nsImpedance to HIGH Level VDD = 10V 75 150

VDD = 15V 55 110

tPZL Propagati on Delay HIGH VDD = 5.0V 140 280 nsImpedance to LOW Level VDD = 10V 75 150

VDD = 15V 55 110

tTHL, tTLH Transition Time VDD = 5.0V 100 200 nsVDD = 10V 50 100

VDD = 15V 40 80

tSU Set-Up Time VDD = 5.0V 80 40 nsData to Clock VDD = 10V 40 20

VDD = 15V 20 10

tr, tfMaximum Clock Rise VDD = 5.0V 1 msand Fall Time VDD = 10V 1

VDD = 15V 1

tPC Minimum Clock VDD = 5.0V 200 100 nsPulse Width VDD = 10V 100 50

VDD = 15V 83 40

tPS Minimum Strobe VDD = 5.0V 200 100 nsPulse Width VDD = 10V 80 40

VDD = 15V 70 35

fmax Maximum Clock Frequency VDD = 5.0V 1.5 3.0 MHzVDD = 10V 3.0 6.0

VDD = 15V 4.0 8.0

CIN Input Capacitance Any Input 5.0 7.5 pF

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CD4094BC

Timing Diagram

Test Circuits and Timing Diagrams for 3-STATE

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CD4094BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M16B

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CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circuit pat ent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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