1. General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. It is
designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply
environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) dete rmine the direction of the data flow.
nDIR (active HIGH) enables dat a from nAn port s to nBn port s. nDIR (active LOW) enables
data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH,
disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins
nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B).
In suspend mode, when one of the supply voltages is zero, there will be no current flow
from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state
and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) VCC(A)
(except in suspend mode).
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range:
3 V port (VCC(A)): 1.5 V to 3.6 V
5 V port (VCC(B)): 1.5 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Control inputs voltage range from 2.7 V to 5.5 V
Inputs accept voltages up to 5.5 V
High-impedance outputs when VCC(A) or VCC(B) = 0 V
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and 40 C to +125 C
74ALVC164245
16-bit dual supply translating transceiver; 3-state
Rev. 8 — 15 March 2012 Product data sheet
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 2 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Temperature
range Package
Name Description Version
74ALVC164245DL 40 C to +125 C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm SOT370-1
74ALVC164245DGG 40 C to +125 C TSSOP48 plastic thin shrink small outline package; 48 leads;
body width 6.1 mm SOT362-1
74ALVC164245BX 40 C to +125 C HXQFN60 plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4 6 0.5 mm
SOT1134-2
Fig 1. Logic symbol
1DIR
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1OE
2DIR
2OE
001aaa789
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 3 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Fig 2. IEC logic symbol
G3
G6
3EN1[BA]
6EN1[BA]
3EN2[AB]
6EN2[AB]
1A0
2A1
2A0
2A2
2A3
2A4
2A5
2A6
2A7
2B1
2B2
2B3
2B4
2B5
2B6
2B7
1OE
1DIR
001aaa790
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1B0
2B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
5
4
2
1
2OE
2DIR
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 4 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
Fig 3. Pin co nfiguration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
74ALVC164245
1DIR 1OE
1B0 1A0
1B1 1A1
GND GND
1B2 1A2
1B3 1A3
V
CC(B)
V
CC(A)
1B4 1A4
1B5 1A5
GND GND
1B6 1A6
1B7 1A7
2B0 2A0
2B1 2A1
GND GND
2B2 2A2
2B3 2A3
V
CC(B)
V
CC(A)
2B4 2A4
2B5 2A5
GND GND
2B6 2A6
2B7 2A7
2DIR 2OE
001aab037
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 5 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 4. Pin co nfiguration SOT1134-2 (HXQFN60)
D1
D3A16A15A14A13A12A11D2
B9 B10 D7 A17
A18
B11
A19
B12
A20
B13
A21
B14
B8
A10 D6
A9
A8
B7
B6
A7
B5
A6
A22
B15
A23
B16
A24
B17
A25
A26
D8
D4A27
B18
A28A29
B19B20
A30A31A32
B4
A5
B3
B2
B1
D5
A4
A3
A2
A1
74ALVC164245
001aai851
Transparent top view
GND
(1)
terminal 1
index area
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 6 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 2. Pin description
Symbol Pin Description
SOT370-1 and SOT362-1 SOT1134-2
1DIR, 2DIR 1, 24 A30, A13 direction control input
1B0 to 1B7 2, 3, 5, 6, 8, 9, 11, 12 B20, A31, D5, D1, A2, B2, B3, A5 data input/output
2B0 to 2B7 13, 14, 16, 17, 19, 20, 22, 23 A6, B5, B6, A9, D2, D6, A12, B8 data input/output
GND 4, 10, 15, 21, 28, 34, 39, 45 A32, A3, A8, A11, A16, A19, A24, A27 ground (0 V)
VCC(B) 7, 18 A1, A10, supply voltage B (5 V bus)
1OE, 2OE 48, 25 A29, A14 output enable input (active LOW)
1A0 to 1A7 47, 46, 44, 43, 41, 40, 38, 37 B18, A28, D8, D4, A25, B16, B15, A22 data input/output
2A0 to 2A7 36, 35, 33, 32, 30, 29, 27, 26 A21, B13, B12, A18, D3, D7, A1 5, B10 data input/output
VCC(A) 31, 42 A17, A26 supply voltage A (3 V bus)
n.c. - A4, A7, A20, A23, B1, B4, B7, B9, B11,
B14, B17, B19 not connected
Table 3. Function table[1]
Inputs Outputs
nOE nDIR nAn nBn
L L nAn = nBn inputs
L H inputs nBn = nAn
HXZZ
Table 4. L imiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Volt ages are referenced to GND (ground = 0 V). See
[1].
Symbol Parameter Conditions Min Max Unit
VCC(B) supply voltage B VCC(B) VCC(A) 0.5 +6.0 V
VCC(A) supply voltage A VCC(B) VCC(A) 0.5 +4.6 V
IIK input clam pi n g cu rre nt VI<0V 50 - mA
VIinput voltage [2] 0.5 +6.0 V
VI/O input/output voltage 0.5 VCC +0.5 V
IOK output clamping current VO>V
CC or VO<0V - 50 mA
VOoutput voltage output HIGH or LOW [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.0 V
IO(sink/source) output sink or source
current VO=0VtoV
CC -50 mA
ICC supply cur r en t - 100 mA
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 7 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create j unction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
[2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C
(T)SSOP48 package [3] -500mW
HXQFN60 package [4] - 1000 mW
Table 4. L imiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Volt ages are referenced to GND (ground = 0 V). See
[1].
Symbol Parameter Conditions Min Max Unit
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC(B) supply voltage B VCC(B) VCC(A)
maximum speed performance 2.7 - 5.5 V
low-voltage applications 1.5 - 5.5 V
VCC(A) supply voltage A VCC(B) VCC(A)
maximum speed performance 2.7 - 3.6 V
low-voltage applications 1.5 - 3.6 V
VIinput voltage control inputs: nOE and nDIR 0- 5.5V
VI/O input/output voltage nAn port 0 - VCC(A) V
nBn port 0 - VCC(B) V
VOoutput voltage nAn port 0 - VCC(A) V
nBn port 0 - VCC(B) V
Tamb ambient temp erature 40 - +125 C
t/V input transition rise
and fall rate VCC(A) = 2.7 V to 3.0 V 0 - 20 ns/V
VCC(A) = 3.0 V to 3.6 V 0 - 10 ns/V
VCC(B) = 3.0 V to 4.5 V 0 - 20 ns/V
VCC(B) = 4.5 V to 5.5 V 0 - 10 ns/V
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Product data sheet Rev. 8 — 15 March 2012 8 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Typ[1] Max
VIH HIGH-level
input voltage nBn port
VCC(B) = 3.0 V to 5.5 V [2] 2.0 - - 2.0 - - V
nAn port, nOE and nDIR
VCC(A) = 3.0 V to 3.6 V 2.0 - - 2.0 - - V
VCC(A) = 2.3 V to 2.7 V [2] 1.7 - - 1.7 - - V
VIL LOW-level
input voltage nBn port
VCC(B) = 4.5 V to 5.5 V [2] --0.8--0.8V
VCC(B) = 3.0 V to 3.6 V [2] --0.7--0.7V
nAn port, nOE and nDIR
VCC(A) = 3.0 V to 3.6 V - - 0.8 - - 0.8 V
VCC(A) = 2.3 V to 2.7 V [2] --0.7--0.7V
VOH HIGH-level
output voltage nBn port; VI=V
IH or VIL
IO=24 mA; VCC(B) = 4.5 V VCC(B) 0.8 - - VCC(B) 1.2 - - V
IO=12 mA; VCC(B) = 4.5 V VCC(B) 0.5 - - VCC(B) 0.8 - - V
IO=18 mA; VCC(B) = 3.0 V VCC(B) 0.8 - - VCC(B) 1.0 - - V
IO=100 A; VCC(B) = 3.0 V VCC(B) 0.2 VCC(B) -V
CC(B) 0.3 VCC(B) -V
nAn port; VI=V
IH or VIL
IO=24 mA; VCC(A) = 3.0 V VCC(A) 0.7 - - VCC(A) 1.0 - - V
IO=100 A; VCC(A) = 3.0 V VCC(A) 0.2 - - VCC(A) 0.3 - - V
IO=12 mA; VCC(A) = 2.7 V VCC(A) 0.5 - - VCC(A) 0.8 - - V
IO=8mA; V
CC(A) = 2.3 V VCC(A) 0.6 - - VCC(A) 0.6 - - V
IO=100 A; VCC(A) = 2.3 V VCC(A) 0.2 VCC(A) -V
CC(A) 0.3 VCC(A) -V
VOL LOW-level
output voltage nBn port; VI=V
IH or VIL
IO=24mA; V
CC(B) = 4.5 V - - 0.55 - - 0.60 V
IO = 12 mA; VCC(B) = 4.5 V - - 0.40 - - 0.80 V
IO= 100 A; VCC(B) = 4.5 V - - 0.20 - - 0.30 V
IO= 18 mA; VCC(B) = 3.0 V - - 0.55 - - 0.80 V
IO= 100 A; VCC(B) = 3.0 V - - 0.20 - - 0.30 V
nAn port; VI=V
IH or VIL
IO= 24 mA; VCC(A) = 3.0 V - - 0.55 - - 0.80 V
IO= 100 A; VCC(A) = 3.0 V - - 0.20 - - 0.30 V
IO= 12 mA; VCC(A) = 2.7 V - - 0.40 - - 0.60 V
IO= 12 mA; VCC(A) = 2.3 V - - 0.60 - - 0.60 V
IO= 100 A; VCC(A) = 2.3 V - - 0.20 - - 0.20 V
IIinput leakage
current VI=5.5VorGND - 0.1 5-0.1 10 A
IOZ OFF-state
output current VI=V
IH or VIL;
VO=V
CC or GND [3] -0.1 10 - 0.1 20 A
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 9 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
[1] All typical values are measured at VCC(B) = 5.0 V, VCC(A) = 3.3 V and Tamb =25C.
[2] If VCC(A) < 2.7 V, the switching levels at all inputs are not TTL compatible.
[3] For transceivers, the parameter IOZ includes the input leakage current.
[4] VCC(A) = 2.7 V to 3.6 V: other inputs at VCC(A) or GND; VCC(B) = 4.5 V to 5.5 V: other inputs at VCC(B) or GND.
10. Dynamic characteristics
ICC supply current VI=V
CC or GND; IO= 0 A - 0.1 40 - 0.1 80 A
ICC additional
supply current per control pin;
VI=V
CC 0.6 V; IO=0A [4] - 5 500 - 5 5000 A
CIinput
capacitance -4.0-- --pF
CI/O input/output
capacit ance nAn and nBn port - 5.0 - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Typ[1] Max
Table 7. Dynamic characteristics
GND = 0 V; tr = tf
2.5 ns; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter Conditions Tamb = 40 C to +85 CTamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation
delay nAn to nBn; see Figure 5 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 1.5 3.3 7.6 1.5 9.5 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 1.0 3.0 5.9 1.0 7.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 1.0 2.9 5.8 1.0 7.5 ns
nBn to nAn; see Figure 5 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 1.0 3.0 7.6 1.0 9.5 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 1.0 4.3 6.7 1.0 8.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 1.2 2.5 5.8 1.2 7.5 ns
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Product data sheet Rev. 8 — 15 March 2012 10 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
ten enable time nOE to nBn; see Figure 6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 1.5 4.1 11.5 1.5 14.5 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 1.5 3.6 9.2 1.5 11.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 1.0 3.2 8.9 1.0 12.0 ns
nOE to nAn; see Figure 6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 1.5 4.6 12.3 1.5 15.5 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 1.5 4.3 9.3 1.5 12.0 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 1.0 3.2 8.9 1.0 11.5 ns
tdis disable time nOE to nBn; see Figure 6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 2.0 2.7 10.5 2.0 13.5 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 2.5 4.6 9.0 2.5 11.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 2.1 4.9 8.6 2.1 11.0 ns
nOE to nAn; see Figure 6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 1.0 2.7 9.3 1.0 12.0 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 1.5 3.5 9.0 1.5 11.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 2.0 3.2 8.6 2.0 11.0 ns
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf
2.5 ns; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter Conditions Tamb = 40 C to +85 CTamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
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Product data sheet Rev. 8 — 15 March 2012 11 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
[1] All typical values are measured at nominal voltage for VCC(B) and VCC(A) and at Tamb =25C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
[4] The condition is VI = GND to VCC.
11. AC waveforms
CPD power
dissipation
capacitance
5 V port: nAn to nBn;
VCC(B) = 5 V; VCC(A) = 3.3 V [3][4]
outputs enabled - 30 - - - pF
outputs disabled - 15 - - - pF
3 V port: nBn to nAn;
VCC(B) = 5 V; VCC(A) = 3.3 V [3][4]
outputs enabled - 40 - - - pF
outputs disabled - 5 - - - pF
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf
2.5 ns; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter Conditions Tamb = 40 C to +85 CTamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. Input (nAn, nBn) to output (nBn, nAn) propagation delays
001aaa792
nAn, nBn
input
nBn, nAn
output
tPHL tPLH
GND
VI
VM
VM
VOH
VOL
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Product data sheet Rev. 8 — 15 March 2012 12 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with output load.
Fig 6. 3-state ena ble and disable tim e s
mna362
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 8. Mea surement points
Direction Supply voltage Input Output
VCC(A) VCC(B) VIVMVMVXVY
nAn port to nBn
port 2.3 V to 2.7 V 2.7 V to 3.6 V VCC(A) 0.5 VCC(A) 1.5 V VOL(B) + 0.3 V VOH(B) 0.3 V
nBn port to nAn
port 2.3 V to 2.7 V 2.7 V to 3.6 V 2.7 V 1.5 V 0.5 VCC(A) VOL(A) + 0.15 V VOH(A) 0.15 V
nAn port to nBn
port 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V 1.5 V 0.5 VCC(B) 0.2 VCC(B) 0.8 VCC(B)
nBn port to nAn
port 2.7 V to 3.6 V 4.5 V to 5.5 V 3.0 V 1.5 V 1.5 V VOL(A) + 0.3 V VOH(A) 0.3 V
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Product data sheet Rev. 8 — 15 March 2012 13 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
Fig 7. Test circuit for measu ring switching times
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Table 9. Test da ta
Direction Supply voltage Load VEXT
VCC(A) VCC(B) CLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ
nAn port to nBn
port 2.3 V to 2.7 V 2.7 V to 3.6 V 50 pF 500 open GND 2 VCC
nBn port to nAn
port 2.3 V to 2.7 V 2.7 V to 3.6 V 50 pF 500 open GND 6.0 V
nAn port to nBn
port 2.7 V to 3.6 V 4.5 V to 5.5 V 50 pF 500 open GND 2 VCC
nBn port to nAn
port 2.7 V to 3.6 V 4.5 V to 5.5 V 50 pF 500 open GND 6.0 V
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 14 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
12. Package outline
Fig 8. Package outline SOT370-1 (SSOP48)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 15 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Fig 9. Package outline SOT362-1 (TSSOP48)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 16 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Fig 10. Package outline SOT1134-2 (HXQFN60)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1134-2 - - -
- - -
- - -
sot1134-2_po
11-08-15
Unit
mm max
nom
min
0.50 0.08
0.05
0.02
0.28
0.23
0.18
1.95
1.85
1.75
6.1
6.0
5.9
3.95
3.85
3.75 1.0 2.5 4.5 0.195
0.145
0.095 0.1
A
Dimensions
HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads;
60 terminals; body 4 x 6 x 0.5 mm SOT1134-2
A1A2
0.42
0.40
0.38
bD
4.1
4.0
3.9
DhEE
h
0.08 0.1
yy
1
e
0.5
e1e2e3
3.0
e4eT
0.49
eR
0.5
K
0.25
0.20
0.15
L
0.28
0.23
0.18
L1v
0.05
w
0 5 mm
terminal 1
index area
BA
D
E
C
y
C
y1
X
detail X
A A2
A1
terminal 1
index area
e2
e1
eT
eR
eT
eR
e4
e3
e
e
1/2 e
1/2 e
AC B
vC
w
bAC B
vC
w
Dh
K
L
Eh
L1
B1
A1
B7
D5 D8
D6 D7
D1 D4
D2 D3
B20 B18 A27
A26
A17
B11
B17
A11 B8 B10 A16
A32
A10
eR
eT
eR
eT
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 17 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
13. Abbreviations
14. Revision history
Table 10. Ab br eviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74ALVC164245 v.8 20120315 Product data sheet - 74ALVC164245 v.7
Modifications: •For type number 74ALVC164245BX the sot code has changed to SOT1134-2.
74ALVC164245 v.7 20111117 Product data sheet - 74ALVC164245 v.6
Modifications: •Legal pages updated.
74ALVC164245 v.6 20110616 Product data sheet - 74ALVC164245 v.5
74ALVC164245 v.5 20100413 Product data sheet - 74ALVC164245 v.4
74ALVC164245 v.4 20081111 Product data sheet - 74ALVC164245 v.3
74ALVC164245 v.3 20040914 Product data sheet - 74ALVC164245 v.2
74ALVC164245 v.2 20040601 Product data sheet - 74ALVC164245 v.1
74ALVC164245 v.1 19980826 Product specification - -
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 18 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full dat a
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environment al
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, paten ts or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74ALVC164245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 15 March 2012 19 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specificatio ns, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product cl aims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 March 2012
Document identifier: 74ALVC164245
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Functional description . . . . . . . . . . . . . . . . . . . 6
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 7
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 11
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
15 Legal information . . . . . . . . . . . . . . . . . . . . . . . 18
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Contact information. . . . . . . . . . . . . . . . . . . . . 19
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
