FPD1050 0.75W POWER PHEMT * * FEATURES 28.5 dBm Linear Output Power at 12 GHz 11 dB Power Gain at 12 GHz 14 dB Maximum Stable Gain at 12 GHz 41 dBm Output IP3 45% Power-Added Efficiency SOURCE BOND PAD (2x) DRAIN BOND PAD (2X) GATE BOND PAD (1X) DIE SIZE: 470 x 440 m DIE THICKNESS: 100 m BONDING PADS: >85 x 60 m DESCRIPTION AND APPLICATIONS The FPD1050 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT), featuring a 0.25 m by 1050 m Schottky barrier gate, defined by high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes parasitics to optimize performance. The epitaxial structure and processing have been optimized for reliable high-power applications. The FPD750 also features Si3N4 passivation and is also available in a low cost plastic SOT89 plastic package. Typical applications include commercial and other narrowband and broadband high-performance amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters. * ELECTRICAL SPECIFICATIONS AT 22C Parameter Symbol Test Conditions Min Typ Max Units RF SPECIFICATIONS MEASURED AT f = 12 GHz USING CW SIGNAL Power at 1dB Gain Compression P1dB VDS = 8 V; IDS = 50% IDSS Maximum Stable Gain (S21/S12) MSG VDS = 8 V; IDS = 50% IDSS Power Gain at P1dB G1dB VDS = 8 V; IDS = 50% IDSS Power-Added Efficiency PAE VDS = 8 V; IDS = 50% IDSS; POUT = P1dB Output Third-Order Intercept Point IP3 VDS = 10V; IDS = 50% IDSS (from 15 to 5 dB below P1dB) 27.5 28.5 dBm 14.0 dB 11.0 dB 45 % Matched for optimal power 39 dBm Tuned for best IP3 41 10.0 Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS +1 V 520 mA Transconductance GM VDS = 1.3 V; VGS = 0 V 280 mS Gate-Source Leakage Current IGSO VGS = -5 V 15 A Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 1 mA 1.0 V Gate-Source Breakdown Voltage |VBDGS| IGS = 1 mA 16 18 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 1 mA 16 18 V Thermal Resistivity (see Notes) JC VDS > 6V 45 C/W Phone: +1 408 850-5790 Fax: +1 408 850-5766 http:// www.filcs.com 250 315 375 mA Revised: 8/05/04 Email: sales@filcsi.com FPD1050 0.75W POWER PHEMT * ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Test Conditions Drain-Source Voltage VDS Gate-Source Voltage Max Units -3V < VGS < +0V 10 V VGS 0V < VDS < +8V -3 V Drain-Source Current IDS For VDS > 2V IDSS mA Gate Current IG Forward or reverse current 10 mA RF Input Power PIN Under any acceptable bias state 175 mW Channel Operating Temperature TCH Under any acceptable bias state 175 C Storage Temperature TSTG Non-Operating Storage 150 C Total Power Dissipation PTOT See De-Rating Note below 3.4 W Gain Compression Comp. Under any bias conditions 5 dB 2 or more Max. Limits 80 % Simultaneous Combination of Limits** *TAmbient = 22C unless otherwise noted Min -40 **Users should avoid exceeding 80% of 2 or more Limits simultaneously Notes: * Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device. * Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib. * Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Absolute Maximum Power Dissipation to be de-rated as follows above 22C: PTOT= 3.4W - (0.022W/C) x THS where THS = heatsink or ambient temperature above 22C Example: For a 85C heatsink temperature: PTOT = 3.4W - (0.022 x (85 - 22)) = 2.01W * HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. * ASSEMBLY INSTRUCTIONS The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280-290C; maximum time at temperature is one minute. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260C. * APPLICATIONS NOTES & DESIGN DATA Complete design data, including S-parameters, noise data, and large-signal models are available on the Filtronic web site. All information and specifications are subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766 http:// www.filcs.com Revised: 8/05/04 Email: sales@filcsi.com