IA6805E2PDW40IR0 - Innovasic Semiconductor

IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

IA6805E2

Microprocessor Unit

Data Sheet

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

FEATURES

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•

• Form, Fit, and Function Compatible with the Harris© CDP6805E2CE and

Motorola© MC146805E2

Internal 8-bit Timer with 7-Bit

Programmable Prescaler

On-chip Clock

Memory Mapped I/O

Versatile Interrupt Handling

True Bit Manipulation

Bit Test and Branch Instruction

Vectored Interrupts

Power-saving STOP and WAIT Modes

Fully Static Operation

112 Bytes of RAM

Packaging options available: 40 Pin Plastic DIP or, 44 Pin Plastic

Leaded Chip Carrier, Standard or RoHS packages available

The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. Innovasic produces replacement

ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology

produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the

original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology

advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features"

are duplicated. This data sheet documents all necessary engineering information about the IA6805E2

including functional and I/O descriptions, electrical characteristics, and applicable timing.

Package Pinout

A12

NC

(6)AS

(1)RESET_N

(2)

IRQ_N (3)

LI (4)DS

(5)RW_N

(7)PA7

(8)

(9)PA5

(10)

(11)

(12)PA2

(13)PA1

(14)

40 Pin DIP

IA6805E2

PB4

PB5

PB6

PB7

(20)VSS

(15)

A12

(16)

A11

(17)

A10

(18)A9

(19)A8

(21)

(22)

(23)

(24)

B6

B7

(40)

(39)

(38)

(37)

(36)

(35)

(34)

(33)

(32)

(31)

(30)

(29)

(28)

(27)

(26)

(25)

PA0

B4

B5

B2

B3

B0

B1

PB2

PB3

PB0

PB1

OSC2

TIMER

VDD

OSC1

PA6

PA4

PA3

RW_N

NC

B2

44 Pin LCC

IA6805E2

(12)PA3

(7)AS

(8)PA7

(9)

PA6

(10)PA5

(11)PA4

(13)PA2

(14)PA1

(15)PA0

(16)NC

(17)NC

PB1

PB7

PB6

PB5

PB3

PB2

A10

A11

(6)

(5)

(4)

(3)

(2)

(1)

(44)

(43)

(42) OSC2

(41) TIMER

(40) PB0

(34)

(39)

(38)

(37)

(36)

(35)

(33)

(32)

(31)

(30)

(29)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26)

(27)

(28)

VDD

OSC1

IRQ_N

RESET_N

DS

LI

A8

A9

B7

VSS

B5

B6

B4

B3

B1

B0

PB4

IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Description

The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a

CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The

following paragraphs will further describe this system block diagram and design in more detail.

PROGRAM

COUNTER

LOW

112x8

RAM

ADDRESS

DRIVE

MUX

BUS

DRIVE

CPU

PORT

A

REG

OSCILLATOR

DATA

DIR

REG

PORT

B

REG

DATA

DIR

REG

CPU

CONTROL

ALU

BUS

CONTROL

STACK

POINTER

CONDITION

CODE

REGISTER

INDEX

REGISTER

ACCUMULATOR

PROGRAM

COUNTER

HIGH

TIMER CONTROL

PRESCALER TIMER/

COUNTER

PA0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PB0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PA0

OSC1 OSC2

TIMER RESET_N

LI

IRQ_N

B0

B7

B6

B5

B4

B3

B2

B1

A8

A12

A11

A10

A9

RW_N

DS

AS

8A

5

6

5

8

X

CC

SP

PCH

PCL

PORT

A

I/O

LINES

PORT

B

I/O

LINES

MULTIPLEXED

ADDRESS

DATA

BUS

ADDRESS

BUS

ADDRESS STROBE

DATA STROBE

READ/WRITE

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Figure 1. System Block Diagram

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

I/O Signal Description

The table below describes the I/O characteristics for each signal on the IC. The signal names

correspond to the signal names on the pinout diagrams provided.

S IGNAL N A ME I/O DESCRIPTION

VDD and VS S

(Power and Ground) N/A Source: These two pins provide power to the chip. VDD provides +5 volts (±0.5)

power and VSS is ground.

RESET_n

(Reset) ITTL: Input pin that can be used to reset the MPU's internal state by pulling the reset_n

pin low.

IRQ_ n

(Interrupt Request) ITTL: Input pin that is level and edge sensitive. Can be used to request an interrupt

sequence.

L I

(Load Instruction) O

TTL with slew rate control: Output pin used to indicate that a next opcode fetch is in

progress. Used only for certain debugging and test systems. Not connected in

normal operation. Overlaps Data Strobe (DS) signal. This output is capable of driving

one standard TT L load and 50pF.

DS

(D a ta S tro b e) O

TTLwithslewratecontrol:Output pin used to transfer data to or from a peripheral

or memory. DS occurs anytime the MPU does a data read or write and during data

transfer to or from internal memory. DS is available at fOSC ¸5 when the MPU is not in

the WAIT or STOP mode. This output is capable of driving one standard TTL load and

130pF.

RW_n

(Read/Write) O

TTL with slew rate control: Output pin used to indicate the direction of data transfer

from internal memory, I/O registers, and external peripheral devices and memories.

Indicates to a selected peripheral whether the MPU is to read (RW_n high) or write

(RW_n low) data on the next data strobe. This output is capable of driving one

standard TTL load and 130pF.

A S

(Ad dress S trobe) O

TTLwithslewratecontrol: Output strobe used to indicate the presence of an

address on the 8-bit multiplexed bus. The AS line is used to demultiplex the eight

least significant address bits from the data bus. AS is available at fOSC ¸5whenthe

MPU is not in the WAIT or STOP modes. This output is capable of driving one

standard T TL load and 130pF.

PA0-PA7/PB0-PB7

(Input/Output Lines) I/O

TTLwithslewratecontrol: These 16 lines constitute Input/Output ports A and B.

Each line is individually programmed to be either an input or output under software

controlof the Data Direction Register (DDR) as shown below in Table 1 and Figure 2.

The port I/O is programmed by writing the corresponding bit in the DDR to a "1" for

output and a "0" for input. In the output mode the bits are latched and appear on the

corresponding output pins. All the DDR's are initialized to a "0" on reset. The output

port registers are not initialized on reset. Each output is capable of driving one

standard T TL load and 50pF.

A 8 -A 12

(High O rder Address

Lines) OTTLwithslewratecontrol: These five outputs constitute the higher order non-

multiplexed address lines. Each output is capable of driving one standard TTL load

and 130pF.

B0- B 7

(Ad dress/D ata B us) I/O

TTLwithslewratecontrol: These bi-directional lines constitute the lower order

addresses and data. These lines are multiplexed with address present at address

strobe time and data present at data strobe time. When in the data mode, these lines

are bi-directional, transferring data to and from memory and peripheral devices as

indicated by the RW_n pin. As outputs, these lines are capable of driving one

standard T TL load and 130

p

F.

Timer ITTL: Input used to control the internal timer/counter circuitry.

OS C1 , OSC2

(S ystem C lock)

TTL Oscillator input/output: These pins provide control input for the on-chip clock

oscillator circuits. Either a crystal or external clock is connected to these pins to

provide a system clock. The crystal connection is shown in Figure 3.TheOSC1to

bus transitions for system designs using oscillators slower than 5MHz is shown in

Figure 4.

Crystal

The circuit shown in Figure 3 is recommended when using a crystal. An external

CMOS oscillator is recommended when using crystals outside the specified ranges.

To minimize output distortion and start-up stabilization time, the crystal and

com ponents should be mounted as close to the input pins as possible.

External C lock When an external clock is used, it should be applied to the OSC1 input with the OSC2

input not connected, as shown in Figure 3.

I/O

Table 1

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

I/O Pin Functions

R/W-n DDR I/O Pin Functions

00

The I/O pin is in input mode. Data is

written into the output data latch.

01

Data is written into the output data latch and

output to the I/O pin.

10

The state of the I/O pin is read.

11

the I/O pin is in an output mode. The

output data latch is read.

I/O Port Circuitry and Register Configuration:

DATA DIRECTION

REGISTER

BIT

I/O

OUTPUT

LATCHED

OUTPUT

DATA BIT

INPUT

REG

BIT

INPUT

I/O

TO

AND

FROM

CPU

DDA7

(DDB7) DDA1

(DDB1)

DDA2

(DDB2)

DDA3

(DDB3)

DDA4

(DDB4)

DDA5

(DDB5)

DDA6

(DDB6) DDA0

(DDB0)

DATA DIRE CT ION

A(B)

REGISTER

PORT A(B)

REGISTER

74563012

PA7

(PB7) PA6

(PB6) PA5

(PB5) PA4

(PB4) PA3

(PB3) PA2

(PB2) PA1

(PB1) PA0

(PB0)

$0004 ( $0005)

$0000 ( $0001)

Figure 2. PA0-PA7/PB0-PB7 (Input/Output Lines)

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Crystal Parameters Representative Frequencies:

5.0 MHz 4.0 MHz 1.0 MHz

RS max 50

Ω

75

Ω

400

Ω

C0 8 pF 7 pF 5 pF

C1 0.02 pF 0.012 pF 0.008 pF

Q 50 k 40 k 30 k

COSC1 15-30 pF 15-30 pF 15-40 pF

COSC2 15-25 pF 15-25 pF 15-30 pF

Oscillator Connections:

LC1

39

C0

RS

OSC1OSC2

38

39

OSC2

38 OSC1

CRYSTAL CIRCUIT CRYSTAL OSCILLATOR CONNECTIONS

t

OL

t

OH

t

OLOL

OSC1 PIN

ia6805E2

10 M

Ω

C

OSC2 OSC1

OSC1

COSC2

38 39

OSC1

IA6805E2

OSC2 38

39

NC

Figure 3. OSC1, OSC2 (System Clock)

OSC1 to Bus Transitions Timing Waveforms:

OSC1

AS

DS

RW_n

A[12:8]

B[7:0]

MPU READ

B[7:0]

MPU W RITE

*READ DATA "LATCHED" ON DS FALL

MUX ADDR

MPU

READ

DATA*

MUX ADDR MPU WRIT E DATA

Figure 4. OSC1, OSC2 (System Clock)

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Functional Description

Memory:

The MPU is capable of addressing 8192 bytes of memory and I/O registers. The locations

are divided into internal memory space and external memory space as shown in Figure 5.

The first 128 bytes of memory contain internal port I/O locations, timer locations, and 112

bytes of RAM. The MPU can read from or write to any of these locations. During program

reads from on chip locations, the MPU accepts data only from the addressed on chip

location. Any read data appearing on the input bus is ignored. The shared stack area is used

during interrupts or subroutine calls. A maximum of 64 bytes of RAM is available for stack

usage. The stack pointer is set to $7f at power up. The unused bytes of the stack can be used

for data storage or temporary work locations, but care must be taken to prevent it from

being overwritten due to stacking from an interrupt or subroutine call.

RAM

(112 BYTES)

I/O PORTS

TIMER RAM

EXTERNAL MEMORY

SPACE (8064 BYTES)

TIMER INTERRUPT FROM WAIT STATE ONLY

TIMER INTERRUPT

EXTERNAL INTERRUPT

SWI

RESET

PORT A DATA REGISTER

PORT B DATA REGISTER

EXTERNAL MEMORY SPACE

PORT A DATA DIRECTION REGISTER

PORT B DATA DIRECTION REGISTER

EXTERNAL MEMORY SPACE

TIMER DATA REGISTER

TIMER CONTROL REGISTER

EXTERNAL MEMORY SPACE

$1FF6 - $1FF7

$1FF8 - $1FF9

$1FFA - $1FFB

$1FFC - $1FFD

$1FFE - $1FFF

$0000

$007F

$0080

$00FF

$0100

63

64

127

0

127

128

255

256

8191

INTERRUPT

VECTORS

ACCESS VIA

PAGE 0

DIRECT

ADDRESS

STACK

(64 BYTES MAX)

0

1

2

3

4

5

6

7

8

9

10

15

16

Figure 5. Memory Map

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Registers:

The following paragraphs describe the registers contained in the MPU. Figure 6 shows the

programming model and Figure 7 shows the interrupt stacking order.

A

X

SP10 0 0 0 0 0

H I N Z C

70

CC CONDITION CODE REGISTER

CARRY/BORROW

HALF CARRY

INTE RRUPT MASK

NEGATIVE

ZERO

STACK POINTER

PROGRAM COUNTER

INDEX REGIS TER

ACCUMULATOR

70

12 078

PCH PCL

12 6 0

40

Fi

g

ure 6. Pro

g

rammin

g

Model

NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,

followed by PCH, etc. Pulling from the stack is in the reverse order.

CONDITION CODE

REGISTER

ACCUMULATOR

INDEX REGISTER

111 I

N

T

E

R

U

P

T

DECREASING MEMORY

ADDRESSES

STACK

PCH000

PCL

R

E

T

U

R

N

INCREASING MEMORY

ADDRESSES

UNSTACK

Figure 7. Interrupt Stacking Order

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A(Accumulator):

The accumulator is an 8-bit register used to hold operands and results of arithmetic

calculations or data manipulations.

X(Index Register):

The index register is an 8-bit register used during the indexed addressing mode. It contains

an 8-bit value used to create an effective address. The index register may also be used as a

temporary storage area when not performing addressing operations.

PC(Program Counter):

The program counter is a 13-bit register that holds the address of the next instruction to be

performed by the MPU.

SP(Stack Pointer):

The stack pointer is a 13-bit register that holds the address of the next free location on the

stack. During an MPU reset or the reset stack pointer (RSP) instruction, the stack pointer is

set to location $007f. The seven most significant bits of the stack pointer are permanently

set to 0000001. They are appended to the six least significant register bits to produce an

address range down to location $0040. The stack pointer gets decremented as data is pushed

onto the stack and incremented as data is removed from the stack. The stack area of RAM is

used to store the return address on subroutine calls and the machine state during interrupts.

The maximum number of locations for the stack pointer is 64 bytes. If the stack goes

beyond this limit the stack pointer wraps around and points to its upper limit thereby losing

the previously stored information. Subroutine calls use 2 bytes of RAM on the stack and

interrupts use 5 bytes.

CC(Condition code Register):

The condition code register is a 5-bit register that indicates the results of the instruction just

executed. The bit is set if it is high. A program can individually test these bits and specific

actions can be taken as a result of their states. Following is an explanation of each bit.

C(Carry Bit):

The carry bit indicates that a carry or borrow out of the Arithmetic Logical Unit (ALU)

occurred during the last arithmetic instruction. This bit is also modified during bit test, shift,

rotate, and branch types of instructions.

Z(Zero Bit):

The zero bit indicates the result of the last arithmetic, logical, or data manipulation was zero.

N(Negative Bit):

The negative bit indicates the result to the last arithmetic, logical, or data manipulation was

negative (bit 7 in the result is high).

IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

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I(Interrupt Mask Bit)

The interrupt mask bit indicates that both the external interrupt and the timer interrupt are

disabled (masked). If an interrupt occurs while this bit is set, the interrupt is latched and is

processed as soon as the interrupt bit is cleared.

H(Half Carry Bit)

The half carry bit indicates that a carry occurred between bits 3 and 4 of the ALU during an

ADD or ADC operation.

Resets:

The MPU can be reset by initial power up or by the external reset pin (reset_n).

POR(Power On Reset)

Power on reset occurs on initial power up. It is strictly for power initialization conditions

and should not be used to detect drops in the power supply voltage. There is a 1920 tCYC

time out delay from the time the oscillator is detected. If the reset_n pin is still low at the

end of the delay, the MPU will remain in the reset state until the external pin goes high.

Reset_n

The reset_n pin is used to reset the MPU. The reset pin must stay low for a minimum of tcyc

to guarantee a reset. The reset_n pin is provided with a Schmitt Trigger to improve noise

immunity capability.

Interrupts:

The MPU can be interrupted with the external interrupt pin (irq_n), the internal timer

interrupt request, or the software interrupt instruction. When any of these interrupts occur,

normal processing is suspended at the end of the current instruction execution. The

processor registers are saved on the stack (stacking order shown in Figure 7) and the

interrupt mask (I) is set to prevent additional interrupts. Normal processing resumes after

the RTI instruction causes the register contents to be recovered from the stack. When the

current instruction is completed, the processor checks all pending hardware interrupts and if

unmasked (I bit clear) proceeds with interrupt processing. Otherwise, the next instruction is

fetched and executed. Masked interrupts are latched for later interrupt service. External

interrupts hold higher priority than timer interrupts. At the end of an instruction execution,

if both an external interrupt and timer interrupt are pending, the external interrupt is

serviced first. The SWI gets executed with the same priority as any other instruction if the

hardware interrupts are masked (I bit set). Figure 8 shows the Reset and Interrupt processing

flowchart.

IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

I_CC <= 1

SP <= $007F

DDRs <= 0

CLR IRQ_N LOGIC

TIMER <= $FF

PRESCALE R <= $7F

TCR <= $7f

FETCH

INSTRUCTION

PUT 1FFE,1FFF ON

ADDRESS BUS

RESET

LOAD PC

FROM

1FFE/1FFF

EXECUTE ALL

INSTRUCTION

CYCLES

CLEAR

IRQ_N

REQUEST

LATCH

LOAD PC FROM:

SWI: 1FFC/1FFD

IRQ_N: 1FFA/1FFB

TIMER: 1FF8/1FF9

TIMER WAIT:1FF6/

1FF7

I <= 1

STACK

PC, X, A, CC

PC+1=>PC

IN

RESET

?

I BIT

?

IRQ_N

EDGE

?

IS FETCHED

INSTRUCTION

AN SWI?

TCR6=0

AND

TCR7=1?

RESET_N

PIN = LOW RESET_N

PIN = LOW SWI

TIMER

IRQ_NY

Y

N

SET

CLEAR

Fi

g

ure 8. Reset and Interru

p

t Processin

g

Flowchart

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

External Interrupt:

If the external interrupt pin irq_n is “low” and the interrupt mask bit of the condition code

register is cleared, the external interrupt occurs. When the interrupt is recognized, the

current state of the machine is pushed onto the stack and the condition code register I-bit

gets set masking further interrupts until the present one is serviced. The program counter is

then loaded with the contents of the interrupt vector, which contains the location of the

interrupt service routine. The contents of $1FFA and $1FFB specify the address for this

service routine. A functional diagram of the external interrupt is shown in Figure 9 and a

mode diagram of the external interrupt is shown in Figure 10. The timing diagram shows

two different treatments of the interrupt line (irq_n) to the processor. The first shows

several interrupt lines “wire ORed” to form the interrupts at the processor. If the interrupt

line (irq_n) remains low after servicing an interrupt, the next interrupt is recognized. The

second shows single pulses on the interrupt line spaced far enough apart to be serviced. The

minimum time between pulses is a function of the length of the interrupt service. After a

pulse occurs, the next pulse should not occur until an RTI has occurred. The time between

pulses (tILIL) is obtained by adding 20 instruction cycles to the total number of cycles it takes

to complete the service routine including the RTI instruction.

D

C

Q

R

VDD

INTERRUPT PIN

POWER-ON RESET

EXTERNAL INTERRUPT

BEING SERVICED

EXTERNAL RESET

I BIT (CCR)

EXTERNAL

INTERUPT

REQUEST

Fi

g

ure 9. Interru

p

t Functional Dia

g

ram

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Microprocessor Unit

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Figure 10. Interrupt Mode Diagram

Timer Interrupt:

If the timer mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are

cleared, each time the timer decrements to zero ($01 to $00 transition) an interrupt request is

generated. When the interrupt is recognized, the current state of the machine is pushed onto

the stack and the condition code register I-bit gets set masking further interrupts until the

present one is serviced. The program counter is then loaded with the contents of the timer

interrupt vector, which contains the location of the timer interrupt service routine. The

contents of $1FF8 and $1FF9 specify the address for this service routine. If the MPU is in

the wait mode and a timer interrupt occurs, then the contents of $1FF6 and $1FF7 specify

the service routine. When the timer interrupt service routine is complete, the software

executes an RTI instruction to restore the machine state and starts executing the interrupt

program.

Software Interrupt:

Software interrupt is an executable instruction regardless of the state of the interrupt mask

bit (I) in the condition code register. SWI is similar to hardware interrupts. It executes after

the other interrupts if the interrupt mask bit is zero. The contents of $1FFC and $1FFD

specify the address for this service routine.

Low Power Modes:

The low power modes consist of the stop instruction and the wait instruction. The

following paragraphs explain these modes of operation.

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Stop Modes:

The stop instruction places the MPU in low power consumption mode. The stop instruction

disables clocking of most internal registers. Timer control register bits 6 and 7 (TCR6 and

TCR7) are altered to remove any pending timer interrupt requests and to disable any further

timer interrupts. The DS and AS output lines go “low” and the RW_n line goes “high”. The

multiplexed address/data bus goes to the data input state. The high order address lines

remain at the address of the next instruction. External interrupts are enabled by clearing the

I bit in the condition code register. All other registers, memory, and I/O remain unaltered.

Only an external interrupt or reset will bring the MPU out of the stop mode. Figure 11

shows a flowchart of the stop function.

TCR BIT 7 <= 0

TCR BIT 6 <= 1

CLEAR I BIT

FETCH EXTERNAL

INTERRUPT

OR RESET VECTOR

STOP

EXTERNAL

INTERRUPT?

RESET?

Y

N

Y

Figure 11. STOP Function Flowchart

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Wait Mode:

The wait instruction places the MPU in low power consumption mode. The wait instruction

disables clocking of most internal registers. The DS and AS output lines go “low” and the

RW_n line goes “high”. The multiplexed address/data bus goes to the data input state. The

high order address lines remain at the address of the next instruction. External interrupts are

enabled by clearing the I bit in the condition code register. All other registers, memory, and

I/O remain unaltered. Only an external interrupt, timer interrupt, or reset will bring the

MPU out of the wait mode. The timer may be enabled to allow a periodic exit from the wait

mode. If an external and a timer interrupt occur at the same time, the external interrupt is

serviced first. Then, if the timer interrupt request is not cleared in the external interrupt

routine, the normal timer interrupt (not the timer wait interrupt) is serviced since the MPU is

no longer in the wait mode. Figure 12 shows a flowchart of the wait function.

OSCILLATOR

ACTIVE,

CLEAR I BIT,

TIMER CLOCK

ACTIVE,

FET CH EXTERNAL

INTERRUPT, RESET,

OR TIMER

INTERRUPT (FROM

WAIT MODE ONLY)

WAIT

EXTERNAL

INTERRUPT?

RESET?

Y

N

YTIMER

INTERRUPT?

(TCR BIT7

= 1)

TCR

BIT 6 = 0? N

Y

N

Y

Figure 12. WAIT Function Flowchart

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Timer:

The MPU contains a single 8-bit software programmable counter driven by a 7-bit software

programmable prescaler. The counter may be loaded under program control and decrements

to zero. When the counter decrements to zero, the timer interrupt request bit in the timer

control register (TCR7) is set. Figure 13 shows a block diagram of the timer. If the timer

mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared, an

interrupt request is generated. After completion of the current instruction, the current state

of the machine is pushed onto the stack. The timer interrupt vector address is then fetched

from locations $1FF8 and $1FF9 and the interrupt routine is executed, unless the MPU was

in the WAIT mode in which case the interrupt vector address in locations $1FF6 and $1FF7

is fetched. Power-On-Reset causes the counter to set to $FF.

NOTE: 1. Prescaler and counter are clocked on the falling edge of the internal

clock (AS) or external input.

2. Counter is written to during Data Strobe (DS) and counts down continuously.

TIMER

(PIN 37)

TCR4 TCR5 TCR3 TCR2 TCR1 TCR0

2 - TO - 1

MUX

PRESCALER

(7 BITS) COUNTER

(8 BITS)

INTERRUPT

CONTROL

WRITEREAD

INT

CLK

EXT

CLK

INTERRUPT

INTERNAL_n / EXTERNAL

INTERNAL

CLOCK

ENABLE /

DISABLE_n

TIMER_n

SETTING TCR3 CLEARS

PRESCALER TO ÷ 1

SOFTWARE FUNCTIONS

Figure 13. Timer Block Diagram

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Customer Support:

Page 17 of 33 1-888-824-4184

©

The counter continues to count past zero, falling from $00 to $FF, and continues. The

processor may read the counter at any time without disturbing the count by reading the

timer data register (TDR). This allows a program to determine the length of time since a

timer interrupt has occurred. The timer interrupt request bit remains set until cleared by

software. The interrupt is lost if this happens before the timer interrupt is serviced.

The prescaler is a 7-bit divider used to extend the maximum length of the timer. TCR bits

0-2 are programmed to choose the appropriate prescaler output, which is used as the count

input. The prescaler is cleared by writing a “1” into TCR bit 3, which avoids truncation

errors. The processor cannot write to or read from the prescaler.

Timer Input Mode 1:

When TCR4 = 0 and TCR5 = 0, the input to the timer is from an internal clock and the

timer input is disabled. The internal clock mode can be used for periodic interrupt

generation as well as a reference for frequency and event measurement. The internal clock is

the instruction cycle clock and is coincident with Address Strobe (AS) except during the wait

instruction where it goes low. During the wait instruction the internal clock to the timer

continues to run at its normal rate.

Timer Input Mode 2:

When TCR4 = 1 and TCR5 = 0, the internal clock and timer input signal are ANDed to

form the timer input. This mode can be used to measure external pulse widths. The external

pulse turns on the internal clock for the duration of the pulse. The count accuracy in this

mode is ±1 clock. Accuracy improves with longer input pulse widths.

Timer Input Mode 3:

When TCR4 = 0 and TCR5 = 1, all inputs to the timer are disabled.

Timer Input Mode 4:

When TCR4 = 1 and TCR5 = 1, the internal clock input to the timer is disabled and the

timer input then comes from the external TIMER pin. The external clock can be used to

count external events as well as to provide an external frequency for generating periodic

interrupts.

IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

TCR (Timer Control Register ($0009)):

An 8-bit register that controls functions such as configuring operation mode, setting ratio of

the prescaler, and generating timer interrupt request signals. All bits except bit 3 are

read/write. Bits TCR5 - TCR0 are unaffected by reset_n.

76543210

TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0

Reset:

01000000

TCR7 – Timer Interrupt Request

Used to indicate the timer interrupt when it is logic one.

1 – Set when the counter decrements to zero or under program control.

0 – Cleared on external reset, POR, STOP instruction, or program control.

TCR6 – Timer Interrupt Mask

Used to inhibit the timer interrupt.

1 – Interrupt inhibited. Set on external reset, POR, STOP instruction, or program

control.

0 – Interrupt enabled.

TCR5 – External or Internal

Selects input clock source. Unaffected by reset.

1 – External clock selected.

0 – Internal clock selected (AS) (fOSC/5).

TCR4 – Timer External Enable

Used to enable external timer pin or to enable the internal clock. Unaffected by reset.

1 – Enables external timer pin.

0 – Disables external timer pin.

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

TCR3 – Prescaler Clear

Write only bit. Writing a “1” to this bit resets the prescaler to zero. A read of this location

always indicates a zero. Unaffected by reset.

TCR2, TCR1, TCR0 – Prescaler select bits

Decoded to select one of eight outputs of the prescaler. Unaffected by reset.

TRC2 TRC1 TRC0 RESET

000

÷

1

001

÷

2

010

÷

4

011

÷

8

100

÷

16

101

÷

32

110

÷

64

111

÷

128

Prescaler

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Instruction Set Description

The MPU has 61 basic instructions divided into 5 types. The 5 types are Register/memory, read-

modify-write, branch, bit manipulation, and control.

Register/Memory Instructions:

Most of the following instructions use two operands. One is either the accumulator or the

index register and the other is obtained from memory. The jump unconditional (JMP) and

jump to subroutine (JSR) instructions have no register operand.

Function Mnemonic

Load A from memory LDA

Load X from memory LDX

Store A in memory STA

Store X in memory STX

Add memory to A ADD

Add memory and carry to A ADC

Subtract memory SUB

Subtract memory from A with Borrow SBC

AND memory to A AND

OR memory with A ORA

Exclusive OR memory with A EOR

Arithmetic compare A with memory CMP

Arithmetic compare X with memory CPX

Bit test memory with A (logical compare) BIT

Jump Unconditional JMP

Jump to subroutine JSR

Read-Modify-Write Instructions:

These instructions read a memory or register location, modify or test its contents and then

write the modified value back to memory or the register.

Function Mnemonic

Increment INC

Decrement DEC

Clear CLR

Complement COM

Negate (2's complement) NEG

Rotate Left Thru Carry ROL

Rotate Right Thru Carry ROR

Logical shift left LSL

Logical shift right LSR

Arithmetic shift right ASR

Test for negative or zero TST

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Bit Manipulation Instructions:

The MPU is capable of altering any bits residing in the first 256 bytes of memory. An

additional feature allows the software to test and branch on the state of any bit within these

locations. For test and branch instructions the value of the bit tested is placed in the carry bit

of the condition code register.

Function Mnemonic

n = 0…7

Branch if bit n set BRSET n

Branch if bit n clear BRCLR n

Set bit n BSET n

Clear bit n BCLR n

Branch Instructions:

If a specific condition is met, the instruction branches. If not, no operation is performed.

Function Mnemonic

Branch always BRA

Branch never BRN

Branch if higher BHI

Branch if lower or same BLS

Branch if carry clear BCC

Branch if higher or same BHS

Branch if carry set BCS

Branch if lower BLO

Branch if not equal BNE

Branch if equal BEQ

Branch if half carry clear BHCC

Branch if half carry set BHCS

Branch if plus BPL

Branch if minus BMI

Branch if interrupt mask bit clear BMC

Branch if interrupt mask bit set BMS

Branch if interrupt line low BIL

Branch if interrupt line high BIH

Branch to subroutine BSR

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Control Instructions:

These are used to control processor operation during program execution. They are register

reference instructions.

Function Mnemonic

Transfer A to X TAX

Transfer X to A TXA

Set carry bit SEC

Clear carry bit CLC

Set interrupt mask bit SEI

Clear interrupt mask bit CLI

Software interrupt SWI

Return from subroutine RTS

Return from interrupt RTI

Reset stack pointer RSP

No-Operation NOP

Stop STOP

Wait WAIT

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Opcode Map Summary:

The following table is an opcode map for the instructions used on the MPU. The legend

following the table shows how to use the table.

Hi Hi

Low Low

5 5 3533659 234543

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 3 6 234543

3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

553 234543

3BTB2 BSC2REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 35336510 234543

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 353365 234543

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

553 234543

3BTB2 BSC2REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 353365 234543

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 353365 2 45654

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 353365 2234543

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 353365 2234543

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 353365 2234543

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

553 2234543

3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 353365 2 23432

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 343364 2656765

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 3 2 234543

3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

5 5 35336522 45654

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

IX1IX2 IX

Branch Read-Modify-Write Control Register/Memory

INH IMM DIR EXT

F 1111

BTB BSC REL DIR INH INH IX1 IX INH

ROR

LSR

8

1000

7

0111

CMP CMP

AND

LDA

CMP

SBC

CPX

AND

CMP CMP CMP

SBC SBC SBC SBC

E

1110

F

1111

C

1100

D

11011010

AB

1011

9

1001

Bit Manipulation

RTS

5

0101

6

0110

0

0000

BRSET0 NEGA

2

0010

3

0011

4

0100

0

0000 BSET0 BRA NEG NEGX NEG NEG RTI SUB SUB SUB SUB SUB SUB

BRCLR0 BCLR0 BRN

0 0000

1 0001

2 0010

BRSET1 BSET1 BHI SBC

SWI 3 0011

CPX CPX CPX CPX

4 0100

5 0101

COMA COMX COM COM CPX

BIT BIT

EO

R

BRCLR1 BCLR1 BLS COM

BIT

LDA

LSRA AND AND ANDANDLSRBRSET2 BSET2 BCC LSR LSRX

BITBRCLR2 BCLR2 BCS

A 1010

9 1001

7 0111

6 0110

8 1000

BIT BIT

EO

R

EO

R

RORA RORX ROR LDABRSET3 BSET3 BNE ROR

D 1101

LDA LDA LDA

STA STA STA

EOR

C 1100

B 1011

E 1110

BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR

T

AX STA STA

BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL CLC EOR EO

R

BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL SEC ADC ADC ADC ADC ADC ADC

BRSET5 BSET5 BPL DEC DECA DECX DEC DEC CLI ORA ORA ORA ORA ORA ORA

BRCLR5 BCLR5 BMI SEI ADD ADD ADD ADD ADD ADD

BRSET6 BSET6 BMC INC INCA INCX INC INC RSP

J

MP

J

MP

J

MP

J

MP

J

MP

BRCLR6 BCLR6 BMS

T

ST

T

STA

T

STX

T

ST

T

ST NOP BSR

J

SR

J

SR

J

SR

J

SR

J

SR

BRSET7 BSET7 BIL STOP LDX LDX LDX LDX LDX LDX

BRCLR7 BCLR7 BIH CL

R

CLRA CLRX CL

R

CLR WAIT

T

XA STX STX STX STX STX

6

0110

7

0111

8

1000

1

0001

2

0010

3

0011

4

0100

D

1101

E

1110

F

1111

1

0001

9

1001

A

1010

B

1011

C

1100

5

0101

Abbreviations for Address

Modes:

Customer Support:

INH Inherent

A Accumulator

X Index Register

IMM Immediate

DIR Direct

EXT Extended

REL Relative

BSC Bit set/clear

SUB 3

IX

1

F

1111

0

0000

Opcode in Hexadecimal

Opcode in Binary

Address Mode

Mnemonic

Bytes

# of Cycles

BTB Bit test and branch

IX Indexed, no offset

IX1 Indexed, 1 byte offset

IX2 Indexed, 2 byte offset

Legend:

Page 23 of 33 1-888-824-4184

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

AC/DC Parameters

Absolute maximum ratings:

Supply Voltage (VDD)........................….…...………….….………-0.3V to 6V

Input Pin Voltage (VIN)…………………………………...-0.3 to VDD+0.3V

Operating Temperature……………………………….……....-40°C to 85°C

Storage temperature Range (Tstg).................…........….…...…- 55°C to 150°C

ESD Protection (HBM)………………………………………………5000V

Note: The specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed

under these conditions. Operation at absolute maximum conditions for extended periods may adversely affect the long-term reliability

of the device.

DC Characteristics

(VDD=4.5 to 5.5 Vdc, VSS=0, TA=TL to TH), unless otherwise specified

Customer Support:

Page 24 of 33 1-888-824-4184

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A

Symbol Parameter Min Max Unit

VDD Supply Voltage 4.5 5.5 V

VOL -0.4V

VOH 3.5 - V

IOL -2m

IOH --2m

VIH High Level input Voltage 2 - V

VIL Low Level input Voltage - 0.8 V

IIH High Level input Current - 1 µA

IIL Low Level input Current - -1 µA

Vt- Schmitt Negative Threshold 1.1 - V

Vt+ Schmitt Positive Threshold - 1.87 V

Frequency of Operation

fOSC Crystal - 5 MHz

fOSC External Clock DC 5 MHz

DC CHARACTERISTICS

Output Current

Output Voltage, ILOAD ≤ 2mA

IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Customer Support:

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Control Timing

VSS=0V, TA=TL to TH

V = 5.0V ±10%

DD

fOSC = 5MHz

Parameters Sym Min Typ Max Unit

I/O Port Timing – Input Setup Time

(Figure 14)

tPVASL 196 - - ns

Input Hold Time (Figure 14) tASLPX 0 - - ns

Output Delay Time (Figure 14) tASLPV - - 0 ns

Interrupt Setup Time (Figure 15) TILASL 0.4 - - μs

Crystal Oscillator Startup Time

(Figure 16)

tOXOV - 5 100 ms

Wait Recovery Startup Time (Figure

17)

tIVASH - - 2

μs

Stop Recovery Startup Time

(Figure 18)

tILASH - - 2

μs

Required Interrupt Release (Figure 15) tDSLIH - - 1.0

μs

Timer Pulse Width (Figure 17) tTH, tTL 0.5 - - tCYC

Reset Pulse Width (Figure 16) tRL 1.05 - -

μs

Timer Period (Figure 17) tTLTL 1.0 - - tCYC

Interrupt Pulse Width Low (Figure10) tILIH 1.0 - - tCYC

Interrupt Pulse Period

(Figure 10)

tILIL * - - tCYC

Oscillator Cycle Period

(1/5 of tCYC) (Figure 3)

tOLOL 200 - - ns

OSC1 Pulse Width High (Figure 3) tOH 75 - - ns

OSC1 Pulse Width Low (Figure 3) tOL 75 - - ns

*The minimum period of tILIL should not be less than the number of tCYC cycles it takes to execute the

interrupt service routine plus 20 tCYC cycles.

IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Bus Timing

VSS=0V, TA=TL to TH (Figure 19)

Num

V = 5.0V ±10%

DD

f = 5MHz

OSC

1 TTL, 100pF Load

Unit

Parameters

Min Max

1 Cycle Time 1000 DC ns

2 Pulse Width, DS Low 587 - ns

3 Pulse Width, DS High 403 - ns

4 Clock Transition - 4 ns

8 RW_n 9 - ns

9 Non-Muxed Address Hold 97 - ns

11 RW_n Delay From DS Fall - 40 ns

16 Non-Muxed Address Delay From AS Rise - 11 ns

17 MPU Read Data Setup 18 - ns

18 Read Data Hold 0 ns

19 MPU Data Delay, Write - 0 ns

21 Write Data Hold 204 - ns

23 Muxed Address Delay From AS Rise - 26 ns

24 Muxed Address Valid to AS Fall 185 - ns

25 Muxed Address Hold 103 - ns

26 Delay DS Fall to AS Rise 190 - ns

27 Pulse Width, AS High 203 - ns

28 Delay, AS Fall to DS Rise 185 - ns

VLOW = 0.8V, VHIGH = VDD – 2.0V, VDD = 5.0V ±10%

TA = TL to TH, CL on Port = 50pF, fOSC = 5MHz

ADDRESS_STROBE

PORT_INPUT

PORT_OUTPUT

tPVASL tASLPX

tASLPV

*NOTE

*Note: The address strobe of the first cycle of the next instruction.

Fi

g

ure 14. I/O Port Timin

g

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

A

S

DS

A

DD_BUS_UNMUX[8:12]

IRQ_N__TCR7_N

MUX_ADD_DATA[0:7]

RW_N

1F (FF) 1F (FF)

SP PCL SP-1 PCH SP-2 XSP-3

A

SP-4 CC NEW PCH NEW PCL 80

n0 n1 n3n2 n4 n5 n6 n7 n8 n9

TILASL

TDSLIH

NEXT OP CODE ADDRESS

INT ROUTINE

STARTING ADDRESS

INT ROUTINE

LAST ADDRESS

FA (IRQ)

F8 (TIMER)FB (IRQ)

F9 (TIMER) 1ST OP

INT ROUTINE RTI

OP CODE

(NOTE)

NEXT OP CODE

Note: tDSLIH- the interrupting device must release the IRQ_N line within this time to prevent subsequent recognition

of the same interrupt.

Figure 15. IRQ_n and TCR7_N Interrupt Timing

Figure 16. Power-On-Reset and RESET_n Timing

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

INT_EXT_CLK

TCR7

A

S

DS

A

[12:8]

B[7:0]

RW_N

OP CODE ADDR

A

DDRESS + 1 1F (FF) 1F (FF)

8F SP PCL SP-1 PCH SP-2 XSP-3

A

SP-4 CC F6NEW PCHF7NEW PCL

tTH

tTL

tIVASH

n1 n2 n3 n4 n5 n6 n7n0

tTLTL

TIMER

COUNTER=$00

1ST OP CODE

INT ROUTINE

STARTING

A

DDRESS

OP CODE

A

DDRESS

A

DDR + 1

WAIT OP CODE

Figure 17. Timer Interrupt After WAIT Instruction Timing

INT_EXT_CLK

TCRB7

A

S

DS

A

[12:8]

B[7:0]

RW_N

OP CODE ADDR

A

DDRESS + 1 1F (FF) 1F (FF)

8E SP PCL SP-1 PCH SP-2 XSP-3

A

SP-4 CC F6NEW PCHF7NEW PCL

tTH

tTL

tIVASH

n1 n2 n3 n4 n5 n6 n7n0

tTLTL

TIMER

COUNTER=$00

1ST OP CODE

INT ROUTINE

STARTING

A

DDRESS

OP CODE

A

DDRESS

A

DDR + 1

STOP OP CODE

Fi

g

ure 18. Interru

p

t Recover

y

From STOP Instruction Timin

g

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

1

23

4 4

88

9 9

11 16

VALID

ADDR

VALID

ADDR

VALID WRITE

DATA

VALID READ

DATA

17

11

18 18

19 21

23 24 25

25

26

27

28AS

DS

RW_n

A[12:8]

B[7:0]

WRITE

B[7:0]

READ

444

4

26

23

21

23

Figure 19. Bus Timing

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Packaging Information

PDIP Packaging

LEAD 1

IDENTIFIER

1

LEAD CO UN T

DIRECTION

E1 E

TOP

eA

eB C

SIDE VIEW (WIDTH)

Lead Count

40 (in Inches)

Symbol MIN MAX

A-.200

A1 .015 -

B .015 .020

B1 .040 .060

C .008 .012

D 1.980 2.065

E .580 .610

E1 .520 .560

e .100 TYP

eA .580 -

eB - .686

L .100 MIN

D

L

A1

A

B

B1

e

SIDE VIEW (LENGTH)

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

PLCC Packaging

LEAD COUNT

44 (in Millimeters)

Symbol MIN MAX

A 4.20 4.57

A1 2.29 3.04

D1 16.51 16.66

D2 14.99 16.00

D3 12.70 BSC

E1 16.51 16.66

E2 14.99 16.00

E3 12.70 BS C

e1.27 BSC

D 17.40 17.67

E 17.40 17.65

.10

.51 MIN.

R 1.14 / .64

SEATING PLANE

A1

e

.81 / .66

A

.53 / .33

D2 / E2

SIDE VIEW

D

D1

E

E1

BOTTOM VIEW

D3

E3

PIN 1

IDENTIFIER & ZONE

1.22/1.07

2 PLCS

TOP VIEW

Customer Support:

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IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Customer Support:

Page 32 of 33 1-888-824-4184

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Ordering Information

The IA6805E2 is available in two package styles, both standard and RoHS compliant, listed in the table

below. Other packages and temperature grades may be available for additional cost and lead time.

Order Number Temperature Grade Package Type

IA6805E2-PDW40I-00 Industrial 40 Lead Plastic DIP, 600 mil wide

IA6805E2-PDW40I-R-00

(RoHS compliant)

Industrial 40 Lead Plastic DIP, 600 mil wide

IA6805E2-PLC44I-00 Industrial

44 Lead Plastic Leaded Chip Carrier

IA6805E2-PLC44I-R-00

(RoHS compliant)

Industrial 44 Lead Plastic Leaded Chip Carrier

Cross Reference to Original Manufacturers

Innovasic Part Number Motorola® P art Number Harris® Part Number

IA6805E2-PDW40I  MC146805E2CP  CDP6805E2CE

 MC146805E2P  CDP6805E2E

IA6805E2-PLC44I  MC146805E2CFN  CDP6805E2CQ

 MC146805E2FN  CDP6805E2Q

IA6805E2 29 August 2007

Microprocessor Unit

As of Production Version 00

Customer Support:

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Errata

Production Version 00

1.

Functional differences between IA6805E2 and Harris and Motorola Versions:

A. Stop mode on IA6805E2 will not halt oscillator. Recovery from stop will be quicker.

B. There is a functional difference between the IA6805E2 and the original device instruction

sets regarding instructions for BSET and BCLR. Analysis: The instructions, BSET and

BCLR (bit set and bit clear), are not supposed to affect the carry flag in the condition code

register but in the IA6805E2 they do. Any situations where the BSET or BCLR commands

are executed between a decision type instruction (branches) based on the carry flag and the

instruction that was to update the carry flag should be considered suspect. Workaround:

The workaround selected by the particular user is code dependent. Software will need to be

revised to address the instruction set issues noted above.

C. There is a functional difference between the IA6805E2 and the original device regarding the

external timer input. Analysis: The original device is edge sensitive on this input (negative

edge). The IA6805E has a synchronizing register on this input. If the stimulus to this input

is a negative pulse less than a clock cycle wide, it is possible that this event will be missed by

the timer circuit. Workaround: The workaround selected by the particular user is situation

dependent. The input pulse either needs to be a minimum of 1 clock cycle wide or the pulse

needs to be centered on the falling edge of the input clock.

2.

Observations:

A. Original data sheets for Motorola and Harris are inconsistent when describing timer input mode 2.

Original parts and Innovasic will AND together the timer input with the inverse of the internal clock

(AS).

B. Original Harris part would unpredictably “pre-increment” timer counter when writing to timer

registers. IA6805E2 will not.

C. Original Harris part displays incorrect address on external pins during intermediate cycles (not a

functional problem) of multi-cycle instructions when accessing memory at page boundaries.

IA6805E2 will not.

D. Execution of illegal op-codes on the IA6805E2 will force a system reset. On the original Harris

and Motorola parts, execution of illegal op-codes would produce unpredictable results.