For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX8743 is a dual pulse-width modulation (PWM)
controller configured for step-down (buck) topologies
that provides the high efficiency, excellent transient
response, and high DC output accuracy necessary for
stepping down high-voltage batteries to generate low-
voltage chipset and RAM power supplies in notebook
computers. The CS_ inputs can be used with low-side
sense resistors to provide accurate current limits or can
be connected to LX_, using low-side MOSFETs as cur-
rent-sense elements. High output impedance in shut-
down eliminates negative output voltages, saving the
cost of a Schottky diode at the output.
The on-demand PWM controllers are free running, con-
stant on-time with input feed-forward. This configuration
provides ultra-fast transient response, wide input-output
differential range, low supply current, and tight load-reg-
ulation characteristics. The MAX8743 is simple and easy
to compensate.
Single-stage buck conversion allows the MAX8743 to
directly step down high-voltage batteries for the highest
possible efficiency. Alternatively, two-stage conversion
(stepping down the 5V system supply instead of the bat-
tery at a higher switching frequency) allows the minimum
possible physical size.
The MAX8743 is intended for generating chipset, DRAM,
CPU I/O, or other low-voltage supplies down to 1V. The
MAX8743 is available in 28-pin QSOP and 36-pin thin
QFN packages.
Applications
Notebook Computers
CPU Core Supplies
Chipset/RAM Supplies as Low as 1V
1.8V and 2.5V I/O Supplies
Features
♦Ultra-High Efficiency
♦Accurate Current-Limit Option
♦Quick-PWM™ with 100ns Load-Step Response
♦1% VOUT Accuracy over Line and Load
♦High Output Impedance in Shutdown
♦Dual Mode™ Fixed 1.8V/1.5V/Adj or 2.5V/Adj Outputs
♦Adjustable 1V to 5.5V Output Range
♦2V to 28V Battery Input Range
♦200kHz/300kHz/420kHz/540kHz Nominal Switching
Frequency
♦Adjustable Overvoltage Protection
♦1.7ms Digital Soft-Start
♦Drives Large Synchronous-Rectifier FETs
♦Power-Good Window Comparator
♦2V ±1% Reference Output
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
________________________________________________________________ Maxim Integrated Products 1
19-3318; Rev 1; 8/05
Pin Configurations appear at end of data sheet.
Quick-PWM and Dual Mode are trademarks of Maxim Integrated
Products, Inc.
VCC
OUTPUT1
1.8V
BATTERY
4.5V TO 28V
ILIM1
ON2
DL1
TON
OUT1
LX1
DH1
FB1
GND
VDD
BST1
ILIM2
ON1
REF
DL2
CS2
OUT2
LX2
DH2
FB2
V+
BST2
SKIP
5V INPUT
PGOOD
OUTPUT2
2.5V
MAX8743EEI
UVP
OVP
CS1
Minimal Operating Circuit
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX8743EEI -40°C to +85°C 28 QSOP
MAX8743EEI+
-40°C to +85°C 28 QSOP
+Denotes lead-free package.
Ordering Information continued at end of data sheet.
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to AGND..............................................................-0.3 to +30V
VCC to AGND............................................................-0.3V to +6V
VDD to PGND............................................................-0.3V to +6V
AGND to PGND .....................................................-0.3V to +0.3V
PGOOD, OUT_ to AGND..........................................-0.3V to +6V
OVP, UVP, ILIM_, FB_, REF,
SKIP, TON, ON_ to AGND......................-0.3V to (VCC + 0.3V)
DL_ to PGND..............................................-0.3V to (VDD + 0.3V)
BST_ to AGND........................................................-0.3V to +36V
CS_ to AGND.............................................................-6V to +30V
DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V)
LX_ to BST_ ..............................................................-6V to +0.3V
DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V)
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation (TA= +70°C)
28-Pin QSOP (derate 10.8mW/°C above +70°C)........860mW
36-Pin 6mm ✕6mm Thin QFN
(derate 26.3mW/°C above +70°C).............................2105mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA= 0°C to +85°C, typical values are at +25°C, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
PWM CONTROLLERS
V+ Battery voltage, V+ 2 28
Input Voltage Range
VCC/VDD
VCC, VDD 4.5 5.5 V
FB1 to AGND
1.782
1.8
1.818
FB1 to VCC
1.485
1.5
1.515
V+ = 2V to 28V, ILOAD
= 0 to 8A, SKIP = VCC,
+25°C to +85°C FB1 to OUT1
0.99
1
1.01
FB1 to AGND
1.773
1.8
1.827
FB1 to VCC
1.477
1.5
1.523
DC Output Voltage OUT1
(Note 2)
VOUT1
V+ = 2V to 28V, ILOAD
= 0 to 8A, SKIP = VCC,
0°C to +85°C FB1 to OUT1
0.985
1
1.015
V
FB2 to AGND
2.475
2.5
2.525
V+ = 4.5V to 28V,
ILOAD = 0 to 4A,
SKIP = VCC,
+25°C to +85°C FB2 to OUT2
0.99
1
1.01
FB2 to AGND
2.463
2.5
2.537
DC Output Voltage OUT2
(Note 2)
VOUT2
V+ = 4.5V to 28V,
ILOAD = 0 to 4A,
SKIP = VCC,
0°C to +85°C FB2 to OUT2
0.985
1
1.015
V
Output Voltage Adjust Range OUT1, OUT2 1 5.5 V
Dual-Mode Threshold, Low OVP, FB_
0.05
0.1
0.15
V
OVP, ILIM_ VCC -
1.5
VCC -
0.4
Dual-Mode Threshold, High
FB1 1.9 2.0 2.1
V
ROUT1
VOUT1 = 1.5V 75
OUT_ Input Resistance
ROUT2
VOUT2 = 2.5V 100 kΩ
FB_ Input-Bias Current IFB
-0.1 +0.1
µA
Soft-Start Ramp Time Zero to full ILIM
1700
µs
Note 1: For the MAX8743EEI, AGND and PGND refer to a single pin designated GND.
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA= 0°C to +85°C, typical values are at +25°C, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
TON = AGND 120 137
153
TON = REF 153 174
195
TON = float 222 247
272
On-Time, Side 1 tON1
V+ = 24V,
VOUT1 = 2V
(Note 3)
TON = VCC 316 353
390
ns
TON = AGND 160 182
204
TON = REF 205 234
263
TON = float 301 336
371
On-Time, Side 2 tON2
V+ = 24V,
VOUT2 = 2V
(Note 3)
TON = VCC 432 483
534
ns
TON = AGND 125 135
145
TON = REF 125 135
145
TON = float 125 135
145
On-Time Tracking
On-time 2 with
respect to on-
time 1
(Note 3) TON = VCC 125 135
145
%
Minimum Off-Time tOFF (Note 3) 400
500
ns
Quiescent Supply Current (VCC)I
CC FB_ forced above the regulation point
1100 1500
µA
Quiescent Supply Current (VDD)I
DD FB_ forced above the regulation point <1 5 µA
Quiescent Supply Current (V+) I+ Measured at V+ 25 70 µA
Shutdown Supply Current (VCC)ON1 = ON2 = AGND, OVP = VCC <1 5 µA
Shutdown Supply Current (VDD)ON1 = ON2 = AGND <1 5 µA
Shutdown Supply Current (V+) ON1 = ON2 = AGND, measured at V+,
VCC = AGND or 5V <1 5 µA
Reference Voltage VREF VCC = 4.5V to 5.5V, no external REF load
1.98
2
2.02
V
Reference Load Regulation IREF = 0 to 50µA
0.01
V
REF Sink Current REF in regulation 10 µA
REF Fault Lockout Voltage Falling edge, hysteresis = 40mV 1.6 V
Overvoltage Trip Threshold
(Fixed-Threshold Mode)
OVP = AGND, with respect to error-
comparator trip threshold 112 114
117
%
1V < VOVP < 1.8V, external feedback,
measured at FB_ with respect to VOVP -28 0
+28
mV
Overvoltage Comparator Offset
(Adjustable-Threshold Mode) 1V < VOVP < 1.8V, internal feedback,
measured at OUT_ with respect to OUT_
regulation point
-3.5
0
+3.5
%
OVP Input Leakage Current 1V < VOVP < 1.8V
-100
<1
+100
nA
Overvoltage Fault Propagation
Delay FB_ forced 2% above trip threshold 1.5 µs
Output Undervoltage Threshold
UVP = VCC, with respect to error-comparator
trip threshold 65 70 75 %
Output Undervoltage Protection
Blanking Time From ON_ signal going high 10 30 ms
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA= 0°C to +85°C, typical values are at +25°C, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Current-Limit Threshold (Fixed) AGND - VCS_, ILIM_ = VCC 40 50 60 mV
AGND - VCS_, ILIM_ = 0.5V 40 50 60
Current-Limit Threshold
(Adjustable) AGND - VCS_, ILIM_ = 1V 85 100
115
mV
ILIM_ Adjustment Range
VILIM_
0.3 2.5 V
Negative Current-Limit Threshold
(Fixed) VCS_ - AGND, ILIM_ = VCC, TA = +25 oC -75 -60
-45
mV
Thermal-Shutdown Threshold Hysteresis = 15oC
+160
oC
VCC Undervoltage-Lockout
Threshold
Rising edge, hysteresis = 20mV, PWMs
disabled below this level
4.05 4.40
V
MAX8743EEI 1.5 5 Ω
DH Gate-Driver On-Resistance
BST - LX forced to 5V
(Note 4) MAX8743ETX 1.5 6 Ω
MAX8743EEI 1.5 5 Ω
DL Gate-Driver On-Resistance DL, high state
(Note 4) MAX8743ETX 1.5 6 Ω
MAX8743EEI 0.5 1.7 Ω
DL Gate-Driver On-Resistance DL, low state
(Note 4) MAX8743ETX 0.5 2.7 Ω
DH_ Gate-Driver Source/Sink
Current VDH_ = 2.5V, VBST_ = VLX_ = 5V 1 A
DL_ Gate-Driver Sink Current VDL_ = 2.5V 3 A
DL_ Gate-Driver Source Current VDL_ = 2.5V 1 A
ON_, SKIP 2.4
Logic Input High Voltage VIH UVP VCC -
0.4
V
ON_, SKIP 0.8
Logic Input Low Voltage VIL UVP
0.05
V
VCC level VCC -
0.4
Float level
3.15 3.85
REF level
1.65 2.35
TON Input Logic Level
AGND level 0.5
V
Logic Input Current TON (AGND or VCC)-3+3µA
Logic Input Current ON_, SKIP, UVP -1 +1 µA
PGOOD Trip Threshold (Lower) With respect to error-comparator trip
threshold, falling edge
-12.5
-10
-7.5
%
PGOOD Trip Threshold (Upper) With respect to error-comparator trip
threshold, rising edge
+7.5 +10 +12.5
%
PGOOD Propagation Delay Falling edge, FB_ forced 2% below PGOOD
trip threshold 1.5 µs
PGOOD Output Low Voltage ISINK = 1mA 0.4 V
PGOOD Leakage Current High state, forced to 5.5V 1 µA
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA= -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
PWM CONTROLLERS
V+ Battery voltage, V+ 2 28
Input Voltage Range
VCC/VDD
VCC, VDD 4.5 5.5 V
FB1 to AGND 1.773 1.827
FB1 to VCC
1.477 1.523
D C O utp ut V ol tag e, O U T1
VOUT1
V+ = 2V to 28V, SKIP = VCC,
ILOAD = 0 to 8A
( N ote 2)
FB1 to OUT1 0.985 1.015
V
FB2 to AGND 2.463 2.537
D C O utp ut V ol tag e, O U T2
VOUT2
V+ = 2V to 28V, SKIP = VCC,
ILOAD = 0 to 4A ( N ote 2)
FB2 to OUT2 0.985 1.015
V
Output Voltage Adjust Range OUT1, OUT2 1.0 5.5 V
Dual-Mode Threshold, Low OVP, FB_
0.05 0.15
V
OVP, ILIM_ VCC -
1.5
VCC -
0.4
Dual-Mode Threshold, High
FB_ 1.9 2.1
V
ROUT1
VOUT1 = 1.5V 75
OUT_ Input Resistance
ROUT2
VOUT2 = 2.5V
100
kΩ
FB_ Input Bias Current IFB
-0.1 +0.1
µA
TON = AGND
120
153
TON = REF
153
195
TON = float
217
272
On-Time, Side 1 tON1
V+ = 24V, VOUT1 = 2V
(Note 3)
TON = VCC
308
390
ns
TON = AGND
160
204
TON = REF
205
263
TON = float
295
371
On-Time, Side 2 tON2
V+ = 24V, VOUT2 = 2V
(Note 3)
TON = VCC
422
534
ns
TON = AGND
125
145
TON = REF
125
145
TON = float
125
145
On-Time Tracking
On-time 2, with
respect to on-time 1
(Note 3)
TON = VCC
125
145
%
Minimum Off-Time tOFF (Note 3) 500 ns
Quiescent Supply Current (VCC)I
CC FB forced above the regulation point
1500
µA
Quiescent Supply Current (VDD)I
DD FB forced above the regulation point 5 µA
Quiescent Supply Current (V+) I+ Measured at V+ 70 µA
Reference Voltage VREF VCC = 4.5V to 5.5V, no external REF load
1.98 2.02
V
Reference Load Regulation IREF = 0 to 50µA
0.01
V
Overvoltage Trip Threshold
(Fixed-Threshold Mode)
OVP = GND, with respect to FB_ regulation
point, no load
112
117 %
Output Undervoltage Threshold UVP = VCC, with respect to FB_ regulation
point, no load 65 75 %
Current-Limit Threshold (Fixed) AGND - VCS_, ILIM_ = VCC 35 65 mV
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
6_______________________________________________________________________________________
0
0.01 1010.1
300
350
400
200
250
100
150
50
MAX8743 toc01
LOAD CURRENT (A)
FREQUENCY (kHz)
FREQUENCY vs. LOAD CURRENT
OUT1, SKIP = VCC
OUT2, SKIP = VCC
OUT1, SKIP = GND
OUT2, SKIP = GND
0
50
100
150
200
250
300
350
400
481216 20 24
MAX8743 toc02
INPUT VOLTAGE (V)
FREQUENCY (kHz)
FREQUENCY vs. INPUT VOLTAGE
(TON = FLOAT, SKIP = VCC)
OUT1
OUT2
IOUT1 = 8A
IOUT2 = 4A
__________________________________________Typical Operating Characteristics
(Circuit of Figure 1, components from Table 1, VIN = 15V, SKIP = GND, TON = unconnected, TA= +25°C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA= -40°C to +85°C, unless otherwise noted.) (Note 5)
Note 2: When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error-compara-
tor threshold by 50% of the output voltage ripple. In discontinuous conduction (SKIP = AGND, light load), the output voltage
has a DC regulation higher than the error-comparator threshold by approximately 1.5% due to slope compensation.
Note 3: On-time and off-time specifications are measured from the 50% point to the 50% point at DH_ with LX_ = GND, BST_ = 5V,
and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds.
Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the QFN
package. The MAX8743EEI and MAX8743ETX contain the same die, and the QFN package imposes no additional resis-
tance in-circuit.
Note 5: Specifications to -40°C are guaranteed by design, not production tested.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AGND - VCS_, ILIM_ = 0.5V 35 65
Current-Limit Threshold
(Adjustable) AGND - VCS_, ILIM_ = 1V 80 120 mV
VCC Undervoltage-Lockout
Threshold
Rising edge, hysteresis = 20mV, PWMs
disabled below this level
4.05 4.40
V
ON_, SKIP 2.4
Logic Input High Voltage VIH UVP VCC -
0.4
V
ON_, SKIP 0.8
Logic Input Low Voltage VIL UVP
0.05
V
TON (AGND or VCC)-3+3
Logic Input Current ON_, SKIP, UVP -1 +1 µA
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
_______________________________________________________________________________________ 7
0
4.5
3.0
1.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
51510 20 25 30
MAX8743 toc03
INPUT VOLTAGE V+ (V)
SUPPLY CURRENT (mA)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (SKIP = VCC)
ICC
VCC = VDD = 5V
IDD
I+ (25µA TYP)
0
100
200
300
400
500
600
700
800
900
1000
1100
MAX8743 toc04
INPUT VOLTAGE V+ (V)
SUPPLY CURRENT (µA)
51015202530
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (SKIP = GND)
VCC = VDD = 5V
IDD (600nA TYP)
ICC
I+
10
0.01 1010.1
60
70
80
90
100
40
50
20
30
MAX8743 toc05
LOAD CURRENT (A)
EFFICIENCY (%)
EFFICIENCY vs. LOAD CURRENT
(8A COMPONENTS, SKIP = VCC)
V+ = 7V
V+ = 20V
V+ = 12V
OUT1 = 1.8V
50
0.01 1010.1
75
80
85
90
95
100
65
70
55
60
MAX8743 toc06
LOAD CURRENT (A)
EFFICIENCY (%)
EFFICIENCY vs. LOAD CURRENT
(8A COMPONENTS, SKIP = GND)
V+ = 7V
V+ = 20V
OUT1 = 1.8V
V+ = 12V
10
50
30
70
90
110
130
150
170
190
210
230
250
0 0.5 1.0 1.5 2.0 2.5
CURRENT-LIMIT TRIP POINT
vs. ILIM VOLTAGE
MAX8743 toc09
ILIM VOLTAGE (V)
CURRENT-LIMIT TRIP POINT (mV)
10
0.01 1010.1
60
70
80
90
100
40
50
20
30
MAX8743 toc07
LOAD CURRENT (A)
EFFICIENCY (%)
EFFICIENCY vs. LOAD CURRENT
(4A COMPONENTS, SKIP = VCC)
V+ = 7V
V+ = 20V
V+ = 12V
OUT2 = 2.5V
80
75
0.01 1010.1
95
100
90
85
MAX8743 toc08
LOAD CURRENT (A)
EFFICIENCY (%)
EFFICIENCY vs. LOAD CURRENT
(4A COMPONENTS, SKIP = GND)
V+ = 7V
V+ = 12V
V+ = 20V
OUT2 = 2.5V
1.0
1.2
1.1
1.4
1.3
1.6
1.5
1.7
1.9
1.8
2.0
1.0 1.2 1.31.1 1.4 1.5 1.6 1.7 1.8
MAX8743 toc10
OVP VOLTAGE (V)
NORMALIZED THRESHOLD (V)
NORMALIZED OVERVOLTAGE PROTECTION
THRESHOLD vs. OVP VOLTAGE
MAX8743 toc11
IOUT2
2A/div
20µs/div
VOUT2
100mV/div
LOAD-TRANSIENT RESPONSE
(4A COMPONENTS, PWM MODE, VOUT2 = 2.5V)
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components from Table 1, VIN = 15V, SKIP = GND, TON = unconnected, TA= +25°C, unless otherwise noted.)
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
8_______________________________________________________________________________________
MAX8743 toc13
400µs/div
VOUT2
1V/div
2.5V
0V
0V
0V
0A ON2
5V/div
PGOOD
5V/div
ILX2
1A/div
STARTUP WAVEFORM (VOUT2)
ROUT2 = 2.5Ω
MAX8743 toc14
400µs/div
VOUT2
1V/div
2.5V
0V
0V
0V
0V
ON2
5V/div
PGOOD
5V/div
DL2
5V/div
SHUTDOWN WAVEFORM (VOUT2)
ROUT2 = 2.5Ω
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components from Table 1, VIN = 15V, SKIP = GND, TON = unconnected, TA= +25°C, unless otherwise noted.)
PIN
QSOP
TQFN
NAME
FUNCTION
132OUT1
Output Voltage Connection for the OUT1 PWM. Connect directly to the junction of the external
inductor and output filter capacitors. OUT1 senses the output voltage to determine the on-time
and also serves as the feedback input in fixed-output modes.
233FB1 Feed b ack Inp ut for O U T1. C onnect to G N D for 1.8V fi xed outp ut or to V
C C
for 1.5V fi xed outp ut, or
connect to a r esi stor - d i vi d er netw or k fr om O U T1 for an ad j ustab l e outp ut b etw een 1V and 5.5V .
334ILIM1
Current-Limit Threshold Adjustment for OUT1. The current-limit threshold at CS1 is 0.1 times the
voltage at ILIM1. Connect a resistor-divider network from REF to set the current-limit threshold
between 25mV and 250mV (with 0.25V to 2.5V at ILIM). Connect to VCC to assert 50mV default
current-limit threshold.
435 V+
Battery Voltage-Sense Connection. Connect to input power source. V+ is only used to adjust the
DH_ on-time for pseudofixed-frequency operation.
On-Time Selection Control Input. This four-level input pin sets the DH_ on-time to determine the
operating frequency.
TON FREQUENCY (OUT1) (kHz)
FREQUENCY (OUT2) (kHz)
AGND 620 460
REF 485 355
Open 345 255
51TON
VCC 235 170
62SKIP Pulse-Skipping Control Input. Connect to VCC for low-noise forced-PWM mode. Connect to AGND
to enable pulse-skipping operation.
Pin Description
MAX8743 toc12
IOUT1
5A/div
20µs/div
VOUT1
100mV/div
LOAD-TRANSIENT RESPONSE
(8A COMPONENTS, PWM MODE, VOUT1 = 1.8V)
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN
QSOP
TQFN
NAME
FUNCTION
73
PGOOD
Power-Good Open-Drain Output. PGOOD is low when either output voltage is more than 10%
above or below the normal regulation point, and during the 1.7ms soft-start time.
84OVP
Overvoltage Protection Threshold. An overvoltage fault occurs if the voltage on FB1 or FB2 is
greater than the programmed overvoltage trip threshold. Adjustment range is 1V (100%) to 1.8V
(180%). Connect OVP to GND to set the default overvoltage threshold of 114% of nominal.
Connect to VCC to disable OVP and clear the OVP latch.
95UVP
U nd er vol tag e P r otecti on Thr eshol d . An und er vol tag e faul t occur s i f the vol tag e on FB1 or FB2 i s l ess
than the und er vol tag e tr i p thr eshol d ( 70% of nom i nal ) . C onnect U V P to V
C C
to enab l e und er vol tag e
p r otecti on. C onnect to GN D to d i sab l e und er vol tag e p r otecti on and cl ear the U V P l atch.
10 7 REF +2.0V Reference Voltage Output. Bypass to GND with 0.22µF (min) capacitor. Can supply 50µA
for external loads.
11 8 ON1 OU T1 ON /OFF C ontr ol Inp ut. C onnect to AGN D to tur n OU T1 off. C onnect to V
C C
to tur n O U T1 on.
12 11 ON2 OU T2 ON /OFF C ontr ol Inp ut. C onnect to AGN D to tur n OU T2 off. C onnect to V
C C
to tur n O U T2 on.
13 12 ILIM2
Current-Limit Threshold Adjustment for OUT2. The current-limit threshold at CS2 is 0.1 times the
voltage at ILIM2. Connect a resistor-divider network from REF to set the current-limit threshold
between 25mV and 250mV (with 0.25V to 2.5V at ILIM). Connect to VCC to assert 50mV default
current-limit threshold.
14 13 FB2 Feedback Input for OUT2. Connect to GND for 2.5V fixed output, or connect to a resistor-divider
network from OUT2 for an adjustable output between 1V and 5.5V.
15 14 OUT2
Output Voltage Connection for the OUT2 PWM. Connect directly to the junction of the external
inductor and output filter capacitors. OUT2 senses the output voltage to determine the on-time
and also serves as the feedback input in fixed-output modes.
16 15 CS2
Current-Sense Input for OUT2. CS2 is the input to the current-limiting circuitry for valley current
limiting. For lowest cost and highest efficiency, connect to LX2. For highest accuracy, use a sense
resistor. See the Current-Limit Circuit (ILIM_) section.
17 16 LX2 External Inductor Connection for OUT2. Connect to the switched side of the inductor. LX2 serves
as the internal lower supply voltage rail for the DH2 high-side gate driver.
18 18 DH2 High-Side Gate-Driver Output for OUT2. Swings from LX2 to BST2.
19 19 BST2
Boost Flying Capacitor Connection for OUT2. Connect to an external capacitor and diode
according to the standard application circuit in Figure 1. See the MOSFET Gate Drivers (DH_,
DL_) section.
20 20 DL2 Low-Side Gate-Driver Output for OUT2. DL2 swings from PGND to VDD.
21 21 VDD Supply Input for the DL Gate Drivers. Connect to system supply voltage, +4.5V to +5.5V. Bypass
to PGND with a low-ESR 4.7µF capacitor.
22 22 VCC Analog Supply Input. Connect to system supply voltage, +4.5V to +5.5V, with a 20Ω series
resistor. Bypass to AGND with a 1µF capacitor.
23 — GND Ground. Combined analog and power ground. Serves as negative input for CS_ amplifiers.
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
10 ______________________________________________________________________________________
Standard Application Circuit
The standard application circuit (Figure 1) generates a
1.8V and a 2.5V rail for general-purpose use in note-
book computers.
See Table 1 for component selections. Table 2 lists
component manufacturers.
Detailed Description
The MAX8743 buck controller is designed for low-volt-
age power supplies for notebook computers. Maxim’s
proprietary Quick-PWM pulse-width modulator in the
MAX8743 (Figure 2) is specifically designed for han-
dling fast load steps while maintaining a relatively con-
stant operating frequency and inductor operating point
over a wide range of input voltages. The Quick-PWM
architecture circumvents the poor load-transient timing
problems of fixed-frequency current-mode PWMs while
avoiding the problems caused by widely varying
switching frequencies in conventional constant-on-time
and constant-off-time PWM schemes.
5V Bias Supply (VCC and VDD)
The MAX8743 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s 95% efficient 5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the 5V supply can be generated
with an external linear regulator such as the MAX1615.
The power input and 5V bias inputs can be connected
together if the input source is a fixed 4.5V to 5.5V sup-
ply. If the 5V bias supply is powered up prior to the bat-
tery supply, the enable signal (ON1, ON2) must be
delayed until the battery voltage is present to ensure
startup. The 5V bias supply must provide VCC and
gate-drive power, so the maximum current drawn is:
IBIAS = ICC + f (QG1 + QG2) = 5mA to 30mA (typ)
where ICC is 1mA (typ), f is the switching frequency,
and QG1 and QG2 are the MOSFET data sheet total
gate-charge specification limits at VGS = 5V.
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time current-mode type with
voltage feed-forward (Figure 3). This architecture relies
on the output filter capacitor’s effective series resis-
tance (ESR) to act as a current-sense resistor, so the
output ripple voltage provides the PWM ramp signal.
The control algorithm is simple: the high-side switch on-
time is determined solely by a one-shot whose pulse
width is inversely proportional to input voltage and
directly proportional to output voltage. Another one-shot
sets a minimum off-time (400ns typ). The on-time one-
PIN
QSOP
TQFN
NAME
FUNCTION
—23
AGND
Analog Ground. Serves as negative input for CS_ amplifiers. Connect backside pad to AGND.
—24PGND Power Ground
24 26 DL1 Low-Side Gate-Driver Output for OUT1. DL1 swings from PGND to VDD.
25 27 BST1 Boost Fl yi ng C ap aci tor C onnecti on for O U T1. C onnect to an exter nal cap aci tor and d i od e accor d i ng
to the stand ar d ap p l i cati on ci r cui t i n Fi g ur e 1. S ee the M OS FE T G ate D r i ver s ( D H _, D L_) secti on.
26 28 DH1 High-Side Gate-Driver Output for OUT1. Swings from LX1 to BST1.
27 30 LX1 External Inductor Connection for OUT1. Connect to the switched side of the inductor. LX1 serves
as the internal lower supply voltage rail for the DH1 high-side gate driver.
28 31 CS1
Current-Sense Input for OUT1. CS1 is the input to the current-limiting circuitry for valley current
limiting. For lowest cost and highest efficiency, connect to LX1. For highest accuracy, use a sense
resistor. See the Current-Limit Circuit (ILIM_) section.
—
6, 9, 10,
17, 25,
29, 36
N.C. No Connection
Pin Description (continued)
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
______________________________________________________________________________________ 11
shot is triggered if the error comparator is low, the low-
side switch current is below the current-limit threshold,
and the minimum off-time one-shot has timed out
(Table 3).
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time for both controllers. This fast,
low-jitter, adjustable one-shot includes circuitry that
varies the on-time in response to battery and output
voltage. The high-side switch on-time is inversely pro-
portional to the battery voltage as measured by the V+
input, and proportional to the output voltage. This algo-
rithm results in a nearly constant switching frequency
despite the lack of a fixed-frequency clock generator.
The benefits of a constant switching frequency are
twofold: First, the frequency can be selected to avoid
noise-sensitive regions such as the 455kHz IF band;
second, the inductor ripple-current operating point
remains relatively constant, resulting in easy design
methodology and predictable output voltage ripple.
The on-times for side 1 are set 35% higher than the on-
times for side 2. This is done to prevent audio-frequen-
cy “beating” between the two sides, which switch asyn-
chronously for each side. The on-time is given by:
On-time = K (VOUT + 0.075V) / VIN
where K is set by the TON pin-strap connection (Table
4), and 0.075V is an approximation to accommodate
for the expected drop across the low-side MOSFET
switch. One-shot timing error increases for the shorter
on-time settings due to fixed propagation delays; it is
approximately ±12.5% at higher frequencies and ±10%
at lower frequencies. This translates to reduced switch-
ing-frequency accuracy at higher frequencies (Table
4). Switching frequency increases as a function of load
current due to the increasing drop across the low-side
MOSFET, which causes a faster inductor-current dis-
charge ramp. The on-times guaranteed in the Electrical
Characteristics tables are influenced by switching
delays in the external high-side power MOSFET.
Two external factors that influence switching-frequency
accuracy are resistive drops in the two conduction
VDD = 5V
BIAS SUPPLY
POWER-GOOD
INDICATOR
MAX8743EEI
VCC
OUTPUT1
1.8V, 8A
VIN
7V TO 24V
D3
CMPSH-3A
ILIM1
DL1
TON
CS1
OUT1
GND
C3
3 ✕ 470µF
C4
470µF
D1 Q4
Q3
Q1
Q2
LX1
DH1
C5
0.1µF
C6
0.1µF
C7
0.22µFFB1
VDD
UVP
C8
1µF
C1
3 ✕ 10µF
C2
2 ✕ 10µF
11
12
8
19
18
17
20
16
15
6
14
7
22
25
26
27
24
5
10
2
23
21
9
C11
1µF
L1
2.2µH
L2
4.7µH
13
3
28
1
BST1
ILIM2
REF
ON1
ON2
OVP
DL2
CS2
5V
100kΩ
OUT2
LX2
DH2
FB2
PGOOD
V+
4
BST2
SKIP
C9
4.7µF
R3
20Ω
R1
5mΩ
OUTPUT2
2.5V, 4A
R2
10mΩ
D2
ON/OFF
CONTROLS
Figure 1. Standard Application Circuit
MAX8743
loops (including inductor and PC board resistance) and
the dead-time effect. These effects are the largest con-
tributors to the change of frequency with changing load
current. The dead-time effect increases the effective
on-time, reducing the switching frequency as one or
both dead times. It occurs only in PWM mode (SKIP =
high) when the inductor current reverses at light or neg-
ative load currents. With reversed inductor current, the
inductor’s EMF causes LX to go high earlier than nor-
mal, extending the on-time by a period equal to the
low-to-high dead time.
For loads above the critical conduction point, the actual
switching frequency is:
where VDROP1is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2 is
the sum of the resistances in the charging path; and
tON is the on-time calculated by the MAX8743.
Automatic Pulse-Skipping Switchover
In skip mode (SKIP = GND), an inherent automatic
switchover to pulse-frequency modulation (PFM) takes
place at light loads. This switchover is effected by a
comparator that truncates the low-side switch on-time at
the inductor current’s zero crossing. This mechanism
causes the threshold between pulse-skipping PFM and
nonskipping PWM operation to coincide with the bound-
ary between continuous and discontinuous inductor-cur-
rent operation (also known as the critical conduction
point). For a 7V to 24V battery range, this threshold is rel-
atively constant, with only a minor dependence on bat-
tery voltage:
where K is the on-time scale factor (Table 4). The load-
current level at which PFM/PWM crossover occurs,
ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple cur-
rent, which is a function of the inductor value (Figure 4).
IKV
2L V-V
V
LOAD(SKIP) OUT_ IN OUT_
IN
≈×
fVV
tV V
OUT DROP
ON IN DROP
=+
+
()
1
2
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
12 ______________________________________________________________________________________
Table 1. Component Selection for
Standard Applications
Table 2. Component Suppliers
COMPONENT SIDE 1: 1.8V AT 8A/
SIDE 2: 2.5V AT 4A
Input Range 4.5V to 28V
Q1 High-Side MOSFET Fairchild Semiconductor
FDS6612A
Q2 Low-Side MOSFET Fairchild Semiconductor
FDS6670A
Q3, Q4 High/Low-Side
MOSFETs
Fairchild Semiconductor
FDS6982A
D1, D2 Rectifier Nihon EP10QY03
D3 Rectifier Central Semiconductor
CMPSH-3A
L1 Inductor
2.2µH
Panasonic ETQP6F2R2SFA
or
Sumida CDRH127-2R4
L2 Inductor 4.7µH
Sumida CDRH124-4R7MC
C1 (3), C2 (2) Input
Capacitor
10µF, 25V
Taiyo Yuden
TMK432BJ106KM or
TDK C4532X5R1E106M
C3 (3), C4 Output Capacitor
470µF, 6V
Kemet T510X477M006AS or
Sanyo 6TPB330M
RSENSE1
5mΩ, ±1%, 1W
IRC LR2512-01-R005-F or
Dale WSL-2512-R005F
RSENSE2
10mΩ, ±1%, 0.5W
IRC LR2010-01-R010-F or
Dale WSL-2010-R010F
MANUFACTURER WEBSITE
Central Semiconductor www.centralsemi.com
Fairchild Semiconductor www.fairchildsemi.com
International Rectifier www.irf.com
IRC www.irctt.com
Kemet www.kemet.com
NIEC (Nihon) www.niec.co.jp
Panasonic www.panasonic.com
Sanyo www.sanyo.com/components
Sumida www.sumida.com
Taiyo Yuden www.t-yuden.com
TDK www.component.tdk.com
Vishay/Dale www.vishay.com
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
______________________________________________________________________________________ 13
For example, in the standard application circuit with
VOUT1 = 2.5V, VIN = 15V, and K = 2.96µs (Table 4),
switchover to pulse-skipping operation occurs at ILOAD
= 0.7A or about 1/6 full load. The crossover point
occurs at an even lower value if a swinging (soft-satu-
ration) inductor is used.
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input-voltage levels).
DC output accuracy specifications refer to the threshold
of the error comparator. When the inductor is in continu-
ous conduction, the output voltage has a DC regulation
higher than the trip level by 50% of the ripple. In discon-
tinuous conduction (SKIP = GND, light-load), the output
FB2
OUT 2
PWM
CONTROLLER
(FIGURE 3)
V+
V+
2V
REF
AGND*
* IN THE MAX8743EEI, AGND AND PGND ARE INTERNALLY CONNECTED AND CALLED GND.
FAULT1
FAULT2
REF
20Ω
VDD
VCC
OUT1
UVP
OVP
FB1
SKIP
TON
ON1
ON2
5V INPUT
DL1
VDD
LX1
CS1
DH1
BST1
VDD
VDD
VDD
V+
PWM
CONTROLLER
(FIGURE 3)
PGND*
MAX8743
PGOOD
VCC - 1V
0.5V
ILIM1 ILIM2
DL2
VDD
LX2
CS2
DH2
BST2
VDD
V+
VCC - 1V
0.5V
2V TO 28V
Figure 2. Functional Diagram
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
14 ______________________________________________________________________________________
FROM
OUT
REF
FROM ZERO-CROSSING
COMPARATOR
ERROR
AMP
TON
FEEDBACK
MUX
(SEE FIGURE 9)
x2
TO DL DRIVER
SHUTDOWN
TO DH DRIVER
ON-TIME
COMPUTE
TON
1-SHOT
FROM ILIM
COMPARATOR
FROM
OPPOSITE
PWM
TO
OPPOSITE
PWM
TOFF 1-SHOT
TRIG
TRIG
Q
Q
S
R
FAULT
Q
R
Q
S
RQ
S
TIMER
TON
V+
S
RQ
TO PGOOD
OR-GATE
1.1V 0.9V
0.7V
0.1V
1.14V
OVP
VCC - 1V
UVP
FB_
OUT_
Figure 3. PWM Controller (One Side Only)
voltage has a DC regulation higher than the trip level by
approximately 1.5% due to slope compensation.
Forced-PWM Mode (
SKIP
= High)
The low-noise, forced-PWM mode (SKIP = high) dis-
ables the zero-crossing comparator, which controls the
low-side switch on-time. This causes the low-side gate-
drive waveform to become the complement of the high-
side gate-drive waveform. This in turn causes the
inductor current to reverse at light loads as the PWM
loop strives to maintain a duty ratio of VOUT/VIN. The
benefit of forced-PWM mode is to keep the switching
frequency fairly constant, but it comes at a cost: The
no-load battery current can be 10mA to 40mA, depend-
ing on the external MOSFETs.
Forced-PWM mode is most useful for reducing audio-
frequency noise, improving load-transient response,
providing sink-current capability for dynamic output
voltage adjustment, and improving the cross-regulation
of multiple-output applications that use a flyback trans-
former or coupled inductor.
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a unique “valley” current-
sensing algorithm. If the magnitude of the current-sense
signal at CS_ is above the current-limit threshold, the
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
______________________________________________________________________________________ 15
PWM is not allowed to initiate a new cycle (Figure 5). The
actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple cur-
rent. Therefore, the exact current-limit characteristic and
maximum load capability are a function of the sense
resistance, inductor value, and battery voltage.
There is also a negative current limit that prevents
excessive reverse inductor currents when VOUT is
sinking current. The negative current-limit threshold is
set to approximately 120% of the positive current limit
and therefore tracks the positive current limit when
ILIM is adjusted.
The current-limit threshold is adjusted with an internal
5µA current source and an external resistor at ILIM. The
current-limit threshold adjustment range is from 25mV
to 250mV. In the adjustable mode, the current-limit
threshold voltage is precisely 1/10 the voltage seen at
ILIM. The threshold defaults to 50mV when ILIM is con-
nected to VCC. The logic threshold for switchover to the
50mV default value is approximately VCC - 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signal seen by CS_ and GND. Mount or
place the IC close to the low-side MOSFET and sense
resistor with short, direct traces, making a Kelvin sense
connection to the sense resistor. In Figure 1, the
Schottky diodes (D1 and D2) provide current paths
parallel to the Q2/RSENSE and Q4/RSENSE current
paths, respectively. Accurate current sensing requires
D1/D2 to be off while Q2/Q4 conducts. Avoid large cur-
rent-sense voltages that, combined with the voltage
across Q2/Q4, would allow D1/D2 to conduct. If very
large sense voltages are used, connect D1/D2 in paral-
lel with Q2/Q4 only.
MOSFET Gate Drivers (DH_, DL_)
The DH and DL drivers are optimized for driving mod-
erate-size, high-side and larger, low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
VBATT - VOUT differential exists. An adaptive dead-time
circuit monitors the DL output and prevents the high-
side FET from turning on until DL is fully off. There must
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate for the adaptive dead-time
Table 3. Operating Mode Truth Table
ON1 ON2 SK IP
DL1/DL2 MODE COMMENTS
GND GND
XLow/Low Shutdown Low-power shutdown state. ICC < 1µA (typ).
VCC GND VCC Switching/Low
Run (PWM), Low Noise,
Side 1 Only
GND VCC VCC Low/Switching
Run (PWM), Low Noise,
Side 2 Only
VCC VCC VCC
Switching/
Switching
Run (PWM), Low Noise,
Both Sides Active
Low-noise, fixed-frequency PWM at all load conditions.
Low noise, high IQ.
VCC GND GND Switching/Low
Run (PWM/PFM), Skip
Mode, Side 1 Only
GND VCC GND Low/Switching
Run (PWM/PFM), Skip
Mode, Side 2 Only
VCC VCC GND
Switching/
Switching
Run ( P W M /P FM ) , S ki p
M od e, Both S i d es Acti ve
Normal operation with automatic PWM/PFM switchover
for pulse skipping at light loads. Best light-load
efficiency.
VCC VCC
XLow/Low
UV Fault (Either Side),
Thermal Fault, or
VCC Below UVLO
Fault latch has been set by undervoltage protection
circuit, thermal shutdown, or VCC below UVLO. The
MAX8743 remains in fault mode until VCC power is
cycled below POR or ON1/ON2 is toggled.
VCC VCC
XHigh/High OV Fault
(Either Side)
Fault latch has been set by overvoltage protection circuit.
The MAX8743 remains in fault mode until VCC power is
cycled below the 2V (typ) POR level.
circuit to work properly. Otherwise, the sense circuitry
in the MAX8743 interprets the MOSFET gate as “off”
while there is actually still charge left on the gate. Use
very short, wide traces measuring 10 to 20 squares (50
to 100 mils wide if the MOSFET is 1in from the
MAX8743).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns (typ) internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.5Ωtypical on-resistance. This helps
prevent DL from being pulled up during the fast rise
time of the inductor node, due to capacitive coupling
from the drain to the gate of the low-side synchronous-
rectifier MOSFET. However, for high-current applica-
tions, some combinations of high- and low-side FETs
might be encountered that will cause excessive gate-
drain coupling, which can lead to efficiency-killing,
EMI-producing shoot-through currents. This is often
remedied by adding a resistor in series with BST, which
increases the turn-on time of the high-side FET without
degrading the turn-off time (Figure 6).
POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the fault latch and prepar-
ing the PWM for operation. Below 4.05V (min), the VCC
undervoltage-lockout (UVLO) circuitry inhibits switching
by keeping DH and DL low.
Soft-start allows a gradual increase of the internal cur-
rent-limit level during startup to reduce the input surge
currents. When ON1 or ON2 goes high, the respective
digital soft-start timer begins to ramp up the maximum
allowed current limit in five steps. During the first step,
the controller limits the current limit to only 20% of the full
current limit. The current limit is increased by 20% every
425µs. 100% current limit is available after 1.7ms ±50%.
A continuously adjustable analog soft-start function can
be realized by adding a capacitor in parallel with the
ILIM external resistor-divider network. This soft-start
method requires a minimum interval between power-
down and power-up to discharge the capacitor.
Power-Good Output (PGOOD)
The PGOOD window comparator continuously monitors
the output voltage for both overvoltage and undervolt-
age conditions. In shutdown, standby, and soft-start,
PGOOD is actively held low. After a digital soft-start
has terminated, PGOOD is released when the output is
within 10% of the error-comparator threshold. The
PGOOD output is a true open-drain type with no para-
sitic ESD diodes. Note that the PGOOD window detec-
tor is independent of the output overvoltage and
undervoltage protection (UVP) thresholds.
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
16 ______________________________________________________________________________________
BST
+5V VIN
5Ω
DH
LX
MAX8743
Figure 6. Reducing the Switching-Node Rise Time
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
INDUCTOR CURRENT
ILOAD = IPEAK / 2
ON-TIME0 TIME
IPEAK
L
VBATT - VOUT
∆i
∆t=
Figure 5. ‘‘Valley’’ Current-Limit Threshold Point
INDUCTOR CURRENT
ILIMIT
ILOAD
0 TIME
IPEAK
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
______________________________________________________________________________________ 17
Output Overvoltage Protection
The output voltage can be continuously monitored for
overvoltage. When overvoltage protection is enabled, if
the output exceeds the overvoltage threshold, overvolt-
age protection is triggered and the DL low-side gate-
drivers are forced high. This activates the low-side
MOSFET switch, which rapidly discharges the output
capacitor and reduces the input voltage.
Note that DL latching high causes the output voltage to
dip slightly negative when energy has been previously
stored in the LC tank circuit. For loads that cannot tol-
erate a negative voltage, place a power Schottky diode
across the output to act as a reverse polarity clamp.
Connect OVP to GND to enable the default trip level of
114% of the nominal output. To adjust the overvoltage-
protection trip level, apply a voltage from 1V (100%) to
1.8V (180%) at OVP. Disable the overvoltage protection
by connecting OVP to VCC.
The overvoltage trip level depends on the internal or
external output-voltage feedback divider and is restrict-
ed by the output-voltage adjustment range (1V to 5.5V)
and by the absolute maximum rating of OUT_. Setting
the overvoltage threshold higher than the output-volt-
age adjustment range is not recommended.
Output Undervoltage Protection
The output voltage can be continuously monitored for
undervoltage. When undervoltage protection is
enabled (UVP = VCC), if the output is less than 70% of
the error-amplifier trip voltage, undervoltage protection
is triggered. If an undervoltage protection threshold is
set, the DL low-side gate driver is forced low and the
outputs float. Connect UVP to GND to disable under-
voltage protection.
Note the nonstandard logic levels if actively driving
UVP (see the Electrical Characteristics).
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good
switching frequency and inductor operating point, and
the following four factors dictate the rest of the design:
1) Input Voltage Range. The maximum value
(VIN(MAX)) must accommodate the worst-case high
AC adapter voltage. The minimum value (VIN(MIN))
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selector
switches. Lower input voltages result in better effi-
ciency.
2) Maximum Load Current. There are two values to
consider. The peak load current (ILOAD(MAX)) deter-
mines the instantaneous component stresses and
filtering requirements, and thus drives output capac-
itor selection, inductor saturation rating, and the
design of the current-limit circuit. The continuous
load current (ILOAD) determines the thermal stress-
es and thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing com-
ponents.
3) Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage due to MOSFET switching losses that
are proportional to frequency and VIN2.
4) Inductor Operating Point. This choice provides
trade-offs between size vs. efficiency. Low inductor
values cause large ripple currents, resulting in the
smallest size, but poor efficiency and high output
noise. The minimum practical inductor value is one
that causes the circuit to operate at the edge of criti-
cal conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further size-
reduction benefit.
The MAX8743’s pulse-skipping algorithm initiates
skip mode at the critical conduction point.
Therefore, the inductor operating point also deter-
mines the load-current value at which PFM/PWM
switchover occurs. The optimum point is usually
found between 20% and 50% of ripple current.
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
18 ______________________________________________________________________________________
Inductor Selection
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as follows:
Example: ILOAD(MAX) = 8A, VIN = 15V, VOUT = 1.8V,
f = 300kHz, 25% ripple current or LIR = 0.25:
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (IPEAK):
IPEAK = ILOAD(MAX) + [(LIR / 2) ✕ILOAD(MAX)]
Transient Response
The inductor ripple current also impacts transient-
response performance, especially at low VIN - VOUT dif-
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maxi-
mum duty factor, which can be calculated from the on-
time and minimum off-time:
where:
where minimum off-time = 400ns typ (Table 4).
The amount of overshoot during a full-load to no-load
transient due to stored inductor energy can be calculat-
ed as:
VSOAR = L ✕IPEAK2/ (2 x COUT x VOUT)
where IPEAK is the peak inductor current.
Determining the Current Limit
For most applications, set the MAX8743 current limit by
the following procedure:
1) Determine the minimum (valley) inductor current
(IL(MIN)) under conditions when VIN is small, VOUT is
large, and load current is maximum. The minimum
inductor current is ILOAD minus half the ripple cur-
rent (Figure 4).
2) The sense resistor determines the achievable cur-
rent-limit accuracy. There is a trade-off between cur-
rent-limit accuracy and sense-resistor power
dissipation. Most applications employ a current-
sense voltage of 50mV to 100mV. Choose a sense
resistor such that:
RSENSE = Current-Limit Threshold Voltage / IL(MIN)
Extremely cost-sensitive applications that do not
require high-accuracy current sensing can use the on-
resistance of the low-side MOSFET switch in place of
the sense resistor by connecting CS_ to LX_ (Figure
7a). Use the worst-case value for RDS(ON) from the
MOSFET data sheet, and add a margin of 0.5%/°C for
the rise in RDS(ON) with temperature. Use the calculat-
ed RDS(ON) and IL(MIN) from step 1 above to determine
the current-limit threshold voltage. If the default 50mV
threshold is unacceptable, set the threshold value as in
step 2 above.
In all cases, ensure an acceptable current limit consid-
ering current-sense and resistor accuracies.
DUTY K (V + 0.075V) V
K (V + 0.075V) V + min off - time
OUT IN
OUT OUT
=
VIL
C DUTY V V
SAG LOAD MAX
FINMIN OUT
=×
××
()
()
()
()
∆
-
2
2
L 1.8V (15V - 1 8V)
15V 345kHz 0.25 8A 2.3 H =×××
=µ
.
L = V(V- V)
Vf LIR I
OUT IN OUT
IN LOAD(MAX)
×× ×
LX
DL
CS
MAX8743
LX
DL
CS
MAX8743
b)
a)
Figure 7. Current-Sense Configurations
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
______________________________________________________________________________________ 19
Output Capacitor Selection
The output filter capacitor must have low enough ESR to
meet output ripple and load-transient requirements, yet
have high enough ESR to satisfy stability requirements.
Also, the capacitance value must be high enough to
absorb the inductor energy going from a full-load to no-
load condition without tripping the OVP circuit.
For CPU core voltage converters and other applica-
tions where the output is subject to violent load tran-
sients, the output capacitor’s size depends on how
much ESR is needed to prevent the output from dip-
ping too low under a load transient. Ignoring the sag
due to finite capacitance:
In non-CPU applications, the output capacitor’s size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple:
The actual microfarad capacitance value required
relates to the physical size needed to achieve low ESR,
as well as to the chemistry of the capacitor technology.
Thus, the capacitor is usually selected by ESR and volt-
age rating rather than by capacitance value (this is true
of tantalums, OS-CONs®, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually
determined by the capacity needed to prevent VSAG
and VSOAR from causing problems during load tran-
sients. Also, the capacitance must be great enough to
prevent the inductor’s stored energy from launching the
output above the overvoltage protection threshold.
Generally, once enough capacitance is added to meet
the overshoot requirement, undershoot at the rising
load edge is no longer a problem (see the VSAG and
VSOAR equations in the Transient Response section).
Output Capacitor Stability
Considerations
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The point of instability
is given by the following equation:
where:
For a typical 300kHz application, the ESR zero frequen-
cy must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use
at the time of publication have typical ESR zero fre-
quencies of 15kHz. In the design example used for
inductor selection, the ESR needed to support 20mVP-P
ripple is 20mV/2A = 10mΩ. Three 470µF/6V Kemet
T510 low-ESR tantalum capacitors in parallel provide
10mΩ(max) ESR. Their typical combined ESR results in
a zero at 11.3kHz, well within the bounds of stability.
Do not put high-value ceramic capacitors directly
across the outputs without taking precautions to ensure
stability. Large ceramic capacitors can have a high-
ESR zero frequency and cause erratic, unstable opera-
tion. However, it is easy to add enough series
resistance by placing the capacitors a couple of inches
downstream from the inductor and connecting OUT_ or
the FB_ divider close to the inductor.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedback-
loop instability.
fRC
ESR ESR F
=×× ×
1
2π
ff
ESR SW
≤π
RV
LIR I
ESR PP
LOAD MAX
≤×−
()
RV
I
ESR DIP
LOAD MAX
≤
()
OS-CON is a registered trademark of Sanyo Electric Co., Ltd.
TON SETTING
SIDE 1
FREQUENCY
(kHz)
SIDE 1
K-FACTOR
(µs)
SIDE 2
FREQUENCY
(kHz)
SIDE 2
K-FACTOR
(µs)
APPROXIMATE
K-FACTOR
ERROR (%)
VCC 235 4.24 170 5.81 ±10
FLOAT 345 2.96 255 4.03 ±10
REF 485 2.08 355 2.81 ±12.5
AGND 620 1.63 460 2.18 ±12.5
Table 4. Frequency Selection Guidelines
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
20 ______________________________________________________________________________________
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there is not enough volt-
age ramp in the output voltage signal. This “fools” the
error comparator into triggering a new cycle immedi-
ately after the 400ns minimum off-time period has
expired. Double-pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it may indicate the possible presence of loop
instability, which is caused by insufficient ESR.
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvolt-
age protection latch or cause the output voltage to fall
below the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (refer to the
MAX8743 EV kit manual) and carefully observe the out-
put-voltage-ripple envelope for overshoot and ringing. It
helps to simultaneously monitor the inductor current with
an AC current probe. Do not allow more than one cycle of
ringing after the initial step-response under- or overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or OS-
CON) are preferred due to their resistance to power-up
surge currents:
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>5A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
For maximum efficiency, choose a high-side MOSFET
(Q1) that has conduction losses equal to the switching
losses at the optimum battery voltage (15V). Ensure
that the conduction losses at the minimum input volt-
age do not exceed the package thermal limits or violate
the overall thermal budget. Ensure that conduction
losses plus switching losses at the maximum input
voltage do not exceed the package ratings or violate
the overall thermal budget.
Choose a low-side MOSFET (Q2) that has the lowest
possible RDS(ON), comes in a moderate to small pack-
age (i.e., SO-8), and is reasonably priced. Ensure that
the MAX8743 DL gate driver can drive Q2; in other
words, check that the gate is not pulled up by the high-
side switch turning on due to parasitic drain-to-gate
capacitance, causing cross-conduction problems.
Switching losses are not an issue for the low-side
MOSFET since it is a zero-voltage switched device
when used in the buck topology.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty cycle
extremes. For the high-side MOSFET, the worst-case-
power dissipation (PD) due to resistance occurs at min-
imum battery voltage:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power-dissipation limits often limits how small the
MOSFET can be. Again, the optimum occurs when the
switching (AC) losses equal the conduction (RDS(ON))
losses. High-side switching losses do not usually
become an issue until the input is greater than approxi-
mately 15V.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV2f switching-loss equation. If the high-side MOSFET
chosen for adequate RDS(ON) at low battery voltages
becomes extraordinarily hot when subjected to
VIN(MAX), reconsider the choice of MOSFET.
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The
following switching-loss calculation provides only a
very rough estimate and is no substitute for bench eval-
uation, preferably including a verification using a ther-
mocouple mounted on Q1:
where CRSS is the reverse transfer capacitance of Q1,
and IGATE is the peak gate-drive source/sink current
(1A typ).
For the low-side MOSFET, Q2, the worst-case power
dissipation always occurs at maximum battery voltage:
PD(Q2) 1 - V
V I R
OUT
IN MAX LOAD2DS ON
=
×
() ()
PD(Q1 switching) CV fI
I
RSS IN(MAX)2LOAD
GATE
=×××
PD(Q1 resistance) V
VI R
OUT
IN MIN LOAD2DS ON
=
×
() ()
I I VV-V
V
RMS LOAD
OUT IN OUT
IN
=
()
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
______________________________________________________________________________________ 21
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
ILOAD(MAX) but are not high enough to exceed the cur-
rent limit. To protect against this possibility, “overde-
sign” the circuit to tolerate:
ILOAD = ILIMIT(HIGH) + (LIR / 2) ✕ILOAD(MAX)
where ILIMIT(HIGH) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. If short-circuit
protection without overload protection is adequate,
enable overvoltage protection, and use ILOAD(MAX) to
calculate component stresses.
Choose a Schottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency is not critical.
Applications Information
Dropout Performance
The output voltage adjust range for continuous-conduc-
tion operation is restricted by the nonadjustable 500ns
(max) minimum off-time one-shot. For best dropout per-
formance, use the slower on-time settings. When work-
ing with low input voltages, the duty-cycle limit must be
calculated using the worst-case values for on- and off-
times. Manufacturing tolerances and internal propaga-
tion delays introduce an error to the TON K-factor. This
error is greater at higher frequencies (Table 4). Also,
keep in mind that transient-response performance of
buck regulators operating close to dropout is poor, and
bulk output capacitance must often be added (see the
VSAG equation in the Design Procedure section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (∆IDOWN)
as much as it ramps up during the on-time (∆IUP). The
ratio h = ∆IUP / ∆IDOWN is an indicator of ability to slew
the inductor current higher in response to increased
load and must always be greater than 1. As h ap-
proaches 1, the absolute minimum dropout point, the
inductor current is less able to increase during each
switching cycle, and VSAG greatly increases unless
additional output capacitance is used.
A reasonable minimum value for h is 1.5, but this may
be adjusted up or down to allow trade-offs between
VSAG, output capacitance, and minimum operating
voltage. For a given value of h, calculate the minimum
operating voltage as follows:
VIN(MIN) = [(VOUT + VDROP1) / {1 - (tOFF(MIN) ✕h / K)}]
+ VDROP2 - VDROP1
where VDROP1 and VDROP2 are the parasitic voltage
drops in the discharge and charge paths (see the On-
Time One-Shot (TON) section), tOFF(MIN) is from the
Electrical Characteristics, and K is taken from Table 4.
The absolute minimum input voltage is calculated with
h = 1.
If the calculated VIN(MIN) is greater than the required
minimum input voltage, reduce the operating frequency
or add output capacitance to obtain an acceptable
VSAG. If operation near dropout is anticipated, calcu-
late VSAG to ensure adequate transient response.
Dropout Design Example:
VOUT = 1.8V
fSW = 600kHz
K = 1.63µs, worst-case K = 1.4175µs
tOFF(MIN) = 500ns
VDROP1 = VDROP2 = 100mV
h = 1.5
VIN(MIN) = (1.8V + 0.1V) / [1 - (0.5µs ✕1.5) / 1.4175µs]
+ 0.1V - 0.1V = 3.8V
Calculating again with h = 1 gives an absolute limit of
dropout:
VIN(MIN) = (1.8V + 0.1V) / [1 - (0.5µs ✕1) / 1.4175µs]
+ 0.1V - 0.1V = 2.8V
Therefore, VIN must be greater than 2.8V, even with very
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 3.8V.
Fixed Output Voltages
The MAX8743’s Dual-Mode operation allows the selec-
tion of common voltages without requiring external
components (Figure 8). Connect FB1 to GND for a fixed
1.8V output or to VCC for a 1.5V output, or connect FB1
directly to OUT1 for a fixed 1V output.
Connect FB2 to GND for a fixed 2.5V output or to OUT2
for a fixed 1V output.
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
22 ______________________________________________________________________________________
Setting VOUT_ with a Resistor-Divider
The output voltage can be adjusted from 1V to 5.5V
with a resistor-divider network (Figure 9). The equation
for adjusting the output voltage is:
where VFB_ is 1.0V and R2 is approximately 10kΩ.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switch-
ing losses and clean, stable operation. This is especial-
ly true for dual converters, where one channel can
affect the other. The switching power stages require
particular attention (Figure 10). Refer to the MAX1845
evaluation kit data sheet for a specific layout example.
Use a four-layer board. Use the top side for power com-
ponents and the bottom side for the IC and the sensitive
ground components. Use the two middle layers as
ground planes, with interconnections between the top
and bottom layers as needed. If possible, mount all of
the power components on the top side of the board,
with connecting terminals flush against one another.
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation. Short power traces and load con-
nections are essential for high efficiency. Using thick
copper PC boards (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PC board
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mil-
liohm of excess trace resistance causes a measurable
efficiency penalty.
V V1
R1
R2
OUT_ FB_
=+
DL_
GND
OUT_
CS_
DH_
FB_
VBATT
VOUT
R1
R2
MAX8743
Figure 9. Setting VOUT with a Resistor-Divider
AGND PLANE
AGND PLANE
PGND PLANE
VIA TO OUT1 VIA TO PGND PLANE AND IC GND
VIA TO CS1
NOTCH
VIN
USE AGND PLANE TO:
- BYPASS VCC AND REF
- TERMINATE EXTERNAL FB, ILIM,
OVP DIVIDERS, IF USED
- PIN-STRAP CONTROL
INPUTS
USE PGND PLANE TO:
- BYPASS VDD
- CONNECT IC GROUND
TO TOP-SIDE STAR GROUND
VIA TO TOP-SIDE
GROUND
TOP-SIDE GROUND PLANE
L2
L1
C1 C2
Q1
Q2
Q3
Q4
CIN CIN CIN
D2
D1
Figure 10. PC Board Layout Example
MAX8743
TO ERROR
AMP1
TO ERROR
AMP2
OUT2
FB2
0.1V
2V
0.1V
FB1
FIXED
2.5V
FIXED
1.5V
FIXED
1.8V
OUT1
Figure 8. Feedback MUX
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
______________________________________________________________________________________ 23
Place the current-sense resistors close to the top-side
star-ground point (where the IC ground connects to the
top-side ground plane) to minimize current-sensing
errors. Avoid additional current-sensing errors by using a
Kelvin connection from CS_ pins to the sense resistors.
The following guidelines are in order of importance:
•Keep the space between the ground connection of
the current-sense resistors short and near the via to
the IC ground pin.
•Minimize the resistance on the low-side path. The
low-side path starts at the ground of the low-side
FET, goes through the low-side FET, through the
inductor, through the output capacitor, and returns
to the ground of the low-side FET. Minimize the resis-
tance by keeping the components close together
and the traces short and wide.
•Minimize the resistance in the high-side path. This
path starts at VIN, goes through the high-side FET,
through the inductor, through the input capacitor,
and back to the input.
•When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
•Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from sensitive analog areas (REF,
ILIM_, FB_).
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (sense resistor, CIN-, COUT-, D1
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the synchronous-
rectifier MOSFETs, preferably on the back side to keep
CS_, GND, and the DL_ gate-drive line short and wide.
The DL_ gate trace must be short and wide, measur-
ing 10 squares to 20 squares (50mils to 100mils wide if
the MOSFET is 1in from the controller IC).
3) Group the gate-drive components (BST_ diode and
capacitor, VDD bypass capacitor) together near the
controller IC.
4) Make the DC-DC controller ground connections as
follows: Create a small analog ground plane (AGND)
near the IC. Connect this plane directly to GND
under the IC, and use this plane for the ground con-
nection for the REF and VCC bypass capacitors,
FB_, OVP, and ILIM_ dividers (if any). Do not con-
nect the AGND plane to any ground other than the
GND pin. Create another small ground island
(PGND), and use it for the VDD bypass capacitor,
placed very close to the IC. Connect the PGND
plane directly to GND from the outside of the IC.
5) On the board’s top side (power planes), make a star
ground to minimize crosstalk between the two sides.
The top-side star ground is a star connection of the
input capacitors, side 1 low-side MOSFET, and side
2 low-side MOSFET. Keep the resistance low
between the star ground and the source of the low-
side MOSFETs for accurate current limit. Connect
the top-side star ground (used for MOSFET, input,
and output capacitors) to the small PGND island with
a short, wide connection (preferably just a via).
Minimize crosstalk between side 1 and side 2 by
directing their switching ground currents into the star
ground with a notch as shown in Figure 10. If multi-
ple layers are available (highly recommended), cre-
ate PGND1 and PGND2 islands on the layer just
below the top-side layer (refer to the MAX1845 EV kit
for an example) to act as an EMI shield. Connect
each of these individually to the star-ground via,
which connects the top side to the PGND plane. Add
one more solid ground plane under the IC to act as
an additional shield, and also connect that to the
star-ground via.
6) Connect the output power planes directly to the out-
put filter-capacitor positive and negative terminals
with multiple vias.
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
24 ______________________________________________________________________________________
Pin Configurations
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CS1
LX1
DH1
BST1
DL1
GND
OUT2
VCC
VDD
DL2
BST2
DH2
LX2
CS2
FB2
ILIM2
ON2
ON1
REF
UVP
OVP
PGOOD
SKIP
TON
V+
ILIM1
FB1
OUT1
QSOP
TOP VIEW
MAX8743EEI
BST1
DL1
PGND
AGND
DL2
BST2
VCC
VDD
N.C.
PGOOD
OVP
UVP
REF
ON1
N.C.
TON 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
OUT2
CS2
LX2
DH2
FB2
ILIM2
ON2
N.C.
V+
ILIM1
FB1
OUT1
CS1
LX1
N.C.
DH1
N.C.
THIN QFN
MAX8743ETX
N.C.
N.C.
SKIP
Chip Information
TRANSISTOR COUNT: 4795
PROCESS: BiCMOS
Ordering Information (continued)
PART TEMP RANGE PIN-PACKAGE
MAX8743ETX -40°C to +85°C 36 Thin QFN
6mm x 6mm
MAX8743ETX+
-40°C to +85°C 36 Thin QFN
6mm x 6mm
+Denotes lead-free package.
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
______________________________________________________________________________________ 25
QSOP.EPS
F
1
1
21-0055
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
Note: The MAX8743EEI does not have a heat slug.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
26 ______________________________________________________________________________________
QFN THIN.EPS
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
MAX8743
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
27 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
