TDA16847GGEG - Infineon Technologies

ICs for Consumer Electronics

Controller for Switch Mode Power Supplies Supporting Low Power

Standby and Power Factor Correct ion

TDA 16846/TDA 16847

Data Sheet 2000-01-14

TDA 16846/TDA 16847

Revision History: Current Version: 2000-01-14

Previous Version: 1999-07-05

Page

(i n previous

Version)

Page

(in current

Version)

Subjects (major changes since last revision)

3 3, 28 P-DSO package added

Edition 01 .00

Published by Infineon Technologies AG i. Gr.,

St.-Martin-Strasse 53

D-81541 München

Atte nti on plea se !

The information herein is given to describe certain components a nd shall not be considered as warranted characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descripti on s and

c harts stated herein.

Infineon Technologiesis an appro v ed CEC C manufacturer.

Information

For furt her information on technology , delivery terms and conditions an d pric es please contact your nearest Infineo n Technologies O f fi c e

in Germany o r our Infine on Technologies Represe ntatives worldwide (see address list).

Warnings

Due to technical requi rement s components may cont ain dangerous sub stances. For information on the types in question please contact

your nea rest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Tech-

nologies, if a fail ure of such components c an reas onably be expected to caus e the failure of that lif e-support de v ice or syste m, or to af f ect

the safety or ef f ect i v en ess of tha t device or sys te m. Lif e su pp ort de vi ces or syst ems are in te nd ed t o be impl ant ed i n th e hu man body, or to

support and/ or maintain and sustai n and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other

persons may be enda ngered.

Data Sheet 3 2000-01-14

Controller for Switch Mode Power Supplies

Supporting Low Power Standby and Power

Factor Correction

TDA 16846

TDA 16847

Preliminary Data Bipolar IC

P-DSO-14-3

P-DIP-14-3

1 Overview

1.1 Features

• Line Current Consum pt ion with PFC

• Low Power Consumpt ion

• Stable and Adjustable Standby Frequenc y

• Very Low Start-up Current

• So ft- Sta r t fo r Qu ie t Sta rt-up

• Free usable Fault Compar ators

• Synchronization and Fixed Frequency Facility

• Over- and Undervoltage Lockout

• Switch Off at Mains Undervoltage

• Temporary high power circuit (only TDA 16847)

• Mains Volt age Dependent Fol d Back Point Corr ection

• Continuous Frequency Reduction with Decreasing Load

• Adjustable and Voltage Dependent Ringing Suppr essi on Time

1.2 Description

The TDA 16846 is optimized to control free running or fixed frequency flyback converters

with or without Power Factor Correction (Current Pump). To provide low power

consumption at light loads, this device reduces the switching frequency continuously

with load , towards an adj ust able mini mu m ( e. g. 20 kHz i n sta ndby m ode) . Addit ionally,

the start up current is very low. To avoid switching stresses of the power devices, the

power transistor is always switched on at minimum voltage. A special circuit is

imple mented to avo id jitter. The device has several pro tection function s: VCC ove r- a nd

underv oltage, m ain s under vol ta ge, curr ent limit ing and 2 free usable fault com par ato rs.

Regulation can be done by using the internal error amplif ier or an opto coupler feedback

(additiona l inp ut). The output driver is ideally suited for driving a pow er MOSFET, but it

can also be used for a bipolar transistor. Fixed frequency and synchronized operation

are also po ssibl e.

Type Ordering Code Package

TDA 16846 Q67000-A9377 P-DIP-14-3

TDA 16847 Q67000-A9378 P-DIP-14-3

TDA 16846G Q67006-A9430 P-DSO-14-3

TDA 16847G Q67006-A9412 P-DSO-14-3

TDA 16 846

TDA 16847

Data Sheet 4 2000-01-14

The TDA 16846 is suited for TV-, VCR- sets and SAT receivers. It also can be good used

in PC monitors.

T he TDA 16847 is i dent ical with TDA 16846 but has an additional power meas urement

outp ut (pin 8) which can be used fo r a Temporary High Power Circui t.

Figure 1 Pin Configuration (top vie w)

1.3 Pi n Definitions and Functions

Pin Symbol Function

1 OTC Off T ime Circuit

2 PCS Primary Current Simulation

3 RZI Regulation and Zer o Crossing In put

4 SRC Soft-Start and Regulat ion Capac itor

5 OC I Opto Coupler Input

6 FC2 Fault Compara tor 2

7 SYN Synchronization Input

8 N. C./P MO Not Connec ted (TDA 1684 6)/P MO (TDA 16847)

9 REF Referenc e Voltage and Current

10 FC1 Fault Comparator 1

11 PVC Primary Voltage Chec k

12 GND Ground

13 OUT Output

14 VCC S upply Voltage

OTC

PCS

RZI

SRC

OCI

FC2

SYN N.C./PMO

REF

FC1

PVC

GND

OUT

AEP02647

VCC

TDA 16 846

TDA 16847

Data Sheet 5 2000-01-14

1.4 Sh or t Des cr ip ti o n of the P in Fu nc ti o n s

Pin Function

1 A parallel RC-circ uit betwee n this pin and ground determ ines the ringing

suppression t ime and the standby -frequency.

2 A capaci tor between this pin and ground and a resistor between this pin and

the positive terminal of the primary elcap quantifies t he max. possible output

power of the SMPS.

3 This is the input of the error amplifier and the zero crossing input. The output

of a voltage divider between the control windi ng and gro und is connect ed to

this input . If the pulses at pin 3 exceed a 5 V threshold, the control voltage at

pin 4 is lowered.

4 This is the pin for the control voltage. A capacitor has to be connect ed

between this pin and ground. The val ue of this capa citor determines t he

duration of the softstart and the spe ed of the control .

5 If an opto coupler for the control is used, it’s outp ut has to be connect ed

between this pin and ground. The vol tage divider at pin 3 has then to be

changed, so that the puls es at pin 3 are below 5 V.

6 Fault comparator 2: If a voltage > 1.2 V is applied to this pin, the SMPS stops.

7 If fixed frequency mode is wante d, a parallel RC circuit has to be connect ed

between this pin and ground. The RC- val ue determ in es the freque ncy. If

synchronized mode is wanted, sync pulses have to be fed into this pin.

8 Not connect ed (TDA 16 846) . / This is the powe r measure men t output of the

Tempora ry High Power Circu it. A capacitor and a RC-circuit has to be

connecte d between t his pin and ground (TD A 16847) .

9 Output for reference voltage (5 V). With a resistor between this pin and ground

the fault comparator 2 (pin 6) is enabl ed.

10 Fault comparato r 1: If a voltage > 1 V is applied to this pin, the SMPS stops.

11 This is the input of the primary voltage check. The voltage at the anode of the

primary elcap has to be fed to this pin via a volt age divide r. If the voltage of

this pin falls below 1 V, the SMPS is switched off. A second function of this pin

is the primary voltage dependent fold back point correction (only active in free

running mode).

12 Common gr ound.

13 Outpu t signal. This pin has to be connect ed acr oss a serial resi stor with the

gate of the power transistor.

14 Connection for supply voltage and st artup capaci tor. After startup the supply

voltage is produced by the control winding of the transf ormer and rectified by

an external diode.

TDA 16 846

TDA 16847

Data Sheet 6 2000-01-14

1.5 Block Diagrams

Figure 2 TDA 16846

AEB02648

5 V

30 kΩ

75 k

Ω

15 k

Ω

Control Voltage

KSY

PVA

1.5 V

Fold Back Point Correction

1 V

Voltage

Check

1.2 V

Off Time

Comparator

2 V

Limit G1

3.5 V

Error

Amplifier

5 V

D3 Control Voltage

Buffer for

5 V

Comparator

Overvoltage

20 kΩ

< 25 mV

1.5 V

ED1

16 V

Comparator

On Time

Startup

ED2

Error-

Flipflop

On Time

Flipflop

Voltage

Comparator

15/8 V

Zero Crossing

Signal

Output

Driver

Primary

FC1

1 V

SYN

OTC

RZI 3

SRC 5

OCI

PCS 2

GND 12

FC1

13 OUT

6FC2

REF

N.C.

PVC

x 1/3

Diode Supply

The input with the lower voltage becomes operative

FC2

CS1

RSTC/RSTF

3.5 V

TDA 16 846

TDA 16847

Data Sheet 7 2000-01-14

Figure 3 TDA 16847

AEB02737

5 V

30 kΩ

75 kΩ

15 kΩ

Control Voltage

KSY

PVA

1.5 V

Fold Back Point Correction

1 V

Voltage

Check

1.2 V

Off Time

Comparator

2 V

Limit G1

3.5 V

+D2

Error

Amplifier

5 V

D3 Control Voltage

Buffer for

5 V

Comparator

Overvoltage

20 kΩ

< 25 mV

1.5 V

ED1

16 V

Comparator

On Time

Startup

ED2

Error-

Flipflop

On Time

Flipflop

Supply Voltage

Comparator

15/8 V

Crossing

Signal

Output

Driver

Primary

FC1

1 V

SYN

OTC

RZI 3

SRC 5

OCI

PCS 2

GND 12

FC1

13 OUT

6FC2

REF

PMO

PVC

x 1/3

Diode

The input with the lower voltage becomes operative

FC2

CS1

RSTC/RSTF

3.5 V

Zero

Flipflop

Discharge Time

TDA 16 846

TDA 16847

Data Sheet 8 2000-01-14

2 Functional Desc ript io n

Start Up Behaviour (Pin 14)

When power is applied to the chip and the voltage V14 at Pin 14 (VCC) is less than the

upper threshold (VON) of the Supply Voltage Comparator (SVC), input current I14 will be

less than 100 µA. The chip is not active and driver output (Pin 13) and control output

(Pin 4) will be actively held low. When V14 exceeds the upper SVC thresho ld (VON) the

chip starts working and I14 increases. When V14 falls below the lower SVC threshold

(VOFF) the chip starts again at his initial condition. Figure 4 shows the start-up circuit and

Figure 5 shows t he voltage V14 during start up. Charging of C14 is done by resi stor R2 of

the “P rimary Curren t Simulation” (see lat er) and the internal di ode D1, so no additional

start up resistor is needed. The capacitor C14 delivers the supply current until the

auxiliary winding of the tra nsformer supplies the chip with current through the external

diode D14.

It is recom me nded t o sw itch a sm al l RF snub ber cap a citor of e.g. 100 nF para llel to the

electrolytic capacitor at pin 14 as shown in the application circuits in Fi gures 15, 16, and

17.

Figure 4 Startup Circuit

AES02649

SVC

TDA 16846

PCS

Out

D14

TDA 16 846

TDA 16847

Data Sheet 9 2000-01-14

Figure 5 Startup Voltage Diagram

Primary Current Simulation PCS (Pin 2) / Current Limiting

A voltage proportional to the c urrent of the power transistor is generated at Pin 2 by the

RC-combination R2, C2 (Figure 4). The voltage at Pin 2 is forced to 1.5 V when the

power transistor is switched off and during its switch on time C2 is charged by R2 from

the rectified mains. The relation of V2 and the current in the power transistor (Iprimary) is

Lprimary: Primary inductance of the transforme r

The vol t ag e V2 is applied to one input of the On Time Comparator ONTC (see Figure 2).

The other input is the control voltage. If V2 exceeds the control voltage, the driver

switche s off (c urrent limiting) . The maxi mum val ue of the c ontrol voltage is t he interna l

reference voltage 5 V, so the maxi mum current in the power transi stor (IMprimary) is

The control voltage can be reduced by either the Error Amplifier EA (current mode

regulation), or by an opto coupler at Pin 5 (regulation with opto coupler isolation) or by

the voltage V11 at Pin 11 (Fol d Back Point Correct ion).

AED02650

Startup Operation

max

Off

V21,5 V Lprimary Iprimary

R2C2

--------------------------------+=

IMprimary 3,5 V R2

×C2

Lprimary

--------------------------------------=

TDA 16 846

TDA 16847

Data Sheet 10 2000-01-14

F old Back Point Correction PVC (Pin 11)

V11 is d evi ated by a voltage divider from the recti fied m ai ns and reduces t he limi t of t he

possible current maximum in the power transistor if the mains voltage increases. I.e. this

limit is independent of the mains (only active in free running mode). The maximum

current (IMprimary) depending on the voltage V11 at Pin 11 is

Off-T ime C i r cuit OTC (Pin 1)

Figure 6 shows the Off-Time Circuit which determines the load dependent frequency

course. When the driver switches of f (Figure 7) the capacitor C1 is charged by current I1

(appr ox. 1 m A) until the capacitor ’s voltage reaches 3. 5 V . The charge time TC1 is

F or p roper operation of the special internal ant i jitter ci rcu it, TC 1 should have the sam e

value as the resonance time “TR” of the power circuit (Figure 7). After charging C1 up to

3.5 V the current source is disconnected and C1 is discharged by resistor R1. The voltage

V1 at Pin 1 is applied to the Off-Time Comparator (OFTC). The other input of OFTC is

the con trol voltage. The value of the control volt age at the in put of OFTC is limited to a

mini mum of 2 V (for stabl e frequency at very light load). The On-Tim e Flip Flop (ONTF)

is set , if the output of OFTC is high 1) and the voltage V3 at Pin 3 fal ls below 25 mV (zero

crossing signal is high). This ensures switching on of the power transistor at minimum

voltage . If no zero crossing signal is coming i nto pin 3, the pow er transistor is switch ed

on after an additional delay until V1 falls below 1.5 V (see Figure 6, OFTCD). As lo ng as

V1 is higher than the limited control voltage, ONTF is disabled to suppress wrong zero

crossings of V3, due to parasitic oscillations from the transformer after switch-off. The

discharge time of C1 is a function of the cont rol vol tage.

1) i.e. V1 is less than the limited control voltage.

If the control voltage is below 2 V (at low output power) the “off-time” is maximum and

constant

Contr o l Voltage Out put Power Off-time TD1

1.5 - 2 V Low Constant (TD1MAX.), const . freque ncy st and by

2 - 3.5 V Medium Decreasing

3.5 - 5 V High Free running, switch-on at first minimum

IMprimary 4V V11 3⁄–()R2C2

××

Lprimary

------------------------------------------------------------=

TC1 C11,5 V×

1mA

-------------------------≈

TD1max 0,47 R1

×C1

×≈

TDA 16 846

TDA 16847

Data Sheet 11 2000-01-14

Figure 6 Off-Time-Circuit

AES02651

OFTC

ED3

Limit

2 V

Control Voltage

ED2

2 V

ONTF &

Output

Driver

From SYNC

From ONTC From UVLO

RSTC

RQRinging Suppression Time

ED1

RSTC

Zero Crossing Signal

3.5 V

InternalExternal

1OTC

From Error FF

RZI 3

OFTCD

1.5 V

TDA 16 846

TDA 16847

Data Sheet 12 2000-01-14

Figure 7 Pulse Diagram of Off-Time-Circuit

Figure 8 shows the converters swi tch ing frequency as a func tion of the output power .

Figure 8 Load Dependant Frequency Course

AED02652

0 V

2 V

3.5 V

Drain

Trans.

Power

D1max

AED02653

OUT

Conventional

Free Running

TDA 16846

e.g. 20 kHz

TDA 16 846

TDA 16847

Data Sheet 13 2000-01-14

Error Amplifier EA / Soft-Start (Pin 3, Pin 4)

Figure 9 shows the simplified Error Amplifier circuit. The positive input of the Error

Amplifier (EA) is the reference voltage 5 V. The negative input is the pulsed output

voltage from the auxiliary winding, divided by R31 and R32. The capacitor C3 is

dimensioned only for delaying zero crossings and smoothi ng the first spike after switch-

off. Smoothing of the regul ation volt age i s done wi th the sof t star t capacitor C4 at Pin 4.

During start up C4 is charged with a current of approx. 2 µA (Soft Start). Figure 10 shows

the voltage diagrams of the Error Amplifier circuit.

Figure 9 Error Amplif ier

Figure 10 Regu lation Pulse Diagram

AES02654

Amplifier

5 V Down

Reg

InternalExternal

RZI

SRC

Error

AED02655

Ref

Down

TDA 16 846

TDA 16847

Data Sheet 14 2000-01-14

Fixed Frequency and Synchronizat ion Circuit SYN (Pin 7)

Figure 11 shows the Fixed Frequency and Synchronization Circuit. The circuit is

disa ble d w hen Pin 7 is not c onnect ed. With R7 and C7 at Pin 7 the circuit is working. C7

is charged fast by approx. 1 mA and discharged slowly by R7 (Figure 11). The power

transistor is switched on at beginning of the charge phase. The switching frequen cy is

(char ge time igno red)

When the oscillator circuit is working the Fold Back Point Correction is disabled (not

necessary in fixed frequency mode). “Swit ch on” is onl y possible when a “zero crossing”

has occurred at Pin 3, otherwise “switch-on” will be delayed (Figure 12).

Figure 11 Synchronization and Fixed Frequency Circuit

f1,18

R7C7

--------------

≈

AES02656

15 k

Ω

75 k

Ω

5 V

R C

SYN 7

Logic

OUT

RZI

3 Zero Crossing Signal

External Internal

OP1OUT

OP1

Ω

TDA 16 846

TDA 16847

Data Sheet 15 2000-01-14

Figure 12 Pulse Diagram for Fixed Frequency Circuit

Synchronization mode is also possible. The sy nchronization frequency must be higher

than the oscill ator frequency.

Figure 13 Ext. Synchronization Circuit

AED02657

0.7 V

RZI(3)

1.5 V

3.6 V

Trans

AES02658

5 V 470 Ω

SFH 6136

39 k

Ω7

1 nF

InternalExternal

SYN

TDA 16 846

TDA 16847

Data Sheet 16 2000-01-14

3 Protectio n Funct i ons

The chip has several protection functions:

Current Limitin g

See “Primary Current Simulation PCS (Pin 2) / Current Limiting” and “Fold Back Point

Corre ction PVC (Pin 11)”.

Ove r- and Undervoltage Lockout OV/SVC (Pin 14)

When V14 at Pin 14 exce eds 16 V, e. g. due to a fault in the regulation circuit, the Error

Fl ip Fl op ERR is set and the output driver is shut-down. When V14 goes below the lower

SVC threshold, ERR i s reset and the driver output (Pin 13) and the soft-st art (Pin 4) are

shut down and actively held low.

Primary Voltage Check PVC (Pin 11)

When the voltage V11 at Pin 1 1 goes bel ow 1 V the Error Flip Flop (ERR) is set. E.g. a

voltage divider from the rectified mains at Pin 11 prevents from high input currents at too

low inp ut voltage.

Free Usable Fault Comparator FC1 (Pin 10)

When the voltage at Pin 1 0 exceeds 1 V, the Error Flip Flop (ERR) is set. This can be

used e. g. for mains overvol tage shutdown.

Free Usable Fault Comparator FC2 (Pin 6)

When the voltage at Pin 6 exceeds 1.2 V, the Error Flip Flop (ERR) is set. A resistor

between Pin 9 (REF) and ground is necessar y to enable this fault com parator .

Voltage dependent Ringing Suppr ession Time

During start-up and short-circuit operation, the output voltage of the converter is low and

parasitic zero crossings are applied for a longer time at Pin 3. Therefore the Ringing

Suppression Time TC1 (see “Off-Time Circuit OTC (Pin 1)”) is made longer with

factor 2.5 at low output voltage. To ensure start-up of the circuit, t he value of resistor R1

(Pin 1, Figure 6) must be higher than 20 kΩ.

TDA 16 846

TDA 16847

Data Sheet 17 2000-01-14

4 Temporary High Power Circuit FC2, PMO, REF

(Pin 6, 8, 9, TDA 16847)

Figure 14 shows the Tempor ary Hi gh Power Circui t:

Figure 14

The Temporary H igh Power Circu it (THPC) consi sts of two parts:

First a power measurement circuit is implemented: The capaci tor C8 at Pin 8 is charged

with a constant current I8 during the discharge time of the flyback transformer and

connected to ground t he oth er time. So the average of the saw to oth voltage V8 at Pin 8

is proportional to the converters output power (at constant output voltages). The charge

current I8 fo r C8 is dimensi oned by t he resist or R9 at P in 9:

I8=5V/R9

1.2 V

16FC2

REF

FC2

to Error Flipflop

Discharge Time

CS2

51 k

Ω

C C

PMO

10 M

Ω

Internal External

AEB02739

TDA 16 846

TDA 16847

Data Sheet 18 2000-01-14

Second a Hig h Power Shutdow n Compar ator (FC2) is implemente d: When the voltage

V6 at Pin 6 exceeds 1.2 V the Error Flip Flop (ERR) is set. The output voltage of the

power measurement circuit (Pin 8) is smoothed by R8/C6 and applied to the “high power

shutdown” input at Pi n 6. The relation betwe en this voltage V6 and the o utput powe r of

the conv erter P is approx imat ely:

V6≈(P×LSecondary ×5V)/(VOUT2×C8×R9)

LSecondary: The transformers secondary inductance

VOUT: T he con verters output volt age

So the time constant of R9/C8 for a certain high power shutdown level PSD is:

R9×C8≈(PSD ×LSecondary ×4.2)/VOUT2

The converters high power shutdown level can be dimensione d lower (by R9, C8) than

the current limit level (see “current limiting”). So because of the delay R8/C6, the

converter can deliver maximum output power (current limit level) for a certain time (e. g.

for power pulses like motor start current) and a power below the high power shutdown

level for unlimited time. This has the advantage that the thermal dimensioning of the

power devices is only needed for the lower power level. Once the voltage V6 exceeds

1.2 V there are no more charge or discharge actions a t Pin 8. The voltage V6 remains

high due t o the bias curr ent out o f HPC and th e conver ter rem ains switc hed-off. Reset

can be done by either plug-off the supply from the mains or with a high value resistor R6

(Figure 14). R6 causes a reset every view seconds. When Pin 9 is not connected or gets

too less current the tempor ary high power circuit is disabled.

TDA 16 846

TDA 16847

Data Sheet 19 2000-01-14

5 Electrical Characteristics

Note: Stresses above those listed here may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended per iods may affect

device reliabi lity.

5.1 Absolute Maximum Ratings

All voltages listed are referenced to ground (0 V, VSS) except where noted.

Parameter Symbol Limit Values Unit Remarks

min. max.

Supply Voltage at Pin 14 VCC –0.3 17 V –

Voltage at Pin 1, 4, 5, 6, 7, 9, 10 ––0.3 6 V –

Voltage at Pin 2, 8, 11 ––0.3 17 V –

Voltage at Pin 3

Cur ren t into Pin 3 RZI –10 6V

mA V3 < –0.3 V

Cur rent in to Pin 9 REF –1–mA –

Cur ren t into Pin 13 OUT –100 100 mA

mA V13 > VCC

V13 < 0 V

ESD Protection ––2 k V MIL STD 883C

met hod 3015.6,

100 pF, 1500 Ω

Storage Temper ature Tstg –65 125 °C–

Operating Junct io n Tempe rature TJ– 25 125 °C–

Thermal Re sistan ce

Junction-Ambient RthJA –110 K/W P-DIP-14-3

Soldering Tempera ture ––260 °C–

Soldering Time ––10 s –

TDA 16 846

TDA 16847

Data Sheet 20 2000-01-14

5.2 Characteristics

Unless otherwise stated, –25 °C<Tj< 125 °C, VCC =12V

Paramete r Symbol Limit Values Unit Test Condition

min. typ. max.

Start-Up Circuit

Supply current, OFF I14 –40 100 µA0 < VCC < V14 ON

Supply current, ON I14 –5 8 mA Output lo w

Turn-O N t h re sho ld V14 ON 14.5 15 15.5 V –

Turn-OFF threshold V14 OFF 7.5 8 8.5 V –

Primary Current Simulation PCS (Pin 2) / Current Limiting

Basic val ue V21.45 1.5 1.55 V I2 = 100 µA

Pe ak val ue V24.85 5 5.15 V V11 = 1.2 V

On-time –9.0 10.5 11.5 µsV11 = 1. 2 V,

C2= 220 pF,

I2 = 75 µA

Bias curren t Pin 2 –– 1.0 –0.3 –µA–

F old Back Point Correction PVC (Pin 11)

Pe ak val ue V23.8 4.1 4.3 V V11 = 4. 5 V

On-time –6.2 7.5 8.5 µsV11 = 4.5 V,

C2= 220 pF,

I2 = 75 µA

Bias curren t Pin 11 –– 1.0 –0.3 –µA–

Off-T ime C i r cuit OTC (Pin 1)

Cha rge cur ren t I10.9 1.1 1.4 mA V3 > 3 V

Cha rge cur ren t I10.35 0.5 0.65 mA V3 <2V

Pe ak val ue V13.38 3.5 3.62 V –

Basic val ue V11.92 2 2.08 V –

TDA 16 846

TDA 16847

Data Sheet 21 2000-01-14

T12 Charge time TC1 0.85 1.0 1.3 µsV3 > 3 V ,

C1= 680 pF,

R1 = 100 kΩ

T13 Charge time TC1 1.9 2.4 3.0 µsV3 < 2 V ,

C1= 680 pF,

R1 = 100 kΩ

Off-time TD1MAX. 65 72 80 µsC1 = 680 pF,

R1= 100 kΩ

Bias cur rent Pin 1 ––1.1 –0.4 –µA–

Zero crossing threshold

(Pin 3) –15 25 35 mV –

Delay to switch-on –280 350 480 ns –

Bias cur rent Pin 3 ––2–1.2 –µAV3 < 25 mV

Error Amplifier EA (Pin 3, Pin 4)

Input thre s hold (P in 3) VEATH 4.85 5 5.15 V –

Bias cur rent Pin 3 –––0.9 –µAV3 > 3 V

Soft-start charge cur rent

(Pin 4) ––2.5 –1.8 –1.2 µA–

Opto Coupler Input (Pin 5)

Input voltage range V50.3 –6V–

Pull high resist or to VREF R115 20 25 kΩ–

5.2 Characteristics (cont’d)

Unless othe rwi se stated, –25 °C<Tj<125°C, VCC =12V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

TDA 16 846

TDA 16847

Data Sheet 22 2000-01-14

Fixed Frequency and Synchronizat ion Circuit SYN (Pin 7)

Frequency –78 88 98 kHz C7 = 470 pF,

R7=20kΩ

Cha rge cur ren t I71.0 1.3 1.6 mA –

Up per thre sho ld V73.5 3.6 3.7 V –

L o wer thresho ld V71.43 1.5 1.57 V –

Cha rge time –0.4 0.55 0.75 µs–

Bias curren t Pin 7 ––2.4 –1.8 –1.1 µA–

Inpu t voltag e range V70.3 –6V–

Undervoltage Lockout SVC (Pin 14)

Threshold V14 OFF 7.5 8 8.5 V –

Ove rvoltage Lockout OV (Pin 14)

Threshold V14 OV 15.7 16.5 17 V –

Delta-OV-V14 ON –0.5 ––V–

Primary Voltage Check PVC (Pin 11)

Threshold V11 0.95 1 1.06 V –

Refere nce Voltage (Pin 9)

Voltage at Pin 9 V94.8 5 5.15 V I9= 100 µA

Cu rrent into Pin 9 I9–200 –0µAVEATH(Pin 3) –

V9<50mV

5.2 Characteristics (cont’d)

Unless otherwise stated, –25 °C<Tj< 125 °C, VCC =12V

Paramete r Symbol Limit Values Unit Test Condition

min. typ. max.

TDA 16 846

TDA 16847

Data Sheet 23 2000-01-14

Note: The listed chara cteristics are ensur ed o ver the operating range of the integrated

circuit. Typical characterist ics s pecify mean va lues e xpected ove r the produc tion

spread. If not otherwise speci fied, typical characterist ics apply at TA = 25 °C and

the given supply voltage.

Fault Comparator FC2 (Pin 6)

HPC Threshold V61.12 1.2 1.28 V –

Bias Current Pi n 6 ––1.0 –0.3 0.1 µA–

Fault Comparator FC1 (Pin 10)

Threshold V10 0.95 1 1.06 V –

Bias cur rent Pin 10 –0.48 0.9 1.2 µA–

Power Measurement Output PMO (Pin 8, only TDA 16847)

Charge current Pin 8 I8–110 –100 –90 µAI9=–100 µA

Output Driver OD (Pin 13)

Output voltage low state V13 low 1.1 1.8 2.4 V I13 = 100 mA

Output voltag e high state V13 high 9.2 10 11 V I13 = –100 mA

Output voltag e during low

supply volta ge V13 aclow 0.8 1.8 2.5 V I13 = –10 mA,

V14 increasing:

0 < V14 < V14 ON

V14 decreasing:

0<V14 <V14 OFF

Ri s e ti me –70 110 180 ns C13 = 10 nF,

V13 =2…8V

Fall time –30 50 80 ns C13 = 10 nF,

V13 =2…8V

5.2 Characteristics (cont’d)

Unless othe rwi se stated, –25 °C<Tj<125°C, VCC =12V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

TDA 16 846

TDA 16847

Data Sheet 24 2000-01-14

Figure 15 Circuit Diagram for Application with PFC

AES02659

10 nF 4

18 k

Ω

1 nF

3.9 M

Ω

1 M

Ω

560 pF

Ω

9.1 k

2 k

Ω

6, 10, 12

150 pF

56 k

Ω

1.5 nF

8N.C.

9.1 k

Ω

220 F

TR1

(AL = 190 nH) D41

MUR4100

52 Turns7 Turns

100 V

MUR120

9 Turns

D42

F470

16 V

MUR120

5 Turns

D43

8.5 V

470

2226

F1N4148

D26

13 7 9

Ω

MUR4100

220 pF

2 mH

10 nF

STTA506D

150

F/450 V

4.7 M

Ω

5.1 k

1 nF

D1-D4

4 x BYW 76

1 nF

RFI Filter

180-270 V

3.15 A

TDA 16846

IC1

54 Turns

4.7 nF

820

Ω

1 k

Ω

10 nF

1 nF

100 k

Ω

2.2 k60

Ω

500

Ω

100 k

IC 02

SFH 617 A-2

SPP (0.6 Ω)

N6055

C27

100 nF

TDA 16 846

TDA 16847

Data Sheet 25 2000-01-14

Figure 16 Circuit Diagr am for Standard Application

AES02660

10 nF 4

18 kΩ11

1 nF

3.9 MΩ

1 M

Ω

680 pF

Ω9.1 k

2 k

10Ω

6, 10, 12

150 pF

56 k

30 Ω

1.5 nF

8N.C.

9.1 kΩ

µ220 F

TR1

(AL = 190 nH) D41

MUR4100

52 Turns7 Turns

100 V

MUR120

9 Turns

D42

F470 µ

16 V

MUR120

5 Turns

D43

8.5 V

470

µ22

1N4148

D26

13 7 9

Ω

220 pF

150

F/385 V

4.7 MΩ

D1-D4

4 x 1N4007

1 nF

RFI Filter

180-270 V

3.15 A

TDA 16846

IC1

77 Turns

D10

BA1 59

D11

N6055

SPP ( Ω1.4 )

C27

100 nF

TDA 16 846

TDA 16847

Data Sheet 26 2000-01-14

Figure 17 Circuit Diagram for Application with Temporary High Power Circ uit

AES02738

10 nF 4

18 kΩ11

1 nF

3.9 MΩ

1 M

Ω

680 pF

Ω9.1 k

2 k

10Ω

10, 12

150 pF

56 k

30 Ω1.5 nF

9.1 kΩ

µ220 F

TR1

(AL = 190 nH) D41

MUR4100

52 Turns7 Turns

100 V

MUR120

9 Turns

D42

F470 µ

16 V

MUR120

5 Turns

D43

8.5 V

470

µ22

1N4148

Ω15

220 pF

150

F/385 V

4.7 MΩ

D1-D4

4 x 1N4007

1 nF

RFI Filter

180-270 V

3.15 A

TDA 16847

IC1

77 Turns

D10

BA 159

D11

N6055

SPP (

Ω

1.4 )

D26

51 kΩ

1 MΩ

100 pF

32 4.7 µF

C27

100 nF

TDA 16 846

TDA 16847

Data Sheet 27 2000-01-14

Package Outlines

P-DIP-14-3

(Plastic Dual In-line Package)

GPD05584

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book "Package Information". Dimensions in mm

TDA 16 846

TDA 16847

Data Sheet 28 2000-01-14

P-DSO-14-3

(Plastic Dual In-line Pack age)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book "Package Information". Dimensions in mm