LTC2382-16
1
238216fa
For more information www.linear.com/LTC2382-16
TYPICAL APPLICATION
FEATURES DESCRIPTION
16-Bit, 500ksps, Low Power
SAR ADC with Serial Interface
The LTC
®
2382-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2382-16 has a
±2.5V fully differential input range. The LTC2382-16
consumes only 6.5mW and achieves ±2LSB INL max, no
missing codes at 16-bits and 92dB SNR.
The LTC2382-16 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisy-chain mode. The fast 500ksps
throughput with no cycle latency makes the LTC2382-16
ideally suited for a wide variety of high speed applica tions.
An internal oscillator sets the conversion time, easing exter-
nal timing considerations. The LTC2382-16 automatically
powers down between conversions, lead ing to reduced
power dissipation that scales with the sampling rate.
The LTC2382-16 features a proprietary sampling archi-
tecture that enables the ADC to begin acquiring the next
sample during the current conversion. The resulting
extended acquisition time of 1.25µs allows the use of
extremely low power ADC drivers.
32k Point FFT fS = 500ksps, fIN = 20kHz
APPLICATIONS
n 500ksps Throughput Rate
n ±2LSB INL (Max)
n Guaranteed 16-Bit No Missing Codes
n Low Power: 6.5mW at 500ksps, 13µW at 1ksps
n 92dB SNR (Typ) at fIN = 20kHz
n Extended Acquisition Time of 1.25µs Allows Use of
Lower Power Drivers
n Guaranteed Operation to 125°C
n 2.5V Supply
n Fully Differential Input Range ±2.5V
n External 2.5V Reference Input
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n 16-Pin MSOP and 4mm × 3mm DFN Packages
n Medical Imaging
n High Speed Data Acquisition
n Portable or Compact Instrumentation
n Industrial Process Control
n Low Power Battery-Operated Instrumentation
n ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
FREQUENCY (kHz)
0 50 100 150 200 250
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
238216 TA02a
SNR = 92.2dB
THD = –106dB
SINAD = 92dB
SFDR = 107dB
LT6350
ANALOG INPUT
0V TO 2.5V
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
50Ω 100Ω
100Ω50Ω
3300pF
10µF 0.1µF
2.5V
REF GND
1.8V TO 5V
SAMPLE CLOCK
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
LTC2382-16
IN+VDD OVDD
IN–
2.5V
47µF
(X5R, 0805 SIZE)
238216 TA01
LTC2382-16
2
238216fa
For more information www.linear.com/LTC2382-16
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ...............................................2.8V
Supply Voltage (OVDD) ................................................6V
Reference Input (REF) .............................................. 2.8V
Analog Input Voltage (Note 3)
IN+, IN– ......................... (GND –0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3) ........................... (GND –0.3V) to (OVDD + 0.3V)
(Notes 1, 2)
16
15
14
13
12
11
10
9
17
GND
1
2
3
4
5
6
7
8
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
CHAIN
VDD
GND
IN+
IN–
GND
REF
REF
TOP VIEW
DE PACKAGE
16-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
CHAIN
VDD
GND
IN+
IN–
GND
REF
REF
16
15
14
13
12
11
10
9
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
TOP VIEW
MS PACKAGE
16-LEAD (4mm × 5mm) PLASTIC MSOP
TJMAX = 150°C, θJA = 110°C/W
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2382CMS-16#PBF LTC2382CMS-16#TRPBF 238216 16-Lead Plastic MSOP 0°C to 70°C
LTC2382IMS-16#PBF LTC2382IMS-16#TRPBF 238216 16-Lead Plastic MSOP –40°C to 85°C
LTC2382HMS-16#PBF LTC2382HMS-16#TRPBF 238216 16-Lead Plastic MSOP –40°C to 125°C
LTC2382CDE-16#PBF LTC2382CDE-16#TRPBF 23826 16-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2382IDE-16#PBF LTC2382IDE-16#TRPBF 23826 16-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel//. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Digital Output Voltage
(Note 3) ........................... (GND –0.3V) to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2382C ................................................ 0°C to 70°C
LTC2382I .............................................–40°C to 85°C
LTC2382H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
http://www.linear.com/product/LTC2382-16#orderinfo
LTC2382-16
3
238216fa
For more information www.linear.com/LTC2382-16
DYNAMIC ACCURACY
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 20kHz l88.5 92 dB
SNR Signal-to-Noise Ratio fIN = 20kHz l89 92 dB
THD Total Harmonic Distortion fIN = 20kHz, First 5 Harmonics l–106 –99 dB
SFDR Spurious Free Dynamic Range fIN = 20kHz 107 dB
–3dB Input Bandwidth 30 MHz
Aperture Delay 2 ns
Aperture Jitter 30 ps
Transient Response Full-Scale Step 250 ns
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8)
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+ Absolute Input Range (IN+) (Note 5) l–0.05 VREF V
VIN– Absolute Input Range (IN–) (Note 5) l–0.05 VREF V
VIN+ – VIN– Input Differential Voltage range VIN = VIN+ – VIN–l–VREF +VREF V
VCM Common-Mode Input Range lVREF/2–
0.05
VREF/2 VREF/2+
0.05
V
IIN Analog Input Leakage Current l±1 µA
CIN Analog Input Capacitance Sample Mode
Hold Mode
45
5
pF
pF
CMRR Input Common Mode Rejection Ratio 70 dB
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
CONVERTER CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l16 Bits
No Missing Codes l16 Bits
Transition Noise 0.6 LSBRMS
INL Integral Linearity Error (Note 6) l–2 ±0.9 2 LSB
DNL Differential Linearity Error l–1 ±0.4 1 LSB
BZE Bipolar Zero-Scale Error (Note 7) l–6 ±0.25 6 LSB
Bipolar Zero-Scale Error Drift 3 mLSB/°C
FSE Bipolar Full-Scale Error (Note 7) l–14 ±3 14 LSB
Bipolar Full-Scale Error Drift ±0.1 ppm/°C
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2382-16
4
238216fa
For more information www.linear.com/LTC2382-16
ADC TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l500 ksps
tCONV Conversion Time l1 1.5 µs
tACQ Acquisition Time tACQ = tCYC – tHOLD (Note 10) l1.25 µs
tHOLD Maximum Time Between Acquisitions l750 ns
tCYC Time Between Conversions l2 µs
tCNVH CNV High Time l20 ns
tBUSYLH CNV ↑ to BUSY Delay CL = 20pF (Note 11) l20 ns
tCNVL Minimum Low Time for CNV (Note 11) l200 ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
POWER REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l2.375 2.5 2.625 V
OVDD Supply Voltage 1.71 5.25 V
IDD Supply Current
Power Down Mode
Power Down Mode
500ksps Sample Rate
Conversion Done
Conversion Done (H-Grade)
l
l
l
2.6
0.5
0.5
3.3
40
110
mA
µA
µA
PDPower Dissipation
Power Down Mode
Power Down Mode
500ksps Sample Rate
Conversion Done
Conversion Done (H-Grade)
6.5
1.25
1.25
8.25
100
275
mW
µW
µW
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
REFERENCE INPUT
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Reference Voltage (Note 5) l2.4 2.6 V
IREF Load Current (Note 9) l495 µA
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l0.8 • OVDD V
VIL Low Level Input Voltage l0.2 • OVDD V
IIN Digital Input Current VIN = 0V to OVDD l–10 10 µA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage IO = –500 µA lOVDD – 0.2 V
VOL Low Level Output Voltage IO = 500 µA l0.2 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 µA
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = OVDD 10 mA
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2382-16
5
238216fa
For more information www.linear.com/LTC2382-16
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSCK SCK Period (Notes 11, 12) l10 ns
tSCKH SCK High Time l4 ns
tSCKL SCK Low Time l4 ns
tSSDISCK SDI Setup Time From SCK ↑(Note 11) l4 ns
tHSDISCK SDI Hold Time From SCK ↑(Note 11) l1 ns
tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l13.5 ns
tDSDO SDO Data Valid Delay from SCK ↑CL = 20pF (Note 11) l9.5 ns
tHSDO SDO Data Remains Valid Delay from SCK ↑CL = 20pF (Note 10) l1 ns
tDSDOBUSYL SDO Data Valid Delay from BUSY ↓ CL = 20pF (Note 10) l5 ns
tEN Bus Enable Time After RDL ↓(Note 11) l16 ns
tDIS Bus Relinquish Time After RDL ↑ (Note 11) l13 ns
tSSCKRDL SCK Setup Time from RDL/SDI ↓(Note 10) l1 ns
tHSCKRDL SCK Hold Time from RDL/SDI ↓(Note 10) l16 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 2.5V, fSMPL = 500kHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000
and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of
–FS or +FS untrimmed deviation from ideal first and last code transitions
and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±2.5V input with
a 2.5V reference voltage.
Note 9: fSMPL = 500kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
0.2*OVDD
50% 50%
238216 F01
0.2*OVDD
0.8*OVDD
0.2*OVDD
0.8*OVDD
tDELAY
tWIDTH
tDELAY
Figure 1. Voltage Levels for Timing Specifications
LTC2382-16
6
238216fa
For more information www.linear.com/LTC2382-16
TYPICAL PERFORMANCE CHARACTERISTICS
32k Point FFT fS = 500ksps,
fIN = 20kHz SNR, SINAD vs Input Frequency
THD, Harmonics
vs Input Frequency
SNR, SINAD vs Input level,
fIN = 20kHz SNR, SINAD vs Temperature THD, Harmonics vs Temperature
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code DC Histogram
OUTPUT CODE
–32768 –16384 0 16384 32768
–2.0
INL ERROR (LSB)
0.0
0.5
1.0
1.5
–0.5
–1.0
–1.5
2.0
238216 G01
OUTPUT CODE
–1.0
DNL ERROR (LSB)
0.5
0.0
–0.5
1.0
238216 G02
–32768 –16384 0 16384 32768
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 2.5V,
fSMPL = 500ksps, unless otherwise noted.
FREQUENCY (kHz)
0 50 100 150 200
250
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
238216 G04
SNR = 92.2dB
THD = –106dB
SINAD = 92dB
SFDR = 107dB
FREQUENCY (kHz)
SNR, SINAD (dBFS)
93
238216 G05
84
85
86
87
88
89
90
91
92
0 25 50 75 100 125 150 175 200
SNR
SINAD
FREQUENCY (kHz)
HARMONICS, THD (dBFS)
–80
238216 G06
–130
–125
–120
–115
–110
–105
–100
–95
–85
–90
0 25 50 75 100 125 150 175 200
THD 3RD
2ND
INPUT LEVEL (dB)
SNR, SINAD (dBFS)
93.0
238216 G07
91.0
91.5
92.0
92.5
–40 –30 –20 –10 0
SNR
SINAD
TEMPERATURE (ºC)
SNR, SINAD (dBFS)
94.00
238216 G08
91.00
91.50
92.00
92.50
93.00
93.50
–55 –35 –15 5 25 45 65 85 105 125
SNR
SINAD
TEMPERATURE (°C)
THD
2ND
3RD
–55 –35 –15 25 455 65 85 105 125
–120
HARMONICS, THD (dBFS)
–110
–115
–105
–100
238216 G09
CODE
–2 –1 0 1 2
0
COUNTS
1400000
1600000
1200000
1000000
800000
600000
400000
200000
1800000
238216 G03
LTC2382-16
7
238216fa
For more information www.linear.com/LTC2382-16
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Temperature Shutdown Current vs Temperature Supply Current vs Sampling Rate
INL/DNL vs Temperature Full-Scale Error vs Temperature Offset Error vs Temperature
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 2.5V,
fSMPL = 500ksps, unless otherwise noted.
TEMPERATURE (°C)
POWER-DOWN CURRENT (µA)
30
238216 G14
0
5
10
15
20
25
–55 –35 –15 5 25 45 65 85 105 125
IVDD + IOVDD + IREF
TEMPERATURE (°C)
INL/DNL ERROR (LSB)
1
238216 G10
–1
–0.5
0
0.5
–55 –35 25 45 65–15 5 85 105 125
MAX INL
MAX DNL
MIN DNL
MIN INL
TEMPERATURE (°C)
FULL-SCALE ERROR (LSB)
1
238216 G11
–1.5
–1.0
–0.5
0
0.5
–55 –35 25 45 65–15 5 85 105 125
–FS
+FS
TEMPERATURE (°C)
OFFSET ERROR (LSB)
0
238216 G12
–1
–0.75
–0.5
–0.25
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
POWER SUPPLY CURRENT (mA)
3
238216 G13
0
0.5
1
1.5
2
2.5
–55 –35 –15 5 25 45 65 85 105 125
IVDD
IREF
IOVDD
SAMPLING RATE (kHz)
0 100 200 300 400 500
0
POWER SUPPLY CURRENT (mA)
2.5
2
1
0.5
1.5
3
238216 G15
LTC2382-16
8
238216fa
For more information www.linear.com/LTC2382-16
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2382-16 operates in Normal Mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2382-16 operates in Chain Mode and the RDL/
SDI pin functions as SDI, the daisy chain serial data input.
VDD (Pin 2): 2.5V Digital Power Supply. The range of
VDD is 2.375V to 2.625V. Bypass VDD to GND with a 10µF
ceramic capacitor.
GND (Pins 3, 6, 10 and 16): Ground.
IN+, IN– (Pins 4, 5): Positive and Negative Differential
Analog Inputs.
REF (Pins 7, 8): Reference Input. The range of REF is 2.4V
to 2.6V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47µF ceramic capacitor
(X5R, 0805 size).
CNV (Pin 9): Convert Input. A rising edge on this input
initiates a new conversion. When the conversion is done,
the part powers down as long as CNV is held high. When
CNV is returned low, the part powers up in preparation
for the next conversion.
BUSY (Pin 11): BUSY indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished.
RDL/SDI (Pin 12): When CHAIN is low, the part is in Nor-
mal Mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input.
SCK (Pin 13): Serial Data Clock Input. When SDO is enabled,
the conversion result or daisy chain data from another ADC
is shifted out on the rising edges of this clock MSB first.
SDO (Pin 14): Serial Data Output. The conversion result or
daisy chain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
format.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1µF capacitor.
GND (Exposed Pad Pin 17 – DFN Package Only): Ground.
Exposed pad must be soldered directly to the ground plane.
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTIONS
REF = 2.5V
LTC2382-16
IN+
VDD = 2.5V
OVDD = 1.8V to 5V
IN–
CHAIN
CNV
GND
BUSY
SDO
SCK
RDL/SDI
CONTROL LOGIC
16-BIT SAMPLING ADC SPI
PORT
+
–
238216 BD01
LTC2382-16
9
238216fa
For more information www.linear.com/LTC2382-16
OVERVIEW
The LTC2382-16 is a low noise, low power, high speed 16-bit
successive approximation register (SAR) ADC. Operating
from a single 2.5V supply, the LTC2382-16 supports a
large ±2.5V fully differential input range, making it ideal
for high performance applications which require a wide
dynamic range. The LTC2382-16 achieves ±2LSB INL max,
no missing codes at 16-bits and 92dB SNR.
Fast 500ksps throughput with no cycle latency makes the
LTC2382-16 ideally suited for a wide variety of high speed
applications. An internal oscillator sets the conversion time,
easing external timing considerations. The LTC2382-16
dissipates only 6.5mW at 500ksps, while an auto pow-
er-down feature is provided to further reduce power
dissipation during inactive periods.
The LTC2382-16 features a proprietary sampling archi-
tecture that enables the ADC to begin acquiring the next
sample during the current conversion. The resulting
extended acquisition time of 1.25µs allows the use of
extremely low power ADC drivers.
APPLICATIONS INFORMATION
CONVERTER OPERATION
A rising edge on the CNV pin initiates a conversion. During
the conversion phase, the 16-bit CDAC is sequenced
through a successive approximation algorithm, effec-
tively comparing the sampled input with binary-weighted
fractions of the reference voltage (e.g. VREF/2, VREF/4 …
VREF/65536) using the differential comparator. At the end
of conversion, the CDAC output approximates the sampled
analog input. The ADC control logic then prepares the 16-
bit digital output code for serial transfer.
TRANSFER FUNCTION
The LTC2382-16 digitizes the full-scale voltage of 2 × REF
into 216 levels, resulting in an LSB size of 76µV with
REF = 2.5V. The ideal transfer function is shown in Figure 2.
The output data is in 2’s complement format.
ANALOG INPUT
The analog inputs of the LTC2382-16 are fully differential
in order to maximize the signal swing that can be digitized.
The analog inputs can be modeled by the equivalent circuit
TIMING DIAGRAM
POWER-UP
ACQUIRE
HOLD
POWER-DOWN
CONVERT
D15 D14 D13 D2 D1 D0
SDO
SCK
CNV
CHAIN, RDL/SDI = 0
BUSY
238216 TD01
Conversion Timing Using the Serial Interface
LTC2382-16
10
238216fa
For more information www.linear.com/LTC2382-16
Figure 2. LTC2382-16 Transfer Function
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
238216 F02
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FSR/2 – 1LSB–FSR/2
FSR = +FS – –FS
1LSB = FSR/65536
RON CIN
RON
REF
REF
CIN
IN+
IN–
BIAS
VOLTAGE
238216 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2382-16
shown in Figure 3. The diodes at the input provide ESD
protection. In the acquisition phase, each input sees ap-
proximately 45pF (CIN) from the sampling CDAC in series
with 40Ω (RON) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both in-
puts will be reduced by the common mode rejection of the
ADC. The inputs draw a current spike while charging the
CIN capacitors during acquisition. When the LTC2382-16
is not acquiring the input, the analog inputs draw only a
small leakage current.
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high im-
pedance inputs of the LTC2382-16 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when entering acquisition.
For best performance, a buffer amplifier should be used
to drive the analog inputs of the LTC2382-16. The ampli-
fier provides low output impedance which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the current spike the ADC inputs draw.
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimize noise. The simple 1-pole RC lowpass filter (LPF1)
shown in Figure 4 is sufficient for many applications.
Another filter network consisting of LPF2 and the 100Ω series
input resistors should be used between the buffer and ADC
inputs to both minimize the noise contribution of the buffer
and to help minimize disturbances reflected into the buffer
from sampling transients. Long RC time constants at the
analog inputs will slow down the settling of the analog inputs.
Therefore, LPF2 requires a wider bandwidth than LPF1. A
buffer amplifier with a low noise density must be selected to
minimize degradation of the SNR. With the 482kHz lowpass
filter shown in Figure 4, the LT6350 provides the full data
sheet performance of the LTC2382-16.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
APPLICATIONS INFORMATION
LT6350
ANALOG INPUT
0V TO 2.5V
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
50Ω
3300pF
6600pF
50Ω
500Ω
15Ω
3300pF
10µF 0.1µF
2.5V
REF GND
1.8V TO 5V
SAMPLE CLOCK
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
LTC2383-16
IN+VDD OVDD
IN–
2.5V
20µF
23816 TA01
100Ω
100Ω
LPF2
LPF1
BW = 482kHz
BW = 48kHz
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
SINGLE-ENDED-
INPUT SIGNAL
LTC2382-16
IN+
IN–
238216 F04
LT6350
Figure 4. Input Signal Chain
LTC2382-16
11
238216fa
For more information www.linear.com/LTC2382-16
APPLICATIONS INFORMATION
Single-to-Differential Conversion
For single-ended input signals, a single-ended to differential
conversion circuit must be used to produce a differential
signal at the inputs of the LTC2382-16. The LT6350 ADC
driver is recommended for performing single-ended-to-dif-
ferential conversions. The LT6350 is flexible and may be
configured to convert single-ended signals of various
amplitudes to the ±2.5V differential input range of the
LTC2382-16. The LT6350 is also available in H-grade to
complement the extended temperature operation of the
LTC2382-16 up to 125°C.
Figure 5 shows the LT6350 being used to convert a 0V
to 2.5V single-ended input signal. In this case, the first
amplifier is configured as a unity gain buffer and the sin-
gle-ended input signal directly drives the high-impedance
input of the amplifier. As shown in the FFT of Figure 5a,
the LT6350 drives the LTC2382-16 to full data sheet per-
formance without degrading the SNR or THD.
The LT6350 can also be used to buffer and convert
single-ended signals larger than the input range of the
LTC2382-16 in order to maximize the signal swing that
can be digitized. Figure 6 shows the LT6350 converting a
0V-5V single-ended input signal to the ±2.5V differential
input range of the LTC2382-16. In this case, the first am-
plifier in the LT6350 is configured as an inverting amplifier
stage, which acts to attenuate the input signal down to the
0V-2.5V input range of the LTC2382-16. In the inverting
amplifier configuration, the single-ended input signal
source no longer directly drives a high impedance input
of the first amplifier. The input impedance is instead set
by resistor RIN. RIN must be chosen carefully based on
the source impedance of the signal source. Higher values
of RIN tend to degrade both the noise and distortion of
the LT6350 and LTC2382-16 as a system. R1, R2 and R3
must be selected in relation to RIN to achieve the desired
attenuation and to maintain a balanced input impedance
in the first amplifier. Table 1 shows the resulting SNR
and THD for several values of RIN, R1, R2 and R3 in this
configuration. Figure 6a shows the resulting FFT when
using the LT6350 as shown in Figure 6.
The LT6350 can also be used to buffer and convert large,
true bipolar signals which swing below ground to the
±2.5V differential input range of the LTC2382-16. Figure
7 shows the LT6350 being used to convert a ±10V true
bipolar signal for use by the LTC2382-16. The input im-
pedance is again set by resistor RIN. Table 2 shows the
resulting SNR and THD for several values of RIN. Figure
7a shows the resulting FFT when using the LT6350 as
shown in Figure 7.
LT6350
VCM = VREF/2
2.5V to
0V
0V to
2.5V
0V to 2.5V
238216 F05
OUT1
RINT RINT
OUT2
8
4
5
2
1
+
–
+
––
+
FREQUENCY (kHz)
0 50 100 150 200 250
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
238216 F05a
SNR = 92.2dB
THD = –106dB
SINAD = 92dB
SFDR = 107dB
Figure 5. LT6350 Converting a 0V-2.5V Single-Ended Signal
to a ±2.5V Differential Input Signal
Figure 5a.32k Point FFT Plot for Circuit Shown in Figure 5
LTC2382-16
12
238216fa
For more information www.linear.com/LTC2382-16
APPLICATIONS INFORMATION
238216 F06
LT6350
R1 = 1k
R2 = 1k
R3 = 2k
R4 = 680Ω
VCM = VREF/2
VREF
75pF
150pF
0V to
2.5V
2.5V to
0V
0V to 5V
OUT1
RINT
10µF
RINT
RIN = 2k
OUT2
8
4
5
2
1
+
–
+
––
+
Figure 6. LT6350 Converting a 0V-5V Single-Ended Signal
to a ±2.5V Differential Input Signal
Figure 6a. 32k Point FFT Plot for Circuit Shown in Figure 6
238216 F07
LT6350
R1 = 1.24k
R2 = 1.24k
R3 = 10k
R4 = 1.1k
VCM = VREF/2
CM
0V to
2.5V
2.5V to
0V
±10V
OUT1
RINT RINT
RIN = 10k
OUT2
8
4
5
2
1
+
–
+
––
+
220pF
10µF
200pF
Table 1. SNR, THD vs RIN for 0-5V Single-Ended Input Signal
RIN
(Ω)
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
SNR
(dB)
THD
(dB)
2k 1k 1k 2k 680 92 –100
10k 5k 5k 10k 3.3k 91 –100
50k 25k 25k 50k 16.5k 91 –97
Figure 7. LT6350 Converting a ±10V Single-Ended Signal to
a ±2.5V Differential Input Signal
Figure 7a. 32k Point FFT Plot for Circuit Shown in Figure 7
FREQUENCY (kHz)
0 50 100 150 200 250
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
238216 F06a
SNR = 91.8dB
THD = –99.6dB
SINAD = 91.3dB
SFDR = 103dB
Table 2. SNR, THD vs RIN for ±10V Single-Ended Input Signal
RIN
(Ω)
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
SNR
(dB)
THD
(dB)
10k 1.24k 1.24k 10k 1.1k 92 –96
50k 6.19k 6.19k 50k 5.49k 91 –96
100k 12.4k 12.4k 100k 11k 91 –97
FREQUENCY (kHz)
0 50 100 150 200 250
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
238316 F07a
SNR = 91.9dB
THD = –96dB
SINAD = 91.3dB
SFDR = 97.2dB
ADC REFERENCE
The LTC2382-16 requires an external reference to define its
input range. A low noise, low temperature drift reference
is critical to achieving the full data sheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and high
accuracy, the LTC6652-2.5 is particularly well suited for
use with the LTC2382-16. The LTC6652-2.5 offers 0.05%
(max) initial accuracy and 5ppm/°C (max) temperature co-
efficient for high precision applications. The LTC6652-2.5
is fully specified over the H-grade temperature range and
complements the extended temperature operation of the
LTC2382-16 up to 125°C. We recommend bypassing the
LTC6652-2.5 with a 47µF ceramic capacitor (X5R, 0805
size) close to the REF pin. All performance curves shown
in this data sheet were obtained using the LTC6652-2.5.
LTC2382-16
13
238216fa
For more information www.linear.com/LTC2382-16
APPLICATIONS INFORMATION
The REF pin of the LTC2382-16 draws charge (QCONV)
from the 47µF bypass capacitor during each conversion
cycle. The reference replenishes this charge with a DC
current, IREF = QCONV/tCYC. The DC current draw of the
REF pin, IREF, depends on the sampling rate and output
code. If the LTC2382-16 is used to continuously sample
a signal at a constant rate, the LTC6652-2.5 will keep the
deviation of the reference voltage over the entire code
span to less than 0.5LSBs.
When idling, the REF pin on the LTC2382-16 draws only
a small leakage current (< 1µA). In applications where a
burst of samples is taken after idling for long periods as
shown in Figure 8, IREF quickly goes from approximately
0µA to a maximum of 495µA at 500ksps. This step in DC
current draw triggers a transient response in the reference
that must be considered since any deviation in the refer-
ence output voltage will affect the accuracy of the output
code. In applications where the transient response of the
reference is important, the fast settling LTC6655-2.5 refer-
ence is recommended. Inserting a 1Ω resistor between the
47µF bypass capacitor and reference output as shown in
Figure 9 helps to improve the transient settling time and
minimize the reference voltage deviation.
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2382-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Figure 10. 32k Point FFT of the LTC2382-16
FREQUENCY (kHz)
0 50 100 150 200 250
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
238216 F10
SNR = 92.2dB
THD = –106dB
SINAD = 92dB
SFDR = 107dB
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 10 shows that the LTC2382-16 achieves
a typical SINAD of 92dB at a 500kHz sampling rate with
a 20kHz input.
CNV
IDLE
PERIOD
IDLE
PERIOD
238216 F08
Figure 8. CNV Waveform Showing Burst Sampling
238216 F09
LTC2382-16
1Ω
47µF
LTC6655-2.5
VOUT_S
VOUT_F
Figure 9. LTC6655-2.5 Driving REF of LTC2382-16
LTC2382-16
14
238216fa
For more information www.linear.com/LTC2382-16
APPLICATIONS INFORMATION
SAMPLING RATE (kHz)
0 100 200 300 400 500
0
POWER SUPPLY CURRENT (mA)
2.5
2
1
0.5
1.5
3
238216 F11
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 10 shows
that the LTC2382-16 achieves a typical SNR of 92dB at a
500kHz sampling rate with a 20kHz input.
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency (fSM-
PL/2). THD is expressed as:
THD VVV V
V
N
=
++++
20 234
1
22
22
log…
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through Nth harmonics.
POWER CONSIDERATIONS
The LTC2382-16 provides two power supply pins: the
2.5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2382-16 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Power Supply Sequencing
The LTC2382-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2382-16
has a power-on-reset (POR) circuit that will reset the
LTC2382-16 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
reenters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 20µs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
Figure 11. Power Supply Current of the
LTC2382-16 vs Sampling Rate
TIMING AND CONTROL
CNV Timing
The LTC2382-16 conversion is controlled by CNV. A rising
edge on CNV will start a conversion. Once a conversion
has been initiated, it cannot be restarted until the conver-
sion is complete. For optimum performance, CNV should
be driven by a clean low jitter signal. Converter status is
indicated by the BUSY output which remains high while
the conversion is in progress. To ensure that no errors
occur in the digitized results, any additional transitions
on CNV should occur within 40ns from the start of the
conversion or after the conversion has been completed.
ACQUISITION
A proprietary sampling architecture allows the LTC2382-16
to begin acquiring the input signal for the next conversion
750ns after the start of the current conversion. This extends
the acquisition time to 1.25µs, easing settling requirements
and allowing the use of extremely low power ADC drivers.
(Refer to the Timing Diagram.)
Internal Conversion Clock
The LTC2382-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 1.5µs.
LTC2382-16
15
238216fa
For more information www.linear.com/LTC2382-16
APPLICATIONS INFORMATION
Auto Power-Down
The LTC2382-16 automatically powers down after a con-
version has been completed as long as CNV remains high.
During power-down, the data from the last conversion
can be clocked out. To minimize power dissipation during
power-down, disable SDO and turn off SCK. To power up
the part, bring CNV low at least 200ns (tCONVL) before the
initiation of the next conversion. The auto power-down
feature will reduce the power dissipation of the LTC2382-
16 as the sampling frequency is reduced. Since the time
required to power up the part does not change at lower
sample rates, the LTC2382-16 can remain powered-down
for a larger fraction of the conversion cycle (tCYC), there-
by reducing the average power dissipation which scales
linearly with sampling rate as shown in Figure 11.
DIGITAL INTERFACE
The LTC2382-16 has a serial digital interface. The flexible
OVDD supply allows the LTC2382-16 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
30MHz, a 500ksps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D15 remains valid till the first rising edge of SCK.
The serial interface on the LTC2382-16 is simple and
straightforward to use. The following sections describe the
operation of the LTC2382-16. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy-chained.
LTC2382-16
16
238216fa
For more information www.linear.com/LTC2382-16
APPLICATIONS INFORMATION
CNV
LTC2382-16
BUSY
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
SDO
SCK
238216 F12a
RDL/SDI
CHAIN
238216 F12
CONVERT CONVERT
POWER-DOWN POWER-UP
ACQUIRE
ACQUIRE
CNV
CHAIN = 0
BUSY
SCK
SDO
(RDL/SDI = 0)
tBUSYLH
tDSDOBUSYL
tSCK
tHSDO
tSCKH
tSCKL
tDSDO
tCONV
tHOLD tACQ
tACQ = tCYC –tHOLD
tCNVH
tCYC
tCNVL
D15 D14 D13 D1 D0
1 2 3 14 15 16
Figure 12. Using a Single LTC2382-16 in Normal Mode
Normal Mode, Single Device
When CHAIN = 0, the LTC2382-16 operates in Normal
mode. In Normal mode, RDL/SDI enables or disables the
serial data output pin SDO. If RDL/SDI is high, SDO is in
high-impedance. If RDL/SDI is low, SDO is driven.
Figure 12 shows a single LTC2382-16 operated in Normal
Mode with CHAIN and RDL/SDI tied to ground. With RDL/
SDI grounded, SDO is enabled and the MSB(D15) of the
new conversion data is available at the falling edge of
BUSY. This is the simplest way to operate the LTC2382-16.
LTC2382-16
17
238216fa
For more information www.linear.com/LTC2382-16
APPLICATIONS INFORMATION
238216 F13a
RDL2
RDL1
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2382-16 SDO
A
SCK
RDL/SDI
CNV
LTC2382-16 SDO
B
SCK
RDL/SDI
CHAIN BUSY
CHAIN
238216 F13
D15A
SDO
SCK
CNV
BUSY
CHAIN = 0
RDL/SDIB
RDL/SDIA
D15BD14BD1BD0B
D13B
D14AD13AD1AD0A
Hi-Z Hi-ZHi-Z
tEN
tHSDO
tDSDO
tDIS
tSCKL
tSCKH
tCNVL
tHSCKRDL
tSSCKRDL
1 2 3 14 15 16 17 18 19 30 31 32
tSCK
POWER-UP CONVERT
POWER-DOWN
CONVERT
ACQUIRE ACQUIRE
tCONV
tHOLD
tBUSYLH
Figure 13. Normal Mode with Multiple Devices Sharing CNV, SCK and SDO
Normal Mode, Multiple Devices
Figure 13 shows multiple LTC2382-16 devices operating
in Normal Mode(CHAIN = 0) sharing CNV, SCK and SDO.
By sharing CNV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
Since SDO is shared, the RDL/SDI input of each ADC must
be used to allow only one LTC2382-16 to drive SDO at a
time in order to avoid bus conflicts. As shown in Figure 13,
the RDL/SDI inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDI is brought low, the MSB of the selected
device is output onto SDO. To ensure the MSB is properly
output and captured, SCK must be held low at least 1ns
before and 16ns after bringing RDL/SDI low.
LTC2382-16
18
238216fa
For more information www.linear.com/LTC2382-16
APPLICATIONS INFORMATION
OVDD
238216 F14a
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2382-16
BUSY
SDO
B
SCK
RDL/SDI
CNV
LTC2382-16
SDO
A
SCK
RDL/SDI
CHAIN
OVDD
CHAIN
When CHAIN = OVDD, the LTC2382-16 operates in Chain
Mode. In Chain Mode, SDO is always enabled and RDL/
SDI serves as the serial data input pin (SDI) where daisy
chain data output from another ADC can be input.
This is useful for applications where hardware constraints
may limit the number of lines needed to interface to a large
number of converters. Figure 14 shows an example with
two daisy chained devices. The MSB of converter A will
appear at SDO of converter B after 16 SCK cycles. The
MSB of converter A is clocked in at the SDI/RDL pin of
converter B on the rising edge of the first SCK.
Figure 14. Chain Mode Timing Diagram
238216 F14
D0A
D1A
D14A
D15A
D13B
D14B
D15B
SDOB
SDOA = RDL/SDIB
RDL/SDIA = 0
D0B
D1B
D13A
D14A
D15AD0A
D1A
1 2 3 14 15 16 17 18 30 31 32
tDSDOBUSYL
tSSDISCK
tHSDISCK
tBUSYLH
tCONV
tHOLD
tHSDO
tDSDO
tSCKL
tSCKH
tSCKCH
tCNVL
tCYC
CONVERT
CONVERT
ACQUIRE ACQUIRE
POWER-DOWN POWER-UP
SCK
CNV
BUSY
CHAIN = OVDD
LTC2382-16
19
238216fa
For more information www.linear.com/LTC2382-16
BOARD LAYOUT
To obtain the best performance from the LTC2382-16
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital clocks
or signals alongside analog signals or underneath the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1571A, the
evaluation kit for the LTC2382-16.
238216 BL01
Partial Top Silkscreen
LTC2382-16
20
238216fa
For more information www.linear.com/LTC2382-16
BOARD LAYOUT
Partial Layer 1 Component Side
238216 BL03
Partial Layer 2 Ground Plane
238216 BL02
LTC2382-16
21
238216fa
For more information www.linear.com/LTC2382-16
BOARD LAYOUT
Partial Layer 3 PWR Plane
238216 BL04
238216 BL05
Partial Layer 4 Bottom Layer
LTC2382-16
22
238216fa
For more information www.linear.com/LTC2382-16
U6
NC7SZ66P5X
C13
0.1µF
4
12
9
CNV
SCK
C20
47µF
6.3V
0805
C56
0.1µF
CNV
REF
GND
GND
GND
GND
REF1
VDD
VREF
0.8VREF
OVDD
SCK
SDO
BUSY
RDL/SDI
SDO
BUSY
RD
LTC2382-16
IN–
IN+13
14
11
12
B A
5
3
GND
VCC
OE
+3.3V
JP4
REF
EXT
6652
HD1X3-100
R5
49.9Ω
1206
R6
1k
U8
NC7SZ04P5X
U2
NC7SVU04P5X
U10
LTC6652AHMS8-2.5
U3
NL17SZ74
U4
NC7SVU04P5X
CNVST_33
FROM CPLD
CLK
TO CPLD
C5
0.1µF
C1
0.1µF
C11
0.1µF
DNC
GND
GND
GND
GND
SHDN
9V TO 10V 1
2
3
4
83
2
1
7
6
5
+3.3V +3.3V +3.3V
3
42
5
3
42
5
C2
0.1µF
R3
33Ω
R2
1k
R1
33Ω
+3.3V
+3.3V
3
1
4
6
2
8
7
5
R8
33Ω
C3
0.1µF
R4
33Ω
C4
0.1µF
C12
1µF
E6
EXT_REF
VIN VOUT GND VCC
CLR\
Q\
CP
Q
D
PR\
3
4 2
5
+3.3V
DC590 DETECT
TO CPLD
+3.3V
C58
OPT
U9
NC7SZ04P5X C15
0.1µF
C16
0.1µF
3
42
5
+3.3V
R13
1k
R17
2k
R10
4.99k
U7
24LC025-I/ST R11
4.99k
R12
4.99k
C14
0.1µF
6
8
4
5
7
3
2
1
SCL
SDA
ARRAY
EEPROM
WP
A2
A1
A0
VSS
VCC
1
3
5
7
9
11
13
2
4
6
8
10
12
14
J3
DC590
SDO
SCK
CNV
9V TO
10V
R7
1k
10
16
6
3
1
15
7
2
8
JP6
FS
1
2
3
HD1X3-100
OPT
R1
ØΩ
C7
0.1µF
C6
10µF
6.3V
+2.5V
C10
0.1µF
C39
OPT
NPO
C19
3300pF
1206 NPO
R38
OPT
R36
49.9Ω
R35
OPT
R45
ØΩ
R34
ØΩ
C10
OPT
C9
10µF
6.3V
R1
100Ω
R32
49.9Ω
OUT1
V+
V–
V+ SHDN
OUT2 5
4
–IN1
+IN18
73
+IN22
6
R1
100Ω
–
+
+
–
R18
1k
R31
OPT
U15
LT6350CMS8
R32
ØΩ
C42
15pF
C45
10µF
C55
1µF V+
V–
C57
0.1µF
R37
1k
R9
1k
C61
10µF
6.3V
C63
10µF
6.3V
C62
10µF
C43
1µF
R15
1k
C18
OPT
C17
10µF
JP2
CM
E7
EXT_CM
1
+2.5V
2
3
VREF/2
EXT
HD1X3-100
C8
1µF
C46
1µF
R40
1k
R39
ØΩ
1
2
3
COUPLING
AC DC
JP1
HD1X3-100
C44
1µF
C49
OPT
C48
10µF
6.3V
C47
OPT
R41
OPT
C59
1µF
C60
1µF
1
2
3
JP5
HD1X3-100
COUPLING
AC DC
DB16
DB17
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
CLKOUT
1
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
J2
CON-EDGE 40-100
CLKIN
R14
Ø
AIN+
AIN–
BOARD LAYOUT
Partial Schematic of Demoboard
LTC2382-16
23
238216fa
For more information www.linear.com/LTC2382-16
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2382-16#packaging for the most recent package drawings.
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ±0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.15 REF
1.70 ±0.05
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE16) DFN 0806 REV Ø
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
3.30 ±0.05
3.30 ±0.10
0.45 BSC
0.23 ±0.05
0.45 BSC
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
LTC2382-16
24
238216fa
For more information www.linear.com/LTC2382-16
PACKAGE DESCRIPTION
MSOP (MS16) 0213 REV A
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
16151413121110
12345678
9
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ±0.038
(.0120 ±.0015)
TYP
0.50
(.0197)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.1016 ±0.0508
(.004 ±.002)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.280 ±0.076
(.011 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev A)
Please refer to http://www.linear.com/product/LTC2382-16#packaging for the most recent package drawings.
LTC2382-16
25
238216fa
For more information www.linear.com/LTC2382-16
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 07/16 Updated graphs G01, G02 and G03 6
LTC2382-16
26
238216fa
LINEAR TECHNOLOGY CORPORATION 2010
LT 0716 REV A • PRINTED IN USA
For more information www.linear.com/LTC2382-16
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC2383-16/LTC2381-16 16-Bit, 1Msps/250ksps Serial ADC 2.5V Supply, Differential Input, 92dB SNR, ±2.5V Input Range,16-Pin MSOP
and 4mmx3mm16-Pin DFN Packages,Pin compatible with the LTC2382-16
LTC2393-16 16-Bit, 1Msps Parallel/Serial ADC 5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP
Package, Pin compatible with the LTC2392-16, LTC2391-16
LTC2392-16 16-Bit, 500ksps Parallel/Serial ADC 5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP
Package, Pin compatible with the LTC2393-16, LTC2391-16
LTC2391-16 16-Bit, 250ksps Parallel/Serial ADC 5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, 48-Pin LQFP
Package, Pin compatible with the LTC2393-16, LTC2392-16
LTC1864/LTC1864L 16-Bit, 250ksps/150ksps 1-Channel µPower, ADC 5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package
LTC1865/LTC1865L 16-Bit, 250ksps 2-Channel µPower ADC 5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package
LTC2302/LTC2306 12-Bit, 500ksps, 1-/2-Channel, Low Noise, ADC 5V Supply, 14mW at 500ksps, 10-pin DFN Package
LTC2355-14/LTC2356-14 14-Bit, 3.5Msps Serial ADC 3.3V Supply, 1-Channel, Unipolar/Bipolar, 18mW, MSOP-10 Package
LTC1417 14-Bit 400ksps Serial ADC 5V/±5V Supply, 1-Channel, Unipolar/Bipolar, 20mW, 16-Pin Narrow SSOP
Package
DACs
LTC2641 16-Bit Single Serial VOUT DACs ±1LSB INL, ±1LSB DNL, MSOP-8 Package, 0V to 5V Output
LTC2630 12-/10-/8-Bit Single VOUT DACs SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
REFERENCES
LTC6652 Precision Low Drift Low Noise Buffered Reference 2.5V, 5ppm/°C Max Tempco, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6655 Precision Low Drift Low Noise Buffered Reference 2.5V, 5ppm/°C Max Tempco, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
AMPLIFIERS
LT6350 Low Noise Single-Ended-To-Differential ADC Driver Rail-to-Rail Input and Outputs, 240ns 0.01% Settling Time, DFN-8 or
MSOP-8 Packages
LT6200/LT6200-5/
LT6200-10
165MHz/800MHz/1.6GHz Op Amp with Unity
Gain/AV = 5/AV = 10
Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at 1MHz,
TSOT23-6 Package
LT6202/LT6203 Single/Dual 100MHz Rail-to-Rail Input/Output
Noise Low Power Amplifiers
1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth
LTC1992 Low Power, Fully Differential Input/Output
Amplifier/Driver Family
1mA Supply Current
50Ω
3300pF
6600pF
50Ω
500Ω
100Ω
100Ω
LPF2
LPF1
BW = 482kHz
BW = 48kHz
SINGLE-ENDED
INPUT SIGNAL
LTC2382-16
IN+
IN–
238216 TA03
LT6350
VCM = VREF/2
RINT RINT
8
4
5
2
1
+
–
+
–+
–
FREQUENCY (kHz)
0 50 100 150 200 250
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
238216 TA04
SNR = 92.2dB
THD = –106dB
SINAD = 92dB
SFDR = 107dB
ADC Driver: Single-Ended Input to Differential Output with Filter
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2382-16