74HC14DTR2G - ON Semiconductor - Datasheet.Directory

March, 2007 − Rev. 1

1Publication Order Number:

74HC14/D

74HC14

Hex Schmitt−Trigger

Inverter

High−Performance Silicon−Gate CMOS

The 74HC14 is identical in pinout to the LS14, LS04 and the HC04.

The device inputs are compatible with Standard CMOS outputs; with

pullup resistors, they are compatible with LSTTL outputs.

The HC14 is useful to “square up” slow input rise and fall times.

Due to hysteresis voltage of the Schmitt trigger, the HC14 finds

applications in noisy environments.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With the JEDEC Standard No. 7A Requirements

•ESD Performance: HBM > 2000 V; Machine Model > 200 V

•Chip Complexity: 60 FETs or 15 Equivalent Gates

•These are Pb−Free Devices

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MARKING

DIAGRAMS

HC14 = Device Code

A = Assembly Location

L, WL = Wafer Lot

Y = Year

W, WW = Work Week

G or G= Pb−Free Package

TSSOP−14

DT SUFFIX

CASE 948G

SOIC−14

D SUFFIX

CASE 751A

HC14G

AWLYWW

ALYW G

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

(Note: Microdot may be in either location)

74HC14

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LOGIC DIAGRAM

Y1A1

Y = A

Pin 14 = VCC

Pin 7 = GND

Pinout: 14−Lead Packages (Top View)

1314 12 11 10 9 8

21 34567

VCC A6 Y6 A5 Y5 A4 Y4

A1 Y1 A2 Y2 A3 Y3 GND

FUNCTION TABLE

Inputs Outputs

ORDERING INFORMATION

Device Package Shipping†

74HC14DR2G SOIC−14

(Pb−Free) 2500 / Tape & Reel

74HC14DTR2G TSSOP−14* 2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

74HC14

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V

Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

Iin DC Input Current, per Pin ±20 mA

Iout DC Output Current, per Pin ±25 mA

ICC DC Supply Current, VCC and GND Pins ±50 mA

PDPower Dissipation in Still Air, SOIC Package†

TSSOP Package†

500

450

Tstg Storage Temperature Range – 65 to + 150 _C

TLLead Temperature, 1 mm from Case for 10 Seconds

SOIC or TSSOP Package 260

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not im-

plied. Extended exposure to stresses above the Recommended Operating Conditions may af-

fect device reliability.

†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

Vin, Vout DC Input Voltage, Output Voltage (Referenced to

GND)

0 VCC V

TAOperating Temperature Range, All Package Types – 55 + 125 _C

tr, tfInput Rise/Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

No Limit*

*When Vin = 50% VCC, ICC > 1mA

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

74HC14

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DC CHARACTERISTICS (Voltages Referenced to GND)

VCC

(V)

Guaranteed Limit

Symbol Parameter Condition −55 to 25°C≤85°C≤125°C Unit

VT+ max Maximum Positive−Going Input

Threshold Voltage

(Figure 3)

Vout = 0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

1.50

2.15

3.15

4.20

1.50

2.15

3.15

4.20

1.50

2.15

3.15

4.20

VT+ min Minimum Positive−Going Input

Threshold Voltage

(Figure 3)

Vout = 0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

1.0

1.5

2.3

3.0

0.95

1.45

2.25

2.95

0.95

1.45

2.25

2.95

VT− max Maximum Negative−Going Input

Threshold Voltage

(Figure 3)

Vout = VCC − 0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

0.9

1.4

2.0

2.6

0.95

1.45

2.05

2.65

0.95

1.45

2.05

2.65

VT− min Minimum Negative−Going Input

Threshold Voltage

(Figure 3)

Vout = VCC − 0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

0.3

0.5

0.9

1.2

0.3

0.5

0.9

1.2

0.3

0.5

0.9

1.2

VHmax

Note 2

Maximum Hysteresis Voltage

(Figure 3)

Vout = 0.1V or VCC − 0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

1.20

1.65

2.25

3.00

1.20

1.65

2.25

3.00

1.20

1.65

2.25

3.00

VHmin

Note 2

Minimum Hysteresis Voltage

(Figure 3)

Vout = 0.1V or VCC − 0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

0.20

0.25

0.40

0.50

0.20

0.25

0.40

0.50

0.20

0.25

0.40

0.50

VOH Minimum High−Level Output

Voltage

Vin ≤ VT− min

|Iout| ≤ 20mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin ≤ VT− min |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

VOL Maximum Low−Level Output

Voltage

Vin ≥ VT+ max

|Iout| ≤ 20mA

2.0

4.5

6.0

0.1

Vin ≥ VT+ max |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

0.26

0.33

0.40

Iin Maximum Input Leakage

Current

Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA

ICC Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0mA

6.0 2.0 20 40 mA

1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

2. VHmin > (VT+ min) − (VT− max); VHmax = (VT+ max) − (VT− min).

74HC14

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AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

VCC

(V)

Guaranteed Limit

Symbol Parameter −55 to 25°C≤85°C≤125°C Unit

tPLH,

tPHL

Maximum Propagation Delay, Input A or B to Output Y

(Figures 1 and 2)

2.0

3.0

4.5

6.0

110

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 2)

2.0

3.0

4.5

6.0

110

Cin Maximum Input Capacitance 10 10 10 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

CPD Power Dissipation Capacitance (Per Inverter)*

Typical @ 25°C, VCC = 5.0 V

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Figure 1. Switching Waveforms

GND

VCC

OUTPUT Y

INPUT A

CL*

*Includes all probe and jig capacitance

TEST

POINT

90%

50%

10%

tTLH

DEVICE

UNDER

TEST

OUTPUT

Figure 2. Test Circuit

tTHL

90%

50%

10%

tPLH tPHL

tftr

74HC14

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VHtyp

Figure 3. Typical Input Threshold, VT+, VT− versus Power Supply Voltage

Figure 4. Typical Schmitt−Trigger Applications

VCC, POWER SUPPLY VOLTAGE (VOLTS)

23456

VT, TYPICAL INPUT THRESHOLD VOLTAGE (VOLT

VHtyp = (VT+ typ) − (VT− typ)

(VT+)

(VT−)

Vin

Vout

VCC

VT+

VT−

GND

VOH

VOL

Vin

Vout

VCC

VT+

VT−

GND

VOH

VOL

(a) A Schmitt−Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt−Trigger Offers Maximum Noise Immunity

74HC14

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PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−A−

−B−

P7 PL

14 8

0.25 (0.010) B M

0.25 (0.010) A S

−T−

RX 45

SEATING

PLANE D14 PL K

_DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

__ __

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

74HC14

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PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

ÉÉÉ

DETAIL E

−W−

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

−V−

14X REFK

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

74HC14

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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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