© Semiconductor Components Industries, LLC, 2017
May, 2019 − Rev. 16
1Publication Order Number:
NTD2955/D
NTD2955, NVD2955
MOSFET – Power,
P-Channel, DPAK
-60 V, -12 A
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low−voltage, high−
speed switching applications in power supplies, converters, and power
motor controls. These devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer an additional safety margin against unexpected
voltage transients.
Features
•Avalanche Energy Specified
•IDSS and VDS(on) Specified at Elevated Temperature
•Designed for Low−Voltage, High−Speed Switching Applications and
to Withstand High Energy in the Avalanche and Commutation Modes
•NVD and SVD Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC−Q101 Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−to−Source Voltage VDSS −60 Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 10 ms)
VGS
VGSM
±20
±25
Vdc
Vpk
Drain Current
Dr− Continuous @ Ta = 25°C
Dr− Single Pulse (tp ≤ 10 ms)
ID
IDM
−12
−18
Adc
Apk
Total Power Dissipation @ Ta = 25°C PD55 W
Operating and Storage Temperature
Range
TJ, Tstg −55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 12 Apk, L = 3.0 mH, RG = 25 W)
EAS 216 mJ
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
RqJC
RqJA
RqJA
2.73
71.4
100
°C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8 in. from case for
10 seconds
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 1 in pad size
(Cu area = 1.127 in2).
2. When surface mounted to an FR4 board using the minimum recommended
pad size (Cu area = 0.412 in2).
D
S
G
P−Channel
www.onsemi.com
−60 V 155 mW @ −10 V, 6 A
RDS(on) TYP
−12 A
ID MAXV(BR)DSS
A = Assembly Location*
NT2955/NV2955 = Specific Device Code (DPAK)
NT2955 = Specific Device Code (IPAK)
Y = Year
WW = Work Week
G = Pb−Free Package
1
Gate
3
Source
2
Drain
4
Drain
DPAK
CASE 369C
STYLE 2
12
3
4
IPAK
CASE 369D
STYLE 2
123
4
AYWW
NT
2955G
See detailed ordering and shipping information on page 5 of
this data sheet.
ORDERING INFORMATION
1
Gate
3
Source
2
Drain
4
Drain
AYWW
NT
2955G
MARKING DIAGRAMS
& PIN ASSIGNMENTS
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
NTD2955, NVD2955
www.onsemi.com
2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = −0.25 mA)
(Positive Temperature Coefficient)
V(BR)DSS
−60
−
−
67
−
−
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VGS = 0 Vdc, VDS = −60 Vdc, TJ = 25°C)
(VGS = 0 Vdc, VDS = −60 Vdc, TJ = 150°C)
IDSS
−
−
−
−
−10
−100
mAdc
Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS − − −100 nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
(VDS = VGS, ID = −250 mAdc)
(Negative Temperature Coefficient)
VGS(th)
−2.0
−
−2.8
4.5
−4.0
−
Vdc
mV/°C
Static Drain−Source On−State Resistance
(VGS = −10 Vdc, ID = −6.0 Adc)
RDS(on)
−0.155 0.180
W
Drain−to−Source On−Voltage
(VGS = −10 Vdc, ID = −12 Adc)
(VGS = −10 Vdc, ID = −6.0 Adc, TJ = 150°C)
VDS(on)
−1.86
−
−2.6
−2.0
Vdc
Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) gFS 8.0 −Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = −25 Vdc, VGS = 0 Vdc,
F = 1.0 MHz)
Ciss −500 750 pF
Output Capacitance Coss −150 250
Reverse Transfer Capacitance Crss −50 100
SWITCHING CHARACTERISTICS (Notes 3 and 4)
Turn−On Delay Time
(VDD = −30 Vdc, ID = −12 A,
VGS = −10 V, RG = 9.1 W)
td(on) −10 20 ns
Rise Time tr−45 85
Turn−Off Delay Time td(off) −26 40
Fall Time tf−48 90
Gate Charge
(VDS = −48 Vdc, VGS = −10 Vdc,
ID = −12 A)
QT−15 30 nC
QGS −4.0 −
QGD −7.0 −
DRAIN−SOURCE DIODE CHARACTERISTICS (Note 3)
Diode Forward On−Voltage
(IS = 12 Adc, VGS = 0 V)
(IS = 12 Adc, VGS = 0 V, TJ = 150°C)
VSD
−
−
−1.6
−1.3
−2.5
−
Vdc
Reverse Recovery Time
(IS = 12 A, dIS/dt = 100 A/ms ,VGS = 0 V)
trr −50 ns
ta−40 −
tb−10 −
Reverse Recovery Stored Charge QRR −0.10 −mC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Indicates Pulse Test: Pulse Width ≤300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
NTD2955, NVD2955
www.onsemi.com
3
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
012345
0
15
25
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
24 6 810
0
10
18
24
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°CVDS ≥ −10 V TJ = -55°C
25°C125°C
VGS = -10 V -9 V -8 V
-6 V
-5 V
-7 V
5
10
20
3579
4
12
22
678910
16
6
03 6 15 24
0
0.10
0.20
0.30
0 6 21 24
0.050
0.075
0.200
0.250
−ID, DRAIN CURRENT (AMPS) -ID, DRAIN CURRENT (AMPS)
TJ = 25°C
VGS = −10 V
TJ = 125°C
25°C
-55°C
12 21 3 12 15
0.05
0.15
0.25
0.100
0.225
0.125
VGS = −10 V
-15 V
189
0.35
0.40
0.175
918
0.150
-50
0.6
0.8
1.2
1.6
520 5060
1
100
1000
TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
-25 0 25 50 75 100 125 150
VGS = 0 V
VGS = −10 V
ID = −6 A
15 30 40
1.0
1.4
TJ = 125°C
175
0.4
0.2
0
1.8
2.0
100°C
-6.5 V
-5.5 V
-9.5 V
8
2
20
14
0.45
0.50
10
10 25 5535 45
−ID, DRAIN CURRENT (A)
−ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
−IDSS, LEAKAGE (nA)
NTD2955, NVD2955
www.onsemi.com
4
0.1
1
10
100
0.1 1 10 100
Figure 7. Capacitance Variation Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (W)
1 10 100
t, TIME (ns)
VDD = −30 V
ID = −12 A
VGS = −10 V
TJ = 25°C
tf
td(off)
0
QT
, TOTAL GATE CHARGE (nC)
2468
ID = 12 A
TJ = 25°C
VGS
1000
100
10
1
15
10
0
2.5
5
60
50
40
30
0
VDS
14
QT
QGS QGD
1610 12
td(on)
tr
12.5
7.5
20
0 0.25 0.75 1.75
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
VGS = 0 V
TJ = 25°C
0
10
15
5
0.5 1 1.25 1.5
10
10 0 10 15 25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
-VGS -VDS
TJ = 25°C
VDS = 0 V VGS = 0 V
1000
800
600
400
200
0
20
Ciss
Coss
Crss
55
Ciss
Crss
1200
Figure 10. Diode Forward Voltage versus Current
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS = −15 V
SINGLE PULSE
TC = 25°C
dc
100 ms
1 ms
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Figure 12. Diode Reverse Recovery Waveform
di/dt
trr
ta
tp
IS
0.25 IS
TIME
IS
tb
ID, DRAIN CURRENT (AMPS)
−VGS, GATE−TO−SOURCE VOLTAGE (V)−IS, SOURCE CURRENT (AMPS)
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
NTD2955, NVD2955
www.onsemi.com
5
Figure 13. Thermal Response
t, TIME (s)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) RqJC(t)
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
1.0
0.1
0.01
0.2
D = 0.5
0.05
0.01
SINGLE PULSE
0.1
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01
0.02
ORDERING INFORMATION
Device Package Shipping†
NTD2955G DPAK
(Pb−Free)
75 Units / Rail
NTD2955−1G IPAK
(Pb−Free)
75 Units / Rail
NTD2955T4G DPAK
(Pb−Free)
2500 / Tape & Reel
NVD2955T4G* DPAK
(Pb−Free)
2500 / Tape & Reel
SVD2955T4G* DPAK
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NVD and SVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified
and PPAP Capable.
SCALE 1:1
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
123
4
V
SA
K
−T−
SEATING
PLANE
R
B
F
G
D3 PL
M
0.13 (0.005) T
C
E
J
H
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.235 0.245 5.97 6.35
B0.250 0.265 6.35 6.73
C0.086 0.094 2.19 2.38
D0.027 0.035 0.69 0.88
E0.018 0.023 0.46 0.58
F0.037 0.045 0.94 1.14
G0.090 BSC 2.29 BSC
H0.034 0.040 0.87 1.01
J0.018 0.023 0.46 0.58
K0.350 0.380 8.89 9.65
R0.180 0.215 4.45 5.45
S0.025 0.040 0.63 1.01
V0.035 0.050 0.89 1.27
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Z
Z0.155 −−− 3.93 −−−
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
xxxxxxxxx = Device Code
A = Assembly Location
lL = Wafer Lot
Y = Year
WW = Work Week
YWW
xxxxxxxx
xxxxx
ALYWW
x
Discrete
Integrated
Circuits
IPAK
CASE 369D−01
ISSUE C
DATE 15 DEC 2010
MARKING
DIAGRAMS
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON10528D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
IPAK (DPAK INSERTION MOUNT)
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F DATE 21 JUL 2015
SCALE 1:1
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
123
4
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. RESISTOR ADJUST
4. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. ANODE
b
D
E
b3
L3
L4b2
M
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D0.235 0.245 5.97 6.22
E0.250 0.265 6.35 6.73
A0.086 0.094 2.18 2.38
b0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.028 0.045 0.72 1.14
c0.018 0.024 0.46 0.61
e0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01
L0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
12 3
4
XXXXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
AYWW
XXX
XXXXXG
XXXXXXG
ALYWW
DiscreteIC
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
ǒmm
inchesǓ
SCALE 3:1
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
A1
H
DET AIL A
SEATING
PLANE
A
B
C
L1
L
H
L2 GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
eBOTTOM VIEW
Z
BOTTOM VIEW
SIDE VIEW
TOP VIEW
ALTERNATE
CONSTRUCTIONS
NOTE 7
Z
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98AON10527D
ON SEMICONDUCTOR STANDARD
REF TO JEDEC TO−252
DPAK SINGLE GAUGE SURFACE MOUNT
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON10527D
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001
AADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008
BADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009
CADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009
DRELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A.
CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE. 29 JUN 2010
EADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS
b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAM-
BALIZA.
06 FEB 2014
FADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K.
MUSTAFA. 21 JUL 2015
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. F Case Outline Number
:
369C
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
◊
