DESCRIPTION
The DD-03182 device is a line driver
chip that transmits data on the serial
data bus in accordance with the
“ARINC Specification 429 Mark 33
Digital Information Transfer System”
(ARINC 429). This de vice can be used
with DDC’s DD-03296 discrete-to-digi-
tal device, in conjunction with the DD-
03282 transceiver chip or the DD-
00429 microprocessor interface.
The line driver receives TTL informa-
tion on the DataA/DataBinput pins
and transmits it out on the AOUT/BOUT
output pins. The output voltage level
is programmable via the VREF input
pin. The output pins are also protect-
ed against short circuits from aircraft
power.The slew r ate of the DD-03182
can be programmed for either High
(100 kbit) or Low (12.5 kbit) speed via
two external timing capacitors con-
nected to the CA/CBinput pins.
APPLICATIONS
The DD-03182 can be used for many
different applications ranging from
flight critical to nonessential. Surface
mount, DIP and PLCC package con-
figurations are a v ailab le . Military tem-
perature range is also available if
required.
DD-03182 SERIES
ARINC 429 LINE DRIVER
FEATURES
•
Plastic 14-Pin SOIC Package
Available with or without Fuse
•
Pin-For-Pin Alternative for Most
Harris/Holt/Raytheon Applications
•
Programmable Output Voltage Level
•
Short-Circuit Protection on Outputs
•
Programmable Slew and Data Rates
DATA (A)
DATA (B)
CLOCK
V
REF
SYNC
+V C
A
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
OUTPUT
DRIVER (A)
OUTPUT
DRIVER (B)
-V C
B
R
OUT
2
R
OUT
2
OVERVOLTAGE
PROTECTION
(OPTIONAL)
CURRENT
REGULATOR
BIAS
V
1
GND
B
OUT
A
OUT
©1993 ILC Data Device Corporation FIGURE 1. DD-03182 BLOCK DIAGRAM
Overvoltage Protection optional for
DD-03182VP only.
GENERAL
The ARINC 429 standard is widely used in the civil aerospace
market (commercial aircraft). ARINC 429 operates at either 12
to 14.5 or 100 kbits on a simplex bus. A simplex bus is one on
which there is only one transmitter b ut m ultiple receivers (up to a
maximum of 20 in the case of 429). If receipt of a message by a
given sink R(n) is required by the source T, a separate bus with
R(n) as the source and T as the sink is required. To those
designers who focus on military systems, a simplex bus may
seem cumbersome, b ut it can be readily certified for civil aircr aft.
Communications on 429 buses use 32-bit words with odd parity.
The waveform is a bipolar return to zero with each bit lasting
either 70 or 83µs ±2.5 percent, or 10µs, ±2.5 percent, depend-
ing on whether the bus is low- or high-speed. A low-speed bus
is used for general purpose, low critical applications. A high-
speed bus is used for transmitting large quantities of data or
flight critical information.
ARINC 429 imposes relatively modest and readily achievable
performance demands on the hardware. FIGURE 2 is a general
schematic of a 429 bus. The transmitter output impedance
should be in the range of 75 to 85 Ω, equally divided between the
two leads. The output voltage, Vo, is 10 V and is generated by
imposing equal but opposite polarity voltages on the two leads.
The null voltage is 0.5 V. For the receiver, the input resistance
shall be greater than 12,000 Ωand the input differential capaci-
tance and the capacitance to ground shall, in both cases, be less
than 50 pF. The 12,000 Ωminimum input resistance ensures
that up to 20 receivers can be on the bus without overloading it
and minimizes receiv er interaction under f ault conditions . To pre-
clude continued receiver operation in a lead-to-ground fault con-
dition, 429 has established the r ange of acceptable receiv er volt-
age levels to be +6.5 to +13.0 V and -6.5 to -13.0 V and null lev-
els from +2.5 to -2.5 V. Any signals falling outside of these lev-
els will be ignored. Also note that a lead-to-ground fault will pro-
duce a differential voltage swing up 5.5 V. FIGURE 4 shows the
waveforms required by 429 and permissible levels f or tr ansmitter
and receiver voltages.
2
A
B
Transmitter
Shield
Signal Leads
To Other Receivers
(max. total of 20)
Receiver
A
B
FIGURE 2. GENERALIZED 429 BUS
Notes:
1. Both outputs can be shor ted to ground or to each other indefinitely, at +25°C
ambient temperature.
2. Both outputs are fused between 0.5 Amp DC and 1.0 Amp DC to prevent an
overvoltage fault from coupling onto the system power bus.
3.Thermal resistance when mounted on a 4" x 4" FR4 PC board in a horizontal
position, still air.
TABLE 1. DD-03182 SPECIFICATIONS
PARAMETER UNITS MIN TYP MAX
ABSOLUTE MAXIMUM
RATINGS
VOLTAGE BETWEEN
PINS
+V and -V
V1and GND
VREF and GND
Output Shor t-circuit
Protection
Output Overvoltage
Protection
Power Dissipation
V
V
VSee Note 1
See Note 2
See TABLE 2
40
7
6
POWER SUPPLY
REQUIREMENTS
+V
-V
V1
VREF (for ARINC 429)
VREF (for other applica-
tions)
VDC
VDC
VDC
VDC
VDC
11.4
-11.4
4.75
4.75
0
15
-15
5
5
16.5
-16.5
5.25
5.25
°C
°C
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C
-55
-40
-65
15
75
95
115
130
+125
+85
+150
+300
175
in.
(mm.)
in.
(mm.)
in.
(mm.)
in.
(mm.)
0.344 x 0.158 x 0.069
(8.737 x 4.013 x 1.753)
0.785 x 0.291 x 0.160
(19.939 x 7.391 x 4.064)
0.413 x 0.300 x 0.082
(10.490 x 7.620 x2.080)
0.454 x 0.454 x 0.155
(11.53 x 11.53 x 3.94)
oz. (g.)
oz. (g.)
oz. (g.)
oz. (g.)
0.01 (0.28)
0.08 (2.26)
0.02 (0.57)
0.04 (1.13)
THERMAL
Operating Ambient
Temperature
Ceramic
Plastic
Storage Temperature
Lead Temperature
(localized 10 sec
duration)
Thermal Resistance:
Junction to Case θjc
DD-03182DC
Junction to Ambient θja
(see Note 3)
DD-03182DC
DD-03182PP
DD-03182GP
DD-03182VP
Max.Junction Temperature
SIZE
DD-03182VP
DD-03182DC
DD-03182GP
DD-03182PP
WEIGHT
DD-03182VP
DD-03182DC
DD-03182GP
DD-03182PP
3
Notes: 1. Supply current data is at 100% duty cycle. Load and chip power is calculated as 89% duty cycle (32 bits,/36 bits).
2. Data is not presented for 30,000 pF at 100 kbps.This is considered an unrealistic load for high-speed operation.
3. For 12 volt power supplies, multiply tabulated values of chip power by 0.8.
TABLE 2. DD-03182 POWER DISSIPATION FOR CONTINUOUS ARINC 429 TRANSMISSION
DATA RATE (KBPS) LOAD
(Note 2)
C
(pF)
R
(Ω)
+V @
15 V
(mA)
(Note 3)
-V @
-15 V
(mA)
(Note 3)
VREF and
V1 @
5 V
(mA)
LOAD POWER
(mW)
(Note 1)
CHIP POWER
(mW)
(Note 1)
0 TO 100 0No load 2.5 -5.0 4.4 0 120
12.5 10002000 4.6 -7.1 4.4 19 158
12.5 10,0002000 6.5 -8.9 4.4 19 206
12.5 30,0002000 11.3 -13.8 4.4 19 336
100
100
100
100
100
12.5
12.5
12.5
100
100
100
100
12.5
12.5
12.5
400
400
800
800
2000
400
400
800
400
2000
800
2000
400
800
800
10,000
3,000
1000
10,000
3,000
10,000
30,000
30,000
1000
10,000
3,000
1000
1000
10,000
1000
24.4
14.3
8.4
23.1
9.3
13
16.2
13.5
12.8
22.2
11.4
5.8
12.5
8.9
7.8
-26.9
-16.8
-11
-25.7
-11.7
-15.5
-18.7
-16
-15.3
-24.7
-14
-8.3
-15.1
-11.4
-10.3
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
4.4
71
71
42
42
19
71
71
42
71
19
42
19
71
42
42
633
364
237
629
281
329
414
371
324
627
317
189
317
249
219
TABLE 3. DD-03182 DC ELECTRICAL CHARACTERISTICS
PARAMETER (SYMBOL) UNITS MIN TYP MAX TEST CONDITIONS
Quiescent +V Supply Current (IQ+V) mA 2.5 No load 429 mode.
DATA = CLOCK = SYNC = L
Quiescent -V Supply Current (IQ-V) mA 5 No load 429 mode.
DATA = CLOCK = SYNC = L
Quiescent V1 Supply Current (IQV1) mA 4.4 No load 429 mode.
DATA = CLOCK = SYNC = L
µA10 No load 429 mode.
DATA = CLOCK = SYNC = L
Logic 1 input V (VIH) V 2.0 No load
Logic 1 input I (IIH) µA10 No load
Logic 0 input V (VIL) V 0.6 No load
Logic 0 input I (IIL) µA-20
Output voltage high: +1 (VOH) V VREF
-250 mV VREF VREF
+250 mV No load 429 Mode
Output voltage null: 0 (VNULL) mV -250 +250 No load 429 Mode
Output voltage low: -1 (VOL) V -VREF
-250 mV -VREF -VREF
+250 mV No load 429 Mode
Timing capacitor charge current:
CA [+1] CB [-1] (ICT+)
CA [-1] CB [+1] (ICT-) µA
µA+200
-200
No load 429 Mode.
SYNC = CLOCK = H
CAand CBheld at 0
+V Shor t-circuit supply current (ISC [+V]) mA +150 Output shor t to GND.
-V Shor t-circuit supply current (ISC [-V]) mA -150 Output shor t to GND.
ohms 30 37.5 45
Input capacitance (CIN) pF 15
*Note:The device will operate with +V and -V supplies at ±12 VDC ±5% in accordance with the temperature range of the device type ordered.
Quiescent VREF supply current (IQVREF)
CONDITIONS: Ambient Temperature is in accordance with the temperature range of device type ordered;
+V = +15 VDC ±10%; -V = -15 VDC ±10%;V1 = VREF = +5 VDC ±5%*.
Output resistance each output (ROUT/2)
is at +25°C only.
No load (Pin 15 IIL = -2 mA max.)
4
0V
0V
A
B
+V
A
-V
-V
+V
B
IN
IN
REF
OUT
REF
REF
OUT
REF
FIGURE 3. ARINC 429 WAVEFORM
Notes:
1. X = Don’t care.
2.The AOUT/BOUT notation is as follows:
+1 = VREF volts
0 = 0
TABLE 4. DD-03182 TRUTH TABLE
SYNC
(Note 1) CLOCK
(Note 1) DATA (A)
(Note 1) DATA (B)
(Note 1) AOUT
(Note 2) BOUT
(Note 2) COMMENTS
L X X X 0 0 Null
X L X X 0 0 Null
H H L L 0 0 Null
H H H H 0 0 Null
H H H L +1 -1 Logic 1
H H L H -1 +1 Logic 0
DATA (A)
DATA (B)
The DD-03182 line driver is designed to take data from a box and
place it on the data bus.The serial data is presented on DATA(A)
and DATA(B) inputs in a dual rail format. The dr iver is enabled by
the SYNC and CLOCK inputs. The output voltage level is pro-
grammed by the VREF input and is nor mally tied to +5 VDC along
with V1to produce output levels of +5V, 0V, and
-5 V on each output for 10 V differential outputs (see FIGURE 3).
The outputs are fused for fail-safe protection against shorts to
aircraft power. The output slew rate is controlled b y external tim-
ing capacitors on CAand CB. Typical Values are 75 pF for
100 kHz data and 500 pF for 12.5 kHz data.
The cable used in 429 buses is a twisted, shielded pair of 20- to
26-gauge conductors. The shield is grounded at both ends of the
cable run and at all production breaks. Although there is no
specification placed on the cable impedance, it generally falls in
the range of 60 to 80 Ω.
Note:The output slew rates are controlled by timing capacitors CAand CB.They are charged to ±200µA (nominal).
Slew rate (SR) is calculated by SR = 200/C (V/µs), where C is in pF.
5
TABLE 5. DD-03182 PINOUTS
PIN NUMBER DC OR GP
PACKAGE PP PACKAGE PP PACKAGE
DC OR GP
PACKAGEPIN NUMBERVP PACKAGE
1VREF VREF GNDN/C15
VREF
2 N/C N/C +V
V1
16N/C
3 SYNC GND BOUT
17SYNC
4 DATA (A) SYNC N/C18DATA (A)
5CAN/C N/C19
CA
6AOUT DATA (A) N/C20
AOUT
7-V N/C N/C21-V
8 GND N/C CB
22GND
9 +V CADATA (B)23+V
10 N/C N/C N/C24
BOUT
11 BOUT N/C CLOCK25
CB
12 CBN/C N/C26DATA (B)
13 DATA (B) AOUT N/C27CLOCK
14 CLOCK -V V1
28
V1
SLEW RATE VS.TIMING CAPACITOR VALUES
The output slew rates are controlled by timing capacitors CAand
CB, and are charged by ±200 µA (nominal).Slew rate (SR) is cal-
culated by:
SR = 200/C (V/µsec), where C is in pF (equation 1).
HIGH-SPEED SLEW RATE
CAand CB= 75 pF for 100 kbps
From equation 1: 200/75 = 2.67 V/µsec
10% - 90% = 0.5 V to 4.5 V
∆= 4.0 V
For 100 kbps bit rate, the slew rate specification is 1.5 µsec
±0.5 µsec. Slew rate range (1.0 to 2.0 µsec).
200/SR = Capacitor, in pF
200/2.67 = 75 pF
(2.67 V/µsec)(1.5) = 4.0 V
SR = 4/(Rise Time)
4 µsec = 4V/1 µsec Capacitor = 200/4 = 50 pF
2 µsec = 4V/2 µsec Capacitor = 200/2 = 100 pF
LOW-SPEED SLEW RATE
CAand CB= 500 pF for 12.5 kbps
From equation 1: 200/500 = 0.4 V/µsec
For 12.5 kbps bit rate, the slew rate specification is 10 µsec
±5.0 µsec. Slew rate range (5 to 15 µsec).
200/SR = Capacitor in pF
200/0.4 = 500 pF
(0.4 V/µsec)(10) = 4.0 V
SR = 4/(Rise Time)
0.8 µsec = 4V/5 µsec Capacitor = 200/0.8 = 250 pF
0.267 µsec = 4V/15 µsec Capacitor = 200/0.267 = 750 pF
DD-03182 PIN FUNCTIONS
Refer to FIGURES 7, 8 and 9 and TABLE 5 for specific package
pin configurations.
VREF (Input) – the voltage on VREF sets the output voltage levels
on AOUT and BOUT.The output logic level swings between
+VREF volts, 0 volts and -VREF volts.
N/C – No Connection
SYNC (Input) – Logic 0 outputs will be forced to NULL or MARK
state. Logic 1 enables data transmission.
CLOCK (Input) – Logic 0 outputs will be forced to NULL or
MARK state. Logic 1 enables data transmission.
DATA(A)/DATA(B) (Inputs) – These signals contain the serial
data to be transmitted on the ARINC 429 data bus.
CA/CB(Analog) – External timing capacitors are tied from these
points to ground to establish the output signal slew rate.
Typically, CA=CB=75 pF f or 100 kHz data and CA=CB=500 pF for
12.5 kHz data.
AOUT/BOUT (Output) – These are the line driver outputs which
are connected to the aircraft serial data bus.
-V (Input) – This is the negative supply input (-15 VDC nominal).
GND – Ground
+V (Input) – This is the positive supply input (+15 VDC nominal).
V1(Input) – This is the logic supply input (+5 VDC nominal).
6
VCC
VCC
VCC
VCC
VCC
TX0_A
TX0_B
DD-03182GP
1
16
3
4
14
13
5
12
7
9
8
6
11
A_OUT
B_OUT
V1
VREF
SYNC
CLK
DATA_A
DATA_B
CA
CB
V-
V+
GND
TX0_A_OUT
TX0_B_OUT
SPD1A
C12 C8
470 pF 68 pF
SPD1B
C13 C9
470 pF 68 pF
ADG412BR
4
12 VCC
14
13
3
5
11
6
GND
1
2
16
15
9
10
8
7
V+
V-
S1
S2
S3
S4
VR
IN1
IN2
IN3
IN4
D4
D3
D2
D1
SPD1A
SPD1B
TX0_SEL
TX1_SEL
TX0_SEL
TX1_SEL
SPD2A
SPD2A
ARINC 429
ARINC 429
RECEIVE CH 1
RECEIVE CH 2
DI1(B)
DI1(A)
DI2(A)
DI2(B)
VCC
+5V
DR1
DR2
TXR
SEL
OE1
OE2
LD1
LD2
LDCW
EN TX
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
TXCK
1MCK
DBCEN
MR
DO(A)
DO(B)
GND 27
16
17
18
19
20
22
23
24
25
26
11
15
14
13
12
21
39
40
37
38
32
31 29
34
33
30
8
9
10
28
6
7
1
5
4
3
2
DIGITAL CONTROL
INTERFACE
DIGITAL DATA
INTERFACE
DD-03282DC
TRANSMIT
ARINC 429
1 MHZ CLK
DD-03182GP
NOTE: C1 = C2 = 500pF FOR
LO SPEED OPERATION
613
4
7
16
9
11 3
14
512 8
1
75pF
C2 C2
+15V +5V -15V
+5V
75pF
CC
A
BTX0 A
TX0 B
FIGURE 4. RECOMMENDED CIRCUITRY -
SWITCHING CAPACITORS FOR HIGH-SPEED/LOW-SPEED OPERATION
FIGURE 5.TYPICAL TRANSCEIVER/LINE DRIVER INTERCONNECT CONFIGURATION
7
FIGURE 7. DD-03182PP PIN CONFIGURATION
TOP VIEW
126
432
25
24
23
22
21
20
19
18
17
15 16
5
7
8
11
10
9
6
DD-03182PPDD-03182PP
PLCCPLCC
DATA (A)
N/C
N/C
N/C
N/C
N/C
S
Y
N
C
G
N
DN
/
C
VR
E
FV
1
N
/
CN
/
C
CA
CB
N/C
N/C
N/C
N/C
DATA (B)
CLOCK
N
/
C
-v +v
AO
U
T
BO
U
T
N
/
C
G
N
D
14
12 13
28 27
TOP VIEW
N/C
1
215
16
N/C
V
1
13
14
DATA(B)
CLOCK
3
4
SYNC
DATA(A)
5
611
12
9
10 N/C
7
8
-V
+V
GND
AB
OUT
OUT
AB
CC
FIGURE 9. DD-03182DC AND GP PIN CONFIGURATION
FIGURE 8. DD-03182VP PIN CONFIGURATION
TOP VIEW
N/C
1
213
14 V1
11
12 DATA(B)
CLOCK
3
4
SYNC
DATA(A)
5
69
10
8
+V
7
-V GND
A
B
OUT
OUT
A
B
C
C
AOUT
BOUT
DD-03182 SMAJ6.5CA
SMAJ6.5CA
MICRO-SEM
MICRO-SEM
FIGURE 6. RECOMMENDED TRANSIENT
PROTECTION CIRCUIT
8
0.785 MAX
(19.94)
LEAD #1
0.025 RAD
(0.64)
0.291 MAX
(7.39)
0.050 MAX
(1.27)
0.060 ±0.005
(1.52 ±0.13)
0.160 MAX
(4.06)
0.020 - 0.070
(0.51 - 1.78) 0.100 ±0.010
(2.54 ±0.25) 0.018 ±0.002
(0.46 ±0.05)
0.125 MIN
(3.18)
0.385 ±0.025
(9.78 ±0.64)
0.290 - 0.320
(7.39 - 8.13)
0.008 - 0.012
(0.20 - 0.31)
DIMENSIONS ARE IN INCHES (mm)
0 - 10 deg.
FIGURE 11. DD-03182DC CERAMIC DIP (JE) MECHANICAL OUTLINE
FIGURE 10. DD-03182VP 14-PIN SURFACE MOUNT (SOIC) MECHANICAL OUTLINE
9
0.018
[0.46]
MIN
0.100
[2.54]
0.175
[4.45]
ORIENTATION MARK
DENOTES PIN 1
0.020
[0.51]
MIN
0.029
[0.74]
(TYP)
±0.005
0.490
[12.45)]
0.050
[1.27]
(TYP)
1. LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN ±0.010.
2. DIMENSIONS SHOWN ARE IN INCHES [MILLIMETERS].
±0.002
0.454
[11.53]
±0.002
0.454
[11.53]
±0.002
0.490
[12.45]
6 EQ. SP @
0.050 = 0.300
(TOL NONCUM)
(TYP) 1
±0.020
0.410
[10.41]
1
Notes:
FIGURE 13. DD-03182PP PLCC MECHANICAL OUTLINE
0.014 MIN 0.019 MAX
(0.36 MIN 0.48 MAX)
0.003 MIN 0.012 MAX
(0.76 MIN 0.30 MAX)
0.47MIN 0.53 MAX
(1.19 MIN 1.35 MAX)
0.397 MIN 0.413 MAX
(10.11 MIN 10.49 MAX) 0.092 MIN 0.094 MAX
(2.34 MIN 0.81 MAX)
0.291 MIN 0.300 MAX
(7.39 MIN 7.62 MAX)
0.007 MIN 0.013 MAX
(0.18 MIN 0.33 MAX)
0.015 MIN 0.050 MAX
(0.38 MIN 1.27 MAX)
0.393 MIN 0.420 MAX
(9.98 MIN 10.67 MAX)
0.26 MIN 0.032 MAX
(0.66 MIN 0.81 MAX)
DIMENSIONS ARE IN INCHES (mm)
LEAD COPLANARITY 0.004 MAX
PIN 1
FIGURE 12. DD-03182GP 16-PIN SURFACE MOUNT (SOIC) MECHANICAL OUTLINE
10
G-06/98-1M PRINTED IN THE U.S.A.
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by ILC Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New Yor k 11716-2482
For Technical Support - 1-800-DDC-5757 ext. 7402 or 7384
Headquarters - Tel: (516) 567-5600 ext. 7402 or 7384, Fax: (516) 567-7358
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World Wide Web - http://www.ilcddc.com
ILC DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NO. A5976
OTHER APPLICABLE DOCUMENTS
RTCA/DO-160D: Environmental Conditions and Test Procedure
for Airborne Equipment
ARINC Specification 429 Mark 33 Digital Information Transfer
System
ORDERING INFORMATION
DD-03182XX-XXXX – ARINC 429 Line Driver
T = Tape and Reel (GP and VP only)
Options:
0 = With resistors and fuses
1 = With resistors, no fuses*
Screening:
0 = Standard DDC Procedures
2 = Burn-in (ceramic only)
Temperature Range:
1 = -55 to +125°C (ceramic only)
2 = -40 to +85°C
9 = -55 to +85°C (GP package only)
Package Style/Type:
DC = 16-pin ceramic DIP
GP = 16-pin plastic SOIC
PP = 28-pin plastic PLCC
VP = 14-Pin plastic SOIC
*VP version only.