April 1994
DATA SHEET
Edition 1.0
1
Copyright1994 by FUJITSU LIMITED
Voltage of VCC supply relative to VSS
VSS, VOT
Parameter Symbol Value Unit
Short Circuit Output Current
Power Dissipation
Storage Temperature
–1 to +7
–1 to +7
50
V
V
W
mA
C
°
V
PD
––
1.0
–55 to +125
CMOS 1,048,576 x 4 bit Fast Page Mode Dynamic RAM
The Fujitsu MB814400D is a fully decoded CMOS Dynamic RAM (DRAM) that contains
4,194,304 memory cells accessible in 4–bit increments. The MB814400D features a
”fast page” mode of operation whereby high–speed random access of up to 1,024–bits
of data within the same row can be selected. The MB814400D DRAM is ideally suited for
mainframe, buffers, hand–held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic
requirements of the design. Since the standby current of the MB814400D is very small,
the device can be used as a non–volatile memory in equipment that uses batteries for
primary and/or auxiliary power.
The MB814400D is fabricated using silicon gate CMOS and Fujitsu’s advanced
four–layer polysilicon process. This process, coupled with three–dimensional stacked
capacitor memory cells, reduces the possibility of soft errors and extends the time
interval between memory refreshes. Clock timing requirements for the MB814400D are
not critical and all inputs are TTL compatible.
NOTE: Permanent device damage may occur if the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure
to absolute maximum rating conditions for extended periods may affect device
reliability.
ABSOLUTE MAXIMUM RATINGS (see NOTE)
PRODUCT LINE & FEATURES
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit.
MB814400D
-60/-70
CMOS 1M X 4 BIT FAST PAGE MODE DYNAMIC RAM
Parameter MB814400D–60
RAS Access Time
Randam Cycle Time
Address Access Time
CAS Access Time
Fast Page Mode Cycle Time
Operating current
Standby current
60ns max.
110ns min.
30ns max.
15ns max.
40ns min.
605mW max.
70ns max.
125ns min.
35ns max.
20ns max.
45ns min.
550mW max.
11mW max. (TTL level) / 5.5mW max. (CMOS level)
MB814400D–70
Low Power
Dissipation
•1,048,576 words x 4Bit organization
•All input and output are TTL compatible
•Silicon gate, CMOS, 3D–Stacked
capacitor Cell
•1024 refresh cycles every 16.4ms
•Early write or OE controlled write capabili-
ty
•RAS only, CAS–before–RAS, or Hidden
Refresh
•Fast page Mode, Read–Modify–Write
capability
•On chip substrate bias generator for high
performance
Voltage at any pin relative to Vss
CC
TSTG
Package and Ordering Information
– 26–pin plastic (300mil) SOJ,
order as MB814400D–xxPJN
(LCC–26P–M04)
Plastic SOJ Package
