12-Bit Monitor and Control System with Multichannel
ADC, DACs, Temperature Sensor, and Current Sense
Data Sheet
AD7294
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
FEATURES
12-bit SAR ADC with 3 μs conversion time
4 uncommitted analog inputs
Differential/single-ended
VREF, 2 × VREF input ranges
2 high-side current sense inputs
5 V to 59.4 V operating range
0.5% max gain error
±200 mV input range
2 external diode temperature sensor inputs
−55°C to +150°C measurement range
±2°C accuracy
Series resistance cancellation
1 internal temperature sensor
±2°C accuracy
Built-in monitoring features
Minimum/maximum recorder for each channel
Programmable alert thresholds
Programmable hysteresis
Four 12-bit monotonic 15 V DACs
5 V span, 0 V to 10 V offset
8 μs settling time
10 mA sink and source capability
Power-on resets (POR) to 0 V
Internal 2.5 V reference
2-wire fast mode I2C interface
Temperature range: −40°C to +105°C
Package type: 64-lead TQFP or 56-lead LFCSP
APPLICATIONS
Cellular base stations
GSM, EDGE, UMTS, CDMA, TD-SCDMA, W-CDMA, WiMAX
Point-to-multipoint and other RF transmission systems
12 V, 24 V, 48 V automotive applications
Industrial controls
GENERAL DESCRIPTION
The AD7294 contains all the functions required for general-
purpose monitoring and control of current, voltage, and
temperature integrated into a single-chip solution. The part
includes low voltage (±200 mV) analog input sense amplifiers
for current monitoring across shunt resistors, temperature sense
inputs, and four uncommitted analog input channels multiplexed
into a SAR analog-to-digital converter (ADC) with a 3 μs conver-
sion time. A high accuracy internal reference is provided to drive
both the digital-to-analog converter (DAC) and ADC. Four 12-bit
DACs provide the outputs for voltage control. The AD7294 also
includes limit registers for alarm functions. The part is designed
on Analog Devices, Inc., high voltage DMOS process for high
voltage compliance, 59.4 V on the current sense inputs, and up
to a 15 V DAC output voltage.
The AD7294 is a highly integrated solution that offers all the
functionality necessary for precise control of the power amplifier
in cellular base station applications. In these types of applications,
the DACs provide 12-bit resolution to control the bias currents
of the power transistors. Thermal diode-based temperature sensors
are incorporated to compensate for temperature effects. The ADC
monitors the high-side current and temperature. All this function-
ality is provided in a 64-lead TQFP or a 56-lead LFCSP operating
over a temperature range of −40°C to +105°C.
AD7294 Data Sheet
Rev. H | Page 2 of 48
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications ..................................................................................... 5
DAC Specifications....................................................................... 5
ADC Specifications ...................................................................... 6
General Specifications ................................................................. 8
Timing Characteristics ................................................................ 9
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 19
DAC Terminology ...................................................................... 19
ADC Terminology ...................................................................... 19
Theory of Operation ...................................................................... 20
ADC Overview ........................................................................... 20
ADC Transfer Functions ........................................................... 20
Analog Inputs .............................................................................. 20
Current Sensor ............................................................................ 22
Analog Comparator Loop ......................................................... 23
Temperature Sensor ................................................................... 24
DAC Operation ........................................................................... 25
ADC and DAC Reference .......................................................... 25
VDRIVE Feature .............................................................................. 26
Register Setting ............................................................................... 27
Address Pointer Register ........................................................... 27
Command Register (0x00) ........................................................ 28
Result Register (0x01) ................................................................ 28
TSENSE1, TSENSE2 Result Registers (0x02 and 0x03) ....................... 29
TSENSEINT Result Register (0x04).............................................. 29
DACA, DACB, DACC, DACD, Registers (0x01 to 0x04) ............... 30
Alert Status Register A (0x05), Register B (0x06), and
Register C (0x07) ........................................................................ 30
Channel Sequence Register (0x08) .......................................... 30
Configuration Register (0x09) .................................................. 31
Power-Down Register (0x0A) ................................................... 32
DATAHIGH/DATALOW Registers: 0x0B, 0x0C (VIN0); 0x0E, 0x0F
(VIN1); 0x11, 0x12 (VIN2); 0x14, 0x15 (VIN3) .............................. 32
Hysteresis Registers: 0x0D (VIN0), 0x10 (VIN1), 0x13 (VIN2),
0x16 (VIN3) .................................................................................. 32
TSENSE Offset Registers (0x26 and 0x27) ................................... 33
I2C Interface .................................................................................... 34
General I2C Timing .................................................................... 34
Serial Bus Address Byte ............................................................. 35
Interface Protocol ....................................................................... 35
Modes of Operation ....................................................................... 39
Command Mode ........................................................................ 39
Autocycle Mode .......................................................................... 40
Alerts and Limits Theory .............................................................. 41
Alert_Flag Bit .............................................................................. 41
Alert Status Registers ................................................................. 41
DataHIGH and DataLOW Monitoring Features ............................ 41
Hysteresis ..................................................................................... 42
Applications Information .............................................................. 43
Base Station Power Amplifier Monitor and Control ............. 43
Gain Control of Power Amplifier ............................................. 44
Layout and Configuration ............................................................. 45
Power Supply Bypassing and Grounding ................................ 45
Outline Dimensions ....................................................................... 46
Ordering Guide .......................................................................... 47
Data Sheet AD7294
Rev. H | Page 3 of 48
REVISION HISTORY
1/12—Rev. G to Rev. H
Changes to Table 2 ............................................................................ 6
11/11—Rev. F to Rev. G
Change to DAC Output Characteristics Parameter of
Table 1 ................................................................................................. 5
Deleted DAC HIGH-Z Pin Leakage from Table 3 ........................ 8
Change to Figure 4 .......................................................................... 11
Changes to Table 7 .......................................................................... 12
Deleted Figure 47; Renumbered Sequentially ............................. 25
Deleted High Impedance Input Pin Section ................................ 26
11/10—Rev. E to Rev. F
Change to Table 2, Dynamic Performance, Spurious-Free
Dynamic Range (SFDR) ................................................................... 6
10/10—Rev. D to Rev. E
Change to Reflow Temperature, Table 5 ...................................... 10
5/10—Rev. C to Rev. D
Added 56-Lead LFCSP ...................................................... Universal
Change to Features Section and General Description Section ... 1
Changes to Table 2 ............................................................................ 6
Changes to Table 6 .......................................................................... 10
Added Figure 4 ................................................................................ 11
Changes to Table 7 .......................................................................... 12
Changes to Command Register Section ...................................... 28
Changes to Autocycle Mode Section ............................................ 40
Updated Outline Dimensions........................................................ 47
Changes to Ordering Guide ........................................................... 48
7/09—Rev. B to Rev. C
Changes to Table 4 Endnotes ........................................................... 8
4/09—Rev. A to Rev. B
Changes to Table 2 ............................................................................ 6
Changes to Table 3 ............................................................................ 7
Changes to Table 23 ........................................................................ 29
3/09—Rev. 0 to Rev. A
Changes to Configuration Register (0x09) Section .................... 29
Changes to Table 23 and Table 24 ................................................. 29
Changes to Table 27 ........................................................................ 30
Changes to Autocycle Mode Section ............................................ 38
Change to Alert Status Registers Section ..................................... 39
Changes to DATAHIGH and DATALOW Monitoring Features
Section .............................................................................................. 39
1/08—Revision 0: Initial Version
AD7294 Data Sheet
Rev. H | Page 4 of 48
FUNCTIONAL BLOCK DIAGRAM
05747-001
LIMIT
REGISTERS
MUX
CONTROL LOGIC
I
2
C INTERF ACE
PROTOCOL
TEMP
SENSOR
HIGH SI DE
CURRENT
SENSE
HIGH SI DE
CURRENT
SENSE
REF
OUT
/
REF
IN
DAC
T1 T2
TO LOAD
RS1(+) RS2(+) RS2(–)RS1(–)
D1+
D2+
D1–
D2–
AV
DD
(1 T O 6) AGND
(1 T O 7) DAC OUT
V+ AB/ CD
AD7294
REF
OUT
/
REF
IN
ADC
V
PP
(1 T O 2)
ALERT/
BUSY
DCAP
V
REF
10.41
I
SENSE
1
OVERRANGE
I
SENSE
2
OVERRANGE
R
SENSE
12-BIT
ADC
AS0
AS1
AS2
SCL
SDA
DV
DD
DGND
(1 T O 2)
V
IN
0
V
IN
1
V
IN
2
V
IN
3
12-BIT
DAC
100kΩ 200kΩ
100kΩ 200kΩ
12-BIT
DAC
100kΩ 200kΩ
100kΩ 200kΩ
12-BIT
DAC
100kΩ 200kΩ
100kΩ 200kΩ
12-BIT
DAC
100kΩ 200kΩ
100kΩ 200kΩ
OFFSET IN A
V
OUT
B
OFFSET IN B
V
OUT
C
OFFSET IN C
V
OUT
D
OFFSET IN D
V
OUT
A
2.5V
REF
Figure 1.
Data Sheet AD7294
Rev. H | Page 5 of 48
SPECIFICATIONS
DAC SPECIFICATIONS
AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, internal 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; TA =−40°C to +105°C, unless
otherwise noted. DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V, OFFSET IN x is floating, therefore, the DAC output
span = 0 V to 5 V.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
ACCURACY
Resolution 12 Bits
Relative Accuracy (INL) ±1 ±3 LSB
Differential Nonlinearity (DNL) ±0.3 ±1 LSB Guaranteed monotonic
Zero-Scale Error 2.5 8 mV
Full-Scale Error of DAC and
Output Amplifier
15.51 mV DAC OUTV+ = 5.0 V
Full-Scale Error of DAC 2 mV DAC OUTV+ = 15.0 V
Offset Error ±8.575 mV Measured in the linear region, TA = −40°C to +105°C
±2 mV Measured in the linear region, TA = 25°C
Offset Error Temperature
Coefficient
±5 ppm/°C
Gain Error ±0.025 ±0.155 % FSR
Gain Temperature Coefficient ±5 ppm/°C
DAC OUTPUT CHARACTERISTICS
Output Voltage Span 0 2 × VREF V 0 V to 5 V for a 2.5 V reference
Output Voltage Offset 0 10 V The output voltage span can be positioned in the 0 V to
15 V range; if the OFFSET IN x is left floating, the offset
pin = 2/3 × V
REF
, giving an output of 0 V to 2 × V
REF
Offset Input Pin Range 0 5 VOUT = 3 VOFFSET − 2 × VREF + VDAC
DC Input Impedance2 75 kΩ 100 kΩ to VREF, and 200 kΩ to AGND, see Figure 48
Output Voltage Settling Time2 8 µs 1/4 to 3/4 change within 1/2 LSB, measured from last
SCL edge
Slew Rate2 1.1 V/µs
Short-Circuit Current2 40 mA Full-scale current shorted to ground
Load Current2 ±10 mA Source and/or sink within 200 mV of supply
Capacitive Load Stability2 10 nF RL = ∞
DC Output Impedance2 1 Ω
REFERENCE
Reference Output Voltage 2.49 2.5 2.51 V ±0.4% maximum @ 25°C, AVDD = DVDD = 4.5 V to 5.5 V
Reference Input Voltage Range 0 AVDD − 2 V
Input Current 100 125 µA VREF = 2.5 V
Input Capacitance2 20 pF
VREF Output Impedance2 25 Ω
Reference Temperature
Coefficient
10 25 ppm/°C
1 This value indicates that the DAC output amplifiers can output voltages 15.5 mV below the DAC OUTV+ supply. If higher DAC OUTV+ supply voltages are used, the
full-scale error of the DAC is typically 2 mV with no load.
2 Samples are tested during initial release to ensure compliance; they are not subject to production testing.
AD7294 Data Sheet
Rev. H | Page 6 of 48
ADC SPECIFICATIONS
AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, V REF = 2.5 V internal or external; VDRIVE = 2.7 V to 5.5 V; VPP = AVDD to 59.4 V;
TA = −40°C to +105°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity (INL)1 ±0.5 ±1 LSB Differential mode
±0.5 ±1.5 LSB Single-ended or pseudo differential mode
Differential Nonlinearity (DNL)1 ±0.5 ±0.99 LSB Differential, single-ended, and pseudo differential
modes
Single-Ended Mode
Offset Error ±1 ±7 LSB
Offset Error Match ±0.4 LSB
Gain Error ±0.5 ±2.5 LSB
Gain Error Match ±0.4 LSB
Differential Mode
Positive Gain Error ±1 LSB
Positive Gain Error Match ±0.5 LSB
Zero Code Error ±3 LSB
Zero Code Error Match ±0.5 LSB
Negative Gain Error ±1 LSB
Negative Gain Error Match ±0.5 LSB
CONVERSION RATE
Conversion Time2 3 μs
Autocycle Update Rate2 50 μs
Throughput Rate 22.22 kSPS fSCL = 400 kHz
ANALOG INPUT3
Single-Ended Input Range 0 VREF V 0 V to VREF mode
0 2 × VREF V 0 V to 2 × VREF mode
Pseudo Differential Input Range: V
IN+
− V
IN−
4 0
V
REF
0 V to V
REF
mode
0 2 × VREF 0 V to 2 × VREF mode
Fully Differential Input Range: VIN+ − VIN− −VREF +VREF 0 V to VREF mode
−2 × VREF +2 × VREF 0 V to 2 × VREF mode
Input Capacitance2 30 pF
DC Input Leakage Current ±1 µA
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)1 73 dB fIN = 10 kHz sine wave; differential mode
72 dB fIN = 10 kHz sine wave; single-ended and pseudo
differential modes
Signal-to-Noise + Distortion (SINAD) Ratio1 71.5 dB fIN = 10 kHz sine wave; differential mode
72.5 dB fIN = 10 kHz sine wave; single-ended and pseudo
differential modes
Total Harmonic Distortion (THD)1 −81 dB fIN = 10 kHz sine wave; differential mode
−79 dB fIN = 10 kHz sine wave; single-ended and pseudo
differential modes
Spurious-Free Dynamic Range (SFDR)1 −81 dB fIN = 10 kHz sine wave; differential mode
−79 fIN = 10 kHz sine wave; single-ended and pseudo
differential modes
Channel-to-Channel Isolation2 −90 dB fIN = 10 kHz to 40 kHz
Data Sheet AD7294
Rev. H | Page 7 of 48
Parameter Min Typ Max Unit Test Conditions/Comments
TEMPERATURE SENSOR—INTERNAL
Operating Range −40 +105 °C
Accuracy ±2 °C Internal temperature sensor, TA = −30°C to +90°C
±2.5 °C Internal temperature sensor, TA = −40°C to +105°C
Resolution 0.25 °C LSB size
Update Rate 5 ms
TEMPERATURE SENSOR—EXTERNAL External transistor is 2N3906
Operating Range −55 +150 °C Limited by external diode
Accuracy ±2 °C TA = TDIODE = −40°C to +105°C
Resolution 0.25 °C LSB size
Low Level Output Current Source2 8 µA
Medium Level Output Current Source2 32 µA
High Level Output Current Source2 128 µA
Maximum Series Resistance (RS) for
External Diode2
100 Ω For < ±0.5°C additional error, CP = 0, see Figure 31
Maximum Parallel Capacitance (CP) for
External Diode2
1 nF RS = 0, see Figure 30
CURRENT SENSE VPP = AVDD to 59.4 V
VPP Supply Range AVDD 59.4 V
Gain 12.4375 12.5 12.5625 Gain of 12.5 gives a gain error = 0.5% maximum;
delivers ±200 mV range with +2.5 V reference
RS(+)/RS(−) Input Bias Current 25 32 µA
CMRR/PSRR2 80 dB Inputs shorted to VPP
Offset Error ±50 ±340 µV
Offset Drift 1 µV/°C
Amplifier Peak-To-Peak Noise2 400 µV Referred to input
VPP Supply Current 0.18 0.25 mA VPP = 59.4 V
REFERENCE
Reference Output Voltage 2.49 2.51 V ±0.2% maximum at 25°C only
Reference Input Voltage Range 0.1 4.1 V For four uncommitted ADCs
1 AVDD − 2 For current sense
DC Leakage Current ±2 μA
VREF Output Impedance2 25 Ω
Input Capacitance2 20 pF
Reference Temperature Coefficient 10 25 ppm/°C
1 See the Terminology section for more details.
2 Sampled during initial release to ensure compliance, not subject to production testing.
3 VIN+ or VIN− must remain within GND/VDD.
4 VIN− = 0 V for specified performance. For full input range on VIN−, see Figure 40.
AD7294 Data Sheet
Rev. H | Page 8 of 48
GENERAL SPECIFICATIONS
AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, V REF = 2.5 V internal or external; VDRIVE = 2.7 V to 5.5 V; VPP = AVDD to 59.4 V;
DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V;
TA = −40°C to +105°C, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, VIH 0.7 VDRIVE V SDA, SCL only
Input Low Voltage, V
0.3 V
DRIVE
V SDA, SCL only
Input Leakage Current, IIN ±1 µA
Input Hysteresis, VHYST 0.05 VDRIVE V
Input Capacitance, CIN 8 pF
Glitch Rejection 50 ns Input filtering suppresses noise spikes of less
than 50 ns
I2C® Address Pins Maximum External
Capacitance if Floating
30 pF Tristate input
LOGIC OUTPUTS
SDA, ALERT SDA and ALERT/BUSY are open-drain outputs
Output Low Voltage, VOL 0.4 V ISINK = 3 mA
0.6 V ISINK = 6 mA
Floating-State Leakage Current ±1 µA
Floating-State Output Capacitance 8 pF
ISENSE OVERRANGE ISENSE OVERRANGE is a push-pull output
Output High Voltage, VOH VDRIVE − 0.2 V ISOURCE = 200 µA for push-pull outputs
Output Low Voltage, VOL 0.2 V ISINK = 200 µA for push-pull outputs
Overrange Setpoint V
FS
V
FS
× 1.2 mV V
FS
= ±V
REF
ADC/12.5
POWER REQUIREMENTS
VPP AVDD 59.4 V
AVDD 4.5 5.5 V
V(+) 4.5 16.5 V
DVDD 4.5 5.5 V Tie DVDD to AVDD
VDRIVE 2.7 5.5 V
IDD Dynamic 5.3 6.5 mA AVDD + DVDD + VDRIVE, DAC outputs unloaded
DAC OUTV+ x, IDD 0.6 1.2 mA @ midscale output voltage, DAC outputs
unloaded
Power Dissipation 70 105 mW
Power-Down
IDD 0.5 1 µA For each AVDD and VDRIVE
DIDD 1 16.5 µA
DAC OUTV+ x, IDD 35 60 µA
Power Dissipation 2.5 mW
Data Sheet AD7294
Rev. H | Page 9 of 48
TIMING CHARACTERISTICS
I2C Serial Interface
AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, V REF = 2.5 V internal or external; VDRIVE = 2.7 V to 5.5 V; VPP = AVDD to 59.4 V;
DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; TA =
−40°C to +105°C, unless otherwise noted.
Table 4.
Parameter1 Limit at TMIN, TMAX Unit Description
f
SCL
400 kHz max SCL clock frequency
t1 2.5 µs min SCL cycle time
t2 0.6 µs min tHIGH, SCL high time
t3 1.3 µs min tLOW, SCL low time
t4 0.6 µs min tHD,STA, start/repeated start condition hold time
t
5
100 ns min t
SU, DAT
, data setup time
t6 0.9 µs max tHD, DAT, data hold time
0 µs min tHD,DAT , data hold time
t7 0.6 µs min tSU,STA, setup time for repeated start
t8 0.6 µs min tSU,STO, stop condition setup time
t9 1.3 µs min tBUF, bus free time between a stop and a start condition
t
10
300 ns max t
R
, rise time of SCL and SDA when receiving
0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11 300 ns max tF, fall time of SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS compatible)
300 ns max tF, fall time of SCL and SDA when receiving
20 + 0.1Cb2 ns min tF, fall time of SCL and SDA when transmitting
C
b
400 pF max Capacitive load for each bus line
1 See Figure 2.
2 Cb is the total capacitance in pF of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.
Timing and Circuit Diagrams
START
CONDITION REPEATED
START
CONDITION
STOP
CONDITION
t9t3
t1
t11 t4
t10
t4t5t7
t6t8
t2
SDA
SCL
05747-002
Figure 2. I2C-Compatible Serial Interface Timing Diagram
C
L
50pF
TO OUTPUT PIN V
OH
(MIN) OR
V
OL
(MAX)
200µA
200µA
I
OL
I
OH
05747-003
Figure 3. Load Circuit for Digital Output
AD7294 Data Sheet
Rev. H | Page 10 of 48
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.1
Table 5.
Parameter Rating
VPPx to AGND −0.3 V to +70 V
AVDDx to AGND −0.3 V to +7 V
DAC OUTV+ AB to AGND −0.3 V to +17 V
DAC OUTV+ CD to AGND −0.3 V to +17 V
DVDD to DGND −0.3 V to +7 V
VDRIVE to OPGND −0.3 V to +7 V
Digital Inputs to OPGND −0.3 V to VDRIVE + 0.3 V
SDA/SCL to OPGND −0.3 V to +7 V
Digital Outputs to OPGND −0.3 V to VDRIVE + 0.3 V
RS(+)/RS(−) to VPPx VPP − 0.3 V to VPP + 0.3 V
REF
OUT
/REF
IN
ADC to AGND −0.3 V to AV
DD
+ 0.3 V
REFOUT/REFIN DAC to AGND −0.3 V to AVDD + 0.3 V
OPGND to AGND −0.3 V to +0.3 V
OPGND to DGND −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
VOUTx to AGND −0.3 V to DAC OUTV(+) + 0.3 V
Analog Inputs to AGND −0.3 V to AV
DD
+ 0.3 V
Operating Temperature Range
B Version −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ Max) 150°C
ESD Human Body Model 1 kV
Reflow Soldering Peak
Temperature
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
To conform with IPC 2221 industrial standards, it is advisable
to use conformal coating on the high voltage pins.
THERMAL RESISTANCE
Table 6. Thermal Resistance
Package Type θJA θJC Unit
64-Lead TQFP 54 16 °C/W
56-Lead LFCSP 21 2 °C/W
ESD CAUTION
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Data Sheet AD7294
Rev. H | Page 11 of 48
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
IN
0
V
IN
1
V
IN
2
V
IN
3
AGND3
AV
DD
3
REF
OUT
/REF
IN
DAC
NC
DGND
DGND
I
SENSE
2 OV E RRANGE
I
SENSE
1 OV E RRANGE
DV
DD
DGND
V
DRIVE
OPGND
SCL
SDA
AS0
AS1
AS2
ALERT/BUSY
AGND5
NC
39
38
37
41
40
36
35
34
33
42
43
44
45
46
47
48
10
11
12
8
9
13
14
15
16
7
6
5
4
3
2
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC
V
PP
2
V
PP
1
RS1(–)
RS1(+)
NC
AV
DD
5
AV
DD
6
AGND6
AGND7
DCAP
REF
OUT
/REF
IN
ADC
NC
RS2(–)
RS2(+)
NC
AV
DD
1
AGND1
AGND2
AV
DD
2
D2–
D2+
D1+
D1–
PIN 1
INDICATOR
NC = NO CONNECT
AD7294
TQFP
TOP VI EW
(No t t o Scal e)
DAC OUT GND CD
NC
NC
OFFSET IN A
OFFSET IN B
OFFSET IN C
OFFSET IN D
V
OUT
A
DAC OUT GND AB
DAC OUTV+ AB
V
OUT
B
V
OUT
C
V
OUT
D
AGND 4
AV
DD
4
DAC OUTV+ CD
05747-005
Figure 4. TQFP Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
56
55
54
53
52
51
50
49
48
47
46
45
44
43
AD7294
LFCSP
TOP VIEW
(No t t o Scal e)
DGND
ISENSE2 O V E RRANGE
ISENSE1 O V E RRANGE
DVDD
DGND
VDRIVE
OPGND
SCL
SDA
AS0
AS1
AS2
ALERT/BUSY
AGND5
DAC OUT GND CD
OFFSET IN B
OFFSET IN C
OFFSET IN D
V
OUT
A
DAC OUT GND AB
OFFSET IN A
DAC OUTV+ AB
V
OUT
B
V
OUT
C
V
OUT
D
AGND4
AV
DD
4
DAC OUTV+ CD
AGND3
AVDD3
REFOUT/REFIN DAC
NC
RS2(–)
RS2(+)
AVDD1
AGND1
AGND2
AVDD2
D1(–)
D1(+)
D2(+)
D2(–)
VIN0
VIN1
VIN2
VIN3
VPP2
VPP1
RS1(–)
RS1(+)
NC
AVDD5
AGND6
AGND7
DCAP
REFOUT/REFIN ADC
PIN 1
INDICATOR
05747-004
NOTES
1. NC = NO CO NNE C T.
2. CONNECT THE EXPOSED PAD TO T HE GRO UND P LANE O F
THE P CB US ING M ULTIPLE VIAS.
Figure 5. LFCSP Pin Configuration
AD7294 Data Sheet
Rev. H | Page 12 of 48
Table 7. Pin Function Descriptions
TQFP Pin No. LFCSP Pin No. Mnemonic Description
2, 61 1, 54 RS2(−), RS1(−) Connection for External Shunt Resistor.
3, 60 2, 53 RS2(+), RS1(+) Connection for External Shunt Resistor.
1, 4, 16, 17, 32,
33, 59, 64
3, 52 NC No Connection. Do not connect these pins.
5, 8, 14, 25, 56, 57 4, 7, 13, 22, 50 AVDD1 to AVDD6
for TQFP; AVDD1
to AVDD4 for
LFCSP
Analog Supply Pins. The operating range is 4.5 V to 5.5 V. These pins provide
the supply voltage for all the analog circuitry on the AD7294. Connect the
AVDD and DVDD pins together to ensure that all supply pins are at the same
potential. This supply should be decoupled to AGND with one 10 µF tantalum
capacitor and a 0.1 µF ceramic capacitor for each AVDD pin.
6, 7, 13, 24, 34,
55, 58
5, 6 12, 21, 29, 49,
51
AGND1 to
AGND7
Analog Ground. Ground reference point for all analog circuitry on the AD7294.
Refer all analog input signals and any external reference signal to this AGND
voltage. Connect all seven of these AGND pins to the AGND plane of the
system. Note that AGND5 is a DAC ground reference point and should be used
as a star ground for circuitry being driven by the DAC outputs. Ideally, the
AGND and DGND voltages should be at the same potential and must not be
more than 0.3 V apart, even on a transient basis.
9, 12 8, 11 D2(−), D1(−) Temperature Sensor Analog Input. These pins are connected to the external
temperature sensing transistor. See Figure 46 and Figure 47.
10, 11 9, 10 D2(+), D1(+) Temperature Sensor Analog Input. These pins are connected to the external
temperature sensing transistor. See Figure 46 and Figure 47.
15 14 REFOUT/REFIN DAC DAC Reference Output/Input Pin. The REFOUT/REFIN DAC pin is common to all
four DAC channels. On power-up, the default configuration of this pin is
external reference (REFIN). Enable the internal reference by writing to the
power-down register; see Table 27. Decoupling capacitors (220 nF
recommended) are connected to this pin to decouple the reference buffer.
Provided the output is buffered, the on-chip reference can be taken from this
pin and applied externally to the rest of a system. A maximum external
reference voltage of AVDD − 2 V can be supplied to the REFOUT portion of the
REFOUT/REFIN DAC pin.
18, 23, 26, 31 15, 20 23,28 OFFSET IN A to
OFFSET IN D
DAC Analog Offset Input Pins. These pins set the desired output range for each
DAC channel. The DACs have an output voltage span of 5 V, which can be
shifted from 0 V to 5 V to a maximum output voltage of 10 V to 15 V by
supplying an offset voltage to these pins. These pins can be left floating, in
which case decouple them to AGND with a 100 nF capacitor.
19, 22, 27, 30 16, 19, 24, 27 VOUT A to VOUT D Buffered Analog DAC Outputs for Channel A to Channel D. Each DAC analog
output is driven from an output amplifier that can be offset using the OFFSET
IN x pin. The DAC has a maximum output voltage span of 5 V that can be level
shifted to a maximum output voltage level of 15 V. Each output is capable of
sourcing and sinking 10 mA and driving a 10 nF load.
20, 29 17, 26 DAC OUT GND
AB, DAC OUT
GND CD
Analog Ground. Analog ground pins for the DAC output amplifiers on VOUTA
and VOUTB, and VOUTC and VOUTD, respectively.
21, 28 18, 25 DAC OUTV+ AB,
DAC OUTV+ CD
Analog Supply. Analog supply pins for the DAC output amplifiers on VOUTA and
VOUTB, and VOUTC and VOUTD, respectively. The operating range is 4.5 V to 16.5 V.
35 30 ALERT/BUSY Digital Output. Selectable as an alert or busy output function in the
configuration register. This is an open-drain output. An external pull-up
resistor is required.
When configured as an alert, this pin acts as an out-of-range indicator and
becomes active when the conversion result violates the DATAHIGH or DATALOW
register values. See the Alert Status Registers section.
When configured as a busy output, this pin becomes active when a conversion
is in progress.
38, 37, 36 33, 32, 31 AS0, AS1, AS2 Digital Logic Input. Together, the logic state of these inputs selects a unique
I2C address for the AD7294. See Table 34 for details.
39 34 SDA Digital Input/Output. Serial bus bidirectional data; external pull-up resistor
required.
Data Sheet AD7294
Rev. H | Page 13 of 48
TQFP Pin No. LFCSP Pin No. Mnemonic Description
40 35 SCL Serial I2C Bus Clock. The data transfer rate in I2C mode is compatible with both
100 kHz and 400 kHz operating modes. Open-drain input; external pull-up
resistor required.
41 36 OPGND Dedicated Ground Pin for I2C Interface.
42 37 VDRIVE Logic Power Supply. The voltage supplied at this pin determines at what
voltage the interface operates. Decouple this pin to DGND. The voltage range
on this pin is 2.7 V to 5.5 V and may be different to the voltage level at AVDD
and DVDD, but should never exceed either by more than 0.3 V. To set the input
and output thresholds, connect this pin to the supply to which the I2C bus is
pulled.
43, 47, 48 38, 42 DGND Digital Ground. This pin is the ground for all digital circuitry.
44 39 DVDD Logic Power Supply. The operating range is 4.5 V to 5.5 V. These pins provide
the supply voltage for all the digital circuitry on the AD7294. Connect the AVDD
and DVDD pins together to ensure that all supply pins are at the same potential.
Decouple this supply to DGND with a10 µF tantalum capacitor and a 0.1 µF
ceramic capacitor.
46, 45 41, 40 ISENSE1
OVERRANGE,
ISENSE2
OVERRANGE
Fault Comparator Outputs. These pins connect to the high-side current sense
amplifiers.
49, 50, 51, 52 43, 44, 45, 46 VIN3 to VIN0 Uncommitted ADC Analog Inputs. These pins are programmable as four
single-ended channels or two true differential analog input channel pairs. See
Table 1 and Table 13 for more details.
53 47 REFOUT/REFIN ADC ADC Reference Input/Output Pin. The REFOUT/REFIN ADC pin provides the
reference source for the ADC. Upon power-up, the default configuration of this
pin is external reference (REFIN). Enable the internal reference by writing to the
power-down register; see Table 27. Connect decoupling capacitors (220 nF
recommended) to this pin to decouple the reference buffer. Provided the
output is buffered, the on-chip reference can be taken from this pin and
applied externally to the rest of a system. A maximum external reference
voltage of 2.5 V can be supplied to the REFOUT portion of the REFOUT/REFIN
ADC pin.
54 48 DCAP External Decoupling Capacitor Input for Internal Temperature Sensor.
Decouple this pin to AGND using a 0.1 μF capacitor. In normal operation, the
voltage is typically 3.7 V.
62, 63 55, 56 VPP1, VPP2 Current Sensor Supply Pins. Power supply pins for the high-side current sense
amplifiers. Operating range is from AVDD to 59.4 V. Decouple this supply to
AGND. See the Current Sense Filtering section.
EP Exposed Pad The exposed pad is located on the underside of the package. Connect the
exposed pad to the ground plane of the PCB using multiple vias.
AD7294 Data Sheet
Rev. H | Page 14 of 48
TYPICAL PERFORMANCE CHARACTERISTICS
20
0
–20
–40
–60
–80
–100
–120 0100008000600040002000
AMPLITUDE ( dB)
FRE QUENCY ( kHz )
8192 PO INT FF T
AVDD = DVDD = 5V
VDRIVE = 5V, VREF RANG E
FSAMPLE = 22.22kSP S
FIN = 10kHz, FSCLK = 400kHz
SINGLE ENDED
SNR = 71d B, T HD = –82dB
05747-088
Figure 6. Signal-to-Noise Ratio Single-Ended, VREF Range
05747-089
20
0
–20
–40
–60
–80
–100
–120 0100008000600040002000
AMPLITUDE ( dB)
FRE QUENCY ( kHz )
8192 PO INT FF T
AVDD = DVDD = 5V
VDRIVE = 5V, 2VREF RANGE
FSAMPLE = 22.22kSP S
FIN = 10kHz, FSCLK = 400kHz
SINGLE ENDED
SNR = 72d B, T HD = –80dB
Figure 7. Signal-to-Noise Ratio Single-Ended, 2 × VREF Range
05747-087
20
0
–20
–40
–60
–80
–100
–120 0100008000600040002000
AMPLITUDE ( dB)
FRE QUENCY ( kHz )
8192 PO INT FF T
AVDD = DVDD = 5V
VDRIVE = 5V, VREF RANG E
FSAMPLE = 22.22kSP S
FIN = 10kHz, FSCLK = 400kHz
DIFFERENTIAL
SNR = 72d B, T HD = –86dB
Figure 8. Signal-to-Noise Ratio Differential, VREF Range
05747-086
20
0
–20
–40
–60
–80
–100
–120 0100008000600040002000
AMPLITUDE ( dB)
FRE QUENCY ( kHz )
8192 PO INT FF T
AV
DD
= DV
DD
= 5V
V
DRIVE
= 5V, 2V
REF
RANGE
F
SAMPLE
= 22.22kS P S
F
IN
= 10kHz, F
SCLK
= 400kHz
DIFFERENTIAL
SNR = 73d B, T HD = –82dB
Figure 9. Signal-to-Noise Ratio Differential, 2 × VREF Range
1.0
0.8
0.4
0.6
0.2
0
–0.4
–1.0
–0.8
–0.2
–0.6
INL (LSB)
CODE
05747-077
256 51207681024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
T
A
= 25° C
V
DRIVE
= 5V, V
REF
RANGE
V
REF
= 2.5V
V
DD
= 5V
SINGLE-ENDED
Figure 10. ADC INL Single-Ended, VREF Range
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.8
0.4
0.6
DNL ( LSB)
CODE
T
A
= 25° C
V
DRIVE
= 5V, V
REF
RANGE
V
REF
= 2.5V
V
DD
= 5V
SINGLE-ENDED
256 51207681024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
05747-072
Figure 11. ADC DNL Single-Ended, VREF Range
Data Sheet AD7294
Rev. H | Page 15 of 48
1.0
0.8
0.4
0.6
0.2
0
–0.4
–1.0
–0.8
–0.2
–0.6
INL (LSB)
CODE
256 51207681024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
T
A
= 25° C
V
DRIVE
= 5V, 2V
REF
RANGE
V
REF
= 2.5V
V
DD
= 5V
SINGLE-ENDED
05747-078
Figure 12. ADC INL Single-Ended, 2 × VREF Range
05747-073
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.8
0.4
0.6
DNL ( LSB)
CODE
T
A
= 25° C
V
DRIVE
= 5V, 2V
REF
RANGE
V
REF
= 5V
V
DD
= 5V
SINGLE-ENDED
256 51207681024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
Figure 13. ADC DNL Single-Ended, 2 × VREF Range
05747-075
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.8
0.4
0.6
INL (LSB)
CODE
TA = 25° C
VDRIVE = 5V, VREF RANG E
VREF = 2. 5V
VDD = 5V
DIFFERENTIAL
256 51207681024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
Figure 14. ADC INL Differential, VREF Range
05747-076
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.8
0.4
0.6
INL (LSB)
CODE
T
A
= 25° C
V
DRIVE
= 5V, V
REF
RANGE
V
REF
= 5V
V
DD
= 5V
DIFFERENTIAL
256 51207681024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
Figure 15. ADC INL Differential, VREF Range
T
A
= 25° C
V
REF
= 2.5V
V
DD
= 5V
DIFFERENTIAL
05747-070
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.8
0.4
0.6
DNL ( LSB)
CODE
T
A
= 25° C
V
DRIVE
= 5V, 2V
REF
RANGE
V
REF
= 2.5V
V
DD
= 5V
DIFFERENTIAL
256 51207681024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
Figure 16. ADC DNL Differential, 2 × VREF Range
05747-071
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.8
0.4
0.6
DNL ( LSB)
CODE
TA = 25° C
VDRIVE = 5V, 2VREF RANGE
VREF = 5V
VDD = 5V
DIFFERENTIAL
256 51207681024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
Figure 17. ADC DNL Differential, 2 × VREF Range
AD7294 Data Sheet
Rev. H | Page 16 of 48
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5 0 654321
INL (LSB)
REFERENCE VOLT AGE (V)
MI N INL
MAX INL
TA = 25° C
VDRIVE = 5V, VREF RANG E
VDD = 5V
SINGLE-ENDED
I2C MO DE 400kHz
05747-093
Figure 18. ADC INL vs. Reference Voltage
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6 0 654321
DNL ( LSB)
REFERENCE VOLT AGE (V)
MI N DNL
MAX DNL
TA = 25° C
VDRIVE = 5V, VREF RANG E
VDD = 5V
SINGLE-ENDED
I2C MO DE 400kHz
05747-094
Figure 19. ADC DNL vs. Reference Voltage
05747-079
2.0
1.0
1.5
0.5
0
–1.0
–2.0
–0.5
–1.5
INL (LSB)
CODE
256 51207681024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
AV
DD
= DV
DD
= 5V
V
DRIVE
= 5V, INT E RNAL REF,
OFFSET IN A/B/C/D = FLOATING
Figure 20. DAC INL
05747-080
0.6
0.4
0.2
0
–0.4
–0.6
–0.2
DNL ( LSB)
CODE
256 51207681024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
4096
AV
DD
= DV
DD
= 5V
V
DRIVE
= 5V, INT E RNAL REF,
OFFSET IN A/B/C/D = FLOATING
Figure 21. DAC DNL
05747-097
20
–20
–15
–10
–5
0
5
10
15
OUTPUT (µV)
TIME (s)
0 1 2 3 4 5 6 7 8 9 10
Figure 22. 0.1 Hz to 10 Hz DAC Output Noise (Code 800)
5.0
0
0.5
1.0
1.5
2.5
3.5
4.5
2.0
3.0
4.0
–5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10
DAC OUTPUT ( V )
TIME (µs)
64pF
1nF
10nF
05747-084
Figure 23. Settling Time for a ¼ to ¾ Output Voltage Step
Data Sheet AD7294
Rev. H | Page 17 of 48
0.8
–0.8
–0.6
–0.4
–0.2
0.2
0.6
0
0.4
02018161412108642
(%)
TIME (µs)
64pF
1nF
10nF
05747-085
Figure 24. Zoomed in Settling for a ¼ to ¾ Output Voltage Step
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
00403530252015105
VOUT (V)
SI NK CURRE NT (mA)
DAC A
DAC B
DAC C
DAC D
05747-090
AVDD = DVDD = 5V
OFFSET IN = FLOATING
DAC OUT V = 15V
VDRIVE = 5V, INTERNAL REF
Figure 25. DAC Sinking Current at Input Code = x000, (VOUT = 0 V)
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0 0403530252015105
VOUT – (V+)
SO URCE CURRE NT (mA)
DAC A
DAC B
DAC C
DAC D
05747-091
AVDD = DVDD = 5V
OFFSET IN = FLOATING
DAC OUT V = 15V
VDRIVE = 5V, INTERNAL REF
Figure 26. DAC Sourcing Current at Input Code = x000, (VOUT = 0 V)
100
80
60
40
20
0
–20
–40
–60
–80
–100
–50 5020 4030100–10–20–30–40
CHANGE IN OUTPUT VO LT AGE (mV )
LOAD CURRENT ( mA)
DAC A
DAC B
DAC C
DAC D
05747-092
AVDD = DVDD = 5V
OFFSET IN = FLOATING
DAC OUT V = 15V
VDRIVE = 5V, INTERNAL REF
Figure 27. DAC Output Voltage vs. Load Current, Input Code = x800
55
50
45
40
35
30
25
20–5 0 5 10 15 20
TE M P E RATURE READING ( °C)
TIME (Seconds)
05747-064
Figure 28. Response of the AD7294 to Thermal Shock Using 2N3906
(2N3906 Placed in a Stirred Oil Bath)
55
50
45
40
35
30
25–5 060555045403530252015105
TEMPERATURE (°C)
TIME (Seconds)
EXTERNAL
INTERNAL
AD7294 IN S OCKET ON
200mm × 100mm 2-L AY E R FR-4 P CB
05747-066
Figure 29. Response to Thermal Shock from Room Temperature into 50°C
Stirred Oil (Both the AD7294 and the 2N3906 are Placed in a Stirred Oil Bath)
AD7294 Data Sheet
Rev. H | Page 18 of 48
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0 00.5 1.0 1.5 2.0 2.5
ERRO R ( °C)
CAPACI TANCE F ROM D+ TO D– ( nF )
05747-065
Figure 30. Temperature Error vs. Capacitor Between D+ and D−
15
10
5
0
–5
–10
–15
–20 02000 4000 6000 8000 10000 12000
ERRO R ( °C)
SERIES RESISTANCE (Ω)
05747-062
Figure 31. Temperature Error vs. Series Resistance for 15 Typical Parts
05747-096
5
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
AMPLITUDE ( dB)
FRE QUENCY ( Hz )
1k 10k 100k 1M 10M 100M
Figure 32. Frequency Response of the High-Side Current Sensor
on the AD7294
–50
–95
–90
–85
–80
–75
–70
–65
–60
–55
1k 10k 100k 1M 10M
PSRR ( dB)
FRE QUENCY ( Hz )
05747-102
Figure 33. ISENSE Power Supply Rejection Ratio vs. Supply Ripple Frequency
Without VPP Supply Decoupling Capacitors for a 500 mV Ripple
–50
–110
–100
–90
–80
–70
–60
1100M10M1M100k10k1k10010
CMRR (dB)
RIPPLE FREQUENCY (Hz)
05747-103
Figure 34. ISENSE Common-Mode Rejection Ratio vs. Ripple Frequency for a
400 mV Peak-To-Peak Ripple
Data Sheet AD7294
Rev. H | Page 19 of 48
TERMINOLOGY
DAC TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design.
Zero Code Error
Zero code error is a measure of the output error when zero code
(0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero code error is always positive in the
AD7294 because the output of the DAC cannot go below 0 V.
Zero code error is expressed in mV.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be VDD − 1 LSB. Full-scale error is expressed in mV.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percent of the full-scale range.
Total Unadjusted Error
Total unadjusted error (TUE) is a measure of the output error,
taking all of the various errors into account.
Zero Code Error Drift
Zero code error drift is a measure of the change in zero code
error with a change in temperature. It is expressed in µV/°C.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
ADC TERMINOLOGY
Signal-to-Noise and Distortion Ratio (SINAD)
The measured ratio of signal-to-noise and distortion at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-noise and distortion ratio for
an ideal N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, the SINAD is 74 dB for an ideal 12-bit converter.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7294, it is defined as
1
2
6
2
5
2
4
2
3
2
2
log20)dB( V
VVVVV
THD ++++
=
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through
sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Typically, the value of this specification
is determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints are
zero scale, a point 1 LSB below the first code transition, and full
scale, a point 1 LSB above the last code transition.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (00…000) to
(00…001) from the ideal—that is, AGND + 1 LSB.
Offset Error Match
The difference in offset error between any two channels.
Gain Error
The deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, REFIN − 1 LSB) after the
offset error has been adjusted out.
Gain Error Match
The difference in gain error between any two channels.
AD7294 Data Sheet
Rev. H | Page 20 of 48
THEORY OF OPERATION
ADC OVERVIEW
The AD7294 provides the user with a 9-channel multiplexer, an
on-chip track-and-hold, and a successive approximation ADC
based around a capacitive DAC. The analog input range for the
part can be selected as a 0 V to VREF input or a 2 × VREF input,
configured with either single-ended or differential analog inputs.
The AD7294 has an on-chip 2.5 V reference that can be disabled
when an external reference is preferred. If the internal ADC
reference is to be used elsewhere in a system, the output must
first be buffered.
The various monitored and uncommitted input signals are multi-
plexed into the ADC. The AD7294 has four uncommitted
analog input channels, VIN0 to VIN3. These four channels allow
single-ended, differential, and pseudo differential mode
measurements of various system signals.
ADC TRANSFER FUNCTIONS
The designed code transitions occur at successive integer LSB
values (1 LSB, 2 LSB, and so on). In single-ended mode, the
LSB size is VREF/4096 when the 0 V to VREF range is used and
2 × VREF/4096 when the 0 V to 2 × VREF range is used. The ideal
transfer characteristic for the ADC when outputting straight
binary coding is shown in Figure 35.
000...000
111...111
1LS B = V
REF
/4096
1LSB V
REF
– 1LS B
ANALOG INPUT
ADC CODE
0V
000...001
000...010
111...110
111...000
011...111
NOTE
1. V
REF
IS EIT HER V
REF
OR 2 × V
REF
.
05747-016
Figure 35. Single-Ended Transfer Characteristic
In differential mode, the LSB size is 2 × VREF/4096 when the 0 V
to VREF range is used, and 4 × VREF/4096 when the 0 V to 2 × VREF
range is used. The ideal transfer characteristic for the ADC when
outputting twos complement coding is shown in Figure 36 (with
the 2 × VREF range).
100...000
011...111
1LS B = 2 × VREF/4096
+VREF – 1LS B–VREF + 1LSB VREF – 1LS B
ANALOG INPUT
ADC CODE
100...001
100...010
011...110
000...001
000...000
111...111
05747-017
Figure 36. Differential Transfer Characteristic with VREF ± VREF Input Range
For VIN0 to VIN3 in single-ended mode, the output code is
straight binary, where
VIN = 0 V, DOUT = x000, VIN = VREF − 1 LSB, and DOUT = xFFF
In differential mode, the code is twos complement, where
VIN+ − VIN− = 0 V, and DOUT = x00
VIN+ − VIN− = VREF − 1 LSB, and DOUT = x7FF
VIN+ − VIN− = −VREF, and DOUT = x800
Channel 5 and Channel 6 (current sensor inputs) are twos
complement, where
VIN+ − VIN− = 0 m V, and DOUT = x000
VIN+ − VIN− = VREF/12.5 − 1 LSB, DOUT = x7FF
VIN+ − VIN− = −VREF/12.5, DOUT = x800
Channel 7 to Channel 9 (temperature sensor inputs) are twos
complement with the LSB equal to 0.25°C, where
TIN = 0°C, and DOUT = x000
TIN = +255.75°C, and DOUT = x7FF
TIN = −256°C, and DOUT = x800
ANALOG INPUTS
The AD7294 has a total of four analog inputs. Depending on
the configuration register setup, they can be configured as two
single-ended inputs, two pseudo differential channels, or two
fully differential channels. See the Register Setting section for
further details.
Single-Ended Mode
The AD7294 can have four single-ended analog input channels.
In applications where the signal source has high impedance, it is
recommended to buffer the analog input before applying it to the
ADC. The analog input range can be programmed to be either
0 V to VREF or 0 V to 2 × VREF. In 2 × VREF mode, the input is
effectively divided by 2 before the conversion takes place. Note
that the voltage with respect to GND on the ADC analog input
pins cannot exceed AVDD.
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
Data Sheet AD7294
Rev. H | Page 21 of 48
signal so that it is correctly formatted for the ADC. Figure 37
shows a typical connection diagram when operating the ADC
in single-ended mode.
V
IN
0V
+1.25V
–1.25V
REF
OUT
ADC
V
IN
0
AD7294
1
V
IN
3
R
R
3R
R
0V
+2.5V
0.47µF
1
ADDITIONAL PINS OMITTED FOR CLARITY.
05747-018
Figure 37. Single-Ended Mode Connection Diagram
Differential Mode
The AD7294 can have two differential analog input pairs.
Differential signals have some benefits over single-ended
signals, including noise immunity based on the common-
mode rejection of the device and improvements in distortion
performance. Figure 38 defines the fully differential analog
input of the AD7294.
VIN+
AD7294
1
VIN–
VREF p-p
VREF p-p
COMMON-MODE
VOLTAGE
1ADDITIONAL PINS OMITTED FOR CLARITY.
05747-019
Figure 38. Differential Input Definition
The amplitude of the differential signal is the difference
between the signals applied to VIN+ and VIN− in each differential
pair (VIN+ − VIN−). The resulting converted data is stored in twos
complement format in the result register. Simultaneously drive
VIN0 and VIN1 by two signals, each of amplitude VREF (or 2 ×
VREF, depending on the range chosen), that are 180° out of
phase. Assuming the 0 V to VREF range is selected, the amplitude
of the differential signal is, therefore, −VREF to +VREF peak-to-
peak (2 × VREF), regardless of the common mode (VCM).
The common mode is the average of the two signals
(VIN+ + VIN−)/2
The common mode is, therefore, the voltage on which the two
inputs are centered.
This results in the span of each input being VCM ± VREF/2. This
voltage has to be set up externally, and its range varies with the
reference value, VREF. As the value of VREF increases, the common-
mode range decreases. When driving the inputs with an amplifier,
the actual common-mode range is determined by the output
voltage swing of the amplifier.
The common mode must be in this range to guarantee the
functionality of the AD7294.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude −VREF to
+VREF, corresponding to the digital output codes of −2048 to
+2047 in twos complement format.
If the 2 × VREF range is used, the input signal amplitude extends
from −2 ×VREF (VIN+ = 0 V, V IN− = VREF) to +2 × VREF (VIN− = 0 V,
VIN+ = VREF).
Driving Differential Inputs
The differential modes available on VIN0 to VIN3 in Table 13
require that VIN+ and VIN− be driven simultaneously with two
equal signals that are 180° out of phase. The common mode on
which the analog input is centered must be set up externally. The
common-mode range is determined by VREF, the power supply,
and the particular amplifier used to drive the analog inputs.
Differential modes of operation with either an ac or dc input
provide the best THD performance over a wide frequency
range. Because not all applications have a signal preconditioned
for differential operation, there is often a need to perform a single-
ended-to-differential conversion.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential signal
to one of the analog input pairs of the AD7294. The circuit con-
figurations illustrated in Figure 39 show how a dual op amp can
be used to convert a single-ended bipolar signal into a differential
unipolar input signal.
The voltage applied to Point A sets up the common-mode voltage.
As shown in Figure 39, Point A connects to the reference, but any
value in the common-mode range can be the input at Point A to
set up the common mode. The AD8022 is a suitable dual op amp
that can be used in this configuration to provide differential
drive to the AD7294.
Care is required when choosing the op amp because the selection
depends on the required power supply and system performance
objectives. The driver circuits in Figure 39 are optimized for dc
coupling applications requiring best distortion performance.
The differential op amp driver circuit shown in Figure 39 is
configured to convert and level shift a single-ended, ground
referenced (bipolar) signal to a differential signal centered at
the VREF level of the ADC.
AD7294 Data Sheet
Rev. H | Page 22 of 48
20kΩ
220kΩ
2 × VREF p-p
27Ω
27Ω
V+
V–
V+
V–
GND
2.5V
3.75V
1.25V
2.5V
3.75V
1.25V REFOUT ADC
VIN+
AD7294
1
VIN–
440Ω
220Ω
0.47µF
1ADDITIONAL PINS OMITTED FOR CLARITY.
220Ω
220Ω
10kΩ
A
05747-023
Figure 39. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
into a Differential Unipolar Signal
Pseudo Differential Mode
The four uncommitted analog input channels can be configured
as two pseudo differential pairs. Uncommitted input, VIN0 and
VIN1, are a pseudo differential pair, as are VIN2 and VIN3. In this
mode, VIN+ is connected to the signal source, which can have a
maximum amplitude of VREF (or 2 × VREF, depending on the
range chosen) to make use of the full dynamic range of the part.
A dc input is applied to VIN−. The voltage applied to this input
provides an offset from ground or a pseudo ground for the VIN+
input. Which channel is VIN+ is determined by the ADC channel
allocation. The differential mode must be selected to operate in the
pseudo differential mode. The resulting converted pseudo differen-
tial data is stored in twos complement format in the result register.
The governing equation for the pseudo differential mode, for
VIN0 is
VOUT = 2(VIN+ − VIN−) − VREF_ADC
where VIN+ is the single-ended signal and VIN− is a dc voltage.
The benefit of pseudo differential inputs is that they separate
the analog input signal ground from the ADC ground, allowing
dc common-mode voltages to be cancelled. The typical voltage
range for VIN− while in pseudo differential mode is shown in
Figure 40; Figure 41 shows a connection diagram for pseudo
differential mode.
2.0
1.5
1.0
0.5
–0.5
0
0 654321
V
IN–
(V)
V
REF
(V)
05747-095
AV
DD
= DV
DD
= 5V
V
DRIVE
= 5V
Figure 40. VIN− Input Range vs. VREF in Pseudo Differential Mode
DC INP UT
VOLTAGE
V
REF
p-p
REF
OUT
/REF
IN
ADC
V
IN+
AD7294
1
V
IN–
0.47µF
1
ADDITIONAL PINS OMITTED FOR CLARITY.
05747-026
Figure 41. Pseudo Differential Mode Connection Diagram
CURRENT SENSOR
Two bidirectional high-side current sense amplifiers are
provided that can accurately amplify differential current shunt
voltages in the presence of high common-mode voltages from
AVDD up to 59.4 V. Each amplifier can accept a ±200 mV
differential input. Both current sense amplifiers have a fixed
gain of 12.5 and utilize an internal 2.5 V reference.
An analog comparator is also provided with each amplifier for
fault detection. The threshold is defined as
1.2 × Full-Scale Voltage Range
When this limit is reached, the output is latched onto a
dedicated pin. This output remains high until the latch is
cleared by writing to the appropriate register.
AD7294
AV
DD
TO 54.5V
RS(+)
R
SENSE
I
LOAD
RS(–)
R1
40kΩ R2
40kΩ
R3
100kΩ R4
100kΩ
Q1 Q2
V
OUT
TO MUX
A1
A1
A2
V
PP
05747-029
Figure 42. High-Side Current Sense
The AD7294 current sense comprises two main blocks: a
differential and an instrumentation amplifier. A load current
flowing through the external shunt resistor produces a voltage
at the input terminals of the AD7294. Resistors R1 and R2
connect the input terminals to the differential amplifier (A1).
A1 nulls the voltage appearing across its own input terminals
by adjusting the current through R1 and R2 with Transistor Q1
and Transistor Q2. Common-mode feedback maintains the sum
of these currents at approximately 50 μA. When the input signal
to the AD7294 is zero, the currents in R1 and R2 are equal. When
the differential signal is nonzero, the current increases through
one of the resistors and decreases in the other. The current differ-
ence is proportional to the size and polarity of the input signal.
The differential currents through Q1 and Q2 are converted into
a differential voltage by R3 and R4. A2 is configured as an instru-
mentation amplifier, buffering this voltage and providing additional
Data Sheet AD7294
Rev. H | Page 23 of 48
gain. Therefore, for an input voltage of ±200 mV at the pins, an
output span of ±2.5 V is generated.
The current sensors on the AD7294 are designed to remove
any flicker noise and offset present in the sensed signal. This is
achieved by implementing a chopping technique that is transpa-
rent to the user. The VSENSE signal is first converted by the AD7294,
the analog inputs to the amplifiers are then swapped, and the
differential voltage is once again converted by the AD7294. The
two conversion results enable the digital removal of any offset
or noise. Switches on the amplifier inputs enable this chopping
technique to be implemented. This process requires 6 μs in total
to return a final result.
Choosing RSENSE
The resistor values used in conjunction with the current sense
amplifiers on the AD7294 are determined by the specific appli-
cation requirements in terms of voltage, current, and power.
Small resistors minimize power dissipation, have low inductance
to prevent any induced voltage spikes, and have good tolerance,
which reduce current variations. The final values chosen are a
compromise between low power dissipation and good accuracy.
Low value resistors have less power dissipated in them, but higher
value resistors may be required to utilize the full input range of
the ADC, thus achieving maximum SNR performance.
When the sense current is known, the voltage range of the
AD7294 current sensor (200 mV) is divided by the maximum
sense current to yield a suitable shunt value. If the power dissi-
pation in the shunt resistor is too large, the shunt resistor can
be reduced, in which case, less of the ADC input range is used.
Using less of the ADC input range results in conversion results,
which are more susceptible to noise and offset errors because
offset errors are fixed and are thus more significant when
smaller input ranges are used.
RSENSE must be able to dissipate the I2R losses. If the power dissi-
pation rating of the resistor is exceeded, its value may drift or
the resistor may be damaged resulting in an open circuit. This
can result in a differential voltage across the terminals of the
AD7294 in excess of the absolute maximum ratings. Additional
protection is afforded to the current sensors on the AD7294 by
the recommended current limiting resistors, RF1 and RF2, as
illustrated in Figure 43. The AD7294 can handle a maximum
continuous current of 30 mA; thus, an RF2 of 1 kΩ provides
adequate protection for the AD7294.
If ISENSE has a large high frequency component, take care to
choose a resistor with low inductance. Low inductance metal
film resistors are best suited for these applications.
Current Sense Filtering
In some applications, it may be desirable to use external
filtering to reduce the input bandwidth of the amplifier (see
Figure 43). The −3 dB differential bandwidth of this filter is
equal to
BWDM = 1/(4πRC)
Note that the maximum series resistance on the RS(+) and
RS(−) inputs (as shown in Figure 42) is limited to a maximum
of 1 kΩ due to back-to-back ESD protection diodes from RS(+)
and RS(−) to VPP. Also, note that if RF1 and RF2 are in series
with R1 and R2 (shown in Figure 42), it affects the gain of the
amplifier. Any mismatch between RF1 and RF2 can introduce
offset error.
05747-098
RF1 RF2
CF
AD7294
VPP RSENSE ILOAD
RSx(–)RSx(+)
10nF
VPP
Figure 43. Current Sense Filtering (RSX Can Be Either RS1 or RS2)
For certain RF applications, the optimum value for RF1 and
RF2 is 1 kΩ whereas CF1 can range from 1 μF to 10 μF. CF2 is a
decoupling capacitor for the VPP supply. Its value is application
dependant, but for initial evaluation, values in the range of 1 nF
to 100 nF are recommended.
Kelvin Sense Resistor Connection
When using a low value sense resistor for high current
measurement, the problem of parasitic series resistance can
arise. The lead resistance can be a substantial fraction of the
rated resistance, making the total resistance a function of lead
length. Avoid this problem by using a Kelvin sense connection.
This type of connection separates the current path through the
resistor and the voltage drop across the resistor. Figure 44 shows
the correct way to connect the sense resistor between the RS(+)
and RS(−) pins of the AD7294.
SENSE RESISTOR
CURRENT
FLOW FROM
SUPPLY
CURRENT
FLOW TO
LOAD
KELVIN
SENSE
TRACES
AD7294
RSX(+) RSX(–)
05747-031
Figure 44. Kelvin Sense Connections (RSX Can Be Either RS1 or RS2)
ANALOG COMPARATOR LOOP
The AD7294 contains two setpoint comparators that are used
for independent analog control. This circuitry enables users
to quickly detect if the sensed voltage across the shunt has
AD7294 Data Sheet
Rev. H | Page 24 of 48
increased about the preset (VREF × 1.2)/12.5. If this occurs, the
ISENSE OVERRANGE pin is set to a high logic level enabling
appropriate action to be taken to prevent any damage to the
external circuitry.
The setpoint threshold level is fixed internally in the AD7294,
and the current sense amplifier saturates above this level. The
comparator also triggers if a voltage of less than AVDD is applied
to the RSENSE or VPP pin.
TEMPERATURE SENSOR
The AD7294 contains one local and two remote temperature
sensors. The temperature sensors continuously monitor the
three temperature inputs and new readings are automatically
available every 5 ms.
The on-chip, band gap temperature sensor measures the temper-
ature of the system. Diodes are used in conjunction with the two
remote temperature sensors to monitor the temperature of other
critical board components.
LIMIT
REGISTERS
TEMP
SENSOR
T1 T2
ALERT
D2+
D2–
D1+
D1–
AD7294
CAP
REMOTE
SENSING
TRANSISTORS
16 × I II-BIAS
MUX
MUX
V
DD
BIAS DIO DE
TO ADC
4 × I
f
C
= 65kHz
LPF
05747-032
Figure 45. Internal and Remote Temperature Sensors
The temperature sensor module on the AD7294 is based on the
three current principle (see Figure 45), where three currents are
passed through a diode and the forward voltage drop is measured
at each diode, allowing the temperature to be calculated free of
errors caused by series resistance.
Each input integrates, in turn, over a period of several hundred
microseconds. This takes place continuously in the background,
leaving the user free to perform conversions on the other channels.
When integration is complete, a signal passes to the control logic
to initiate a conversion automatically. If the ADC is in command
mode, the temperature conversion is performed as soon as the
next conversion is completed. In autocycle mode, the conversion
is inserted into an appropriate place in the current sequence; see
the Register Setting section for further details. If the ADC is
idle, the conversion takes place immediately.
Three registers store the result of the last conversion on each
temperature channel; these can be read at any time. In addition,
in command mode, one or both of the two external channel
registers can be read out as part of the output sequence.
Remote Sensing Diode
The AD7294 is designed to work with discrete transistors,
2N3904 and 2N3906. If an alternative transistor is used, the
AD7294 operates as specified provided the following conditions
are adhered to.
Ideality Factor
The ideality factor, nf, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
AD7294 is trimmed for an nf value of 1.008. Use the following
equation to calculate the error introduced at a Temperature T
(°C) when using a transistor whose nf does not equal 1.008:
ΔT = (nf − 1.008) × (273.15 K + T)
To factor this in, the user can write the ∆T value to the offset
register. The AD7294 automatically adds it to, or subtracts it
from, the temperature measurement.
Base Emitter Voltage
The AD7294 operates as specified provided that the base-
emitter voltage is greater than 0.25 V at 8 µA at the highest
operating temperature, and less than 0.95 V at 128 µA for the
lowest operating temperature.
Base Resistance
The base resistance should be less than 100 Ω.
hFE Variation
A transistor with small variation in hFE (approximately 50 to
150) should be used. Small variation in hFE indicates tight
control of the VBE characteristics.
For RF applications, the use of high Q capacitors functioning as a
filter protects the integrity of the measurement. These capacitors,
such as Johanson Technology 10 pF high Q capacitors: Reference
Code 500R07S100JV4T, should be connected between the base and
the emitter, as close to the external device as possible. However,
large capacitances affect the accuracy of the temperature measure-
ment; thus, the recommended maximum capacitor value is 100 pF.
In most cases, a capacitor is not required; the selection of any
capacitor is dependent on the noise frequency level.
05747-099
2N3904
NPN
AD7294
D+
D–
10pF
Figure 46. Measuring Temperature Using an NPN Transistor
05747-100
10pF
2N3906
PNP
AD7294
D+
D–
Figure 47. Measuring Temperature Using a PNP Transistor
Data Sheet AD7294
Rev. H | Page 25 of 48
Series Resistance Cancellation
The AD7294 has been designed to automatically cancel out the
effect of parasitic, base, and collector resistance on the tempera-
ture reading. This gives a more accurate result, without the need
for any user characterization of the parasitic resistance. The
AD7294 can compensate for up to 100 Ω in a process that is
transparent to the user.
DAC OPERATION
The AD7294 contains four 12-bit DACs that provide digital
control with 12 bits of resolution with a 2.5 V internal reference.
The DAC core is a thin film 12-bit string DAC with a 5 V output
span and an output buffer that can drive the high voltage output
stage. The DAC has a span of 0 V to 5 V with a 2.5 V reference
input. The output range of the DAC, which is controlled by the
offset input, can be positioned from 0 V to 15 V.
Resistor String
The resistor string structure is shown in Figure 48. It consists of
a string of 2n resistors, each of Value R. The code loaded to the
DAC register determines at which node on the string the voltage
is tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. This architecture is inherently monotonic,
voltage out, and low glitch. It is also linear because all of the
resistors are of equal value.
R
R
R
R
RTO OUTPUT
AMPLIFIER
05747-028
Figure 48. Resistor String Structure
Output Amplifier
Referring to Figure 48, the purpose of A1 is to buffer the DAC
output range from 0 V to VREF. The second amplifier, A2, is
configured such that when an offset is applied to OFFSET IN x,
its output voltage is three times the offset voltage minus twice
the DAC voltage.
VOUT = 3VOFFSET − 2VDAC
The DAC word is digitally inverted on-chip such that
VOUT = 3VOFFSET + 2(VDAC − VREF)
and VDAC =
×n
REF D
V2
where:
VDAC is the output of the DAC before digital inversion.
D is the decimal equivalent of the binary code that is loaded to the
DAC register.
n is the bit resolution of the DAC.
An example of the offset function is given in Table 8.
Table 8. Offset Voltage Function Example
Offset
Voltage VOUT with 0x000 VOUT with 0xFFF
1.67 V 0 V 5 V − 1 LSB
3.33 V 5 V 10 V − 1 LSB
5.00 V 10 V 15 V − 1 LSB
The user has the option of leaving the offset pin open, in which
case the voltage on the noninverting input of Op Amp A2 is set
by the resistor divider, giving
VOUT = 2VDAC
This generates the 5 V output span from a 2.5 V reference.
Digitally inverting the DAC allows the circuit to operate as a
generic DAC when no offset is applied. If the offset pin is not
being driven, it is best practice to place a 100 nF capacitor
between the pin and ground to improve both the settling time
and the noise performance of the DAC.
Note that a significant amount of power can be dissipated in the
DAC outputs. A thermal shutdown circuit sets the DAC outputs
to high impedance if a die temperature of >150°C is measured
by the internal temperature sensor. This also sets the overtem-
perature alert bit in Alert Register C, see the Alerts and Limits
Theory section. Note that this feature is disabled when the
temperature sensor powers down.
ADC AND DAC REFERENCE
The AD7294 has two independent internal high performance
2.5 V references, one for the ADCs and the other for the four
on-chip DACs. If the application requires an external reference,
it can be applied to the REFOUT/REFIN DAC pin and/or to the
REFOUT/REFIN ADC pin. The internal reference should be buffered
before being used by external circuitry. Decouple both the REFOUT/
REFIN DAC pin and the REFOUT/REFIN ADC pin to AGND using a
220 nF capacitor. On power-up, the AD7294 is configured for
use with an external reference. To enable the internal references,
write a zero to both the D4 and D5 bits in the power-down
register (see the Register Setting section for more details). Both
the ADC and DAC references require a minimum of 60 μs to
power up and settle to a 12-bit performance when a 220 nF
decoupling capacitor is used.
AD7294 Data Sheet
Rev. H | Page 26 of 48
The AD7294 can also operate with an external reference.
Suitable reference sources for the AD7294 include AD780,
AD1582, ADR431, REF193, and ADR391. In addition, choosing
a reference with an output trim adjustment, such as the ADR441,
allows a system designer to trim system errors by setting a
reference voltage to a voltage other than the nominal.
Long-term drift is a measure of how much the reference drifts
over time. A reference with a low long-term drift specification
ensures that the overall solution remains stable during its entire
lifetime. If an external reference is used, select a low temperature
coefficient specification to reduce the temperature dependence
of the system output voltage on ambient conditions.
VDRIVE FEATURE
The AD7294 also has a VDRIVE feature to control the voltage at
which the I2C interface operates. The VDRIVE pin is connected to
the supply to which the I2C bus is pulled. This pin sets the input
and output threshold levels for the digital logic pins and the
ISENSE OVERRANGE pins. The VDRIVE feature allows the AD7294
to easily interface to both 3 V and 5 V processors. For example,
if the AD7294 is operated with a VDD of 5 V, t h e VDRIVE pin can
be powered from a 3 V supply, allowing a large dynamic range
with low voltage digital processors. Thus, the AD7294 can be
used with the 2 × VREF input range with a VDD of 5 V, yet remains
capable of interfacing to 3 V digital parts. Decouple this pin to
DGND with a 100 nF and a 1 μF capacitor.
Data Sheet AD7294
Rev. H | Page 27 of 48
REGISTER SETTING
The AD7294 contains internal registers (see Figure 49) that
store conversion results, high and low conversion limits, and
information to configure and control the device.
ADDRESS
POINTER
REGISTER
SERIAL BUS INT E RFACE SDA
SCL
DATA
COMMAND
REGISTER
RESULT
REGISTER
DAC
REGISTERS
T
SENSE
RESULT
REGISTERS × 3
T
SENSE
OFFSET
REGISTERS × 2
ALERT
REGISTERS × 3
CONFIGURATION
REGISTER
POWER-DOWN
REGISTER
HYSTERESIS
REGISTER
DATAHIGH/
DATALOW
REGISTERS × 1 8
CHANNEL
SEQUENCE
REGISTER
05747-039
Figure 49. AD7294 Register Structure
Each data register has an address to which the address pointer
register points when communicating with it. The command
register is the only register that is a write-only register; the rest
are read/write registers.
ADDRESS POINTER REGISTER
The address pointer register is an 8-bit register, in which the
6 LSBs are used as pointer bits to store an address that points
to one of the AD7294 data registers, see Table 9.
Table 9. AD7294 Register Address
Address in Hex Registers (R is Read/W is Write)
00 Command Register (W)
01 Result Register (R)/DACA Value (W)
02 TSENSE1 Result (R)/DACB Value (W)
03 TSENSE2 Result (R)/DACC Value (W)
04 TSENSEINT Result (R)/DACD Value (W)
05 Alert Register A (R/W)
06 Alert Register B (R/W)
07 Alert Register C (R/W)
08 Channel Sequence Register (R/W)
09 Configuration Register (R/W)
0A Power-Down Register (R/W)
0B DATA
LOW
Register V
IN
0 (R/W)
0C DATAHIGH Register VIN0 (R/W)
0D Hysteresis Register VIN0 (R/W)
0E DATALOW Register VIN1 (R/W)
0F DATAHIGH Register VIN1 (R/W)
10 Hysteresis Register VIN1 (R/W)
11 DATALOW Register, VIN2 (R/W)
12 DATAHIGH Register VIN2 (R/W)
13 Hysteresis Register VIN2 (R/W)
14 DATALOW Register VIN3 (R/W)
15 DATAHIGH Register VIN3 (R/W)
16 Hysteresis Register V
IN
3 (R/W)
17 DATALOW Register ISENSE1 (R/W)
18 DATAHIGH Register ISENSE1 (R/W)
19 Hysteresis Register ISENSE1 (R/W)
1A DATALOW Register ISENSE2 (R/W)
1B DATAHIGH Register ISENSE2 (R/W)
1C Hysteresis Register ISENSE2 (R/W)
1D DATALOW Register TSENSE1 (R/W)
1E DATAHIGH Register TSENSE1 (R/W)
1F Hysteresis Register TSENSE1 (R/W)
20 DATALOW Register TSENSE2 (R/W)
21 DATA
HIGH
Register T
SENSE
2 (R/W)
22 Hysteresis Register TSENSE2 (R/W)
23 DATALOW Register TSENSEINT (R/W)
24 DATAHIGH Register TSENSEINT (R/W)
25 Hysteresis Register TSENSEINT (R/W)
26 TSENSE1 Offset Register (R/W)
27 T
SENSE
2 Offset Register (R/W)
40 Factory Test Mode
41 Factory Test Mode
AD7294 Data Sheet
Rev. H | Page 28 of 48
COMMAND REGISTER (0x00)
Writing in the command register puts the part into command
mode. When in command mode, the part cycles through the
selected channels from LSB (D0) to MSB (D7) on each subse-
quent read (see Table 10). A channel is selected for conversion
if a one is written to the desired bit in the command register. On
power-up, all bits in the command register are set to zero. If the
external TSENSE channels are selected in the command register
byte, it is not actually requesting a conversion. The result of the
last automatic conversion is output as part of the sequence (see
the Modes of Operation section).
If a command mode conversion is required while the autocycle
mode is active, it is necessary to disable the autocycle mode
before proceeding to the command mode (see the Autocycle
Mode section for more details).
RESULT REGISTER (0x01)
The result register is a 16-bit read-only register. The conversion
results for the four uncommitted ADC inputs and the two ISENSE
channels are stored in the result register for reading.
Bit D14 to Bit D12 are the channel allocation bits, each of which
identifies the ADC channel that corresponds to the subsequent
result (see the ADC Channel Allocation section for more
details). Bit D11 to Bit D0 contain the most recent ADC result.
D15 is reserved as an alert_flag bit. Table 11 lists the contents of
the first byte that is read from the AD7294 results register; Table 12
lists the contents of the second byte read.
Table 10. Command Register1
MSB LSB
Bits D7 D6 D5 D4 D3 D2 D1 D0
Channel Read out last
result from
TSENSE2
Read out last
result from
TSENSE1
ISENSE2 ISENSE1 VIN3 (S.E.)
or
VIN3 − VIN2
(DIFF)
VIN2 (S.E.)
or
VIN2 − VIN3
(DIFF)
VIN1 (S.E.)
or
VIN1 − VIN0
(DIFF)
VIN0 (S.E.)
or
VIN0 − VIN1
(DIFF)
1 S.E. indicates single-ended and DIFF indicates differential.
Table 11. Result Register (First Read)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8
Alert_Flag CH
ID2
CH
ID1
CH
ID0
B11 B10 B9 B8
Table 12. Result Register (Second Read)
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1 B0
Data Sheet AD7294
Rev. H | Page 29 of 48
ADC Channel Allocation
The three channel address bits indicate which channel the result
in the result register represents. Table 13 details the channel ID bits
(S.E. indicates single-ended and DIFF indicates differential).
Table 13. ADC Channel Allocation
Function
Channel ID
CHID2 CHID1 CHID0
VIN0 (S.E.) or
VIN0 − VIN1 (DIFF)
0 0 0
VIN1 (S.E.) or
VIN1 − VIN0 (DIFF)
0 0 1
VIN2 (S.E.) or
VIN2 − VIN3 (DIFF)
0 1 0
VIN3 (S.E.) or
VIN3 − VIN2 (DIFF)
0 1 1
ISENSE1 1 0 0
ISENSE2 1 0 1
T
SENSE
1 1 1 0
TSENSE2 1 1 1
TSENSE1, TSENSE2 RESULT REGISTERS (0x02 AND 0x03)
Register TSENSE1 and Register TSENSE2 are 16-bit read only registers.
The MSB, D15 is the alert_flag bit whereas Bit D14 to Bit D12
contain the three ADC channel allocation bits. D11 is reserved
for flagging diode open circuits. The temperature reading from
the ADC is stored in an 11-bit twos complement format, D10 to
D0 (see Table 14 and Table 15). Conversions take place approx-
imately every 5 ms.
Table 14. TSENSE Register (First Read)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8
Alert_Flag CH
ID2
CH
ID1
CH
ID0
B11 B10 B9 B8
Table 15. Register (Second Read)
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1 B0
TSENSEINT RESULT REGISTER (0x04)
The TSENSEINT register is a 16-bit read-only register used to
store the ADC data generated from the internal temperature
sensor. Similar to the TSENSE1 and TSENSE2 result registers, this
register stores the temperature readings from the ADC in an 11-
bit twos complement format, D10 to D0, and uses the MSB as a
general alert flag. Bits[ D14:D11] are not used and are set to
zero. Conversions take place approximately every 5 ms. The
temperature data format in Table 16 also applies to the internal
temperature sensor data.
Temperature Value Format
The temperature reading from the ADC is stored in an 11-bit
twos complement format, D10 to D0, to accommodate both
positive and negative temperature measurements. The temper-
ature data format is provided in Table 16.
Table 16. TSENSE Data Format
Input D10 (MSB) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB)
Value (°C) −256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25
AD7294 Data Sheet
Rev. H | Page 30 of 48
DACA, DACB, DACC, DACD, REGISTERS (0x01 TO 0x04)
Writing to these register addresses sets the DACA, DACB, DACC,
and DACD output voltage codes, respectively. Bits[D11:D0] in
the write result register are the data bits sent to DACA. Bit D15
to Bit D12 are ignored.
Table 17. DAC Register (First Write)1
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8
X X X X B11 B10 B9 B8
1 X is don’t care.
Table 18. DAC Register (Second Write)
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1 B0
ALERT STATUS REGISTER A (0x05), REGISTER B
(0x06), AND REGISTER C (0x07)
The alert status registers (A, B, and C) are 8-bit read/write
registers that provide information on an alert event. If a
conversion results in activating the ALERT/BUSY pin or the
alert_flag bit in the result register or TSENSE registers, the alert
status register can be read to gain further information. To clear
the full content of any one of the alert registers, write a code of
FF (all ones) to the relevant registers. Alternatively, the user can
write to the respective alert bit in the selected alert register to
clear the alert associated with that bit. The entire contents of all
the alert status registers can be cleared by writing a 1 to Bit D1
and Bit D2 in the configuration register, as shown in Table 24.
However, this operation then enables the ALERT/BUSY pin for
subsequent conversions. See the Alerts and Limits Theory
section for more details.
CHANNEL SEQUENCE REGISTER (0x08)
The channel sequence register is an 8-bit read/write register that
allows the user to sequence the ADC conversions to be per-
formed in autocycle mode. Table 22 shows the content of the
channel sequence register. See the Modes of Operation section
for more information.
Table 19. Alert Status Register A
Alert Bit D7 D6 D5 D4 D3 D2 D1 D0
Function VIN3
high alert
VIN3
low alert
VIN2
high alert
VIN2
low alert
VIN1
high alert
VIN1
low alert
VIN0
high alert
VIN0
low alert
Table 20. Alert Status Register B
Alert Bit D7 D6 D5 D4 D3 D2 D1 D0
Function Reserved Reserved ISENSE2
overrange
ISENSE1
overrange
ISENSE2
high alert
ISENSE2
low alert
ISENSE1
high alert
ISENSE1
low alert
Table 21. Alert Status Register C
Alert Bit D7 D6 D5 D4 D3 D2 D1 D0
Function Open-diode
flag
Overtemp
alert
TSENSEINT
high alert
TSENSEINT
low alert
TSENSE2
high alert
TSENSE2
low alert
TSENSE1
high alert
TSENSE1
low alert
Table 22. Channel Sequence Register
Channel Bit D7 D6 D5 D4 D3 D2 D1 D0
Function Reserved Reserved I
SENSE
2 I
SENSE
1 V
IN
3 V
IN
2 V
IN
1 V
IN
0
Data Sheet AD7294
Rev. H | Page 31 of 48
CONFIGURATION REGISTER (0x09)
The configuration register is a 16-bit read/write register that
sets the operating modes of the AD7294. The bit functions of
the configuration register are outlined in Table 23 and Table 24.
On power-up, the configuration register is reset to 0x0000.
Sample Delay and Bit Trial Delay
It is recommended that no I2C bus activity occur when a con-
version is taking place; however, this may not be possible, for
example, when operating in autocycle mode. Bit D14 and Bit D13
in the configuration register are used to delay critical sample
intervals and bit trials from occurring while there is activity
on the I2C bus. On power-up, Bit D14 (noise-delayed sampling),
Bit D13 (noise-delayed bit trials), and Bit D3 (I2C filters) are
enabled (set to 0). This configuration is appropriate for low
frequency applications because the bit trials are prevented from
occurring when there is activity on the I2C bus, thus ensuring
good dc linearity perfor-mance. For high frequency input
signals, it may be desirable to have a known sampling point, thus
the noise-delayed sampling can be disabled by writing a 1 to Bit
D14 in the configuration register. This ensures that the
sampling instance is fixed relative to SDA, resulting in improved
SNR performance. If noise-delay samplings extend longer than 1
µs, the current conversion terminates. This termination can occur
if there are edges on SDA that are outside the I2C specification.
When noise-delayed sampling is enabled, the rise and fall times
must meet the I2C-specified standard. When D13 is enabled, the
conversion time may vary.
The default configuration for Bit D3 (enabled) is recommended
for normal operation because it ensures that the I2C requirements
for tOf (minimum)and tSP are met. The I2C filters reject glitches
shorter than 50 ns. If this function is disabled, the conversion
results are more susceptible to noise from the I2C bus.
Table 23. Configuration Register Bit Function Description D15 to D8
Channel
Bit D15 D14 D13 D12 D11 D10 D9 D8
Function Reserved Noise-delayed
sampling. Use to
delay critical
sample intervals
from occurring
when there is
activity on the
I2C bus.
Noise-delayed
bit trials. Use to
delay critical bit
trials from
occurring when
there is activity
on the I2C bus.
Autocycle
mode
Pseudo
differential
mode for
VIN3/VIN4
Pseudo
differential
mode for
VIN1/VIN2
Differential
mode for
VIN3/VIN4
Differential
mode for
VIN1/VIN2
Setting Enabled = 0 Enabled = 0 Enabled = 1 Enabled = 1 Enabled = 1 Enabled = 1 Enabled = 1
Disabled = 1 Disabled = 1 Disabled = 0 Disabled = 0 Disabled = 0 Disabled = 0 Disabled = 0
Table 24. Configuration Register Bit Function Description D7 to D0
Channel
Bit D7 D6 D5 D4 D3 D2 D1 D0
Function 2VREF range
for VIN4
2VREF range
for VIN3
2VREF range
for VIN2
2VREF range
for VIN1
I2C filters ALERT pin BUSY pin (D2 = 0),
clear alerts (D2 = 1)
Select ALERT
pin polarity
(active high/
active low)
Setting Enabled = 1
Disabled = 0
Enabled = 1
Disabled = 0
Enabled = 1
Disabled = 0
Enabled = 1
Disabled = 0
Enabled = 0
Disabled = 1
Enabled
D2 = 1
D1 = 0
Disabled
D2 = 0
Enabled
D1 = 1 + D0 = 0
Disabled D1 = 0
Active high = 1
Active low = 0
Table 25. Alert/Busy Function Description
D2 D1 ALERT/BUSY Pin Functions
0 0 Pin does not provide any interrupt signal.
0 1 Configures pin as a busy output.
1 0 Configures pin as an alert output.
1 1 Resets the ALERT/BUSY output pin, the alert_flag bit in the conversion result register, and the entire alert status register (if any is
active). 1,1 is written to Bits[D2:D1] in the configuration register to reset the ALERT/BUSY pin, the alert_flag bit, and the alert status
register. Following this write, the contents of the configuration register read 1, 0 for Bit D2 and Bit D1, respectively, if read back.
Table 26. ADC Input Mode Example
D11 D10 D9 D8 Description
0 0 0 0 All channels single-ended
0 0 0 1 Differential mode on VIN1/VIN2
0 1 0 1 Pseudo differential mode on VIN1/VIN2
AD7294 Data Sheet
Rev. H | Page 32 of 48
POWER-DOWN REGISTER (0x0A)
The power-down register is an 8-bit read/write register that
powers down various sections on the AD7294 device. On
power-up, the default value for the power-down register is 0x30.
The content of the power-down register is provided in Table 27.
Table 27. Power-Down Register Description
Bit Function
D7 Power down the full chip
D6 Reserved
D5 Power down the ADC reference buffer (to allow
external reference, 1 at power-up)
D4 Power down the DAC reference buffer (to allow
external reference, 1 at power-up)
D3 Power down the temperature sensor
D2 Power down I
SENSE
1
D1 Power down ISENSE2
D0 DAC outputs set to high impedance (set
automatically if die temperature >150°C)
In normal operation, the two MSBs of the I2C slave address are
set to 11 by an internal ROM. However, in full power-down
mode (power down by setting Bit D7 = 1), this ROM is switched
off and the slave address MSBs become 00. Therefore, to exit the
full-power-down state, it is necessary to write to the AD7294
using this modified slave address.
After writing 0 to power down Bit D7, the slave address MSBs
return to their original 11 value.
DATAHIGH/DATALOW REGISTERS: 0x0B, 0x0C (VIN0);
0x0E, 0x0F (VIN1); 0x11, 0x12 (VIN2); 0x14, 0x15 (VIN3)
The DATAHIGH and DATALOW registers for a channel are 16-bit,
read/write registers (see Table 29 and Table 30). General alert is
flagged by the MSB, D15. D14 to D12 are not used in the register
and are set to 0s. The remaining 12 bits set the high and low limits
for the relevant channel. For single-ended mode, the default values
for VIN0 to VIN3, are 000 and FFF in binary format. For differen-
tial mode on VIN0 to VIN3, the default values for DATAHIGH and
DATALOW are 7FF and 800, twos complement format. Note that if
the part is configured in either single-ended or differential mode
and the mode is changed, the user must reprogram the limits in
the DATAHIGH and DATALOW registers.
Channel 7 to Channel 9 (TSENSE1, TSENSE2, and TSENSEINT) default
to 3FF and 400 for the DATAHIGH and DATALOW limits because
they are in twos complement 11-bit format.
Table 28. Default Values for DATAHIGH and DATALOW
Registers
ADC
Channel
Single-Ended Differential
DATALOW DATAHIGH DATALOW DATAHIGH
VIN0 000 FFF 800 7FF
VIN1 000 FFF 800 7FF
VIN2 000 FFF 800 7FF
VIN3 000 FFF 800 7FF
ISENSE1 N/A N/A 800 7FF
ISENSE2 N/A N/A 800 7FF
TSENSE1 N/A N/A 400 3FF
TSENSE2 N/A N/A 400 3FF
T
SENSE
INT N/A N/A 400 3FF
Table 29. AD7294 DATAHIGH/LOW Register (First Read/Write)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8
Alert_Flag 0 0 0 B11 B10 B9 B8
Table 30. AD7294 DATAHIGH/LOW Register (Second Read/Write)
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1 B0
HYSTERESIS REGISTERS: 0x0D (VIN0), 0x10 (VIN1),
0x13 (VIN2), 0x16 (VIN3)
Each hysteresis register is a 16-bit read/write register wherein
only the 12 LSBs of the register are used; the MSB signals the
alert event. If FFF is written to the hysteresis register, the hyste-
resis register enters the minimum/maximum mode, see the
Alerts and Limits Theory section for further details.
Table 31. Hysteresis Register (First Read/Write)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8
Alert_Flag 0 0 0 B11 B10 B9 B8
Table 32. Hysteresis Register (Second Read/Write)
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1 B0
Data Sheet AD7294
Rev. H | Page 33 of 48
TSENSE OFFSET REGISTERS (0x26 AND 0x27)
The AD7294 has temperature offset, 8-bit twos complement regis-
ters for both Remote Channel TSENSE1 and Remote Channel TSENSE2.
It allows the user to add or subtract an offset to the temperature.
The offset registers for TSENSE1 and TSENSE2 are 8-bit read/write
registers that store data in a twos complement format. This data
is subtracted from the temperature readings taken by TSENSE1
and TSENSE2 temperature sensors. The offset is implemented
before the values are stored in the TSENSE result register.
The offset registers can be used to compensate for transistors
with different ideality factors because the TSENSE results are
based on the 2N3906 transistor ideality factor. Different
transistors with different ideality factors result in different
offsets within the region of interest, which can be compensated
for by using this register.
Table 33. TSENSE Offset Data Format
Input
MSB
D7 D6 D5 D4 D3 D2 D1
LSB
D0
Value (°C) −32 +16 +8 +4 +2 +1 +0.5 +0.25
AD7294 Data Sheet
Rev. H | Page 34 of 48
I2C INTERFACE
GENERAL I2C TIMING
Figure 50 shows the timing diagram for general read and write
operations using an I2C-compliant interface.
The I2C bus uses open-drain drivers; therefore, when no device
is driving the bus, both SCL and SDA are high. This is known as
idle state. When the bus is idle, the master initiates a data transfer
by establishing a start condition, defined as a high-to-low
transition on the serial data line (SDA) while the serial clock line
(SCL) remains high. This indicates that a data stream follows. The
master device is responsible for generating the clock.
Data is sent over the serial bus in groups of nine bits—eight bits
of data from the transmitter followed by an acknowledge bit (ACK)
from the receiver. Data transitions on the SDA line must occur
during the low period of the clock signal and remain stable
during the high period. The receiver should pull the SDA line
low during the acknowledge bit to signal that the preceding byte
has been received correctly. If this is not the case, cancel the
transaction.
The first byte that the master sends must consist of a 7-bit slave
address, followed by a data direction bit. Each device on the bus
has a unique slave address; therefore, the first byte sets up
communication with a single slave device for the duration of the
transaction.
The transaction can be used either to write to a slave device
(data direction bit = 0) or to read data from it (data direction
bit = 1). In the case of a read transaction, it is often necessary
first to write to the slave device (in a separate write transaction)
to tell it from which register to read. Reading and writing
cannot be combined in one transaction.
When the transaction is complete, the master can keep control
of the bus, initiating a new transaction by generating another
start bit (high-to-low transition on SDA while SCL is high). This
is known as a repeated start (Sr). Alternatively, the bus can be
relinquished by releasing the SCL line followed by the SDA line.
This low-to-high transition on SDA while SCL is high is known
as a stop bit (P), and it leaves the I2C bus in its idle state (no
current is consumed by the bus).
The example in Figure 50 shows a simple write transaction
with an AD7294 as the slave device. In this example, the
AD7294 register pointer is being set up ready for a future read
transaction.
P7 P6 P5 P4 P3 P2 P1 P0
START CO ND
BY MASTER ACK. BY
AD7294
SLAVE ADDRESS BYTE ACK. BY
AD7294
SCL
SDA
REGISTER ADDRE S S STOP BY
MASTER
USER PROG RAM M ABLE 5 LSBs
R/W
A6 A5 A4 A3 A2 A1 A0
05747-040
Figure 50. General I2C Timing
Data Sheet AD7294
Rev. H | Page 35 of 48
SERIAL BUS ADDRESS BYTE
The first byte the user writes to the device is the slave address
byte. Similar to all I2C-compatible devices, the AD7294 has a
7-bit serial address. The 5 LSBs are user-programmable by the
3 three-state input pins, as shown in Table 34.
In Table 34, H means tie the pin to VDRIVE, L means tie the pin
to DGND, and NC refers to a pin left floating. Note that in this
final case, the stray capacitance on the pin must be less than
30 pF to allow correct detection of the floating state; therefore,
any PCB trace must be kept as short as possible.
Table 34. Slave Address Control Using Three-State Input Pins
AS2 AS1 AS0 Slave Address (A6 to A0)
L L L 0x61
L L H 0x62
L L NC 0x63
L H L 0x64
L H H 0x65
L H NC 0x66
L NC L 0x67
L NC H 0x68
L NC NC 0x69
H L L 0x6A
H L H 0x6B
H L NC 0x6C
H H L 0x6D
H H H 0x6E
H H NC 0x6F
H NC L 0x70
H NC H 0x71
H NC NC 0x72
NC L L 0x73
NC L H 0x74
NC L NC 0x75
NC H L 0x76
NC H H 0x77
NC H NC 0x78
NC NC L 0x79
NC NC H 0x7A
NC NC NC 0x7B
INTERFACE PROTOCOL
The AD7294 uses the following I2C protocols.
Writing a Single Byte of Data to an 8-Bit Register
The alert registers (0x05, 0x06, 0x07), power-down register
(0x0A), channel sequence register (0x08), temperature offset
registers (0x26, 0x27), and the command register (0x00) are
8-bit registers; therefore, only one byte of data can be written to
each. In this operation, the master device sends a byte of data to
the slave device, see Figure 51. To write data to the register, the
command sequence is as follows:
1. The master device asserts a start condition.
2. The master sends the 7-bit slave address followed by a zero
for the direction bit, indicating a write operation.
3. The addressed slave device asserts an acknowledge on SDA.
4. The master sends a register address.
5. The slave asserts an acknowledge on SDA.
6. The master sends a data byte.
7. The slave asserts an acknowledge on SDA.
8. The master asserts a stop condition to end the transaction.
AD7294 Data Sheet
Rev. H | Page 36 of 48
SDA
1 1 99
P0P1P2P3P4P5P6P7
R/W
A4 A3 A2 A1 A0A6
SCL
A5
1 9
SDA (CONTINUED)
SCL ( CONTINUED)
ST ART BY
MASTER ACK. BY
AD7294 ACK. BY
AD7294
FRAM E 1
SLAVE ADDRESS BYTE FRAM E 2
ADDRESS P OINTER RE GIS TER BY TE
SSL AV E ADDRE S S 0 A REG POINTER ADATA A P
FRAM E 3
DATA BY TE
ACK. BY
AD7294 STOP BY
MASTER
D0D1D2D3D4D5D6D7
FROM MASTER TO SL AVE
FROM SLAVE TO MASTER
S = START CONDITION
SR = REP E ATED S TART
P = STOP CONDITION
A = ACKNOWL E DGE
A = NOT ACKNO WL E DGE
05747-061
Figure 51. Single Byte Write Sequence
Data Sheet AD7294
Rev. H | Page 37 of 48
Writing Two Bytes of Data to a 16-Bit Register
The limit and hysteresis registers (0x0B to 0x25), the result
registers (0x01 to 0x04), and the configuration register (0x09)
are 16-bit registers; therefore, two bytes of data are required to
write a value to any one of these registers. Writing two bytes of
data to one of these registers consists of the following sequence:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an acknowledge on SDA.
4. The master sends a register address. The slave asserts an
acknowledge on SDA.
5. The master sends the first data byte (most significant).
6. The slave asserts an acknowledge on SDA.
7. The master sends the second data byte (least significant).
8. The slave asserts an acknowledge on SDA.
9. The master asserts a stop condition on SDA to end the
transaction.
Writing to Multiple Registers
Writing to multiple address registers consists of the following:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device (AD7294) asserts an
acknowledge on SDA.
4. The master sends a register address, for example the Alert
Status Register A register address. The slave asserts an
acknowledge on SDA.
5. The master sends the data byte.
6. The slave asserts an acknowledge on SDA.
7. The master sends a second register address, for example
the configuration register. The slave asserts an
acknowledge on SDA.
8. The master sends the first data byte.
9. The slave asserts an acknowledge on SDA.
10. The master sends the second data byte.
11. The slave asserts an acknowledge on SDA.
12. The master asserts a stop condition on SDA to end the
transaction.
The previous examples detail writing to two registers only
(the Alert Status Register A and the configuration register).
However, the AD7294 can read from multiple registers in one
write operation as shown in Figure 53.
05747-059
SSLAV E ADDRE S S 0AREG POINTER ADATA<15:8> A PDATA<7:0> A
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
SR = REP E ATED S TART
P = STOP CONDITION
A = ACKNOWL E DGE
A = NOT ACKNO WL E DGE
Figure 52. Writing Two Bytes of Data to a 16-Bit Register
05747-054
SSLAV E ADDRE S S 0 A POINT TO CONFIG REG (0x09)A
DATA<15:8>
A
P
DATA<7:0> APOINT TO P D RE G (0x0A)
DATA<7:0>A A
...
...
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
SR = REP E ATED S TART
P = STOP CONDITION
A = ACKNOWL E DGE
A = NOT ACKNO WL E DGE
Figure 53. Writing to Multiple Registers
AD7294 Data Sheet
Rev. H | Page 38 of 48
Reading Data from an 8-Bit Register
Reading the contents from any of the 8-bit registers is a single
byte read operation, as shown in Figure 55. In this protocol, the
first part of the transaction writes to the register pointer. When
the register address has been set up, any number of reads can be
performed from that particular register without having to write
to the address pointer register again. When the required number
of reads is completed, the master should not acknowledge the final
byte. This tells the slave to stop transmitting, allowing a stop
condition to be asserted by the master. Further reads from this
register can be performed in a future transaction without
having to rewrite to the register pointer.
If a read from a different address is required, the relevant
register address has to be written to the address pointer register,
and again, any number of reads from this register can then be
performed. In the next example, the master device receives two
bytes from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts an acknowledge
on SDA.
4. The master receives a data byte.
5. The master asserts an acknowledge on SDA.
6. The master receives another 8-bit data byte.
7. The master asserts a no acknowledge (NACK) on SDA to
inform the slave that the data transfer is complete.
8. The master asserts a stop condition on SDA, and the
transaction ends.
Reading Two Bytes of Data from a 16-Bit Register
In this example, the master device reads three lots of two-byte
data from a slave device, but as many lots consisting of two-
bytes can be read as required. This protocol assumes that the
particular register address has been set up by a single byte write
operation to the address pointer register (see the previous read
example).
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts an acknowledge
on SDA.
4. The master receives a data byte.
5. The master asserts an acknowledge on SDA.
6. The master receives a second data byte.
7. The master asserts an acknowledge on SDA.
8. The master receives a data byte.
9. The master asserts an acknowledge on SDA.
10. The master receives a second data byte.
11. The master asserts an acknowledge on SDA.
12. The master receives a data byte.
13. The master asserts an acknowledge on SDA.
14. The master receives a second data byte.
15. The master asserts a no acknowledge on SDA to notify the
slave that the data transfer is complete.
16. The master asserts a stop condition on SDA to end the
transaction.
05747-060
S A
P
...
...
1 A
A
A A A
A
SLAV E ADDRE S S
DATA<7:0>
DATA<7:0> DATA<7:0>
DATA<15:8>
DATA<15:8> DATA<15:8>
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
SR = REP E ATED S TART
P = STOP CONDITION
A = ACKNOWL E DGE
A = NOT ACKNO WL E DGE
Figure 54. Reading Three Lots of Two Bytes of Data from the Conversion Result Register
05747-055
S0 A A A
P
REG POINTER
...
...
SR 1 A
A
SLAV E ADDRE S S SLAV E ADDRE S S
DATA<7:0>
DATA<7:0>
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
S = START CONDITION
SR = REP E ATED S TART
P = STOP CONDITION
A = ACKNOWL E DGE
A = NOT ACKNO WL E DGE
Figure 55. Reading Two Single Bytes of Data from a Selected Register
Data Sheet AD7294
Rev. H | Page 39 of 48
MODES OF OPERATION
There are two different methods of initiating a conversion on
the AD7294: command mode and autocycle mode.
COMMAND MODE
In command mode, the AD7294 ADC converts on-demand on
either a single channel or a sequence of channels. To enter this
mode, the required combination of channels is written into the
command register (0x00). The first conversion takes place at the
end of this write operation, in time for the result to be read out
in the next read operation. While this result is being read out,
the next conversion in the sequence takes place, and so on.
To exit the command mode, the master should not acknowledge
the final byte of data. This stops the AD7294 transmitting,
allowing the master to assert a stop condition on the bus. It is
therefore important that, after writing to the command register,
a repeated start (Sr) signal be used rather than a stop (P) followed
by a start (S) when switching to read mode; otherwise, the
command mode exits after the first conversion.
After writing to the command register, the register pointer is
returned to its previous value. If a new pointer value is required
(typically the ADC Result Register 0x01), it can be written
immediately following the command byte. This extra write
operation does not affect the conversion sequence because the
second conversion triggers only at the start of the first read
operation.
The maximum throughput that can be achieved using this
mode with a 400 kHz I2C clock is (400 kHz/18) = 22.2 kSPS.
Figure 56 shows the command mode converting on a sequence
of channels including VIN0, VIN1, and ISENSE1.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device (AD7294) asserts an
acknowledge on SDA.
4. The master sends the Command Register Address 0x00.
The slave asserts an acknowledge on SDA.
5. The master sends the Data Byte 0x13 which selects the
VIN0, VIN1, and ISENSE1 channels.
6. The slave asserts an acknowledge on SDA.
7. The master sends the result register address (0x01). The
slave asserts an acknowledge on SDA.
8. The master sends the 7-bit slave address followed by the
write bit (high).
9. The slave (AD7294) asserts an acknowledge on SDA.
10. The master receives a data byte, which contains the
alert_flag bit, the channel ID bits, and the four MSBs of the
converted result for Channel VIN0. The master then asserts
an acknowledge on SDA.
11. The master receives the second data byte, which contains
the eight LSBs of the converted result for Channel VIN0.
The master then asserts on acknowledge on SDA.
12. Point 10 and Point 11 repeat for Channel VIN1 and
Channel ISENSE1.
13. Once the master has received the results from all the
selected channels, the slave again converts and outputs
the result for the first channel in the selected sequence.
Point 10 to Point 12 are repeated.
14. The master asserts a no acknowledge on SDA and a stop
condition on SDA to end the conversion and exit
command mode.
The AD7294 automatically exits command mode if no read
occurs in a 5 ms period. To change the conversion sequence,
rewrite a new sequence to the command mode.
05747-056
S A
P
...
...
0 A ACOM M AND = 0x13
A
VIN0<11:8>
A
PO INT TO RE S ULT RE G (0x01) SR 1 A
*
ACH ID ( 000)ALERT?
...
ACH ID ( 001)ALERT? A
...
A
ISENSE1<11:8>
*
*
*
*
A A
...
...
A
VIN0<7:0>
...........
A
* = POSITION OF A CONVERSION START
SL AV E ADDRE S S
PO INT TO COMMAND RE G (0x00)
VIN1<7:0>VIN0<7:0> VIN1<11:8>
VIN0<11:8>
SL AV E ADDRE S S
ISENSE1<7:0>
ISENSE1<7:0>
ALERT? CH I D ( 100) ALERT? CH ID ( 000)
FROM MASTER TO SL AVE
FROM SLAVE TO MASTER
S = START CONDITION
SR = REP E ATED S TART
P = STOP CONDITION
A = ACKNOWL E DGE
A = NOT ACKNO WL E DGE
Figure 56. Command Mode Operation
AD7294 Data Sheet
Rev. H | Page 40 of 48
AUTOCYCLE MODE
The AD7294 can be configured to convert continuously on a
programmable sequence of channels making it the ideal mode
of operation for system monitoring. These conversions take
place in the background approximately every 50 µs, and are
transparent to the master. Typically, this mode is used to
automatically monitor a selection of channels with either the
limit registers programmed to signal an out-of-range condition
via the alert function or the minimum/maximum recorders
tracking the variation over time of a particular channel. Reads
and writes can be performed at any time (the ADC Result
Register 0x01 contains the most recent conversion result).
On power up, this mode is disabled. To enable this mode, write
to Bit D12 in the configuration register (0x09) and select the
desired channels for conversion in the channel sequence
register (0x08).
If a command mode conversion is required while the autocycle
mode is active, it is necessary to disable the autocycle mode before
proceeding to the command mode. This is achieved either by clear-
ing Bit D12 of the configuration register or by writing 0x00 to the
channel sequence register. When the command mode conversion is
complete, the user must exit command mode by issuing a stop
condition before reenabling autocycle mode.
When switching out of autocycle mode to command mode,
the temperature sensor must be given sufficient time to settle
and complete a new temperature integration cycle. Therefore,
temperature sensor conversions performed within the first
500 ms after switching from autocycle mode to command mode
may result in false temperature high and low alarms being
triggered. It is recommended to disable temperature sensor
alarms for the first 500 ms after mode switching by writing
0x400 to the DATALOW TSENSEx register and 0x3FF to the
DATAHIGH register TSENSEx. The temperature sensor alerts should
be reconfigured to the desired alarm level once the 500 ms has
elapsed. Alternatively, temperature alerts triggered during the
first 500 ms after mode switching should be ignored.
Data Sheet AD7294
Rev. H | Page 41 of 48
ALERTS AND LIMITS THEORY
ALERT_FLAG BIT
The alert_flag bit indicates whether the conversion result being
read or any other channel result has violated the limit registers
associated with it. If an alert occurs and the alert_flag bit is set,
the master can read the alert status register to obtain more
information on where the alert occurred.
ALERT STATUS REGISTERS
The alert status registers are 8-bit read/write registers that provide
information on an alert event. If a conversion results in activa-
tion of the ALERT/BUSY pin or the alert_flag bit in the result
register or TSENSE registers, the alert status register can be read to
get more information (see Figure 57 for the alert register
structure).
05747-057
ALERT
REGISTER
A
ALERT
REGISTER
B
ALERT
REGISTER
C
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
VIN3 HIGH AL E RT
VIN3 LOW ALERT
VIN2 HIGH AL E RT
VIN2 LOW ALERT
VIN1 HIGH AL E RT
VIN1 LOW ALERT
VIN0 HIGH AL E RT
VIN0 LOW ALERT
RESERVED
RESERVED
ISENSE2 O V E RRANGE*
ISENSE2 HI GH ALE RT
ISENSE1 O V E RRANGE*
ISENSE2 L OW ALERT
ISENSE1 L OW ALERT
ISENSE1 HI GH ALE RT
OPEN DIODE FLAG*
OVER TEMP ALERT*
TSENSEI NT HIGH ALE RT
TSENSE2 HI GH ALE RT
TSENSEINT LOW ALERT
TSENSE2 L OW ALERT
TSENSE1 L OW ALERT
TSENSE1 HI GH ALE RT
ALERT
FLAG
OR ALERT/BUSY
CONFIGURATION
REGISTER
D2 = 1, D1 = 0
*THES E BIT S ARE ALWAY S ACTIV E , AL L OTHER BI TS CAN BE
PROGRAMM E D TO BE ACTIV E OR NO T AS REQUIRE D.
Figure 57. Alert Register Structure
Register A (see Table 19) consists of four channels with two status
bits per channel, one corresponding to each of the DATAHIGH and
DATALOW limits. It stores the alert event data for VIN3 to VIN0,
which are the standard voltage inputs. When the content of this
register is read, any bit with a status of 1 indicates a violation of
its associated limit; that is, it identifies the channel and whether
the violation occurred on the upper or lower limit. If a second
alert event occurs on another channel before the content of the
alert register has been read, the bit corresponding to the second
alert event is also set.
Register B (see Table 20) consists of three channels also with
two status bits per channel, representing the specified DATAHIGH
and DATALOW limits. Bits[D3:D0] correspond to the high and low
limit alerts for the current sense inputs. Bit D4 and Bit D5 represent
the ISENSE1 OVERRANGE and ISENSE2 OVERRANGE of VREF/10.41.
During power-up, it is possible for the fault outputs to be trig-
gered, depending on which supply comes up first. Clearing these
bits as part of the initialization routine is recommended on
power-up by writing a 1 to both D4 and D5.
Internal circuitry in the AD7294 can alert if either the D1± or
the D2± input pins for the external temperature sensor are open
circuit. The most significant bit of Register C (see Table 21)
alerts the user when an open diode flag occurs on the external
temperature sensors. If the internal temperature sensor detects
an AD7294 die temperature greater than 150°C, the overtem-
perature alert bit, Bit D6 in Register C, is set and the DAC
outputs are set to a high impedance sate. The remaining six
bits in Register 6 store alert event data for TSENSE1, TSENSE2, and
TSENSEINT with two status bits per channel, one corresponding to
each of the DATAHIGH and DATALOW limits.
To clear the full content of any one of the alert registers, write a
code of FF (all ones) to the relevant registers. Alternatively, the
user can write to the respective alert bit in the selected alert
register to clear the alert associated with that bit. The entire
contents of all the alert status registers can be cleared by writing
a 1 to Bit D1 and Bit D2 in the configuration register, as shown
in Table 24. However, this operation then enables the ALERT/
BUSY pin for subsequent conversions.
DATAHIGH AND DATALOW MONITORING FEATURES
The AD7294 signals an alert (in either hardware via the
ALERT/BUSY pin, software via the alert_flag bit, or both,
depending on the configuration) if the result moves outside the
upper or lower limit set by the user.
The DATAHIGH register stores the upper limit that activates the
ALERT/BUSY output pin and/or the alert_flag bit in the conver-
sion result register. If the conversion result is greater than the value
in the DATAHIGH register, an alert occurs. The DATALOW register
stores the lower limit that activates the ALERT/BUSY output pin
and/or the alert_flag bit in the conversion result register. If the
conversion result is less than the value in the DATALOW register,
an alert occurs.
An alert associated with either the DATAHIGH or DATALOW
register is cleared automatically once the monitored signal is
back in range; that is, the conversion result is between the limits.
The content of the alert register is updated after each conversion.
A conversion is performed every 50 µs in autocycle mode,
so the content of the alert register may change every 50 µs. If
the ALERT pin signals an alert event and the content of the alert
register is not read before the next conversion is complete, the
content of the register may be changed if the signal being
monitored returns between the prespecified limits. In these circum-
stances, the ALERT pin no longer signals the occurrence of an
alert event.
AD7294 Data Sheet
Rev. H | Page 42 of 48
The hysteresis register can be used to avoid flicker on the ALERT/
BUSY pin. If the hysteresis function is enabled, the conversion
result must return to a value of at least N LSB below the DATAHIGH
register value, or N LSB above the DATALOW register value for the
ALERT/BUSY output pin and alert_flag bit to be reset. The value of
N is taken from the 12-bit hysteresis register associated with that
channel. By setting the hysteresis register to a code close to the
maximum output code for the ADC, that is, 0x77D, DATAHIGH
or DATALOW alerts do not clear automatically by the AD7294.
Bit D11 of the TSENSE DATAHIGH or DATALOW limit registers is
the diode open-circuit flag. If this bit is set to 0, it indicates the
presence of an open circuit between the Dx+ and Dx− pins. An
alert triggered on either ISENSE OVERRANGE pin remains until it
is cleared by the user writing to the alert register. The contents
of the DATAHIGH and DATALOW registers are reset to their default
values on power-up (see Table 28).
HYSTERESIS
The hysteresis value determines the reset point for the ALERT/
BUSY pin and/or alert_flag bit if a violation of the limits occurs.
The hysteresis register stores the hysteresis value, N, when using
the limit registers. Each pair of limit registers has a dedicated
hysteresis register. For example, if a hysteresis value
of 8 LSBs is required on the upper and lower limits of VIN0,
the 16-bit word 0000 0000 0000 1000 should be written to the
hysteresis register of VIN0 (see Table 9). On power-up, the
hysteresis registers contain a value of 8 LSBs for nontempera-
ture result registers and 8°C, or 32 LSBs, for the TSENSE registers.
If a different hysteresis value is required, that value must be
written to the hysteresis register for the channel in question.
The advantage of having hysteresis registers associated with
each of the limit registers is that it prevents chatter on the alert
bits associated with each ADC channel. Figure 58 shows the
limit checking operation.
Using the Limit Registers to Store Minimum/Maximum
Conversion Results
If FFF is written to the hysteresis register for a particular channel,
the DATAHIGH and DATALOW registers for that channel no longer
act as limit registers as previously described, but act as storage
registers for the maximum and minimum conversion results.
This function is useful when an alert signal is not required in an
application, but it is still required to monitor the minimum and
maximum conversion values over time. Note that on power-up,
the contents of the DATAHIGH register for each channel are set to
maximum code, whereas the contents of the DATALOW registers
are set to minimum code by default.
HIGH LIMIT
LOW LIMIT
HIGH LIMIT – HYSTERESIS
LOW LIMIT + HYSTERESIS
TIME
INP UT SI GNAL
ALE RT SI GNAL
05747-067
Figure 58. Limit Checking
Data Sheet AD7294
Rev. H | Page 43 of 48
APPLICATIONS INFORMATION
The AD7294 contains all the functions required for general-
purpose monitoring and control of current, voltage, and
temperature. With its 59.4 V maximum common-mode range,
the device is useful in industrial and automotive applications where
current sensing in the presence of a high common-mode voltage
is required. For example, the part is ideally suited for monitoring
and controlling a power amplifier in a cellular base station.
BASE STATION POWER AMPLIFIER MONITOR AND
CONTROL
The AD7294 is used in a power amplifier signal chain to
achieve the optimal bias condition for the LDMOS transistor.
The main factors influencing the bias conditions are tempera-
ture, supply voltage, gate voltage drift, and general processing
parameters. The overall performance of a power amplifier
configuration is determined by the inherent tradeoffs required
in efficiency, gain, and linearity. The high level of integration
offered by the AD7294 allows the use of a single chip to
dynamically control the drain bias current to maintain a constant
value over temperature and time, thus significantly improving
the overall performance of the power amplifier. The AD7294
incorporates the functionality of eight discrete components
bringing considerable board area savings over alternative
solutions.
The circuit in Figure 59 is a typical system connection diagram
for the AD7294. The device monitors and controls the overall
performance of two final stage amplifiers. The gain control and
phase adjustment of the driver stage are incorporated in the
application and are carried out by the two available uncommitted
outputs of the AD7294. Both high-side current senses measure
the amount of current on the respective final stage amplifiers.
The comparator outputs, ISENSE1 OVERRANGE and ISENSE2
OVERRANGE pins, are the controlling signals for switches
on the RF inputs of the LDMOS power FETs. If the high-side
current sense reads a value above a specified limit compared
with the setpoint, the RF IN signal is switched off by the
comparator.
By measuring the transmitted power (Tx) and the received
power (Rx), the device can dynamically change the drivers and
PA signal to optimize performance. This application requires a
logarithmic detector/controller, such as Analog Devices AD8317
or AD8362.
COMPARATORS
AND REG IST E RS
MUX
TEMP
SENSOR
HIGH SI DE
CURRENT
SENSE
HIGH SI DE
CURRENT
SENSE
T1 T2
V
OUT
A
V
OUT
B
V
OUT
C
FILTER
FILTER
RF CHOKE
RF OUT
LDMOS
RS1(+) RS2(+) RS2(–)RS1(–)
RS2(–)
D1+
D2+
D2–
D1–
SET-POINT
240mV
I
SENSE
1
OVERRANGE
I
SENSE
2
OVERRANGE
GAIN
CONTROL
R
SENSE
R
SENSE
V
DD
LDMOS
RF OUT
12-BIT
ADC
V
IN
0
V
IN
1
V
IN
2
V
IN
3
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC V
OUT
DGAIN
CONTROL
RF CHOKE
Tx POWER
MONITOR
Rx PO WER
MONITOR
Tx
POWER
RF CUTOFF
Rx
POWER
AD7294*
RF IN
RF IN
*ADDITIONAL PINS OMITTED FOR CLARITY.
REF
REF
05747-036
Figure 59. Typical HPA Monitor and Control Application
AD7294 Data Sheet
Rev. H | Page 44 of 48
GAIN CONTROL OF POWER AMPLIFIER
In gain control mode, a setpoint voltage, proportional in dB to
the desired output power, is applied to a power detector such as
the AD8362. A sample of the output power from the power
amplifier (PA), through a directional coupler and attenuator (or
by other means), is fed to the input of the AD8362. The VOUT
is connected to the gain control terminal of the PA, see Figure 60.
Based on the defined relationship between VOUT and the RF
input signal, the AD8362 adjusts the voltage on VOUT (VOUT
is now an error amplifier output) until the level at the RF input
corresponds to the applied VSET. The AD7294 completes a
feedback loop that tracks the output of the AD8362 and adjusts
the VSET input of the AD8362 accordingly.
VOUT of the AD8362 is applied to the gain control terminal of
the power amplifier. For this output power control loop to be
stable, a ground referenced capacitor must be connected to the
CLPF pin. This capacitor integrates the error signal (which is
actually a current) that is present when the loop is not balanced.
In a system where a variable gain amplifier (VGA) or variable
voltage attenuator (VVA) feeds the power amp, only one AD8362
is required. In such a case, the gain on one of the parts (VVA,
PA) is fixed and VOUT feeds the control input of the other.
C5
1nF C7
0.1nF
C6
0.1nF
1:4
T2
AD8362
AD7294
C
LPF
ENVELOPE OF
TRANSMITTED
SIGNAL
DIRECTIONAL
COUPLER
ATTENUATOR
POWER
AMPLIFIER RF IN
V
IN
V
OUT
VOUT
VSET
INLO
INHI
05747-037
Figure 60. Setpoint Controller Operation
Data Sheet AD7294
Rev. H | Page 45 of 48
LAYOUT AND CONFIGURATION
POWER SUPPLY BYPASSING AND GROUNDING
For optimum performance, carefully consider the power supply
and ground return layout on any PCB where the AD7294 is
used. The PCB containing the AD7294 should have separate
analog and digital sections, each having its own area of the
board. The AD7294 should be located in the analog section
on any PCB.
Decouple the power supply to the AD7294 to ground with
10 µF and 0.1 µF capacitors. Place the capacitors as physically
close as possible to the device, with the 0.1 µF capacitor ideally
right up against the device. It is important that the 0.1 µF
capacitor have low effective series resistance (ESR) and low
effective series inductance (ESL); common ceramic types of
capacitors are suitable. The 0.1 µF capacitor provides a low
impedance path to ground for high frequencies caused by
transient currents due to internal logic switching. The 10 µF
capacitors are the tantalum bead type.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Shield clocks and other components with fast
switching digital signals from other parts of the board by a
digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects on the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side; however, this is not
always possible with a 2-layer board.
Layout Considerations for External Temperature Sensors
Power amplifier boards can be electrically noisy environments,
and care must be taken to protect the analog inputs from noise,
particularly when measuring the very small voltages from a
remote diode sensor.
Take the following precautions:
• Place the remote sensing diode as close as possible to
the AD7294. If the worst noise sources are avoided, this
distance can be 4 inches to 8 inches.
• Route the D+ and D− tracks close together, in parallel,
with grounded guard tracks on each side. Provide a ground
plane under the tracks, if possible.
• Use wide tracks to minimize inductance and reduce noise
pickup. A 10 mil track minimum width and spacing is
recommended, as shown in Figure 61.
AGND
D1+
D1–
AGND
0.25mm
0.25mm
0.25mm
0.25mm
0.25mm
0.25mm
0.25mm
05747-049
Figure 61. Arrangement of Signal Tracks
• Try to minimize the number of copper/solder joints
because they can cause thermocouple effects. Where
copper/solder joints are used, make sure that they are
in both the Dx+ and Dx− path and are at the same
temperature.
• Place a 10 pF capacitor between the base and emitter of the
discrete diode, as close as possible to the diode.
• If the distance to the remote sensor is more than 20 cm, the
use of twisted-pair cable is recommended.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor can
be reduced or removed.
AD7294 Data Sheet
Rev. H | Page 46 of 48
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MS - 026- ABD
1.20
MAX
33
48
64
1
17
16 32
49
0.40
BSC
LE AD P IT CH
0.75
0.60
0.45
9.20
9.00 S Q
8.80
7.20
7.00 S Q
6.80
0.23
0.18
0.13
TOP VIEW
(P INS DOW N)
PI N 1
VIEW A
1.05
1.00
0.95
0.20
0.09
0.08 M AX
COPLANARITY
SEATING
PLANE
0° M IN
7°
3.5°
0°
0.15
0.05
VIEW A
ROTATED 90° CCW
012108-A
Figure 62. 64-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-64-1)
Dimensions shown in millimeters
COMPLIANT TO JE DE C S TANDARDS MO-220- V LL D- 2
030509-A
PI N 1
INDICATOR
TOP
VIEW 7.75
BSC SQ
8.00
BSC SQ
1
56
14
15
43
42
28
29
6.25
6.10 S Q
5.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BS C 0.20 RE F
12° M AX 0.80 MAX
0.65 TYP
1.00
0.85
0.80
6.50
REF
SEATING
PLANE
0.60 M AX
0.60 M AX PI N 1
INDICATOR
COPLANARITY
0.08
0.05 M AX
0.02 NOM
0.25 M IN
EXPOSED
PAD
(BOTTOM VIEW )
FOR PROPE R CONNECTI ON OF
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURAT IO N AND
FUNCTI ON DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
Figure 63. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
8 mm × 8 mm body, Very Thin Quad
(CP-56-1)
Dimensions shown in millimeters
Data Sheet AD7294
Rev. H | Page 47 of 48
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7294BSUZ −40°C to +105°C 64-Lead Thin Plastic Quad Flat Package [TQFP] SU-64-1
AD7294BSUZRL −40°C to +105°C 64-Lead Thin Plastic Quad Flat Package [TQFP] SU-64-1
AD7294BCPZ −40°C to +105°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-1
AD7294BCPZRL −40°C to +105°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-1
EVAL-AD7294EBZ Evaluation Board
1 Z = RoHS Compliant Part.
AD7294 Data Sheet
Rev. H | Page 48 of 48
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05747-0-1/12(H)