Precision Lowest Cost
ISOLATION AMPLIFIER
FEATURES
●100% TESTED FOR HIGH-VOLTAGE
BREAKDOWN
●RATED 1500Vrms
●HIGH IMR: 140dB at 60Hz
●BIPOLAR OPERATION: VO = ±10V
●16-PIN PLASTIC DIP AND 28-LEAD SOIC
●EASE OF USE: Fixed Unity Gain
Configuration
●0.020% max NONLINEARITY
●±4.5V to ±18V SUPPLY RANGE
APPLICATIONS
●INDUSTRIAL PROCESS CONTROL:
Transducer Isolator, Isolator for Thermo-
couples, RTDs, Pressure Bridges, and
Flow Meters, 4mA to 20mA Loop Isolation
●GROUND LOOP ELIMINATION
●MOTOR AND SCR CONTROL
●POWER MONITORING
●PC-BASED DATA ACQUISITION
●TEST EQUIPMENT
VOUT
VIN
+VS1
ISO122
DESCRIPTION
The ISO122 is a precision isolation amplifier incor-
porating a novel duty cycle modulation-demodulation
technique. The signal is transmitted digitally across
a 2pF differential capacitive barrier. With digital modu-
lation the barrier characteristics do not affect signal
integrity, resulting in excellent reliability and good high
frequency transient immunity across the barrier. Both
barrier capacitors are imbedded in the plastic body of
the package.
The ISO122 is easy to use. No external components
are required for operation. The key specifications are
0.020% max nonlinearity, 50kHz signal bandwidth,
and 200µV/°C VOS drift. A power supply range of
±4.5V to ±18V and quiescent currents of ±5.0mA on
VS1 and ±5.5mA on VS2 make these amplifiers ideal
for a wide range of applications.
The ISO122 is available in 16-pin plastic DIP and 28-
lead plastic surface mount packages.
–VS1
Gnd
+VS2
–VS2
Gnd
©1989 Burr-Brown Corporation PDS-857F Printed in U.S.A. November, 1993
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
SBOS160
2
®
ISO122
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
SPECIFICATIONS
At TA = +25°C , VS1 = VS2 = ±15V, and RL = 2kΩ unless otherwise noted.
ISO122P/U ISO122JP/JU
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ISOLATION
Voltage Rated Continuous AC 60Hz 1500 * VAC
100% Test (1) 1s, 5pc PD 2400 * VAC
Isolation Mode Rejection 60Hz 140 * dB
Barrier Impedance 1014 || 2 * Ω || pF
Leakage Current at 60Hz VISO = 240Vrms 0.18 0.5 * * µArms
GAIN VO = ±10V
Nominal Gain 1 * V/V
Gain Error ±0.05 ±0.50 * * %FSR
Gain vs Temperature ±10 * ppm/°C
Nonlinearity(2) ±0.016 ±0.020 ±0.025 ±0.050 %FSR
INPUT OFFSET VOLTAGE
Initial Offset ±20 ±50 * * mV
vs Temperature ±200 * µV/°C
vs Supply ±2 * mV/V
Noise 4*µV/√Hz
INPUT
Voltage Range ±10 ±12.5 * * V
Resistance 200 * kΩ
OUTPUT
Voltage Range ±10 ±12.5 * * V
Current Drive ±5±15 * * mA
Capacitive Load Drive 0.1 * µF
Ripple Voltage(3) 20 * mVp-p
FREQUENCY RESPONSE
Small Signal Bandwidth 50 * kHz
Slew Rate 2*V/µs
Settling Time VO = ±10V
0.1% 50 * µs
0.01% 350 * µs
Overload Recover Time 150 * µs
POWER SUPPLIES
Rated Voltage ±15 * V
Voltage Range ±4.5 ±18 * * V
Quiescent Current: VS1 ±5.0 ±7.0 * * mA
VS2 ±5.5 ±7.0 * * mA
TEMPERATURE RANGE
Specification –25 +85 * * °C
Operating –25 +85 * * °C
Storage –40 +85 * * °C
θ
JA 100 * °C/W
θ
JC 65 * °C/W
* Specification same as ISO122P/U.
NOTES: (1) Tested at 1.6 X rated, fail on 5pC partial discharge. (2) Nonlinearity is the peak deviation of the output voltage from the best-fit straight line. It is expressed
as the ratio of deviation to FSR. (3) Ripple frequency is at carrier frequency (500kHz).
3
®
ISO122
Top View —P Package
1
2
7
8
16
15
9
Gnd
VIN
VOUT
–VS1
+VS1
10
+VS2
Gnd
–VS2
Top View—U Package
1
2
28
27
Gnd
VIN
VOUT
–VS1
+VS1
+VS2
Gnd
–VS2
16
15
13
14
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Supply Voltage................................................................................... ±18V
VIN ......................................................................................................±100V
Continuous Isolation Voltage .....................................................1500Vrms
Junction Temperature .................................................................... +150°C
Storage Temperature ....................................................................... +85°C
Lead Temperature (soldering, 10s)................................................ +300°C
Output Short to Common ......................................................... Continuous
PACKAGE INFORMATION(1)
PACKAGE DRAWING
MODEL PACKAGE NUMBER
ISO122P 16-Pin Plastic DIP 238
ISO122JP 16-Pin Plastic DIP 238
ISO122U 28-Pin Plastic SOIC 217-1
ISO122JU 28-Pin Plastic SOIC 217-1
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
NONLINEARITY
MODEL PACKAGE MAX %FSR
ISO122P Plastic DIP ±0.020
ISO122JP Plastic DIP ±0.050
ISO122U Plastic SOIC ±0.020
ISO122JU Plastic SOIC ±0.050
ORDERING INFORMATION
4
®
ISO122
+10
0
–10
0
Output Voltage (V)
500
Time (µs)
SINE RESPONSE
(f = 2kHz)
1000
Time (µs)
+10
0
–10
0
Output Voltage (V)
100
50
SINE RESPONSE
(f = 20kHz)
Time (µs)
+10
0
–10
0
Output Voltage (V)
STEP RESPONSE
100
50
Time (µs)
+10
0
–10
0
Output Voltage (V)
STEP RESPONSE
500 1000
TYPICAL PERFORMANCE CURVES
TA = +25°C, VS = ±15V unless otherwise noted.
100
0
100M10M
ISOLATION VOLTAGE
vs FREQUENCY
Typical
Performance
Frequency (Hz)
100k10k
Max DC Rating
1k
Peak Isolation Voltage
Degraded
Performance
100 1k 1M
2.1k
IMR vs FREQUENCY
1M1
Frequency (Hz)
160
140
120
100
80
60
40 10 100 100k10k
1k
IMR (dB)
5
®
ISO122
TYPICAL PERFORMANCE CURVES
TA = +25°C, VS = ±15V unless otherwise noted.
PSRR vs FREQUENCY
60
40
20
0
Frequency (Hz)
1 10 100 1k 10k 100k 1M
54
PSRR (dB)
–V
S1
, –V
S2
+V
S1
, +V
S2
Frequency (Hz)
100mA
10mA
1mA
100µA
10µA
1µA
0.1µA1 10 100 1k 10k 100k 1M
ISOLATION LEAKAGE CURRENT
vs FREQUENCY
Leakage Current (rms)
1500Vrms
240Vrms
Input Frequency
0 500kHz 1MHz 1.5MHz
0
–10
–20
–30
–40
250
200
150
100
50
V
OUT
/ V
IN
dBm
SIGNAL RESPONSE TO
INPUTS GREATER THAN 250kHz
Frequency Out
100kHz
V
OUT
/V
IN
Freq
Out
(NOTE: Shaded area shows aliasing frequencies that cannot
be removed by a low-pass filter at the output.)
6
®
ISO122
THEORY OF OPERATION
The ISO122 isolation amplifier uses an input and an output
section galvanically isolated by matched 1pF isolating ca-
pacitors built into the plastic package. The input is duty-
cycle modulated and transmitted digitally across the barrier.
The output section receives the modulated signal, converts it
back to an analog voltage and removes the ripple component
inherent in the demodulation. Input and output sections are
fabricated, then laser trimmed for exceptional circuitry match-
ing common to both input and output sections. The sections
are then mounted on opposite ends of the package with the
isolating capacitors mounted between the two sections. The
transistor count of the ISO122 is 250 transistors.
MODULATOR
An input amplifier (A1, Figure 1) integrates the difference
between the input current (VIN/200kΩ) and a switched
±100µA current source. This current source is implemented
by a switchable 200µA source and a fixed 100µA current
sink. To understand the basic operation of the modulator,
assume that VIN = 0.0V. The integrator will ramp in one
direction until the comparator threshold is exceeded. The
comparator and sense amp will force the current source to
switch; the resultant signal is a triangular waveform with a
50% duty cycle. The internal oscillator forces the current
source to switch at 500kHz. The resultant capacitor drive is
a complementary duty-cycle modulation square wave.
DEMODULATOR
The sense amplifier detects the signal transitions across the
capacitive barrier and drives a switched current source into
integrator A2. The output stage balances the duty-cycle
modulated current against the feedback current through the
200kΩ feedback resistor, resulting in an average value at the
VOUT pin equal to VIN. The sample and hold amplifiers in the
output feedback loop serve to remove undesired ripple
voltages inherent in the demodulation process.
BASIC OPERATION
SIGNAL AND SUPPLY CONNECTIONS
Each power supply pin should be bypassed with 1µF tanta-
lum capacitors located as close to the amplifier as possible.
The internal frequency of the modulator/demodulator is set
at 500kHz by an internal oscillator. Therefore, if it is desired
to minimize any feedthrough noise (beat frequencies) from
a DC/DC converter, use a π filter on the supplies (see Figure
4). ISO122 output has a 500kHz ripple of 20mV, which can
be removed with a simple two pole low-pass filter with a
100kHz cutoff using a low cost op amp. See Figure 4.
The input to the modulator is a current (set by the 200kΩ
integrator input resistor) that makes it possible to have an
input voltage greater than the input supplies, as long as the
output supply is at least ±15V. It is therefore possible when
using an unregulated DC/DC converter to minimize PSR
related output errors with ±5V voltage regulators on the
isolated side and still get the full ±10V input and output
swing. An example of this application is shown in Figure
10.
CARRIER FREQUENCY CONSIDERATIONS
The ISO122 amplifier transmits the signal across the isola-
tion barrier by a 500kHz duty cycle modulation technique.
For input signals having frequencies below 250kHz, this
system works like any linear amplifier. But for frequencies
above 250kHz, the behavior is similar to that of a sampling
amplifier. The signal response to inputs greater than 250kHz
1pF
200µA
100µA
200kΩ
Isolation Barrier
1pF
1pF
200µA
100µA
200kΩ
VIN
+
–
Osc
Gnd 1 –VS1
+VS1
VOUT
S/H
G = 6
S/H
G = 1
Gnd 2
+VS2 –VS2
–
+
A2
Sense
Sense
FIGURE 1. Block Diagram.
A1
150pF 150pF
1pF
||
7
®
ISO122
performance curve shows this behavior graphically; at input
frequencies above 250kHz the device generates an output
signal component of reduced magnitude at a frequency
below 250kHz. This is the aliasing effect of sampling at
frequencies less than 2 times the signal frequency (the
Nyquist frequency). Note that at the carrier frequency and its
harmonics, both the frequency and amplitude of the aliasing
go to zero.
ISOLATION MODE VOLTAGE INDUCED ERRORS
IMV can induce errors at the output as indicated by the plots
of IMV vs Frequency. It should be noted that if the IMV
frequency exceeds 250kHz, the output also will display
spurious outputs (aliasing), in a manner similar to that for
VIN > 250kHz and the amplifier response will be identical to
that shown in the Signal Response to Inputs Greater Than
250kHz performance curve. This occurs because IMV-
induced errors behave like input-referred error signals. To
predict the total error, divide the isolation voltage by the
IMR shown in the IMR vs Frequency curve and compute the
amplifier response to this input-referred error signal from
the data given in the Signal Response to Inputs Greater than
250kHz performance curve. For example, if a 800kHz
1000Vrms IMR is present, then a total of [(–60dB) +
(–30dB)] x (1000V) = 32mV error signal at 200kHz plus a
1V, 800kHz error signal will be present at the output.
HIGH IMV dV/dt ERRORS
As the IMV frequency increases and the dV/dt exceeds
1000V/µs, the sense amp may start to false trigger, and the
output will display spurious errors. The common mode
current being sent across the barrier by the high slew rate is
the cause of the false triggering of the sense amplifier.
Lowering the power supply voltages below ±15V may
decrease the dV/dt to 500V/µs for typical performance.
Isolation Barrier
VIN
1µF
+VS2
–
VS1
+VS1
1µF1µF
Gnd
–VS2
1µF
VOUT
Gnd
±VS1 ±VS2
FIGURE 2. Basic Signal and Power Connections.
HIGH VOLTAGE TESTING
Burr-Brown Corporation has adopted a partial discharge test
criterion that conforms to the German VDE0884 Optocou-
pler Standards. This method requires the measurement of
minute current pulses (<5pC) while applying 2400Vrms,
60Hz high voltage stress across every ISO122 isolation
barrier. No partial discharge may be initiated to pass this
test. This criterion confirms transient overvoltage (1.6 x
1500Vrms) protection without damage to the ISO122. Lifetest
results verify the absence of failure under continuous rated
voltage and maximum temperature.
This new test method represents the “state of the art” for
non-destructive high voltage reliability testing. It is based on
the effects of non-uniform fields that exist in heterogeneous
dielectric material during barrier degradation. In the case of
void non-uniformities, electric field stress begins to ionize
the void region before bridging the entire high voltage
barrier. The transient conduction of charge during and after
the ionization can be detected externally as a burst of 0.01-
0.1µs current pulses that repeat on each AC voltage cycle.
The minimum AC barrier voltage that initiates partial dis-
charge is defined as the “inception voltage.” Decreasing the
barrier voltage to a lower level is required before partial
discharge ceases and is defined as the “extinction voltage.”
We have characterized and developed the package insulation
processes to yield an inception voltage in excess of 2400Vrms
so that transient overvoltages below this level will not
damage the ISO122. The extinction voltage is above
1500Vrms so that even overvoltage induced partial dis-
charge will cease once the barrier voltage is reduced to the
1500Vrms (rated) level. Older high voltage test methods
relied on applying a large enough overvoltage (above rating)
to break down marginal parts, but not so high as to damage
good ones. Our new partial discharge testing gives us more
confidence in barrier reliability than breakdown/no break-
down criteria.
ISO122P
ISO150 A1
A0
–15V
+15V +15V –15V
12
910 7
8
VOUT
2
1
15 15
16
PGA
102
7
6
8
VIN
345
FIGURE 3. Programmable-Gain Isolation Channel with
Gains of 1, 10, and 100.
8
®
ISO122
FIGURE 4. Optional π Filter to Minimize Power Supply Feedthrough Noise; Output Filter to Remove 500kHz Carrier Ripple.
For more information concerning output filter refer to AB-023.
Isolation Barrier
–VS1
10µH
10µH10µH10µH
1µF
1µF1µF1µF
1µF
1µF1µF1µF
±V
S1
VIN ISO122
+VS1
+VS2
–VS2
Gnd
13kΩ
13kΩ
100pF
+
–6VOUT = –VIN
Gnd
4700pF
385Ω
Charge/Discharge
Control
10kΩ
10kΩ
25kΩ
25kΩ
7
–V+V
25kΩ
25kΩ+
–INA105
1
3V = e50
2
5
6
V = e1
2
Control
Section
Multiplexer
+V
ISO122P
10kΩ
10kΩ15
9
7
8
–V
+V
ISO122P
9
7
8
–V
4
e49=12V
e50=12V
e1 = 12V
e2 = 12V
FIGURE 5. Battery Monitor for a 600V Battery Power System. (Derives Input Power from the Battery.)
10
±VS2
This Section Repeated 49 Times.
10
1
2
16
15
16 2
1
OPA602
2
3
2
9
®
ISO122
10.0V
Thermocouple REF
102
27kΩ
R1
R4
+In
–In
–15V
2
14
13
1
RG
12
10
3
5
4
11
R5
R3
R2
Isothermal
Block with
1N4148 (1)
Ground Loop Through Conduit
100
Zero Adj
R6
50Ω100Ω
+15V
+15V –15V +15V –15V
12
9
8
16
15 10 7VOUT
ISO122P
FIGURE 6. Thermocouple Amplifier with Ground Loop Elimination, Cold Junction Compensation, and Up-scale Burn-out.
SEEBACK
ISA COEFFICIENT R2R4
TYPE MATERIAL (µV/°C) (R3 = 100Ω)(R
5
+ R6 = 100Ω)
Chromel
E Constantan 58.5 3.48kΩ56.2kΩ
Iron
J Constantan 50.2 4.12kΩ64.9kΩ
Chromel
K Alumel 39.4 5.23kΩ80.6kΩ
Copper
T Constantan 38.0 5.49kΩ84.5kΩ
NOTE: (1) –2.1mV/°C at 2.00µA.
1MΩ
INA101
2
6 4
+15V
0.01µF
6
5
RTD
(PT100)
1mA
1mA
2mA
R2 = 2.5kΩ
–V
0V-5V
+V
Gnd
–VS = –15V
on PWS740
4-20mA
ISO122P
3
214 9
8
2
11
8
7
4
3
VOUT
10
7
12
4
10
XTR101
+VS =15V
on PWS740
R1 = 100Ω10
11
5, 13
15
16
15
16
1
FIGURE 7. Isolated 4-20mA Instrument Loop. (RTD shown.)
RS
RCV420
10
®
ISO122
FIGURE 8. Isolated Power Line Monitor.
MPY100
X
Y
(V2)PL= V2(RD1 + RD2)
RS RD2
XY
10
(V1)
10kΩ
2
3
6
0.01µF
ISO122P
–V
(V3)VL= V3(RD1 + RD2)
RD2
+V
ISO122P
2kΩIL= V1
10RS
0.1µF
2kΩ
+V
97
15
16
8
Load IL
RD2
RD1
VL
RS
0.3µF
0.3µF
PWS740-3
63
14
213
465
PWS740-2
To PWS740-1
0.3µF
0.3µF
97
8
15
16
41
PWS740-3
36
PWS740-2
To PWS740-1
132
456
2
1
1
2
10
10
–V
OPA602
–
+
11
®
ISO122
FIGURE 9. Three-Port, Low-Cost, Four-Channel Isolated, Data Acquisition System.
+V
Channel 2
(Same as Channel 1.)
PWS740-1
465
3
3
44
0.3µF
ISO122P
0.3µF
0.3µF
64
11
66
16
15 7
0.3µF
Channel 1
1
Channel 4
(Same as Channel 1.)
Channel 3
(Same as Channel 1.)
98
2
VIN VOUT
123123
20µHPWS740-2 PWS740-2
5
0.3µF
10µF
6
3
4
8
5
10
PWS740-3 PWS740-3
12
®
ISO122
+15V
9
7
8
10
VIN , up to
± 10V Swing
2
16
1–15
0.1µF
0.1µF
0.33µF 0.33µF
4
PWS740–3
VOUT
To PWS740–2,–1
NOTE: The input supplies can be subregulated to ±5V to reduce
PSR related errors without reducing the ±10V input range.
1
2
3
1
2
3
MC78L05
+5V
Regulator –5V
Regulator
MC79L05
VSINPUT RANGE
(V) (V)(1)
20+ –2 to +10
15 –2 to +5
12 –2 to +2
FIGURE 10. Improved PSR Using External Regulator.
FIGURE 11. Single Supply Operation of the ISO122P Isolation Amplifier. For additional information see AB-009.
NOTE: Since the amplifier is unity gain, the input
range is also the output range. The output can go to
–2V since the output section of the ISO amp operates
from dual supplies.
ISO
122P
R
1
R
2
R
4
INA105
Difference Amp
R
3
R
S
2
3
4
IN4689
5.1V
Reference
5
7
6
1
V
IN
Signal Source
+
NOTE: (1) Select to match R .
S
10kΩ
15 1
9
V (+15V)
S1
+V (+15V)
S2
–V (–15V)
S2
16 2
–V
S1
Com 2
V = V
OUT IN
7
8
10
In
Gnd
ISO
122
R
C(1)
ISO
122P
ISO
122P
13
®
ISO122
1516
1 2
10 9
ISO122P
INPUT
SECTION OUTPUT
SECTION
7 8
Gnd V
IN
V– V+
V+ V– V
O
Gnd
HPR117
65421
Output
Gnd
V
O
V
IN
+15V
–15V
Auxiliary
Isolated
Power
Output
–15V, 20mA
+15V, 20mA
Input
Gnd
–15V, 20mA
+15V, 20mA
1516
1 2
10 9
ISO122P
INPUT
SECTION OUTPUT
SECTION
7 8
Gnd V
IN
V– V+
V+ V– V
O
Gnd
HPR117
456 12
V
IN
Input
Gnd
+15V, 20mA
–15V, 20mA
Auxiliary
Isolated
Power
Output
HPR117
6541
V
O
Output
Gnd
Auxiliary
Isolated
Power
Output
Gnd+15V
2
FIGURE 13. Powered ISO Amp with Three-Port Isolation. For additional information refer to AB-024.
FIGURE 12. Input-Side Powered ISO Amp. For additional information refer to AB-024.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ISO122JP ACTIVE PDIP NVF 8 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
ISO122JPE4 ACTIVE PDIP NVF 8 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
ISO122JU ACTIVE SOIC DVA 8 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO122JU/1K ACTIVE SOIC DVA 8 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO122JU/1KE4 ACTIVE SOIC DVA 8 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO122JUE4 ACTIVE SOIC DVA 8 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO122P ACTIVE PDIP NVF 8 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
ISO122PE4 ACTIVE PDIP NVF 8 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
ISO122U ACTIVE SOIC DVA 8 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO122U/1K ACTIVE SOIC DVA 8 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO122U/1KE4 ACTIVE SOIC DVA 8 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ISO122UE4 ACTIVE SOIC DVA 8 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jul-2011
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ISO122JU/1K SOIC DVA 8 1000 330.0 24.4 10.9 18.3 3.2 12.0 24.0 Q1
ISO122U/1K SOIC DVA 8 1000 330.0 24.4 10.9 18.3 3.2 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO122JU/1K SOIC DVA 8 1000 367.0 367.0 45.0
ISO122U/1K SOIC DVA 8 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDI072 – AUGUST 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NVF (R-PDIP-T8/16) PLASTIC DUAL-IN-LINE
4202501/A 08/01
0.150 (3,81)
0.115 (2,92)
C
0.005 (0,13)
MIN 4 PL
18
916
0.775 (21,34)
0.735 (18,67)
0.240 (6,10)
0.280 (7,11)
0.070 (1,78)
0.045 (1,14)0.030 (0,76)
0.045 (1,14)
0.014 (0,36)
0.022 (0,56)
0.010 (0,25) MC
0.210 (5,33)
0.195 (4,95)
0.115 (2,92)
0.300 (7,63)
MAX
0.430 (10,92)
0.000 (0,00)
0.060 (1,52)
0.014 (0,36)
0.008 (0,20)
0.325 (8,26)
0.300 (7,62)
Index
Area
0.015 (0,38)
MIN
0.100 (2,54)
Seating Plane
Base Plane
MAX
F
F
D
D
D
E
1/2 Lead
A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001-BB with the exception of lead
count.
D. Dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 (0,25).
E. Dimensions measured with the leads constrained to be
perpendicular to Datum C.
F. Dimensions are measured at the lead tips with the leads
unconstrained.
G. A visual index feature must be located within the
cross-hatched area.
MECHANICAL DATA
MPDS105 – AUGUST 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DVA (R-PDSO-G8/28) PLASTIC SMALL-OUTLINE
4202103/B 08/01
Index
Area
114
1528
Seating
Plane
17,70
18,10
7,60
7,40 10,01
10,65
2,35
2,65
0,30
0,10
0,51
0,33 0,32
0,23
0,25
0,75 x 45°
1,27
0,40
0°–8°
C
F
G
1,27
0,25 M BAC S
0,10
0,25 MB
C
B
A
D
M
M
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body length dimension does not include mold
flash, protrusions, or gate burrs. Mold flash, protrusions,
and gate burrs shall not exceed 0,15 mm per side.
D. Body width dimension does not include inter-lead flash
or portrusions. Inter-lead flash and protrusions
shall not exceed 0,25 mm per side.
E. The chamfer on the body is optional. If it is not present,
a visual index feature must be located within the
cross-hatched area.
F. Lead dimension is the length of terminal for soldering
to a substrate.
G. Lead width, as measured 0,36 mm or greater
above the seating plane, shall not exceed a
maximum value of 0,61 mm.
H. Lead-to-lead coplanarity shall be less than
0,10 mm from seating plane.
I. Falls within JEDEC MS-013-AE with the exception
of the number of leads.
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