May 2002
2002 Fairc hild Semiconduct or Cor por ation NDC7001C Rev B ( W)
NDC7001C
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N & P-Channel Enhancement Mode Field
Effect Transistors are produced using Fairchild’s
proprietary, hi gh cell densit y, DMOS technology. This
very high density process has been designed to
minimize on-state resistance, provide rugged and
reliable performance and fast switching. These
device is particularly suited for low voltage, low
current, switching, and power supply appli cations.
Features
• Q1 0.51 A, 60V . RDS(ON) = 2 Ω @ VGS = 10 V
R
DS(ON) = 4 Ω @ VGS = 4. 5 V
• Q2 –0.34 A, 60V . RDS(ON) = 5 Ω @ VGS = –10 V
R
DS(ON) = 7. 5Ω @ V GS = –4.5 V
• High saturation current
• High densit y cell design for low RDS(ON)
• Proprietary S uperSOTTM –6 package: design using copper
lead frame f or superior thermal and electrical capabilities
D1
S2
G1
D2
S1
G2
SuperSOT -6
TM
3
2
1
4
5
6Q1(N)
Q2(P)
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol Parameter Q1 Q2 Units
VDSS Drain-Source V ol tage 60 –60 V
VGSS Gate-Source Voltage ±20 ±20
ID Drain Current – Continuous (Note 1a) 0.51 –0.34 A
– Pulsed 1.5 –1
Power Dissipation for Single Operation (Note 1a) 0.96
(Note 1b) 0.9
PD
(Note 1c) 0.7 W
TJ, TSTG Operating and St orage Junction Temperature Range –55 to +150 °C
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 130 °C/W
RθJC Thermal Resistanc e, Juncti on-to-Case (Note 1) 60
Package Marking and Ordering Information
Device Marki ng Device Reel Siz e Tape width Quantity
.01C NDC7001C 7’’ 8mm 3000
NDC7001C
NDC7001C Rev B ( W)
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS
Drain–Source B reakdown Voltage
VGS = 0 V, ID = 250 µA
VGS = 0 V, ID = –250 µAQ1
Q2 60
–60 V
∆BVDSS
∆TJ Breakdown Voltage Temperature
Coefficient ID = 250 µA,Ref. to 25°C
ID = –250 µA,Ref. to 25°C Q1
Q2 67
–57 mV/°C
IDSS
Zero Gate Volt age Drai n Current
VDS = 48 V, VGS = 0 V
VDS = –48 V, VGS = 0 V Q1
Q2
1
–1 µA
IGSSF Gate–Body Leakage, Forward VGS = 20 V, VDS = 0 V All 100 nA
IGSSR Gate–Body Leakage, Reverse VGS = –20 V, VDS = 0 V All –100 nA
On Characteristics (Note 2)
VGS(th) Q1 VDS = VGS, ID = 250 µA 1 2.1 2.5
Gate Threshold V ol t age
Q2 VDS = VGS, ID = –250 µA –1 –1.9 –3.5
V
∆VGS(th) Q1 ID = 250 µA,Ref erenced. to 25°C –3.8
∆TJ Gate Threshold Vol tage
Temperature Coefficient Q2 ID = –250 µA,Ref. to 25°C 3.2
mV/°C
RDS(on) Q1 VGS = 10 V, ID = 0.51 A
VGS = 4.5 V, ID = 0.35 A
VGS = 10 V, ID = 0.51 A,TJ=125°C
1
2
1.7
2
4
3.5
Stati c Drain–Source
On–Resistance
Q2 VGS = –10 V, ID = –0.34 A
VGS = – 4.5 V,ID = –0. 25 A
VGS = –10V,ID= –0.34A,TJ=125°C
1.2
1.5
1.9
5
7.5
10
Ω
ID(on) Q1 VGS = 10 V VDS = 10 V 1.5
On-State Drai n Current
Q2 VGS = –10 V VDS = –10 V –1 A
gFS Q1 VDS = 10 V ID = 0.51 A 380
Forward Transconductanc e
Q2 VDS = –10 V ID = –0.34A 700 mS
Dynamic Characteristics
Ciss Q1 20
Input Capac i t ance Q2 66 pF
Coss Q1 11
Output Capaci tance Q2 13 pF
Crss Q1 4.3
Reverse Transfer Capacitance Q2
For Q1:
VDS = 25 V, VGS = 0 V
f = 1.0MHz
For Q2:
VDS = –25 V, VGS = 0 V
f = 1.0MHz 6 pF
RG Gate Resistance Q1 11.2 Ω
Q2 VGS = 15 mV, f = 1.0 MHz 11.2
Switching Characteristics (Note 2)
td(on) Q1 2.8 5.6
Turn–On Delay Time Q2 3.2 6.4 ns
tr Q1 8 16
Turn–On Rise Time Q2 10 20 ns
td(off) Q1 14 26
Turn–Off Delay Time Q2 8 16
ns
tf Q1 4 8
Turn–Off Fall Time Q2
For Q1:
VDS =25 V, I DS = 1 A
VGS= 10 V, RGEN = 6 Ω
For Q2:
VDS =–25 V, I DS= –1 A
VGS= –10 V, RGEN = 6 Ω
1 2 ns
Qg Q1 1.1 1.5
Total Gate Charge Q2 1.6 2.2
nC
Qgs Q1 0.2
Gate–Source Charge Q2 0.3 nC
Qgd Q1 0.4
Gate–Drain Charge Q2
For Q1:
VDS =25 V, I DS = 0. 51 A
VGS= 10 V, RGEN = 6 Ω
For Q2:
VDS =–25 V, I DS= –0.35 A
VGS= –10 V, RGEN = 6 Ω 0.3 nC
NDC7001C
NDC7001C Rev B ( W)
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Drain–Source Diode Characteristics and Maximum Ratings
IS Maxim um Continuous Drain–Source Diode Forward Current Q1 0.51
A
Q2 –0.34
VSD Q1 VGS = 0 V, IS = 0.51 A (Note 2) 0.8 1.2
Drain–Source Di ode Forward
Voltage Q2 VGS = 0 V, IS = –0.34 A (Note 2) –0.8 –1.4 V
trr Q1 IF = 0.51 A, diF/dt = 100 A/µs 18
Diode Reverse Rec overy
Time Q2 IF = –0.34 A, diF/dt = 100 A/µs 16 nS
Qrr Q1 IF = 0.51 A, diF/dt = 100 A/µs 16
Diode Reverse Rec overy
Charge Q2 IF = –0.34 A, diF/dt = 100 A/µs 11 nC
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 130 °C/W when
mounted on a 0.125
in2 pad of 2 oz.
copper.
b) 140°C/W when mounted
on a .005 in2 pad of 2 oz
copper
c) 180°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
NDC7001C
NDC7001C Rev B ( W)
Typical Characteristics: N-Channel
0
0.3
0.6
0.9
1.2
1.5
02468
VDS, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
6.0V
VGS = 10V
4.5V
4.0V
5.0V
8.0V
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
0 0.3 0.6 0.9 1.2 1.5
ID, DRAIN CURRENT (A)
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESIS T ANCE
VGS = 4.5V
10V
8.0V
5.0V
7.0V
6.0V
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
ID = 0.51A
VGS = 10V
0
1
2
3
4
5
6
246810
VGS, GATE TO SOURCE VOLTAGE (V)
R
DS(ON)
, ON-RESISTANCE (OHM)
ID = 0.26A
TA = 125oC
TA = 25oC
Figure 3. On-Resistance Variation
withTemperature. Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
0.3
0.6
0.9
1.2
1.5
13579
VGS, GATE TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
T
A
=-55oC25oC125oC
VDS = 5V
0.0001
0.001
0.01
0.1
1
10
0.2 0.4 0.6 0.8 1 1.2
VSD, BODY DIODE FORW ARD VOLTAGE (V )
I
S
, REVERSE DRAIN CURRENT (A)
TA = 125oC
25oC
-55oC
VGS = 0V
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
NDC7001C
NDC7001C Rev B ( W)
Typical Characteristics: N-Channel (continued)
0
2
4
6
8
10
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Qg, GATE CHARGE (nC)
V
GS
, GATE-SOURCE VOLTAGE (V)
ID = 0.51A VDS = 25V
48V
30V
0
10
20
30
40
50
60
0 102030405060
VDS, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
CISS
CRSS
COSS
f = 1MHz
VGS = 0 V
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
0.1 1 10 100
VDS, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A
)
DC 1s
100ms
RDS(ON) LIMIT
VGS = 10V
SINGLE PULSE
RθJA = 180oC/W
TA = 25oC
10ms
1ms
10µs
100µs
0
2
4
6
8
10
0.001 0.01 0.1 1 10 100
t1, TIM E (sec)
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
RθJA = 180°C/W
TA = 25°C
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
r(t), NORM ALIZED EFFECTIVE TRANSIEN
T
THERMAL RESISTANCE
RθJA(t) = r(t) * RθJA
RθJA = 180 °C/W
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
P(pk)
t1t2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 21. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
NDC7001C
NDC7001C Rev B ( W)
Typical Characteristics: P-Channel
0
0.2
0.4
0.6
0.8
1
012345
-VDS, DRAIN TO SOURCE VOLTAGE (V)
-I
D
, DRAIN CURRENT (A)
VGS = -10V
-3.0V
-4.5V
-3.5V
-4.0V -6.0V
0.8
1
1.2
1.4
1.6
1.8
2
2.2
00.20.40.60.81
-ID, DRAIN CURRENT (A)
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
VGS= -3.0V
-3.5V
-10V
-4.0V -4.5V -6.0V
Figure 11. On-Region Characteristics. Figure 12. On-Resistance Variation with
Drain Current and Gate Voltage.
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
ID = -0.34A
VGS = -10V
0
1
2
3
4
5
246810
-VGS, GATE TO SOURCE VOLTAGE (V)
R
DS(ON)
, ON-RES I STANCE (OHM)
ID = -0.17A
TA = 125oC
TA = 25oC
Figure 13. On-Resistance Variation
withTemperature. Figure 14. On-Resistance Variation with
Gate-to-Source Voltage.
0
0.2
0.4
0.6
0.8
1
12345
-VGS, GATE TO SOURCE VOLTAGE (V)
-I
D
, DRAIN CURRENT (A
)
TA = -55oC25oC
125oC
VDS = -5V
0.0001
0.001
0.01
0.1
1
10
0.2 0.4 0.6 0.8 1 1.2
-VSD, BODY DIODE FORWARD VOLTAGE (V)
-I
S
, REVERSE DRAIN CURRENT (A)
VGS = 0V
TA = 125oC
25oC
-55oC
Figure 15. Transfer Characteristics. Figure 16. Body Diode Forward Voltage Variation
with Source Current and Temperature.
NDC7001C
NDC7001C Rev B ( W)
Typical Characteristics: P-Channel (continued)
0
2
4
6
8
10
00.40.81.21.62
Qg, GATE CHARGE (nC)
-V
GS
, GATE-SOURCE VOLTAGE (V)
ID = -0.34A VDS = -25V -30V
-48V
0
20
40
60
80
100
0 102030405060
-VDS, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
CISS
COSS
CRSS
f = 1 MHz
VGS = 0 V
Figure 17. Gate Charge Characteristics. Figure 18. Capacitance Characteristics.
0.01
0.1
1
10
110100
-VDS, DRAIN-SOU RCE VOLTAGE (V)
-I
D
, DRAIN CURRENT (A)
DC 1s 100ms
RDS(ON) LIMIT
VGS = -10V
SINGLE PULSE
RθJA = 180oC/W
TA = 25oC
10ms1ms
10µs
0
2
4
6
8
10
0.001 0.01 0.1 1 10 100
t1, TIME (se c )
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
RθJA = 180°C/W
TA = 25°C
Figure 19. Maximum Safe Operating Area. Figure 20. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
r(t), NORM ALIZED EFFECTIVE TRANSIEN
T
THERMAL RESISTANCE
RθJA(t) = r(t) * RθJA
RθJA = 180 °C/W
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
P(pk)
t1t2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 21. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
NDC7001C
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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