Philips Semiconductors Objective Specification
PowerMOS transistor PHX1N50E
Isolated version fo PHP1N50E
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
field-effect power transistor in a full
pack, plastic envelope featuring high VDS Drain-source voltage 500 V
avalanche energy capability, stable IDDrain current (DC) 1.4 A
blocking voltage, fast switching and Ptot Total power dissipation 25 W
high thermal cycling performance RDS(ON) Drain-source on-state resistance 5 Ω
withlowthermalresistance.Intended
for use in Switched Mode Power
Supplies (SMPS), motor control
circuits and general purpose
switching applications.
PINNING - SOT186A PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
case isolated
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Drain-source voltage - 500 V
VDGR Drain-gate voltage RGS = 20 kΩ- 500 V
±VGS Gate-source voltage - 30 V
IDDrain current (DC) Ths = 25 ˚C - 1.4 A
Ths = 100 ˚C - 0.9 A
IDM Drain current (pulse peak Ths = 25 ˚C - 5.6 A
value)
IDR Source-drain diode current Ths = 25 ˚C - 1.4 A
(DC)
IDRM Source-drain diode current Ths = 25 ˚C - 5.6 A
(pulse peak value)
Ptot Total power dissipation Ths = 25 ˚C - 25 W
Tstg Storage temperature -55 150 ˚C
TjJunction temperature - 150 ˚C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
WDSS Drain-source non-repetitive ID = 2 A ; VDD ≤ 50 V ; VGS = 10 V ;
unclamped inductive turn-off RGS = 50 Ω
energy Tj = 25˚C prior to surge - 120 mJ
Tj = 100˚C prior to surge - 20 mJ
WDSR1Drain-source repetitive ID = 2 A ; VDD ≤ 50 V ; VGS = 10 V ; - 3.6 mJ
unclamped inductive turn-off RGS = 50 Ω ; Tj ≤ 150 ˚C
energy
1. Pulse width and frequency limited by Tj(max)
123
case
d
g
s
November 1996 1 Rev 1.000
Philips Semiconductors Objective specification
PowerMOS transistor PHX1N50E
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Visol R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal - 2500 V
three terminals to external waveform;
heatsink R.H. ≤ 65% ; clean and dustfree
Cisol Capacitance from T2 to external f = 1 MHz - 10 - pF
heatsink
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Rth j-hs Thermal resistance junction to with heatsink compound - - 5 K/W
heatsink
Rth j-a Thermal resistance junction to - 55 - K/W
ambient
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA 500 - - V
voltage
VGS(TO) Gate threshold voltage VDS = VGS; ID = 0.25 mA 2.0 3.0 4.0 V
IDSS Drain-source leakage current VDS = 500 V; VGS = 0 V; Tj = 25 ˚C - 10 100 µA
VDS = 400 V; VGS = 0 V; Tj = 125 ˚C - 0.1 1.0 mA
IGSS Gate-source leakage current VGS = ±30 V; VDS = 0 V - 10 100 nA
RDS(ON) Drain-source on-state VGS = 10 V; ID = 1 A - 4.5 5.0 Ω
resistance
VSD Source-drain diode forward IF = 2 A ;VGS = 0 V - 0.8 1.2 V
voltage
November 1996 2 Rev 1.000
Philips Semiconductors Objective specification
PowerMOS transistor PHX1N50E
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
gfs Forward transconductance VDS = 15 V; ID = 1 A 0.5 0.9 - S
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 230 300 pF
Coss Output capacitance - 35 50 pF
Crss Feedback capacitance - 14 30 pF
Qg(tot) Total gate charge VGS = 10 V; ID = 2 A; VDS = 400 V - 10 - nC
Qgs Gate to source charge - 1 - nC
Qgd Gate to drain (Miller) charge - 5 - nC
td on Turn-on delay time VDD = 30 V; ID = 2 A; - 10 15 ns
trTurn-on rise time VGS = 10 V; RGS = 50 Ω; - 30 45 ns
td off Turn-off delay time RGEN = 50 Ω- 3040ns
t
fTurn-off fall time - 20 30 ns
trr Source-drain diode reverse IF = 2 A; -dIF/dt = 100 A/µs; - 350 - ns
recovery time
Qrr Source-drain diode reverse VGS = 0 V; VR = 100 V - 2.5 - µC
recovery charge
LdInternal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
LsInternal source inductance Measured from source lead 6 mm - 7.5 - nH
from package to source bond pad
November 1996 3 Rev 1.000
Philips Semiconductors Objective specification
PowerMOS transistor PHX1N50E
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Fig.1. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
10.3
max
3.2
3.0
4.6
max
2.9 max
2.8
seating
plane
6.4
15.8
max
0.6
2.5
2.54
5.08
123
3 max.
not tinned
3
0.5
2.5
0.9
0.7
M
0.4
15.8
max. 19
max.
13.5
min.
Recesses (2x)
2.5
0.8 max. depth
1.0 (2x)
1.3
November 1996 4 Rev 1.000
Philips Semiconductors Objective specification
PowerMOS transistor PHX1N50E
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
November 1996 5 Rev 1.000
