DESCRIPTION
The 3850 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 3850 group is designed for the household products and office
automation equipment and includes serial I/O functions, 8-bit
timer, and A-D conver ter.
FEATURES
●Basic machine-language instr uctions ...................................... 71
●Minimum instruction execution time .................................. 0.5 µs
(at 8 MHz oscillation frequency)
●Memory siz e
ROM ................................................................... 8K to 24K bytes
RAM.....................................................................512 to 640 byte
●Programmable input/output ports ............................................ 34
●Interrupts ................................................. 14 sources, 14 vectors
●Timers ............................................................................. 8-bit ✕ 4
●Serial I/O....................... 8-bit ✕ 1(UART or Clock-synchronized)
●PWM ............................................................................... 8-bit ✕ 1
●A-D converter ............................................... 10-bit ✕ 5 channels
●Watchdog timer ............................................................ 16-bit ✕ 1
●Clock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PIN CONFIGURATION (TOP VIEW)
Fig. 1 M38503M4-XXXFP/SP pin configuration
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In high-speed mode .................................................. 2.7 to 5.5 V
(at 4 MHz oscillation frequency)
In middle-speed mode............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
In low-speed mode.................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
●Power dissipation
In high-speed mode ..........................................................34 mW
(at 8 MHz oscillation frequency, at 5 V po wer source voltage)
In low-speed mode............................................................ 6 0 µW
(at 32 kHz oscillation frequency, at 3 V pow er source voltage)
●Operating temperature range....................................–20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products ,
Consumer electronics, etc.
P4
0
/CNTR
1
P4
1
/INT
0
P4
2
/INT
1
P4
3
/INT
2
AV
SS
P4
4
/INT
3
/PWM
V
REF
V
CC
P3
1
/AN
1
P3
2
/AN
2
P0
0
P0
4
P0
5
P0
6
P0
7
P1
1
P1
2
P1
3
/(LED
0
)
P1
4
/(LED
1
)
P1
5
/(LED
2
)
P1
0
P0
1
P0
2
P3
0
/AN
0
P3
3
/AN
3
P3
4
/AN
4
P0
3
40
41
42
22
23
24
25
26
27
28
29
30
31
32
34
35
36
37
38
39
33
3
2
1
21
20
19
18
17
16
15
14
13
12
11
9
8
7
6
5
4
10
M38503M4-XXXFP
M38503M4-XXXSP
P1
6
/(LED
3
)
P1
7
/(LED
4
)
P2
7
/CNTR
0
/S
RDY
P2
6
/S
CLK
P2
5
/TxD
P2
4
/RxD
P2
3
P2
2
CNV
SS
P2
1
/X
CIN
P2
0
/X
COUT
RESET
X
IN
X
OUT
V
SS
Package type : FP ........................... 42P2R-A (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin shrink plastic-molded DIP)
2
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
FUNCTIONAL BLOCK DIAGRAM
Fig. 2 Functional block diagram
FUNCTIONAL BLOCK
INT
0
–
CNTR
0
CNTR
1
V
REF
AV
SS
R A M R O M
C P U
A
X
Y
S
PC
H
PC
L
PS
V
SS
21
RESET
18
V
CC
1 15
CNV
SS
23
X
IN
19 20
SI/O(8)
Reset input
Clock generating circuit
Main-clock
input Main-clock
output
A-D
converter
(10)
Timer Y( 8 )
Timer X( 8 )
Prescaler 12(8)
Prescaler X(8)
Prescaler Y(8)
Timer 1( 8 )
Timer 2( 8 )
Sub-clock
input
X
OUT
X
CIN
X
COUT
Sub-clock
output
Watchdog
timer Reset
P2(8)
P3(5)
I/O port P2
I/O port P3
P4(5)
I/O port P4
INT
3
468
5739 4138 40 42 911 13 17
10 12 1416
P1(8)
I/O port P1
22 24 26 2823 25 27 29
P0(8)
I/O port P0
30 31 32 33 34 35 36 37
PWM
(8)
X
CIN
X
COUT
3
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
VCC, VSS
PIN DESCRIPTION
Functions
NamePin
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reset input pin for active “L.”
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•P13 to P17 (5 bits) are enabled to output large current for LED drive.
•8-bit CMOS I/O port.
Power source
Table 1 Pin description
Function except a port function
• Sub-clock generating circuit I/O
pins (connect a resonator)
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
CNVSS inputCNVSS
RESET Reset input
XIN
XOUT
P00–P07
P10–P17
P20/XCOUT
P21/XCIN
P22
P23
P24/RxD
P25/TxD
P26/SCLK
P27/CNTR0/
SRDY
P30/AN0–
P34/AN4I/O port P3
I/O port P4
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•P20, P21, P24 to P27: CMOS3-state output structure.
•P22, P23: N-channel open-drain structure. • Serial I/O function pin
• Serial I/O function pin/
Timer X function pin
• A-D converter input pin
• Timer Y function pin
• Interrupt input pins
• Interrupt input pin
• PWM output pin
P40/CNTR1
P41/INT0–
P43/INT2
P44/INT3/PWM
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
4
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PART NUMBERING
Fig. 3 Part numbering
M3850 3 M 4 XXX FP
Product
ROM/PROM size
1
2
3
4
5
6
7
8
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M
E : Mask ROM version
: EPROM or One Time PROM version
RAM size
0
1
2
3
4
5
6
7
8
9
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
ROM number
Omitted in some types.
Package type
FP
SP
SS
: 42P2R-A package
: 42P4B package
: 42S1B-A package
9
A
B
C
D
E
F
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
5
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
GROUP EXPANSION
Mitsubishi plans to expand the 3850 group as follows:
Memory T ype
Support for mask ROM, One Time PROM, and EPROM versions.
Memory Size
ROM/PROM size................................................... 8K to 24K bytes
RAM size .............................................................. 512 to 640 bytes
Packages
42P4B..........................................42-pin shrink plastic molded DIP
42P2R-A ............................................ 42-pin plastic molded SSOP
42S1B-A ................... 42-pin shrink ceramic DIP(EPROM version)
Fig. 4 Memory expansion plan
Currently planning products are listed below.
RAM size (bytes) Remarks
Package
Table 2 Suppor t products
Product name
As of August 1998
8192
(8062)
(P) ROM size (bytes)
ROM size for User in ( )
Memory Expansion Plan
Products under development or planning : the development schedule and specification may be revised without notice.
Planning products may be stopped the development.
M38503M2-XXXSP
M38503M2-XXXFP
M38503M4-XXXSP
M38503E4-XXXSP
M38503E4SP
M38503E4SS
M38503M4-XXXFP
M38503E4-XXXFP
M38503E4FP
M38504M6-XXXSP
M38504E6-XXXSP
M38504E6SP
M38504E6SS
M38504M6-XXXFP
M38504E6-XXXFP
M38504E6FP
512 42P2R-A
42P4B
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version (stock only replaced by M38504E6SS)
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Mask ROM version
16384
(16254)
42P2R-A
48K
ROM size (bytes)
32K
28K
24K
20K
16K
12K
8K
128 192 256
RAM size (bytes)
384 512 640 768 896 1024
M38503M4/E4
Under development
M38504M6/E6
Mass production
M38503M2
Mass production
42P4B
512 42S1B-A
42P4B One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Mask ROM version
32768
(32638)
42P2R-A
640 42S1B-A
6
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3850 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
Fig. 5 Structure of CPU mode register
CPU mode register
(
CPUM : address
003B
16
)
b7 b0
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (return “1” when read)
(Do not write “0” to this bit.)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Port X
C
switch bit
0 : I/O port function (stop oscillating)
1 : X
CIN
–X
COUT
oscillating function
Main clock (X
IN
–X
OUT
) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(X
IN
)/2 (high-speed mode)
0 1 : φ = f(X
IN
)/8 (middle-speed mode)
1 0 : φ = f(X
CIN
)/2 (low-speed mode)
1 1 : Not available
7
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts .
ROM
The first 128 bytes and the last 2 bytes of ROM are reser ved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
Fig. 6 Memory map diagram
0100
16
0000
16
0040
16
FF00
16
FFDC
16
FFFE
16
FFFF
16
192
256
384
512
640
768
896
1024
1536
2048
3072
4032
XXXX
16
00FF
16
013F
16
01BF
16
023F
16
02BF
16
033F
16
03BF
16
043F
16
063F
16
083F
16
0C3F
16
0FFF
16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F000
16
E000
16
D000
16
C000
16
B000
16
A000
16
9000
16
8000
16
7000
16
6000
16
5000
16
4000
16
3000
16
2000
16
1000
16
F080
16
E080
16
D080
16
C080
16
B080
16
A080
16
9080
16
8080
16
7080
16
6080
16
5080
16
4080
16
3080
16
2080
16
1080
16
YYYY
16
ZZZZ
16
RAM
ROM
0440
16
SFR area
Not used
Interrupt vector area
ROM area Reserved ROM area
(128 bytes)
Zero page
Special page
RAM area
RAM size
(bytes) Address
XXXX
16
ROM size
(bytes) Address
YYYY
16
Reserved ROM area
Address
ZZZZ
16
Reserved area
8
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 7 Memory map of special function register (SFR)
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Transmit/Receive buffer register (TB/RB)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt control register 2 (ICON2)
A-D conversion low-order register (ADL)
Prescaler Y (PREY)
Timer Y (TY)
A-D control register (ADCON)
A-D conversion high-order register (ADH)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Prescaler 12 (PRE12)
Timer 2 (T2)
Prescaler X (PREX)
Timer X (TX)
Timer 1 (T1)
Timer XY mode register (TM)
Reserved ✽
MISRG
Watchdog timer control register (WDTCON)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Timer count source selection register (TCSS)
Reserved ✽
Reserved ✽
Reserved ✽
✽ Reserved : Do not write “1” to this address.
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
Reserved ✽
9
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Pin Name Input/Output I/O Structure Non-Port Function Ref.No.
Table 3 I/O port function Related SFRs
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Port P0
Port P1
Port P3
Input/output,
individual
bits
CMOS compatible
input level
CMOS 3-state output Sub-clock generating
circuit CPU mode register
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
P00–P07
P10–P17
P20/XCOUT
P21/XCIN
P22
P23
P24/RxD
P25/TxD
Port P2
P26/SCLK
P27/CNTR0/SRDY
P30/AN0–
P34/AN4
P40/CNTR1
P41/INT0–
P43/INT2
P44/INT3/PWM
Port P4
CMOS compatible
input level
N-channel open-drain
output
Serial I/O function I/O
Serial I/O function I/O
Serial I/O function I/O
Timer X function I/O
A-D conversion input
Serial I/O control
register
Serial I/O control
register
Serial I/O control
register
Timer XY mode register
A-D control register
Timer Y function I/O
External interrupt input
External interrupt input
PWM output
Timer XY mode register
Interrupt edge selection
register
Interrupt edge selection
register
PWM control register
CMOS compatible
input level
CMOS 3-state output
10
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 8 Port block diagram (1)
(1) Port P0, P1
Direction
register
Data bus Port latch
(2) Port P2
0
Port X
C
switch bit
Oscillator
Port P2
1
Data bus Port latch
Direction
register
Port X
C
switch bit
(3) Port P2
1
Port X
C
switch bit
Data bus Port latch
Direction
register
Sub-clock generating circuit input
(4) Port P2
2,
P2
3
Data bus Port latch
Direction
register
(5) Port P2
4
Data bus Port latch
Direction
register
Serial I/O enable bit
Receive enable bit
Serial I/O input
(6) Port P2
5
Data bus Port latch
Direction
register
Serial I/O enable bit
Transmit enable bit
Serial I/O output
(7) Port P2
6
Data bus Port latch
Direction
register
Serial I/O enable bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O clock
selection bit
(8) Port P2
7
P-channel output disable bit
Serial clock output
External clock input
Data bus Port latch
Direction
register
Timer output
Serial I/O enable bit
S
RDY
output enable bit
Serial I/O mode selection bit
CNTR
0
interrupt
input
Serial ready output
Pulse output mode
Pulse output mode
11
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 9 Port block diagram (2)
(9) Port P3
0
–P3
4
Direction
register
Data bus Port latch
A-D converter input
Analog input pin selection bit
(11) Port P4
1
–P4
3
Direction
register
Data bus Port latch
Interrupt input
(10) Port P4
0
CNTR
1
interrupt input
Data bus Port latch
Direction
register
Pulse output mode
Timer output
(12) Port P4
4
PWM output
Data bus Port latch
Direction
register
PWM output enable bit
12
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
INTERRUPTS
Interrupts occur by 14 sources among 14 sources: six external,
seven internal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interr upt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interr upt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interr upt disable) flag disables all interrupts except the BRK in-
struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the progr am counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interr upt jump destination address is read from the vector
table into the prog ram counter.
■Notes
When the active edge of an external interrupt (INT0–INT3, CNTR0,
CNTR1) is set, the corresponding interrupt request bit may also be
set. Therefore, take the follo wing sequence:
1. Disable the interrupt
2. Change the interrupt edge selection register
(the timer XY mode register for CNTR0 and CNTR1)
3. Clear the interrupt request bit to “0”
4. Accept the interr upt.
13
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Interrupt Request
Generating Conditions Remarks
Interr upt Source Low
FFFC16
High
FFFD16
Priority
1
Table 4 Interrupt vector addresses and priority
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Vector Addresses (Note 1)
Reset (Note 2)
INT0
Reserved
INT1
INT2
INT3
Reserved
Timer X
Timer Y
Timer 1
Timer 2
Serial I/O
reception
Serial I/O
Transmission
CNTR0
CNTR1
A-D converter
BRK instruction
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
Reserved
At completion of serial I/O data
reception
At completion of serial I/O trans-
fer shift or when transmission
buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
Non-maskable
External interrupt
(active edge selectable)
Valid when serial I/O is selected
Valid when serial I/O is selected
External interrupt
(active edge selectable)
STP release timer underflow
External interrupt
(active edge selectable)
Reserved
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of A-D conversion
At BRK instruction execution
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDC16
FFDD16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 Non-maskable software interrupt
14
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 10 Interrupt control
Fig. 11 Structure of interrupt-related registers (1)
b7 b0
b7 b0
b7 b0
b7 b0
b7 b0
Interrupt edge selection register
INT
0
active edge selection bit
INT
1
active edge selection bit
INT
2
active edge selection bit
INT
3
active edge selection bit
Reserved(Do not write “1” to this bit)
Not used (returns “0” when read)
(INTEDGE : address 003A
16
)
Interrupt request register 1
INT
0
interrupt request bit
Reserved
INT
1
interrupt request bit
INT
2
interrupt request bit
INT
3
interrupt request bit
Reserved
Timer X interrupt request bit
Timer Y interrupt request bit
Interrupt control register 1
INT
0
interrupt enable bit
Reserved(Do not write "1" to this bit)
INT
1
interrupt enable bit
INT
2
interrupt enable bit
INT
3
interrupt enable bit
Reserved(Do not write "1" to this bit)
Timer X interrupt enable bit
Timer Y interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C
16
)
(ICON1 : address 003E
16
)
Interrupt request register 2
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O reception interrupt request bit
Serial I/O transmit interrupt request bit
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
(IREQ2 : address 003D
16
)
Interrupt control register 2
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O reception interrupt enable bit
Serial I/O transmit interrupt enable bit
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F
16
)
0 : Falling edge active
1 : Rising edge active
0 : No interrupt request issued
1 : Interrupt request issued
0 : Interrupts disabled
1 : Interrupts enabled
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
15
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
TIMERS
The 3850 group has four timers: timer X, timer Y, timer 1, and
timer 2.
The division ratio of each timer or prescaler is given b y 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an un-
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The out-
put of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source
selection bit.
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach “0016”, the
signal output from the CNTR0 (or CNTR1) pin is inverted. If the
CNTR0 (or CNTR 1) active edge selection bit is “0”, output begins
at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P27 ( or port P40) direction register to out-
put mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode, ex-
cept that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR 1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts the selected signals by the count source selection bit while
the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) ac-
tive edge selection bit is “1”, the timer counts it while the CNTR0
(or CNTR1) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.
Fig. 12 Structure of timer XY mode register
■Note
When switching the count source by the timer 12, X and Y count
source bit, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
Fig. 13 Structure of timer count source selection register
Timer count source selection register
(TCSS : address 0028
16
)
b7 b0
Timer X count source selection bit
0 : f(X
IN
)/16 (f(X
CIN
)/16 at low-speed mode)
1 : f(X
IN
)/2 (f(X
CIN
)/2 at low-speed mode)
Timer Y count source selection bit
0 : f(X
IN
)/16 (f(X
CIN
)/16 at low-speed mode)
1 : f(X
IN
)/2 (f(X
CIN
)/2 at low-speed mode)
Timer 12 count source selection bit
0 : f(X
IN
)/16 (f(X
CIN
)/16 at low-speed mode)
1 : f(X
CIN
)
Not used (returns “0” when read)
Timer X count stop bit
0: Count start
1: Count stop
Timer XY mode register
(TM : address 002316)
Timer Y operating mode bit
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
b7
CNTR0 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
b0
Timer X operating mode bit
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
b1b0
b5b4
Timer Y count stop bit
0: Count start
1: Count stop
16
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 14 Block diagram of timer X, timer Y, timer 1, and timer 2
Q
Q
“1”
“0”
P27/CNTR0
Q
Q
P40/CNTR1
“0”
“1”
R
R
“1”
“0”
“0”
“1”
T
T
Prescaler X latch (8)
Prescaler X (8)
Timer X latch (8)
Timer X (8) To timer X interrupt
request bit
Toggle flip-flop
Timer X count stop bit
Pulse width
measurement
mode
Event
counter
mode To CNTR0 interrupt
request bit
Pulse output mode
Port P27
latch
Port P27
direction register
CNTR0 active
edge selection
bit
Timer X latch write pulse
Pulse output mode
Timer mode
Pulse output mode
Prescaler Y latch (8)
Prescaler Y (8)
Timer Y latch (8)
Timer Y (8) To timer Y interrupt
request bit
Toggle flip-flop
Timer Y count stop bit
To CNTR1 interrupt
request bit
Pulse output mode
Port P40
latch
Port P40
direction register
CNTR1 active
edge selection
bit
Timer Y latch write pulse
Pulse output mode
Timer mode
Pulse output mode
Data bus
Data bus
Prescaler 12 latch (8)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 1 (8)
Data bus
Timer 2 latch (8)
Timer 2 (8) To timer 2 interrupt
request bit
To timer 1 interrupt
request bit
CNTR0 active
edge selection
bit
CNTR1 active
edge selection
bit
Pulse width
measure-
ment mode
Event
counter
mode
f(XCIN)
Timer 12 count source selection bit
f(XIN)/16
f(XIN)/2
Timer Y count source selection bit
f(XIN)/16
f(XIN)/2
Timer X count source selection bit
f(XIN)/16
17
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for baud
rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register (bit 6
of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Fig. 15 Block diagram of clock synchronous serial I/O
Fig. 16 Operation of clock synchronous serial I/O function
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
TBE = 0 TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write pulse to receive/transmit
buffer register (address 0018
16
)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has
ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal
S
RDY
1/4
1/4
F/F
P26/SCLK
Serial I/O status register
Serial I/O control register
P27/SRDY
P24/RXD
P25/TXD
XIN
Receive buffer register
Address 001816
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
BRG count source selection bit
Clock control circuit
Falling-edge detector
Transmit buffer register
Data bus Address 001816
Shift clock Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
Data bus
Address 001A16
Transmit shift register
18
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit (b6) of the serial I/O con-
trol register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read from
the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig.17 Block diagram of UART serial I/O
XIN
1/4
OE
PE FE
1/16
1/16
Data bus
Receive buffer register
Address 001816
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+1)
Address 001C16
ST/SP/PA generator
Transmit buffer register
Data bus
Transmit shift register
Address 001816
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address 001916
ST detector
SP detector UART control register
Address 001B16
Character length selection bit
Address 001A16
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O control register
P26/SCLK1
Serial I/O status register
P24/RXD
P25/TXD
19
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 18 Operation of UART serial I/O function
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive b uffer is “0”.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the ser ial I/O
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the ser ial I/O enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O status register are initialized to “0” at re-
set, but if the transmit enable bit (bit 4) of the serial I/O control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register consists of eight control bits for the
serial I/O function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is al-
ways valid and sets the output structure of the P25/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
STD
0
D
1
SP D
0
D
1
ST SP
TBE=1 TSC=1
STD
0
D
1
SP D
0
D
1
ST SP
Transmit or receive clock
Transmit buffer write
signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
Serial output T
X
D
Serial input R
X
D
Receive buffer read
signal
20
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 19 Structure of serial I/O control registers
b7
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
Serial I/O status register
Serial I/O control register
b0 b0
BRG count source selection bit (CSS)
0: f(X
IN
)
1: f(X
IN
)/4
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
S
RDY
output enable bit (SRDY)
0: P2
7
pin operates as ordinary I/O pin
1: P2
7
pin operates as S
RDY
output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P2
4
to P2
7
operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P2
4
to P2
7
operate as serial I/O pins)
b7
UART control register
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P2
5
/T
X
D P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
b0
(SIOSTS : address 0019
16
) (SIOCON : address 001A
16
)
(UARTCON : address 001B
16
)
21
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PULSE WIDTH MODULATION (PWM)
The 3850 group has a PWM function with an 8-bit resolution,
based on a signal that is the clock input XIN or that clock input di-
vided by 2.
Data Setting
The PWM output pin also functions as port P44. Set the PWM pe-
r iod by the PWM prescaler, and set the “H” term of output pulse by
the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ✕ (n+1) / f(XIN)
= 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz)
Output pulse “H” term = PWM period ✕ m / 255
= 0.125 ✕ (n+1) ✕ m µs
(when f(XIN) = 8 MHz)
Fig. 20 Timing of PWM period
Fig. 21 Block diagram of PWM function
31.875 ✕ m ✕ (n+1)
255 µs
T = [31.875 ✕ (n+1)] µs
PWM output
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM period (when f(XIN) = 8 MHz)
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Data bus
Count source
selection bit
“0”
“1”
PWM
prescaler pre-latch PWM
register pre-latch
PWM
prescaler latch PWM
register latch
Transfer control circuit
PWM register
1/2
XIN
Port P44 latch
PWM enable bit
Port P44
PWM prescaler
22
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 22 Structure of PWM control register
Fig. 23 PWM output timing when PWM register or PWM prescaler is changed
PWM control register
(PWMCON : address 001D16)
PWM function enable bit
Count source selection bit
Not used (return “0” when read)
b7 b0
0: PWM disabled
1: PWM enabled
0: f(XIN)
1: f(XIN)/2
ABC
B
T
C
T2
=
PWM output
PWM register
write signal
PWM prescaler
write signal
(Changes “H” term from “A” to “B”.)
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
TTT2
■Note
The PWM starts after the PWM enable bit is set to enable and "L" level is output from the PWM pin.
The length of this "L" level output is as follows:
sec (Count source selection bit = 0, where n is the value set in the prescaler)
sec (Count source selection bit = 1, where n is the value set in the prescaler)
n+1
2 • f(XIN)
n+1
f(XIN)
23
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
003516, 003616
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion
[AD Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Comparison V oltage Generator
The comparison voltage generator divides the voltage between
AVSS and V REF into 1024 and outputs the divided voltages.
Channel Selector
The channel selector selects one of ports P30/AN0 to P34/AN4 and
inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(XIN) to 500 kHz or more during an A-D conversion.
Fig. 24 Structure of AD control register
Fig. 25 Structure of A-D conversion registers
AD control register
(ADCON : address 003416)
Analog input pin selection bits
0 0 0: P30/AN0
0 0 1: P31/AN1
0 1 0: P32/AN2
0 1 1: P33/AN3
1 0 0: P34/AN4
Not used (returns “0” when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
b7 b0
b2 b1 b0
10-bit reading
(Read address 0036
16
before 0035
16
)
(Address 0036
16
)
(Address 0035
16
)
8-bit reading (Read only address 0035
16
)
(Address 0035
16
)
b8
b7 b6 b5 b4 b3 b2 b1 b0
b7 b0
b9
b7 b0
Note : The high-order 6 bits of address 0036
16
become “0”
at reading.
b9 b8 b7 b6 b5 b4 b3 b2
b7 b0
Channel selector
A-D control circuit
A-D conversion low-order register
Resistor ladder
V
REF
AV
SS
Comparator
A-D interrupt request
b7 b0
3
10
P3
0
/AN
0
P3
1
/AN
1
P3
2
/AN
2
P3
3
/AN
3
P3
4
/AN
4
Data bus
AD control register
A-D conversion high-order register
(Address 0034
16
)
(Address 0036
16
)
(Address 0035
16
)
Fig. 26 Block diagram of A-D converter
24
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
WATCHDOG TIMER
The watchdog timer gives a mean of retur ning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 003916) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watch-
dog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003916) may be
started before an underflo w. When the watchdog timer control reg-
ister (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watch-
dog timer H count source selection bit are read.
●Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L is set to “FF16.”
Fig. 28 Structure of Watc hdog timer control register
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) per-
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at f(XIN)
= 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case
is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN)
= 32 kHz frequency. This bit is cleared to “0” after resetting.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instr uction is enabled.
When this bit is “1”, the STP instruction is disabled, once the STP
instruction is executed, an internal reset occurs. When this bit is
set to “1”, it cannot be rewritten to “0” by program. This bit is
cleared to “0” after resetting.
Fig. 27 Block diagram of Watchdog timer
XIN
Data bus
XCIN
“10”
“00”
“01”
Main clock division
ratio selection bits
(Note)
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction disable bit
Watchdog timer H (8)
“FF16” is set when
watchdog timer
control register is
written to.
Internal reset
RESET
Watchdog timer L (8)
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
STP instruction
“FF16” is set when
watchdog timer
control register is
written to.
b0
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Watchdog timer H (for read-out of high-order 6 bit)
Watchdog timer control register
(WDTCON : address 003916)
b7
25
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an "L"
level for 2 µs or more. Then the RESET pin is returned to an "H"
level (the power source voltage must be between 2.7 V and 5.5 V,
and the oscillation must be stable), reset is released. After the re-
set is completed, the program starts from the address contained in
address FFFD16 (high-order byte) and address FFFC16 (low-order
byte). Make sure that the reset input voltage is less than 0.54 V for
VCC of 2.7 V.
Fig. 30 Reset sequence
Fig. 29 Reset circuit example
(Note)
0.2V
CC
0V
0V
Poweron
V
CC
RESET
V
CC
RESET
Power source
voltage detection
circuit
Power source
voltage
Reset input
voltage
Note : Reset release voltage ; Vcc=2.7 V
RESET
Data
φ
Address
SYNC
XIN: 8 to 13 clock cycles
XIN
???? ?FFFC FFFD ADH,L
??? ??ADLADH
1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 2 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
3: All signals except XIN and RESET are internals.
Reset address from the vector table.
Notes
RESETOUT
26
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 31 Internal status at reset
Port P0 direction register (P0D)
Port P1 direction register (P1D)
Port P2 direction register (P2D)
Port P3 direction register (P3D)
Port P4 direction register (P4D)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIOCON)
UART control register (UARTCON)
PWM control register (PWMCON)
Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
Timer count source select register
Reserved
Reserved
Reserved
Reserved
Reserved
AD control register (ADCON)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Processor status register
Program counter
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
Note : X indicates Not fixed .
Address Register contents
000116
000316
000516
000716
000916
001916
001A16
001B16
001D16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002C16
002D16
002E16
002F16
003016
003416
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
(PCH)
(PCL)
0016
0016
0016
0016
0016
0016
0016
FF16
0116
0016
0016
FF16
FF16
FF16
FF16
0016
Not fixed
Not fixed
Not fixed
Not fixed
Not fixed
0016
0016
0016
0016
0016
0016
10000000
11100000
1
010010 0
XXXXXXX
00010000
00111111
0
FFFD16 contents
FFFC16 contents
27
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
CLOCK GENERATING CIRCUIT
The 3850 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator betw een XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external f eed-back resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and X COUT pins function as I/O por ts .
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
set, this mode is selected.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
■Note
If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately af-
ter power on and at returning from the stop mode. When switching
the mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3•f(XCIN).
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1.” When the main clock XIN is
restar ted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
The sub-clock XCIN-XCOUT oscillating circuit can not directly input
clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillation stops. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF 16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
Either XIN or XCIN divided by 16 is input to the prescaler 12 as
count source. Oscillator restarts when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU (remains
at “H”) until timer 1 underflows. The internal clock φ is supplied for
the first time, when timer 1 underflows. This ensures time for the
clock oscillation using the ceramic resonators to be stabilized.
When the oscillator is restarted by reset, apply “L” level to the
RESET pin until the oscillation is stable since a wait time will not
Fig. 32 Ceramic resonator circuit
Fig. 33 External clock input circuit
XCIN XCOUT XIN XOUT
CIN COUT
CCIN CCOUT
Rf Rd
XCIN XCOUT XIN XOUT
CCIN CCOUT
Rf Rd Open
External oscillation
circuit
Vcc
Vss
be generated.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before ex-
ecuting of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruc-
tion.
■Note
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
28
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 35 System clock generating circuit block diagram (Single-chip mode)
MISRG
(MISRG : address 0038
16
)
Oscillation stabilizing time set after STP instruction
released bit
Middle-speed mode automatic switch set bit
Middle-speed mode automatic switch wait time set bit
Middle-speed mode automatic switch start bit
(Depending on program)
Not used (return “0” when read)
b7 b0
0: Automatically set “01
16
” to Timer 1,
“FF
16
” to Prescaler 12
1: Automatically set nothing
0: Not set automatically
1: Automatic switching enable
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
0: Invalid
1: Automatic switch start
Fig. 34 Structure of MISRG
WIT instruction STP instruction
Timing φ (internal clock)
S
R
Q
STP instruction
S
R
Q
Main clock stop bit
S
R
Q
1/2 1/4
X
IN
X
OUT
X
COUT
X
CIN
Interrupt request
Reset
Interrupt disable flag l
1/2
Port X
C
switch bit
“1” “0”
Low-speed mode
High-speed or
middle-speed
mode
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits (Note)
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b1) to “1”.
Main clock division ratio
selection bits (Note)
FF
16
01
16
Prescaler 12 Timer 1
Reset or
STP instruction
Middle-speed mode automatic switch set bit
By setting the middle-speed mode automatic switch set bit to “1”
while operating in the low-speed mode, XIN oscillation automati-
cally starts and the mode is automatically switched to the
middle-speed mode when defecting a rising/falling edge of the
SCL or SDA pin. The middle-speed automatic switch wait time set
bit can select the switch timing from the low-speed to the middle-
speed mode; either 4.5 to 5.5 machine cycles or 6.5 to 7.5
machine cycles in the low-speed mode. Select it according to os-
cillation start char acteristics of used XIN oscillator.
The middle-speed mode automatic switch start bit is used to auto-
matically make to XIN oscillation start and switch to the
middle-speed mode by setting this bit to “1” while operating in the
low-speed mode.
29
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 36 State transitions of system clock
CM4 : Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
0 0 : φ = f(XIN)/2 ( High-speed mode)
0 1 : φ = f(XIN)/8 (Middle-speed mode)
1 0 : φ = f(XCIN)/2 (Low-speed mode)
1 1 : Not available
Notes
Reset
CM4
“1”←→“0”
CM
4
“0”←→“1”
CM
6
“1”←→“0”
CM
4
“1”←→“0”
CM
6
“1”←→“0”
CM7
“1”←→“0” CM4
“1”←→“0”
CM5
“1”←→“0”
CM6
“1”←→“0”
CM6
“1”←→“0”
CPU mode register
b7 b4
CM
7
“0”←→“1”
CM
6
“1”←→“0”
(CPUM : address 003B16)
CM7=0
CM6=1
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
Middle-speed mode
(f(φ)=1 MHz)
CM7=0
CM6=1
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
Middle-speed mode
(f(φ)=1 MHz)
CM7=0
CM6=0
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
High-speed mode
(f(φ)=4 MHz)
CM7=1
CM6=0
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
Low-speed mode
(f(φ)=16 kHz)
CM7=1
CM6=0
CM5=1(8 MHz stopped)
CM4=1(32 kHz oscillating)
Low-speed mode
(f(φ)=16 kHz)
CM7=0
CM6=0
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
High-speed mode
(f(φ)=4 MHz)
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 in middle/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 16 ms occurs by Timer 1 and Timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/high-speed
mode.
7 : The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
30
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After
a reset, initialize flags which affect program execution. In particu-
lar, it is essential to initialize the index X mode (T) and the decimal
mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing
a BBC or BBS instruction.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instr uction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
• The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instr uction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1.”
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
When an external clock is used as synchronous clock in serial I/O,
write transmission data to the transmit buffer register while the
transfer clock is “H.”
A-D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an
A-D conversion.
Do not execute the STP or WIT instruction dur ing an A-D conver-
sion.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instr uction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency in
high-speed mode.
31
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
DATA REQUIRED FOR MASK ORDERS
The follo wing are necessary when order ing a mask ROM produc-
tion:
1.Mask ROM Order Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop-
ies)
DATA REQUIRED FOR ROM WRITING
ORDERS
The following are necessary when ordering a ROM writing:
1.R OM Writing Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop-
ies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
Fig. 37 Programming and testing of One Time PROM version
Table 5 Programming adapter
Package
42P2R-A
42P4B
Name of Programming Adapter
PCA4738F-42A
PCA4738S-42A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 49 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
32
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
VCC
VSS
VREF
AVSS
VIA
VIH
VIH
VIL
VIL
VIL
ELECTRICAL CHARACTERISTICS
Table 6 Absolute maximum ratings
Power source voltage
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS
Output voltage P0 0–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
Output voltage P22, P23
Power dissipation
Operating temperature
Storage temper ature
VCC
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Symbol Parameter Conditions Ratings
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to 5.8
–0.3 to V CC +0.3
–0.3 to 13
–0.3 to V CC +0.3
–0.3 to 5.8
300
–20 to 85
–40 to 125
V
V
V
V
V
V
V
mW
°C
°C
Unit
Ta = 25 °C
All voltages are based on VSS.
Output transistors are cut off.
5.5
5.5
VCC
VCC
VCC
VCC
0.2VCC
0.2VCC
0.16VCC
Power source voltage (At 8 MHz)
Power source voltage (At 4 MHz)
Power source voltage
A-D convert reference voltage
Analog power source voltage
Analog input voltage AN0–AN4
“H” input voltage P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
“H” input voltage RESET, XIN, CNVSS
“L” input voltage P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
“L” input voltage RESET, CNVSS
“L” input voltage XIN
Symbol Parameter Limits
Min.
V
V
V
V
V
V
V
V
V
V
Unit
Table 7 Recommended operating conditions (1)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
4.0
2.7
2.0
AVSS
0.8VCC
0.8VCC
0
0
0
5.0
5.0
0
0
Typ. Max.
–80
–80
80
80
80
–40
–40
40
40
40
“H” total peak output current P00–P07, P10–P17, P30–P34 (Note)
“H” total peak output current P20, P21, P24–P27, P40–P44 (Note)
“L” total peak output current P00–P07, P10–P12, P30–P34 (Note)
“L” total peak output current P13–P17 (Note)
“L” total peak output current P20–P27,P40–P44
(Note)
“H” total average output current P00–P07, P10–P17, P3 0–P34 (Note)
“H” total average output current P20, P21, P24–P27, P40–P44 (Note)
“L” total average output current P00–P07, P10–P12, P30–P34 (Note)
“L” total average output current P13–P17 (Note)
“L” total average output current P20–P27,P40–P44
(Note)
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
33
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Table 8 Recommended operating conditions (2)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
–10
10
20
–5
5
15
8
4
“H” peak output current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44 (Note 1)
“L” peak output current P00–P07, P10–P12, P20–P27, P30–P34, P40–P44
(Note 1)
“L” peak output current P13–P17 (Note 1)
“H” average output current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44 (Note 2)
“L” average output current P00–P07, P10–P12, P20–P27, P30–P34, P40–P44
(Note 2)
“L” peak output current P13–P17 (Note 2)
Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3)
Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
f(XIN)
Symbol Parameter Limits
Min.
mA
mA
mA
mA
mA
mA
MHz
kHz
Unit
Typ. Max.
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
34
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 9 Electrical characteristics
(VCC = 2.7 to 5.5 V, V SS = 0 V , Ta = –20 to 85 °C, unless otherwise noted)
“H” output v oltage
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
(Note)
“L” output voltage
P00–P07, P10–P12, P20–P27
P30–P34, P4 0–P44
“L” output voltage
P13–P17
Hysteresis
CNTR0, CNTR1, INT 0–INT3
Hysteresis
RxD, S
CLK
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
“H” input current RESET, CNV SS
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27
P30–P34, P4 0–P44
“L” input current RESET,CNVSS
“L” input current XIN
RAM hold voltage
Limits
V
V
V
V
V
V
Parameter Min. Typ. Max.
Symbol Unit
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
IOH = –10 mA
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 2.7–5.5 V
IOL = 10 mA
VCC = 4.0–5.5 V
IOL = 1.0 mA
VCC = 2.7–5.5 V
IOL = 20 mA
VCC = 4.0–5.5 V
IOL = 10 mA
VCC = 2.7–5.5 V
VI = V CC
VI = V CC
VI = V CC
VI = V SS
VI = V SS
VI = V SS
When clock stopped
VCC–2.0
VCC–1.0
Test conditions
0.4
0.5
0.5
2.0
1.0
2.0
1.0
VOH
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
VRAM 2.0
5.0
5.0
–5.0
–5.0
5.5
V
V
V
µA
µA
µA
µA
µA
µA
V
–4
4
35
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Table 10 Electrical characteristics
(VCC = 2.7 to 5.5 V, V SS = 0 V , Ta = –20 to 85 °C, unless otherwise noted)
Power source current
Limits
Parameter Min. Typ. Max.
Symbol Unit
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output tr ansistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output tr ansistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
Increment when A-D conversion is
executed
f(XIN) = 8 MHz
Test conditions
13
ICC
Ta = 25 °C
Ta = 85 °C
6.8 mA
All oscillation stopped
(in STP state)
Output transistors “off”
1.6
60
20
20
5.0
4.0
1.5
800
0.1
200
40
55
10.0
7.0
1.0
10
mA
µA
µA
µA
µA
mA
mA
µA
µA
µA
36
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
bit
LSB
tc(φ)
kΩ
µA
µA
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Ladder resistor
Reference power source input current
A-D port input current
Min.
50
Typ.
35
150
0.5
Max.
10
±4
61
200
5.0
VREF = 5.0 V
Table 11 A-D converter c haracteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted)
Unit
Limits
Parameter
–
–
tCONV
RLADDER
IVREF
II(AD)
Test conditionsSymbol
37
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
TIMING REQUIREMENTS
Table 12 Timing requirements (1)
(VCC = 4.0 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1, INT0–INT3 input “H” pulse width
CNTR0, CNTR1, INT0–INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Limits
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
2
125
50
50
200
80
80
800
370
370
220
100
Typ. Max.
Symbol Unit
Note : When f(X IN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Serial I/O input setup time
Serial I/O input hold time
Table 13 Timing requirements (2)
(VCC = 2.7 to 4.0 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1, INT0–INT3 input “H” pulse width
CNTR0, CNTR1, INT0–INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input setup time
Serial I/O input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Limits
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
2
250
100
100
500
230
230
2000
950
950
400
200
Typ. Max.
Symbol Unit
Note : When f(X IN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
38
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Switching characteristics 1
(VCC = 4.0 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tWH (SCLK)
tWL (SCLK)
td (SCLK-TXD)
tv (SCLK-TXD)
tr (SCLK)
tf (SCLK)
tr (CMOS)
tf (CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
tC(SCLK)/2–30
tC(SCLK)/2–30
–30
Typ.
10
10
Max.
140
30
30
30
30
Symbol Unit
Notes 1: For tWH(SCLK), tWL(SCLK), when the P51/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
Table 15 Switching characteristics 2
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
tWH (SCLK)
tWL (SCLK)
td (SCLK-TXD)
tv (SCLK-TXD)
tr (SCLK)
tf (SCLK)
tr (CMOS)
tf (CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
tC(SCLK)/2–50
tC(SCLK)/2–50
–30
Typ.
20
20
Max.
350
50
50
50
50
Symbol Unit
Notes 1: For tWH(SCLK), tWL(SCLK), when the P51/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: The XOUT pin is excluded.
39
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
N-channel open-drain output
Measurement output pin
100pF
1kΩ
Measurement output pin
100pF
CMOS output
Fig. 38 Circuit for measuring output switching characteris-
tics (1) Fig. 39 Circuit for measuring output switching characteris-
tics (2)
40
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 40 Timing diagram
0.2VCC
tWL(INT)
0.8VCC
tWH(INT)
0.2VCC
0.2VCC
0.8VCC
0.8VCC
0.2VCC
tWL(XIN)
0.8VCC
tWH(XIN)
tC(XIN)
XIN
0.2VCC 0.8VCC
tW(RESET)
RESET
tftr
0.2VCC
tWL(CNTR)
0.8VCC
tWH(CNTR)
tC(CNTR)
td(SCLK-TXD) tv(SCLK-TXD)
tC(SCLK)
tWL(SCLK)tWH(SCLK)
th(SCLK-RxD)
tsu(RxD-SCLK)
TXD
RXD
SCLK
INT0 to INT3
CNTR0, CNTR1
41
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
GZZ-SH53-11B<86A0>
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M2-XXXSP/FP
MITSUBISHI ELECTRIC
Mask ROM number
Date:
Section head
signature Supervisor
signature
Company
name
Note : Please fill in all items marked ❈.
Customer❈
Issuance
signature
Date
issued
Submitted by
TEL
()
Date:
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM (hexadecimal notation)
In the address space of the microcomputer, the internal
ROM area is from address 608016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38503M2–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the r ight
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘5’ = 3516
‘0’ = 3016
‘3’ = 3316
‘M’ = 4D16
‘2’ = 3216
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
EPROM type (indicate the type used)
27256
EPR OM address
000016
000F16
001016
607F16
608016
7FFD16
7FFE16
7FFF16
Product name
ASCII code :
‘M38503M2-’
data
ROM (8K-130) bytes
27512
EPROM address
000016
000F16
001016
E07F16
E08016
FFFD16
FFFE16
FFFF16
Product name
ASCII code :
‘M38503M2-’
data
ROM (8K-130) bytes
Microcomputer name: M38503M2-XXXSP M38503M2-XXXFP
MASK ROM CONFIRMATION FORM
42
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
27256
*= $8000
.BYTE ‘M38503M2–’
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M2-XXXSP/FP
MITSUBISHI ELECTRIC
GZZ-SH53-11B<86A0> Mask ROM n umber
We recommend the use of the following pseudo-command to set the star t address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
(2/2)
❈ 2. Mark specification
Mark specification must be submitted using the correct for m for the package being ordered. Fill out the appropriate
mark specification form (42P4B for M38503M2-XXXSP, 42P2R-A for M38503M2-XXXFP) and attach it to the mask
ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
At what frequency? f(XIN) =
(2) Which function will you use the pins P21/XCIN and P20/XCOUT as P2 1 and P20, or XCIN and XCOUT ?
Ceramic resonator
External clock input
Por ts P21 and P20 function
Quartz crystal
Other ( )
XCIN and XCOUT function (external resonator)
MHz
❈ 4. Comments
27512
*= $0000
.BYTE ‘M38503M2–’
43
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
GZZ-SH11-40A<6YA0>
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M4-XXXSP/FP
MITSUBISHI ELECTRIC
Mask ROM number
Date:
Section head
signature Supervisor
signature
Company
name
Note : Please fill in all items mar ked ❈.
Customer❈
Issuance
signature
Date
issued
Submitted by
TEL
()
Date:
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM (hexadecimal notation)
In the address space of the microcomputer, the internal
ROM area is from address C08016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38503M4–”
m ust be entered in addresses 000016 to 0008 16. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the r ight
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘5’ = 3516
‘0’ = 3016
‘3’ = 3316
‘M’ = 4D16
‘4’ = 3416
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
EPROM type (indicate the type used)
27256
EPROM address
000016
000F16
001016
407F16
408016
7FFD16
7FFE16
7FFF16
Product name
ASCII code :
‘M38503M4-’
data
ROM (16K-130) bytes
27512
EPROM address
000016
000F16
001016
C07F16
C08016
FFFD16
FFFE16
FFFF16
Product name
ASCII code :
‘M38503M4-’
data
ROM (16K-130) bytes
Microcomputer name: M38503M4-XXXSP M38503M4-XXXFP
MASK ROM CONFIRMATION FORM
44
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
27256
*= $8000
.BYTE ‘M38503M4–’
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503M4-XXXSP/FP
MITSUBISHI ELECTRIC
GZZ-SH11-40A<6YA0> Mask ROM number
We recommend the use of the following pseudo-command to set the start address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation for m, the ROM
will not be processed.
(2/2)
❈ 2. Mark specification
Mar k specification must be submitted using the correct for m for the package being ordered. Fill out the appropriate
mar k specification form (42P4B for M38503M4-XXXSP, 42P2R-A for M38503M4-XXXFP) and attach it to the mask
ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
At what frequency? f(XIN) =
(2) Which function will you use the pins P2 1/XCIN and P20/XCOUT as P21 and P20, or XCIN and XCOUT ?
Ceramic resonator
External clock input
Por ts P21 and P20 function
Quartz crystal
Other ( )
XCIN and XCOUT function (exter nal resonator)
MHz
❈ 4. Comments
27512
*= $0000
.BYTE ‘M38503M4–’
45
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
GZZ-SH11-41A<6YA0>
Receipt
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503E4-XXXSP/FP
MITSUBISHI ELECTRIC
ROM number
Date:
Section head
signature Supervisor
signature
Company
name
Note : Please fill in all items marked ❈.
Customer❈
Issuance
signature
Date
issued
Submitted by
TEL
()
Date:
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based
on this data. We shall assume the responsibility for errors only if the programming data on the products we produce dif-
fers from this data. Thus , extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM (hexadecimal notation)
In the address space of the microcomputer, the internal
ROM area is from address C08016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M38503E4–”
must be entered in addresses 000016 to 000816. And
set the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right
in hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘5’ = 3516
‘0’ = 3016
‘3’ = 3316
‘E’ = 4516
‘4’ = 3416
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2D 16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
EPROM type (indicate the type used)
27256
EPROM address
000016
000F16
001016
407F16
408016
7FFD16
7FFE16
7FFF16
Product name
ASCII code :
‘M38503E4-’
data
ROM (16K-130) bytes
27512
EPROM address
000016
000F16
001016
C07F16
C080 16
FFFD16
FFFE16
FFFF16
Product name
ASCII code :
‘M38503E4-’
data
ROM (16K-130) bytes
Microcomputer name: M38503E4-XXXSP M38503E4-XXXFP
ROM PROGRAMMING CONFIRMATION FORM
46
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
27256
*= $8000
.BYTE ‘M38503E4–’
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38503E4-XXXSP/FP
MITSUBISHI ELECTRIC
GZZ-SH11-41A<6YA0> ROM number
We recommend the use of the following pseudo-command to set the star t address of the assembler source program be-
cause ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation
form, the ROM will not be processed.
(2/2)
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropr iate
mark specification form; 42P2R-A for the M38503E4-XXXFP, the shrink DIP package Mark Specification Form (only for
built-in One Time PROM microcomputer) for the M38503E4-XXXSP; and attach it to the ROM programming confirma-
tion form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
At what frequency? f(XIN) =
(2) Which function will you use the pins P21/XCIN and P20/XCOUT as P2 1 and P20, or XCIN and XCOUT ?
Ceramic resonator
External clock input
Por ts P21 and P20 function
Quartz crystal
Other ( )
XCIN and XCOUT function (external resonator)
MHz
❈ 4. Comments
27512
*= $0000
.BYTE ‘M38503E4–’
47
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
MARK SPECIFICATION FORM
48
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
49
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Enter the catalog number of the microcomputer for which this mark specification is intended. (If you do not know the ROM code n umber,
enter XXX in its place.)
The catalog number of the microcomputer
A. Standard Mitsubishi Mark
Customer specified part number will be printed together with the ROM code number on the top line.
Enter the desired part number left aligned in the box below. (up to 10 characters)
SHRINK DIP MARK SPECIFICATION FORM
for One Time PROM version microcomputers
M
Mitsubishi lot number
(6-digit or 7-digit)
Mitsubishi catalog name
(blank model number before writing)
RXXX
Note2 :
Note1 : The following characters can be used in the part number :
Uppercase alphabet, numbers, ampersand, hyphen, period, comma, +, /, (, ),
( will be printed at 1.5
x
character width)
2 : XXX is the R OM code n umber.
B. Special Mark Required
If you desire anything other than the standard Mitsubishi mark, it will be treated as a special mark.
Special marks will take longer to produce and should be avoided if possible.
If a special mar k is to be printed, indicate the desired layout of the mark in the figure below. The layout will be duplicated as closely as
possible.
Note1 : If the customer’s trademark logo m ust be used in the Special Mark, please submit a clean original logo.
Note that special marks require extra cost and time to produce.
50
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
SSOP42-P-450-0.80 Weight(g)
–
JEDEC Code 0.63
EIAJ Package Code Lead Material
Alloy 42/Cu Alloy
42P2R-A
Plastic 42pin 450mil SSOP
Symbol Min Nom Max
A
A
2
b
c
D
E
L
L
1
y
Dimension in Millimeters
H
E
A
1
I
2
–
–
.350
.050
.130.317.28–
.6311.30–
–
–
.271
–
–
.02.40.150.517.48.80.9311.50.7651–
.4311–
–
.42
–
.50.20.717.68–
.2312.70–
.150
–
b
2
–.50–
–
0°–10°
e
e
1
42 22
21
1
H
E
E
D
b
ey
F
A
A
2
A
1
L
1
L
c
eb
2
e
1
I
2
Recommended Mount Pad
Detail F
SDIP42-P-600-1.78 Weight(g)
–
JEDEC Code 4.1
EIAJ Package Code Lead Material
Alloy 42/Cu Alloy
42P4B
Plastic 42pin 600mil SDIP
Symbol Min Nom Max
A
A
2
b
b
1
b
2
c
E
D
L
Dimension in Millimeters
A
1
0.51 – –
–3.8–
0.35 0.45 0.55
0.9 1.0 1.3
0.63 0.73 1.03
0.22 0.27 0.34
36.5 36.7 36.9
12.85 13.0 13.15
– 1.778 –
– 15.24 –
3.0 – –
0°–15°
– – 5.5
e
e
1
42 22
21
1
E
c
e
1
A
2
A
1
b
b
1
b
2
e
LA
SEATING PLANE
D
© 1998 MITSUBISHI ELECTRIC CORP.
New publication, effective Aug. 1998.
Specifications subject to change without notice.
Notes regarding these materials
●These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
●Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
●All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
●Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
●The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
●If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
●Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Keep safety first in your circuit designs!
●Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
3850 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WDIP42-C-600-1.78 Weight(g)
JEDEC Code
EIAJ Package Code
42S1B-A
Metal seal 42pin 600mil DIP
–– ––
––
0.46
0.25
––
3.44
15.8 –
–
–
––
–
3.05
–– ––
–
Symbol Min Nom Max
A
A
2
b
b
1
c
D
E
L
Z
Dimension in Millimeters
A
1
3.05 15.24
1.778
41.1
0.33 0.17 0.9 0.8 0.7 0.540.38
1.0 5.0
e
e
1
e
E
D
1
42 22
21
bZ
SEATING PLANE
AL
A
2
A
1
b
1
e
1
c
Rev. Rev.
No. date
1.0 First Edition 980817
REVISION DESCRIPTION LIST 3850 GROUP DATA SHEET
(1/1)
Revision Description
