MT45W8MW16BGX-708WT - Micron Technology

09005aef80ec6f79 pdf/09005aef80ec6f65 zip

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

128Mb BURST

CellularRAMTM 1.5

MT45W8MW16BGX

Features

• Single device supports asynchronous, page, and

burst operations

• Vcc, VccQ Voltages

1.7V–1.95V Vcc

1.7V–1.95V VccQ

• Random Access Time: 70ns

• Burst Mode READ and WRITE Access

4, 8, 16, or 32 words, or continuous burst

Burst wrap or sequential

MAX clock rate: 104 MHz (tCLK = 9.62ns)

Burst initial latency: 39ns (4 clocks) @ 104 MHz

tACLK: 7ns @ 104 MHz

• Page Mode Read Access

Sixteen-word page size

Interpage read access: 70ns

Intrapage read access: 20ns

•Low Power Consumption

Asynchronous READ: < 30mA

Intrapage Read: < 15mA

Initial access, burst READ:

(39ns [4 clocks] @ 104 MHz) < 40mA

Continuous burst READ: < 25mA

Standby: < 50µA (TYP at 25°C)

Deep power-down: < 3µA (TYP)

• Low-Power Features

On-chip Temperature Compensated Refresh (TCR)

Partial Array Refresh (PAR)

Deep Power-Down (DPD) Mode

Figure 1: Ball Assignment 54-Ball VFBGA

Part Number Example:

MT45W8MW16BGX-701LWT

Options Designator

•Configuration: MT45W8MW16B

8 Meg x 16

VCC Core Voltage Supply: 1.8V

VCCQ I/O Voltage Supply: 1.8V

•Package

54-ball VFBGA—”green” GX

• Timing

70ns access -70

85ns access -85

Options (continued) Designator

•Frequency

66 MHz 6

80 MHz 8

104 MHz 1

• Standby Power at 85°C

Standard: 200µA (MAX) None

Low-power: 160µA (MAX) L

•Operating Temperature Range

Wireless (-30°C to +85°C) WT

Industrial (-40°C to +85°C) IT

1 2 3 4 5 6

Top View

(Ball Down)

LB#

DQ8

DQ9

VSSQ

VCCQ

DQ14

DQ15

A18

WAIT

OE#

UB#

DQ10

DQ11

DQ12

DQ13

A19

CLK

A17

A21

A14

A12

ADV#

CE#

DQ1

DQ3

DQ4

DQ5

WE#

A11

RFU

CRE

DQ0

DQ2

VCC

VSS

DQ6

DQ7

A20

RFU

A16

A15

A13

A10

A22

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Part-Numbering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Device Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Burst Wrap (BCR[3]) Default = No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .22

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Latency Counter (BCR[13:11]) Default = Three Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Initial Access Latency (BRC[14]) Default = Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Partial Array Refresh (RCR[2:0] Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Page Mode Operation (RCR[7]) Default = Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Electrical Characteristics and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Data Sheet Designation: Production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Figures

Figure 1: Ball Assignment 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: Functional Block Diagram—8 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 3: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 4: Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 5: READ Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 6: WRITE Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 7: Page Mode READ Operation (ADV# LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 8: Burst Mode READ (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 9: Burst Mode WRITE (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 10: Wired or WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 11: Refresh Collision During Variable-Latency READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 12: Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY Operation . . . . . .16

Figure 13: Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation . . . . . . .16

Figure 14: Register READ, Asynchronous Mode Followed by READ ARRAY Operation . . . . . . . . . . . . . . . . . . . .17

Figure 15: Register READ, Synchronous Mode Followed by READ ARRAY Operation . . . . . . . . . . . . . . . . . . . . .18

Figure 16: Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 17: Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 18: Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 19: WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 20: WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 21: WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 22: Latency Counter (Variable Initial Latency, No Refresh Collision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 23: Latency Counter (Fixed Latency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 24: Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 25: Typical Refresh Current vs. Temperature (ITCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 26: AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 27: AC Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 28: Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 29: DPD Entry and Exit Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 30: Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 31: Asynchronous READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 32: Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 33: Single-Access Burst READ Operation—Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 34: 4-Word Burst READ Operation—Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 35: Single-Access Burst READ Operation—Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 36: 4-Word Burst READ Operation—Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 37: READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 38: Continuous Burst READ Showing an Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 39: CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 40: LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 41: WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 42: Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 43: Burst WRITE Operation—Variable Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 44: Burst WRITE Operation—Fixed Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 45: Continuous Burst WRITE Showing an Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 46: Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 47: Burst READ Interrupted by Burst READ or WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 48: Burst WRITE Interrupted by Burst WRITE or READ—Variable Latency Mode . . . . . . . . . . . . . . . . . .55

Figure 49: Burst WRITE Interrupted by Burst WRITE or READ—Fixed Latency Mode . . . . . . . . . . . . . . . . . . . . .56

Figure 50: Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 51: Asynchronous WRITE (ADV# LOW) Followed By Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 52: Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 53: Burst READ Followed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 54: Asynchronous WRITE Followed by Asynchronous READ—ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 55: Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 56: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Tables

Table 1: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 2: Bus Operations—Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 3: Bus Operations—Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Table 4: Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 5: Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 6: Variable Latency Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 7: Fixed Latency Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 8: 128Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 9: Device Identification Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 10: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 11: Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 12: Partial Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 13: Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 14: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 15: Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 16: Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 17: Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 18: Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 19: Initialization and DPD Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 20: Asynchronous READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 21: Asynchronous READ Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 22: Asynchronous READ Timing Parameters—Page Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 23: Burst READ Timing Parameters—Single Access, Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 24: Burst READ Timing Parameters—4-Word Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 25: Burst READ Timing Parameters—Single Access, Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 26: Burst READ Timing Parameters—4-Word Burst, Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 27: Burst READ Timing Parameters—Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 28: Burst READ Timing Parameters—BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 29: Asynchronous WRITE Timing Parameters—CE#-Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 30: Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 31: Asynchronous WRITE Timing Parameters—WE#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 32: Asynchronous WRITE Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 33: Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 34: Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 35: Burst WRITE Timing Parameters—BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 36: WRITE Timing Parameters—Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 37: READ Timing Parameters—Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 38: READ Timing Parameters—Burst WRITE Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 39: WRITE Timing Parameters—Burst WRITE Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 40: WRITE Timing Parameters—Burst READ Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 41: READ Timing Parameters—Burst READ Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 42: WRITE Timing Parameters—Burst READ Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 43: READ Timing Parameters—Burst READ Interrupted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 44: WRITE Timing Parameters—Async WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 45: READ Timing Parameters—Async WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 46: Asynchronous WRITE Timing Parameters—ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 47: Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 48: Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 49: Asynchronous WRITE Timing Parameters—WE# Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 50: Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 51: Asynchronous WRITE Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

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Table 52: WRITE Timing Parameters—ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 53: READ Timing Parameters—ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 54: WRITE Timing Parameters—Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 55: READ Timing Parameters—Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . . .62

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

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General Description

Micron CellularRAM™ products are high-speed,

CMOS pseudo-static random access memories devel-

oped for low-power, portable applications. The

MT45W8MW16BGX device has a 128Mb DRAM core,

organized as 8 Meg x 16 bits. These devices include

an industry-standard burst mode Flash interface that

dramatically increases read/write bandwidth com-

pared with other low-power SRAM or Pseudo SRAM

offerings.

To operate seamlessly on a burst Flash bus, Cellu-

larRAM products incorporate a transparent self refresh

mechanism. The hidden refresh requires no additional

support from the system memory controller and has

no significant impact on device read/write perfor-

mance.

Two user-accessible control registers define device

operation. The bus configuration register (BCR)

defines how the CellularRAM device interacts with the

system memory bus and is nearly identical to its coun-

terpart on burst mode Flash devices. The refresh con-

figuration register (RCR) is used to control how refresh

is performed on the DRAM array. These registers are

automatically loaded with default settings during

power-up and can be updated anytime during normal

operation.

Special attention has been focused on standby cur-

rent consumption during self refresh. CellularRAM

products include three mechanisms to minimize

standby current. Partial array refresh (PAR) enables

the system to limit refresh to only that part of the

DRAM array that contains essential data. Temperature

compensated refresh (TCR) uses an on-chip sensor to

adjust the refresh rate to match the device tempera-

ture—the refresh rate decreases at lower temperatures

to minimize current consumption during standby.

Deep power-down (DPD) enables the system to halt

the refresh operation altogether when no vital infor-

mation is stored in the device. The system config-

urable refresh mechanisms are accessed through the

RCR.

This CellularRAM device is compliant with the

industry-standard CellularRAM 1.5 feature set estab-

lished by the CellularRAM Workgroup. It includes sup-

port for both variable and fixed latency, with three

output-device drive-strength settings, additional wrap

options, and a device ID register (DIDR).

Figure 2: Functional Block Diagram—8 Meg x 16

NOTE:

Functional block diagrams illustrate simplified device operation. See ball descriptions (Table 1 on page 7); bus operations

tables (Tables 2 and 3 on page 8); and timing diagrams for detailed information.

A[22:0]

Input/

Output

MUX

and

Buffers

Control

Logic

8,192K x 16

DRAM

MEMORY

ARRAY

CE#

WE#

OE#

CLK

ADV#

CRE

WAIT

LB#

UB#

DQ[7:0]

DQ[15:8]

Address Decode

Logic

Refresh Configuration

Device ID Register

(DIDR)

Bus Configuration

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

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NOTE:

The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will

be asserted but should be ignored during asynchronous and page mode operations.

Table 1: VFBGA Ball Descriptions

VFBGA

ASSIGNMENT SYMBOL TYPE DESCRIPTION

A3, A4, A5, B3,

B4, C3, C4, D4,

H2, H3, H4, H5,

G3, G4, F3, F4,

E4, D3, H1, G2,

H6, E3, J4

A[22:0] Input Address Inputs: Inputs for addresses during READ and WRITE operations.

Addresses are internally latched during READ and WRITE cycles. The address lines

are also used to define the value to be loaded into the BCR or the RCR.

J2 CLK Input Clock: Synchronizes the memory to the system operating frequency during

synchronous operations. When configured for synchronous operation, the address

is latched on the first rising CLK edge when ADV# is active. CLK is static LOW

during asynchronous access READ and WRITE operations and during PAGE READ

ACCESS operations.

J3 ADV# Input Address Valid: Indicates that a valid address is present on the address inputs.

Addresses can be latched on the rising edge of ADV# during asynchronous READ

and WRITE operations. ADV# can be held LOW during asynchronous READ and

WRITE operations.

A6 CRE Input Control Register Enable: When CRE is HIGH, WRITE operations load the RCR or

BCR, and READ operations access the RCR, BCR, or DIDR.

B5 CE# Input Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is

disabled and goes into standby or deep power-down mode.

A2 OE# Input Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the

output buffers are disabled.

G5 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle

is a WRITE to either a configuration register or to the memory array.

A1 LB# Input Lower Byte Enable. DQ[7:0]

B2 UB# Input Upper Byte Enable. DQ[15:8]

B6, C5, C6, D5,

E5, F5, F6, G6,

B1, C1, C2, D2,

E2, F2, F1, G1

DQ[15:0] Input/

Output

Data Inputs/Outputs.

J1 WAIT Output Wait: Provides data-valid feedback during burst READ and WRITE operations. The

signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and

READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary.

WAIT is also used to mask the delay associated with opening a new internal page.

WAIT is asserted and should be ignored during asynchronous and page mode

operations. WAIT is High-Z when CE# is HIGH.

J5, J6 RFU — Reserved for future use.

D6 VCC Supply Device Power Supply: (1.70V–1.95V) Power supply for device core operation.

E1 VCCQ Supply I/O Power Supply: (1.70V–1.95V) Power supply for input/output buffers.

E6 VSS Supply VSS must be connected to ground.

D1 VSSQ Supply VSSQ must be connected to ground.

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

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NOTE:

1. CLK must be LOW during async read and async write modes; and to achieve standby power during standby and DPD

modes. CLK must be static (HIGH or LOW) during burst suspend.

2. The WAIT polarity is configured through the bus configuration register (BCR[10]).

3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are

affected. When only UB# is in the select mode, DQ[15:8] are affected.

4. The device will consume active power in this mode whenever addresses are changed.

5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any

external influence.

6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current.

7. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transi-

tions from HIGH to LOW.

8. Burst mode operation is initialized through the bus configuration register (BCR[15]).

9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word

burst (as indicated by WAIT).

Table 2: Bus Operations—Asynchronous Mode

MODE POWER CLK1ADV# CE# OE# WE# CRE

LB#/

UB# WAIT2DQ[15:0]3NOTES

Read Active L L L L H L L Low-Z Data-Out 4

Write Active L L L X L L L Low-Z Data-In 4

Standby Standby L X H X X L X High-Z High-Z 5, 6

No Operation Idle L X L X X L X Low-Z X 4, 6

Configuration

Active L LLHLHXLow-ZHigh-Z

Configuration

Active L L L L H H L Low-Z Config. Reg.

Out

DPD Deep

Power-Down

LXHXXXXHigh-ZHigh-Z 7

Table 3: Bus Operations—Burst Mode

MODE POWER CLK1ADV# CE# OE# WE# CRE

LB#/

UB# WAIT2DQ[15:0]3NOTES

Async Read Active L L L L H L L Low-Z Data-Out 4

Async Write Active L L L X L L L Low-Z Data-In 4

Standby Standby L X H X X L X High-Z High-Z 5, 6

No Operation Idle LXLXXLXLow-ZX 4, 6

Initial Burst

Read

Active L L X H L L Low-Z Data-Out 4, 8

Initial Burst

Write

Active L L H L L X Low-Z Data-In 4, 8

Burst Continue Active H L X X X L Low-Z Data-In or

Data-Out

4, 8

Burst Suspend Active X X L H X X X Low-Z High-Z 4, 8

Configuration

Active L L H L H X Low-Z High-Z 8, 9

Configuration

Active L L L H H L Low-Z Config. Reg.

Out

8, 9

DPD Deep

Power-Down

L X H X X X X High-Z High-Z 7

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

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Part-Numbering Information

Micron CellularRAM devices are available in several

different configurations and densities (see Figure 3).

Figure 3: Part Number Chart

Valid Part Number Combinations

After building the part number from the part num-

bering chart above, please go to the Micron Part Mark-

ing Decoder Web site at http://www.micron.com/

partsearch to verify that the part number is offered and

valid. If the device required is not on this list, please

contact the factory.

Device Marking

Due to the size of the package, the Micron standard

part number is not printed on the top of the device.

Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated

device marks are cross-referenced to the Micron part

numbers at http://www.micron.com/partsearch. To

view the location of the abbreviated mark on the

device, please refer to customer service note, CSN-11,

“Product Mark/Label,” at http://www.micron.com/

csn.

MT 45 W 8M W 16 B GX -70 8 WT ES

Micron Technology

Product Family

45 = PSRAM/CellularRAM Memory

Operating Core Voltage

W = 1.70V–1.95V

Address Locations

M = Megabits

Operating Voltage

W = 1.70V–1.95V

Bus Configuration

16 = x16

READ/WRITE Operation Mode

B = Asynchronous/Page/Burst

Package Codes

GX = "Green" VFBGA (6 x 9 grid, 0.75mm pitch, 8.0mm x 10.0mm x 1.0mm) 54-ball

Production Status

Blank = Production

ES = Engineering Sample

MS = Mechanical Sample

Operating Temperature

WT = -30˚C to +85˚C

IT = -40˚ to +85˚C

Standby Power Options

Blank = Standard

L = Low Power

Frequency

6 = 66 MHz

8 = 80 MHz

1 = 104 MHz

Access/Cycle Time

70 = 70ns

85 = 85ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

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Functional Description

In general, the MT45W8MW16BGX device is a high-

density alternative to SRAM and Pseudo SRAM prod-

ucts, popular in low-power, portable applications.

MT45W8MW16BGX contains a 134,217,728-bit

DRAM core, organized as 8,388,608 addresses by 16

bits. The device implements the same high-speed bus

interface found on burst mode Flash products.

The CellularRAM bus interface supports both asyn-

chronous and burst mode transfers. Page mode

accesses are also included as a bandwidth-enhancing

extension to the asynchronous read protocol.

Power-Up Initialization

CellularRAM products include an on-chip voltage

sensor used to launch the power-up initialization pro-

cess. Initialization will configure the BCR and the RCR

with their default settings (see Figure 18 on page 20

and Figure 24 on page 26). VCC and VCCQ must be

applied simultaneously. When they reach a stable level

at or above 1.7V, the device will require 150µs to com-

plete its self-initialization process. During the initial-

ization period, CE# should remain HIGH. When

initialization is complete, the device is ready for nor-

mal operation.

Figure 4: Power-Up Initialization

Timing

Bus Operating Modes

The MT45W8MW16BGX CellularRAM product

incorporates a burst mode interface found on Flash

products targeting low-power, wireless applications.

This bus interface supports asynchronous, page mode,

and burst mode read and write transfers. The specific

interface supported is defined by the value loaded into

the BCR. Page mode is controlled by the refresh con-

figuration register (RCR[7]).

Asynchronous Mode

CellularRAM products power up in the asynchro-

nous operating mode. This mode uses the industry-

standard SRAM control bus (CE#, OE#, WE#, LB#/

UB#). READ operations (Figure 5) are initiated by

bringing CE#, OE#, and LB#/UB# LOW while keeping

WE# HIGH. Valid data will be driven out of the I/Os

after the specified access time has elapsed. WRITE

operations (Figure 6) occur when CE#, WE#, and LB#/

UB# are driven LOW. During asynchronous WRITE

operations, the OE# level is a “Don't Care,” and WE#

will override OE#. The data to be written is latched on

the rising edge of CE#, WE#, or LB#/UB# (whichever

occurs first). Asynchronous operations (page mode

disabled) can either use the ADV input to latch the

address, or ADV can be driven LOW during the entire

READ/WRITE operation.

During asynchronous operation, the CLK input must

be held static LOW. WAIT will be driven while the device

is enabled and its state should be ignored. WE# LOW

time must be limited to tCEM.

Figure 5: READ Operation (ADV# LOW)

NOTE:

ADV must remain LOW for page mode operation.

Figure 6: WRITE Operation (ADV# LOW)

Vcc

VccQ Device Initialization

Vcc = 1.7V Device ready for

normal operation

tPU > 150µs

ADDRESS VALID

DATA

CE#

DON’T CARE

DATA VALID

OE#

WE#

LB#/UB#

tRC = READ Cycle Time

ADDRESS

ADDRESS VALID

DATA

CE#

DON’T CARE

DATA VALID

OE#

WE#

LB#/UB#

tWC = WRITE Cycle Time

ADDRESS

< tCEM

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

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Page Mode READ Operation

Page mode is a performance-enhancing extension

to the legacy asynchronous READ operation. In page-

mode-capable products, an initial asynchronous read

access is performed, then adjacent addresses can be

read quickly by simply changing the low-order

address. Addresses A[3:0] are used to determine the

members of the 16-address CellularRAM page. Any

change in addresses A[4] or higher will initiate a new

tAA access time. Figure 7 shows the timing for a page

mode access. Page mode takes advantage of the fact

that adjacent addresses can be read in a shorter period

of time than random addresses. WRITE operations do

not include comparable page mode functionality.

During asynchronous page mode operation, the

CLK input must be held LOW. CE# must be driven

HIGH upon completion of a page mode access. WAIT

will be driven while the device is enabled and its state

should be ignored. Page mode is enabled by setting

RCR[7] to HIGH. ADV must be driven LOW during all

page mode read accesses.

Due to refresh considerations, CE# must not be

LOW longer than tCEM.

Figure 7: Page Mode READ Operation

(ADV# LOW)

Burst Mode Operation

Burst mode operations enable high-speed synchro-

nous READ and WRITE operations. Burst operations

consist of a multi-clock sequence that must be per-

formed in an ordered fashion. After CE# goes LOW, the

address to access is latched on the rising edge of the

next clock that ADV# is LOW. During this first clock ris-

ing edge, WE# indicates whether the operation is going

to be a READ (WE# = HIGH, Figure 8 on page 12) or

WRITE (WE# = LOW, Figure 9 on page 12).

The size of a burst can be specified in the BCR either

as a fixed length or continuous. Fixed-length bursts

consist of four, eight, sixteen, or thirty-two words.

Continuous bursts have the ability to start at a speci-

fied address and burst through the entire memory.

The latency count stored in the BCR defines the

number of clock cycles that elapse before the initial

data value is transferred between the processor and

CellularRAM device. The initial latency for READ oper-

ations can be configured as fixed or variable (WRITE

operations always use fixed latency). Variable latency

allows the CellularRAM to be configured for minimum

latency at high clock frequencies, but the controller

must monitor WAIT to detect any conflict with refresh

cycles.

Fixed latency outputs the first data word after the

worst-case access delay, including allowance for

refresh collisions. The initial latency time and clock

speed determine the latency count setting. The

boundaries of 128-word rows should not be crossed in

fixed latency mode. Fixed latency is used when the

controller cannot monitor WAIT. Fixed latency also

provides improved performance at lower clock fre-

quencies.

The WAIT output asserts as soon as CE# goes LOW,

and de-asserts to indicate when data is to be trans-

ferred into (or out of) the memory. WAIT will again be

asserted if the burst crosses a row boundary (variable

latency only—do not cross row boundaries when using

fixed latency). Once the CellularRAM device has

restored the previous row's data and accessed the next

row, WAIT will be de-asserted and the burst can con-

tinue (see Figure 38 on page 45).

To access other devices on the same bus without the

timing penalty of the initial latency for a new burst,

burst mode can be suspended. Bursts are suspended

by stopping CLK. CLK can be stopped HIGH or LOW. If

another device will use the data bus while the burst is

suspended, OE# should be taken HIGH to disable the

CellularRAM outputs; otherwise, OE# can remain

LOW. Note that the WAIT output will continue to be

active, and as a result no other devices should directly

share the WAIT connection to the controller. To con-

tinue the burst sequence, OE# is taken LOW, then CLK

is restarted after valid data is available on the bus.

The CE# LOW time is limited by refresh consider-

ations. CE# must not stay LOW longer than tCEM. If a

burst suspension will cause CE# to remain LOW for

longer than tCEM, CE# should be taken HIGH and the

burst restarted with a new CE# LOW/ADV# LOW cycle.

DATA

CE#

DON’T CARE

OE#

WE#

LB#/UB#

ADDRESS Add[0] Add[1] Add[2] Add[3]

D[1] D[2] D[3]

tAA tAPA

< tCEM

tAPA tAPA

D[0]

8 MEG x 16

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Figure 8: Burst Mode READ (4-word burst)

NOTE:

Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency; latency code two (three clocks); WAIT active

LOW; WAIT asserted during delay. Diagram above is representative of variable latency with no refresh collision or fixed-latency access.

Figure 9: Burst Mode WRITE (4-word burst)

NOTE:

Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency; latency code two (three clocks); WAIT active

LOW; WAIT asserted during delay.

A[22:0]

D[0]

ADV#

CE#

OE#

D[1] D[2] D[3]

WE#

WAIT

DQ[15:0]

LB#/UB#

Latency Code 2 (3 clocks)

CLK

UNDEFINEDDON’T CARE

READ Burst Identified

(WE# = HIGH)

ADDRESS

VALID

A[22:0]

D[0]

ADV#

CE#

OE#

D[1] D[2] D[3]

WE#

WAIT

DQ[15:0]

LB#/UB#

ADDRESS

VALID

Latency Code 2 (3 clocks)

CLK

DON’T CARE

WRITE Burst Identified

(WE# = LOW)

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Mixed-Mode Operation

The device supports a combination of synchronous

READ and asynchronous READ and WRITE operations

when the BCR is configured for synchronous opera-

tion. The asynchronous READ and WRITE operations

require that the clock (CLK) remain LOW during the

entire sequence. The ADV# signal can be used to latch

the target address, or it can remain LOW during the

entire WRITE operation. CE# can remain LOW when

transitioning between mixed-mode operations with

fixed latency enabled; however, the CE# LOW time

must not exceed tCEM. Mixed-mode operation facili-

tates a seamless interface to legacy burst mode Flash

memory controllers. See Figure 50 on page 57 for the

“Asynchronous WRITE Followed by Burst READ” tim-

ing diagram.

WAIT Operation

The WAIT output on a CellularRAM device is typi-

cally connected to a shared, system-level WAIT signal

(see Figure 10). The shared WAIT signal is used by the

processor to coordinate transactions with multiple

memories on the synchronous bus.

Figure 10: Wired or WAIT

Configuration

Once a READ or WRITE operation has been initi-

ated, WAIT goes active to indicate that the Cellular-

RAM device requires additional time before data can

be transferred. For READ operations, WAIT will remain

active until valid data is output from the device. For

WRITE operations, WAIT will indicate to the memory

controller when data will be accepted into the Cellu-

larRAM device. When WAIT transitions to an inactive

state, the data burst will progress on successive clock

edges.

CE# must remain asserted during WAIT cycles

(WAIT asserted and WAIT configuration BCR[8] = 1).

Bringing CE# HIGH during WAIT cycles may cause

data corruption. (Note that for BCR[8] = 0, the actual

WAIT cycles end one cycle after WAIT de-asserts, and

for row boundary crossings, start one cycle after the

WAIT signal asserts.)

When using variable initial access latency (BCR[14]

= 0), the WAIT output performs an arbitration role for

READ operations launched while an on-chip refresh is

in progress. If a collision occurs, WAIT is asserted for

additional clock cycles until the refresh has completed

(see Figure 11 on page 14). When the refresh operation

has completed, the READ operation will continue nor-

mally.

WAIT is also asserted when a continuous READ or

WRITE burst crosses the boundary between 128-word

rows. The WAIT assertion allows time for the new row

to be accessed, and permits any pending refresh oper-

ations to be performed.

WAIT will be asserted but should be ignored during

asynchronous READ and WRITE, and page READ

operations.

By using fixed initial latency (BCR[14] = 1), this Cel-

lularRAM device can be used in burst mode without

monitoring the WAIT signal. However, WAIT can still

be used to determine when valid data is available at

the start of the burst and at row-boundary crossings. If

WAIT is not monitored, the controller must stop burst

accesses at row boundaries and restart the burst to

access the next row.

LB#/UB# Operation

The LB# enable and UB# enable signals support

byte-wide data transfers. During READ operations, the

enabled byte(s) are driven onto the DQs. The DQs

associated with a disabled byte are put into a High-Z

state during a READ operation. During WRITE opera-

tions, any disabled bytes will not be transferred to the

RAM array and the internal value will remain

unchanged. During an asynchronous WRITE cycle, the

data to be written is latched on the rising edge of CE#,

WE#, LB#, or UB#, whichever occurs first.

When both the LB# and UB# are disabled (HIGH)

during an operation, the device will disable the data

bus from receiving or transmitting data. Although the

device will seem to be deselected, it remains in an

active mode as long as CE# remains LOW.

CellularRAM

External

Pull-Up/

Pull-Down

Resistor

Processor

READY

Other

Device

WAIT

Other

Device

WAIT

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Figure 11: Refresh Collision During Variable-Latency READ Operation

NOTE:

Non-default BCR settings for refresh collision during variable-latency READ operation: Latency code two (three clocks);

WAIT active LOW; WAIT asserted during delay.

A[22:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

CLK VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

D[2]D[1] D[3]

VALID

ADDRESS

Additional WAIT states inserted to allow refresh completion.

LB#/UB#

UNDEFINED DON’T CARE

D[0]

High-Z

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Low-Power Operation

Standby Mode Operation

During standby, the device current consumption is

reduced to the level necessary to perform the DRAM

refresh operation. Standby operation occurs when CE#

is HIGH.

The device will enter a reduced power state upon

completion of a READ or WRITE operation, or when

the address and control inputs remain static for an

extended period of time. This mode will continue until

a change occurs to the address or control inputs.

Temperature Compensated Refresh

Temperature compensated refresh (TCR) allows for

adequate refresh at different temperatures. This Cellular-

RAM device includes an on-chip temperature sensor that

automatically adjusts the refresh rate according to the

operating temperature. The device continually adjusts

the refresh rate to match that temperature.

Partial Array Refresh

Partial array refresh (PAR) restricts refresh opera-

tion to a portion of the total memory array. This fea-

ture enables the device to reduce standby current by

refreshing only that part of the memory array required

by the host system. The refresh options are full array,

one-half array, one-quarter array, one-eighth array, or

none of the array. The mapping of these partitions can

start at either the beginning or the end of the address

map (see Table 8 on page 27). READ and WRITE opera-

tions to address ranges receiving refresh will not be

affected. Data stored in addresses not receiving refresh

will become corrupted. When re-enabling additional

portions of the array, the new portions are available

immediately upon writing to the RCR.

Deep Power-Down Operation

Deep power-down (DPD) operation disables all

refresh-related activity. This mode is used if the system

does not require the storage provided by the Cellular-

RAM device. Any stored data will become corrupted

when DPD is enabled. When refresh activity has been

re-enabled, the CellularRAM device will require 150µs

to perform an initialization procedure before normal

operations can resume. During this 150µs period, the

current consumption will be higher than the specified

standby levels, but considerably lower than the active

current specification.

DPD can be enabled by writing to the RCR using

CRE or the software access sequence; DPD starts when

CE# goes HIGH. DPD is disabled the next time CE#

goes LOW and stays LOW for at least 10µs.

Registers

Two user-accessible configuration registers define

the device operation. The bus configuration register

(BCR) defines how the CellularRAM interacts with the

system memory bus and is nearly identical to its coun-

terpart on burst mode Flash devices. The refresh config-

uration register (RCR) is used to control how refresh is

performed on the DRAM array. These registers are

automatically loaded with default settings during

power-up, and can be updated any time the devices

are operating in a standby state.

A DIDR provides information on the device manu-

facturer, CellularRAM generation, and the specific

device configuration. The DIDR is read-only.

Access Using CRE

The registers can be accessed using either a syn-

chronous or an asynchronous operation when the

control register enable (CRE) input is HIGH (see Fig-

ures 12 through 15 on pages 16 through 18). When CRE

is LOW, a READ or WRITE operation will access the

memory array. The configuration register values are

written via addresses A[22:0]. In an asynchronous

WRITE, the values are latched into the configuration

whichever occurs first; LB# and UB# are “Don’t Care.”

The BCR is accessed when A[19:18] are 10b; the RCR is

accessed when A[19:18] are 00b. The DIDR is read

when A[19:18] are 01b. For reads, address inputs other

than A[19:18] are “Don’t Care,” and register bits 15:0

are output on DQ[15:0]. Immediately after performing

a configuration register READ or WRITE operation,

reading the memory array is highly recommended.

8 MEG x 16

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Figure 12: Configuration Register WRITE, Asynchronous Mode

Followed by READ ARRAY Operation

NOTE: 1. A[19:18] = 00b to load RCR, and 10b to load BCR.

Figure 13: Configuration Register WRITE, Synchronous Mode

Followed by READ ARRAY Operation

NOTE: 1. Non-default BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency

code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. A[19:18] = 00b to load RCR, and 10b to load BCR.

3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by refresh

collisions require a corresponding number of additional CE# LOW cycles.

A[22:0]

(except A[19:18]) OPCODE ADDRESS

ADDRESS

DATA VALID

A[19:18]1

ADV#

CE#

OE#

WE#

LB#/UB#

DQ[15:0]

Initiate Control Register Access

Write Address Bus Value

to Control Register

CRE

tAVS tAVH

tAVH

tAVS

tVP

tVPH

tCPH

tWP

tCW

DON’T CARE

Select Control Register

CLK

A[22:0]

(except A[19:18])

A[19:18]2

CRE

ADV#

CE#

OE#

WE#

LB#/UB#

WAIT

DQ[15:0]

tSP

tHD

tCSP

tSP

tHD

High-Z

DON’T CARE

OPCODE ADDRESS

High-Z

tCEW

Latch Control Register Value

Latch Control Register Address

tCBPH3

DATA

VALID

ADDRESS

8 MEG x 16

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Figure 14: Register READ, Asynchronous Mode

Followed by READ ARRAY Operation

NOTE:

A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.

A[22:0]

(except A[19:18]) ADDRESS

ADDRESS

DATA VALID

CR VALID

A[19:18]1

ADV#

CE#

OE#

WE#

LB#/UB#

DQ[15:0]

Initiate Register Access

CRE

tAVH

tAVS

tAA

tVP

tVPH

tCPH

tCO

tOLZ

tBA

tLZ

tOE

tLZ

UNDEFINEDDON’T CARE

Select Register

tAAVD

tAVS

tAA

tHZ

tOHZ

tBHZ

tAVH

8 MEG x 16

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Figure 15: Register READ, Synchronous Mode Followed by READ ARRAY Operation

NOTE:

1. Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code two

(three clocks); WAIT active LOW; WAIT asserted during delay.

2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.

3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by

refresh collisions require a corresponding number of additional CE# LOW cycles.

CLK

A[22:0]

(except A[19:18])

A[19:18]2

CRE

ADV#

CE#

OE#

WE#

LB#/UB#

WAIT

DQ[15:0]

tSP

tHD

tHZ

tCSP

tKOH

UNDEFINEDDON’T CARE

tSP tHD

ADDRESS

tCW

Latch Control Register Value

tOLZ

Latch Control Register Address

tCBPH3

tBOE

DATA

VALID

ADDRESS

tACLK

tOHZ

High-Z

tABA

VALID

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Software Access

Software access of the registers uses a sequence of

asynchronous READ and asynchronous WRITE opera-

tions. The contents of the configuration registers can

be modified and all registers can be read using the

software sequence.

The configuration registers are loaded using a four-

step sequence consisting of two asynchronous READ

operations followed by two asynchronous WRITE

operations (see Figure 16). The read sequence is virtu-

ally identical except that an asynchronous READ is

performed during the fourth operation (see Figure 17).

The address used during all READ and WRITE opera-

tions is the highest address of the CellularRAM device

being accessed (7FFFFFh for 128Mb); the contents of

this address are not changed by using this sequence.

The data value presented during the third operation

(WRITE) in the sequence defines whether the BCR,

RCR, or the DIDR is to be accessed. If the data is 0000h,

the sequence will access the RCR; if the data is 0001h,

the sequence will access the BCR; if the data is 0002h,

the sequence will access the DIDR. During the fourth

operation, DQ[15:0] transfer data in to or out of bits

15–0 of the registers.

The use of the software sequence does not affect the

ability to perform the standard (CRE-controlled)

method of loading the configuration registers. How-

ever, the software nature of this access mechanism

eliminates the need for CRE. If the software mecha-

nism is used, CRE can simply be tied to VSS. The port

line often used for CRE control purposes is no longer

required.

Figure 16: Load Configuration Register

Figure 17: Read Configuration Register

ADDRESS

(MAX)

ADDRESS

(MAX)

ADDRESS

(MAX)

ADDRESS

(MAX)

XXXXh XXXXh

RCR: 0000h

BCR: 0001h

CR VALUE

DDRESS

CE#

OE#

WE#

LB#/UB#

DATA

DON'T CARE

READ READ WRITE WRITE

ADDRESS

(MAX)

ADDRESS

(MAX)

ADDRESS

(MAX)

ADDRESS

(MAX)

XXXXh XXXXh CR VALUE

OUT

ADDRESS

CE#

OE#

WE#

LB#/UB#

DATA

DON'T CARE

READ READ WRITE READ

RCR: 0000h

BCR: 0001h

DIDR: 0002h

8 MEG x 16

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Bus Configuration Register

The BCR defines how the CellularRAM device inter-

acts with the system memory bus. Page mode opera-

tion is enabled by a bit contained in the RCR. Figure 18

describes the control bits in the BCR. At power-up, the

BCR is set to 9D1Fh.

The BCR is accessed with CRE HIGH and A[19:18] =

10b, or through the register access software sequence

with DQ = 0001h on the third cycle.

Figure 18: Bus Configuration Register Definition

NOTE:

1. Burst wrap and length apply to both READ and WRITE operations.

A13

13 12 11 0

Latency

Counter

Initial

Latency

321

WAIT

Polarity

WAIT

Configuration (WC)

Drive Strength Burst

Wrap (BW)*

A12A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Operating Mode

Synchronous burst access mode

Asynchronous access mode (default)

BCR[12] BCR[11]

Latency Counter

BCR[13]

Code 0–Reserved

Code 1–Reserved

Code 2

Code 3 (Default)

Code 4

Code 5

Code 6

Code 7–Reserved

WAIT Polarity

Active LOW

Active HIGH (default)

BCR[10]

WAIT Configuration

Asserted during delay

Asserted one data cycle before delay (default)

Drive Strength

Full

1/2 (default)

1/4

Reserved

BCR[5]

BCR[4]

Initial Access Latency

Variable (default)

Fixed

BCR[14]

Burst Wrap (Note 1)

Burst wraps within the burst length

Burst no wrap (default)

BCR[3]

BCR[1] BCR[0] Burst Length (Note 1)

BCR[2]

Burst

Length (BL)*

Reserved Reserved

Operating

Mode

Reserved

22–20

A14A15

A[17:16]

Select RCR

Select BCR

Select DIDR

19–18 17–16

Select

Reserved

A[19:18]A[22:20]

Reserved

Must be set to "0"

Must be set to "0"Must be set to "0"

All must be set to "0"

BCR[8]

BCR[15]

BCR[19]

BCR[18]

Others

4 words

8 words

16 words

32 words

Continuous burst (default)

Reserved

Setting is ignored

(Default to "0")

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Burst Length (BCR[2:0])

Default = Continuous Burst

Burst lengths define the number of words the device

outputs during burst READ and WRITE operations. The

device supports a burst length of 4, 8, 16, or 32 words.

The device can also be set in continuous burst mode

where data is accessed sequentially without regard to

address boundaries; the internal address wraps to

000000h if the burst goes past the last address.

Burst Wrap (BCR[3]) Default = No Wrap

The burst-wrap option determines if a 4-, 8-, 16-, or

32-word READ or WRITE burst wraps within the burst

length, or steps through sequential addresses. If the

wrap option is not enabled, the device accesses data

from sequential addresses without regard to burst

boundaries; the internal address wraps to 000000h if

the burst goes past the last address.

Drive Strength (BCR[5:4])

Default = Outputs Use Half-Drive Strength

The output driver strength can be altered to full,

one-half, or one-quarter strength to adjust for different

data bus loading scenarios. The reduced-strength

options are intended for stacked chip (Flash + Cellular-

RAM) environments when there is a dedicated memory

bus. The reduced-drive-strength option minimizes the

noise generated on the data bus during READ opera-

tions. Full output drive strength should be selected

when using a discrete CellularRAM device in a more

heavily loaded data bus environment. Outputs are con-

figured at half-drive strength during testing. See Table 5

on page 22 for additional information.

Table 4: Sequence and Burst Length

BURST WRAP

STARTING

ADDRESS

WORD

BURST

LENGTH

8-WORD

BURST LENGTH 16-WORD BURST LENGTH

32-WORD

BURST LENGTH CONTINUOUS BURST

BCR[3] WRAP (DECIMAL) LINEAR LINEAR LINEAR LINEAR LINEAR

0Yes

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-...-29-30-31 0-1-2-3-4-5-6-…

1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-...-30-31-0 1-2-3-4-5-6-7-…

2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-...-31-0-1 2-3-4-5-6-7-8-…

3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-...-0-1-2 3-4-5-6-7-8-9-…

4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-...-1-2-3 4-5-6-7-8-9-10-…

5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-...-2-3-4 5-6-7-8-9-10-11-…

6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-...-3-4-5 6-7-8-9-10-11-12-

7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-...-4-5-6 7-8-9-10-11-12-13-…

... ... ... ...

14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-...-11-12-13 14-15-16-17-18-19-20-...

15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-...-12-13-14 15-16-17-18-19-20-21-...

... ... ...

30 30-31-0-...-27-28-29 30-31-32-33-34-...

31 31-0-1-...-28-29-30 31-32-33-34-35-...

1No

0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2...--29-30-31 0-1-2-3-4-5-6-…

1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-...-30-31-32 1-2-3-4-5-6-7-…

2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-...-31-32-33 2-3-4-5-6-7-8-…

3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-...-32-33-34 3-4-5-6-7-8-9-…

4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-...-33-34-35 4-5-6-7-8-9-10-…

5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20 5-6-7-...-34-35-36 5-6-7-8-9-10-11…

6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21 6-7-8-...-35-36-37 6-7-8-9-10-11-12…

7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-...-17-18-19-20-21-22 7-8-9-...-36-37-38 7-8-9-10-11-12-13…

... ... ... ...

14 14-15-16-17-18-19-...-23-24-25-26-27-28-29 14-15-16-...-43-44-45 14-15-16-17-18-19-20-…

15 15-16-17-18-19-20-...-24-25-26-27-28-29-30 15-16-17-...-44-45-46 15-16-17-18-19-20-21-…

... ... ...

30 30-31-32-...-59-60-61 30-31-32-33-34-35-36-...

31 31-32-33-...-60-61-62 31-32-33-34-35-36-37-...

8 MEG x 16

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WAIT Configuration (BCR[8])

Default = WAIT Transitions One Clock Before

Data Valid/Invalid

The WAIT configuration bit is used to determine

when WAIT transitions between the asserted and the

de-asserted state with respect to valid data presented

on the data bus. The memory controller will use the

WAIT signal to coordinate data transfer during synchro-

nous READ and WRITE operations. When BCR[8] = 0,

data will be valid or invalid on the clock edge immedi-

ately after WAIT transitions to the de-asserted or

asserted state, respectively (Figures 19 and 21). When A8

= 1, the WAIT signal transitions one clock period prior to

the data bus going valid or invalid (Figures 20 and 21).

WAIT Polarity (BCR[10])

Default = WAIT Active HIGH

The WAIT polarity bit indicates whether an asserted

WAIT output should be HIGH or LOW. This bit will

determine whether the WAIT signal requires a pull-up

or pull-down resistor to maintain the de-asserted

state.

Figure 19: WAIT Configuration (BCR[8] = 0)

NOTE:

Data valid/invalid immediately after WAIT

transitions (BCR[8] = 0). See Figure 21.

Figure 20: WAIT Configuration (BCR[8] = 1)

NOTE:

Valid/invalid data delayed for one clock after WAIT

transitions (BCR[8] = 1). See Figure 21.

Figure 21: WAIT Configuration During Burst Operation

NOTE:

Non-default BCR setting: WAIT active LOW.

Table 5: Drive Strength

BCR[5] BCR[4] DRIVE STRENGTH IMPEDANCE TYP (Ω)USE RECOMMENDATION

0 0 Full 25–30 CL = 30pF to 50pF

01 1/2

(default)

50 CL = 15pF to 30pF

104 MHz at light load

1 0 1/4 100 CL = 15pF or lower

1 1 Reserved

WAIT

DQ[15:0]

CLK

Data[0] Data[1]

Data immediatel

valid (or invalid)

High-Z

WAIT

D[15:0]

CLK

Data[0]

Data valid (or invalid) after one clock delay

High-Z

WAIT

DQ[15:0]

CLK

D[0]

BCR[8] = 0

Data valid in current cycle.

BCR[8] = 1

Data valid in next cycle.

DON’T CARE

D[2] D[3]

D[1]

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Latency Counter (BCR[13:11])

Default = Three Clock Latency

The latency counter bits determine how many

clocks occur between the beginning of a READ or

WRITE operation and the first data value transferred.

For allowable latency codes, see Tables 6 and 7 on

pages 24 and 25 respectively, and Figures 22 and 23 on

pages 24 and 25 respectively).

Initial Access Latency (BRC[14])

Default = Variable

Variable initial access latency outputs data after the

number of clocks set by the latency counter. However,

WAIT must be monitored to detect delays caused by

collisions with refresh operations.

Fixed initial access latency outputs the first data at a

consistent time that allows for worst-case refresh colli-

sions. The latency counter must be configured to

match the initial latency and the clock frequency. It is

not necessary to monitor WAIT with fixed initial

latency. The burst begins after the number of clock

cycles configured by the latency counter. The burst

will pause (and WAIT will be asserted) at the boundary

of a 128-word row. (See Table 7 and Figure 23 on

page 25.)

Operating Mode (BCR[15])

Default = Asynchronous Operation

The operating mode bit selects either synchronous

burst operation or the default asynchronous mode of

operation.

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NOTE:

1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on

the next clock cycle.

Figure 22: Latency Counter (Variable Initial Latency, No Refresh Collision)

Table 6: Variable Latency Configuration Codes

BCR[13:11]

LATENCY

CONFIGURATION CODE

LATENCY1MAX INPUT CLK FREQUENCY (MHz)

NORMAL

REFRESH

COLLISION -701 -708 -856

010 2 (3 clocks) 2 4 66 (15ns) 54 (18.5ns) 40 (25ns)

011 3 (4 clocks)—default 3 6 104 (9.62ns) 80 (12.5ns) 66 (15ns)

Others Reserved —————

A[22:0]

ADV#

DQ[15:0]

CLK

Code 2

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

Code 3 (Default)

DQ[15:0]

DON’T CARE UNDEFINED

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VOH

VOL

VALID

ADDRESS

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NOTE:

1. Fixed latency > 80 MHz available only with VCC/VCCQ from 1.8V–1.95V.

Figure 23: Latency Counter (Fixed Latency)

Table 7: Fixed Latency Configuration Codes

BCR[13:11]

LATENCY

CONFIGURATION CODE LATENCY COUNT (N)

MAX INPUT CLK FREQUENCY (MHz)

-701 -708 -856

010 2 (3 clocks) 2 33 (30ns) 33 (30ns) 20 (50ns)

011 3 (4 clocks)—default 3 52 (19.2ns) 52 (19.2ns) 33 (30ns)

100 4 (5 clocks) 4 66 (15ns) 66 (15ns) 40 (25ns)

101 5 (6 clocks) 5 75 (13.3ns) 75 (13.3ns) 52 (19.2ns)

110 6 (7 clocks) 6104 (9.62ns)180 (12.5ns) 66 (15ns)

Others Reserved ————

A[22:0]

ADV#

DQ[15:0]

(READ)

CLK

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

DON’T CARE UNDEFINED

VIH

VIL

VIH

VIL

VIH

VIL

CE# VIH

VIL

VOH

VOL

tAADV

tAA

tCO

tACLK

tSP tHD

DQ[15:0]

(WRITE)

VOH

VOL

N-1

Cycles Cycle N

VALID

INPUT

VALID

INPUT

VALID

INPUT

VALID

INPUT

VALID

INPUT

Burst Identified

(ADV# = LOW)

VALID

ADDRESS

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Refresh Configuration Register

The refresh configuration register (RCR) defines

how the CellularRAM device performs its transparent

self refresh. Altering the refresh parameters can dra-

matically reduce current consumption during standby

mode. Page mode control is also embedded into the

RCR. Figure 24 describes the control bits used in the

RCR. At power-up, the RCR is set to 0010h.

The RCR is accessed with CRE HIGH and A[19:18] =

00b; or through the register access software sequence

with DQ = 0000h on the third cycle (see “Registers” on

page 15.)

Partial Array Refresh (RCR[2:0]

Default = Full Array Refresh

The PAR bits restrict refresh operation to a portion

of the total memory array. This feature allows the

device to reduce standby current by refreshing only

that part of the memory array required by the host sys-

tem. The refresh options are full array, one-half array,

one-quarter array, one-eighth array, or none of the

array. The mapping of these partitions can start at

either the beginning or the end of the address map

(see Table 8 on page 27).

Figure 24: Refresh Configuration Register Mapping

PAR

A4 A3 A2 A1 A0

Read Configuration

Address Bus

45 1

Deep Power-Down

DPD Enable

DPD Disable (default)

RCR[4]

All must be set to "0"

A[17:8]

17–8

19–18

22–20

Select

Reserved Reserved ReservedReserved

A[22:20] A[19:18]

Select RCR

Select BCR

Select DIDR

RCR[19]

All must be set to "0"

RCR[1]

RCR[0]

Refresh Coverage

Full array (default)

Bottom 1/2 array

Bottom 1/4 array

Bottom 1/8 array

RCR[2]

None of array

Top 1/2 array

Top 1/4 array

Top 1/8 array

DPD

Must be set to "0"Setting is ignored

(Default 00b)

Page

Page Mode Enable/Disable

Page Mode Disabled (default)

Page Mode Enable

RCR[7]

RCR[18]

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Deep Power-Down (RCR[4])

Default = DPD Disabled

The deep power-down bit enables and disables all

refresh-related activity. This mode is used if the system

does not require the storage provided by the Cellular-

RAM device. Any stored data will become corrupted

when DPD is enabled. When refresh activity has been

re-enabled, the CellularRAM device will require 150µs

to perform an initialization procedure before normal

operations can resume.

Deep power-down is enabled by setting RCR[4] = 0

and taking CE# HIGH. DPD can be enabled using CRE

or the software sequence to access the RCR. Taking

CE# LOW for at least 10µs disables DPD and sets RCR[4] =

1; it is not necessary to write to the RCR to disable DPD.

Page Mode Operation (RCR[7])

Default = Disabled

The page mode operation bit determines whether

page mode is enabled for asynchronous READ opera-

tions. In the power-up default state, page mode is dis-

abled.

Device Identification Register

The DIDR provides information on the device man-

ufacturer, CellularRAM generation, and the specific

device configuration. Table 9 describes the bit fields in

the DIDR. This register is read-only.

The DIDR is accessed with CRE HIGH and A[19:18]

= 01b, or through the register access software

sequence with DQ = 0002h on the third cycle.

Table 8: 128Mb Address Patterns for PAR (RCR[4] = 1)

RCR[2] RCR[1] RCR[0] ACTIVE SECTION ADDRESS SPACE SIZE DENSITY

0 0 0 Full die 000000h–7FFFFFh 8 Meg x 16 128Mb

0 0 1 One-half of die 000000h–3FFFFFh 4 Meg x 16 64Mb

0 1 0 One-quarter of die 000000h–1FFFFFh 2 Meg x 16 32Mb

0 1 1 One-eighth of die 000000h–0FFFFFh 1 Meg x 16 16Mb

1 0 0 None of die 0 0 Meg x 16 0Mb

1 0 1 One-half of die 400000h–7FFFFFh 4 Meg x 16 64Mb

1 1 0 One-quarter of die 600000h–7FFFFFh 2 Meg x 16 32Mb

1 1 1 One-eighth of die 700000h–7FFFFFh 1 Meg x 16 16Mb

Table 9: Device Identification Register Mapping

BIT FIELD DIDR[15] DIDR[14:11] DIDR[10:8] DIDR[7:5] DIDR[4:0]

Field Name Reserved Device Version Device Density CellularRAM

Generation

Vendor ID

Bit Setting Version

Bit Setting 0b 0000b 1st 011b 010b 00011b

0001b 2nd

Meaning — 128Mb CellularRAM 1.5 Micron

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Electrical Characteristics and Conditions

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

Table 10: Absolute Maximum Ratings

PARAMETER RATING

Voltage to Any Ball Except Vcc, VccQ Relative to Vss –0.50V to (4.0V or VccQ + 0.3V, whichever is less)

Voltage on Vcc Supply Relative to Vss –0.2V to +2.45V

Voltage on VccQ Supply Relative to Vss –0.2V to +2.45V

Storage Temperature (plastic) –55ºC to +150ºC

Operating Temperature (case)

Wireless –30ºC to +85ºC

Industrial –40ºC to +85ºC

Soldering Temperature and Time

10s (solder ball only) +260ºC

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NOTE:

1. Input signals may overshoot to VccQ + 1.0V for periods less than 2ns during transitions.

2. Input signals may undershoot to Vss - 1.0V for periods less than 2ns during transitions.

3. BCR[5:4] = 01b (default setting of one-half drive strength).

4. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current

required to drive output capacitance expected in the actual system.

5. ISB (MAX) values measured with PAR set to FULL ARRAY and at +85°C. In order to achieve low standby current, all inputs

must be driven to either VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, or when entering

standby mode.

Table 11: Electrical Characteristics and Operating Conditions

Wireless Temperature (-30ºC < TC < +85ºC); Industrial Temperature (-40ºC < TC < +85ºC)

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Supply Voltage VCC 1.7 1.95 V

I/O Supply Voltage VCCQ W: 1.8V 1.7 1.95 V

Input High Voltage VIH VCCQ - 0.4 VCCQ + 0.2 V 1

Input Low Voltage VIL -0.20 0.4 V 2

Output High Voltage IOH = -0.2mA VOH 0.80 VCCQV3

Output Low Voltage IOL = +0.2mA VOL 0.20 VCCQV 3

Input Leakage Current VIN = 0 to VCCQILI 1µA

Output Leakage Current OE# = VIH or

Chip Disabled

ILO 1µA

Operating Current

Asynchronous Random READ/

WRITE

VIN = VCCQ or 0V

Chip Enabled,

IOUT = 0

ICC1-70 25 mA 4

-85 22

Asynchronous Page READ ICC1P -70 15 mA 4

-85 12

Initial Access, Burst READ/WRITE ICC2 104 MHz 35 mA 4

80 MHz 30

66 MHz 25

Continuous Burst READ ICC3R 104 MHz 30 mA 4

80 MHz 25

66 MHz 20

Continuous Burst WRITE ICC3W 104 MHz 35 mA 4

80 MHz 30

66 MHz 25

Standby Current VIN = VCCQ or 0V

CE# = VCCQ

ISB Standard 200 µA 5

Low-Power (L) 160

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NOTE:

IPAR (MAX) values measured at 85°C. IPAR might be slightly higher for up to 500ms after changes to the PAR array parti-

tion.

Figure 25: Typical Refresh Current vs. Temperature (ITCR)

Table 12: Partial Array Refresh Specifications and Conditions

DESCRIPTION CONDITIONS SYMBOL

ARRAY

PARTITION MAX UNITS

Partial Array Refresh Standby

Current

VIN = VCCQ or 0V,

CE# = VCCQ

IPAR Standard Power

(no desig.)

Full 200 µA

1/2 170

1/4 155

1/8 150

0140

Low-Power

Option

(L)

Full 160 µA

1/2 130

1/4 115

1/8 110

0100

140

130

120

110

100

–30 –20 –10 0 10 20 30 40 50 60 70 80 90

Current (µA)

Temperature (C)

PAR = Full Array

PAR = 1/2 of Array

PAR = 1/4 of Array

PAR = 1/8 of Array

PAR = None of Array

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NOTE:

Typical (TYP) IZZ value applies across all operating temperatures and voltages.

NOTE:

1. These parameters are verified in device characterization and are not 100% tested.

Figure 26: AC Input/Output Reference Waveform

NOTE:

1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns.

2. Input timing begins at VCCQ/2.

3. Output timing ends at VCCQ/2.

Figure 27: AC Output Load Circuit

NOTE:

All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).

Table 13: Deep Power-Down Specifications

DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS

Deep Power-Down VIN = VCCQ or 0V;

VCC, VCCQ = 1.95V; +85°C

IZZ 325µA

Table 14: Capacitance

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Input Capacitance TC = +25ºC; f = 1 MHz;

VIN = 0V

CIN 2.0 6 pF 1

Input/Output Capacitance (DQ) CIO 3.5 6 pF 1

Output

Test Points

Input

VCCQ

VSSQ

VCCQ/2

VCC

DUT VccQ/2

30pF

Test Point

50Ω

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NOTE:

1. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 31. The High-Z timings measure a 100mV

transition from either VOH or VOL toward VCCQ/2.

2. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 31. The Low-Z timings measure a 100mV

transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.

3. Page mode enabled only.

Table 15: Asynchronous READ Cycle Timing Requirements

All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).

PARAMETER SYMBOL

-701/708 -856

UNITS NOTESMIN MAX MIN MAX

Address Access Time tAA 70 85 ns

ADV# Access Time tAADV 70 85 ns

Page Access Time tAPA 20 25 ns

Address Hold from ADV# HIGH tAVH 22ns

Address Setup to ADV# HIGH tAVS 55ns

LB#/UB# Access Time tBA 70 85 ns

LB#/UB# Disable to DQ High-Z Output tBHZ 88ns1

LB#/UB# Enable to Low-Z Output tBLZ 10 10 ns 2

Maximum CE# Pulse Width tCEM 44µs3

CE# LOW to WAIT Valid tCEW 17.517.5ns

Chip Select Access Time tCO 70 85 ns

CE# LOW to ADV# HIGH tCVS 77ns

Chip Disable to DQ and WAIT High-Z Output tHZ 88ns1

Chip Enable to Low-Z Output tLZ 10 10 ns 2

Output Enable to Valid Output tOE 20 20 ns

Output Hold from Address Change tOH 55ns

Output Disable to DQ High-Z Output tOHZ 88ns1

Output Enable to Low-Z Output tOLZ 33ns2

Page Cycle Time tPC 20 25 ns

READ Cycle Time tRC 70 85 ns

ADV# Pulse Width LOW tVP 57ns

ADV# Pulse Width HIGH tVPH 10 10 ns

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NOTE:

1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two

conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.

2. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 31. The High-Z timings measure a 100mV

transition from either VOH or VOL toward VCCQ/2.

3. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 31. The Low-Z timings measure a 100mV

transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.

Table 16: Burst READ Cycle Timing Requirements

All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).

PARAMETER SYMBOL

-701 -708 -856

UNITS NOTESMIN MAX MIN MAX MIN MAX

Address Access Time (Fixed Latency) tAA 70 70 85 ns

ADV# Access Time (Fixed Latency) tAADV 70 70 85 ns

Burst to READ Access Time (Variable Latency) tABA 35 46 55 ns

CLK to Output Delay tACLK 7911ns

Address Hold from ADV# HIGH (Fixed Latency) tAVH 222 ns

Burst OE# LOW to Output Delay tBOE 20 20 20 ns

CE# HIGH between Subsequent Burst or Mixed-

Mode Operations

tCBPH 5 6 8 ns 1

Maximum CE# Pulse Width tCEM 444µs1

CE# or ADV# LOW to WAIT Valid tCEW 17.517.517.5 ns

CLK Period tCLK 9.62 12.5 15 ns

Chip Select Access Time (Fixed Latency) tCO 70 70 85 ns

CE# Setup Time to Active CLK Edge tCSP 345 ns

Hold Time from Active CLK Edge tHD 222 ns

Chip Disable to DQ and WAIT High-Z Output tHZ 8 8 8 ns 2

CLK Rise or Fall Time tKHKL 1.6 1.8 2.0 ns

CLK to WAIT Valid tKHTL 7911ns

Output HOLD from CLK tKOH 2 2 2 ns

CLK HIGH or LOW Time tKP 3 4 5 ns

Output Disable to DQ High-Z Output tOHZ 8 8 8 ns 2

Output Enable to Low-Z Output tOLZ 333 ns 3

Setup Time to Active CLK Edge tSP 3 3 3 ns

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NOTE:

1. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 31. The High-Z timings measure a 100mV

transition from either VOH or VOL toward VCCQ/2.

2. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 31. The Low-Z timings measure a 100mV

transition away from the High-Z (VCCQ/2) level toward either VOH or VOL.

3. WE# LOW time must be limited to tCEM (4µs).

Table 17: Asynchronous WRITE Cycle Timing Requirements

PARAMETER SYMBOL

-701/708 -856

UNITS NOTESMIN MAX MIN MAX

Address and ADV# LOW Setup Time tAS 00ns

Address Hold from ADV# Going HIGH tAVH 22ns

Address Setup to ADV# Going HIGH tAVS 55ns

Address Valid to End of WRITE tAW 70 85 ns

LB#/UB# Select to End of WRITE tBW 70 85 ns

CE# LOW to WAIT Valid tCEW 1 7.5 1 7.5 ns

CE# HIGH between Subsequent Async Operations tCPH 55ns

CE# LOW to ADV# HIGH tCVS 77ns

Chip Enable to End of WRITE tCW 70 85 ns

Data Hold from WRITE Time tDH 00ns

Data WRITE Setup Time tDW 20 20 ns

Chip Disable to WAIT High-Z Output tHZ 88ns1

Chip Enable to Low-Z Output tLZ 10 10 ns 2

End WRITE to Low-Z Output tOW 55ns 2

ADV# Pulse Width tVP 57ns

ADV# Pulse Width HIGH tVPH 10 10 ns

ADV# Setup to End of WRITE tVS 70 85 ns

WRITE Cycle Time tWC 70 85 ns

WRITE to DQ High-Z Output tWHZ 88ns 1

WRITE Pulse Width tWP 45 55 ns 3

WRITE Pulse Width HIGH tWPH 10 10 ns

WRITE Recovery Time tWR 00ns

8 MEG x 16

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NOTE:

1. tAS required if tCSP > 20ns.

2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two

conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.

3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 31. The High-Z timings measure a 100mV

transition from either VOH or VOL toward VCCQ/2.

Table 18: Burst WRITE Cycle Timing Requirements

PARAMETER SYMBOL

-701 -708 -856

UNITS NOTESMIN MAX MIN MAX MIN MAX

Address and ADV# LOW setup time tAS 000 ns1

Address Hold from ADV# HIGH (Fixed Latency) tAVH 222 ns

CE# HIGH between Subsequent Burst or Mixed-

Mode Operations

tCBPH 5 6 8 ns 2

Maximum CE# Pulse Width tCEM 444µs2

CE# LOW to WAIT Valid tCEW 17.517.517.5 ns

Clock Period tCLK 9.62 12.5 15 ns

CE# Setup to CLK Active Edge tCSP 345 ns

Hold Time from Active CLK Edge tHD 222 ns

Chip Disable to WAIT High-Z Output tHZ 888ns3

Last Clock to ADV# LOW (Fixed Latency) tKADV 466 ns

CLK Rise or Fall Time tKHKL 1.6 1.8 2.0 ns

Clock to WAIT Valid tKHTL 7911ns

CLK HIGH or LOW Time tKP 345 ns

Setup Time to Activate CLK Edge tSP 3 3 3 ns

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Timing Diagrams

Figure 28: Initialization Period

Figure 29: DPD Entry and Exit Timing Parameters

tPU

Vcc, VccQ = 1.7V

Vcc (MIN)

Device ready fo

normal operation

CE#

DPD EnabledWrite

RCR[4] = 0

DPD Exit Device Initialization Device ready for

normal operation

tDPD tDPDX tPU

Table 19: Initialization and DPD Timing Parameters

PARAMETER SYMBOL

-701/708 -856

UNITS NOTEMIN MAX MIN MAX

Initialization Period (required before normal operations) tPU 150 150 µs

Time from DPD entry to DPD exit tDPD 10 10 µs

CE# LOW time to exit DPD tDPDX 10 10 µs

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Figure 30: Asynchronous READ

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

A[22:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

tAA

tHZ

tBA

High-Z High-Z

tRC

tCO

tBHZ

tOHZ

tHZ

tOE

tCEW

VALID OUTPUT

High-Z

UNDEFINED

DON’T CARE

tBLZ

tLZ

tOLZ

Table 20: Asynchronous READ Timing Parameters

SYMBOL

-701/708 -856

UNITS SYMBOL

-701/708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tHZ 88ns

tBA 70 85 ns

tLZ 10 10 ns

tBHZ 8 8 ns

tOE 20 20 ns

tBLZ 10 10 ns

tOHZ 8 8 ns

tCEW 1 7.5 1 7.5 ns tOLZ 33ns

tCO 70 85 ns

tRC 70 85 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 31: Asynchronous READ Using ADV#

A[22:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

tVPH

tAADV

tAA

tVP

tHZ

tBA

High-Z High-Z

tCVS

tCO

tBLZ

tBHZ

tOHZ

tHZ

tLZ

tOE

tOLZ

VALID OUTPUT

tAVH

tAVS

High-Z

UNDEFINED

DON’T CARE

tCEW

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

Table 21: Asynchronous READ Timing Parameters Using ADV#

SYMBOL

-701/708 -856

UNITS SYMBOL

-701/708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns tCVS 77ns

tAADV 70 85 ns

tHZ 88ns

tAVH 22ns

tLZ 10 10 ns

tAVS 55ns

tOE 20 20 ns

tBA 70 85 ns

tOHZ 8 8 ns

tBHZ 8 8 ns

tOLZ 33ns

tBLZ 10 10 ns

tVP 57ns

tCEW 1 7.5 1 7.5 ns tVPH 10 10 ns

tCO 70 85 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 32: Page Mode READ

A[3:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

tAA

tHZ

tBA

High-Z High-Z

tCO

tCEM

tBLZ

tBHZ

tOHZ

tHZ

tLZ

tOE

tOLZ

tCEW

High-Z

UNDEFINED

DON’T CARE

A[22:4] VALID ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

tRC

VALID

OUTPUT

tAPA

tPC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

tOH

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

Table 22: Asynchronous READ Timing Parameters—Page Mode Operation

SYMBOL

-701/708 -856

UNITS SYMBOL

-701/708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tHZ 8 8 ns

tAPA 20 25 ns tLZ 10 10 ns

tBA 70 85 ns

tOE 20 20 ns

tBHZ 8 8 ns

tOH 5 5 ns

tBLZ 10 10 ns

tOHZ 8 8 ns

tCEM 44µs

tOLZ 33ns

tCEW 1 7.5 1 7.5 ns tPC 20 25 ns

tCO 70 85 ns

tRC 70 85 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 33: Single-Access Burst READ Operation—Variable Latency

NOTE:

Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

A[22:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

tSP

tCLK

tCEW

tHD

tABA

tHD

VALID

OUTPUT

VALID

ADDRESS

High-Z

tKOH

tOHZ

tSP

LB#/UB#

VIH

VIL

tCSP

tCEM

High-Z

OLZ

tHD

tSP

tHZ

tKP tKP

tKHKL

tHD

tSP

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tKHTL

tBOE

High-Z

tACLK

Table 23: Burst READ Timing Parameters—Single Access, Variable Latency

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tABA 35 46 55 ns tHZ 8 8 8 ns

tACLK 79 11ns tKHKL 1.6 1.8 2.0 ns

tBOE 20 20 20 ns tKHTL 7911ns

tCEM 444µs

tKOH 2 2 2 ns

tCEW 17.517.517.5ns tKP 345ns

tCLK 9.62 12.5 15 ns tOHZ 8 8 8 ns

tCSP 345ns

tOLZ 333ns

tHD 222ns

tSP 3 3 3 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 34: 4-Word Burst READ Operation—Variable Latency

NOTE:

Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tSP

tCLK

tKHKL

tHD

tABA

VALID

ADDRESS

High-Z

tKOH

tHZ

tHD

tSP

LB#/UB# VIH

VIL

High-Z

tOLZ

High-Z

tCBPH

tCSP

tCEM

tSP tHD

tOHZ

tHD

tKP tKP

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tCEW

tACLK

tKHTL

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

tBOE

Table 24: Burst READ Timing Parameters—4-Word Burst

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tABA 35 46 55 ns tHZ 8 8 8 ns

tACLK 7911ns

tKHKL 1.6 1.8 2.0 ns

tBOE 20 20 20 ns tKHTL 7911ns

tCBPH 5 6 8 ns

tKOH 2 2 2 ns

tCEM 444µs

tKP 345ns

tCEW 17.517.517.5ns tOHZ 8 8 8 ns

tCLK 9.62 12.5 15 ns tOLZ 333ns

tCSP 345ns

tSP 3 3 3 ns

tHD 222ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 35: Single-Access Burst READ Operation—Fixed Latency

NOTE:

Non-default BCR settings: Fixed latency; latency code four (five clocks); WAIT active LOW; WAIT asserted during delay.

A[22:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

CLK

CEW

AVH

AADV

VALID

OUTPUT

VALID

ADDRESS

High-Z

KOH

OHZ

LB#/UB#

VIH

VIL

CSP

CEM

High-Z

OLZ

KHKL

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

KHTL

BOE

High-Z

ACLK

Table 25: Burst READ Timing Parameters—Single Access, Fixed Latency

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 70 85 ns tHD 222ns

tAADV 70 70 85 ns tHZ 8 8 8 ns

tACLK 7911ns

tKHKL 1.6 1.8 2.0 ns

tAVH 222ns

tKHTL 7911ns

tBOE 20 20 20 ns tKOH 2 2 2 ns

tCEM 444µs

tKP 345ns

tCEW 17.517.517.5ns tOHZ 8 8 8 ns

tCLK 9.62 12.5 15 ns

tOLZ 333ns

tCO 70 70 85 ns tSP 3 3 3 ns

tCSP 345ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 36: 4-Word Burst READ Operation—Fixed Latency

NOTE:

Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tAVH

tCLK

tKHKL

tCO

tAADV

tAA

High-Z

tKOH

tHZ

tHD

tSP

LB#/UB# VIH

VIL

High-Z

tOLZ

High-Z

tCBPH

tCSP

tCEM

tSP tHD

tOHZ

tHD

tKP tKP

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

tCEW tKHTL

tACLK

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

tBOE

VALID

ADDRESS

Table 26: Burst READ Timing Parameters—4-Word Burst, Fixed Latency

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 70 85 ns tCSP 345ns

tAADV 70 70 85 ns tHD 222ns

tACLK 7911ns

tHZ 8 8 8 ns

tAVH 222ns

tKHKL 1.6 1.8 2.0 ns

tBOE 20 20 20 ns tKHTL 7911ns

tCBPH 5 6 8 ns

tKOH 2 2 2 ns

tCEM 444µs

tKP 345ns

tCEW 17.517.517.5ns tOHZ 8 8 8 ns

tCLK 9.62 12.5 15 ns tOLZ 333ns

tCO 70 70 85 ns tSP 3 3 3 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 37: READ Burst Suspend

NOTE:

1. Non-default BCR settings for READ burst suspend: Fixed or variable latency; latency code two (three clocks); WAIT active

LOW; WAIT asserted during delay.

2. CLK can be stopped LOW or HIGH, but must be static, with no LOW-to-HIGH transitions during burst suspend.

3. OE# can stay LOW during burst suspend. If OE# is LOW, DQ[15:0] will continue to output valid data.

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tSP tHD

High-Z

tOLZ

tACLK

LB#/UB# VIH

VIL

tCLK

tSP

tCSP

tSP tHD

tHD

tSP tHD

tKOH

VALID

OUTPUT VALID

OUTPUT

UNDEFINED

DON’T CARE

VALID

ADDRESS

High-Z

CBPH

CEM

tOHZ

VALID

OUTPUT VALID

OUTPUT

tBOE

OHZ

tBOE

tOLZ

VALID

ADDRESS

NOTE 3

NOTE 2

High-Z

Table 27: Burst READ Timing Parameters—Burst Suspend

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 7911ns

tHD 222ns

tBOE 20 20 20 ns tHZ 8 8 8 ns

tCBPH 5 6 8 ns

tKOH 222ns

tCEM 444µs

tOHZ 8 8 8 ns

tCLK 9.62 12.5 15 ns

tOLZ 333ns

tCSP 3 4 5 ns

tSP 3 3 3 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 38: Continuous Burst READ Showing an Output Delay

with BCR[8] = 0 for Variable Latency End-of-Row Condition

NOTE:

1. Non-default BCR settings for continuous burst READ, BCR[8] = 0: WAIT active LOW; WAIT asserted during delay. Do not

cross row boundaries with fixed latency.

2. CE# must not remain LOW longer than tCEM.

3. WAIT asserts for anywhere from LC to 2LC cycles. LC = Latency Code (BCR[13:11]).

tACLK tKOH

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VOH

VOL

tKHTL tKHTL

tCLK

LB#/UB# VIH

VIL

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

DON’T CARE

VALID

OUTPUT

NOTE 3

NOTE 2

End of Row

Table 28: Burst READ Timing Parameters—BCR[8] = 0

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 7911ns

tKHTL 7911ns

tCLK 9.62 12.5 15 ns

tKOH 2 2 2 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 39: CE#-Controlled Asynchronous WRITE

A[22:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VALID ADDRESS

High-Z High-Z

tWC

tCEW tHZ

VALID INPUT

tAW

DON’T CARE

tWR

tCW tCPH

tDW

DQ[15:0]

OUT

tWHZ

tBW

tLZ

tDH

tAS

tWP

tWPH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

High-Z

Table 29: Asynchronous WRITE Timing Parameters—CE#-Controlled

SYMBOL

-701/708 -856

UNITS SYMBOL

-701/708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tHZ 88ns

tAW 70 85 ns tLZ 10 10 ns

tBW 70 85 ns tWC 70 85 ns

tCEW 1 7.5 1 7.5 ns tWHZ 88ns

tCPH 55ns

tWP 45 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 00ns

tWR 00ns

tDW 20 20 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 40: LB#/UB#-Controlled Asynchronous WRITE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

A[22:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VIH

VIL

VALID ADDRESS

High-Z

tWC

tCEW tHZ

VALID INPUT

tAW

DON’T CARE

tWR

tCW

tDW

DQ[15:0]

OUT

VOH

VOL

tWHZ

tBW

tLZ

tDH

tAS

tWP

tWPH

High-Z

Table 30: Asynchronous WRITE Timing Parameters—LB#/UB#-Controlled

SYMBOL

-701/708 -856

UNITS SYMBOL

-701/708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tHZ 88ns

tAW 70 85 ns

tLZ 10 10 ns

tBW 70 85 ns

tWC 70 85 ns

tCEW 1 7.5 1 7.5 ns tWHZ 8 8 ns

tCW 70 85 ns

tWP 45 55 ns

tDH 0 0 ns

tWPH 10 10 ns

tDW 20 20 ns tWR 0 0 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 41: WE#-Controlled Asynchronous WRITE

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

A[22:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VIH

VIL

VALID ADDRESS

tWC

tCEW tHZ

VALID INPUT

tAW

DON’T CARE

tWR

tDW

DQ[15:0]

OUT

VOH

VOL

tWHZ

tBW

tCW

tLZ

tWP

tDH

tOW

tAS

tWPH

High-Z

Table 31: Asynchronous WRITE Timing Parameters—WE#-Controlled

SYMBOL

-701/708 -856

UNITS SYMBOL

-701/708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tLZ 10 10 ns

tAW 70 85 ns

tOW 55ns

tBW 70 85 ns

tWC 70 85 ns

tCEW 1 7.5 1 7.5 ns tWHZ 8 8 ns

tCW 70 85 ns

tWP 45 55 ns

tDH 0 0 ns

tWPH 10 10 ns

tDW 20 20 ns tWR 0 0 ns

tHZ 88ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 42: Asynchronous WRITE Using ADV#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

A[22:0]

ADV#

CE#

LB#/UB#

OE#

WE#

WAIT

DQ[15:0]

VIH

VIL

VALID ADDRESS

High-Z High-Z

tCEW tHZ

VALID INPUT

tVS

DON’T CARE

tCW

tDW

DQ[15:0]

OUT

VOH

VOL

tWHZ

tBW

tLZ

tWP

tDH

tOW

tAS

tWPH

tAS

tVPH

tAVH

tAVS

tVP

tAW

High-Z

Table 32: Asynchronous WRITE Timing Parameters Using ADV#

SYMBOL

-701/708 -856

UNITS SYMBOL

-701/708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tHZ 88ns

tAVH 22ns

tLZ 10 10 ns

tAVS 55ns

tOW 55ns

tAW 70 85 ns

tVP 57ns

tBW 70 85 ns

tVPH 10 10 ns

tCEW 1 7.5 1 7.5 ns tVS 70 85 ns

tCW 70 85 ns

tWHZ 8 8 ns

tDH 0 0 ns

tWP 45 55 ns

tDW 20 20 ns tWPH 10 10 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 43: Burst WRITE Operation—Variable Latency Mode

NOTE:

1. Non-default BCR settings for burst WRITE operation in variable latency mode: Latency code two (three clocks); WAIT

active LOW; WAIT asserted during delay; burst length four; burst wrap enabled.

2. WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]).

3. tAS required if tCSP > 20ns.

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK tKP

tSP

tAS3

tCSP

D[0]D[3]D[2]D[1]

VALID

ADDRESS

tHD

tSP

tHD

tSP

tHD

tSP

High-Z High-Z

LB#/UB# VIH

VIL

tSP tHD

tHD

DON’T CARE

WRITE Burst Identified

(WE# = LOW)

tCBPH

tKADV

tKHTL

tAS3

tHZ

tCEW

tKP tKHKL

NOTE 2

tCEM

Table 33: Burst WRITE Timing Parameters

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tAS 000ns

tHZ 888ns

tCBPH 5 6 8 ns

tKADV 466ns

tCEM 444µs

tKHKL 1.6 1.8 2.0 ns

tCEW 17.517.517.5ns tKHTL 7911ns

tCLK 9.62 12.5 15 ns

tKP 3 4 5 ns

tCSP 3 4 5 ns

tSP 3 3 3 ns

tHD 2 2 2 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 44: Burst WRITE Operation—Fixed Latency Mode

NOTE:

1. Non-default BCR settings for burst WRITE operation in fixed latency mode: Fixed latency; latency code two (three

clocks); WAIT active LOW; WAIT asserted during delay; burst length four; burst wrap enabled.

2. WAIT asserts for LC cycles for both fixed and variable latency. LC = Latency Code (BCR[13:11]).

3. tAS required if tCSP > 20ns.

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK tKP

tSP

tAS3

tCSP

D[0]D[3]D[2]D[1]

VALID

ADDRESS

tHD

tSP

tHD

tSP

tHD

tSP

High-Z High-Z

LB#/UB# VIH

VIL

tSP tHD

tHD

tKADV

DON’T CARE

WRITE Burst Identified

(WE# = LOW)

tCBPH

tKHTL

tAS3

tHZ

tCEW

tKP tKHKL

NOTE 2

tCEM

tAVH

Table 34: Burst WRITE Timing Parameters

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tAS 000ns

tHD 2 2 2 ns

tAVH 222ns

tHZ 888ns

tCBPH 5 6 8 ns

tKADV 466ns

tCEM 444µs

tKHKL 1.6 1.8 2.0 ns

tCEW 17.517.517.5ns tKHTL 7911ns

tCLK 9.62 12.5 15 ns tKP 3 4 5 ns

tCSP 3 4 5 ns

tSP 3 3 3 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 45: Continuous Burst WRITE Showing an Output Delay

with BCR[8] = 0 for Variable Latency End-of-Row Condition

NOTE:

1. Non-default BCR settings for continuous burst WRITE, BCR[8] = 0: WAIT active LOW; WAIT asserted during delay. Do not

cross row boundaries with fixed latency.

2. CE# must not remain LOW longer than tCEM.

3. WAIT asserts for anywhere from LC to 2LC cycles. LC = Latency Code (BCR[13:11]).

4. Taking CE# HIGH or ADV# LOW on the start-of-row cycle will abort the burst and not write the start-of-row data.

Devices from different CellularRAM vendors can assert WAIT so that the start-of-row data is input just before (as

shown), or just after WAIT asserts. This difference in behavior will not be noticed by controllers that monitor WAIT, or

that use WAIT to abort on the start-of-row input cycle.

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK VIH

VIL

VIH

VIL

tKHTL tKHTL

tCLK

tSP tHD

START OF ROW

(A[6:0] = 00h)

(NOTE 4)

END OF ROW

(A[6:0] = 7Fh)

VALID INPUTVALID INPUTVALID INPUTVALID INPUT

DON’T CARE

VIH

VIL

LB#/UB#

NOTE 3

NOTE 2

Table 35: Burst WRITE Timing Parameters—BCR[8] = 0

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tCLK 9.62 12.5 15 ns

tKHTL 7811ns

tHD 2 2 2 ns

tSP 3 3 3 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 46: Burst WRITE Followed by Burst READ

NOTE:

1. Non-default BCR settings for burst WRITE followed by burst READ: Fixed or variable latency; latency code two (three

clocks); WAIT active LOW; WAIT asserted during delay.

2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two

conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns. CE# can stay LOW between burst READ and burst

WRITE operations, but CE# must not remain LOW longer than tCEM. See burst interrupt diagrams (Figures 47–49,

pages 54 through 56) for cases where CE# stays LOW between bursts.

3. Only fixed latency requires tKADV.

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK

tSP

tCSP

D[3]D[2]D[1]

D[0]

VALID

ADDRESS

tHD

tSP

tHD

tSP

tSP tHD

VALID

ADDRESS

tCSP tOHZ

tKOH

tACLK

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

High-Z

High-Z VOH

VOL

LB#/UB# VIH

VIL

tHD

tSP tHD

tHD

High-Z

UNDEFINED

DON’T CARE

tBOE

tCBPH

High-Z

tHD

tHD tSP

tKADV3

NOTE 2

Table 36: WRITE Timing Parameters—Burst WRITE Followed by Burst READ

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tCBPH 5 6 8 ns

tHD 222ns

tCLK 9.62 20 12.5 20 15 20 ns tKADV 466ns

tCSP 3 20420520ns tSP 3 3 3 ns

Table 37: READ Timing Parameters—Burst WRITE Followed by Burst READ

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 7911ns

tHD 222ns

tBOE 20 20 20 ns tKOH 2 2 2 ns

tCLK 9.62 12.5 15 ns

tOHZ 8 8 8 ns

tCSP 345ns

tSP 333ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 47: Burst READ Interrupted by Burst READ or WRITE

NOTE:

1. Non-default BCR settings for burst READ interrupted by burst READ or WRITE: Fixed or variable latency code two (three

clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no refresh collision.

2. Burst interrupt shown on first allowable clock (i.e., after the first data received by controller).

3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.

4. For variable latency, WAIT asserts tKHTL after ADV# is clocked LOW. For fixed latency, WAIT asserts tCEW after ADV#

transitions LOW.

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

2nd Cycle READ

VIH

VIL

OE#

2nd Cycle WRITE

VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0] OUT

2nd Cycle READ

VOH

VOL

CLK VIH

VIL

DQ[15:0] IN

2nd Cycle WRITE

VIH

VIL

tHD

tSP

tSP tHD

tCLK

tOHZ

tKOH

tACLK

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

LB#/UB#

2nd Cycle READ

VIH

VIL

LB#/UB#

2nd Cycle WRITE

VIH

VIL

tSP tHD

UNDEFINED

DON’T CARE

tHD

tSP

tCSP

tSP tHD

VALID

ADDRESS

tOHZ

tKOH

tACLK

VALID

OUTPUT

High-Z

tBOE

tCEW

tSP tHD

tHD

tSP

VOH

VOL

tBOE

D[2] D[3]D[1]

D[0]

High-Z

tCEM (Note 3)

VALID

ADDRESS

READ Burst interrupted with new READ or WRITE. See Note 2.

High-Z

tKHTL

NOTE 4

tHD

High-Z

Table 38: READ Timing Parameters—Burst WRITE Interrupted

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 7911ns

tHD 222ns

tBOE 20 20 20 ns tKHTL 7911ns

tCEW 17.517.517.5ns tKOH 2 2 2 ns

tCLK 9.62 12.5 15 ns

tOHZ 8 8 8 ns

tCSP 345ns

tSP 333ns

Table 39: WRITE Timing Parameters—Burst WRITE Interrupted

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tCLK 9.62 20 12.5 20 15 20 ns tHD 222 ns

tCSP 3 20 4 20 5 20 ns tSP 3 3 3 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 48: Burst WRITE Interrupted by Burst WRITE or READ—

Variable Latency Mode

NOTE:

1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in variable latency mode: Variable latency;

latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. All bursts shown for variable latency; no

refresh collision.

2. Burst interrupt shown on first allowable clock (i.e., after first data word written).

3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

2nd Cycle WRITE

VIH

VIL

OE#

2nd Cycle READ

VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0] IN

2nd Cycle WRITE

DQ[15:0] OUT

2nd Cycle READ

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK

tSP

tCSP

D[0]

VALID

ADDRESS

tHD

tSP

tHD

tSP

tSP tHD

VALID

ADDRESS

tHD

High-Z

LB#/UB#

2nd Cycle WRITE

LB#/UB#

2nd Cycle READ

VIH

VIL

VIH

VIL

tHD

tSP tHD

tKHTL

tSP tHD

UNDEFINED

DON’T CARE

D[2] D[3]D[1]

D[0]

tHD

tSP

tHD

tHD tSP

tOHZ

tBOE

tSP tHD

tKOH

tACLK

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

High-Z

VOH

VOL

VOH

VOL

WRITE Burst interrupted with new WRITE or READ. See Note 2.

VALID

ADDRESS

tCEM (NOTE 3)

High-Z

Table 40: WRITE Timing Parameters—Burst READ Interrupted

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tCLK 9.62 20 12.5 20 15 20 ns tKHTL 7911ns

tCSP 3 20 4 20 5 20 ns tSP 3 3 3 ns

tHD 222ns

Table 41: READ Timing Parameters—Burst READ Interrupted

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 7911ns

tHD 222ns

tBOE 20 20 20 ns tKOH 2 2 2 ns

tCLK 9.62 12.5 15 ns

tOHZ 8 8 8 ns

tCSP 345ns

tSP 333ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 49: Burst WRITE Interrupted by Burst WRITE or READ—Fixed Latency Mode

NOTE:

1. Non-default BCR settings for burst WRITE interrupted by burst WRITE or READ in fixed latency mode: Fixed latency; latency

code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. Burst interrupt shown on first allowable clock (i.e., after first data word written).

3. CE# can stay LOW between burst operations, but CE# must not remain LOW longer than tCEM.

A[22:0] VIH

VIL

ADV# VIH

VIL

CE# VIH

VIL

OE#

2nd Cycle WRITE

VIH

VIL

OE#

2nd Cycle READ

VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0] IN

2nd Cycle WRITE

DQ[15:0] OUT

2nd Cycle READ

VOH

VOL

CLK VIH

VIL

VIH

VIL

tCLK

tSP

tCSP

D[0]

VALID

ADDRESS

tHD

tSP

tHD

tSP

VALID

ADDRESS

tHD

High-Z

LB#/UB#

2nd Cycle WRITE

LB#/UB#

2nd Cycle READ

VIH

VIL

VIH

VIL

tSP tHD

High-Z

UNDEFINED

DON’T CARE

tHD

D[2] D[3]D[1]

D[0]

tHD

tSP

High-Z

tHD tSP

tOHZ

tBOE

tKOH

tACLK

VALID

OUTPUT

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

High-Z

VOH

VOL

VOH

VOL

tKHTL

WRITE Burst interrupted with new WRITE or READ. See Note 2.

VALID

ADDRESS

tCEM (NOTE 3)

tKADV

tAVH tAVH

tHD

Table 42: WRITE Timing Parameters—Burst READ Interrupted

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tAVH 222ns

tKADV 466ns

tCLK 9.62 20 12.5 20 15 20 ns tKHTL 7911ns

tCSP 3 20420520ns tSP 3 3 3 ns

tHD 222ns

Table 43: READ Timing Parameters—Burst READ Interrupted

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 7911ns

tHD 222ns

tBOE 20 20 20 ns tKOH 2 2 2 ns

tCLK 9.62 12.5 15 ns tOHZ 8 8 8 ns

tCSP 345ns

tSP 333ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 50: Asynchronous WRITE Followed by Burst READ

NOTE:

1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Fixed or variable latency; latency code two

(three clocks); WAIT active LOW; WAIT asserted during delay.

2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW

when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportu-

nity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.

tCLK

tSP tHD

tSP

VALID

ADDRESS

tOHZ

tKOH

tACLK

High-Z

VALID ADDRESS VALID ADDRESS

tAVS tAVH tAW tWR

tVP tVS

A[22:0] VIH

VIL

ADV# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL

VOH

VOL

CE# VIH

VIL

LB#/UB# VIH

VIL

tCW

tCVS

tWPH

tAS

tWP

tWC

tDH tDW

DATA DATA

High-Z

tHD

tSP

tCEW

tSP tHD

tCSP

tWC

tBW

VALID

OUTPUT VALID

OUTPUT

VALID

OUTPUT

DON’T CARE UNDEFINED

tHD

tBOE

tCBPH

tVPH

NOTE 2

Table 44: WRITE Timing Parameters—Async WRITE Followed by Burst READ

SYMBOL

-701/708 -856

UNITS SYMBOL

-701/708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAVH 22ns

tDW 20 20 ns

tAS 00ns

tVP 57ns

tAVS 55ns

tVPH 10 10 ns

tAW 70 85 ns tVS 70 85 ns

tBW 70 85 ns tWC 70 85 ns

tCVS 77ns

tWP 45 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 0 0 ns

tWR 0 0 ns

Table 45: READ Timing Parameters—Async WRITE Followed by Burst READ

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 7911ns

tCSP 3 4 5 ns

tBOE 20 20 20 ns tHD 2 2 2 ns

tCBPH 5 6 8 ns

tKOH 2 2 2 ns

tCEW 1 7.5 1 7.5 1 7.5 ns tOHZ 888 ns

tCLK 9.62 12.5 15 ns

tSP 3 3 3 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 51: Asynchronous WRITE (ADV# LOW) Followed By Burst READ

NOTE:

1. Non-default BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: Fixed or variable latency;

latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW

when transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportu-

nity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.

tCLK

tSP tHD

tHD

VALID

ADDRESS

tCSP

tKOH

tACLK

VALID

OUTPUT

High-Z

VALID ADDRESS VALID ADDRESS

A[22:0] VIH

VIL

ADV# VIH

VIL

OE# VIH

VIL

WE# VIH

VIL

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

CLK VIH

VIL

VIH

VIL

VOH

VOL

CE# VIH

VIL

LB#/UB# VIH

VIL

tCW

tWPH

tWP

tWC

tDH tDW

DATA DATA

High-Z

tHD

tSP

tSP tHD

tWC tWC

tBW

tAW tWR

tSP

VALID

OUTPUT VALID

OUTPUT

UNDEFINED

DON’T CARE

tBOE

tOHZ

tCEW

tCBPH

High-Z

NOTE 2

Table 46: Asynchronous WRITE Timing Parameters—ADV# LOW

SYMBOL

-701/708 -856

UNITS SYMBOL

-701/708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAW 70 85 ns tWC 70 85 ns

tBW 70 85 ns tWP 45 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 00ns

tWR 0 0 ns

tDW 20 20 ns

Table 47: Burst READ Timing Parameters

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 7911ns

tCSP 345ns

tBOE 20 20 20 ns tHD 222ns

tCBPH 5 6 8 ns

tKOH 2 2 2 ns

tCEW 17.517.517.5ns tOHZ 888 ns

tCLK 9.62 12.5 15 ns

tSP 333ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 52: Burst READ Followed by Asynchronous WRITE (WE#-Controlled)

NOTE:

1. Non-default BCR settings for burst READ followed by asynchronous WE#-controlled WRITE: Fixed or variable latency; latency code two (three

clocks); WAIT active LOW; WAIT asserted during delay.

2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from

fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every tCEM.

A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.

A[22:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

VIH

VIL

CLK

ACLK

CEW

tCW

VALID

OUTPUT

VALID

ADDRESS

High-Z

KOH

OHZ

LB#/UB#

VIH

VIL

CSP

High-Z

OLZ

WPH

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

KHTL

BOE

VALID

ADDRESS

VALID

INPUT

High-Z

CEW

CBPH

NOTE 2

Table 48: Burst READ Timing Parameters

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 79 11ns tHD 222ns

tBOE 20 20 20 ns tHZ 8 8 8 ns

tCBPH 568ns

tKHTL 7911ns

tCEW 17.517.517.5ns tKOH 2 2 2 ns

tCLK 9.62 12.5 15 ns

tOHZ 8 8 8 ns

tCSP 345ns

tSP 333ns

Table 49: Asynchronous WRITE Timing Parameters—WE# Controlled

SYMBOL

-701/-708 -856

UNITS SYMBOL

-701/-708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tHZ 88ns

tAW 70 85 ns tWC 70 85 ns

tBW 70 85 ns tWP 45 55 ns

tCW 70 85 ns tWPH 10 10 ns

tDH 00ns

tWR 0 0 ns

tDW 20 20 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 53: Burst READ Followed by Asynchronous WRITE Using ADV#

NOTE:

1. Non-default BCR settings for burst READ followed by asynchronous WRITE using ADV#: Fixed or variable latency; latency code two (three

clocks); WAIT active LOW; WAIT asserted during delay.

2. When transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when transitioning from

fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity must be provided every tCEM.

A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.

A[22:0]

VIH

VIL

ADV#

VIH

VIL

CE#

VIH

VIL

OE#

VIH

VIL

WE#

VIH

VIL

WAIT

DQ[15:0]

VOH

VOL

CLK

VIH

VIL

VOH

VOL

CLK

CEW

VPH

AVS

AVH

tCW

VALID

OUTPUT

VALID

ADDRESS

High-Z

KOH

OHZ

LB#/UB#

VIH

VIL

CSP

High-Z

OLZ

WPH

UNDEFINED

DON’T CARE

READ Burst Identified

(WE# = HIGH)

KHTL

VALID

ADDRESS

VALID

INPUT

High-Z

CEW

CBPH

ACLK

BOE

NOTE 2

VIH

VIL

Table 50: Burst READ Timing Parameters

SYMBOL

-701 -708 -856

UNITS SYMBOL

-701 -708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tACLK 79 11ns tHD 222ns

tBOE 20 20 20 ns tHZ 8 8 8 ns

tCBPH 568ns

tKHTL 7911ns

tCEW 17.517.517.5ns tKOH 2 2 2 ns

tCLK 9.62 12.5 15 ns

tOHZ 8 8 8 ns

tCSP 345ns

tSP 333ns

Table 51: Asynchronous WRITE Timing Parameters Using ADV#

SYMBOL

-701/-708 -856

UNITS SYMBOL

-701/-708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tDW 20 20 ns

tAVH 22ns

tHZ 88ns

tAVS 55ns

tVP 57ns

tAW 70 85 ns

tVPH 10 10 ns

tBW 70 85 ns

tVS 70 85 ns

tCEW 1 7.5 1 7.5 ns tWP 45 55 ns

tCW 70 85 ns

tWPH 10 10 ns

tDH 0 0 ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 54: Asynchronous WRITE Followed by Asynchronous READ—ADV# LOW

NOTE:

1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the

appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs.

VALID ADDRESS VALID ADDRESS

A[22:0] VIH

VIL

ADV#

VIH

VIL

OE#

WE#

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB# VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCW

tWPH

tWP

tAS

tWC

tDH tDW

DATA

High-Z

VALID ADDRESS

tAA

tBHZ

tCPH

VALID

OUTPUT

High-Z

tOE

tOLZ

tLZ

tBLZ

tOHZ

tHZ

tAW tWR

tBW

tWHZ

tHZ tHZ

DON’T CARE UNDEFINED

DATA

NOTE 1

Table 52: WRITE Timing Parameters—ADV# LOW

SYMBOL

-701/-708 -856

UNITS SYMBOL

-701/-708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tHZ 88ns

tAW 70 85 ns

tWC 70 85 ns

tBW 70 85 ns tWHZ 88 ns

tCPH 55ns

tWP 45 55 ns

tCW 70 85 ns

tWPH 10 10 ns

tDH 0 0 ns

tWR 0 0 ns

tDW 20 20 ns

Table 53: READ Timing Parameters—ADV# LOW

SYMBOL

-701/-708 -856

UNITS SYMBOL

-701/-708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tLZ 10 10 ns

tBHZ 88 ns tOE 20 20 ns

tBLZ 10 10 ns

tOHZ 88 ns

tHZ 88 ns tOLZ 33ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 55: Asynchronous WRITE Followed by Asynchronous READ

NOTE:

1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the

appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs.

VALID ADDRESS VALID ADDRESS

tAVS tAVH

tVPH tVP tVS

A[22:0] VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADV#

OE#

WE#

WAIT

DQ[15:0]

IN/OUT

VOH

VOL

VIH

VIL

VOH

VOL

CE#

LB#/UB#

tCW

tWPH

tAS tWP

tWC

tDH tDW

DATA DATA

High-Z

VALID ADDRESS

tAA

tBHZ

tCPH

VALID

OUTPUT

High-Z

tCVS

tOLZ

tLZ

tAS

tBLZ

tOHZ

tHZ

tAW tWR

tBW

tWHZ

UNDEFINED

DON’T CARE

tOE

NOTE 1

Table 54: WRITE Timing Parameters—Async WRITE Followed by Async READ

SYMBOL

-701/-708 -856

UNITS SYMBOL

-701/-708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAS 00ns

tDW 20 20 ns

tAVH 22ns

tVP 57ns

tAVS 55ns

tVPH 10 10 ns

tAW 70 85 ns

tVS 70 85 ns

tBW 70 85 ns tWC 70 85 ns

tCPH 55ns

tWHZ 88ns

tCVS 77ns

tWP 45 55 ns

tCW 70 85 ns

tWPH 10 10 ns

tDH 00ns

tWR 00ns

Table 55: READ Timing Parameters—Async WRITE Followed by Async READ

SYMBOL

-701/-708 -856

UNITS SYMBOL

-701/-708 -856

UNITSMIN MAX MIN MAX MIN MAX MIN MAX

tAA 70 85 ns

tLZ 10 10 ns

tBHZ 88 ns tOE 20 20 ns

tBLZ 10 10 ns

tOHZ 88 ns

tHZ 88 ns tOLZ 33ns

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

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E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S.

All other trademarks are the property of their respective owners.

Figure 56: 54-Ball VFBGA

NOTE:

1. All dimensions in millimeters; MAX/MIN, or typical, as noted.

Data Sheet Designation: Production

Released: This data sheet contains minimum and

maximum limits specified over the complete power

supply and temperature range for production devices.

Although considered final, these specifications are

subject to change, as further product development

and data characterization sometimes occur.

BALL A1 ID

1.00 MAX

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

SOLDER BALL MATERIAL: 96.5% Sn, 3% Ag, 0.5% Cu

SOLDER BALL PAD: Ø 0.30 SOLDER MASK DEFINED

BALL A6 BALL A1

8.00 ±0.10

4.00 ±0.051.875 ±0.05

BALL A1 ID

54X Ø 0.37

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER IS Ø 0.35

0.75 TYP

5.00 ±0.05

3.00 ±0.05

6.00

10.00 ±0.10

0.70 ±0.05

0.10 C C

SEATING PLANE

3.75

0.75 TYP

8 MEG x 16

ASYNC/PAGE/BURST CellularRAM 1.5 MEMORY

09005aef80ec6f79 pdf/09005aef80ec6f65 zip Micron Technology, Inc., reserves the right to change products or specifications without notice.

Revision History

Rev. D, Production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/05

•Clarified

tKADV operation in fixed latency; removed

it from Figure 48 and Table 40 on page 55.

• Added Figure 29, DPD Entry and Exit Timing

Parameters, on page 36.

•Added

tDPD and tDPDX to Table 19 on page 36.

•Changed I

CC specifications to match workgroup

specifications.

• Deleted 4-word burst READ operation with LB#/

UB# timing diagram and parameters table.

• Clarified end-of-row and start-of-row addressing

and vendor-based differences in CellularRAM

device operation—Figure 45 on page 52—diagram

and Note 4.

•Updated I

TCR chart.

Rev. C, Production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/04

• Changed status to Production.

•Added

tACLK to first data output on fixed latency

READ diagrams.

• Noted CE# must stay LOW for at least 10µs when

exiting DPD.

• Updated LB#/UB# in timing diagrams, and clarified

LB#/UB# operation across Workgroup devices.

•Clarified I

SB operation.

• Modified Figure 25 on page 30 to support non-color

printout.

•Added to tCEW definition and updated related

diagrams.

• Clarified CE# LOW between burst operations.

• Updated ADV# LOW and WAIT relative to burst

interrupts, and corrected interrupt latency in

diagrams.

• Clarified VSSQ in Figure 26 on page 31.

• Clarified end-of-row operation and added Note 4 to

Figure 45 on page 52.

Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/04

• Clarified CRE access.

•Changed

tCBPH to tCPH in Figures Figure 12 on

page 16 and Figure 13 on page 16.

•Added V

IH, VIL for register READ operation followed

by READ ARRAY operation, and burst READ

followed by async WRITE in Figures 52 and 53

respectively.

• Defined the beginning of asynchronous operation

for each figure.

• Adjusted valid address in Figure 23 on page 25.

Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/04

• Initial release.