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FEATURES
See mechanical drawings for dimensions.
DBV PACKAGE
(TOP VIEW)
2
GND VCC
5
34
B1 A
6
1
B2 S
DCK PACKAGE
(TOP VIEW)
34
B1
2
GND
A
5
1
B2
VCC
6S
DRL PACKAGE
(TOP VIEW)
2
GND VCC
5
1
B2
34
B1 A
6S
YZP PACKAGE
(BOTTOM VIEW)
2
GND VCC
1
5
B2
B1 4
3A
6S
DRY PACKAGE
(TOP VIEW)
GND VCC
B2 6
5
4
2
3
B1 A
S
1
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G3157SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
Low On-State Resistance, Typically 6(V
CC
= 4.5 V)1.65-V to 5.5-V V
CC
Operation
Latch-Up Performance Exceeds 100 mA PerUseful for Both Analog and Digital
JESD 78, Class IIApplications
ESD Protection Exceeds JESD 22Specified Break-Before-Make Switching
2000-V Human-Body Model (A114-A)Rail-to-Rail Signal Handling
200-V Machine Model (A115-A)High Degree of Linearity
1000-V Charged-Device Model (C101)High Speed, Typically 0.5 ns(V
CC
= 3 V, C
L
= 50 pF)
This single-pole, double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes ofup to V
CC
(peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing foranalog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(2)
NanoFree™ WCSP (DSBGA)
Reel of 3000 SN74LVC1G3157YZPR _ _ _ C5_0.23-mm Large Bump YZP (Pb-free)SON DRY Reel of 5000 SN74LVC1G3157DRYR C5_–40 °C to 85 °C
SOT (SOT-23) DBV Reel of 3000 SN74LVC1G3157DBVR CC5_SOT (SC-70) DCK Reel of 3000 SN74LVC1G3157DCKR C5_SOT (SOT-553) DRL Reel of 4000 SN74LVC1G3157DRLR C5_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
(2) DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one followingcharacter to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
B2
S
1
4
6
A
3
B1
Absolute Maximum Ratings
(1)
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
FUNCTION TABLE
CONTROL
ONINPUT
CHANNELS
L B1H B2
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range
(2)
–0.5 6.5 VV
IN
Control input voltage range
(2) (3)
–0.5 6.5 VV
I/O
Switch I/O voltage range
(2) (3) (4) (5)
–0.5 V
CC
+ 0.5 VI
IK
Control input clamp current V
IN
< 0 –50 mAI
IOK
I/O port diode current V
I/O
< 0 or V
I/O
> V
CC
±50 mAI
I/O
On-state switch current
(6)
V
I/O
= 0 to V
CC
±128 mAContinuous current through V
CC
or GND ±100 mADBV package 165DCK package 259θ
JA
Package thermal impedance
(7)
DRL package 142 °C/WDRY package 234YZP package 123T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to ground unless otherwise specified.(3) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(4) This value is limited to 5.5 V maximum.(5) V
I
, V
O
, V
A
, and V
Bn
are used to denote specific conditions for V
I/O
.(6) I
I
, I
O
, I
A
, and I
Bn
are used to denote specific conditions for I
I/O
.(7) The package thermal impedance is calculated in accordance with JESD 51-7.
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Recommended Operating Conditions
(1)
Electrical Characteristics
SN74LVC1G3157SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
MIN MAX UNIT
V
CC
1.65 5.5 VV
I/O
0 V
CC
VV
IN
0 5.5 VV
CC
= 1.65 V to 1.95 V V
CC
×0.75V
IH
High-level input voltage, control input VV
CC
= 2.3 V to 5.5 V V
CC
×0.7V
CC
= 1.65 V to 1.95 V V
CC
×0.25V
IL
Low-level input voltage, control input VV
CC
= 2.3 V to 5.5 V V
CC
×0.3V
CC
= 1.65 V to 1.95 V 20V
CC
= 2.3 V to 2.7 V 20t/ v Input transition rise or fall rate ns/VV
CC
= 3 V to 3.6 V 10V
CC
= 4.5 V to 5.5 V 10T
A
Operating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
I
= 0 V I
O
= 4 mA 11 201.65 VV
I
= 1.65 V I
O
= –4 mA 15 50V
I
= 0 V I
O
= 8 mA 8 122.3 VV
I
= 2.3 V I
O
= –8 mA 11 30See Figure 1 andr
on
On-state switch resistance
(2)
V
I
= 0 V I
O
= 24 mA 7 9 Figure 2
3 VV
I
= 3 V I
O
= –24 mA 9 20V
I
= 0 V I
O
= 30 mA 6 7V
I
= 2.4 V I
O
= –30 mA 4.5 V 7 12V
I
= 4.5 V I
O
= –30 mA 7 15I
A
= –4 mA 1.65 V 140I
A
= –8 mA 2.3 V 45On-state switch resistance 0 V
Bn
V
CCr
range
over signal range
(2) (3)
(see Figure 1 and Figure 2 )
I
A
= –24 mA 3 V 18I
A
= –30 mA 4.5 V 10V
Bn
= 1.15
I
A
= –4 mA 1.65 V 0.5VDifference of on-state
V
Bn
= 1.6 V I
A
= –8 mA 2.3 V 0.1r
on
resistance between See Figure 1 V
Bn
= 2.1 V I
A
= –24 mA 3 V 0.1switches
(2) (4) (5)
V
Bn
= 3.15
I
A
= –30 mA 4.5 V 0.1V
I
A
= –4 mA 1.65 V 110I
A
= –8 mA 2.3 V 26r
on(flat)
ON resistance flatness
(2) (4) (6)
0V
Bn
V
CC
I
A
= –24 mA 3 V 9I
A
= –30 mA 4.5 V 4
(1) T
A
= 25 °C(2) Measured by the voltage drop between I/O pins at the indicated current through the switch. ON resistance is determined by the lower ofthe voltages on the two (A or B) ports.(3) Specified by design(4) r
on
= r
on(max)
r
on(min)
measured at identical V
CC
, temperature, and voltage levels(5) This parameter is characterized, but not tested in production.(6) Flatness is defined as the difference between the maximum and minimum values of ON resistance over the specified range ofconditions.
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
Electrical Characteristics (continued)over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
±1Off-state switch leakage 0 V
I
, V
O
V
CC
1.65 V toI
off
(7)
µAcurrent (see Figure 3 ) 5.5 V
±0.05 ±1
(1)
±1On-state switch leakage V
I
= V
CC
or GND, V
O
= OpenI
S(on)
5.5 V µAcurrent (see Figure 4 )
±0.1
(1)
±10 V toI
IN
Control input current 0 V
IN
V
CC
µA5.5 V
±0.05 ±1
(1)
I
CC
Supply current V
IN
= V
CC
or GND 5.5 V 1 10 µAI
CC
Supply-current change V
IN
= V
CC
0.6 V 5.5 V 500 µAControl inputC
in
S 5 V 2.7 pFcapacitance
Switch input/ouputC
io(off)
Bn 5 V 5.2 pFcapacitance
Bn 17.3Switch input/ouputC
io(on)
5 V pFcapacitance
A 17.3
(7) I
off
is the same as I
S(off)
(off-state switch leakage current).
4
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Analog Switch Characteristics
Switching Characteristics
SN74LVC1G3157SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
T
A
= 25 °C
FROM TOPARAMETER TEST CONDITIONS V
CC
TYP UNIT(INPUT) (OUTPUT)
1.65 V 300Frequency R
L
= 50 ,
2.3 V 300response
(1)
A or Bn Bn or A f
in
= sine wave MHz3 V 300(switch on) (see Figure 6 )
4.5 V 3001.65 V –54Crosstalk
(2)
R
L
= 50 ,
2.3 V –54(between B1 or B2 B2 or B1 f
in
= 10 MHz (sine wave) dB3 V –54switches) (see Figure 7 )
4.5 V –541.65 V –57Feed-through C
L
= 5 pF, R
L
= 50 ,
2.3 V –57attenuation
(2)
A or Bn Bn or A f
in
= 10 MHz (sine wave) dB3 V –57(switch off) (see Figure 8 )
4.5 V –573.3 V 3C
L
= 0.1 nF, R
L
= 1 M Charge injection
(3)
S A pC(see Figure 9 )
5 V 71.65 V 0.1V
I
= 0.5 Vp-p, R
L
= 600 ,
2.3 V 0.025Total harmonic
A or Bn Bn or A f
in
= 600 Hz to 20 kHz (sine wave) %distortion
3 V 0.015(see Figure 10 )
4.5 V 0.01
(1) Adjust f
in
voltage to obtain 0 dBm at output. Increase f
in
frequency until dB meter reads –3 dB.(2) Adjust f
in
voltage to obtain 0 dBm at input.(3) Specified by design
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5 and Figure 11 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VFROM TO
±0.15 V ±0.2 V ±0.3 V ±0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
(1)
A or Bn Bn or A 2 1.2 0.8 0.3 nst
en
(2)
7 24 3.5 14 2.5 7.6 1.7 5.7S Bn nst
dis
(3)
3 13 2 7.5 1.5 5.3 0.8 3.8t
B-M
(4)
0.5 0.5 0.5 0.5 ns
(1) t
pd
is the slower of t
PLH
or t
PHL
. The propagation delay is calculated RC time constant of the typical on-state resistance of the switch andthe specified load capacitance when driven by an ideal voltage source (zero output impedance).(2) t
en
is the slower of t
PZL
or t
PZH
.(3) t
di
s is the slower of t
PLZ
or t
PHZ
.(4) Specified by design
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PARAMETER MEASUREMENT INFORMATION
V V
I O
ron =Ω
IO
0
20
40
60
80
100
120
0 1 2 3 4 5
on
r
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
VCC = 4.5 V
VI- V
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
Figure 1. On-State Resistance Test Circuit
Figure 2. Typical r
on
as a Function of Input Voltage (V
I
) for V
I
= 0 to V
CC
6
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SW
1
2
S
VIL
VIH
B1
B2
S
A
VCC
VCC
SW
1
2
GND
VIL or VIH
VO
VIA
VO= Open
VI= VCC or GND
SN74LVC1G3157SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Off-State Switch Leakage-Current Test Circuit
Figure 4. On-State Switch Leakage-Current Test Circuit
7Submit Documentation Feedback
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th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
500 W
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
2×VCC
2× VCC
VLOAD CL
50pF
50pF
50pF
50pF
0.3V
0.3V
0.3V
0.3V
VD
VCC
VI
VCC/2
VCC/2
V /2
CC
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 5. Load Circuit and Voltage Waveforms
8
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B1
B2
S
A
VCC
VCC
GND
50
VIL or VIH VB1
fin
VB2 Analyzer
S
VIL
VIH
TEST CONDITION
20log10(VO2/VI)
20log10(VO1/VI)
RL= 50
RL
SN74LVC1G3157SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 6. Frequency Response (Switch On)
Figure 7. Crosstalk (Between Switches)
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B1
B2
RL
S
A
VOUT
CLRL/CL= 1 M/100 pF
VOUT
VCC
VCC
SW
1
2
RGEN
GND
LOGIC
INPUT
LOGIC
INPUT OFF OFFON
Q = (VOUT) (CL)
VOUT
VGE
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Feedthrough
Figure 9. Charge-Injection Test
10
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600
10k
VI= VCC/2
B1
B2
RL
S
A
VO
CLRL/CL= 50 /35 pF
0.9 x VO
VO
tD
VS
VCC
VCC
GND
SN74LVC1G3157SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424F JANUARY 2003 REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 10. Total Harmonic Distortion
Figure 11. Break-Before-Make Internal Timing
11Submit Documentation Feedback
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
74LVC1G3157DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVC1G3157DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVC1G3157DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVC1G3157DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVC1G3157DRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVC1G3157DRYRG4 ACTIVE SON DRY 6 5000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G3157DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G3157DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G3157DGVR PREVIEW SOT-23 DBV 6 TBD Call TI Call TI
SN74LVC1G3157DRLR ACTIVE SOT DRL 6 4000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G3157DRYR ACTIVE SON DRY 6 5000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G3157YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS &
no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jan-2009
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G3157 :
Automotive: SN74LVC1G3157-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jan-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G3157DBVR SOT-23 DBV 6 3000 180.0 9.2 3.23 3.17 1.37 4.0 8.0 Q3
SN74LVC1G3157DCKR SC70 DCK 6 3000 180.0 8.4 2.24 2.34 1.22 4.0 8.0 Q3
SN74LVC1G3157DCKR SC70 DCK 6 3000 180.0 9.2 2.24 2.34 1.22 4.0 8.0 Q3
SN74LVC1G3157DRLR SOT DRL 6 4000 180.0 9.2 1.78 1.78 0.69 4.0 8.0 Q3
SN74LVC1G3157DRYR SON DRY 6 5000 179.0 8.4 1.2 1.65 0.7 4.0 8.0 Q1
SN74LVC1G3157YZPR DSBGA YZP 6 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Sep-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G3157DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0
SN74LVC1G3157DCKR SC70 DCK 6 3000 202.0 201.0 28.0
SN74LVC1G3157DCKR SC70 DCK 6 3000 205.0 200.0 33.0
SN74LVC1G3157DRLR SOT DRL 6 4000 202.0 201.0 28.0
SN74LVC1G3157DRYR SON DRY 6 5000 220.0 205.0 50.0
SN74LVC1G3157YZPR DSBGA YZP 6 3000 220.0 220.0 34.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Sep-2009
Pack Materials-Page 2