Si9120
Vishay Siliconix
FaxBack 408-970-5600, request 70006 S-60752—Rev. F, 05-Apr-99
www.siliconix.com 1
Universal Input Switchmode Controller
FEATURES
DESCRIPTION
The Si9120 is a BiC/DMOS integrated circuit designed for
use in low-power, high-efficiency off-line power supplies.
High-voltage DMOS inputs allow the controller to work over a
wide range of input voltages (10- to 450-VDC). Current-mode
PWM control circuitry is implemented in CMOS to reduce
quiescent current to less than 1.5 mA.
A CMOS output driver provides high-speed switching for
MOSFET devices with gate charge, Qg, up to 25 nC, enough
to supply 30 W of output power at 100 kHz. These devices,
when com bi ned w ith an ou tpu t M OSF ET an d tr a ns former, can
be used to implement single-ended power converter
topologies (i.e., flyback and forward).
The Si9120 is available in a 16-pin plastic DIP and SOIC
packages, and is specified over the industrial, D suffix (-40 to
85°C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
• 10- to 450-V Input Range
• Current-Mode Control • 125-mA Output Drive
• Internal Start-Up Circuit • Internal Oscillator (1 MHz)
• SHUTDOWN and RESET
Applications information may also be obtained via FaxBack, request document #70580 and #70578.
Si9120Off-Line Power
Si9120
Vishay Siliconix
S-60752—Rev. F, 05-Apr-99 FaxBack 408-970-5600, request 70006
2 www.siliconix.com
ABSOLUTE MAXIMUM RATINGS
Voltages Ref erenced to -VIN (Note: VCC < +VIN + 0.3 V)
VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 V
+VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450 V
Logic Inputs (RESET
SHUTDOWN, OSC IN, OSC OUT). . . . . . . . . . .-0.3 V to VCC + 0.3 V
Linear Input
(FEEDBACK, SE NSE , BI AS, VREF) . . . . . . . . . . . . . . . . .-0.3 V to 7 V
HV Pre-Regulator Input Current (continuous). . . . . . . . . . . . . . .5 mAa
Continuous Output Current (Source or Sink) . . . . . . . . . . . . . 125 mA
Storage Temperat ure . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Power Dissipation (Package)b
16-Pin Plastic DIP (J Suffix)c. . . . . . . . . . . . . . . . . . . . . . . . . 750 mW
16-Pin SOIC (Y Suffix)d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW
Thermal Impedance (ΘJA)
16-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167°C/W
16-Pin SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140°C/W
Notes
a. Continuous current may be limited by the applications maximum
input voltage and the package power dissipation.
b. Device mounted with all leads soldered or welded to PC board.
c. Derate 6 mW/°C above 25°C.
d. Derate 7.2 mW/°C above 25°C.
RECOMMENDED OPERATING RANGE
Voltages Ref erenced to -VIN
VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.5 V to 1 3 . 5 V
+VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 V to 450 V
fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz
ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kΩ to 1 MΩ
Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC - 3 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
SPECIFICATIONSa
Parameter Symbol
Test Conditions
Unless Specified
DISCHARGE = -VIN = 0 V,
VCC = 10 V +VIN = 300 V
RBIAS = 390 kΩ, ROSC = 330 kΩTempb
Limits
D Suffix -40 to 85°C
UnitMincTypdMaxc
Reference
Output Voltage VROSC IN = - VIN (OSC Disabled)
RL = 10 MΩRoom
Full 3.88
3.82 4.0 4.12
4.14 V
Output ImpedanceeZOUT Room 15 30 45 kΩ
Short Circuit Current ISREF VREF = -VIN Room 70 100 130 µA
Temperature StabilityeTREF Full 0.5 1.0 mV/°C
Oscillator
Maximum FrequencyefMAX ROSC = 0 Room 1 3 MHz
Initial Accuracy fOSC CSTRAY Pin 9 ≤ 5 pF, ROSC = 330 kΩRoom 80 100 120 kHz
CSTRAY Pin 9 ≤ 5 pF, ROSC = 150 kΩRoom 160 200 240
Voltage Stability ∆f/f ∆f/f = f(13.5 V) - f(9.5 V) / f(9.5 V) Room 10 15 %
Temperature CoefficienteTOSC Full 200 500 ppm/°C
Error Amplifier
Feedback Input Voltage VFB FB Tied to COMP
OSC IN = - VIN (OSC Disabled) Room 3.92 4.08 V
Input BIAS Current IFB OSC IN = - VIN, V FB = 4 V Room 25 500 nA
Input OFFSET Voltage VOS OSC IN = - VIN Room ±15 ±40 mV
Open Loop Voltage GaineAVOL OSC IN = - VIN Room 60 80 dB
Unity Gain BandwidtheBW OSC IN = - VIN Room 1.0 1.5 MHz
Dynamic Output ImpedanceeZOUT Error Amp configured for 60 dB gain Room 1000 2000 Ω
Output Current IOUT Source VFB = 3.4 V Room -2.0 -1.4 mA
Sin k VFB = 4.5 V Room 0.12 0.15
Power Supply Rejection PSRR 9.5 V ≤ VCC ≤ 13.5 V Room 50 70 dB
Si9120
Vishay Siliconix
FaxBack 408-970-5600, request 70006 S-60752—Rev. F, 05-Apr-99
www.siliconix.com 3
Notes
a. Refer to PROCESS OPTION FLOWCHART for additional infor m ation.
b . Room = 25°C, Cold and Hot = as determined by the operating temperature suffix.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
e. Guaranteed by design, not subject to production test.
f. 250V ≤ +VIN ≤ 380V place a 10 kΩ, ¼ W resistor in series with +VIN (Pin 1).
380V ≤ +VIN ≤ 450V place a 15 kΩ, ¼ W resistor in series with +VIN (Pin 1).
Connect a 0.01 µƒd capacitor between +VIN (Pin 1) and -VIN (Pin 6).
Current Limit
Threshold Voltage VSOURCE VFB = 0 V Room 1.0 1.2 1.4 V
Dela y to OutputetdVSENSE = 1.5 V, See Figure 1. Room 100 150 ns
Pre-regulator/Start-up
Input Voltagef+VIN IIN = 10 µA Room 450 V
Input Leakage Current +IIN VCC ≥ 9.4 V Room 10 µA
VCC Pre-Regulator Turn-Off
Threshold Voltage VREG IPRE-REGULATOR = 10 µA Room 7.8 8.6 9.4
V
Underv oltage Lockout VUVLO Room 7.0 8.1 8.9
VREG -VUVLO VDELTA Room 0.3 0.6
Supply
Supply Current ICC CL = 500 pF at Pin 5 Room 0.85 1.5 mA
Bias Current IBIAS Room 10 15 20 µA
Logic
SHUTDOWN DelayetSD CL = 500 pF, VSENSE = -VIN
See Figure 2. Room 50 100
ns
SHUTDOWN Pulse WidthetSW
See Figure 3.
Room 50
RESET Pulse WidthetRW Room 50
Latching Pulse Width
SHUTDOWN and RESET
LowetLW Room 25
Input Low Voltage VIL Room 2.0 V
Input High Voltage VIH Room 8.0
Input Current Input Voltage
High IIH VIN = 10 V Room 1 5 µA
Input Current Input Voltage
Low IIL VIN = 0 V Room -35 -25
Output
Output High Voltage VOH IOUT = -10 mA Room
Full 9.7
9.5 V
Output Low Voltage VOL IOUT = 10 mA Room
Full 0.3
0.5
Output Resistance ROUT IOUT = 10 mA, Source or Sink Room
Full 20
25 30
50 Ω
Rise TimeetrCL = 500 pF Room 40 75 ns
Fa ll T imeetfRoom 40 75
SPECIFICATIONSa
Parameter Symbol
Test Conditions
Unless Specified
DISCHARGE = -VIN = 0 V,
VCC = 10 V +VIN = 300 V
RBIAS = 390 kΩ, ROSC = 330 kΩTempb
Limits
D Suffix -40 to 85°C
UnitMincTypdMaxc
Si9120
Vishay Siliconix
S-60752—Rev. F, 05-Apr-99 FaxBack 408-970-5600, request 70006
4 www.siliconix.com
TIMING WAVEFORMS
FIGURE 1. FIGURE 2.
FIGURE 3.
TYPICAL CHARACTERISTICS
FIGURE 4.
Si9120
Vishay Siliconix
FaxBack 408-970-5600, request 70006 S-60752—Rev. F, 05-Apr-99
www.siliconix.com 5
PIN CONFIGURATIONS
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section
Due to the low quiescent current requirement of the Si9120
control circuitry, bias power can be supplied from the
unregulated input power source, from an external regulated
low -voltage suppl y, or from an auxiliary “bootstra p” win ding on
the output inductor or transformer.
When power is first applied during start-up, +VIN (pin 1) will
draw a constant current. The magnitude of this current is
determined by a high-voltage depletion MOSFET which is
connected between +VIN and VCC (pin 7). This start-up
circuitry provides initial power to the IC by charging an
external bypass capacitance connected to the VCC pin. The
constant current is disabled when VCC exceeds 8.6 V.
If VCC is not forced to exceed the 8.6-V threshold, then VCC
will be regulated to a nominal value of 8.6 V by the
pre-regulator circuit.
As the supply voltage rises toward the normal operating
conditio ns, an internal undervoltage (U V) lockout circuit k eep s
the output driver disabled until VCC exceeds the undervoltage
lockout threshold (typically 8.1 V). This guarantees that the
control logic will be functioning properly and that sufficient
gate drive voltage is available before the MOSFET turns on.
The design of the IC is such that the undervoltage lockout
threshold will be at least 300 mV less than the pre-regulator
turn-off voltage. Power dissipation can be minimized by
providing an external power source to VCC such that the
constant current source is always disabled.
Note: When driving large MOSFETs at high frequency
without a bootstrap VCC supply, power dissipation in the
pre-regulator may exceed the power rating of the IC package.
For operati on of +VIN > 250V a 10 kΩ, ¼ W resistor should be
placed in series with +VIN (Pin 1). For +VIN > 380V a 15 kΩ,
¼ W resistor is recommended.
BIAS
To properly set the bias for the Si9120, a 390-kΩ resistor
should be tied from BIAS (pin 16) to -VIN (pin 6). This
determines the magnitude of bias current in all of the analog
sections and the pull-up current for the SHUTDOWN and
RESET pins. The current flowing in the bias resistor is
nominally 15 µA.
Reference Section
The reference section of the Si9120 consists of a temperature
compensated buried zener and trimmable divider network.
The ou tput o f the referenc e sect ion is co nnecte d inter nally to
the non-inverting input of the error amplifier. Nominal
ref er ence outp ut v olta ge is 4 V. The trimming pro cedure that is
used on the Si9120 brings the output of the error amplifier
(which is configured for unity gain during trimming) to within
±2% of 4 V. This compensates for input offset voltage in the
error amplifier.
The output impedance of the reference section has been
purposely made high so that a low impedance external
voltage source can be used to override the internal voltage
source, if desired, without otherwise altering the performance
of the device.
Error Amplifier
Closed-loop regulation is provided by the error amplifier,
which is intended for use with “around-the-amplifier”
compensation. A MOS differential input stage provides for
high input impedance. The noninverting input to the error
amplifier (VREF) is internally connected to the output of the
reference supply and should be bypassed with a small
capacito r to ground.
Top Vie w
Order Number: Si9120DJ
Top View
Order Number: Si9120DY
Note: Pins 2 and 3 are removed
Si9120
Vishay Siliconix
S-60752—Rev. F, 05-Apr-99 FaxBack 408-970-5600, request 70006
6 www.siliconix.com
Oscillator Section
The oscillator consists of a ring of CMOS inverters,
capac itors , and a cap acitor di scharg e s wit ch. Frequency is set
by an external resistor between the OSC IN and OSC OUT
pins. (See Typical Characteristics for details of resistor value
vs . freq uen cy.) The DISC HA RGE p in sho uld be ti ed to -VIN for
normal inter nal oscillator operation. A frequency divider in the
logic section limits switch duty cycle to ≤50% by locking the
switching frequency to one half of the oscillator frequency.
SHUTDOWN and RESET
SHUTDOWN (pin 12) and RESET (pin 13) are intended for
overriding the output MOSFET switch via external control
logic. The two inputs are fed through a latch preceding the
output switch. Depending on the logic state of RESET.
SHUTDOWN can be either a latched or unlatched input. The
output is off whene ver SHUTDOWN is low . By simultaneously
having SHUTDOWN and RESET low, the latch is set and
SHUTDOWN has no effect until RESET goes high. See
Table 1.
Both pins have internal current source pull-ups and should be
left disconnected when not in use. An added feature of the
current sources is the ability to connect a capacitor and an
open-collector driver to the SHUTDOWN or RESET pins to
provide variable shutdown time.
TABLE 1. Truth Tab le f or SHUTDOWN and RESET Pins
Output Driver
The push-pull driver output has a typical on-resistance of
20-Ω maximum switching times are specified at 75 ns for a
500-pF load. This is sufficient to directly drive MOSFETs
such as the IRF820, BUZ78 or BUZ80. Larger devices can
be driven, but switching times will be longer, resulting in
higher switching losses.
For appli cations information refer to AN707 (FaxBack # 705 80)
and AN708 (FaxBack #70581).
SHUTDOWN RESET Output
H H Normal Operation
H Norm al Operation (No Change)
L H Off (Not Latched)
L L Off (Latched)
L Off (Latched, No Change)
