Intel(R) Advanced+ Boot Block Flash Memory (C3) C3 SCSP Datasheet Product Features Device Architecture -- Flash Density: 16-, 32-Mbit -- Async PSRAM Density: 16-Mbit Device Voltage -- Flash VCC = 3.3 V; Flash VCCQ = 3.3 V -- PSRAM VCC = 3.0 V; Flash VCCQ = 3.0 V Flash Memory Plus PSRAM -- Reduces Memory Board Space Required, Simplifying PCB Design Complexity Device Packaging -- 66 balls (8 x 10 x 1.2 mm) Advanced SRAM Technology -- 70 ns Access Time -- Low Power Operation -- Low Voltage Data Retention Mode Flash Technologies -- 0.25 m ETOXTM VI, 0.18 m ETOXTM VII and 0.13 m ETOXTM VIII Flash Technologies Advanced+ Boot Block Flash Memory -- 70 ns Access Time -- Instant, Individual Block Locking -- 128 bit Protection Register -- 12 V Production Programming -- Fast Program and Erase Suspend -- Extended Temperature -25 C to +85 C Blocking Architecture -- Block Sizes for Code + Data Storage -- 4-Kword Parameter Blocks -- 64-Kbyte Main Blocks -- 100,000 Erase Cycles per Block Low Power Operation -- Asynchronous Read Current: 9 mA (Flash) -- Standby Current: 7 A (Flash) Automatic Power Saving Mode Intel(R) Flash Data Integrator (FDI) Software -- Real-Time Data Storage and Code Execution in the Same Memory Device -- Full Flash File Manager Capability Document Number: 252636-005US February 2007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. 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Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 2 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Contents 1.0 Introduction .............................................................................................................. 6 1.1 Document Conventions ........................................................................................ 6 1.2 Product Overview ................................................................................................ 6 2.0 Functional Overview .................................................................................................. 8 2.1 Block Diagram .................................................................................................... 8 2.2 Memory Map....................................................................................................... 9 2.3 Device ID Table ................................................................................................ 14 3.0 Package Information ............................................................................................... 15 4.0 Ballout and Signal Descriptions ............................................................................... 16 4.1 Ballout ............................................................................................................. 16 4.2 Signal Descriptions ............................................................................................ 16 5.0 Maximum Ratings and Operating Conditions............................................................ 18 5.1 Absolute Maximum Ratings................................................................................. 18 5.2 Operating Conditions ......................................................................................... 18 6.0 Electrical Specifications ........................................................................................... 19 7.0 AC Characteristics ................................................................................................... 23 7.1 Flash AC Characteristics--Read Operations ........................................................... 23 7.2 Flash AC Characteristics--Write Operations ........................................................... 24 7.3 Flash AC Characteristics--Erase and Program Timings ............................................ 25 7.4 Flash AC Characteristics--Reset Operations........................................................... 27 7.5 PSRAM AC Characteristics--Read Operations ......................................................... 27 7.6 PSRAM AC Characteristics--Write Operations......................................................... 29 8.0 Bus Operation.......................................................................................................... 31 8.0.1 Read .................................................................................................... 31 8.0.2 Output Disable ....................................................................................... 32 8.0.3 Standby ................................................................................................ 32 8.0.4 Flash Reset ........................................................................................... 32 8.0.5 Write .................................................................................................... 33 9.0 Flash 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Operations ..................................................................................................... 34 Read Array (FFh)............................................................................................... 34 Read Identifier (90h) ......................................................................................... 34 Read Status Register (70h)................................................................................. 35 9.3.1 Clear Status Register (50h) ..................................................................... 35 CFI Query (98h)................................................................................................ 36 Word Program (40h/10h) ................................................................................... 36 9.5.1 Suspending and Resuming Program (B0h/D0h) .......................................... 37 Block Erase (20h).............................................................................................. 37 9.6.1 Suspending and Resuming Erase (B0h/D0h) .............................................. 38 Block Locking.................................................................................................... 40 9.7.1 Block Locking Operation Summary............................................................ 40 9.7.2 Locked State ......................................................................................... 40 9.7.3 Unlocked State ...................................................................................... 40 9.7.4 Lock-Down State.................................................................................... 41 9.7.5 Reading Lock Status for a Block ............................................................... 41 9.7.6 Locking Operation During Erase Suspend ................................................... 41 9.7.7 Status Register Error Checking ................................................................. 42 128 Bit Protection Register ................................................................................. 42 9.8.1 Reading the Protection Register................................................................ 42 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 3 Intel(R) Advanced+ Boot Block Flash Memory (C3) 9.8.2 9.8.3 Programming the Protection Register (C0h)................................................43 Locking the Protection Register.................................................................43 10.0 Power and Reset Considerations ..............................................................................44 10.1 Power-Up/Down Characteristics ...........................................................................44 10.2 Additional Flash Features ....................................................................................44 10.2.1 Improved 12 Volt Production Programming ................................................44 10.2.2 F-VPP VPPLK for Complete Protection.......................................................44 11.0 Program/Erase Flowcharts ......................................................................................45 12.0 CFI Query Structure .................................................................................................51 12.1 Query Structure Output ......................................................................................51 12.2 Query Structure Overview...................................................................................52 12.3 Block Lock Status Register ..................................................................................52 12.4 CFI Query Identification String ............................................................................53 12.5 System Interface Information ..............................................................................53 12.6 Device Geometry Definition .................................................................................54 12.7 Intel-Specific Extended Query Table .....................................................................55 13.0 Protection Register Addressing ................................................................................58 A Additional Information.............................................................................................59 B Ordering Information ...............................................................................................59 C SRAM Information, Not for New Designs ..................................................................60 Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 4 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Revision History Date Revision 02/11/03 -001 Initial release, Stacked Chip Scale Package 01/29/04 -002 Minor text edits. 03/05 -003 Updated Ordering Information figures and table in Appendix H. 26 Aug 2005 -004 Updated Ordering Information to add PF28F1602C3TD70. 005 Moved SRAM information to an Appendix Added PSRAM information. February 2007 Description February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 5 Intel(R) Advanced+ Boot Block Flash Memory (C3) 1.0 Introduction This document contains the specifications for the Intel(R) Advanced+ Boot Block Flash Memory (C3) Stacked Chip Scale Package (SCSP) device. C3 SCSP memory solutions are offered in the following combinations: * 32-Mbit flash + 16-Mbit PSRAM The Intel(R) Advanced+ Boot Block Flash Memory (C3) Stacked Chip Scale Package (SCSP) device delivers a feature-rich solution for low-power applications. The C3 SCSP memory device incorporates flash memory and PSRAM in one package with low voltage capability to achieve the smallest system memory solution form-factor together with high-speed, low-power operations. The C3 SCSP memory device offers a protection register and flexible block locking to enable next generation security capability. Combined with the Intel(R) Flash Data Integrator (Intel(R) FDI) software, the C3 SCSP memory device provides a cost-effective, flexible, code plus data storage solution. 1.1 Document Conventions Throughout this document, the following conventions have been adopted. * Voltages: -- 2.7 V refers to the full voltage range, 2.7 V-3.3V -- 12 V refers to 11.4 V to 12.6 V * Main block(s): 32-Kword block * Parameter block(s): 4-Kword block * Flash Signal Names: Flash signals names may include an F- prefix. * PSRAM Signal Names: PSRAM signal names may include prefixes: R- or P- (RAM or PSRAM). In Figure 3, "66-Ball SCSP Package Ballout" on page 16 PSRAM signals include an S- prefix because SRAM and PSRAM ballouts are interchangeable. Note: Flash and RAM signal names in Table 6, "Signal Descriptions, NOR Flash" on page 17 and in Table 7, "Signal Descriptions - x16 PSRAM Memory Die" on page 17 respectively are generic and therefore do not include prefixes. 1.2 Product Overview The C3 SCSP device combines flash memory and PSRAM into a single package, which provides secure low-voltage memory solutions for portable applications. The flash memory provides the following features: * Enhanced security. * Instant locking/unlocking of any flash block with zero-latency * A 128-bit protection register that enables unique device identification, to meet the needs of next generation portable applications. * Improved 12 V production programming for increased factory throughput. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 6 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 1. Block Organization (x16) Memory Device Kwords 32-Mbit Flash 2048 16-Mbit PSRAM 1024 Note: All words are 16 bits each. The flash memory is asymmetrically-blocked to enable system integration of code and data storage in a single device. Each flash block can be erased independently of the others up to 100,000 times. The flash memory has eight 8-KB parameter blocks located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map, to accommodate different microprocessor protocols for kernel code location. The remaining flash memory is grouped into 32-Kword main blocks. Any individual flash memory block can be locked or unlocked instantly to provide complete protection for code or data (see Section 7.3, "Flash AC Characteristics--Erase and Program Timings" on page 25 for details). The flash memory contains both a Command User Interface (CUI) and a Write State Machine (WSM). * The CUI is the interface between the microcontroller and the internal operation of the flash memory. * The internal WSM automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. To indicate the status of the WSM, the flash memory status register signifies block erase or word program completion and status. Flash program and erase automation enables executing program and erase operations using an industry-standard two-write command sequence to the CUI. * Program operations are performed in word increments. * Erase operations erase all locations within a block simultaneously. The system software can suspend both program and erase operations to read from any other flash block. In addition, data can be programmed to another flash block during an erase suspend. The C3 SCSP memory device offers two low-power savings features to significantly reduce power consumption: * Automatic Power Savings (APS) for flash memory. The C3 SCSP memory device automatically enters APS mode after a read cycle completes from the flash memory. * Standby mode for flash and PSRAM. This mode is initiated when the system deselects the device by driving F-CE# and P-CS# inactive. To reset the flash memory, lower the F-RP# signal to GND. Setting F-RP# to GND provides CPU memory reset synchronization and additional protection against bus noise that can occur during system reset and power-up/power-down sequences. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 7 Intel(R) Advanced+ Boot Block Flash Memory (C3) 2.0 Functional Overview The flash memory uses a CUI and automated algorithms to simplify program and erase operations. To automate program and erase operations, the WSM handles data and address latches, WE#, and system status requests. 2.1 Block Diagram Figure 1. Intel(R) Advanced+ Boot Block SCSP Block Diagram F-VCC F-VCCQ F-OE# F-WE# F-CE# F-RP# Flash VSS F-WP# A[Max:0] P-VCC F-VPP D[15:0] PSRAM R-WE# P-CS# R-UB# R-OE# R-LB# Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 8 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 2.2 Memory Map Table 2. 16 and 32 Mbit Memory Addressing (Sheet 1 of 2) 16-Mbit, 32-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 16-Mbit 32-Mbit Size (KW) 4 FF000-FFFFF 1FF000-1FFFFF 32 4 FE000-FEFFF 1FE000-1FEFFF 32 4 FD000-FDFFF 1FD000-1FDFFF 32 4 FC000-FCFFF 1FC000-1FCFFF 32 4 FB000-FBFFF 1FB000-1FBFFF 32 4 FA000-FAFFF 1FA000-1FAFFF 32 4 F9000-F9FFF 1F9000-1F9FFF 32 4 F8000-F8FFF 1F8000-1F8FFF 32 32 F0000-F7FFF 1F0000-1F7FFF 32 32 E8000-EFFFF 1E8000-1EFFFF 32 32 E0000-E7FFF 1E0000-1E7FFF 32 32 D8000-DFFFF 1D8000-1DFFFF 32 32 D0000-D7FFF 1D0000-1D7FFF 32 32 C8000-CFFFF 1C8000-1CFFFF 32 32 C0000-C7FFF 1C0000-1C7FFF 32 32 B8000-BFFFF 1B8000-1BFFFF 32 32 B0000-B7FFF 1B0000-1B7FFF 32 32 A8000-AFFFF 1A8000-1AFFFF 32 32 A0000-A7FFF 1A0000-1A7FFF 32 32 98000-9FFFF 198000-19FFFF 32 32 90000-97FFF 190000-197FFF 32 32 88000-8FFFF 188000-18FFFF 32 32 80000-87FFF 180000-187FFF 32 32 78000-7FFFF 178000-17FFFF 32 32 70000-77FFF 170000-177FFF 32 32 68000-6FFFF 168000-16FFFF 32 32 60000-67FFF 160000-167FFF 32 February 2007 Document Number: 252636-005US 16-Mbit 32-Mbit Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 9 Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 2. 16 and 32 Mbit Memory Addressing (Sheet 2 of 2) 16-Mbit, 32-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 16-Mbit 32-Mbit Size (KW) 32 58000-5FFFF 158000-15FFFF 32 32 50000-57FFF 150000-157FFF 32 32 48000-4FFFF 148000-14FFFF 32 32 40000-47FFF 140000-147FFF 32 32 38000-3FFFF 138000-13FFFF 32 32 30000-37FFF 130000-137FFF 32 32 28000-2FFFF 128000-12FFFF 32 32 20000-27FFF 120000-127FFF 32 32 18000-1FFFF 118000-11FFFF 32 32 10000-17FFF 110000-117FFF 32 32 08000-0FFFF 108000-10FFFF 32 32 00000-07FFF 100000-107FFF 32 32 0F8000-0FFFFF 32 32 0F0000-0F7FFF 32 32 0E8000-0EFFFF 32 32 0E0000-0E7FFF 32 32 0D8000-0DFFFF 32 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 32 32 0C0000-0C7FFF 32 32 0B8000-0BFFFF 32 32 0B0000-0B7FFF 32 32 0A8000-0AFFFF 32 This column continues on next page Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 10 16-Mbit 32-Mbit This column continues on next page February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 3. 16 and 32 Mbit Memory Addressing (Sheet 1 of 2) 16-Mbit, 32-Mbit Word-Wide Memory Addressing Top Boot Size (KW) Bottom Boot 32-Mbit Size (KW) 32 0A0000-0A7FFF 32 32 098000-09FFFF 32 32 090000-097FFF 32 32 088000-08FFFF 32 32 080000-087FFF 32 32 078000-07FFFF 32 32 070000-077FFF 32 32 068000-06FFFF 32 32 060000-067FFF 32 32 058000-05FFFF 32 32 050000-057FFF 32 32 048000-04FFFF 32 32 040000-047FFF 32 32 038000-03FFFF 32 32 030000-037FFF 32 1F8000-1FFFFF 32 028000-02FFFF 32 1F0000-1F7FFF 32 020000-027FFF 32 1E8000-1EFFFF 32 018000-01FFFF 32 1E0000-1E7FFF 32 010000-017FFF 32 1D8000-1DFFFF 32 008000-00FFFF 32 1D0000-1D7FFF 32 000000-007FFF 32 1C8000-1CFFFF 32 32 1C0000-1C7FFF 32 32 1B8000-1BFFFF 32 32 1B0000-1B7FFF 32 32 1A8000-1AFFFF 32 32 1A0000-1A7FFF 32 32 198000-19FFFF 32 32 190000-197FFF 32 32 188000-18FFFF 16-Mbit February 2007 Document Number: 252636-005US 16-Mbit 32-Mbit Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 11 Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 3. 16 and 32 Mbit Memory Addressing (Sheet 2 of 2) 16-Mbit, 32-Mbit Word-Wide Memory Addressing Top Boot Size (KW) 16-Mbit Bottom Boot 32-Mbit Size (KW) 16-Mbit 32-Mbit 32 32 180000-187FFF 32 32 178000-17FFFF 32 32 170000-177FFF 32 32 168000-16FFFF 32 32 160000-167FFF 32 32 158000-15FFFF 32 32 150000-157FFF 32 32 148000-14FFFF 32 32 140000-147FFF 32 32 138000-13FFFF 32 32 130000-137FFF 32 32 128000-12FFFF 32 32 120000-127FFF 32 32 118000-11FFFF 32 32 110000-117FFF 32 32 108000-10FFFF 32 32 100000-107FFF 32 32 F8000-FFFFF F8000-FFFFF 32 32 F0000-F7FFF F0000-F7FFF 32 32 E8000-EFFFF E8000-EFFFF 32 32 E0000-E7FFF E0000-E7FFF 32 32 D8000-DFFFF D8000-DFFFF 32 32 D0000-D7FFF D0000-D7FFF 32 32 C8000-CFFFF C8000-CFFFF 32 32 C0000-C7FFF C0000-C7FFF This column continues on next page Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 12 This column continues on next page February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 4. 16 and 32 Mbit Memory Addressing (Sheet 1 of 2) 16-Mbit, 32-Mbit Word-Wide Memory Addressing Top Boot Size (KW) Bottom Boot Size (KW) 16-Mbit 32-Mbit 32 32 B8000-BFFFF B8000-BFFFF 32 32 B0000-B7FFF B0000-B7FFF 32 32 A8000-AFFFF A8000-AFFFF 32 32 A0000-A7FFF A0000-A7FFF 32 32 98000-9FFFF 98000-9FFFF 32 32 90000-97FFF 90000-97FFF 32 32 88000-8FFFF 88000-8FFFF 32 32 80000-87FFF 80000-87FFF 32 32 78000-7FFFF 78000-7FFFF 32 32 70000-77FFF 70000-77FFF 32 32 68000-6FFFF 68000-6FFFF 32 32 60000-67FFF 60000-67FFF 32 32 58000-5FFFF 58000-5FFFF 32 32 50000-57FFF 50000-57FFF 32 32 48000-4FFFF 48000-4FFFF 32 32 40000-47FFF 40000-47FFF 32 32 38000-3FFFF 38000-3FFFF 32 32 30000-37FFF 30000-37FFF 32 32 28000-2FFFF 28000-2FFFF 32 32 20000-27FFF 20000-27FFF 32 32 18000-1FFFF 18000-1FFFF 32 32 10000-17FFF 10000-17FFF 32 32 08000-0FFFF 08000-0FFFF 32 4 07000-07FFF 07000-07FFF 32 4 06000-06FFF 06000-06FFF 32 4 05000-05FFF 05000-05FFF 32 4 04000-04FFF 04000-04FFF 32 4 03000-03FFF 03000-03FFF 32 4 02000-02FFF 02000-02FFF 16-Mbit February 2007 Document Number: 252636-005US 32-Mbit Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 13 Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 4. 16 and 32 Mbit Memory Addressing (Sheet 2 of 2) 16-Mbit, 32-Mbit Word-Wide Memory Addressing Top Boot Size (KW) Bottom Boot Size (KW) 16-Mbit 32-Mbit 32 4 01000-01FFF 01000-01FFF 32 4 00000-00FFF 00000-00FFF 16-Mbit 32-Mbit 2.3 Device ID Table Table 5. Device ID Read Configuration Address and Data Item Address Data x16 00000 0089 16-Mbit x 16-T x16 00001 88C2 16-Mbit x 16-B x16 00001 88C3 32-Mbit x 16-T x16 00001 88C4 32-Mbit x 16-B x16 00001 88C5 Manufacturer Code Device Code Note: Other locations within the configuration address space are reserved by Intel for future use. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 14 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 3.0 Package Information Figure 2. Mechanical Specifications for I Ballout (66 balls) Package (8x10x1.2 mm) A1 Index Mark 1 E 2 3 4 S2 5 6 7 8 9 10 11 12 12 11 10 9 8 7 6 5 4 3 2 S1 1 A A B B C C D D E E F F G G H H b e D Top View - Ball Down Bottom View - Ball Up A2 A Y A1 Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D February 2007 Document Number: 252636-005US Symbol A A1 A2 b D E e N Y S1 S2 Min Millimeters Nom Max 1.200 0.200 0.325 9.900 7.900 1.100 0.500 Notes Min Inches Nom Max 0.0472 0.0079 0.860 0.375 10.000 8.000 0.800 67 1.200 0.600 0.425 10.100 8.100 0.0128 0.3898 0.3110 0.100 1.300 0.700 0.0433 0.0197 0.0339 0.0148 0.3937 0.3150 0.0315 67 0.0472 0.0236 0.0167 0.3976 0.3189 0.0039 0.0512 0.0276 Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 15 Intel(R) Advanced+ Boot Block Flash Memory (C3) 4.0 Ballout and Signal Descriptions 4.1 Ballout Note: RAM ballout signals in Figure 3, "66-Ball SCSP Package Ballout" are shown with prefixes such as S-WE# or S-VCC to indicate SRAM. However, these ballout signals also indicate PSRAM, and are interchangeable with PSRAM specifications in this datasheet that are prefixed by R- or P-, such as R-WE# or P-VCC. Figure 3. 66-Ball SCSP Package Ballout 1 2 3 4 5 6 7 A20 A11 A15 A14 A13 A16 A8 A10 A9 F-WE# NC A21 8 9 10 11 12 A NC A12 F-VSS F-VCCQ NC B DQ15 S-WE# DQ14 DQ7 C DQ13 DQ6 DQ4 DQ5 D S-VSS F-RP# A22 E F-WP# F-VPP A19 DQ12 S-CS2 S-VCC F-VCC DQ11 DQ10 DQ2 DQ3 DQ9 DQ8 DQ0 DQ1 A3 A2 F S-LB# S-UB# S-OE# G A18 A17 A7 A6 A1 S-CS1# NC A5 A4 A0 F-CE# F-VSS F-OE# NC H NC NC Top View, Balls Down Notes: 1. Flash memory upgrade balls are shown up to A21 (64-Mbit flash) and A22 (128-Mbit flash). In all flash memory and PSRAM combinations, 66 balls are populated on lower density devices. (Upper address balls are not populated). Ball location A10 is NC on 16/2 devices only. 2. To maintain compatibility with all JEDEC Variation B options for the C6 ball location, connect this C6 land pad directly to the land pad for the G4 (A17) ball. 4.2 Signal Descriptions Table 6, "Signal Descriptions, NOR Flash" and Table 7, "Signal Descriptions - x16 PSRAM Memory Die" include generic names and descriptions for the signals in Figure 3, "66-Ball SCSP Package Ballout" on page 16 that are labeled according to Flash signals (F-) and SRAM/PSRAM signals (S-). Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 16 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 6. Signal Descriptions, NOR Flash Symbol Type A[Max:0] Input DQ[15:0] Input/ Output CE# Input Chip Enable (low-true): When low, selects the die; when high, deselects the die and places it in standby. OE# Input Output Enable (low-true): Must be low for reads, and high for writes. WE# Input Write Enable (low-true): Must be low for writes, and high for reads. WP# Input Write Protect (low-true): When low, activates Block Lock-Down; when high, deactivates Block Lock-Down. RP# Input Reset (low-true): When low, inhibits all operations; must be high for normal operations. VPP Input/ Power Program/Erase Power: Enabling voltage (VPP1) or power source (VPP2) for program and erase operations. Array contents cannot be altered when VPP is at or below VPPLK. VCC Power Core Power: Supply voltage for core circuits. All operations are inhibited when VCC is at, or below, VLKO. VCCQ Power I/O Power: Supply voltage for all I/O drivers. All operations are inhibited when VCCQ is at, or below, VLKO2. GND Power Ground: Core logic and I/O ground return. Connect to system ground - do not float any grounds. Table 7. Description Address: Address inputs for all read/write cycles. 32Mb A[Max] = A20 Data: Data or command inputs during write cycles; data, status, or device-information outputs during read cycles. Signal Descriptions - x16 PSRAM Memory Die Symbol Type A[Max:0] Input D[15:0] Input/ Output CS# Input Description Address: Address inputs for all bus cycles. 16Mb A[Max] = A19 Data: Data inputs during write cycles; data outputs during read cycles. Chip Select (low-true): CE#-low selects the die; CE#-high deselects the die, placing it in standby. OE# Input Output Enable (low-true): OE# must be low for reads and high for writes. WE# Input Write Enable (low-true): WE# must be low for writes and high for reads. UB# LB# Input Upper/Lower Byte Enable (low-true): LB#-low enables D[7:0] during read/write operations; UB#-low enables D[15:8] during read/write operations. When high, UB# and LB# mask their respective bytes. Asynchronous Only MODE Input Mode (low-true): MODE-low enables access to the Configuration Register, or to enter/exit lowpower mode. MODE must be high for read/write data operations. Power VCC Power Logic Power: Supply voltage for core-logic circuits. VCCQ Power I/O Power: Supply voltage for I/O drivers. VSS Power Ground: Core-logic and I/O-driver ground return. Connect all VSS balls to system ground - do not float any VSS balls. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 17 Intel(R) Advanced+ Boot Block Flash Memory (C3) 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the Absolute Maximum Ratings might cause permanent damage. These are stress ratings only. Do not operate the flash memory device beyond the Operating Conditions. Extended exposure beyond these Operating Conditions might affect device reliability. NOTICE: This datasheet contains information on products in full production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Table 8. Absolute Maximum Ratings Parameter Maximum Rating Extended Operating Temperature Notes -- During Read -- -25C to +85C During Flash Block Erase and Program -- Temperature under Bias -- Storage Temperature -55C to +125C -- Voltage on Any Ball (except F-VCC /F-VCCQ / P-VCC and F-VPP) with Respect to GND -0.5 V to +3.6 V 1 F-VPP Voltage (for Block Erase and Program) with Respect to GND -0.5 V to +13.5 V F-VCC / F-VCCQ / P-VCC Supply Voltage with Respect to GND -0.2V to +3.6 V -- Output Short Circuit Current 100 mA 3 1,2,4 Notes: 1. Minimum DC voltage is -0.5 V on input/output balls. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output balls is F-VCC / F-VCCQ / P-VCC + 0.5 V which, during transitions, may overshoot to F-VCC / F-VCCQ / P-VCC + 2.0 V for periods < 20 ns. 2. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns. 3. F-VPP voltage is normally 1.65 V-3.3 V. Connection to supply of 11.4 V-12.6 V can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. F-VPP may be connected to 12 V for a total of 80 hours maximum. See Section 10.2.1 for details 4. Output shorted for no more than one second. No more than one output shorted at a time. 5.2 Operating Conditions Symbol Parameter Notes Min Max Units -25 +85 C TCASE Operating Temperature VCC / VCCQ F-VCC /F-VCCQ /P-VCC Supply Voltage 1 2.7 3.3 Volts VPP1 Supply Voltage 1 1.65 3.3 Volts VPP2 Supply Voltage 1, 2 11.4 12.6 Cycling Block Erase Cycling 2 100,000 Volts Cycles Notes: 1. F-VCC/F-VCCQ must share the same supply. F-VCC/P-VCC must share the same supply when not in data retention. 2. Applying F-VPP = 11.4 V-12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V for a total of 80 hours maximum. See Section 10.2.1 for details. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 18 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 6.0 Electrical Specifications Note: All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TCASE = +25 C. Table 9. Flash DC Characteristics (Sheet 1 of 2) 2.7 V - 3.3 V Symbol Parameter Device Notes Unit Typ ILI Input Load Current -- -- ILO Output Leakage Current -- -- 0.25m -- ICCS ICCD ICCR ICCW ICCE ICCES VCC Standby Current VCC Deep Power-Down Current VCC Read Current VCC Program Current VCC Erase Current VCC Erase Suspend Current Test Conditions Max 2 A F-VCC/P-VCC = VCC Max VIN = VCC Max or GND 0.2 10 A F-VCC/P-VCC = VCC Max VIN = VCC Max or GND 10 25 A F-VCC = VCC Max F-CE# = F-RP# = VCC F-WP# = VCC or GND VIN = VCC Max or GND A F-VCC = VCCMax VIN = VCC Max or GND F-RP# = GND 0.2 V 0.13m and 0.18m -- 7 15 0.25m -- 7 25 0.13m and 0.18m -- 7 15 0.25m 1 10 18 mA 0.13m and 0.18m 1 9 18 mA 18 55 mA F-VPP = VPP1 Program in Progress 8 22 mA F-VPP = VPP2 (12 V) Program in Progress 16 45 mA F-VPP = VPP1 Erase in Progress 8 15 mA F-VPP = VPP2 (12 V) Erase in Progress A F-CE# = VCC , Erase Suspend in Progress A F-CE# = VCC , Program Suspend in Progress A F-RP# = GND 0.2 V F-VPP VCC -- -- 2 2 -- 2,3 7 15 0.25m 2,3 10 25 0.13m and 0.18m 2,3 7 15 5 F-VCC = VCCMax F-OE# = VIH, F-CE# = VIL f = 5 MHz, IOUT = 0 mA VIN = VIL or VIH ICCWS VCC Program Suspend Current IPPD F-VPP Deep Power-Down Current -- 0.2 IPPS F-VPP Standby Current -- 0.2 5 A F-VPP VCC 2 15 A F-VPP VCC 50 200 A F-VPP VCC IPPR IPPW IPPE F-VPP Read Current F-VPP Program Current F-VPP Erase Current February 2007 Document Number: 252636-005US -- -- -- 1 0.05 0.1 mA F-VPP =VPP1 Program in Progress 8 22 mA F-VPP = VPP2 (12 V) Program in Progress 0.05 0.1 ma F-VPP = VPP1 Erase in Progress 2 1 Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 19 Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 9. Flash DC Characteristics (Sheet 2 of 2) 2.7 V - 3.3 V Symbol IPPES Parameter Device F-VPP Erase Suspend Current IPPWS Notes -- F-VPP Program Suspend Current -- Unit Test Conditions Typ Max 0.2 5 A F-VPP = VPP1 Erase Suspend in Progress 50 200 A F-VPP = VPP2 (12 V) Erase Suspend in Progress 0.2 5 A F-VPP = VPP1 Program Suspend in Progress 50 200 A F-VPP = VPP2 (12 V) Program Suspend in Progress 1 1 Notes: 1. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 2. Sampled, not 100% tested. 3. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR. Note: All currents are in RMS unless otherwise noted. Table 10. PSRAM DC Characteristics Parameter V CC ICC ICC2 ISB Description 3.0 V PSRAM Test Conditions Voltage Range Operating Current at min cycle time Operating Current at max cycle time (1 s) Standby Current IIO = 0 mA IIO = 0 mA Min Max 2.7 3.1 8M - 30 16M - 35 16M - - 32M - 45 8M - 5 16M - 7 32M - 7 IOL Output Leakage Current V -- mA -- mA -- mA -- A -- A -- P-CS# P-VCC-0.2V. 8M - 80 16M - 100 P-CS# P-VCC -0.2V or 16M - 85 32M - 100 -1 +1 A 1 -1 +1 A 1 Address/Data toggling at minimum cycle time Input Leakage Current Note All inputs stable (either high or low) P-Mode P-VCC -0.2V IIL Unit -0.2 < VIN < P-VCC + 0.2 V -0.2 < VIN < P-VCC + 0.2 V P-VCC = VDR Notes: 1. Input Leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 20 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 11. Flash Voltage Characteristics 2.7 V - 3.3 V Symbol Parameter Device Note Min Max Unit Test Conditions VIL Input Low Voltage Flash -- -0.2 0.6 V -- VIH Input High Voltage Flash -- 2.3 VCC +0.2 V -- VOL Output Low Voltage Flash -- -0.10 0.10 V F-VCC /P-VCC = VCC Min IOL = 100 A VOH Output High Voltage Flash -- VCC - 0.1 -- V F-VCC /P-VCC = VCC Min IOH = -100 A VPPLK F-VPP Lock-Out Voltage Flash 1 1.0 V Complete Write Protection VPP1 F-VPP during Program / Erase Flash 1 1.65 3.3 V -- VPP2 Operations Flash 1,2 11.4 12.6 -- -- VLKO VCC Prog/Erase Lock Voltage Flash -- 1.5 -- V -- VLKO2 VCCQ Prog/Erase Lock Voltage Flash -- 1.2 -- V -- Notes: 1. Erase and Program are inhibited when F-Vpp < VPPLK and not guaranteed outside the valid F-Vpp ranges of VPP1 and VPP2. 2. Applying F-Vpp = 11.4V-12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-Vpp may be connected to 12 V for a total of 80 hours maximum. See Section 10.2.1 for details. Table 12. Parameter PSRAM Voltage Characteristics Description V CC Voltage Range VOH Output HIGH Voltage VOL Output LOW Voltage V IH Input HIGH Voltage VIL Input LOW Voltage Figure 4. 3.0 V PSRAM Test Conditions Unit Notes 3.1 V -- Min Max 2.7 IOH = -0.5 mA 2.4 - V -- IOH = -0.1 mA P-VCC - 0.3 - V -- IOL = 1 mA, - 0.4 V -- IOL = 0.1 mA, VCCMin -0.1 0.3 V -- P-VCC - 0.3 P-VCC + 0.2 V -- P-VCC-0.4 P-VCC + 0.2 V -- -0.2 0.5 V -- -0.2 0.6 V -- Input/Output Reference Waveform VCC Input 0.0 Note: V CC 2 Test Points VCC 2 Output AC test inputs are driven at VCCQ for a logic "1" and 0.0V for a logic "0." Input timing begins, and output February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 21 Intel(R) Advanced+ Boot Block Flash Memory (C3) timing ends, at VCCQ /2. Input rise and fall times (10%-90%) <10 ns. Worst case speed conditions are when VCCQ = VCCQMin. Figure 5. Test Configuration Device Under Test Note: Table 13. Out CL CL includes jig capacitance. Flash Test Configuration Component Values Test Configuration CL (pF) 2.7 V-3.3 V Standard Test 50 TCASE = +25 C, f = 1 MHz Table 14. Sym Capacitance Parameter Notes Typ Max Units Conditions CIN Input Capacitance 1 16 18 pF VIN = 0 V COUT Output Capacitance 1 20 22 pF VOUT = 0 V Note: Sampled, not 100% tested. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 22 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 7.0 AC Characteristics 7.1 Flash AC Characteristics--Read Operations Table 15. Flash AC Characteristics--Read Operations Density 16-Mbit Product # Sym Parameter -70 -90 -110 -70 -90 Unit Voltage Range Notes 32-Mbit 2.7 V - 3.3 V Min Max Max Max 110 Min Max 70 Min Max tAVAV Read Cycle Time R2 tAVQV Address to Output Delay R3 tELQV F-CE# to Output Delay 1 R4 tGLQV F-OE# to Output Delay 1 R5 tPHQV F-RP# to Output Delay R6 tELQX F-CE# to Output in Low Z 2 0 0 0 0 0 ns R7 tGLQX F-OE# to Output in Low Z 2 0 0 0 0 0 ns R8 tEHQZ F-CE# to Output in High Z 2 20 25 25 20 20 ns R9 tGHQZ F-OE# to Output in High Z 2 20 20 20 20 20 ns R1 0 tOH Output Hold from Address F-CE#, or F-OE# Change, Whichever Occurs First 2 0 90 Min R1 Notes: 1. 2. 3. 4. 70 Min 90 ns 70 90 110 70 90 ns 70 90 110 70 90 ns 20 30 30 20 20 ns 150 150 150 150 150 ns 0 0 0 0 ns F-OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV Sampled, but not 100% tested. See Figure 6, "AC Waveform: Flash Read Operations" on page 24. See Figure 4, "Input/Output Reference Waveform" on page 28 for timing measurements and maximum allowable input slew rate. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 23 Intel(R) Advanced+ Boot Block Flash Memory (C3) Figure 6. AC Waveform: Flash Read Operations Deviceand AddressSelection VIH ADDRESSES(A) VIL CE#(E) Data Valid Standby AddressStable R1 VIH VIL R8 VIH OE#(G) VIL R9 VIH WE#(W) VIL R7 VOH DATA(D/Q) VOL RP#(P) HighZ R4 R10 R3 R6 HighZ ValidOutput R2 VIH R5 VIL 7.2 Flash AC Characteristics--Write Operations Table 16. Flash AC Characteristics--Write Operations (Sheet 1 of 2) Density Product # Sym Parameter 16-Mbit -70 -90 -110 -70 -90 Unit Voltage Range Notes 32-Mbit 2.7 V - 3.3 V Min Min Min Min Min W1 tPHWL, tPHEL F-RP# High Recovery to F-WE# (F-CE#) Going Low 150 150 150 150 150 ns W2 tELWL, tWLEL F-CE# (F-WE#) Setup to F-WE# (F-CE#) Going Low 0 0 0 0 0 ns W3 tELEH, tWLWH F-WE# (F-CE#) Pulse Width 1 45 60 70 45 60 ns W4 tDVWH, tDVEH Data Setup to F-WE# (F-CE#) Going High 2 40 50 60 40 40 ns W5 tAVWH, tAVEH Address Setup to F-WE# (F-CE#) Going High 2 50 60 70 50 60 ns W6 tWHEH, tEHWH F-CE# (F-WE#) Hold Time from F-WE# (F-CE#) High 0 0 0 0 0 ns W7 tWHDX, tEHDX Data Hold Time from F-WE# (F-CE#) High 2 0 0 0 0 0 ns W8 tWHAX , tEHAX Address Hold Time from F-WE# (F-CE#) High 2 0 0 0 0 0 ns W9 tWHWL, tEHEL F-WE# (F-CE#) Pulse Width High 1 25 30 30 25 30 ns Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 24 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 16. Flash AC Characteristics--Write Operations (Sheet 2 of 2) Density Product # Sym Parameter 16-Mbit -70 -90 32-Mbit -110 -70 -90 Unit Voltage Range 2.7 V - 3.3 V Notes Min Min Min Min Min W10 tVPWH, tVPEH F-VPP Setup to F-WE# (F-CE#) Going High 3 200 200 200 200 200 ns W11 tQVVL F-VPP Hold from Valid SRD 3 0 0 0 0 0 ns Notes: 1. Write pulse width (tWP) is defined from F-CE# or F-WE# going low (whichever goes low last) to F-CE# or F-WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from F-CE# or F-WE# going high (whichever goes high first) to F-CE# or F-WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 2. Refer to Table 24, "Flash Memory Command Definitions" on page 38 for valid AIN or DIN. 3. Sampled, but not 100% tested. See Figure 4, "Input/Output Reference Waveform" on page 21 for timing measurements and maximum allowable input slew rate. See Figure 7, "AC Waveform: Flash Program and Erase Operations" on page 26. 7.3 Flash AC Characteristics--Erase and Program Timings Note: Typical values measured at TCASE = +25 C and nominal voltages. Table 17. Flash Erase and Program Timings Symbol Parameter F-VPP 1.65 V- 3.3 V Notes Typ(1) Max 11.4 V- 12.6 V Unit Typ(1) Max tBWPB 4-KW Parameter Block Program Time (Word) 1, 2 0.10 0.30 0.03 0.12 s tBWMB 32-KW Main Block Program Time (Word) 1, 2 0.8 2.4 0.24 1 s 0.25 m Word Program Time 1, 2 22 200 8 185 0.13 m and 0.18 m Word Program Time 1, 2 12 200 8 185 tWHQV1 / tEHQV1 s tWHQV2 / tEHQV2 4-KW Parameter Block Erase Time (Word) 1, 2 0.5 4 0.4 4 s tWHQV3 / tEHQV3 32-KW Main Block Erase Time (Word) 1, 2 1 5 0.6 5 s tWHRH1 / tEHRH1 Program Suspend Latency 2 5 10 5 10 s tWHRH2 / tEHRH2 Erase Suspend Latency 2 5 20 5 20 s Notes: 1. Excludes external system-level overhead. 2. Sampled, but not 100% tested. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 25 Intel(R) Advanced+ Boot Block Flash Memory (C3) Figure 7. AC Waveform: Flash Program and Erase Operations ADDRESSES [A] CE#(WE#) [E(W)] VIH A B AIN VIL VIH E F AIN W8 (Note 1) W6 VIH W2 VIL W E#(CE#) [W(E)] D W5 VIL OE# [G] C W9 VIH VIL (Note 1) W3 W4 DATA [D/Q] VIH High Z VIL RP# [P] W1 DIN W7 DIN Valid SRD DIN VIH VIL VIH W P# V [V] PP VIL W10 W11 VPPH 2 VPPH1 VPPLK VIL Notes: 1. F-CE# must be toggled low when reading Status Register Data. F-WE# must be inactive (high) when reading Status Register Data. 2. F-VCC Power-Up and Standby. 3. Write Program or Erase Setup Command. 4. Write Valid Address and Data (for Program) or Erase Confirm Command. 5. Automated Program or Erase Delay. 6. Read Status Register Data (SRD): reflects completed program/erase operation. 7. Write Read Array Command. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 26 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 7.4 Flash AC Characteristics--Reset Operations Figure 8. AC Waveform: Reset Operation R P # (P ) V IH V IL t P LP H (A ) R e s e t d u rin g R e a d M o d e tPHQV tPHW L tPHEL A b o rt C o m p le te t PLRH R P # (P ) V IH t PHQ V t PHW L t PHEL V IL t PLPH (B ) R e se t d u rin g P ro g ra m o r B lo ck E ra se , t P L P H < t P L R H A b o rt D e e p C o m p le te P o w e rD ow n R P # (P ) t PLRH V IH V IL t PHQ V t PHW L t PHEL t PLP H (C ) R e se t P ro g ra m o r B lo c k E ra se , t P L P H > t P LR H Table 18. Reset Specifications(1) Symbol Parameter Notes F-VCC 2.7 V - 3.3 V Min Unit Max tPLPH F-RP# Low to Reset during Read (If F-RP# is tied to VCC, this specification is not applicable) 2,4 tPLRH1 F-RP# Low to Reset during Block Erase 3,4 22 s tPLRH2 F-RP# Low to Reset during Program 3,4 12 s 100 ns Notes: 1. See Section 8.0.4, "Flash Reset" on page 32 for a full description of these conditions. 2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed. 3. If F-RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 4. Sampled, but not 100% tested. 7.5 PSRAM AC Characteristics--Read Operations Table 19. PSRAM AC, 85/88 ns Initial Access--Read Operations (Sheet 1 of 2) 3.0 V # R1 Symbol Parameter Min Max Unit Notes tRC Read Cycle Time 85 4,000 ns -- R2 tAA Address to Output Delay - 85 ns -- R3 tCO P-CS# to Output Delay - 85 ns -- R4 tOE R-OE# to Output Delay - 40 ns -- February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 27 Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 19. PSRAM AC, 85/88 ns Initial Access--Read Operations (Sheet 2 of 2) 3.0 V # Symbol Parameter Unit Min Max Notes R5 tBA R-UB#, R-LB# to Output Delay - 85 ns -- R6 tLZ P-CS# to Output in Low-Z 10 - ns 1,2 R7 tOLZ R-OE# to Output in Low-Z 0 - ns 2 R8 tHZ P-CS# to Output in High-Z 0 25 ns 1,2,3 R9 tOHZ R-OE# to Output in High-Z 0 25 ns 2,3 R10 tOH Output Hold (from Address, P-CS# or R-OE# change, whichever occurs first) 0 - ns -- R11 tBLZ R-UB#, R-LB# to Output in Low-Z 0 - ns 2 R12 tBHZ R-UB#, R-LB# to Output in High-Z 0 25 ns 2 PR1 tPC Page Cycle Time 40 - ns 4 PR2 tPA Page Access Time - 35 ns 4 Note: 1. 2. 3. 4. At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. Sampled but not 100% tested. Timings of tHZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4-Word Page read only available for 32-Mbit PSRAM. No page mode feature for 16-Mbit PSRAM. Table 20. PSRAM AC, 70 ns Initial Access--Read Operations (Sheet 1 of 2) 3.0 V # Symbol Parameter Unit Min Max 70 15000 - R1 tRC Read Cycle Time - - R2 tAA Address to Output Delay - 70 ns - R3 tCO P-CS# to Output Delay - 70 ns - R4 tOE R-OE# to Output Delay - 45 ns - R5 tBA R-UB#, R-LB# to Output Delay - 70 ns - R6 tLZ P-CS# to Output in Low-Z 5 - ns 1 R7 tOLZ R-OE# to Output in Low-Z 0 - ns - R8 tHZ P-CS# to Output in High-Z 0 25 ns 1, 2 R9 tOHZ R-OE# to Output in High-Z 0 25 ns 2 R10 tOH Output Hold (from Address, P-CS# or R-OE# change, whichever occurs first) 0 - ns - R11 tBLZ R-UB#, R-LB# to Output in Low-Z 0 - ns - R12 tBHZ R-UB#, R-LB# to Output in High-Z 0 25 ns - PR1 tPC Page Cycle Time 25 - ns 3 Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 28 ns Notes - February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 20. PSRAM AC, 70 ns Initial Access--Read Operations (Sheet 2 of 2) 3.0 V # Symbol PR2 Note: Parameter Min Max Unit Notes tPA Page Access Time - 25 ns 3 tCEL CE# low-time restriction ns 4 ns 4 1. At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. 2. Timings of t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4-Word Page read only available for 16-Mbit PSRAM. No page mode feature for 8-Mbit PSRAM. CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns 3. 4. 7.6 PSRAM AC Characteristics--Write Operations Table 21. PSRAM AC Characteristics--Write Operations # Symbol1 3.0 V Parameter7 Notes - ns -- 0 - ns 4 Max 70 W1 tWC W2 tAS W3 tWP R-WE# (P-CS#) Pulse Width 55 - ns 2,3 W4 tDW Data to Write Time Overlap 35 - ns -- W5 tAW 60 - ns -- W6 tCW 60 - ns -- W7 tDH 0 - ns -- W8 tWR Write Recovery 0 - ns 5 W9 tBW R-UB#, R-LB# Setup to R-WE# (P-CS#) Going High 60 - ns -- tCEL P-CS# low-time restriction (Chip Enable/Chip Select) - - ns 7 tWPH Write High Pulse Width - - ns -- W10 Write Cycle Time Unit Min Address Setup to R-WE# (P-CS#) and R-UB#, R-LB# going low Address Setup to R-WE# (P-CS#) Going High P-CS# (R-WE#) Setup to R-WE# (P-CS#) Going High Data Hold from R-WE# (P-CS#) High Notes: 1. See Figure 11, "AC Waveform PSRAM Write Operation" . 2. A write occurs during the overlap (tWP ) of low P-CS# and low R-WE#. A write begins when P-CS# goes low and R-WE# goes low with asserting R-UB# or R-LB# for single byte operation or simultaneously asserting R-UB# and R-LB# for double byte operation. A write ends at the earliest transition when P-CS# goes high and R-WE# goes high. 3. tWP is measured from P-CS# going low to end of a write. 4. tAS is measured from the address valid to the beginning of a write. 5. tWR is measured from the end of a write to the address change. tWR applied in case a write ends as P-CS# or R-WE# going high. 6. W3 is 70 ns for continuous write operations over 50 times. 7. P-CS# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 29 Intel(R) Advanced+ Boot Block Flash Memory (C3) Figure 9. AC Waveform of PSRAM Read Operations R1 R2 ADDRESSES R3 R8 P-CS# R5 R12 R-UB#, R-LB# R4 R9 R-OE# R7 R11 R6 R10 DATA Figure 10. Valid Data AC Waveform of PSRAM 4-Word Page Read Operation R1 R2 A[Max:2] Vali d Address A[1:0] PR1 Val id Address Valid Address Val id Address Vali d Address R3 R8 P-CS# R4 R9 R-OE# R7 R6 PR2 Valid Data DATA Note: Valid Data Valid Data Val id Data Available only for 32-Mbit PSRAM and line items with 16-Mbit PSRAM (70 ns). Not applicable to 8-Mbit PSRAM. Figure 11. AC Waveform PSRAM Write Operation W1 W2 ADDRESSES W6 P-CS# W9 R-UB#, R-LB# W8 W3 W5 R-WE# W4 DAT A Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 30 W7 Data In February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 8.0 Bus Operation All bus cycles to or from the SCSP conform to standard microcontroller bus cycles. Four control signals dictate the data flow in and out of the flash component: * F-CE# * F-OE# * F-WE# * F-RP# Four separate control signals handle the data flow in and out of the PSRAM component: * P-CS# * R-UB# * R-LB# * R-OE# * R-WE# Table 42 on page 65 and Table 22 on page 32 summarize these bus operations . 8.0.1 Read The flash memory device provides four read modes: * Read array * Read identifier * Read status * CFI query These flash memory read modes do not depend on the F-VPP voltage. Upon initial device power-up or after exit from reset, the flash memory device automatically defaults to read array mode. F-CE# and F-OE# must be asserted to obtain data from the flash memory device. The PSRAM provides only one read mode. P-CS#, and R-OE# must be asserted to obtain data from the PSRAM device. See Table 22 for a summary of operations. Note: Two devices cannot drive the memory bus at the same time. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 31 Intel(R) Advanced+ Boot Block Flash Memory (C3) Intel Advanced+ Boot Block Flash Memory SCSP Bus Operations L Standby H H X X Output Disable H L H H Reset L X X X FLASH F-RP# Read PSRAM must be in High Z Any PSRAM mode is allowable FLASH must be in High Z Write Standby Output Disable Any FLASH mode is allowable L L H D0-D15 Flash DOUT -- Flash DIN -- Notes Other High Z -- Other High Z -- Other High Z -- L RAM DOUT -- RAM DIN -- Other High Z -- Other High Z -- Other High Z 1 L H L L H X X X X X X X L H H X Data Retention Memory Bus Control H Memory Output R-UB#,R-LB# L H R-WE# L L P-CS# F-WE# H H F-CE# Read Write Modes RAM PSRAM Signals F-OE1# Flash Signals R-OE# Table 22. same as a standby Notes: 1. To place the PSRAM into data retention mode, lower the P-VCC signal to the VDR range, as specified. 8.0.2 Output Disable When F-OE# and R-OE# are deasserted, the SCSP output signals are placed in a highimpedance state. 8.0.3 Standby When F-CE# and P-CS# are deasserted, the SCSP enters a standby mode, which substantially reduces device power consumption. In standby mode, outputs are placed in a high-impedance state independent of F-OE# and R-OE#. If the flash memory device is deselected during a program or erase operation, the flash memory continues to consume active power until the program or erase operation is complete. 8.0.4 Flash Reset The flash memory device enters a reset mode when RP# is driven low. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. After returning from reset, a time tPHQV is required until outputs are valid. A delay (tPHWL or tPHEL) is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored. * The flash memory device defaults to read array mode. * The status register is set to 80h. * The read configuration register defaults to asynchronous reads. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 32 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) If RP# is taken low during a block erase or program operation, the operation aborts and the memory contents at the aborted location are no longer valid. 8.0.5 Write * Writes to flash memory occur when both F-CE# and F-WE# are asserted and FOE# is deasserted. * Writes to PSRAM occur when both P-CS# and R-WE# are asserted and R-OE# is deasserted. Commands are written to the flash memory Command User Interface (CUI), using standard microprocessor write timings to control flash memory operations. The CUI does not occupy an addressable memory location within the flash memory device. The address and data buses are latched on the rising edge of the second F-WE# or F-CE# pulse, whichever occurs first. (See Figure 6 on page 24 and Figure 7 on page 26 for read and write waveforms.) February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 33 Intel(R) Advanced+ Boot Block Flash Memory (C3) 9.0 Flash Operations The flash memory has four read modes: * Read array * Read configuration * Read status * CFI query The write modes are: * Program * Erase Three additional modes are available only during suspended operations: * Erase suspend to program * Erase suspend to read * Program suspend to read These modes are reached using the commands summarized in Table 24, "Flash Memory Command Definitions" on page 38. 9.1 Read Array (FFh) When F-RP# transitions from VIL (reset) to VIH, the flash memory device defaults to read array mode and responds to the read control inputs without additional CUI commands. In addition, the address of the desired location must be applied to the address balls. If the flash memory device is not in read array mode, such as after a program or erase operation, the Read Array command (FFh) must be written to the CUI before array reads can take place. 9.2 Read Identifier (90h) The Read Configuration mode outputs three types of information: * Manufacturer/device identifier * Block locking status * Protection register 1. To switch the flash memory device to this mode, write the read configuration command (90h). In this mode, read cycles from addresses shown in Table 23, "Read Configuration Table" on page 34 retrieve the specified information. 2. To return to read array mode, write the Read Array command (FFh). Table 23. Read Configuration Table (Sheet 1 of 2) Item Manufacturer Code (x16) Address Data 0x00000 0x0089 Device ID (See Appendix D) 0x00001 ID Block Lock Configuration 0xXX002 LOCK Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 34 Notes 1, 2 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 23. Read Configuration Table (Sheet 2 of 2) Item Address Data * Block Is Unlocked DQ 0 = 0 * Block Is Locked DQ 0 = 1 * Block Is Locked-Down DQ 1 = 1 Protection Register Lock 0x80 PR-LK Protection Register (x16) 0x81-0x88 PR Notes 3 Notes: 1. See Section 9.7 for valid lock status outputs. 2. "XX" specifies the block address of lock configuration being read. 3. See Section 9.8 for protection register information. Intel reserves other locations within the configuration address space for future use. 9.3 Read Status Register (70h) The status register indicates the status of device operations, and the success/failure of that operation. 1. After you issue the Read Status Register (70h) command, subsequent reads output data from the status register until another command is issued. 2. To return to reading from the array, issue a Read Array (FFh) command. The status register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 00h during a Read Status Register command. The contents of the status register are latched on the falling edge of F-OE# or F-CE#, whichever occurs last. Latching on the falling edge prevents possible bus errors that might occur if status register contents change while being read. F-CE# or F-OE# must be toggled with each subsequent status read, or the status register does not indicate completion of a program or erase operation. When the WSM is active, SR7 indicates the status of the WSM. The remaining bits in the status register indicate whether the WSM was successful in performing the desired operation (see Table 25, "Flash Memory Status Register Definition" on page 39). 9.3.1 Clear Status Register (50h) The WSM sets status bits 1 through 7 to a 1 value, and clears bits 2, 6 and 7 to a 0 value. However, WSM cannot clear status bits 1 or 3 through 5 to a 0 value. Because bits 1, 3, 4, and 5 indicate various error conditions, only the Clear Status Register (50h) command can clear these bits. If the system software controls resetting these bits, several operations (such as cumulatively programming several addresses or erasing multiple blocks in sequence) can be performed before reading the status register to determine whether an error occurred during that series. * Clear the status register before beginning another command or sequence. * A Read Array command must be issued before data can be read from the memory array. * Resetting the flash memory device also clears the status register. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 35 Intel(R) Advanced+ Boot Block Flash Memory (C3) 9.4 CFI Query (98h) The CFI query mode outputs Common Flash Interface (CFI) data when the flash memory device is read. The CFI data structure contains information such as: * block size * density * command set * electrical specifications 1. To access this mode, write the CFI Query Command (98h). In this mode, read cycles from addresses shown in Appendix , "CFI Query Structure" retrieve the specified information. 2. To return to read array mode, write the Read Array command (FFh). 9.5 Word Program (40h/10h) Programming uses a two-write sequence. 1. The Program Setup command (40h) is written to the CUI. 2. A second write specifies the address and data to program. 3. The WSM executes a sequence of internally timed events to program desired bits of the addressed location 4. The WSM then verifies that the bits are sufficiently programmed. Programming the memory changes the value of specific bits within an address to 0. Note: If you attempt to program a 1 value, the memory cell contents do not change and no error occurs. The status register indicates programming status: * While the program sequence executes, status bit 7 has a 0 value. * To poll the status register, toggle either F-CE# or F-OE#. While programming, the only valid commands are: * Read Status Register * Program Suspend * Program Resume 1. When programming is complete, check the program status bits. -- If the programming operation was unsuccessful, status register but SR.4 is set to indicate a program failure. -- If SR.3 is set, then F-VPP was not within acceptable limits, and the WSM did not execute the program command. -- If SR.1 is set, a program operation was attempted on a locked block and the operation aborted. 2. Clear the status register before attempting the next operation. Any CUI instruction can follow after programming is completed. 3. To prevent inadvertent status register reads, reset the CUI to read array mode. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 36 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 9.5.1 Suspending and Resuming Program (B0h/D0h) The Program Suspend command halts an in-progress program operation, so that data can be read from other locations of memory. 1. After the programming process starts, write the Program Suspend command to the CUI. -- This command requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). -- The flash memory device continues to output status register data after the Program Suspend command is written. 2. Poll status register bits SR.7 and SR.2 to determine when the program operation has been suspended (both are set to 1). Note: tWHRH1/tEHRH1 specifies the program suspend latency. A Read Array command can be written to the CUI to read data from any block other than the suspended block. The only other valid commands, while program is suspended, are: * Read Status Register * Read Configuration * CFI Query * Program Resume. After the Program Resume command is written to the flash memory: * WSM continues the programming process. * Status register bits SR.2 and SR.7 are automatically cleared. * The flash memory device automatically outputs status register data when read (see Appendix , "Program/Erase Flowcharts"). Note: F-VPP must remain at the same F-VPP level used for program while in program suspend mode. F-RP# must also remain at VIH. 9.6 Block Erase (20h) To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to "1." Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to program all bits within the block to "0," erase all bits within the block to "1," then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a "0." When the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status register will be set to a "1," indicating an erase failure. If F-VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a "1" to identify that F-VPP supply voltage was not within acceptable limits. After an erase operation, clear the status register (50h) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 37 Intel(R) Advanced+ Boot Block Flash Memory (C3) 9.6.1 Suspending and Resuming Erase (B0h/D0h) An erase operation can take several seconds to complete, therefore, the Erase Suspend command is provided to allow erase-sequence interruption in order to read data from, or program data to, another block in memory. Once an erase sequence has started, writing the Erase Suspend command to the CUI causes the device to suspend the erase sequence at a predetermined point in the erase algorithm. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 7.3, "Flash AC Characteristics--Erase and Program Timings" on page 25. When an erase operation has been suspended, a Word Program or Read operation can be performed within any block, except the block that is in an erase suspend state. An erase operation cannot be nested within another erase suspend operation. A suspended erase operation cannot resume until the nested program operation has completed. Following are valid commands during Erase Suspend: * Read Array * Read/Clear Status Register * Read Identifier * CFI Query * Erase Resume * Program * Program Suspend/Resume * Lock/Unlock/Lock-Down Block. To resume an erase suspend operation, issue the Resume command. The Resume command can be written to any device address. When a program operation is nested within an Erase Suspend operation and the Program Suspend command is issued, the device suspends the program operation. When the resume command is issued, the device resumes the program operation first. Once the nested program operation completes, an additional Resume command is required to complete the block operation. Table 24. Flash Memory Command Definitions (Sheet 1 of 2) First Bus Cycle Command Read Array Second Bus Cycle Note 1 Operation Address Data Write X FFh Operation Address Data Read Identifier 1, 2 Write X 90h Read IA ID CFI Query 1, 2 Write X 98h Read QA QD Read Status Register 1 Write X 70h Read X SRD Clear Status Register 1 Write X 50h Word Program 1, 3 Write X 40h/10h Write PA PD Block Erase/ Confirm 1 Write X 20h Write BA D0h Program/Erase Suspend 1 Write X B0h Program/Erase Resume 1 Write X D0h 1 Write X 60h Write BA 01h 1, 4 Write X 60h Write BA D0h Lock Block Unlock Block Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 38 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 24. Flash Memory Command Definitions (Sheet 2 of 2) First Bus Cycle Command Second Bus Cycle Note Operation Address Data Operation Address Data Lock-Down Block 1 Write X 60h Write BA 2Fh Protection Register Program 1 Write X C0h Write PA PD Lock Protection Register 1 Write X C0h Write PA FFFD BA = Block Address IA = Identifier Address QA = Query Address X = Don't Care PA = Program Address BA = Block Address ID = Identifier Data QD = Query Data SRD = Status Register Data PD = Program Data X = Don't Care PA = Program Address SRD = Status Register Data PD = Program Data Notes: 1. When writing commands, the upper data bus [DQ8-DQ 15] should be either VIL or VIH, to minimize current draw. 2. Following the Read Configuration or CFI Query commands, read operations output device configuration or CFI query information, respectively. 3. Either 40h or 10h command is valid, but the Intel standard is 40h. 4. When unlocking a block, WP# must be held for three clock cycles (1 clock cycle after the second command bus cycle). Table 25. Flash Memory Status Register Definition WSMS ESS ES PS VPPS PSS BLS R 7 6 5 4 3 2 1 0 Bit Number NOTES: SR.7 WRITE STATE MACHINE STATUS 1 = Ready (WSMS) 0 = Busy Check Write State Machine bit first to determine Word Program or Block Erase completion, before checking Program or Erase Status bits. SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to 1. ESS bit remains set to 1 until an Erase Resume command is issued. SR.5 = ERASE STATUS (ES) 1 = Error In Block Erase 0 = Successful Block Erase When this bit is set to 1, WSM has applied the max. number of erase pulses and is still unable to verify successful block erasure. SR.4 = PROGRAM STATUS (PS) 1 = Error in Programming 0 = Successful Programming When this bit is set to 1, WSM has attempted but failed to program a word/byte. SR.3 = F-VPP STATUS (VPPS) 1 = F-VPP Low Detect, Operation Abort 0 = F-VPP OK The F-VPP status bit does not provide continuous indication of VPP level. The WSM interrogates F-VPP level only after the Program or Erase command sequences have been entered, and informs the system if F-VPP has not been switched on. The FVPP is also checked before the operation is verified by the WSM. The F-VPP status bit is not guaranteed to report accurate feedback between VPPLK and VPP1 min. SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to 1. PSS bit remains set to 1 until a Program Resume command is issued. SR.1 = BLOCK LOCK STATUS 1 = Prog/Erase attempted on a locked block; Operation aborted. 0 = No operation to locked blocks If a program or erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserved for future use and should be masked out when polling the status register. Note: A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 39 Intel(R) Advanced+ Boot Block Flash Memory (C3) 9.7 Block Locking The instant, individual block locking feature that allows any flash block to be locked or unlocked with no latency, which enables instant code and data protection. This locking offers two levels of protection. The first level allows software-only control of block locking (useful for data blocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). The following sections will discuss the operation of the locking system. The term "state [XYZ]" will be used to specify locking states; e.g., "state [001]," where X = value of WP#, Y = bit DQ1 of the Block Lock status register, and Z = bit DQ0 of the Block Lock status register. Table 27, "Block Locking State Transitions" on page 42 defines all of these possible locking states. 9.7.1 Block Locking Operation Summary The following concisely summarizes the locking functionality. All blocks are locked when powered-up, and can be unlocked or locked with the Unlock and Lock commands. * The Lock-Down command locks a block and prevents it from being unlocked when WP# = 0. * When WP# = 1, Lock-Down is overridden and commands can unlock/lock lockeddown blocks. * When WP# returns to 0, locked-down blocks return to Lock-Down. * Lock-Down is cleared only when the device is reset or powered-down. The locking status of each block can set to Locked, Unlocked, and Lock-Down, each of which will be described in the following sections. A comprehensive state table for the locking functions is shown in Table 27 on page 42, and a flowchart for locking operations is shown in Figure 17 on page 49. 9.7.2 Locked State The default status of all blocks upon power-up or reset is locked (states [001] or [101]). Locked blocks are fully protected from alteration. Any program or erase operations attempted on a locked block will return an error on bit SR.1 of the status register. The status of a locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. Unlocked blocks can be locked issuing the "Lock" command sequence, 60h followed by 01h. 9.7.3 Unlocked State Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the Locked state when the device is reset or powered down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A Locked block can be unlocked by writing the Unlock command sequence, 60h followed by D0h. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 40 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 9.7.4 Lock-Down State Blocks that are Locked-Down (state [011]) are protected from program and erase operations (just like Locked blocks), but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-down by writing the Lock-Down command sequence, 60h followed by 2Fh. Locked-Down blocks revert to the Locked state when the device is reset or powered down. The Lock-Down function is dependent on the WP# input ball. When WP# = 0, blocks in Lock-Down [011] are protected from program, erase, and lock status changes. When WP# = 1, the Lock-Down function is disabled ([111]) and locked-down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. These blocks can then be re-locked [111] and unlocked [110] as desired while WP# remains high. When WP# goes low, blocks that were previously locked-down return to the Lock-Down state [011] regardless of any changes made while WP# was high. Device reset or power-down resets all blocks, including those in Lock-Down, to Locked state. 9.7.5 Reading Lock Status for a Block The lock status of every block can be read in the configuration read mode of the device. To enter this mode, write 90h to the device. Subsequent reads at Block Address + 00002 will output the lock status of that block. The lock status is represented by the least significant outputs, DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by device reset or power-down. Table 26. Block Lock Status Item Block Lock Configuration 9.7.6 Address XX002 Data LOCK * Block Is Unlocked DQ0 = 0 * Block Is Locked DQ0 = 1 * Block Is Locked-Down DQ1 = 1 Locking Operation During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the erase suspend command (B0h), then check the status register until it indicates that the erase operation has been suspended. Next write the desired lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command (D0h). If a block is locked or locked-down during a suspended erase of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 41 Intel(R) Advanced+ Boot Block Flash Memory (C3) 9.7.7 Status Register Error Checking Using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. Since locking changes are performed using a two cycle command sequence, e.g., 60h followed by 01h to lock a block, following the Configuration Setup command (60h) with an invalid command will produce a lock command error (SR.4 and SR.5 will be set to 1) in the status register. If a lock command error occurs during an erase suspend, SR.4 and SR.5 will be set to 1, and will remain at 1 after the erase is resumed. When erase is complete, any possible error during the erase cannot be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an erase suspend. Table 27. Block Locking State Transitions Current State Next State after Command Input WP# DQ 1 DQ 0 Name Erase/ Program Allowed? 0 0 0 Unlocked Yes Go To [001] - Go To [011] 1 0 0 Unlocked Yes Go To [101] - Go To [111] 0 0 1 Locked (Default) No - Go To [000] Go To [011] 1 0 1 Locked No - Go To [100] Go To [111] 0 1 1 Locked-Down No - - - 1 1 0 Go To [111] - Go To [111] 1 1 1 Lock-Down Disabled Yes No - Go To [110] - Lock Unlock Lock-Down Notes: 1. "-" indicates no change in the current state. 2. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ1, and Z = DQ0. The current locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ0, DQ1). DQ0 indicates if a block is locked (1) or unlocked (0). DQ1 indicates if a block has been locked-down (1) or not (0). 3. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). holding WP# = 0 is the recommended default. 4. The "Erase/Program Allowed?" column shows whether erase and program operations are enabled (Yes) or disabled (No) in that block's current locking state. 5. The "Lock Command Input Result [Next State]" column shows the result of writing the three locking commands (Lock, Unlock, Lock-Down) in the current locking state. For example, "Goes To [001]" would mean that writing the command to a block in the current locking state would change it to [001]. 6. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64 bit number, which is unchangeable. The other segment is left blank for customer designs to program as desired. 9.8 128 Bit Protection Register The C3 SCSP architecture includes a 128-bit protection register than can be used to increase the security of a system design. For example, the number contained in the protection register can be used to "mate" the flash component with other system components such as the CPU or ASIC, preventing device substitution. 9.8.1 Reading the Protection Register The protection register is read in the configuration read mode. The device is switched to this mode by writing the Read Configuration command (90h). Once in this mode, read cycles from addresses shown in Appendix E retrieve the specified information. To return to read array mode, write the Read Array command (FFh). Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 42 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 9.8.2 Programming the Protection Register (C0h) The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide parts. First write the Protection Program Setup command, C0h. The next write to the device will latch in address and data and program the specified location. The allowable addresses are shown in Appendix E. See Figure 18, "Protection Register Programming Flowchart" on page 50. Any attempt to address Protection Program commands outside the defined protection register address space will result in a status register error (program error bit SR.4 will be set to 1). Attempting to program or to a previously locked protection register segment will result in a status register error (program error bit SR.4 and lock error bit SR.1 will be set to 1). 9.8.3 Locking the Protection Register The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set using the Protection Program command to program FFFDh to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. A Protection Program command to locked words will result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1). The protection register lockout state is not reversible. Figure 12. Protection Register Memory Map 88H 4 Words User Programmed 85H 84H 4 Words Factory Programmed 81H 80H February 2007 Document Number: 252636-005US PR-LOCK Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 43 Intel(R) Advanced+ Boot Block Flash Memory (C3) 10.0 Power and Reset Considerations 10.1 Power-Up/Down Characteristics In order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up F-VCC, F-VCCQ and P-VCC together. Conversely, F-VCC, F-VCCQ and P-VCC must power-down together. It is also recommended to power-up FVPP with or slightly after F-VCC. Conversely, F-VPP must power down with or slightly before F-VCC. If F-VCCQ and/or F-VPP are not connected to the F-VCC supply, then F-VCC should attain F-VCCMin before applying F-VCCQ and F-VPP. Device inputs should not be driven before supply voltage = F-VCCMin. Power supply transitions should only occur when F-RP# is low. 10.2 Additional Flash Features C3 SCSP products provide in-system programming and erase in the 1.65 V-3.3 V range. For fast production programming, it also includes a low-cost, backwardcompatible 12 V programming feature. 10.2.1 Improved 12 Volt Production Programming When F-VPP is between 1.65 V and 3.3 V, all program and erase current is drawn through the F-VCC signal. Note that if F-VPP is driven by a logic signal, VIH min = 1.65 V. That is, F-VPP must remain above 1.65 V to perform in-system flash modifications. When F-VPP is connected to a 12 V power supply, the device draws program and erase current directly from the F-VPP signal. This eliminates the need for an external switching transistor to control the voltage F-VPP. The 12 V F-VPP mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to F-VPP during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage. 10.2.2 F-VPP VPPLK for Complete Protection In addition to the flexible block locking, the F-VPP programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. When F-VPP is below VPPLK, any program or erase operation will result in a error, prompting the corresponding status register bit (SR.3) to be set. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 44 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 11.0 Program/Erase Flowcharts Figure 13. Automated Word Programming Flowchart Start Write 40H Bus Operation Command Write Program Setup Write Program Program Address/Data Data = Data to Program Addr = Location to Program Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Repeat for subsequent programming operations. No SR.7 = 1? Data = 40H Status Register Data Toggle CE# or OE# to Update Status Register Data Read Read Status Register Comments SR Full Status Check can be done after each program or after a sequence of program operations. Yes Full Status Check if Desired Write FFH after the last program operation to reset device to read array mode. Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) Bus Operation 1 SR.3 = 0 VPP Range Error Programming Error 0 1 SR.1 = Attempted Program to Locked Block - Aborted 0 Program Successful February 2007 Document Number: 252636-005US Comments Standby Check SR.3 1 = V PP Low Detect Standby Check SR.4 1 = V PP Program Error Standby Check SR.1 1 = Attempted Program to Locked Block - Program Aborted 1 SR.4 = Command SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 45 Intel(R) Advanced+ Boot Block Flash Memory (C3) Figure 14. Program Suspend/Resume Flowchart Start Bus Operation Command Write Program Suspend Data = B0H Addr = X Write Read Status Data = 70H Addr = X Write B0H Comments Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Write 70H Read Read Status Register Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.2 1 = Program Suspended 0 = Program Completed 0 SR.7 = Write 1 0 SR.2 = Program Completed Write Data = FFH Addr = X Read array data from block other than the one being programmed. Read 1 Write FFH Read Array Program Resume Data = D0H Addr = X Read Array Data No Done Reading Yes Write D0H Write FFH Program Resumed Read Array Data Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 46 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Figure 15. Automated Block Erase Flowchart Start Write 20H Write D0H and Block Address Bus Operation Command Write Erase Setup Data = 20H Addr = Within Block to Be Erased Write Erase Confirm Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Data Read Read Status Register Suspend Erase Loop 0 SR.7 = No Suspend Erase Yes Comments Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures. 1 Full Status Check if Desired Write FFH after the last write operation to reset device to read array mode. Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) Bus Operation 1 SR.3 = 0 1 Command Sequence Error 0 1 SR.5 = Block Erase Error 0 1 SR.1 = Attempted Erase of Locked Block - Aborted 0 Comments Standby Check SR.3 1 = VPP Low Detect Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error Standby Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted VPP Range Error SR.4,5 = Command SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Block Erase Successful 0645_14 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 47 Intel(R) Advanced+ Boot Block Flash Memory (C3) Figure 16. Erase Suspend/Resume Flowchart Start Bus Operation Command Write Erase Suspend Data = B0H Addr = X Write Read Status Data = 70H Addr = X Write B0H Comments Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Write 70H Read Read Status Register Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.6 1 = Erase Suspended 0 = Erase Completed 0 SR.7 = Write 1 0 SR.6 = Erase Completed Read Array Read array data from block other than the one being erased. Read 1 Write Write FFH Data = FFH Addr = X Erase Resume Data = D0H Addr = X Read Array Data No Done Reading Yes Write D0H Write FFH Erase Resumed Read Array Data 0645_15 Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 48 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Figure 17. Locking Operations Flowchart Start Write 60H (Configuration Setup) Write 01H, D0H, or 2FH Write 90H (Read Configuration) Bus Operation Command Write Config. Setup Data = 60H Addr = X Write Lock, Unlock, or Lockdown Data= 01H (Lock Block) D0H (Unlock Block) 2FH (Lockdown Block) Addr=Within block to lock Write (Optional) Read Configuration Data = 90H Addr = X Read (Optional) Block Lock Status Optional Standby (Optional) Read Block Lock Status Comments Block Lock Status Data Addr = Second addr of block Confirm Locking Change on DQ1, DQ0. (See Block Locking State Table for valid combinations.) Locking Change Confirmed? No Write FFh (Read Array) Locking Change Complete 0645_16 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 49 Intel(R) Advanced+ Boot Block Flash Memory (C3) Figure 18. Protection Register Programming Flowchart Start Bus Operation Command Write C0H (Protection Reg. Program Setup) Write Protection Program Setup Data = C0H Write Protection Program Data = Data to Program Addr = Location to Program Write Protect. Register Address/Data Read Check SR.7 1 = WSM Ready 0 = WSM Busy Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. No SR.7 = 1? Status Register Data Toggle CE# or OE# to Update Status Register Data Standby Read Status Register Comments Repeat for subsequent programming operations. Yes SR Full Status Check can be done after each program or after a sequence of program operations. Full Status Check if Desired Write FFH after the last program operation to reset device to read array mode. Program Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) VPP Range Error 0,1 SR.1, SR.4 = 1,1 SR.1, SR.4 = Protection Register Programming Error Comments Standby SR.1 SR.3 SR.4 0 1 1 V PP Low Standby 0 0 1 Prot. Reg. Prog. Error 1 0 1 Register Locked: Aborted 1, 1 SR.3, SR.4 = Command Standby SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. Attempted Program to Locked Register Aborted Program Successful SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases of multiple protection register program operations before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. 0645_17 Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 50 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) 12.0 CFI Query Structure This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI. 12.1 Query Structure Output The Query "database" allows system software to gain information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of wordwide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 28. Summary of Query Structure Output as a Function of Device and Mode Device Hex Offset Device Address Table 29. Code ASCII Value 10: 51 "Q" 11: 52 "R" 12: 59 "Y" Example of Query Structure Output of x16 and x8 Devices (Sheet 1 of 2) Word Addressing Offset Hex Code A15-A0 Byte Addressing Value D15-D0 Offset Hex Code A7-A0 Value D7-D0 0010h 0051 "Q" 10h 51 "Q" 0011h 0052 "R" 11h 52 "R" 0012h 0059 "Y" 12h 59 "Y" 0013h P_IDLO PrVendor 13h P_IDLO PrVendor February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 51 Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 29. Example of Query Structure Output of x16 and x8 Devices (Sheet 2 of 2) Word Addressing Offset Hex Code A15-A0 12.2 Byte Addressing Value D15-D0 Offset Hex Code A7-A0 Value D7-D0 0014h P_IDHI ID # 14h P_IDLO ID # 0015h PLO PrVendor 15h P_IDHI ID # ... ... 0016h PHI TblAdr 16h 0017h A_IDLO AltVendor 17h 0018h A_IDHI ID # 18h ... ... ... ... Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below. Table 30. Offset Query Structure Sub-Section Name 00h 01h Description Notes Manufacturer Code 1 Device Code 1 Block Status Register Block-specific information 1,2 04-0Fh Reserved Reserved for vendor-specific information 1 10h CFI Query Identification String Command set ID and vendor data offset 1 (BA+2)h 1Bh System Interface Information Device timing & voltage information 1 27h Device Geometry Definition Flash device layout 1 P Primary Intel-Specific Extended Query Table Vendor-defined additional information specific to the Primary Vendor Algorithm 1,3 Notes: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table. 12.3 Block Lock Status Register The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Block Erase Status (BSR.1) allows system software to determine the success of the last block erase operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation. This bit is only reset by issuing another erase operation to the block. The Block Status Register is accessed from word address 02h within each block. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 52 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 31. Offset Block Status Register Length (BA+2)h Note: Description 1 Address Value Notes 1 Block Lock Status Register BA+2: --00 or --01 BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BA+2: (bit 0): 0 or 1 BSR.1 Block Lock-Down Status 0 = Not locked down 1 = Locked down BA+2: (bit 1): 0 or 1 BSR 2-7: Reserved for future use BA+2: (bit 2-7): 0 1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.) 12.4 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 32. CFI Identification Offset Length 10h 3 13h 15h 17h 19h 2 2 2 2 Description Addr. Hex Code Value 10 --51 "Q" 11: --52 "R" 12: --59 "Y" Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code. 13: --03 16-bit ID code for vendor-specified algorithms 14: --00 Extended Query Table primary algorithm address 15: --35 16: --00 Alternate vendor command set and control interface ID code 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 Secondary algorithm Extended Query Table address. 19: --00 0000h means none exists 1A: --00 12.5 System Interface Information Table 33. System Interface Information (Sheet 1 of 2) Addr. Hex Code Value VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1B: --27 2.7 V 1 VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1C: --36 3.3 V 1 VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1D: --B4 11.4 V Offset Length 1Bh 1 1Ch 1Dh Description February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 53 Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 33. System Interface Information (Sheet 2 of 2) Addr. Hex Code Value VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1E: --C6 12.6 V 1 "n" such that typical single word program time-out = 2n s 1F: --05 32 s 1Bh 1 VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1B: --27 2.7 V 1Ch 1 VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1C: --36 3.3 V 1Dh 1 VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1D: --B4 11.4 V 1Eh 1 VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1E: --C6 12.6 V 1Fh 1 "n" such that typical single word program time-out = 2n s 1F: --05 32 s 1Bh 1 VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1B: --27 2.7 V 1Ch 1 VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts 1C: --36 3.3 V 1Dh 1 VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts 1D: --B4 11.4 V 20h 1 "n" such that typical max. buffer write time-out = 2 n s 20: --00 n/a 21h 1 "n" such that typical block erase time-out = 2n ms 21: --0A 1s Offset Length 1Eh 1 1Fh Description n 22h 1 "n" such that typical full chip erase time-out = 2 ms 22: --00 n/a 23h 1 "n" such that maximum word program time-out = 2n times typical 23: --04 512 s 24h 1 "n" such that maximum buffer write time-out = 2n times typical 24: --00 n/a 25h 1 "n" such that maximum block erase time-out = 2n times typical 25: --03 8s 26: --00 NA 26h 12.6 1 n "n" such that maximum chip erase time-out = 2 times typical Device Geometry Definition n Table 34. Device Geometry Definition (Sheet 1 of 2) Code See Table Below Offset Length Description 27h 1 "n" such that device size = 2n in number of bytes 27: 28h 2 Flash device interface: 28: --01 29: --00 2A: --00 2B: --00 x8 async x16 async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 2Ah 2 "n" such that maximum number of bytes in write buffer = 2n Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 54 x16 0 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 34. Offset Device Geometry Definition (Sheet 2 of 2) Length Code See Table Below Description 2Ch 1 Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) 2Dh 4 Erase Block Region 1 Information 2D: bits 0-15 = y, y+1 = number of identical-size erase blocks 2E: bits 16-31 = z, region erase block(s) size are z x 256 bytes 2F: 2C: --02 2 30: 31h 4 Erase Block Region 2 Information 31: bits 0-15 = y, y+1 = number of identical-size erase blocks 32: bits 16-31 = z, region erase block(s) size are z x 256 bytes 33: 34: Device Geometry Definition 16-Mbit 32-Mbit Address 12.7 -B -T -B -T 27: --15 --15 --16 --16 28: --01 --01 --01 --01 29: --00 --00 --00 --00 2A: --00 --00 --00 --00 2B: --00 --00 --00 --00 2C: --02 --02 --02 --02 2D: --07 --1E --07 --3E 2E: --00 --00 --00 --00 2F: --20 --00 --20 --00 30: --00 --01 --00 --01 31: --1E --07 --3E --07 32: --00 --00 --00 --00 33: --00 --20 --00 --20 34: --01 --00 --01 --00 Intel-Specific Extended Query Table Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 55 Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 35. (1) Primary-Vendor Specific Extended Query Offset P = 35h Length (P+0)h 3 (P+1)h Description (Optional Flash Features and Commands) Addr. Hex Code Primary extended query table 35: --50 "P" Unique ASCII string "PRI" 36: --52 "R" 37: --49 "I" 38: --31 "1" "0" (P+2)h (P+3)h 1 Major version number, ASCII (P+4)h 1 Minor version number, ASCII 39: --30 (P+5)h 4 Optional feature and command support (1=yes, 0=no) 3A: --66 (P+6)h bits 9-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. (P+7)h (P+8)h bit 0 Chip erase supported (P+9)h 1 2 (P+B)h 3B: --00 3C: --00 3D: --00 bit 0 = 0 No bit 1 Suspend erase supported bit 1 = 1 Yes bit 2 Suspend program supported bit 2 = 1 Yes bit 3 Legacy lock/unlock supported bit 3 = 0 No bit 4 Queued erase supported bit 4 = 0 No bit 5 Instant individual block locking supported bit 5 = 1 Yes bit 6 Protection bits supported bit 6 = 1 Yes bit 7 Page mode read supported bit 7 = 0 No bit 8 Synchronous read supported bit 8 = 0 No Supported functions after suspend: read array, status, query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend (P+A)h Value 3E: --01 bit 0 = 1 Block status register mask 3F: --03 bits 2-15 are Reserved; undefined bits are "0" 40: --00 Yes bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes bit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes (P+C)h 1 VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts 41: --33 3.3 V (P+D)h 1 VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts 42: --C0 12.0 V Addr. Hex Code Value 43: --01 01 Table 36. Protection Register Information (Sheet 1 of 2) Offset(1) P = 35h Length (P+E)h 1 Description (Optional Flash Features and Commands) Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 56 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 36. (1) Offset P = 35h Protection Register Information (Sheet 2 of 2) (P+F)h (P+10)h 4 (P+11)h Description (Optional Flash Features and Commands) Addr. Hex Code Value Protection Field 1: Protection Description 44: --80 80h This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with deviceunique serial numbers. Others are user programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. 45: --00 00h bits bits bits bits 46: --03 8 byte 47: --03 8 byte Length 0-7 = Lock/bytes JEDEC-plane physical low address 8-15 = Lock/bytes JEDEC -plane physical high address 16-23 = "n" such that 2n = factory pre- programmed bytes 24-31 = "n" such that 2n = user programmable bytes (P+12)h (P+13)h Note: Reserved for future use 48: 1. The variable P is a pointer which is defined at CFI offset 15h. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 57 Intel(R) Advanced+ Boot Block Flash Memory (C3) 13.0 Protection Register Addressing Table 37. Protection Register Addressing Word-Wide Protection Register Addressing Word Use A7 A6 A5 A4 A3 A2 A1 A0 LOCK Both 1 0 0 0 0 0 0 0 0 Factory 1 0 0 0 0 0 0 1 1 Factory 1 0 0 0 0 0 1 0 2 Factory 1 0 0 0 0 0 1 1 3 Factory 1 0 0 0 0 1 0 0 4 User 1 0 0 0 0 1 0 1 5 User 1 0 0 0 0 1 1 0 6 User 1 0 0 0 0 1 1 1 7 User 1 0 0 0 1 0 0 0 Note: All address lines not specified in the above table must be 0 when accessing the Protection Register--for example, A21-A8 = 0. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 58 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Appendix A Additional Information Please contact your local Intel representation for additional detailed information. Table 38. Related Documents Order Number Document/Tool 292216 AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory 292215 AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture Contact Your Intel Representative Flash Data Integrator (FDI) Software Developer's Kit Appendix B Ordering Information Table 39 shows available M18 with synchronous PSRAM device combinations and additional device details. Note: For devices not listed in this table, contact your local Intel representative. Table 39. Available Product Ordering Information Package I/O Voltage (V) Flash Family (Mbit) and I/O Interface xRAM Type (Mbit) Size (mm) Ballout Name Ball Type 8x10x1.2 I RoHS Part Number Add'l Detail Notes PF38F1030C0ZTL0 -- M18 90 nm 1.8 32 C3 (Non-Mux) February 2007 Document Number: 252636-005US 16 Async PSRAM Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 59 Intel(R) Advanced+ Boot Block Flash Memory (C3) Appendix C SRAM Information, Not for New Designs This appendix contains the SRAM specifications for the memory solutions are offered in the following combinations: * 32-Mbit flash + 8-Mbit SRAM * 32-Mbit flash + 4-Mbit SRAM * 16-Mbit flash + 4-Mbit SRAM * 16-Mbit flash memory + 2-Mbit SRAM C.1 Product Overview The C3 SCSP device combines flash memory and SRAM into a single package, which provides secure low-voltage memory solutions for portable applications. Table 40. Block Organization (x16) Memory Device 32-Mbit Flash 2048 16-Mbit Flash 1024 2-Mbit SRAM 128 4-Mbit SRAM 256 8-Mbit SRAM 512 Note: Figure 19. Kwords All words are 16 bits each. Intel(R) Advanced+ Boot Block SCSP Block Diagram F-VCC F-OE# F-CE# F-WP# F-RP# Flash 28F160C3 or 28F320C3 A[Max:0] S-VCC S-CS1 F-VCCQ F-WE# F-VPP F-VSS D[15:0] SRAM 2-, 4- or 8-Mbit S-VSS S-WE# S-CS2 S-UB# S-OE# S-LB# Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 60 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) C.2 Mechanical Specification A1 Index 1 2 S2 3 4 5 6 7 8 9 10 11 12 12 11 10 9 8 7 6 5 4 3 2 E S1 1 A A B B C C D D E E F F G G H H b e D Top View - Ball Down Bottom View - Ball Up A2 A Y A1 Note: Table 41. Shaded pins indicate upper address balls for 64-Mbit and 128-Mbit devices. In all Flash and SRAM combinations, 66 balls are populated on lower density devices. (Upper address balls are not populated). Packaging Specifications (0.18m and 0.25m) (Sheet 1 of 2) Millimeters Sym Package Height A1 Package Body Thickness A2 b Package Body Length - 16-Mbit/2-Mbit Package Body Length - 32-Mbit/4-Mbit, 16-Mbit/4-Mbit D Package Body Length - 32-Mbit/8-Mbit Package Body Width - 16-Mbit/2-Mbit, 16-Mbit/4-Mbit, 32-Mbit/4-Mbit, 32-Mbit/8-Mbit Nom A Ball Height Ball Lead Diameter Min E Inches Max Min Nom 1. 400 0.250 Max 0.0551 0.0098 0.960 0.0378 0.350 0.400 0.450 0.0138 0.0157 0.0177 9.900 10.00 10.100 0.3898 0.3937 0.3976 11.900 12.000 12.100 0.4685 0.4724 0.4764 13.900 14.000 14.100 0.5472 0.5512 0.5551 7.900 8.000 8.100 0.3110 0.3150 0.3189 Pitch e 0.800 0.0315 Ball (Lead) Count N 66 66 Seating Plane Coplanarity Y 0.100 0.0039 Corner to Ball A1 Distance Along E 16-Mbit/2-Mbit, 16-Mbit/4-Mbit, 32-Mbit/4-Mbit, 32-Mbit/8-Mbit February 2007 Document Number: 252636-005US S1 1.100 1.200 1.300 0.0433 0.0472 0.0512 Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 61 Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 41. Packaging Specifications (0.18m and 0.25m) (Sheet 2 of 2) Millimeters Sym Corner to Ball A1 Distance Along D 16-Mbit/2-Mbit Corner to Ball A1 Distance Along D 32-Mbit/4-Mbit, 16-Mbit/4-Mbit S2 Corner to Ball A1 Distance Along D 32-Mbit/8-Mbit Inches Min Nom Max Min Nom Max 0.500 0.600 0.700 0.0197 0.0236 0.0276 1.500 1.600 1.700 0.0591 0.0630 0.0669 2.500 2.600 2.700 0.0984 0.1024 0.1063 Millimeters Sym Package Height 16/02-Mb, 16/04-Mb, 32/08-Mb Package Height 32/04-Mb Ball Height 16/02-Mb, 16/04-Mb, 32/08-Mb Ball Height 32/04-Mb Package Body Thickness 16/02-Mb, 16/04-Mb, 32/08-Mb Package Body Thickness 32/04-Mb Ball (Lead) Width 16/02-Mb, 16/04-Mb, 32/08-Mb Ball (Lead) Width 32/04-Mb Package Body Length 16/02-Mb, 16/04-Mb Package Body Length 32/04-Mb, 32/08-Mb Package Body Width 16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb Min Nom Inches Max Min Nom Max 1. 200 0.0472 1. 400 0.0551 A 0.200 0.0079 0.250 0.0098 A1 0.860 0.0339 0.960 0.0378 A2 0.325 0.375 0.425 0.0128 0.0148 0.0167 0.350 0.40 0.450 0.0138 0.0157 0.0177 9.900 10.000 10.100 0.3898 0.3937 0.3976 11.900 12.000 12.100 0.4685 0.4724 0.4764 7.900 8.000 8.100 0.3110 0.3150 0.3189 b D E Pitch e 0.800 0.0315 Ball (Lead) Count N 66 66 Seating Plane Coplanarity Y 0.100 0.0039 Corner to Ball A1 Distance Along E 16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb S1 1.100 1.200 1.300 0.0433 0.0472 0.0512 Corner to Ball A1 Distance Along D 16/02-Mb, 16/04-Mb S2 0.500 0.600 0.700 0.0197 0.0236 0.0276 Corner to Ball A1 Distance Along D 32/04-Mb, 32/08-Mb S2 1.500 1.600 1.700 0.0591 0.0630 0.0669 Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 62 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) C.3 Media Information Device Pin 1 Tray Chamfer Note: Top view, ball side down. Drawing is not to scale and is only designed to show orientation of devices. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 63 Intel(R) Advanced+ Boot Block Flash Memory (C3) Figure 20. SCSP Device in 24 mm Tape (10 mm x 8 mm and 12 mm x 8 mm) Device Pin 1 Note: Top view, ball side down. C.4 Ballout and Signals C.4.1 Ballout Figure 21. 66-Ball SCSP Package Ballout 1 2 3 4 5 6 7 A20 A11 A15 A14 A13 A16 A8 A10 A9 F-WE# NC A21 8 9 10 11 12 A NC A12 F-VSS F-VCCQ NC B DQ15 S-WE# DQ14 DQ7 C DQ13 DQ6 DQ4 DQ5 D S-VSS F-RP# A22 E F-WP# F-VPP A19 DQ12 S-CS2 S-VCC F-VCC DQ11 DQ10 DQ2 DQ3 DQ9 DQ8 DQ0 DQ1 F S-LB# S-UB# S-OE# G A18 A17 A7 A6 A3 A2 A1 S-CS1# NC A5 A4 A0 F-CE# F-VSS F-OE# NC H NC NC Top View, Balls Down Notes: 1. Flash memory upgrade balls are shown up to A21 (64-Mbit flash) and A22 (128-Mbit flash). In all flash memory and PSRAM combinations, 66 balls are populated on lower density devices. (Upper address balls are not populated). Ball location A10 is NC on 16/2 devices only. 2. To maintain compatibility with all JEDEC Variation B options for the C6 ball location, connect this C6 land pad directly to the land pad for the G4 (A17) ball. Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 64 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) C.4.2 Signal Descriptions Table 42. Intel(R) Advanced+ Boot Block SCSP Ball Descriptions (Sheet 1 of 2) Symbol Type Name and Function INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. 2-Mbit : A[16:0] 4-Mbit : A[18:0] 16-Mbit : A[19:0] 32-Mbit A[20:0] INPUT / OUTPUT DATA INPUTS/OUTPUTS: Inputs array data for SRAM write operations and on the second F-CE# and F-WE# cycle during a flash program command. Inputs commands to the flash memory Command User Interface when F-CE# and F-WE# are asserted. Data is internally latched. Outputs array, configuration, and status register data. The data balls float to tristate when the chip is deselected or the outputs are disabled. INPUT FLASH CHIP ENABLE: Activates the flash internal control logic, input buffers, decoders, and sense amplifiers. F-CE# is active low. F-CE# high deselects the flash memory device and reduces power consumption to standby levels. INPUT SRAM CHIP SELECT1: Activates the SRAM internal control logic, input buffers, decoders, and sense amplifiers. S-CS1# is active low. S-CS1# high deselects the SRAM memory device and reduces power consumption to standby levels. S-CS2 INPUT SRAM CHIP SELECT2: Activates the SRAM internal control logic, input buffers, decoders, and sense amplifiers. S-CS2 is active high. S-CS2 low deselects the SRAM memory device and reduces power consumption to standby levels. F-OE# INPUT FLASH OUTPUT ENABLE: Enables flash memory outputs through the data buffers during a read operation. F-OE# is active low. S-OE# INPUT SRAM OUTPUT ENABLE: Enables SRAM outputs through the data buffers during a read operation. S-OE# is active low. F-WE# INPUT FLASH WRITE ENABLE: Controls writes to the flash memory command register and memory array. F-WE# is active low. Addresses and data are latched on the rising edge of the second F-WE# pulse. S-WE# INPUT SRAM WRITE ENABLE: Controls writes to the SRAM memory array. S-WE# is active low. S-UB# INPUT SRAM UPPER BYTE ENABLE: Enables the upper byte for SRAM (DQ 8-DQ 15). S-UB# is active low. S-LB# INPUT SRAM LOWER BYTE ENABLE: Enables the lower byte for SRAM (DQ0-DQ7). S-LB# is active low. INPUT FLASH RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep power-down mode. When F-RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD ). When F-RP# is at logic high, the device is in standard operation. When F-RP# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. A[20:0] DQ[15:0] F-CE# S-CS1# F-RP# February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 65 Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 42. Symbol Intel(R) Advanced+ Boot Block SCSP Ball Descriptions (Sheet 2 of 2) Type Name and Function F-WP# INPUT FLASH WRITE PROTECT: Controls the lock-down function of the flexible Locking feature. When F-WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. After F-WP# goes low, any blocks previously marked lock-down revert to that state. When F-WP# is logic high, the lock-down mechanism is disabled. Blocks previously locked-down are now locked, and can be unlocked or locked through software. F-VCC SUPPLY FLASH POWER SUPPLY: [2.7 V-3.3 V] Supplies power for device core operations. F-VCCQ SUPPLY FLASH I/O POWER SUPPLY: [2.7 V-3.3 V] Supplies power for device I/O operations. S-VCC SUPPLY SRAM POWER SUPPLY: [2.7 V-3.3 V] Supplies power for device operations. F-VPP INPUT / SUPPLY FLASH PROGRAM/ERASE POWER SUPPLY: [1.65 V-3.3 V or 11.4 V-12.6 V] Operates as an input at logic levels to control complete flash memory protection. Supplies power for accelerated flash memory program and erase operations in 12 V 5% range. This ball cannot be left floating. Lower F-VPP VPPLK, to protect all contents against Program and Erase commands. Set F-VPP = F-V CC for in-system read, program and erase operations. In this configuration, F-VPP can drop as low as 1.65 V to allow for resistor or diode drop from the system supply. If F-VPP is driven by a logic signal, then VIH = 1.65 V. That is, F-VPP must remain above 1.65 V to modify in-system flash memory. Raise F-VPP to 12 V 5% for faster program and erase in a production environment. 12 V 5% to F-VPP can be applied for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-VPP can be connected to 12 V for a total of 80 hours maximum. F-VSS SUPPLY S-VSS SUPPLY NC C.5 FLASH GROUND: For all internal circuitry. All ground inputs must be connected. SRAM GROUND: For all internal circuitry. All ground inputs must be connected. NOT CONNECTED: Internally disconnected within the device. Bus Operation All bus cycles to or from the SCSP conform to standard microcontroller bus cycles. Four control signals dictate the data flow in and out of the flash component: * F-CE# * F-OE# * F-WE# * F-RP# Four separate control signals handle the data flow in and out of the SRAM component: * S-CS1# * S-CS2 * S-OE# * S-WE# The flash memory device provides four read modes: * Read array * Read identifier * Read status * CFI query Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 66 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) These flash memory read modes do not depend on the F-VPP voltage. Upon initial device power-up or after exit from reset, the flash memory device automatically defaults to read array mode. F-CE# and F-OE# must be asserted to obtain data from the flash memory device. The SRAM provides only one read mode. S-CS1#, S-CS2, and S-OE# must be asserted to obtain data from the SRAM device. Intel Advanced+ Boot Block Flash Memory SCSP Bus Operations L H Write H L H L Standby H H X X Output Disable H L H H Reset L X X X Read FLASH must be in High Z SRAM Write Standby Output Disable Any FLASH mode is allowable Data Retention SRAM must be in High Z Any SRAM mode is allowable Memory Bus Control F-WE# L S-UB#,S-LB#(1) F-OE1# H S-WE# F-CE# Read S-OE1# F-RP# FLASH Modes Memory Output SRAM Signals S-CS1# Flash Signals S-CS2 Table 43. D0- D15 Flash DOUT 2,3,4 Flash DIN 2,4 Other High Z 5,6 Other High Z 5,6 Other High Z 5,6 Notes L H L H L SRAM DOUT 2,4 L H H L L SRAM DIN 2,4 H X X X X X L X X X Other High Z 4,5,6 H H H X Other High Z 4,5,6 Other High Z 4,5,7 L same as a standby Notes: 1. Two devices cannot drive the memory bus at the same time. 2. To place the SRAM into data retention mode, lower the S-VCC signal to the VDR range, as specified. C.5.1 Output Disable When F-OE# and S-OE# are deasserted, the SCSP output signals are placed in a highimpedance state. C.5.2 Standby When F-CE# and S-CS1# or S-CS2 are deasserted, the SCSP enters a standby mode, which substantially reduces device power consumption. In standby mode, outputs are placed in a high-impedance state independent of F-OE# and S-OE#. If the flash memory device is deselected during a program or erase operation, the flash memory continues to consume active power until the program or erase operation is complete. C.5.3 Flash Reset The flash memory device enters a reset mode when RP# is driven low. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 67 Intel(R) Advanced+ Boot Block Flash Memory (C3) After returning from reset, a time tPHQV is required until outputs are valid. A delay (tPHWL or tPHEL) is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored. * The flash memory device defaults to read array mode. * The status register is set to 80h. * The read configuration register defaults to asynchronous reads. If RP# is taken low during a block erase or program operation, the operation aborts and the memory contents at the aborted location are no longer valid. C.5.4 Write * Writes to flash memory occur when both F-CE# and F-WE# are asserted and FOE# is deasserted. * Writes to SRAM occur when both S-CS1# and S-WE# are asserted and S-OE# and S-CS2 are deasserted. Commands are written to the flash memory Command User Interface (CUI), using standard microprocessor write timings to control flash memory operations. The CUI does not occupy an addressable memory location within the flash memory device. The address and data buses are latched on the rising edge of the second F-WE# or F-CE# pulse, whichever occurs first. C.6 Absolute Maximum Ratings Warning: Stressing the device beyond the Absolute Maximum Ratings might cause permanent damage. These are stress ratings only. Do not operate the flash memory device beyond the Operating Conditions. Extended exposure beyond these Operating Conditions might affect device reliability. NOTICE: This datasheet contains information on products in full production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design . Table 44. Absolute Maximum Ratings Parameter Maximum Rating Notes Extended Operating Temperature During Read During Flash Block Erase and Program -25C to +85C Temperature under Bias Storage Temperature -65C to +125C Voltage on Any Ball (except F-VCC /F-VCCQ / S-VCC and F-VPP) with Respect to GND -0.5 V to +3.3 V 1 F-VPP Voltage (for Block Erase and Program) with Respect to GND -0.5 V to +13.5 V 1,2,4 Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 68 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 44. Absolute Maximum Ratings Parameter Maximum Rating F-VCC / F-VCCQ / S-VCC Supply Voltage with Respect to GND -0.2V to +3.3 V Output Short Circuit Current 100 mA Notes: 1. 2. 3. 4. Notes 3 Minimum DC voltage is -0.5 V on input/output balls. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output balls is F-VCC / F-VCCQ / S-VCC + 0.5 V which, during transitions, may overshoot to F-VCC / F-VCCQ / S-VCC + 2.0 V for periods < 20 ns. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns. F-VPP voltage is normally 1.65 V-3.3 V. Connection to supply of 11.4 V-12.6 V can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. FVPP may be connected to 12 V for a total of 80 hours maximum. Output shorted for no more than one second. No more than one output shorted at a time. C.7 Operating Conditions Table 45. Maximum Operating Conditions Symbol Parameter Notes Min Max Units -25 +85 C TCASE Operating Temperature VCC / VCCQ F-VCC /F-VCCQ /S-VCC Supply Voltage 1 2.7 3.3 Volts VPP1 Supply Voltage 1 1.65 3.3 Volts 1, 2 11.4 12.6 2 100,000 VPP2 Cycling Block Erase Cycling Volts Cycles Notes: 1. F-VCC/F-VCCQ must share the same supply. F-VCC/S-VCC must share the same supply when not in data retention. 2. Applying F-VPP = 11.4 V-12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V for a total of 80 hours maximum. C.8 Capacitance TCASE = +25C, f = 1 MHz Table 46. Capacitance Sym Parameter Notes Typ Max Units Conditions CIN Input Capacitance 1 16 18 pF VIN = 0 V COUT Output Capacitance 1 20 22 pF VOUT = 0 V Note: Sampled, not 100% tested. February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 69 Intel(R) Advanced+ Boot Block Flash Memory (C3) C.9 Electrical C.9.1 SRAM DC Characteristics Note: All currents are in RMS unless otherwise noted. Typical values at nominal P-VCC, TCASE = +25 C. Table 47. SRAM DC Characteristics 2.7 V - 3.3 V Symbol Parameter Device Unit Typ Max Test Conditions ILI Input Load Current -- -- 2 A F-VCC/S-VCC = VCC Max VIN = VCCMax or GND ILO Output Leakage Current -- 0.2 10 A F-VCC/S-VCC = VCC Max VIN = VCC Max or GND 2-Mb SRAM -- 10 A 4-Mb SRAM -- 15 A 8-Mb SRAM -- 25 A 2-Mb SRAM -- 7 mA 4-Mb SRAM -- 10 mA 8-Mb SRAM -- 10 mA 2-Mb SRAM -- 40 mA 4-Mb SRAM -- 45 mA 8-Mb SRAM -- 50 mA ICCS ICC ICC2 Table 48. VCC Standby Current Operating Power Supply Current (cycle time = 1 s) Operating Power Supply Current (min cycle time) S-VCC = VCC Max S-CS1# = VCC, S-CS2 = VCC or S-CS2 = GND VIN = VCC Max or GND IIO = 0 mA, S-CS1# = VIL S-CS2 = S-WE# = VIH VIN = VIL or VIH Cycle time = Min, 100% duty, IIO = 0 mA, S-CS1# = VIL, S-CS2 = VIH, VIN = VIL or VIH SRAM Voltage Characteristics 2.7 V - 3.3 V Symbol Parameter Device Units Min Test Conditions Max VIL Input Low Voltage -- -0.2 0.6 V -- VIH Input High Voltage -- 2.3 VCC +0.2 V -- VOL Output Low Voltage -- -0.10 0.10 V F-VCC /S-VCC = VCC Min IOL = 100 A VOH Output High Voltage -- VCC -0.1 -- V F-VCC /S-VCC = VCC Min IOH = -100 A Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 70 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) C.9.2 SRAM AC Characteristics--Read Operations Table 49. SRAM AC Characteristics--Read Operations # Sym Parameter Density 2/4/8-Mbit Voltage Range 2.7 V- 3.3 V Note Min Max 70 - ns R1 tRC Read Cycle Time R2 tAA Address to Output Delay - 70 ns R3 tCO1, tCO2 S-CS1#, S-CS2 to Output Delay - 70 ns R4 tOE S-OE# to Output Delay - 35 ns R5 tBA S-UB#, LB# to Output Delay - 70 ns R6 tLZ1, tLZ2 S-CS1#, S-CS2 to Output in Low Z R7 tOLZ S-OE# to Output in Low Z R8 tHZ1, tHZ2 S-CS1#, S-CS2 to Output in High Z R9 tOHZ S-OE# to Output in High Z R10 tOH Output Hold from Address, S-CS1#, S-CS2, or S-OE# Change, Whichever Occurs First R11 tBLZ S-UB#, S-LB# to Output in Low Z R12 tBHZ S-UB#, S-LB# to Output in High Z Note: 1. 2. 3. Unit 1,2 5 - ns 2 0 - ns 1,2,3 0 25 ns 2,3 0 25 ns 0 - ns 2 0 - ns 2 0 25 ns At any given temperature and voltage condition, tHZ (Max) is less than and tLZ (Max) both for a given device and from device to device interconnection. Sampled, but not 100% tested. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. Figure 22. AC Waveform: SRAM Read Operations Standby VIH ADDRESSES (A) Device Address Selection Address Stable VIL R1 VIH CS1# (E1) Data Valid VIL VIH CS2 (E2) OE# (G) R3 VIL R2 R8 VIH VIL WE# (W) DATA (D/Q) VIL VOH VOL UB#, LB# February 2007 Document Number: 252636-005US R9 VIH VIH R7 High Z R6 R4 R10 High Z Valid Output R11 R5 R12 VIH Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 71 Intel(R) Advanced+ Boot Block Flash Memory (C3) C.9.3 SRAM AC Characteristics--Write Operations A write occurs during the overlap (tWP) of low S-CS1# and low S-WE#. A write begins when S-CS1# goes low and S-WE# goes low with asserting S-UB# or S-LB# for single byte operation or simultaneously asserting S-UB# and S-LB# for double byte operation. A write ends at the earliest transition when S-CS1# goes high and S-WE# goes high. The tWP is measured from the beginning of write to the end of write. Table 50. SRAM AC Characteristics--Write Operations Density # Sym Parameter Volt Note W1 2/4/8-Mbit 2.7 V - 3.3 V Unit Min Max 70 - ns tWC Write Cycle Time W2 tAS Address Setup to S-WE# (S-CS1#) and S-UB#, S-LB# Going Low 1 0 - ns W3 tWP S-WE# (S-CS1#) Pulse Width 2 55 - ns W4 tDW Data to Write Time Overlap 30 - ns W5 tAW Address Setup to S-WE# (S-CS1#) Going High 60 - ns W6 tCW S-CE# (S-WE#) Setup to S-WE# (S-CS1#) Going High 60 - ns 0 - ns 0 - ns 60 - ns W7 tDH Data Hold Time from S-WE# (S-CS1#) High W8 tWR Write Recovery W9 tBW S-UB#, S-LB# Setup to S-WE# (S-CS1#) Going High 3 Notes: 1. tAS is measured from the address valid to the beginning of write. 2. tWP is measured from S-CS1# going low to end of write. 3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CS1# or S-WE# going high. Figure 23. AC Waveform: SRAM Write Operations Standby VIH ADDRESSES (A) Device Address Selection Address Stable VIL W1 VIH CS1# (E1) W8 VIL VIH CS2 (E2) OE# (G) VIL W6 VIH W5 VIL WE# (W) W3 VIH VIL W7 W4 DATA (D/Q) VOH High Z W2 VIH UB#, LB# Data In High Z VOL W9 VIH Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 72 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) C.9.4 SRAM Data Retention Characteristics--Extended Temperature Table 51. SRAM Data Retention Characteristics(1)--Extended Temperature Sym Min Typ Max Unit S-VCC for Data Retention 1.5 - 3.3 V Deep Retention Current 8-Mbit - - 6 A - - 5 A Deep Retention Current 2-Mbit - - 4 A tSDR Data Retention Set-up Time 0 - - ns tRDR Recovery Time tRC - - ns VDR IDR Parameter Note 2 Deep Retention Current 4-Mbit Test Conditions CS1# VCC - 0.2 V S-VCC = 1.5 V CS1# VCC - 0.2 V See Data Retention Waveform Notes: 1. Typical values at nominal S-VCC , TCASE = +25 C. 2. S-CS1# VCC - 0.2 V, S-CS2 VCC - 0.2 V (S-CS1# controlled) or S-CS2 0.2 V (S-CS2 controlled). Figure 24. SRAM Data Retention Waveform CS1# Controlled tSDR Data Retention Mode tRDR VCC 3.0/2.7V CS1# (E1) 2.2V VDR GND CS2 Controlled tSDR Data Retention Mode tRDR VCC 3.0/2.7V CS2 (E2) VDR 0.4V GND February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 73 Intel(R) Advanced+ Boot Block Flash Memory (C3) C.10 SRAM Order Information . Table 52. Ordering Information for Product Combinations with 0.25 m to 0.13 m Flash R D 2 8 F 1 6 0 2 C 3 T D 7 0 Package 16 Mbit = 70, 90 , or 110 ns 32 Mbit = 70 or 90 ns Product Line Designator Technology Differentiator (R) 28F or 38F = Intel Flash Memory Flash Density 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) SRAM Device Density 8 = x16 (8 Mbit) 4 = x16 (4 Mbit) 2 = x16 (2 Mbit) Table 53. Access Speed (ns) RD = Leaded Ball Stacked -CSP PF = Lead -Free Ball Stacked-CSP D = 0.13m <blank> = 0.25m or 0.18 m (refer to access speed for differientation) Parameter Location T = Top Blocking B = Bottom Blocking Product Family C = Advanced+ Boot Block Flash Memory Ordering Information for Combinations specific to 32M 0.13 m Flash R D 3 8 F 1 0 1 0 C 0 Z T L 0 Package RD = Leaded Ball Stacked -CSP PF = Lead -Free Ball Stacked-CSP Product Line Designator 38 F = Intel(R) Flash Stacked Memory Device Details 0 = Original Version of this product: Flash Speed = 70 ns Flash Process = 0.13 m Vccq = 2.7 V to 3 .3 V Density Flash #1 = 1 = 32 Mbit Flash #2 = 0 = No Die Flash #3 = 1 = 4 Mbit SRAM = 2 = 8 Mbit SRAM Flash #4 = 0 = No Die Product Family C = Advanced+ Boot Block Flash Memory Pinout Indicator L = 72 ball "I"-ballout Parameter Location T = Top Blocking B = Bottom Blocking Voltage Z = 3.0 V I/O Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 74 February 2007 Document Number: 252636-005US Intel(R) Advanced+ Boot Block Flash Memory (C3) Table 54. Ordering Information Valid Combinations 0.25m C3 SCSP 0.18m C3 SCSP 32-Mbit No longer available. RD28F3208C3T70 RD28F3208C3B70 RD28F3208C3T90 RD28F3208C3B90 RD28F3204C3T70 RD28F3204C3B70 16-Mbit RD28F1604C3T90 RD28F1604C3B90 RD28F1604C3T110 RD28F1604C3B110 RD28F1602C3T90 RD28F1602C3B90 RD28F1602C3T110 RD28F1602C3B110 RD28F1602C3T70 RD28F1602C3B70 February 2007 Document Number: 252636-005US 0.13m C3 SCSP RD38F1010C0ZTL0 RD38F1010C0ZBL0 PF38F1010C0ZTL0 PF38F1010C0ZBL0 RD38F1020C0ZTL0 RD38F1020C0ZBL0 PF28F1602C3TD70 RD28F1602C3TD70 RD28F1602C3BD70 RD28F1604C3TD70 RD28F1604C3BD70 Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 75 Intel(R) Advanced+ Boot Block Flash Memory (C3) Intel(R) Advanced+ Boot Block Flash Memory (C3) SCSP Family DS 76 February 2007 Document Number: 252636-005US