Document Numb er: 252636-005US
February 2007
Intel® Advanced+ Boot Block Flash Memory
(C3)
C3 SC SP
Datasheet
Product Features
Device Architecture
— Flash Density: 16-, 32-M bit
— Async PSRAM Density: 16-Mb it
Devi ce Voltage
—Flash V
CC = 3.3 V; Flash VCCQ = 3.3 V
— PSRAM VCC = 3.0 V; Fla sh VCCQ = 3.0 V
Flash Memory Plus PSRAM
— Redu ces Memory Bo ar d S pace Requir ed,
Simplify ing P CB Design Com plexity
Device Packaging
— 66 balls (8 x 10 x 1.2 mm)
Advance d SRAM Technology
— 70 ns Access Time
—Low Power Operation
— Low Volt age Da ta Retent ion Mo de
Flas h Tec h nologi es
— 0.25 µm ETOX™ VI, 0.18 µm ETOX™ VII
and 0 .1 3 µm E TOX™ VIII Flash
Technologies
Advanced+ Boot Blo ck Fl ash Me mo ry
— 70 ns Access Time
— Instant, Individual Block Locking
— 128 bit Protection Re gister
— 12 V Production Progr amming
— Fast Program and Erase Suspend
— Extended Tem peratu r e –25 °C to + 85 °C
Blocking Architectu re
— Block Sizes for Code + Data S torage
— 4-Kword Par ameter Blocks
— 64-Kbyte Ma in Blo cks
— 100,000 Erase Cycles per Block
Low Power Operation
— Asynchronous Read Current: 9 mA (Flash)
— Standby Current: 7 µA (Flash)
Autom a tic Power Savin g Mod e
Intel® Flash Data Integrator (FDI) Software
— Real- Time Data Storage and Code Execution
in the Same Memory Devic e
— Full Fl ash File Manag er C ap a bility
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
DS February 2007
2Document Number: 252636-005US
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Copy right © 2007, Intel Corporation. All Rights Reserved.
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
February 2007 DS
Document Number: 252636-005US 3
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
Contents
1.0 Introduction..............................................................................................................6
1.1 Docum ent Co nve n tions ....................... ........ ............... .............................. ............6
1.2 Product Overview....................... ........ ............... ............................... ...................6
2.0 Functional Overview..................................................................................................8
2.1 Block Dia gra m ............ ............................... .............................. ...........................8
2.2 Memor y Ma p ............... ........ ............... .............................. ............................... ....9
2.3 Device ID Table ................................................................................................14
3.0 Package Information...............................................................................................15
4.0 Ballout and Signal Descriptions ...............................................................................16
4.1 Ballout.............................................................................................................16
4.2 Signal Descr i pt ion s............................. .............................. ............................... .. 16
5.0 Maximum Ratings and Operating Conditions............................................................18
5.1 Absolut e Ma ximum R ating s... .............................. ............................... .................18
5.2 Opera ting Cond it ions ... ............................... .............................. ........ ............... ..18
6.0 Electri cal Speci fic ati ons...........................................................................................19
7.0 AC Characteristics ...................................................................................................23
7.1 Flash AC Characteristics—Read Operations ...........................................................23
7.2 Flas h AC Cha ract erist ics—W rit e O pe rat ions.................................. .........................24
7.3 Flas h AC Char acterist ics—Erase and Pro gram Timing s ........................... ................. 25
7.4 Flash AC Characteristics—Reset Operations...........................................................27
7.5 PSRAM AC Characteristics—Read Operations.........................................................27
7.6 PSRAM AC Characteristics—Write Operations.........................................................29
8.0 Bus Operation..........................................................................................................31
8.0.1 Read ....................................................................................................31
8.0.2 Output Disabl e......... .............................. ............................... ....... ..........32
8.0.3 Standby................................................................................................32
8.0.4 Flash Reset .................... ........ ............... ............................... ................. 32
8.0.5 Write.................................................................................................... 33
9.0 Flash Operations ..................................................................................................... 34
9.1 Read Array (FFh)...............................................................................................34
9.2 Read Identifier (90h) .........................................................................................34
9.3 Read Status Register (70h).................................................................................35
9.3.1 Clear Status Register (50h) ..................................................................... 35
9.4 CFI Quer y (98h).. ............................... .............................. ................ ....... ..........36
9.5 Word Pr ogra m (40h/10h) ............ ............................... .............................. ........ .. 36
9.5.1 Suspending and Resuming Program (B0h/D0h) ..........................................37
9.6 Block Er ase (20h)................ ....... ................ .............................. ......................... 37
9.6.1 Suspending and Resuming Erase (B0h/D0h) ..............................................38
9.7 Block Locking..................................... .............................. ............................... .. 40
9.7.1 Block Locking Opera tion Summary..... ............... .............................. ........ .. 40
9.7.2 Locked State .........................................................................................40
9.7.3 Unlocked State ......................................................................................40
9.7.4 Lock-Down Sta t e..................... .............................. ............................... .. 41
9.7.5 Reading Lock St at us for a Block ............... ............... ............................... .. 41
9.7.6 Locking Oper atio n During Erase Susp end.......................... .........................41
9.7.7 Status Regist er Er ro r Chec king.......... ....... ............... ............................... ..42
9.8 128 Bit Pro tect ion Re gi ste r .......................... .............................. .........................42
9.8.1 Reading the P ro te ction R eg ister....................................... .........................42
Intel® Advanced+ Boot Block Flash Memory (C3)
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
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9.8.2 P ro gramming the Protection R egiste r (C0h).......... .............................. ........43
9.8.3 L o cking the Prote ction R egiste r................... ........ ............... .......................43
10.0 Power and Reset Considerations..............................................................................44
10.1 Power-Up/Down Characteristics ...........................................................................44
10.2 Additional Flash Features ....................................................................................44
10.2.1 Improved 12 Volt Production Programming ................................................44
10.2.2 F-VPP ≤ VPP L K for Compl ete Prote cti on .. ............... .............................. ........44
11. 0 Pro gr am/ Er ase Fl owc h ar ts ......................................................................................45
12.0 CFI Query Structure.................................................................................................51
12.1 Query Str ucture Out put ......................... .............................. ........ ............... ........51
12.2 Query Str ucture Overview.............. ............................... .............................. ........52
12.3 Block Lock Status Register ..................................................................................52
12.4 CFI Query Identification String ............................................................................53
12.5 System Inte rfa ce In formation.. ............... .............................. ...............................53
12.6 Device Geometry Defi nition.................... ........ ............... .............................. ........54
12.7 Intel-Sp ecif ic Exte nded Qu ery Ta b le ........ ............... ............................... ...............55
13.0 Protection Register Addressing................................................................................58
A Additional Information .............................................................................................59
B Ordering Information...............................................................................................59
C SRAM Information, Not for New Designs..................................................................60
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
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Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
Revision Hist ory
Date Revision Description
02/11/03 -001 Initial release, Stacked Chip Scale Package
01/29/04 -002 M inor text edits.
03/05 -003 Updated Ordering Information figures and table in Appendix H.
26 Aug 2005 -004 Updated Ordering Information to add PF28F1602C3TD70.
February 2007 005 Moved SRAM information to an Appendix
Adde d PSRAM information.
Intel® Advanced+ Boot Block Flash Memory (C3)
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
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1.0 Introduction
This document contains the specifications for the Intel ® Advanced+ Boot Block Flash
Memo ry (C 3) St acked C hip Scale Pac kage (SCSP) devi ce. C 3 SCSP m emo ry so lutions
are o ffered in the followin g com bina t io ns :
• 32-Mbi t flash + 16-M bit PSRAM
The Intel® Advanced+ Boot Block Flash Memory (C3) Stacked Chip Scale Package
(SCSP) device delivers a feature-rich solution for low-power applications. The C3 SCSP
memory device incorpor ates flash memory and P SRAM in one package with low v oltage
capability to achiev e the smallest system memory solution form-factor together with
high-speed, low-power operations. The C3 SCSP memory device offers a protection
regist er and flexible b loc k lockin g to enable next generatio n secur ity capab ility.
Combined with the Intel® Flash Da ta Integrat or (Intel® FDI ) s o ftwar e, th e C 3 S C SP
memory device pr ovides a cost-effective, flexib l e, c o de plus data st orage so lution.
1.1 Document Conventions
Throughout this document, the following conventions have been adopted.
•Voltages:
— 2.7 V refers to the full voltage range, 2.7 V–3.3V
— 12 V refers to 11.4 V to 12.6 V
• Main block(s ) : 32 - Kw o rd bl ock
• Parameter block(s): 4-Kword block
• Flash Signal Names: Flash sign als names may include an F- prefix.
• PSRAM Signal Names: PSRAM signal names ma y i nclude prefixe s : R- or P- (RAM or
PSRAM). In Fi gu r e 3 , “6 6-Ball SCSP Packag e Ballout” on page 16 P SRAM sig nal s
inc lude an S- prefix becaus e SRA M and PS RAM ba llo u ts ar e intercha n ge able.
Note: Flash an d RA M s i gn al na m es in Table 6, “Signal D escrip tions, NOR Flash ” on pa ge 17
and in T able 7, “Signal Descriptions - x16 PSRAM Memory Die” on page 17 respectively
ar e gener ic a n d th eref o r e do n o t in c lu de prefixe s .
1.2 Product Overview
The C3 SCSP device combines flash memory and PSRAM into a single package, which
provide s secure lo w-voltage m emor y so lut io ns for porta b le app lica tio ns.
T h e fl ash m e m ory prov ides th e follow i n g fea tu re s :
• Enhanced security.
• Instant locking/unlocking of any flash block with zero-latency
• A 128-bit protection reg ist er that enabl es uniqu e device ident ifi cation, to meet the
needs of next gener a tion portable applications.
• Improved 12 V production programming for increased factory throughput.
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
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The flas h memo ry is asym metric ally-blo cked to en ab le syst em int eg ration of code and
data storage in a single device. Each flash block can be erased independently of the
others up to 100,000 times.
The flash memory has eight 8-KB parameter blocks located at either the top (denoted
by -T suffix) or the bottom (-B suffix) of the address map, to accommodate different
microprocessor protocols for kernel code location.
The r emai n ing flash m e mory is g r oupe d i n to 3 2 - Kw o r d m ain bl o c k s .
Any individu al flash memory bl o c k can be locked or unlocked instantly to pr ovide
complete protection for code or data (see Section 7.3, “Flash AC Characteristics—Erase
and Program Timings” on page 25 for details).
The flash memory contains both a Command User Interface (CUI) and a Write State
Machine (WSM ).
• The CUI is th e interface between the mic ro c o n troller an d th e inte r n al oper ati o n o f
the flash memory.
• The internal WSM automatically executes the algorithms and timings necessary for
pro gram and erase operation s, inclu ding verif icat i o n, th ereb y unbu r d en ing the
microprocessor or microcontroller. To indicate the status of the WSM, the flash
memory status register signifies block erase or word progra m compl etion and
status.
Flash program and erase au tomatio n en ables execut in g pr o g ram and erase operati o n s
using an industry-sta ndard two-write command sequence to the CUI.
• Program op eratio ns a r e perfor m ed in wo r d inc r ements.
• E rase operati o ns erase all loca tion s wit hin a blo ck simu lt ane o us ly.
The system software can suspend both program and erase operations to read from any
oth er flas h b lock. In ad ditio n, data ca n be pr ogr ammed to ano ther fl ash bloc k d uring an
erase sus p en d.
The C3 SCSP memory device offers two low-power savings features to significantly
reduce power consumption:
• A utomatic Power Savings (APS) for flash m emory. The C3 SCSP memory device
automatical l y en ters APS mode after a read cycle comp l etes from the fla s h
memory.
• Stand by mo d e for flas h and PS RA M. This mo d e is initia te d when the syst em
de sele cts the device by driving F-CE# and P-CS# ina ctive.
To r e set the fla sh me m o r y, lo w er th e F-RP# sign al to GN D. Setti n g F-RP# to GND
provides CPU memory reset synchroni zation and additi onal protection a gainst bus noise
that can occur during system reset and power-up/power-down sequences.
Table 1. Block Organization (x16)
Memor y De v i c e Kwor d s
32-Mbit Fl ash 2048
16-Mbit PS RAM 1024
Note: All words are 16 bits each.
Intel® Advanced+ Boot Block Flash Memory (C3)
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
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8Document Number: 252636-005US
2.0 Functional Overview
The flash memory uses a CUI and automated algorithms to simpli fy program and erase
operations. To automate program and erase operations, the WSM handles data and
addres s latches, WE#, and system status requests.
2.1 Block Diagram
Figure 1. Intel® Advanced+ Boot Block SCSP Block Diagram
A[Max:0]
F-VCCQ
F-VPP
F-WE#
D[15:0]
PSRAM
Flash
VSS
F-RP#
F-VCC
F-OE#
F-CE#
F-WP#
P-VCC
P-CS#
R-OE#
R-WE #
R-UB#
R-LB#
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
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2.2 Memory Map
Table 2. 16 and 32 Mbit Memory Addressing (Sheet 1 of 2)
16-Mbit, 32-Mbit Word-Wide Memory Address ing
Top Boot Bottom Boot
Size
(KW) 16-Mbit 32-Mbit Size
(KW) 16-Mbit 32-Mbit
4 FF000-FFFFF 1FF000-1FFFFF 32
4 FE000-FEFFF 1FE000-1FEFFF 32
4 FD000-FDFFF 1FD000-1FDFFF 32
4 FC000-FCFFF 1FC000-1FCFFF 32
4 FB000-FBFFF 1FB000-1FBFFF 32
4 FA000-FAFFF 1FA000-1FAFFF 32
4 F9000-F9FFF 1F9000-1F9FFF 32
4 F8000-F8FFF 1F8000-1F8FFF 32
32 F0000-F7FFF 1F0000-1F7FFF 32
32 E8000-EFFFF 1E8000-1EFFFF 32
32 E0000-E7FFF 1E0000-1E7FFF 32
32 D8000-DFFFF 1D8000-1DFFFF 32
32 D0000-D7FFF 1D0000-1D7FFF 32
32 C8000-CFFFF 1C8000-1CFFFF 32
32 C0000-C7FFF 1C0000-1C7FFF 32
32 B8000-BFFFF 1B8000-1BFFFF 32
32 B0000-B7FFF 1B0000-1B7FFF 32
32 A8000-AFFFF 1A8000-1AFFFF 32
32 A0000-A7FFF 1A0000-1A7FFF 32
32 98000-9FFFF 198000-19FFFF 32
32 90000-97FFF 190000-197FFF 32
32 88000-8FFFF 188000-18FFFF 32
32 80000-87FFF 180000-187FFF 32
32 78000-7FFFF 178000-17FFFF 32
32 70000-77FFF 170000-177FFF 32
32 68000-6FFFF 168000-16FFFF 32
32 60000-67FFF 160000-167FFF 32
Intel® Advanced+ Boot Block Flash Memory (C3)
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32 58000-5FFFF 158000-15FFFF 32
32 50000-57FFF 150000-157FFF 32
32 48000-4FFFF 148000-14FFFF 32
32 40000-47FFF 140000-147FFF 32
32 38000-3FFFF 138000-13FFFF 32
32 30000-37FFF 130000-137FFF 32
32 28000-2FFFF 128000-12FFFF 32
32 20000-27FFF 120000-127FFF 32
32 18000-1FFFF 118000-11FFFF 32
32 10000-17FFF 110000-117FFF 32
32 08000-0FFFF 108000-10FFFF 32
32 00000-07FFF 100000-107FFF 32
32 0F8000-0FFFFF 32
32 0F0000-0F7FFF 32
32 0E8000-0EFFFF 32
32 0E0000-0E7FFF 32
32 0D8000-0DFFFF 32
32 0D0000-0D7FFF 32
32 0C8000-0CFFFF 32
32 0C0000-0C7FFF 32
32 0B8000-0BFFFF 32
32 0B0000-0B7FFF 32
32 0A8000-0AFFFF 32
This column continues on next page This column continues on next page
Table 2. 16 and 32 Mbit Memory Addressing (Sheet 2 of 2)
16-Mbit, 32-Mbit Word-Wide Memory Addressing
Top Boo t Bottom Bo ot
Size
(KW) 16-Mbit 32-Mbit Size
(KW) 16-Mbit 32-Mbit
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
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Table 3. 16 and 32 Mbit Memory Addressing (Sheet 1 of 2)
16-Mbit, 32-Mbit Word-Wide Mem ory Addre ssing
Top Boot Bottom Boot
Size
(KW) 16-Mbit 32-Mbit Size
(KW) 16-Mbit 32-Mbit
32 0A0000-0A7FFF 32
32 098000-09FFFF 32
32 090000-097FFF 32
32 088000-08FFFF 32
32 080000-087FFF 32
32 078000-07FFFF 32
32 070000-077FFF 32
32 068000-06FFFF 32
32 060000-067FFF 32
32 058000-05FFFF 32
32 050000-057FFF 32
32 048000-04FFFF 32
32 040000-047FFF 32
32 038000-03FFFF 32
32 030000-037FFF 32 1F8000-1FFFFF
32 028000-02FFFF 32 1F0000-1F7FFF
32 020000-027FFF 32 1E8000-1EFFFF
32 018000-01FFFF 32 1E0000-1E7FFF
32 010000-017FFF 32 1D8000-1DFFFF
32 008000-00FFFF 32 1D0000-1D7FFF
32 000000-007FFF 32 1C8000-1CFFFF
32 32 1C0000-1C7FFF
32 32 1B8000-1BFFFF
32 32 1B0000-1B7FFF
32 32 1A8000-1AFFFF
32 32 1A0000-1A7FFF
32 32 198000-19FFFF
32 32 190000-197FFF
32 32 188000-18FFFF
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32 32 180000-187FFF
32 32 178000-17FFFF
32 32 170000-177FFF
32 32 168000-16FFFF
32 32 160000-167FFF
32 32 158000-15FFFF
32 32 150000-157FFF
32 32 148000-14FFFF
32 32 140000-147FFF
32 32 138000-13FFFF
32 32 130000-137FFF
32 32 128000-12FFFF
32 32 120000-127FFF
32 32 118000-11FFFF
32 32 110000-117FFF
32 32 108000-10FFFF
32 32 100000-107FFF
32 32 F8000-FFFFF F8000-FFFFF
32 32 F0000-F7FFF F0000-F7FFF
32 32 E8000-EFFFF E8000-EFFFF
32 32 E0000-E7FFF E0000-E7FFF
32 32 D8000-DFFFF D8000-DFFFF
32 32 D0000-D7FFF D0000-D7FFF
32 32 C8000-CFFFF C8000-CFFFF
32 32 C0000-C7FFF C0000-C7FFF
This column continues on next page This column continues on next page
Table 3. 16 and 32 Mbit Memory Addressing (Sheet 2 of 2)
16-Mbit, 32-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 16-Mbit 32-Mbit Size
(KW) 16-Mbit 32-Mbit
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
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Table 4. 16 and 32 Mbit Memory Addressing (Sheet 1 of 2)
16-Mbit, 32-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 16-Mbit 32-Mbit Size
(KW) 16-Mbit 32-Mbit
32 32 B8000-BFFFF B8000-BFFFF
32 32 B0000-B7FFF B0000-B7FFF
32 32 A8000-AFFFF A8000-AFFFF
32 32 A0000-A7FFF A0000-A7FFF
32 32 98000-9FFFF 98000-9FFFF
32 32 90000-97FFF 90000-97FFF
32 32 88000-8FFFF 88000-8FFFF
32 32 80000-87FFF 80000-87FFF
32 32 78000-7FFFF 78000-7FFFF
32 32 70000-77FFF 70000-77FFF
32 32 68000-6FFFF 68000-6FFFF
32 32 60000-67FFF 60000-67FFF
32 32 58000-5FFFF 58000-5FFFF
32 32 50000-57FFF 50000-57FFF
32 32 48000-4FFFF 48000-4FFFF
32 32 40000-47FFF 40000-47FFF
32 32 38000-3FFFF 38000-3FFFF
32 32 30000-37FFF 30000-37FFF
32 32 28000-2FFFF 28000-2FFFF
32 32 20000-27FFF 20000-27FFF
32 32 18000-1FFFF 18000-1FFFF
32 32 10000-17FFF 10000-17FFF
32 32 08000-0FFFF 08000-0FFFF
32 4 07000-07FFF 07000-07FFF
32 4 06000-06FFF 06000-06FFF
32 4 05000-05FFF 05000-05FFF
32 4 04000-04FFF 04000-04FFF
32 4 03000-03FFF 03000-03FFF
32 4 02000-02FFF 02000-02FFF
Intel® Advanced+ Boot Block Flash Memory (C3)
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2.3 De vic e ID Tabl e
32 4 01000-01FFF 01000-01FFF
32 4 00000-00FFF 00000-00FFF
Table 5. Device ID
Re a d Configur a tio n Addr ess and Dat a
Item Address Data
Manufacturer Code x16 00000 0089
Device Code
16-Mbit x 16-T x16 00001 88C2
16-Mbit x 16-B x16 00001 88C3
32-Mbit x 16-T x16 00001 88C4
32-Mbit x 16-B x16 00001 88C5
Note: Other locations within the configuration address space are reserved by Intel for future
use.
Table 4. 16 and 32 Mbit Memory Addressing (Sheet 2 of 2)
16-Mbit, 32-Mbit Word-Wide Memory Addressing
To p Boot Bot t om Boot
Size
(KW) 16-Mbit 32-Mbit Size
(KW) 16-Mbit 32-Mbit
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
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3.0 Package Information
Figure 2. Mechanical Specifications for I Ballout (66 balls) Package (8x10x1.2 mm)
E
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
910 11 12
D
12345678
A
B
C
D
E
F
G
H
9101112
S2
S1
b
e
Bottom View - Ball UpTop View - Ball Down
A
A2
Y
A1
Millimeters Inches
Dimensions Symbol Min Nom Max Notes Min Nom Max
Package Height A 1.200 0.0472
Ball Height A1 0.200 0.0079
Package Body Thickness A2 0.860 0.0339
Ball (L ead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body Length D 9.900 10.000 10.100 0.3898 0.3937 0.3976
Package Body Width E 7.900 8.000 8.100 0.3110 0.31 50 0.3189
Pitch e 0 .800 0.0315
Ball (Lead) Count N 67 67
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Corner to Ball A1 Distance Along D S2 0.500 0.600 0.700 0.0197 0.02 36 0.0276
A1 Index Mark
Intel® Advanced+ Boot Block Flash Memory (C3)
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4.0 Bal lout and Sig nal Descrip ti ons
4.1 Ballout
Note: RAM ballout signals in Figure 3, “66-Ball SCSP Package Ballout” are show n wi th pr efix es
such as S-WE# o r S-VCC to indicate SRAM. However, these ballout signals also indicate
PSRAM, and are int erch a nge able with PSRAM sp ecif ications in this dat ashe et tha t are
prefixed by R- o r P-, su ch as R-WE# or P -VCC.
Notes:
1. Flash memory upgrade balls are shown up to A21 (64-Mbit flash) and A22 (128-Mbit flash). In all flash
memory and PSRAM combinations, 66 balls are populated on lower density devices. (Upper address
balls are not populated). Ball location A10 is NC on 16/2 devices only.
2. T o maintain compatibility with all JEDEC Variation B options for the C6 ball location, connect this C6 land
pad directly to the land pad for the G4 (A17) ball.
4.2 Signal Descriptions
Ta b le 6, “Signal Descr ip ti on s, NOR Fla sh” and Table 7, “Signal Descriptions - x16
PSRAM Memory Die” include generic names and descriptions for the signals in
Fig ure 3, “66-Ball SCSP Package Ballo u t ” o n pa ge 16 that are labeled according to
Flash signa ls (F-) and SRAM/PSRAM sig n al s (S-).
Figure 3. 66-Ball SCSP Package Ballout
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
NC A
20
A
11
A
15
A
14
A
13
A
12
A
16
A
8
A
10
A
9
DQ
15
S-WE#
F-WE# NC A
21
DQ
13
DQ
6
S-V
SS
F-WP# A
19
DQ
11
DQ
10
S-LB# S-UB# S-OE# DQ
9
DQ
8
A
18
A
17
A
7
A
6
A
3
A
2
NC NC A
5
A
4
A
0
F-CE# F-V
SS
F-RP# A
22
DQ
12
S-CS
2
910 11 12
F-V
SS
NC
DQ
14
DQ
7
DQ
4
DQ
5
DQ
2
DQ
3
DQ
0
DQ
1
A
1
S-CS
1
#
F-OE# NC NC
S-V
CC
F-V
CC
Top View, Balls Down
F-V
CCQ
F-V
PP
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Table 6. Signal Descriptions, NOR Flash
Symbol Type Description
A[Max:0] Input Address: Address inputs for all read/write cycles.
32Mb
A[M ax] = A20
DQ[15:0] Input/
Output Data: Data or command inputs during write cycles; data, status, or device-information outputs
during read cycles.
CE# Input Chip Enable (low-true): When low, selects the die; when high, deselects the die and places it in
standby.
OE# Input Output Enable (low-true): Must be low for reads, and high for writes.
WE# Input Write Enab le (low-true): Must be low for writes, and high for reads.
WP# Input Write Protect (low-true): When low, activates Block Lock-Down; when high, deactivates Block
Lock-Down.
RP# Input Reset (low-true): When low, inhibits all operations; must be high for normal operations.
VPP Input/
Power Program/E ra se Power: Enabling voltage (VPP1) or power source (VPP2) for p rogram and erase
operations. Array contents cannot be altered when VPP is at or below VPPLK.
VCC Power Core Power: Supply voltage for core circuits. All operations are inhibited when VCC is at, or below,
VLKO.
VCCQ Power I/O Pow er: Supply voltage for all I/ O drivers. All operations ar e inhibited when VCCQ is at, or
belo w, VLKO2.
GND Power Ground: Core logic and I/O ground return. Connect to system ground - do not float any grounds.
Table 7. Signal Descriptions - x16 PSRAM Memory Die
Symbol Type Description
A[Max:0] Input Address: Address inputs for all bus cycles.
16Mb
A[Max] = A19
D[15:0] Input/
Output Data: Data inputs during write cycles; data outputs during read cycles.
CS# Input Chip Select (low-true): CE#-low selects the die; CE#-high deselects the die, placing it in standby.
OE# Input Output Enable (low-true) : OE# must be low for reads and high for writes.
WE# Input Write Enab le (low-true): WE# must be low for writes and high for reads.
UB#
LB# Input Upper/Low er Byt e En ab le (lo w-true): L B#-lo w enables D[7:0] during read/write operations;
UB#-low enables D[15:8] during read/write operations. When high, UB# and LB# mask their
respective bytes.
Asynch r onous Onl y
MODE Input Mode (low-true): MODE-low enables access to the Configuration Register, or to enter/exit low-
power mode. MODE must be high for read/write data operations.
Power
VCC Power Logic Power: Supply voltage for core-log ic circuits.
VCCQ Power I/O Pow er: Supply voltage for I/O drivers.
VSS Power Ground: Core-logic and I/O-driver ground return. Connect all VSS balls to system ground - do not
float any VSS balls.
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5.0 Maximum Ratings and Operating Conditions
5.1 Absolute Maximum Ra tings
Warning: Stressing th e de vi c e beyo nd the Absol u te Maxi mum Ratings m i ght cause perm an ent
damage. These are stress ratings only. Do not operate the flash memory device beyond
the Operating Conditions. Extended exposure beyond these Operating Conditions might
affe ct device reliability.
5.2 Operating Conditions
NOTICE: This datasheet contains information on products in full production. The specifications are
subject to change without notice. Verify with your local Intel Sales office that you have the latest
datasheet before finalizing a design.
Table 8. Absolute Maximum Ratings
Parame ter Maximum Ratin g Notes
Exte nded Operating Temperature
–25°C to +85°C
—
Dur ing Read —
During Flash Block Erase and Program —
Temperature under Bias —
Storage Temperature –55°C to +125°C —
Voltage on Any Ball (except F-VCC /F-VCCQ / P-VCC and F-VPP) with Respect to
GND –0.5 V to +3.6 V 1
F-VPP Voltage (for Block Erase and Program) with Respect to GND –0.5 V to +13.5 V 1,2,4
F-VCC / F-V CCQ / P-VCC Supply Voltage with Respect to GND –0.2V to +3.6 V —
Output Short Circuit Current 100 mA 3
Notes:
1. Minimum DC voltage is –0.5 V on input/output balls. During transitions, this level may undershoot to –2.0 V
for periods < 20 ns . Maximum DC voltage on in put/output balls is F-VCC / F-VCCQ / P-VCC + 0.5 V which,
during transitions, may overshoot to F-VCC / F-VCCQ / P-VCC + 2.0 V for periods < 20 ns.
2. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns.
3. F-VPP voltage is normally 1.65 V–3.3 V. Connection to supply of 11.4 V–12.6 V can only be done for 1000
cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. F-VPP may be
connected to 12 V for a total of 80 hours maximum. See Section 10.2.1 for details
4. Output shorted for no more than one second. No more than one output shorted at a time.
Symbol Parameter Notes Min Max Units
TCASE Operating Temperature –25 +85 °C
VCC / VCCQ F-VCC /F-VCCQ /P-VCC Supply Voltage 1 2.7 3.3 Volts
VPP1 Supply Voltage 1 1.65 3.3 Volts
VPP2 Supply Voltage 1, 2 11.4 12.6 Volts
Cycling Block Erase Cycling 2 100,000 Cycles
Notes:
1. F-VCC/F-VCCQ must share the same supply. F-VCC/P-VCC must share the same supply when not in data retention.
2. Applying F-VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main
blocks and 2500 cycles on the par ameter block s. F-V PP may be connecte d to 12 V for a total of 80 hours maxim um. See
Section 10.2.1 for details.
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6.0 E lectric al Specif icatio n s
Note: All currents are in RMS unless otherwise noted. Typical values at nominal VCC,
TCASE =+25 °C.
Table 9. Flash DC Characteristics (Sheet 1 of 2)
Symbol Parameter Device Notes 2.7 V – 3.3 V Unit Test Conditions
Typ Max
ILI Input Load Current — — ± 2µA
F-VCC/P-VCC =V
CC Max
VIN =V
CCMa x or GND
ILO Output Leakage Current — — 0.2 ± 10 µA F-VCC/P-VCC =V
CC Max
VIN =V
CC Max or GND
ICCS VCC Standby Current
0.25µm — 10 25
µA
F-VCC =V
CC Max
F-CE#=F-RP#=V
CC
F-WP# = VCC or GND
VIN =V
CC Max or GND
0.13µm
and
0.18µm —715
ICCD VCC Deep Power-Down Current
0.25µm — 7 25
µA F-VCC =V
CCMax
VIN =V
CC Max or GND
F-RP#=GND ± 0.2V
0.13µm
and
0.18µm —715
ICCR VCC Read Current
0.25µm 1 10 18 mA F-VCC =V
CCMax
F-OE#=V
IH, F-CE# = VIL
f=5 MHz, I
OUT =0 mA
VIN =V
IL or VIH
0.13µm
and
0.18µm 1918mA
ICCW VCC Program Current — 2
18 55 mA F-VPP =V
PP1
Program in Progress
822mA
F-VPP =V
PP2 (12 V)
Program in Progress
ICCE VCC Erase Current — 2
16 45 mA F-VPP =V
PP1
Erase in Prog ress
815mA
F-VPP =V
PP2 (12 V)
Erase in Prog ress
ICCES VCC Erase Suspend Current — 2,3 7 15 µA F-CE#=V
CC, Erase Suspend
in Progress
ICCWS VCC Program Suspend Current
0.25μm 2,3 10 25
µA F-CE#=V
CC, Program
Suspend in Progress
0.13µm
and
0.18µm 2,3 7 15
IPPD F-VPP Deep Power-Down Current — 0.2 5 µA F-RP#=GND ± 0.2V
F-VPP ≤ VCC
IPPS F-VPP Standby Current — 0.2 5 µA F-VPP ≤ VCC
IPPR F-VPP Read Current — 2±15 µA F-VPP ≤ VCC
1 50 200 µA F-VPP ≥ VCC
IPPW F-VPP Program Current — 2
0.05 0.1 mA F-VPP =VPP1
Program in Progress
822mA
F-VPP =V
PP2 (12 V)
Program in Progress
IPPE F-VPP Erase Current — 1 0.05 0.1 ma F-VPP =V
PP1
Erase in Prog ress
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Note: All cu rre nts a re in RM S un less otherwise noted .
IPPES F-VPP Erase Suspend Current — 1
0.2 5 µA F-VPP =V
PP1
Erase S uspend in Progress
50 200 µA F-VPP =V
PP2 (12 V)
Erase S uspend in Progress
IPPWS F-VPP Program Suspend Current — 1 0.2 5 µA F-VPP =V
PP1
Program Suspend in Progress
50 200 µA F-VPP =V
PP2 (12 V)
Program Suspend in Progress
Notes:
1. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
2. Sampled, not 100% tested.
3. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of
ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR.
Table 9. Flash DC Characteristics (Sheet 2 of 2)
Symbol Parameter Device Notes 2.7 V – 3.3 V Unit Test Conditions
Typ Max
Table 10. PSRAM DC Characteristics
Parameter Description Test Conditions 3.0 V PSRAM Unit Note
Min Max
VCC Voltage Range 2.7 3.1 V —
ICC Operating Current
at min cycle time IIO = 0 mA
8M – 30
mA —
16M – 35
16M – – mA —
32M – 45
ICC2
Operating Current
at max cycle time
(1 μs)
IIO = 0 mA
8M – 5
mA —16M – 7
32M – 7
ISB Standby Current
P-CS# ≥ P-VCC-0.2V.
All inputs stable (either high or
low)
8M – 80
μA—
16M – 100
P-CS# ≥ P-VCC-0.2V or
P-Mode ≥ P-VCC-0.2V
Address/Data toggling at
minimum cycle time
16M – 85
μA—
32M – 100
IIL Input Leakage
Current -0.2 < VIN < P-VCC + 0.2 V -1 +1 μA1
IOL Output Leakage
Current
-0.2 < VIN < P-VCC + 0.2 V
P-VCC = VDR
-1 +1 μA1
Notes:
1. Input Leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs.
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Note: AC tes t i np uts are dr iv en at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output
Table 11. Flash Voltage Characteristics
Symbol Parameter Device Note 2.7 V – 3.3 V Unit Test Conditions
Min Max
VIL Input Low Voltage Flash — –0.2 0.6 V —
VIH Input High Voltage Flash — 2.3 VCC
+0.2 V—
VOL Output Low Voltage Flash — –0.10 0.10 V F-VCC/P-VCC =V
CC Min
IOL = 100 µA
VOH Output High Voltage Flash — VCC –
0.1 —V
F-VCC/P-VCC =V
CC Min
IOH = –100 µA
VPPLK F-VPP Lock-Out Voltag e Flash 1 1.0 V Complete Write Protection
VPP1 F-VPP during Program / Erase Flash 1 1.65 3.3 V —
VPP2 Operations Flash 1,2 11.4 12.6 ——
VLKO VCC Prog/Erase Lock Volt age Flash — 1.5 — V —
VLKO2 VCCQ Prog/Erase Lock Voltage Flash — 1.2 — V —
Notes:
1. Erase and Program are inhibited when F-Vpp < VPPLK and not guaranteed outsid e the valid F-Vpp ranges of VPP1 and
VPP2.
2. Applying F-Vpp = 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main
blocks and 2500 cy cles on th e par ameter block s. F- Vpp may be connected to 12 V for a total of 80 hours maximum. See
Section 10.2.1 for details.
Table 12. PSRAM Voltage Characteristics
Parameter Description Test Conditions 3.0 V PSRAM Unit Notes
Min Max
VCC Voltage Range 2.7 3.1 V —
VOH Output HIGH
Voltage
IOH = -0.5 mA 2.4 – V —
IOH = -0.1 mA P-VCC - 0.3 – V —
VOL Output LOW
Voltage
IOL = 1 mA, – 0.4 V —
IOL = 0.1 mA, VCCMin -0.1 0.3 V —
VIH Input HIGH
Voltage
P-VCC - 0.3 P-VCC + 0.2 V —
P-VCC-0.4 P-VCC + 0.2 V —
VIL Input LOW Voltage
-0.2 0.5 V —
-0.2 0.6 V —
Figure 4. Input/Output Reference Wavef orm
Input Test Points
V
CC
2
V
CC
2
Output
V
CC
0.0
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timing ends, at VCCQ/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are
when VCCQ = VCCQMin.
Note: CL includes jig capacitance.
TCASE = +25 °C, f = 1 MHz
Figure 5. Test Configuration
Device
Under Test Out
C
L
Table 13. Flash Test Configuration Component Values
Test Configuration CL (p F )
2.7 V–3.3 V Standard Test 50
Table 14. Capacitance
Sym Parameter Notes Typ Max Units Conditions
CIN Input Capacitance 1 16 18 pF VIN =0V
COUT Output Capacitance 1 20 22 pF VOUT =0V
Note: Sampled, not 100% tested.
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Document Number: 252636-005US 23
7.0 AC Characteristics
7.1 Flash AC Characteristics—Read Operations
Table 15. Flash AC Characteristics—Read Operations
#Sym Parameter
Density 16-Mbit 32-Mbit
Unit
Product -70 -90 -110 -70 -90
Voltage
Range 2.7 V - 3.3 V
Notes Min Max Min Max Min Max Min Max Min Max
R1 tAVAV Read Cycle Time 70 90 110 70 90 ns
R2 tAVQV Address to Output Delay 70 90 110 70 90 ns
R3 tELQV F-CE# to Output Delay 1 70 90 110 70 90 ns
R4 tGLQV F-OE# to Output Delay 1 20 30 30 20 20 ns
R5 tPHQV F-RP# to Output Delay 150 150 150 150 150 ns
R6 tELQX F-CE# to Output in Low Z 2 0 0 0 0 0 ns
R7 tGLQX F-OE# to Output in Low Z 2 0 0 0 0 0 ns
R8 tEHQZ F-CE# to Output in High Z 2 20 25 25 20 20 ns
R9 tGHQZ F-OE# to Output in High Z 2 20 20 20 20 20 ns
R1
0tOH
Output Hold from Address
F-CE#, or F-OE# Change,
Whichever Occurs First 2000 00ns
Notes:
1. F-OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV
2. Sampled, but not 100% tested.
3. See Figure 6, “AC Waveform: Flash Read Operations” on page 24.
4. See Figure 4, “Input/Output Reference Waveform” on page 28 for timing measurements and maximum allowable input
slew rate.
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7.2 Flash AC Characteristics—Write Operations
Figure 6. AC Waveform: Flash Read Operations
Table 16. Flash AC Characteristics—Write Operations (Sheet 1 of 2)
#Sym Parameter
Density 16-Mbit 32-Mbit
Unit
Product -70 -90 -110 -70 -90
Voltage
Range 2.7 V - 3.3 V
Notes Min Min Min Min Min
W1 tPHWL, t PHEL F-RP# High Recovery to F-WE# (F-CE#) Going Low 150 150 150 150 150 ns
W2 tELWL, tWLEL F-CE# (F-WE#) Setup to F-WE# (F-CE#) Going Low 0 0 0 0 0 ns
W3 tELEH, tWLWH F-WE# (F-CE#) Pulse Width 1 45 60 70 45 60 ns
W4 tDVWH, tDVEH Data Setup to F-WE# (F-CE#) Going High 2 40 50 60 40 40 ns
W5 tAVWH, tAVEH Address Setup to F-WE# (F-CE#) Going High 2 50 60 70 50 60 ns
W6 tWHEH, tEHWH F-CE# (F-WE#) Hold Time from F-WE# (F-CE#) High 0 0 0 0 0 ns
W7 tWHDX, tEHDX Data Hold Time from F-WE# (F-CE#) High 2 0 0 0 0 0 ns
W8 tWHAX, tEHAX Address Ho ld Time from F-WE# (F- CE#) High 2 0 0 0 0 0 n s
W9 tWHWL, tEHEL F-WE# (F-CE#) Pulse Width High 1 25 30 30 25 30 ns
Address Stabl e
Device and
Address Selection
I
H
V
IL
V
ADDRESSES ( A)
I
H
V
IL
V
I
H
V
IL
V
I
H
V
IL
V
CE# (E)
OE# ( G)
WE# (W)
DATA ( D/ Q)
I
H
V
IL
V
RP#(P)
OL
V
O
H
VHi gh Z Val i d Out put
Dat a
Valid Standby
Hi gh Z
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
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See Figure 4, “Input/Output Reference Wa veform” on page 21 for tim ing
measurements and maximum allowable input slew rate.
See Figure 7, “AC Waveform: Flash Program a nd Erase Operations” on page 2 6.
7.3 Flash AC Characteristics—Erase and Program Timings
Note: Typical values meas u r ed at TCA SE = +25 °C and nominal voltages.
W10 tVPWH, tVPEH F-VPP Setup to F-WE# (F-CE#) Going High 3 200 200 200 200 200 ns
W11 tQVVL F-VPP Hold from Valid SRD 3 0 0 0 0 0 ns
Notes:
1. Write pulse wid th (tWP) is defined from F-CE# or F-WE# going low (whichever goes low last) to F-CE# or
F-WE# going high (whichever goes high first). Hence, tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH. Similarly, write pulse width
high (tWPH) is defined from F-CE# or F-WE# going high (whichever goes high first ) to F-CE# or
F-WE# going low (whichever goes low first). Hence, tWPH =t
WHWL=t
EHEL =t
WHEL =t
EHWL.
2. Refer to Table 24, “Flash Memory Command Definitions” on page 38 for valid AIN or DIN.
3. Sampled, but not 100% tested.
Table 16. Flash AC Characteristics—Write Operations (Sheet 2 of 2)
#Sym Parameter
Density 16-Mbit 32-Mbit
Unit
Product -70 -90 -110 -70 -90
Voltage
Range 2. 7 V - 3.3 V
Notes Min Min Min Min Min
Table 17. Flash Erase and Progra m Timings
Symbol Parameter F-VPP 1.65 V– 3 .3 V 11.4 V – 12 .6 V Unit
Notes Typ(1) Max Typ(1) Max
tBWPB 4-KW Parameter Block Progra m Time (Word) 1, 2 0.10 0.30 0.03 0.12 s
tBWMB 32-KW Main Block Program Time (Word) 1, 2 0.8 2.4 0.24 1 s
tWHQV1 / tEHQV1 0.25 µm Word Program Time 1, 2 22 200 8 185 µs
0.13 µm and 0.18 µm Word Program Time 1, 2 12 200 8 185
tWHQV2 / tEHQV2 4-KW Parameter Block Erase Time (Word) 1, 2 0.5 4 0.4 4 s
tWHQV3 / tEHQV3 32-KW Main Block Erase Time (Word) 1, 2 1 5 0.6 5 s
tWHRH1 / tEHRH1 Program Suspend Latency 2 510510µs
tWHRH2 / tEHRH2 Erase Suspend Latency 2 520520µs
Notes:
1. Excludes external system-level overhead.
2. Sampled, but not 100% tested.
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Notes:
1. F-CE# mus t be toggled low when reading Status Register Data. F-WE# mus t be inactive (high) when
reading Status Register Data.
2. F-VCC Power-Up and Standby.
3. Write Program or Erase Setup Command.
4. Write Valid Address and Data (for Program) or Erase Confirm Comm and.
5. Automated Program or Erase Delay.
6. Read Status Register Data (SRD): reflects completed program/erase operation.
7. Write Read Array Command.
Figure 7. AC Waveform: Flash Program and Erase Operations
ADDRESSES [A]
CE#(WE#) [E(W)]
OE# [G]
W
E#(CE#) [W(E)]
DATA [D/Q]
RP# [P]
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
IN
D
IN
A
IN
A
Valid
SRD
IN
D
IH
V
High Z
IH
V
IL
V
V [V]
PP
PPH
V
PPLK
V
PPH
V1
2
WP#
IL
V
IH
V
IN
D
AB C D E F
W8
W6
W9
W3
W4
W7
W1
W5
W2
W10 W11
(Note 1)
(Note 1)
ADDRESSES [A]
CE#(WE#) [E(W)]
OE# [G]
W
E#(CE#) [W(E)]
DATA [D/Q]
RP# [P]
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
IN
D
IN
A
IN
A
Valid
SRD
IN
D
IH
V
High Z
IH
V
IL
V
V [V]
PP
PPH
V
PPLK
V
PPH
V1
2
WP#
IL
V
IH
V
IN
D
AB C D E F
W8
W6
W9
W3
W4
W7
W1
W5
W2
W10 W11
(Note 1)
(Note 1)
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7.4 Flash AC Characteristics—Reset Operations
7.5 PSRAM AC Characteri stics—Read Operations
Figure 8. AC Waveform: Reset Operation
Table 18. Reset Specifications(1)
Symbol Parameter Notes F-VCC 2 .7 V – 3.3 V Unit
Min Max
tPLPH F-RP# Low to Reset during Read (If F-RP# is tied to VCC,
this specification is not applicable) 2,4 100 ns
tPLRH1 F-RP# Low to Reset during Block Erase 3,4 22 µs
tPLRH2 F-RP# Low to Reset during Program 3,4 12 µs
Notes:
1. See Section 8.0.4, “Flash Reset” on page 32 for a full description of these conditions.
2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed.
3. If F-RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100
ns.
4. Sampled, but not 100% tested.
Table 19. PSRAM AC, 85/88 ns Initial Access—Read Operations (Sheet 1 of 2)
# Symbol Parameter 3. 0 V Unit Notes
Min Max
R1 tRC Read Cycle Time 85 4,000 ns —
R2 tAA Address to Output Delay – 85 ns —
R3 tCO P-CS# to Output Delay – 85 ns —
R4 tOE R-OE# to Output Delay – 40 ns —
IH
V
IL
V
RP# (P)
PLPH
t
IH
V
IL
V
RP# (P)
PLPH
t
(A) Reset during Read Mode
Abort
Complete
PHQV
t
PHW L
t
PHEL
t
PHQV
t
PHWL
t
PHEL
t
(B) Reset during Program or Block Erase, <
PLPH
t
PLRH
t
PLRH
t
IH
V
IL
V
R P# (P)
PLPH
t
Abort
Complete
PHQV
t
PHW L
t
PHEL
t
PLRH
t
Deep
Power-
Down
(C) Reset Program or Block Erase, >
PLPH
t
PLRH
t
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R5 tBA R-UB#, R-LB# to Output Delay – 85 ns —
R6 tLZ P-CS# to Output in Low-Z 10 – ns 1,2
R7 tOLZ R-OE# to Output in Low-Z 0 – ns 2
R8 tHZ P-CS# to Output in High-Z 0 25 ns 1,2,3
R9 tOHZ R-OE# to Output in High-Z 0 25 ns 2,3
R10 tOH
Output Hold (from Address, P-CS# or R-OE#
change, whichever occurs first) 0–ns —
R11 tBLZ R-UB#, R-LB# to Output in Low-Z 0 – ns 2
R12 tBHZ R-UB#, R-LB# to Output in High-Z 0 25 ns 2
PR1 tPC Page Cycle Time 40 – ns 4
PR2 tPA Page Access Time – 35 ns 4
Note:
1. At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device
to device interconnection.
2. Sampled but not 100% tested.
3. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
4. 4-Word Page read only available for 32-Mbit PSRAM. No page mode feature for 16-Mbit PSRAM.
Table 20. PSRAM AC, 70 ns Initial Access—Read Operations (Sheet 1 of 2)
# Symbol Parameter 3.0 V Unit Notes
Min Max
R1 tRC Read Cycle Time
70 15000
ns
–
–– –
R2 tAA Address to Output Delay – 70 ns –
R3 tCO P-CS# to Output Delay – 70 ns –
R4 tOE R-OE# to Output Delay – 45 ns –
R5 tBA R-UB#, R-LB# to Output Delay – 70 ns –
R6 tLZ P-CS# to Output in Low-Z 5 – ns 1
R7 tOLZ R-OE# to Output in Low-Z 0 – ns –
R8 tHZ P-CS# to Output in High-Z 0 25 ns 1, 2
R9 tOHZ R-OE# to Output in High-Z 0 25 ns 2
R10 tOH
Output Hold (from Address, P-CS# or R-OE#
change, whichever occurs first) 0–ns –
R11 tBLZ R-UB#, R-LB# to Output in Low-Z 0 – ns –
R12 tBHZ R-UB#, R-LB# to Output in High-Z 0 25 ns –
PR1 tPC Page Cycle Time 25 – ns 3
Table 19. PSRAM AC, 85/88 ns Initial Access—Read Operations (Sheet 2 of 2)
# Symbol Parameter 3.0 V Unit Notes
Min Max
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7.6 PSRAM AC Characteristics—Write Operations
PR2 tPA Page Access Time – 25 ns 3
tCEL CE# low-time restriction ns 4 ns 4
Note:
1. At any given temperature and voltage condition, tHZ (M ax) i s l ess t han t LZ (Max) both for a g iv en devi c e and f r om de vi c e
to de vice interconnection.
2. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
3. 4-Word Page read only available for 16-Mbit PSRAM. No page mode feature for 8-Mbit PSRAM.
4. CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns
Table 21. PSRAM AC Characteristics—Write Operations
#Symbol
1Parameter73.0 V Unit Notes
Min Max
W1 tWC Write Cycle Time 70 – ns —
W2 tAS
Address Setup to R-WE#
(P-CS#) and R-UB#, R-LB# going low 0–ns4
W3 tWP R-WE# (P-CS#) Pulse Width 55 – ns 2,3
W4 tDW Data to Write Time Overlap 35 – ns —
W5 tAW
Address Setup to R-WE#
(P-CS#) Going High 60 – ns —
W6 tCW P-CS# (R-WE#) Setup to R-WE# (P-CS#) Going High 60 – ns —
W7 tDH
Data Hold from R-WE#
(P-CS#) High 0–ns—
W8 tWR Write Recovery 0 – ns 5
W9 tBW R-UB#, R-LB# Setup to R-WE# (P-CS#) Going High 60 – ns —
tCEL P-CS# low-time restriction (Chip Enable/Chip Select) – – ns 7
W10 tWPH Write High Pulse Width – – ns —
Notes:
1. See Figure 11, “AC Waveform PSRAM Write Operation” .
2. A write occurs during the overlap (tWP) of low P-CS# and low R-WE#. A write begins when P-CS# goes low and R-WE#
goes low with asserting R-UB# or R-LB# for single byte operation or simultaneously asserting R-UB# and R-LB# for
double byte operation. A write ends at the earliest transition when P-CS# goes high and R-WE# goes high.
3. tWP is measured from P-CS# going low to end of a write.
4. tAS is measured from the address valid to the beginning of a write.
5. tWR is measured from the end of a write to the address change. tWR applied in case a write ends as P-CS# or R-WE#
going high.
6. W3 is 70 ns for continuous write operations over 50 times.
7. P-CS# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns
Table 20. PSRAM AC, 70 ns Initial Access—Read Operations (Sheet 2 of 2)
# Symbol Parameter 3.0 V Unit Notes
Min Max
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Note: Available only for 32-Mbit PSRAM and line items with 16-Mbit PSRAM (70 ns). Not applicable to 8-Mbit PSRAM.
Figure 9. AC Waveform of PSRAM Read Operations
Figure 10. AC Waveform of PSRAM 4-Word Page Read Operation
Figure 11. AC Waveform PSRAM Write Operation
Valid Data
R10R6
R11
R7
R9R4
R12R5
R8R3
R1
R2
R1
ADDRESSES
P-CS#
R-UB#, R-LB#
R-OE#
DAT A
Valid Addres
s
Valid Addres
s
Valid Addres
s
Valid Addres
s
Valid Addres
s
Valid Data Valid Data Valid Data Valid Data
PR2R6
R7
R9R4
R8R3
PR1PR1
R1
R2
R1
A
[Max:2]
A[1:0]
P-CS#
R-OE#
DATA
Data In
W7W4
W8
W5
W3W3
W9
W6
W1
W2
W1
ADDRESSES
P-CS#
R-UB#, R-LB#
R-WE#
DAT A
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8.0 Bus Operation
All bus cycles to or from the SCSP conform to standard microcontroller bus cycles. F our
con trol signals dict ate th e data flow in an d ou t o f th e fla s h com pon ent:
•F-CE#
•F-OE#
•F-WE#
•F-RP#
Four separate control signals handle the data flow in and out of the PSRAM component:
•P-CS#
•R-UB#
•R-LB#
•R-OE#
•R-WE#
Tabl e 4 2 on page 6 5 and Table 22 o n pa ge 3 2 summarize th ese bus op erations .
8.0.1 Read
The fla sh memo r y device prov id es fou r read mo des:
•Read array
• Read identifi er
•Read status
•CFI query
Thes e flash memory read modes do not depend on the F-VPP voltage. Upon initial
device power-u p or aft er ex it from r es et, the fla s h m em ory devic e auto m ati c ally
defaults to r ead arra y mo de. F-CE # an d F-OE# must be as s er ted to obta in data from
the flash memory device.
The PSRAM provides o n l y on e r ead mo de. P- C S #, an d R-OE# must be ass erted to
obtain data from the PSRAM device. See Table 22 for a summary of operations.
Note: Two devices cannot drive the memory bus at the sam e time.
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8.0.2 Output Disable
When F- O E # and R-OE# ar e deasserted, th e SC SP outpu t s ignals ar e placed in a hi gh-
impedanc e stat e.
8.0.3 Standby
When F-CE # and P-CS # are d easserted, the SC SP enters a stand by mod e, wh ich
substantially reduces device power consumption. In standby mode, outputs are placed
in a high-impedance state independent of F-OE# and R-OE#. If the flash memory
device is deselected during a program or erase operation, the flash memory continues
to consume active power until the program or erase operation is complete.
8.0.4 Flash Reset
The flash memory device enters a reset mode when RP# is driven low. In reset mode,
int ern al circ u itry is tur n ed of f a n d o utputs a r e place d in a h igh-im p edance state.
After returning from reset, a time tPHQV is required u ntil ou tp ut s are valid . A del ay
(tPHWL or tPHEL) is required before a write sequence can be initiated. After this wake-up
interval, normal operation is restored.
• The flash memory device defaults to read array mode.
• The status register is set to 80h.
• The read configura tion register defaults to asynchronous reads.
Table 22. Intel Advanced+ Boot Block Flash Memory SCSP Bus Operations
Modes
Flash Signals PSRAM Signals Memory Output
Notes
F-RP#
F-CE#
F-OE1#
F-WE#
P-CS#
R-OE#
R-WE#
R-UB#,R-LB#
Memory Bus Control
D0–D15
FLASH
Read H L L H PSRAM must be in High
ZFlash DOUT —
Write H L H L Flash DIN —
Standby H H X X Any PSRAM mode is
allowable
Other High Z —
Output Disable H L H H Other High Z —
Reset L XXX OtherHigh Z —
RAM
Read FLASH must be in High Z LLHL RAM D
OUT —
Write L H L L RAM DIN —
Standby
Any FL AS H mode is allow abl e
HXXXOther H igh Z —
XXXX
Output Disable L H H X Other High Z —
Data Retention same as a standby Other High Z 1
Notes:
1. To place the PSRAM into data retention mode, lower the P-VCC signal to the V DR range, as specified.
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If RP# is taken low during a block era se or progr am oper ation, the oper ation aborts and
the me m o r y c o n tents at the a bo r ted loc ation are no lo n ger vali d .
8.0.5 Write
• Writes to flash memory occur when both F-CE# and F-W E# are asserted and F-
OE# is deasserted.
• Writes to PSRAM occur when both P-CS# and R-WE# are asserted and R -OE# is
deasserted.
Commands are written to the flash memory Comm and User Interface (CUI), using
standard microprocessor write timings to control flash memory operations. The CUI
does not occupy an addressable memory location within the flash memory device. The
address and data buses are latched on the rising edge of the second F-W E# or F-CE#
pulse, whichever oc curs first. (See Figure 6 on page 24 and Figu r e 7 on page 26 for
read and write waveforms.)
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9.0 Flash Oper at io n s
The flash memory has four read modes:
•Read array
• Read configuration
•Read status
•CFI query
The write modes are:
•Program
•Erase
Three additional modes are avai lable only during suspended operations:
• Erase suspend to progra m
• Erase suspend to read
• Progr am suspend to read
These modes are reached using the commands summarized in Table 24, “Flash Memory
Command Definitions” on page 38.
9.1 Read Array (FFh)
When F-RP# transiti ons from VIL (reset) to VIH, the flash m e mo ry device defa u l ts to
re ad array mod e and re s p onds to th e re ad co n tr o l in puts wi tho u t addi tio n al C UI
commands.
In ad di tion, the address of th e desi r ed locat i o n mus t be a ppl ied to th e address balls. If
th e flash m e mory device is n ot in re ad array mod e, s u c h as af ter a pro gra m o r erase
operatio n, th e R ead Array command ( FFh) must be wri tten to th e CUI bef o r e array
reads can take place.
9.2 Read Identifier (90h)
The Read Con fig uration mo de out pu ts three types of inf orm at io n:
• Manufacturer/device identifier
• Block locking stat u s
• Protection register
1. To switch the flash memory device to this mode, wri te the read configuration
command (90h).
In this mode, read cycles from addresses shown in Table 23, “Read Configuration
Tabl e” o n page 34 retrieve the specified information.
2. To return to read array mode, write the Re ad Array command (FFh).
Table 23. Read Configuration Table (Sheet 1 of 2)
Item Address Data Notes
Manufacturer Code (x16) 0x00000 0x0089
Device ID (See Appendix D) 0x00001 ID
Block Lock Configuration 0xXX002 LOCK 1, 2
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Intel reserves other locations within the config uration address space for future use.
9.3 Read Status Register (70h)
The status register indicates the status of device opera tions, and the success/failure of
that operation.
1. After you issue the Read Status Re gister (70h) command, subsequent reads output
data from the status register until another command is issued.
2. To re tu r n to r e a ding from the arra y, is s u e a Rea d A r ra y (FFh) com man d.
The status register bits are output on DQ[7:0]. The upper byte, DQ[15:8], outputs 00h
duri ng a Rea d S tatu s Regi ster comm a n d.
The contents of the status register are latched on the falling edge of F-OE# or F-CE#,
whichever occurs last. Latching on the falling edge prevents possible bus errors that
might occur if status register contents change while being read. F-CE# or F-O E# must
be toggled with each subsequent status read, or the status regi ster does not indicate
completio n of a progr a m or erase opera tion.
When the WSM is active, SR7 indicates the status of the WSM. The remaining bits in
the status register indicate whether the WSM was successful in performing the desired
operat ion (see Table 25, “Flash Memory Status Register Definition” on page 39).
9.3.1 Cle ar Status Re g ister (50h)
The WSM sets status bits 1 through 7 to a 1 value, and clears bits 2, 6 and 7 to a 0
value. However, W SM cannot clear status bits 1 or 3 through 5 to a 0 value. Because
bits 1, 3, 4, and 5 indicate various error conditions, only the Clear Status Register
(50h) command can clear these bits.
If the system software controls resetting these bits, several operations (such as
cumulative ly pro g rammin g several addre sses o r erasing mult ipl e blocks in sequence)
can be performed before reading the status register to determine whether an error
occurred during that series.
• Clear the status register before beginning another command or sequen ce.
• A Read Array command must be issued before data can be read from the memory
array.
• Resetting the flash memory device also clea rs the status register.
•Block Is Unlocked DQ0=0
•Block Is Locked DQ0=1
•Block Is Locked-Down DQ1=1
Protection Register Lock 0x80 PR-LK 3
Protection Register (x16) 0x81-0x88 PR
Notes:
1. See Section 9.7 for valid lock status outputs.
2. “XX” specifies the block address of lock configuration being read.
3. See Section 9.8 for p rotection register information.
Table 23. Read Conf iguration Table (Sheet 2 of 2)
Item Address Data Notes
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9.4 CFI Query (98h)
The CFI query mode outputs Common Flash Interface (CFI) data when the flash
memory device is read.
The CFI data structure contains information such as:
• block size
•density
• command set
• electri cal specif ica tions
1. To access this mode, write the CFI Query Command (98h).
In this mode, read cycles from addresses shown in Appendix , “CFI Query
Structure” retrieve the speci fie d inf o rm atio n.
2. To return to read array mode, write the Re ad Array command (FFh).
9.5 Word Program (40h/10h)
Programming uses a two-writ e sequence.
1 . Th e Pro gram Setup comman d ( 4 0 h ) is w r i tten to th e CU I.
2. A second write s pecifies the address and data to program.
3. The WSM executes a sequence of internally timed events to program desired bits of
the addressed location
4. T h e WSM th en ve r ifies tha t th e bit s ar e suffici ently pro grammed.
Programming the memory changes the value of specific bits within an address to 0.
Note: If you attempt to program a 1 value, the memory cell contents do not change and no
error occurs.
The status register indicates programming status:
• While the program sequence executes, status bit 7 has a 0 va lue.
• To po ll the statu s re gister, toggle eit h er F-C E # o r F- O E#.
While programming, the only valid commands are:
• Read S t atus Register
•Program Suspend
•Program Resume
1. When progr amming is complete, check the program status bits.
— If the progra mming operation was unsuccessful, status register but SR.4 is set
to indicate a program failur e .
— If SR.3 is set, then F-VPP was not within acceptable limits, and the WSM did not
execut e th e program co m m a n d.
— If SR.1 is set, a program operation was attempted on a locked block and the
operation ab orted.
2. Clear the status register before attempting the next operation.
Any CUI instruction can follow after programming is completed.
3. To prevent inadvertent status register reads, reset the CUI to read arra y mode.
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9.5.1 Suspending and Resuming Program (B0h/D0h)
The Pr o gram Sus p en d c ommand h alt s an in-p rogress program operation, so t ha t data
can be read from other locations of memory.
1. After the programming process starts, write the Program Suspend command to the
CUI.
— T h is c ommand requests that the W SM s us pend th e p r og ra m s eq u en c e (at
pr ed etermi ned p oi n ts in th e p r o gram algori thm).
— The flash memory device continues to output status register data after the
Program Suspend comman d is written.
2. Po l l s tatu s re gi s ter bits SR . 7 an d S R . 2 to dete rmine w h en th e pr o gram operation
has been suspended (both are set to 1).
Note: tWHRH1/tEHRH1 specif ies the program suspend latency.
A Read A r ray c o m m and can be writte n to th e C UI to r e a d data fr o m an y bloc k ot h er
than the susp ended block . Th e on ly other valid commands, while program is
suspended, are:
• Read St atus Regi ste r
• Read Configuration
•CFI Query
•Program Resume.
After th e Pr ogram Resum e command is w r itten to th e fla s h m em ory:
• WSM continues the programming process.
• Sta tu s r egister bits SR . 2 an d SR. 7 ar e a u to m atically cleared .
• The flash memory device automatically outputs status register data when read (see
Appendix , “Program/Erase Flowcharts”).
Note: F-VPP must remain at the same F-VPP level used for program while in program suspend
mode. F-RP# must also remain at VIH.
9.6 Block Erase (20h)
To erase a block, writ e th e Erase Set -up and Erase Confirm commands to the CUI,
along wi th an address id en tifyin g th e block to be erased. This addr ess is latc h ed
internally when the Erase Conf irm co m mand is issued . Blo ck er asure results in all bit s
within the block being set to “1.” Only one block can be erased at a time. The WSM will
execute a seque n c e o f i ntern ally tim ed events to pr o gram all bits w ithin th e b l o c k to
“0,” erase a ll bits within the block to “1,” then ver ify th at all b its within the bloc k are
sufficiently erased. While the erase executes, status bit 7 is a “0.”
When th e statu s registe r indi cates that erasur e is co m plete, c h eck the eras e status bit
to verify that th e eras e operation was successf ul . If th e E rase o peration was
unsuccessful, SR.5 of the status register will be set to a “1,” indicating an er ase failure.
If F-VPP was not within acceptable limits after the Erase Confirm command was issued,
the WSM will not execute the erase sequence; instead, SR.5 of the status register is set
to in dicate an er as e er ror, and SR. 3 i s set to a “1 ” to id en tify t h at F-VPP supply volta ge
was not within accept able limits.
After an eras e op eration , c lear the s ta tus re gister (5 0h ) b efore atte m pt in g t h e n ext
operation. Any CU I instr uction ca n follo w a ft er erasur e is com ple te d; howe ver, to
prevent inadvertent status register reads, it is advisable to place the flash in read array
mode after the erase is co m plete.
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9.6.1 Suspending and Resuming Erase (B0h/D0h)
An erase operation can take several seconds to complete, therefore, the Er ase Suspend
command is provide d to a llow eras e-sequ ence interruption in order to read data from,
or program data to, another block in memory. Once an erase sequence has started,
writing the Erase Suspend command to the CUI causes the device to suspend the erase
sequence at a predetermined point in the erase algorithm. Block erase is suspended
wh en Sta t us Register bits SR [7,6] a r e set . Su spe nd la te ncy is s pec ifi ed in Section 7.3,
“Flash AC Characteristics—Erase and Program Timings” on page 25.
When an era s e o pe rat io n h as been su spend ed, a Word Program or Read o peration c an
be performed within any block, except the block that is in an erase suspend state. An
er ase ope r ation cannot be ne sted within another er ase suspend op erati o n .
A suspended erase ope ration cannot resume until the nested program operation has
completed. Following are valid commands during Erase Suspend:
•Read Array
• Read/Clear Status Register
• Read Identifier
•CFI Query
• Erase Resume
•Program
• Program Susp end/Resume
• Lock/Unlock/Lock-Down Block.
To resume an erase suspend operation, issue the Resume command. The Resume
command can be written to any device address. When a program opera tion is nested
within an Erase Suspend operation and the Program Suspend command is issued, the
device suspends the program operation. When the resume command is issued, the
device resumes the progr am operation first. Once the nested program operation
completes, an additional Resume command is required to complete the block operation.
Table 24. Flash Memory Command Definitions (Sheet 1 of 2)
Command Note First Bus Cyc le Second Bus Cycle
Operation Address Data Operation Address Data
Read Array 1 Write X FFh
Read Identifier 1, 2 Write X 90h Read IA ID
CFI Query 1, 2 Write X 98h Read QA QD
Read Status
Register 1 Write X 70h Read X SRD
Clear Status
Register 1 Write X 50h
Word Program 1, 3 Write X 40h/10h Write PA PD
Block Erase/
Confirm 1 Write X 20h Write BA D0h
Program/Erase
Suspend 1WriteX B0h
Program/Erase
Resume 1WriteX D0h
Lock Block 1 Write X 60h Write B A 01h
Unlock Block 1, 4 Write X 60h Write BA D0h
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Lock-Down
Block 1WriteX 60hWrite BA2Fh
Protection
Register
Program 1WriteX C0hWrite PAPD
Lock Protection
Register 1WriteX C0hWrite PAFFFD
X=Don’t Care PA = Program
Address BA = Block
Address IA = Identifier
Address QA = Query
Address X=Don’t Care PA = Program
Address BA = Block
Address
SRD = Status
Register Data PD = Program
Data ID = Identifier
Data QD = Query
Data SRD = Status
Register Data PD = Program
Data
Notes:
1. When writing commands, the upper data bus [DQ8–DQ15] should be either VIL or VIH, to minimize current draw.
2. Following the Read Configuration or CFI Query commands, read operations output device configuration or CFI query
inf or ma t io n , res pe c ti vel y.
3. Either 40h or 10h command is va lid, but the Intel stan dard is 40h.
4. When unlocking a block, WP# must be held for three clock cycles (1 clock cycle after the second command bus cycle).
Table 25. Flash Memory Status Register Definition
WSMS ESS ES PS VPPS PSS BLS R
76543210
Bit Number NOTES:
SR.7 WRITE STATE MACHINE STATUS
1=Ready (WSMS)
0=Busy
Check Write State Machine bit firs t to det e rmine Word Program or Block Erase
completion, before checking Program or Erase Status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Eras e Suspend i s issu ed, WSM halts exe cution and sets b oth WSMS and ES S
bits to 1. ESS bit remains set to 1 until an Erase Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erase
0 = Successful Block Erase
Whe n thi s bi t is s e t to 1, WS M has ap pl ie d th e ma x. numb er of er a se pu ls e s and i s
still unable to verify successful block erasure.
SR. 4 = PRO G RAM STATU S (PS)
1 = Error in Programming
0 = Successful Programming When this bit is set to 1, WSM has a ttempted but failed to program a word/byte.
SR.3 = F-VPP STATUS (VPPS)
1=F-V
PP Low Detect, Operation Abort
0=F-V
PP OK
The F-VPP status bit does not provide continuous indication of VPP le vel . Th e WSM
inte rrog ates F-VPP level only after the Pr ogram or Er ase command seque nces have
been entered, and informs the system if F-VPP has not been switched on. The F-
VPP is also checked before the operation is verified b y the WSM. The F-VPP st atus
bit is n ot guaranteed to rep ort accurate feedback between VPPLK and VPP1 min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1=Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and sets both WSMS and
PSS bits t o 1. PSS bit remai ns set to 1 until a Pr ogram R esume c ommand is issued.
SR.1 = BLOC K LOCK STATUS
1 = Prog/Erase attempted on a locked
block; Operation aborted.
0 = No operatio n to locked blocks
If a pr ogram or e r ase ope rati on i s attempted to one of th e lock ed block s, this b it i s
set by the WSM. The operation specified is aborted and the d evice is returned to
read status mode.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R) This bit is reserved for future use and should be masked out when polling the
status register.
Note: A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
Table 24. Flash Memory Command Definitions (Sheet 2 of 2)
Command Note First Bus C ycle Se cond Bus Cy c l e
Operation Address Data Operation Address Data
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9.7 Block Locking
The in stan t , individual block lock ing f ea ture t h at allows any flash block to be locked or
unl oc ked with no late n cy, which en a b les insta nt code and data prot ection.
This locking offers two levels of protection. The first level allows software-only control
of block lo cking (useful for data blocks tha t chang e f r eq uently), while the second level
requ ires hardware inte ractio n befo re locking can be c h anged (useful fo r code blocks
that change infrequently).
The following sections will discuss the operation of the locking system. The term “state
[XYZ]” will be used to specify locking states; e.g., “state [001],” where X = value of
WP#, Y = bit DQ1 of the Block Lock status register, and Z = b it DQ0 of the Block Lock
status register. Table 27, “Bl ock Locking Stat e Transitions” on page 42 define s all of
these possib le locking sta tes.
9.7.1 Block Locking Operation Summary
The follo wing concise ly sum ma r izes the loc king function ality.
All blocks are locked when powered-up, and can be unlocked or locked with the Unlock
and Lock commands.
• The Lock -Down command locks a block and preve nts it from being unlocked when
WP# = 0.
• When WP# = 1, Lock-Down is overridden and commands can unlock/lock locked-
down bl o c k s.
• When WP# returns to 0, locked-down blocks return to Lock-Down.
• Lock-Down is cleared only when the device is reset or pow ered-down.
The locking status of each block can set to Locked, Unlocked, and Lock -Down, each of
wh ich will be desc ri be d in the followin g sect io ns . A compr ehe n sive state tabl e for the
lock ing fun ctions is sho wn in Tabl e 2 7 on page 4 2 , and a flowchart for locki n g
operations is shown in Figur e 17 o n pa ge 4 9 .
9.7. 2 Loc ke d State
The default status of all blocks upon power-up or reset is locked (states [001] or
[101]). Locked blocks are fully protected from alteration. Any program or erase
operation s attempted on a locked block will return an error on bit SR.1 of the status
register. The status of a locked block can be changed to Unlocked or Lock-Down using
the appropriate software commands. Unlocked blocks can be locked issuing the “Lock”
command sequence, 60h followed by 01h.
9.7.3 Unlocked State
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All
unloc ke d b l o c ks r etu r n to th e Loc ked sta te when th e device is re s et or power ed do w n .
The status of an unlocked block can be changed to Locked or Locked-Down using the
appr opr iate so ftw are c omma nds. A Lo cked bl ock can be u nlo cke d by w ri ting t he U nlo ck
command sequence, 60h followed by D0h.
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9.7.4 Lock-Down State
Blocks that are Locked-Down (state [011]) are protected from program and erase
opera tions (just like Locked blocks), but their protection status cannot be changed
using software commands alone. A Locked or U n locked block can be Locked-down by
writing the Lock-Down command sequence, 60h followed by 2Fh. Locked-Down blocks
revert to the Locked state when the device is reset or powered down.
The Lock-Dow n fu n c tion is dependen t on the WP# inpu t ball. When WP# = 0, blo ck s i n
Lock- Do wn [011] are prote cted fr om program, erase, and lock status changes. When
WP# = 1, the Lock-Dow n functio n is disabled ([111 ]) and locked-down bl ocks can be
individually unlo cked by software command to the [110] state, where they can be
erased and progr ammed. These blocks can then be re-locked [111] and unlocked [110]
as desire d while WP# rem a ins h ig h. Whe n WP # goe s low, blocks that were previo usly
locked-down return to the Lock-Down state [011] regardless of any changes made
while WP# was high. Device reset or power-down resets all blocks, including those in
Lock- Down, to Locked state.
9.7.5 Reading Lock Status for a Block
The lock status of e very block can be read in the configuration read mode o f the device.
To en t er this m o d e, wr it e 9 0h to the devic e. Subseq uen t re ads at Bl oc k Ad dr ess +
00002 will outp ut the lock status of that bloc k. The lock stat us is represen ted b y the
least significant outputs, DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and
is set by the Lo ck command and clea red by the Unlock command. It is also
automatically set when entering Lock -Down. DQ1 indicates Lock -Down status and is set
by the Lock-Down command. It cannot be cleared by software, only by device reset or
power-down.
9.7.6 Locking Operation During Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the
standard locking command sequences to unlock, lock, or lock-down a block. This is
usef ul in the c a s e when another block ne ed s to be updated while an era se o pe ra tion is
in progress.
To change block locking during an erase operation, first write the erase suspend
com mand (B0h), th en c h eck the statu s register u n t il i t indicat es th at the era s e
operation has been suspended. Next write the desired lock command sequence to a
bloc k and the lock s tatus w i ll be c h a nged. After c ompletin g an y desired l ock, read, o r
program operations, resume the erase operation with the Erase Resume command
(D0h).
If a bl ock is locked or locked-down during a suspended erase of the same block, the
locking s tatus bits will be changed immedia te ly, but when the erase is resumed, the
erase op eration will complet e.
Locking operations cannot be performed during a program suspend.
Table 26. Block Lock Status
Item Address Data
Block Lock Configuration XX002 LOCK
• Block Is Unlocked DQ0=0
• Block Is Locked DQ0=1
• Block Is Locked-Down DQ1=1
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42 Document Number: 252636-005US
9.7.7 S tatu s Re g ister E rror Ch e c king
Using nested locking or program command sequences during erase suspend can
introduce ambig uity into status register results.
Since locking changes are performed using a two cycle command sequence, e.g., 60h
followed by 01h to lock a block, following the Configura tion Setup command (60h) with
an invalid command will produce a lock command error (SR.4 and SR.5 will be set to 1)
in the status register. If a lock com mand error occurs during an erase suspend, SR.4
and SR.5 will be se t to 1, and will r ema in at 1 after the erase is resumed . Wh en erase
is comp lete, any po s si ble erro r dur in g th e eras e canno t b e detect ed via the sta tus
register because of the previous locking command error.
A similar situation happens if an error occurs during a program operatio n error nested
within an erase suspend.
9.8 128 Bit Protection Register
The C3 SCSP architecture includes a 128-bit protection register than can be used to
increase the security of a system design. For exam ple, the number contained in the
protection register can be used to “mate” the flash component with other system
components such as the CPU or ASIC, preventing device substitution.
9.8.1 Reading the P rotection Register
Th e pr o tecti o n re gister is r ead in the co n f iguratio n re ad m o de. The device is switched
to this mo de by writin g the Read Configu ration c om mand (90h). O nce in this mode,
read cycles from add r esse s show n in App end ix E retrieve the specified informa ti on . To
return to read array mode, write the Read Array command (FFh).
Table 27. Block Locking State Transitions
Curre nt Sta t e Erase/
Program
Allowed?
Next State after Command Input
WP# DQ1DQ0Name Lock Unlock Lock-Down
0 0 0 Unlocked Yes Go To [001] – Go To [011]
1 0 0 Unlocked Yes Go To [101] – Go To [111]
001Locked (Default) No – Go To [000] Go To [011]
1 0 1 Locked No – Go To [100] Go To [111]
011Locked-Down No – – –
110 Lock-Down
Disabled Yes Go To [111] – Go To [111]
1 1 1 No - Go To [110] –
Notes:
1. “–” indicates no change in the current state.
2. In this tab le, the notation [X YZ] denotes the locking state of a block, where X = WP#, Y = DQ1, and Z = DQ0. The
current lock ing sta te of a block is defi ned by th e state of WP# and the two bi ts of the b lock l ock status (D Q0, D Q 1). DQ0
indicates if a block is locked (1) or unlocked (0). DQ1 indicates if a block has been locked-down (1) or not (0).
3. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). holding WP# = 0 is the
re co mm ende d de fau l t.
4. Th e “Erase/ P rog r am A ll o wed ?” co l um n sh ow s w he the r erase a n d p rog r a m o pe ra ti o ns are enab le d ( Yes) or d is ab l ed (No )
in that block’s current locking state.
5. The “Lock Command Input Result [Next State]” column shows the result of writing the three locking commands (Lock,
Unlock, Lock-Down) in the current locking state. For example, “Goes To [001]” would mean that writing the command
to a block in the current locking state would change it to [001].
6. The 128 bits of t he prot ection regist er are divid ed into two 6 4-bit segments. One of the segments i s progr ammed at the
Intel factory with a unique 64 bit number, which is unchangeable. The other segment is left blank for customer designs
to program as desire d.
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9.8.2 Programming the Protection Register (C0h)
The protection register bits are progr a mmed using the two-cycle Protection Program
command. The 64-bit number is programmed 16 bits at a time for word-wide parts.
First wr ite the Protect io n Pr o g ram Se tu p c om m an d , C0 h . Th e next writ e to the device
will latch in address and data and pro gram the spe cifi ed location. The all owabl e
addresses are shown in Appendix E. Se e Figure 18, “Protection Register Programming
Flowchart” on pa ge 5 0.
Any attempt to address Protecti on Program commands outside the defined protection
registe r address space will result in a status regist er err or (program err o r bit SR.4 w ill
be se t to 1). A ttempting to pr o gram or to a pr eviousl y locked pro tect i o n re gi s ter
segment will result in a status register error (program error bit SR.4 and lock error bit
SR.1 will be set to 1).
9.8.3 Lock ing the Protection Register
Th e us er -pr ogr a mmabl e s egm ent of t he prot ect io n re gis ter is l oc kable by pr ogr ammi ng
Bi t 1 of th e PR- LOC K loca tio n to 0. Bit 0 of thi s loca ti on is progr am med to 0 at t he Int el
fact ory to protect the unique device number. This bit is set u sing the Protection
Program command to program FFFDh to the PR-LOCK location. After these bits have
been programmed, no further changes can be made to th e values stored in the
protection register. A Protection Program command to locked words will result in a
status register error (prog ram error bit SR.4 and Lock Error b it SR.1 will be set to 1).
The pro tect io n r egister lockout state is n ot rever sib le.
Figure 12. Protection Register Memory Map
4 Words
Factory Programmed
4 Words
User Programmed
PR-LOCK
88H
85H
84H
81H
80H
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10.0 P ower and Reset Considerations
10.1 Power-Up/Down Char acteri stic s
In order to prevent any condition that may result in a spurious write or era se operation,
it is recommended to power-up F-VCC, F-VCCQ and P-VCC together. Conver sely, F-VCC,
F-VCCQ and P-VCC m u s t po w er-down together. It is also rec o m men ded to power - u p F-
VPP with or sligh tl y afte r F-VCC. C onversely, F-VPP mus t power down wi th or sli ghtly
before F-VCC.
If F- V CCQ and/or F-VPP ar e n ot con nect ed to t he F- VCC supply, then F-VCC should attain
F-VCCMin before ap pl y in g F-V CCQ and F-VPP. Device inputs should not be driven before
supply voltage = F-VCCMin. Power supply transitions should only occur when F-RP# is
low.
10.2 Additional Flash Features
C3 S C SP pro ducts pr ovide in - s y stem pr ogrammi n g a n d er as e in the 1.65 V–3.3 V
range. Fo r fast production programming, it also includes a low-cost, backward-
compatible 12 V programming feature.
10.2.1 I mpr oved 12 V olt Pro duct ion Programm ing
When F-VPP is between 1.65 V an d 3.3 V, all pr o gram and er ase cu rr ent is drawn
through the F- V CC si gnal. No te that if F -VPP is driven by a logic signal, VIH min = 1.65 V.
That is, F-VPP must remain above 1.65 V to perform in-system flash modifications.
When F-VPP is connected to a 12 V power supply, th e device draws program and erase
current directly from the F-VPP signa l . This eliminates the need for an external
switching transistor to control the voltage F-VPP
.
The 12 V F-VPP mode enhances programming performance during the short period of
time typica lly f o un d in manufacturing processes; howe ver, it is not intend ed for
ext end ed use. 12 V ma y be appli ed to F- V PP during program and e rase op er ati ons f or a
maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks.
F-VPP ma y b e connected to 12 V for a total of 80 hours maximum. Stressing the device
bey o n d th ese limits may cau s e permanen t dam age.
10.2.2 F-VPP ≤ VPPLK for Complete Protection
In addition to the flexible block locking, the F-VPP programming voltage can be held low
for absolute hardware write protection of all blocks in the flash device. When F-V PP is
bel o w VPPLK, any program or era se operation will result in a error, prompting the
corresponding status register bit (SR.3) to be set.
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11.0 Progr am/Erase Flowcharts
Figure 13. Automated Word Programming Flowchart
Start
Write 40H
Program Address/Data
Read Status Register
SR.7 = 1?
Full Status
Check if Desired
Program Complete
Read Status Register
Data (See Above)
V
PP
Range Error
Programming Error
Attempted Program to
Locked Block - Aborted
Program Successful
SR.3 =
SR.4 =
SR.1 =
F
ULL STATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program or after a sequence of
program operations.
Write FFH after the last program operation to reset device to read array mode.
Bus Operation
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases where multiple bytes are programmed before full status is checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
No
Yes
1
0
1
0
1
0
Command
Program Setup
Program
Comments
Data = 40H
Data = Data to Program
Addr = Location to Program
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command Comments
Check SR.3
1 = V
PP
Low Detect
Check SR.1
1 = Attempted Program to
Locked Block - Program
Aborted
Read
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Standby Check SR.4
1 = V
PP
Program Error
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Figure 14. Program Suspend/Resume Flowchart
Start
Write B0H
Read Status Register
No
Comments
Data = B0H
Addr = X
Data = FFH
Addr = X
SR.7 =
SR.2 =
1
Write FFH
Read Array Data
Program Completed
Done
Reading
Yes
Write FFHWrite D0H
Program Resumed Read Array Data
0
1
Read array data from block
other than the one being
programmed.
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check SR.2
1 = Program Suspended
0 = Program Completed
Data = D0H
Addr = X
Bus
Operation Command
0
Write 70H
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Write
Write
Write
Read
Read
Standby
Standby
Write
Data = 70H
Addr = X
Command
Program
Suspend
Read Status
Read Array
Program
Resume
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0645_14
Figure 15. Automated Block Erase Flowchart
Start
Write 20H
Write D0H and
Block Address
Read Status Register
SR.7 =
Full Status
Check if Desired
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase or after a sequence of
block erasures .
Write FFH after the last write operation to reset device to read array mode.
Bus Operation
Standby
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases
where multiple bytes are erased before full status is checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
No Yes
Suspend Erase
Suspend
Erase Loop
1
0
Standby
Command
Erase Setup
Erase C onfirm
Comments
Data = 20H
Addr = Within Block to Be
Erased
Data = D0H
Addr = Within Block to Be
Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command Comments
Check SR.3
1 = V
PP
Low Detect
Check SR.4,5
Both 1 = Command Sequence
Error
Read Status Register
Data (See Above)
V
PP
Range Error
Command Sequence
Error
Block Erase
Successful
SR.3 =
SR.4,5 =
1
0
1
0
Block Erase ErrorSR.5 =
1
0
Attempted Erase of
Locked Block - Aborted
SR.1 =
1
0
Read
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Standby Check SR.5
1 = Block Erase Error
Standby
Check SR.1
1 = Attempted Erase of
Locked Block - Erase Aborted
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0645_15
Figure 16. Erase Suspend/Resume Flowchart
Start
Write B0H
Read Status Register
No
Comments
Data = B0H
Addr = X
Data = FFH
Addr = X
SR.7 =
SR.6 =
1
Write FFH
Read Array Data
Erase Completed
Done
Reading
Yes
Write FFHWrite D0H
Erase Resumed Read Array Data
0
1
Read array data from block
other than the one being
erased.
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check SR.6
1 = Erase Suspended
0 = Erase Completed
Data = D0H
Addr = X
Bus
Operation
Write
Standby
Write
Read
Standby
Read
Command
0
Write 70H
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Write
Write
Data = 70H
Addr = X
Command
Erase Suspend
Read Status
Read Array
Erase Resume
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0645_16
Figure 17. Locking Operations Flowchart
Start
Write 60H
(Configuration Setup)
No
Comments
Data = 60H
Addr = X
Write 90H
(Read Configuration)
Read Block Lock Status
Locking
Change
Confirmed?
Locking Change
Complete
Bus
Operation
Write
Command
Write
01H, D0H, or 2FH
Write
Write
Data= 01H (Lock Block)
D0H (Unlock Block)
2FH (Lockdown Block)
Addr=Within block to lock
Command
Config. Setup
Lock, Unlock,
or Lockdown
Data = 90H
Addr = X
Write
(Optional)
Read
Configuration
Block Lock Status Data
Addr = Second addr of block
Read
(Optional)
Block Lock
Status
Confirm Locking Change on
DQ
1
, DQ
0
. (See Block Locking
State Table for valid
combinations.)
Standby
(Optional)
Optional
Write FFh
(Read Array)
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0645_17
Figure 18. Protection Register Programming Flowchart
Start
Write C0H
(Protection Reg.
Program Setup)
Write Protect. Register
Address/Data
Read Status Register
SR.7 = 1?
Full Status
Check if Desired
Program Complete
Read Status Register
Data (See Above)
V
PP
Range Error
Protection Register
Programming Error
Attempted Program to
Locked Register -
Aborted
Program Successful
SR.3, SR.4 =
SR.1, SR.4 =
SR.1, SR.4 =
FULL STATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Protection Program operations can only be addressed within the protection
register address space. Addresses outside the defined space will return an
error.
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program or after a sequence of
program operations.
Write FFH after the last program operation to reset device to read array mode.
Bus Operation
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases of multiple protection register program operations before full status is
checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
No
Yes
1, 1
0,1
1,1
Command
Protection Program
Setup
Protection Program
Comments
Data = C0H
Data = Data to Program
Addr = Location to Program
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command Comments
SR.1 SR.3 SR.4
0 1 1 V
PP
Low
0 0 1 Prot. Reg.
Prog. Error
1 0 1 Register
Locked:
Aborted
Read
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Standby
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12.0 CFI Query Structure
This appendix defines the data structure or “database” returned by the Common Flash
Interface (CFI) Query command. System software should parse this structure to gain
critical inf or mat ion such as block size, de nsity, x8/x16, and ele ctrica l sp ecif ications.
Once this inf or mat ion has b een o b tain ed , the softwa re will kno w which com ma n d sets
to u s e to enable flas h w r ites, block e r ases, and otherwis e c o n trol the flash compon ent.
The Query is part of an overall specification fo r mult ip le co mm a nd set and cont ro l
interface descriptions called Common Flash Interface, or CFI.
12.1 Query Structure Output
The Query “database” allows system software to gain information for controlling the
flash component. This section describes the de vice’s CFI-compliant interface that allows
the host system to access Query data.
Quer y da ta are always presented o n the lo west-ord er data outpu ts (D Q0-7) only. The
num erical o ff set value is th e a ddress re lative to th e m a xim u m bus w idth su pp o r ted by
th e device. On thi s f am i l y of dev i ce s , the Qu ery table dev i ce st ar ting addr es s is a 10h,
which is a word address for x16 devices.
F or a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R ” in
AS CII, appear o n the low byte a t word addresses 10h an d 11h . Thi s C FI-compl i an t
device outputs 00h data on upp er bytes. Thus, the device outputs ASCII “Q” in the low
byt e ( D Q0-7) an d 00 h i n th e high by te (D Q8-15).
At Query add resses containin g two or mor e bytes of inf or mat ion , the least s ignifica n t
data byt e i s pr esen ted at th e lo w er add r es s, and th e most sign i f i c a n t dat a byte is
pre s en ted at the h igh er ad dr ess .
In all of the following tables, addresses and data are represented in hexadecimal
notation, so t h e “h” suff i x ha s been dr o ppe d. In addition, si n c e the uppe r by te of word -
wide devices is always “00h,” the leading “00” has been dropped from the table
notation a nd on ly the low er byte value is shown . Any x16 de vice out put s can be
assume d to have 0 0 h on the u pp e r byte in th i s mod e .
Table 28. Summary of Query Structure Output as a Function of Device and Mode
Device Hex Offset Co de ASCII Value
Device Address
10: 51 “Q”
11: 52 “R”
12: 59 “Y”
Table 29. Example of Query Structure Output of x16 and x8 Devices (Sheet 1 of 2)
Word Addressing Byte Addressing
Offset Hex Code Value Offset Hex Code Value
A15–A0D15–D0A7–A0D7–D0
0010h 0051 “Q” 10h 51 “Q”
0011h 0052 “R” 11h 52 “R”
0012h 0059 “Y” 12h 59 “Y”
0013h P_IDLO PrVendor 13h P_IDLO PrVendor
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52 Document Number: 252636-005US
12.2 Query Structure Overview
Th e Q u er y co m m and ca u ses the fla sh component to display th e Co m m o n Flash
Interface (CFI) Query structure or “database.” The structure sub-sections and address
locations are summarized below.
12.3 Block Lock Stat u s Register
The Block Status Register indicates whether an er ase operation completed successfully
or whether a given block is locked or can be accessed for flash program/erase
operations.
Block Erase Status (BSR.1) allows system software to determine the success of the last
block erase operation. BSR.1 can be used just after power-up to verify that the VCC
supply was not accidentally removed during an erase operation. This bit is only reset by
issuing another erase operatio n to the block. The Block Sta tus Regi ster is accessed
from word address 02h within each block.
0014h P_IDHI ID # 14h P_IDLO ID #
0015h PLO PrVendor 15h P_IDHI ID #
0016h PHI TblAdr 16h ... ...
0017h A_IDLO AltVendor 17h
0018h A_IDHI ID # 18h
... ... ... ...
Table 29. Example of Query Structure Output of x16 and x8 Devices (Sheet 2 of 2)
Word A ddress ing Byte Addressing
Offset Hex Code Value Offset Hex Code Value
A15–A0D15–D0A7–A0D7–D0
Table 30. Query Structure
Offset Sub -Secti on Name D e scripti on Notes
00h Manufacturer Code 1
01h Device Code 1
(BA+2)h Block Status Register Block-specific information 1,2
04-0Fh Reserved Reserved for vendor-specific inform ation 1
10h CFI Query Ide ntification String Command s et ID and vendor data offset 1
1Bh System Inte rface Information Device timing & voltage information 1
27h Device Geometry Definition Flash device layout 1
PPrimary Intel-Speci fic Extended
Query Table Vendor-defined additional information specific to the Primary
Vendor Algorithm 1,3
Notes:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the
block size is 32 Kword).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
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12.4 CFI Query Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-spe cified command set(s).
12.5 System Interface Information
Table 31. Block Status Register
Offset Length Description Address Value Notes
(BA+2)h 1 Block Lock Status Register BA+2: --00 or --01 1
BSR .0 Bl ock Loc k St at us
0 = Unlocked
1 = Locked BA+2: (bit 0): 0 or 1
BSR.1 Block Lock-Down Status
0 = Not locked down
1 = Locked down BA+2: (bit 1): 0 or 1
BSR 2–7: Reserved for future use BA+2: (bit 2–7): 0
Note: 1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1
in word mode.)
Table 32. CFI Identification
Offset Length Description Addr. Hex
Code Value
10h 3 Query-unique ASCII string “QRY“ 10 --51 “Q”
11: --52 “R”
12: --59 “Y”
13h 2 Primary vendor command set and control interface ID code. 13: --03
16-bit ID code for vendor-specified algorithms 14: --00
15h 2 Extended Query Table primary algorithm address 15: --35
16: --00
17h 2 Alternate vendor command set and control interface ID code 17: --00
0000h means no second vendor-specified algorithm exists 18: --00
19h 2 Secondary algorithm Extended Query Table address. 19: --00
0000h means none exists 1A: --00
Table 33. System Interface Information (Sheet 1 of 2)
Offset Length Description Addr. Hex
Code Value
1Bh 1 VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts 1B: --27 2.7 V
1Ch 1 VCC logic supply maximum program/era se voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts 1C: --36 3.3 V
1Dh 1 VPP [pr ogramming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts 1D: --B4 11.4 V
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12.6 D e vice Geomet r y Definition
n
1Eh 1 VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts 1E: - -C6 12.6 V
1Fh 1 “n” such that typical single word program time-out = 2n µs 1F: --0 5 32 µs
1Bh 1 VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts 1B: --27 2.7 V
1Ch 1 VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts 1C: --36 3.3 V
1Dh 1 VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts 1D: --B4 11.4 V
1Eh 1 VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts 1E: - -C6 12.6 V
1Fh 1 “n” such that typical single word program time-out = 2n µs 1F: --0 5 32 µs
1Bh 1 VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts 1B: --27 2.7 V
1Ch 1 VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts 1C: --36 3.3 V
1Dh 1 VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts 1D: --B4 11.4 V
20h 1 “n” such that typical max. buffer write time-out = 2n µs 20: --00 n/a
21h 1 “n ” such that typical block erase time-out = 2n ms 21: --0A 1 s
22h 1 “n” such that typical full chip erase time-out = 2n ms 22: --00 n/a
23h 1 “n” such that maximum word program time-out = 2n time s typic a l 23 : - - 0 4 5 12 µ s
24h 1 “n” such that maximum buffer write time-out = 2n times typical 24: --00 n/a
25h 1 “n” such that maximum block erase time-out = 2n times typical 25: --03 8 s
26h 1 “n” such that maximum chip erase time-out = 2n times typical 26: --00 NA
Table 34. Device Geometry Definition (Sheet 1 of 2)
Offset Length Description Code
See Table Below
27h 1 “n” such that device size = 2n in number of bytes 27:
28h 2 Flash device interface: x8 async x16 async x8/x16 async 28: --01 x16
28:00,29:00 28:01,29:00 28:02,29 :00 29: --00
2Ah 2 “n” such that maximum number of bytes in write buffer = 2n2A: --00 0
2B: --00
Table 33. System Inter face Information (Sheet 2 of 2)
Offset Length Description Addr. Hex
Code Value
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12.7 Intel-Specific Extended Query Table
Certain flash features and commands are optional. The Intel-Specific Extended Query
table specifies this and other similar types of information.
2Ch 1
Number of erase block regions within device:
1. x = 0 me ans no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions with one or
more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
2C: --02 2
2Dh 4 Erase Block Region 1 Information 2D:
bits 0–15 = y, y+1 = number of identical-size erase blocks 2E:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F:
30:
31h 4 Erase Block Region 2 Information 31:
bits 0–15 = y, y+1 = number of identical-size erase blocks 32:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 33:
34:
Device Geometry Def init io n
Address 16-Mbit 32-Mbit
–B –T –B –T
27: --15 --15 --16 --16
28: --01 --01 --01 --01
29: --00 --00 --00 --00
2A: --00 --00 --00 --00
2B: --00 --00 --00 --00
2C: --02 --02 --02 --02
2D: --07 --1E --07 --3E
2E: --00 --00 --00 --00
2F: --20 --00 --20 --00
30: --00 --01 --00 --01
31: --1E --07 --3E --07
32: --00 --00 --00 --00
33: --00 --20 --00 --20
34: --01 --00 --01 --00
Table 34. Device Geometry Definition (Sheet 2 of 2)
Offset Length Description Code
See Table Below
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Table 35. Primary-Vendor Specific Extended Query
Offset(1)
P = 35h Length Description
(Optional Flash Features and Commands) Addr. Hex
Code Value
(P+0)h 3 Primary extended query table 35: --50 “P”
(P+1)h Unique ASCII string “PRI” 36: --52 “R”
(P+2)h 37: --49 “I”
(P+3)h 1 Major version number, ASCII 38: --31 “1”
(P+4)h 1 Minor version number, ASCII 39: --30 “0”
(P+5)h 4 Optional feature and command support (1=yes, 0=no) 3A: --66
(P+6)h bits 9–31 are reserved; undefined bits are “0.” If b it 31 is “1” then
another 31 bi t fi eld of op tional feature s fo llows at th e end of th e bit- 30
field.
3B: --00
(P+7)h 3C: --00
(P+8)h 3D: --00
bit 0 Chip erase suppor ted bit 0 = 0 No
bit 1 Suspend erase supported bit 1 = 1 Yes
bit 2 Su spend program supported bit 2 = 1 Yes
bit 3 Legacy lock/unlock supported bit 3 = 0 No
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant individual block locking supported bit 5 = 1 Yes
bit 6 Protection bits supported bit 6 = 1 Yes
bit 7 Page mode read supported bit 7 = 0 No
bit 8 Synchronous read supported bit 8 = 0 No
(P+9)h 1 Supported functions after suspend: read array, status, query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0” 3E: --01
bit 0 Program supported after erase suspend bit 0 = 1 Yes
(P+A)h 2 Block status register mask 3F: --03
(P+B)h bits 2–15 are Reserved; undefined bits are “0” 40: --00
bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes
bit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes
(P+C)h 1 VCC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts 41: --33 3.3 V
(P+D)h 1 VPP optimum prog ram/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts 42: --C0 12.0 V
Table 36. Protection Register Information (Sheet 1 of 2)
Offset(1)
P = 35h Length Description
(Optional Flash Features and Commands) Addr. Hex
Code Value
(P+E)h 1 Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available 43: --01 01
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(P+F)h
4
Protection Field 1: Protection Description 44: - -80 80h
(P+10)h
This field describes user-available One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device-
unique seri al numbers. Others are user progr ammable. Bits 0–15 point
to the Protection register Lock byte, the section’s first byte. The
following bytes are factory pre-programmed and user-programmable.
45: --00 00h
(P+11)h
bits 0–7 = Lock/bytes JEDEC-plane physical low address
bits 8–15 = Lock/bytes JEDEC -plane physical high address
bits 16–23 = “n” such that 2n = factory pre- programmed bytes
bits 24–31 = “n” such that 2n = user programmable by tes
46: --03 8 byte
(P+12)h 47: --03 8 byte
(P+13)h Reserved for future use 48:
Note: 1. The variable P is a pointer which i s defined at CFI offset 15h.
Table 36. Protection Register Information (Sheet 2 of 2)
Offset(1)
P = 35h Length Description
(Optional Flash Features and Commands) Addr. Hex
Code Value
Intel® Advanced+ Boot Block Flash Memory (C3)
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13.0 Protection Register Addressing
Table 37. Protection Register Addressing
Word-Wide Protection Register Addressing
WordUseA7A6A5A4A3A2A1A0
LOCKBoth10000000
0Factory10000001
1Factory10000010
2Factory10000011
3Factory10000100
4User10000101
5User10000110
6User10000111
7User10001000
Note: All address lines not specified in the above table must be 0 when accessing the Protection Register—for example,
A21–A8 = 0.
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
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Appendix A Ad ditional Information
Please contact your local Intel representation for additional detailed information.
Appendix B Orde ri ng Information
Table 39 shows available M18 with synchronous PSRAM device combinations and
additional device details.
Note: For devices not listed in this ta bl e, co nta ct you r local Intel representat ive.
Table 38. Related Documents
Order Number Document/Tool
292216 AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory
292215 AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture
Contact You r Intel
Representative Flash Data Integrator (FDI) Software Deve loper’s Kit
Table 39. Available Product Ordering Information
I/O
Voltage
(V)
Flash Fam ily (Mb i t)
and I/O Interface xRAM Type (Mbit)
Package
Part Number Add’l
Detail
Notes
Size
(mm) Ballout
Name Ball
Type
M18 90 nm
1.8 32 C3 (Non-Mux) 16 Async PSRAM 8x10x1.2 I RoHS PF38F1030C0ZTL0 —
Intel® Advanced+ Boot Block Flash Memory (C3)
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Appendix C SRAM Information, Not for New Designs
This appendix contains the SRAM specifications for the memory solutions are offered in
the following combin a tion s:
• 32-Mbi t flash + 8-Mb it SRA M
• 32-Mbi t flash + 4-Mb it SRA M
• 16-Mbi t flash + 4-Mb it SRA M
• 16-Mbi t flash memory + 2-Mbit SR AM
C.1 Product Overview
The C3 SCSP device combi nes flash memory and SRAM into a single packag e, which
provide s secure lo w-voltage m emor y so lut io ns for porta b le app lica tio ns.
Table 40. Block Organization (x16)
Memory Device Kwords
32-Mbit Flash 2048
16-Mbit Flash 1024
2-Mbit SRAM 128
4-Mbit SRAM 256
8-Mbit SRAM 512
Note: All words are 16 bits each.
Figure 19. Intel® Advanced+ Boot Block SCSP Block Diagram
F
-VCC
F-OE#
F-CE#
A
[Max:0]
2-, 4- or 8-Mbit
SRAM
28F160C3
or
28F320C3
Flash
S-VCC
F-VCC
Q
S-CS1
S-CS2
S-OE#
S-WE#
S-UB#
S-LB#
F-VPP
F-WE#
F-VSS
S-VSS
D[15:0]
F
-WP#
F
-RP#
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Document Number: 252636-005US 61
C.2 Mechanical Specification
Note: Shaded pins indicate upper address balls for 64-Mbit and 128-Mbit devices. In all Flash and SRAM
com bi nation s, 6 6 b all s a re po p ul a te d on l ow er de n sit y d ev ic e s. (Upper ad dre s s b alls ar e no t pop ulated) .
E
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
910 11 12
A1
Index
D
12345678
A
B
C
D
E
F
G
H
9101112
S2
S1
b
e
Bottom View - Bal l UpTop View - Ball Down
A
A2
Y
A1
Table 41. Packaging Specifications (0.18µm and 0.25µm) (Sheet 1 of 2)
Millimeters Inches
Sym Min Nom Max Min Nom Max
Package Height A 1. 400 0.0551
Ball Height A1 0.250 0.0098
Package Body Thickness A2 0.960 0.0378
Ball Lead Diameter b 0.350 0.400 0.450 0.0138 0.0157 0.0177
Package Body Length – 16-Mbit/2-Mbit
D
9.900 10.00 10.100 0.3898 0.3937 0.3976
Package Body Length –
32-Mbit/4-Mbit, 16-Mbit/4-Mbit 11.900 12.000 12.100 0.4685 0.4724 0.4764
Package Body Length –
32-Mbit/8-Mbit 13.900 14.000 14.100 0.5472 0.5512 0.5551
Package Body Width –
16-Mbit/2-Mbit, 16-Mbit/4-Mbit,
32-Mbit/4-Mbit, 32-Mbit/8-Mbit E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e 0.800 0.0315
Ball (Lead) Count N 66 66
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along E
16-Mbit/2-Mbit, 16-Mbit/4-Mbit,
32-Mbit/4-Mbit, 32-Mbit/8-Mbit S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
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Corner to Ball A1 Distance Along D
16-Mbit/2-Mbit
S2
0.500 0.600 0.700 0.0197 0.0236 0.0276
Corner to Ball A1 Distance Along D
32-Mbit/4-Mbit, 16-Mbit/4-Mbit 1.500 1.600 1.700 0.0591 0.0630 0.0669
Corner to Ball A1 Distance Along D
32-Mbit/8-Mbit 2.500 2.600 2.700 0.0984 0.1024 0.1063
Millimeters Inches
Sym Min Nom Max Min Nom Max
Package Height
16/02-Mb, 16/04-Mb, 32/08-Mb A
1. 200 0.0472
Package Height
32/04-Mb 1. 400 0.0551
Ball Height
16/02-Mb, 16/04-Mb, 32/08-Mb A1
0.200 0.0079
Ball Height
32/04-Mb 0.250 0.0098
Package Body Thickness
16/02-Mb, 16/04-Mb, 32/08-Mb A2
0.860 0.0339
Package Body Thickness
32/04-Mb 0.960 0.0378
Ball (Lead) Width
16/02-Mb, 16/04-Mb, 32/08-Mb b
0.325 0.375 0.425 0.0128 0.0148 0.0167
Ball (Lead) Width
32/04-Mb 0.350 0.40 0.450 0.0138 0.0157 0.0177
Package Body Length
16/02-Mb, 16/04-Mb D
9.900 10.000 10.100 0.3898 0.3937 0.3976
Package Body Length
32/04-Mb, 32/08-Mb 11.900 12.000 12.100 0.4685 0.4724 0.4764
Package Body Width
16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e 0.800 0.0315
Ball (Lead) Count N 66 66
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along E
16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Corner to Ball A1 Distance Along D
16/02-Mb, 16/04-Mb S2 0.500 0.600 0.700 0.0197 0.0236 0.0276
Corner to Ball A1 Distance Along D
32/04-Mb, 32/08-Mb S2 1.500 1.600 1.700 0.0591 0.0630 0.0669
Table 41. Packaging Specifications (0.18µm and 0.25µm) (Sheet 2 of 2)
Millimeters Inches
Sym Min Nom Max Min Nom Max
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
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Document Number: 252636-005US 63
C.3 Media Information
Note: Top view, ball side down. Drawing is not to scale and is only designed to show orientation of devices.
Tray Chamf er
Device Pin 1
Intel® Advanced+ Boot Block Flash Memory (C3)
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Note: Top view, ball si de down.
C.4 Ballout and Signals
C.4.1 Ballout
Notes:
1. Flash memory upgrade balls are shown up to A21 (64-Mbit flash) and A22 (128-Mbit flash). In all flash
memory and PSRAM combinations, 66 balls are populated on lower density devices. (Upper address
balls are not populated). Ball location A10 is NC on 16/2 devices only.
2. T o maintain compatibility with all JEDEC Variation B options for the C6 ball location, connect this C6 land
pad directly to the land pad for the G4 (A17) ball.
Figure 20. SCSP Device in 24 mm Tape (10 mm x 8 mm and 12 mm x 8 mm)
Device Pin 1
Figure 21. 66-Ball SCSP Package Ballout
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
NC A
20
A
11
A
15
A
14
A
13
A
12
A
16
A
8
A
10
A
9
DQ
15
S-WE#
F-WE# NC A
21
DQ
13
DQ
6
S-V
SS
F-WP# A
19
DQ
11
DQ
10
S-LB# S-UB# S-OE# DQ
9
DQ
8
A
18
A
17
A
7
A
6
A
3
A
2
NC NC A
5
A
4
A
0
F-CE# F-V
SS
F-RP# A
22
DQ
12
S-CS
2
910 11 12
F-V
SS
NC
DQ
14
DQ
7
DQ
4
DQ
5
DQ
2
DQ
3
DQ
0
DQ
1
A
1
S-CS
1
#
F-OE# NC NC
S-V
CC
F-V
CC
Top View, Balls Down
F-V
CCQ
F-V
PP
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C.4.2 Signal Descr ip tions
Table 42. Intel® Advanced+ Boot Block SCSP Ball Descriptions (Sheet 1 of 2)
Symbol Type Name and Function
A[20:0] INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or
erase cycle.
2-Mbit : A[16:0]
4-Mbit : A[18:0]
16-Mbit : A[19:0]
32-Mbit A[20:0]
DQ[15:0] INP UT /
OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data for SRAM write operations and on the second F-CE# and F-WE# cycle during a
flash program command.
Inputs commands to the flash memory Command U ser Interface when F -CE# and F-WE# are
asserted.
Data is internally latched.
Outputs array, configuration, and status register data.
The data balls float to tristate when th e chip is deselected or the outputs are disabled.
F-CE# INPUT
FLASH CHIP ENABLE: Activates the flash internal control logic, input buffers, decoders, and
sense amplifiers.
F-CE# is active low.
F-CE# high deselects the flash memory device and reduces power consum ption to standby levels.
S-CS1#INPUT
SRAM CHIP SELECT1: Activates the SRAM internal control logic, input buffers, decoders, and
sense amplifiers.
S-CS1# is active low.
S-CS1# high deselects the SRAM memory device and reduces power consu mption to standby
levels.
S-CS2INPUT
SRAM CHIP SELECT2: Activates the SRAM internal control logic, input buffers, decoders, and
sense amplifiers.
S-C S 2 is acti ve hi gh.
S-CS2 low deselects the SRAM memory device and reduces p ower consumption to st and by levels.
F-OE# INPUT FLASH OUTPUT ENABLE: Enables flash memory outputs through the data buffers during a read
operation. F-OE# is active low.
S-OE# INPUT SRAM OUTPUT ENABLE: Enables SRAM outputs through the data buffers during a read
operation. S-OE# is active low.
F-WE# INPUT FLASH WRITE ENABLE: Controls writes to the flash memory command register and memory
arr ay. F- WE# is ac tive l ow . Add resses and data ar e latche d on t he ri sing edge of the se cond F- WE#
pulse.
S-WE# INPUT SR AM WRIT E ENAB LE: Controls writes to the SRAM memory array. S-WE# is active low.
S-UB# INPUT SR AM UPPER BYTE EN ABLE: Enables the upper byte for SRAM (DQ 8–DQ15).
S-UB# is active low.
S-LB# INPUT SRAM LOWER BYTE ENABLE: Enables the lower byte for SRAM (DQ0–DQ7).
S-LB# is active low.
F-RP# INPUT
FLASH RES ET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep
power-down mode.
When F-RP# is at logic low, the device is in reset/deep po wer-down mode, which drives
the outputs to High-Z, resets the Write State Machine, and mi nimizes current levels (ICCD).
When F-RP# is at logic high, the device is in standard operation.
When F-RP# transitions from logic-low to logic-high, the device resets all blocks to locked and
defaults to the read arra y mode.
Intel® Advanced+ Boot Block Flash Memory (C3)
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
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66 Document Number: 252636-005US
C.5 Bus Operation
All bus cycles to or from the SCSP conform to standard microcontroller bus cycles. Four
con tro l si gn als di cta te the data fl o w i n and ou t of the fl ash c ompon ent:
•F-CE#
•F-OE#
•F-WE#
•F-RP#
Four separate control signals handle the data flow in and out of the SRAM component:
•S-CS1#
•S-CS2
•S-OE#
•S-WE#
The flash memory device provides four read modes:
•Read array
• Read id en t i fi er
•Read status
•CFI query
F-WP# INPUT
FLASH WRITE PROTECT: Controls the lock-down function of the flexible Locking feature.
When F-WP# is a lo gic low, the lock-down mechanism is enabled and blocks marked
lock-down cannot be unlocked through software. After F-WP# goes low, any blocks previously
marked lock-down revert to that state.
When F-WP# is logic high, the lock-down mechanism is disabled. Blocks previously
locked-down are now locked, and can be unlocked or locked through software.
F-VCC SUPPLY FLASH POWER SUPPLY: [2.7 V–3.3 V] Supplies power for device core operations.
F-VCCQ SUPPLY F LAS H I/O POWER SUPPLY: [2.7 V–3.3 V] Supplies power for device I /O operations.
S-VCC SUPPLY SR AM POW ER SUPPLY : [2.7 V–3.3 V] Supplies power for device operations.
F-VPP INPUT /
SUPPLY
FLASH PROGRAM/ER ASE P OWER SUP PL Y: [1.65 V–3.3 V or 11.4 V–12.6 V] Operates as an
input at logic levels to control complete flash memory prote ction. Supplies power for accelerated
flash memory prog ram and erase operations in 12 V ± 5% range. This bal l cannot be left float in g.
Lower F-VPP ≤ VPPLK, to protect all contents against Program and Erase commands.
Set F-VPP =F-V
CC for in-system read, program and erase operations. In this co nfigurat ion,
F-VPP can drop as low as 1.65 V to allow for resistor or diode drop fro m the system supply.
If F-VPP is driven by a logic signal, then VIH = 1.65 V. That is, F-VPP must remain above 1.65 V to
modify in-system flash memory.
Raise F-VPP to 1 2 V ± 5% for faster progr am and erase in a production environ ment. 12 V
± 5% to F-VPP can be app lied for a maximum of 10 00 cy cles on the main block s and 250 0 cycle s on
the parameter blocks. F-VPP can be con nected to 12 V for a total of 80 hours maximum.
F-VSS SUPPLY FLASH G R OUN D: For all internal circuitry. All ground inputs must be connected.
S-VSS SUPPLY SRAM GROUND: For all internal circuitry. All ground inputs must be connected.
NC NOT CONNECTED: Internally disconnected within the device.
Table 42. Intel® Advanced+ Boot Block SCSP Ball Descriptions (Sheet 2 of 2)
Symbol Type Name and Function
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
February 2007 DS
Document Number: 252636-005US 67
Thes e flash memory read modes do not depend on the F-VPP voltage. Upon initial
device power-u p or aft er ex it from r es et, the fla s h m em ory devic e auto m ati c ally
defaults to r ead arra y mo de. F-CE # an d F-OE# must be as s er ted to obta in data from
the flash memory device.
The SRAM provides only one read mode. S-CS1#, S-CS2, and S-OE# must be asserted
to obtain data from the SRAM device.
C.5.1 Output Disable
When F-OE# and S-OE# are deasserted, the SCSP output signals are placed in a high-
impedance s tate.
C.5.2 Standby
When F-CE# and S-CS1# or S-CS2 ar e deasserted, th e SC S P en ters a stan dby mode,
which substantially reduces device power consumption. In standby mode, outputs are
placed in a high-impedance state independent of F-OE# and S-OE#. If the flash
memo r y devic e is des elec ted du r in g a pr o gram or eras e o p era tion , the fla s h m em o r y
contin ues to co n su m e active po wer u ntil the pr ogram or eras e o pe ratio n is c o m ple te.
C.5.3 Flash Reset
The flash memory device enters a reset mode when RP# is driven low. In reset mode ,
internal circuitry is turned off and outputs are placed in a high-impedance state.
Table 43. Intel Advanced+ Boot Block Flash Memory SCSP Bus Operations
Modes
Flash Signals SRAM Signals Memory
Output
Notes
F-RP#
F-CE#
F-OE1#
F-WE#
S-CS1#
S-CS2
S-OE1#
S-WE#
S-UB#,S-LB#(1)
Memory Bus Contr ol
D0–
D15
FLASH
Read H L L H
SRAM must be in High Z
Flash DOUT 2,3,4
Write H L H L Flash DIN 2,4
Standby H H X X
Any SRAM mode is allowable
Other High Z 5,6
Output Disable H L H H Other High Z 5,6
Reset L X X X Other High Z 5,6
SRAM
Read FLASH must be in High Z LHLHLSRAMD
OUT 2,4
Write L H H L L SRAM DIN 2,4
Standby
Any FLASH mode is allowable
HXXXX
Other High Z 4,5,6
XLXXX
Output Disable L H H H X Other High Z 4,5,6
Data Retention same as a standby Other Hig h Z 4,5,7
Notes:
1. Two devices cannot drive the memory bus at the same time.
2. To place the SRAM into data retention mode, lower the S-VCC signal to the VDR range, as specified.
Intel® Advanced+ Boot Block Flash Memory (C3)
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
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After returning from reset, a time tPHQV is required u ntil ou tp ut s are valid . A del ay
(tPHWL or tPHEL) is required before a write sequence can be initiated. After this wake-up
interval, normal operation is restored.
• The flash memory device defaults to read array mode.
• The status register is set to 80h.
• The read configura tion register defaults to asynchronous reads.
If RP# is taken low during a block er ase or progr am oper ation, the operation aborts and
the memory contents at the aborted location are no longer valid.
C.5.4 Write
• Wr ites to flash memory occur when both F-CE# and F-WE# are asserted and F-
OE# is deasserte d.
• Writes to SRAM occur when both S-CS1# and S-WE# are as ser ted and S-OE # and
S-CS2 are deasserted.
Commands are written to the flash memory Command User Interfa ce (CUI), using
standard microprocessor write timings to control flash memory operations. The CUI
do es n o t o cc upy an ad dr essabl e memory locatio n within th e f las h m emo ry devi c e. Th e
address and data buses are latched on the rising edge of the second F-WE# or F-CE#
pulse , whicheve r occurs fi rst.
C.6 Absolute Maximum Ratings
Warning: Stressing th e de vi c e beyo nd the Absol u te Maxi mum Ratings m i ght cause perm an ent
damage. These are stress ratings only. Do not operate the flash memory device beyond
the Operating Conditions. Extended exposure beyond these Operating Conditions might
affe ct device reliability.
NOTICE: This datasheet contains information on products in full production. The specifications are subject to
change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a
design.
Table 44. Absolute Maximum Ratings
Paramete r Maximum Rating Notes
Extended Operating Temperature
–25°C to +85°C
During Read
During Flash Block Erase and Program
Temperature under Bias
Storage Temperature –65°C to +125°C
Voltage on Any Ball (except F-VCC /F-VCCQ / S-VCC and F- VPP ) w i th R e spe ct
to GND –0.5 V to +3.3 V 1
F-VPP Voltage (for Block Erase and Program) with Respect to GND –0.5 V to +13.5 V 1,2,4
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
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February 2007 DS
Document Number: 252636-005US 69
C.7 Operating Conditions
C.8 Capacitance
TCASE = +25°C, f = 1 MHz
F-VCC / F-VCCQ / S-VCC Supply Voltage with Respect to GND –0.2V to +3.3 V
Output Short Circuit Current 100 mA 3
Notes:
1. Minimum DC volta ge is –0.5 V o n input/output balls . During transitions, this level may undershoot
to –2.0 V for period s < 20 ns. Maximum DC vol tage on input /output balls is F-V CC / F-V CCQ / S-VCC
+ 0.5 V which, during transitions, may overshoot to
F-VCC / F-VCCQ / S-VCC + 2.0 V for periods < 20 ns.
2. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns.
3. F-VPP voltage is normally 1.65 V– 3.3 V. Connection to supply of 11.4 V–12. 6 V can only be done for
1000 cycles on the main blocks and 2500 cycles on the par ameter block s during progr am/era se. F-
VPP may be connected to 12 V for a total of 80 hours maximum.
4. Output shorted for no more than one second. No more than one output shorted at a time.
Table 45. Maximum Operating Conditions
Symbol Parameter Notes Min Max Units
TCASE Operating Temperature –25 +85 °C
VCC / VCCQ F-VCC /F-VCCQ /S-VCC Su pp ly Voltag e 1 2 .7 3.3 Volt s
VPP1 Supply Voltage 1 1.65 3.3 Volts
VPP2 1, 2 11.4 12.6 Volts
Cycling Block Erase Cycling 2 100,000 Cycles
Notes:
1. F-VCC/F-VCCQ must share the same supply. F-VCC/S-VCC must share the same supply when not in
data retention.
2. Applying F-VPP = 11.4 V–12.6 V during a progra m/erase can only be done for a maximum of 1000
cycles on t he main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V
for a total of 80 hours maximum.
Table 44. Absolute Maximum Ratings
Parameter Maximum Rating Notes
Table 46. Capacitance
Sym Parameter Notes Typ Max Units Conditions
CIN Input Capacitan ce 1 16 18 pF VIN =0V
COUT Output Capacitance 1 20 22 pF VOUT =0V
Note: Sampled, not 100% tested.
Intel® Advanced+ Boot Block Flash Memory (C3)
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C.9 Electrical
C.9.1 SRAM DC Characteri stics
Note: All cu rre nts a re in RM S unless o therwise not ed . Ty pical values a t nom inal P-VCC,
TCASE = +25 °C.
Table 47. SRAM DC Characteristics
Symbol Parameter Device 2.7 V – 3.3 V Un it Test Conditions
Typ Max
ILI Input Load Current — — ± 2µA
F-VCC/S-VCC =V
CC Max
VIN =V
CCMax or GND
ILO Output Leakage Current — 0.2 ± 10 µA F-VCC/S-VCC =V
CC Max
VIN =V
CC Max or GND
ICCS VCC Standby Current
2-Mb
SRAM —10µA
S-VCC =V
CC Max
S-CS1# = VCC, S-CS2 = VCC or
S-CS2 = GND
VIN =V
CC Max or GND
4-Mb
SRAM —15µA
8-Mb
SRAM —25µA
ICC Operating Power Supply Current
(cycle time = 1 μs)
2-Mb
SRAM —7mA
IIO =0 mA, S-CS1#=V
IL
S-CS2 = S-WE# = VIH
VIN =V
IL or VIH
4-Mb
SRAM —10mA
8-Mb
SRAM —10mA
ICC2 Operating Power Supply Current
(min cycle time)
2-Mb
SRAM —40mA
Cycle time = Min, 100% duty,
IIO =0 mA, S-CS1#= V
IL,
S-CS2 = VIH, VIN =V
IL or VIH
4-Mb
SRAM —45mA
8-Mb
SRAM —50mA
Table 48. SRAM Voltage Characteristics
Symbol Parameter Device 2.7 V – 3.3 V Units Test Conditions
Min Max
VIL Input Low Voltage — –0.2 0.6 V —
VIH Input High Voltage — 2.3 VCC +0.2 V —
VOL Output Low Voltage — –0.10 0.10 V F-VCC/S-VCC =V
CC Min
IOL = 100 µA
VOH Output High Vo ltage — VCC –0.1 — V F-VCC/S-VCC =V
CC Min
IOH = –100 µA
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
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C.9.2 SRAM AC Characteristics—Read Operations
Table 49. SRAM AC Characteristics—Read Operations
#Sym Parameter
Density 2/4/8-Mbit
UnitVol tage Rang e 2. 7 V – 3.3 V
Note Min Max
R1 tRC Read Cycle Time 70 – ns
R2 tAA Address to Output Delay – 70 ns
R3 tCO1, tCO2 S-CS1#, S-CS2 to Output Delay – 70 ns
R4 tOE S-OE# to Output Delay – 35 ns
R5 tBA S-UB#, LB# to Output Delay – 70 ns
R6 tLZ1, tLZ2 S-CS1#, S-CS2 to Output in Low Z 1,2 5 – ns
R7 tOLZ S-OE# to Output in Low Z 2 0 – ns
R8 tHZ1, tHZ2 S-CS1#, S-CS2 to Output in High Z 1,2,3 0 25 ns
R9 tOHZ S-OE# to Output in High Z 2,3 0 25 ns
R10 tOH Output Hold from Address, S-CS1#,
S-CS2, or S-OE# Change, Whichever Occurs First 0–ns
R11 tBLZ S-UB#, S-LB# to Output in Low Z 2 0 – ns
R12 tBHZ S-UB#, S-LB# to Output in Hi gh Z 2 0 25 ns
Note:
1. At any given temperature and voltage condition, tHZ (Max) is less than and tLZ (Max) both for a given device and from
device to device interconnection.
2. Sampled, but not 100% tested.
3. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
Figure 22. AC Waveform: SRAM Read Operations
High Z
Valid Output
Address Stable
Data Valid
Device
Address Selection
Standby
ADDRESSES (A)
V
IH
V
IL
V
IH
V
IL
CS
1
# (E
1
)
V
IH
V
IL
V
OH
V
OL
V
IH
OE# (G)
WE# (W)
DATA (D/ Q)
UB#, LB#
High Z
V
IH
V
IL
R1
R2
R4
R3
R6
R7
R8
R9
R10
CS
2
(E
2
)
V
IH
V
IL
V
IH
R5
R11
R12
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C.9.3 SRAM AC Characterist ics—Writ e Operations
A write occurs during the overlap (tWP) of low S-CS1# and low S-WE#. A write begins
when S-CS1# goe s low and S-WE# goes low with asserting S-UB# or S-LB# fo r single
byte oper at ion or simult ane o us ly a sserting S-UB# a nd S-LB# for doubl e byte
op eration. A writ e en d s at the earlie s t trans ition wh en S-C S1# go es high and S-W E #
goes high. The tWP is measured from the beginning of write to the end of write.
Table 50. SRAM AC Characteristics—Write Operations
#Sym Parameter
Density 2/4/8-Mbit
UnitVol t 2.7 V – 3.3 V
Note Min Max
W1 tWC Write Cycle Time 70 – ns
W2 tAS Address Setup to S-WE# (S-CS1#) and S-UB#,
S-LB# Going Low 10–ns
W3 tWP S-WE# (S-CS1#) Pulse Width 2 55 – ns
W4 tDW Data to Write Tim e Overlap 30 – ns
W5 tAW Address Setup to S-WE# (S-CS1#) Going High 60 – ns
W6 tCW S-CE# (S-WE#) Setup to S-WE# (S-CS1#) Going High 60 – ns
W7 tDH Data Hold Time from S-WE# (S-CS1#) High 0 – ns
W8 tWR Write Recovery 3 0 – ns
W9 tBW S-UB#, S-LB# Setup to S-WE# (S-CS1#) Going High 60 – ns
Notes:
1. tAS is measured from the address valid to the beginning of write.
2. tWP is measu red from S-CS 1# going low to end of write.
3. tWR is me asured from the end of write to the address change. tWR applied in case a write ends as S-CS1# or S-WE#
going high.
Figure 23. AC Waveform: SRAM Write Operations
High Z
Data In
Address Stable
Device
Address Selection
Standby
ADDRESSES (A)
V
IH
V
IL
V
IH
V
IL
CS
1
# (E
1
)
V
IH
V
IL
V
OH
V
OL
V
IH
OE# (G)
WE# (W)
DATA (D/Q)
UB#, LB#
High Z
V
IH
V
IL
W1
W8
CS
2
(E
2
)
V
IH
V
IL
V
IH
W9
W6
W5
W2
W3
W4
W7
Intel® Advan ce d + Bo ot Bl ock Flash Memory (C3)
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C.9.4 SRAM D ata Re te ntion Characteris t ics—Extended Temperature
Table 51. SRAM Data Retention Characteristics(1)—Extended Temperature
Sym Parameter No te Min Typ Max Unit Test Conditions
VDR S-VCC for Data Retention
2
1.5 – 3.3 V CS1# ≥VCC – 0.2 V
IDR
Deep Retention Current -
8-Mbit ––6µA
S-VCC =1.5 V
CS1# ≥VCC – 0.2 V
Deep Retention Current -
4-Mbit ––5µA
Deep Retention Current -
2-Mbit ––4µA
tSDR Data Retention Set-up Time 0 – – ns See Data Retention Waveform
tRDR Recovery Time tRC ––ns
Notes:
1. Typical values at nominal S-VCC, TCASE = +25 °C.
2. S-CS1# ≥ VCC – 0.2 V, S-CS2 ≥ VCC – 0.2 V (S-CS1# controlled) or S-CS2 ≤ 0.2 V (S-CS2 controlle d).
Figure 24. SRAM Data Retention Waveform
V
CC
3.0/2.7V
CS
1
# (E
1
)
2.2V
V
DR
CS
2
(E
2
)
GND
V
CC
3.0/2.7V
0.4V
V
DR
GND
CS
1
# Controlled
CS
2
Controlled
Data Retention Modet
SDR
t
RDR
Data Retention Mode
t
SDR
t
RDR
Intel® Advanced+ Boot Block Flash Memory (C3)
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C.10 SRAM Order Information
.
Table 52. Ordering Information for Product Combinations with 0.25 µm to 0.13 µm Flash
Table 53. Ordering Information for Combinations specific to 32M 0.13 µm Flash
R D 2 8 F 1 6 0 2 C 3 T D 7 0
Package
RD = Leaded Ball Stacked-CSP
Prod uct Li n e D esi gn ator
16 Mbit = 70, 90 , or 110 ns
32 Mbit = 70 or 90 ns
Access S p eed (n s)
28F or 38F = Intel® Flash Memory
Fl ash D ensi ty
320 = x16 (32 Mbit)
160 = x16 (16 Mbit)
SRAM Device Density
8 = x16 (8 Mbit)
4 = x16 (4 Mbit)
2 = x16 (2 Mbit)
P aram eter Locatio n
T = Top Blocking
B = Bottom Blocking
D = 0.13μm
<blank> = 0.25μm or
0.18μm (refer to access
speed for differientation)
Technology
Differentiator
C = Advanced+ Boot Block
Flash Memory
Prod uct Fam i ly
PF = Lead-Free Ball Stacked-CSP
Parameter Location
R D 3 8 F 1 0 1 0 C 0 Z T L 0
Package
RD = Leaded Ball Stacked -CSP
Product Line Designator
Density
Flash #1 = 1 = 32 Mbit
Flash #2 = 0 = No Die
Flash #3 = 1 = 4 Mbit SRAM
= 2 = 8 Mbit SRAM
Flash #4 = 0 = No Die
Product Family
0 = Original Version of
this product:
Flash Speed = 70 ns
Flash Process = 0.13 μm
Vccq = 2.7 V to 3 .3 V
Devi ce Details
L = 72 ball "I"-ballout
Pi nout I ndicator
T = Top Blocking
B = Bottom Blocking
Voltage
Z = 3.0V I/O
C = Advanced+ Boot Block Flash Memory
38F = Intel Flash Stacked Memory
®
PF = Lead -Free Ball Stacked-CSP
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Table 54. Ordering Information Valid Combinations
0.25µm C 3 SCSP 0.18µm C 3 SCSP 0.13µm C 3 SCSP
32 - Mb i t No lo n ge r availa b le .
RD28F3208C3T70
RD28F3208C3B70
RD28F3208C3T90
RD28F3208C3B90
RD28F3204C3T70
RD28F3204C3B70
RD38F1010C0ZTL0
RD38F1010C0ZBL0
PF38F1010C0ZTL0
PF38F1010C0ZBL0
RD38F1020C0ZTL0
RD38F1020C0ZBL0
16-Mbit
RD28F1604C3T90
RD28F1604C3B90
RD28F1604C3T110
RD28F1604C3B110
RD28F1602C3T90
RD28F1602C3B90
RD28F1602C3T110
RD28F1602C3B110
RD28F1602C3T70
RD28F1602C3B70
PF28F1602C3TD70
RD28F1602C3TD70
RD28F1602C3BD70
RD28F1604C3TD70
RD28F1604C3BD70
Intel® Advanced+ Boot Block Flash Memory (C3)
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