LP3855ESX-5.0/NOPB - Texas Instruments

OUT

GND

LP3855-2.5 COUT*

10 PF

CIN*

INPUT VOUT

10 PF

SD** SENSE

2.5V, 1.5A

3.3V ± 10%

* TANTALUM OR CERAMIC

OUTIN

GND

LP3852-2.5 COUT*

10 PF

CIN*

INPUT VOUT

10 PF

ERROR**

SD** ERROR

2.5V, 1.5A

3.3V ± 10%

* TANTALUM OR CERAMIC

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

LP385x 1.5-A Fast Response Ultra-Low Dropout Linear Regulators

1 Features 3 Description

The LP3852 and LP3855 series of fast ultra-low

1• Input Supply Voltage: 2.5 V to 7 V dropout linear regulators operate from a 2.5-V to 7-V

• Ultra-Low Dropout Voltage input supply. A wide range of preset output voltage

• Stable with Selected Ceramic Capacitors options are available. These ultra-low dropout linear

regulators respond very quickly to step changes in

• Low Ground-Pin Current load, which makes them suitable for low voltage

• Load Regulation of 0.06% microprocessor applications. The LP3852 and

• 10-nA Quiescent Current in Shutdown Mode LP3855 are developed on a CMOS process which

allows low quiescent-current operation independent

• Specified Output Current of 1.5 A DC of output load current, typically 4 mA at 1.5-A load

• Output Voltage Accuracy ± 1.5% current. This CMOS process also allows the LP3852

• ERROR Pin Indicates Output Status and LP3855 to operate under extremely low dropout

• SENSE Option Improves Load Regulation conditions, typically 24 mV at 150-mA load current

and 240 mV at 1.5-A load current.

• Overtemperature/Overcurrent Protection

•−40°C to 125°C Junction Temperature Range The LP3852 has an ERROR pin; it goes low when

the output voltage drops 10% below nominal value.

The LP3855 has a SENSE pin to improves regulation

2 Applications at remote loads.

• Microprocessor Power Supplies The LP3852 and LP3855 are available with fixed

• GTL, GTL+, BTL, and SSTL Bus Terminators output voltages from 1.8 V to 5 V with a specified

• Power Supplies for DSPs accuracy of ±1.5% at room temperature, and ±3%

• SCSI Terminator over all conditions (varying line, load, and

temperature). Contact Texas Instruments Sales for

• Post Regulators specific voltage option needs.

• High Efficiency Linear Regulators

• Battery Chargers Device Information(1)

• Other Battery Powered Applications PART NUMBER PACKAGE BODY SIZE (NOM)

SOT (5) 6.50 mm x 3.56 mm

LP3852 TO-263 (5) 10.16 mm x 8.42 mm

LP3855 TO-220 (5) 14.986 mm x 10.16 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

4 Simplified Schematics

**SD and ERROR pins must be pulled high through a 10-kΩpull-up resistor. Connect the ERROR pin to ground if this

function is not used.

**SD must be pulled high through a 10-kΩpull-up resistor.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

www.ti.com

Table of Contents

9.3 Feature Description................................................. 12

1 Features.................................................................. 19.4 Device Functional Modes........................................ 13

2 Applications ........................................................... 110 Application and Implementation........................ 14

3 Description............................................................. 110.1 Application Information.......................................... 14

4 Simplified Schematics........................................... 110.2 Typical Applications ............................................. 14

5 Revision History..................................................... 211 Power Supply Recommendations ..................... 17

6 Voltage Options ..................................................... 312 Layout................................................................... 18

7 Pin Configuration and Functions......................... 412.1 Layout Guidelines ................................................. 18

8 Specifications......................................................... 512.2 Layout Example .................................................... 18

8.1 Absolute Maximum Ratings ...................................... 512.3 RFI and/or EMI Susceptibility................................ 19

8.2 ESD Ratings.............................................................. 512.4 Power Dissipation/Heatsinking.............................. 19

8.3 Recommended Operating Conditions....................... 513 Device and Documentation Support................. 21

8.4 Thermal Information.................................................. 513.1 Related Links ........................................................ 21

8.5 Electrical Characteristics........................................... 613.2 Trademarks........................................................... 21

8.6 Typical Characteristics.............................................. 813.3 Electrostatic Discharge Caution............................ 21

9 Detailed Description............................................ 11 13.4 Glossary................................................................ 21

9.1 Overview................................................................. 11 14 Mechanical, Packaging, and Orderable

9.2 Functional Block Diagrams ..................................... 11 Information........................................................... 21

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (December 2014) to Revision I Page

• Changed pin names to TI nomenclature; correct typos ........................................................................................................ 1

• Changed pin numbers and I/O types to correct errors .......................................................................................................... 4

• Changed Handling to ESD Ratings ....................................................................................................................................... 5

Changes from Revision G (April 2013) to Revision H Page

• Added Device Information and Handling Rating tables, Feature Description,Device Functional Modes,Application

and Implementation,Power Supply Recommendations,Layout,Device and Documentation Support, and

Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section;

updated Thermal Values ....................................................................................................................................................... 1

Changes from Revision F (April 2013) to Revision G Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 20

Product Folder Links: LP3852 LP3855

LP3852

LP3855

www.ti.com

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

6 Voltage Options(1)(2)

DEVICE NUMBER PACKAGE VOLTAGE OPTION (V)

1.8

TO-220 (5) 2.5

LP3852 DDPAK/TO-263 (5)

LP3855 3.3

SOT-223 (5) 5.0

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available on the Packaging Information page at www.ti.com.

Product Folder Links: LP3852 LP3855

1 2 34

SD IN OUT ERROR/SENSE

GND

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

www.ti.com

7 Pin Configuration and Functions

SOT-223 (NDC)

5 Pins

Top View

5 Pins 5 Pins

DDPAK/TO-263 (KTT) TO-220 (NDH)

Top View Top View, Bent, Staggered Leads

Pin Functions for SOT-223

LP3852 LP3855 I/O DESCRIPTION

NAME NDC NDC

ERROR 4 N/A O ERROR flag

GND 5 5 — Ground

IN 2 2 I Input supply

OUT 3 3 O Output voltage

SD 1 1 I Shutdown

SENSE N/A 4 I Remote sense pin

Pin Functions for TO-220 and TO-263

LP3852 LP3855 I/O DESCRIPTION

NAME KTT/NDH KTT/NDH

ERROR 5 N/A O ERROR flag

GND 3 3 — Ground

IN 2 2 I Input supply

OUT 4 4 O Output voltage

SD 1 1 I Shutdown

SENSE N/A 5 I Remote sense pin

Product Folder Links: LP3852 LP3855

LP3852

LP3855

www.ti.com

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNIT

Lead temperature (soldering, 5 sec.) 260 °C

Power dissipation(2) Internally limited

Input supply voltage (survival) –0.3 7.5

Shutdown input voltage (survival) –0.3 7.5 V

Output voltage (survival)(3),(4) –0.3 6

IOUT (survival) Short-circuit protected

Maximum voltage for ERROR pin VIN

Maximum voltage for SENSE pin VOUT

Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be

derated at RθJA = 32°C/W (with 0.5 in2, 1-oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO-263 surface-

mount package must be derated at RθJA = 40.3°C/W (with 0.5 in2, 1-oz. copper area), junction-to-ambient. See Application and

Implementation section.

(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.

(4) The output PMOS structure contains a diode between the IN and OUT terminals. This diode is normally reverse biased. This diode will

get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can

typically withstand 200 mA of DC current and 1 A of peak current.

8.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

Input supply voltage(1) 2.5 7 V

Shutdown input voltage −0.3 7

Maximum operating current (DC) 1.5 A

Junction temperature −40 125 °C

(1) The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5 V, whichever is greater.

8.4 Thermal Information LP3852/LP3855

THERMAL METRIC(1) NDC KTT NDH UNIT

5 PINS 5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance, High-K 65.2 40.3 32

RθJC(top) Junction-to-case (top) thermal resistance 47.2 43.4 43.8

RθJB Junction-to-board thermal resistance 9.9 23.1 18.6 °C/W

ψJT Junction-to-top characterization parameter 3.4 11.5 8.8

ψJB Junction-to-board characterization parameter 9.7 22 18

RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 1 1.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Product Folder Links: LP3852 LP3855

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

www.ti.com

8.5 Electrical Characteristics

Unless otherwise specified: VIN = VOUT(NOM) + 1 V, IOUT = 10 mA, COUT = 10 µF, VSD = 2 V, TJ= 25°C.

PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT

VOUT +1 V ≤VIN ≤7 V –1.5% 0 1.5%

10 mA ≤IOUT ≤1.5 A

VOUT Output voltage tolerance(3)

For –40°C ≤TJ≤125°C –3% 3%

VOUT +1 V ≤VIN ≤7 V 0.02%

ΔVOUT/ΔVIN Output voltage line regulation(3) For –40°C ≤TJ≤125°C 0.06%

10 mA ≤IOUT ≤1.5 A 0.06%

ΔVOUT/ΔIOUT Output voltage load regulation(3) For –40°C ≤TJ≤125°C 0.12%

IOUT = 150 mA 24 35

For –40°C ≤TJ≤125°C 45

Dropout voltage

TO-263 and TO-220(4) IOUT = 1.5A 240 280

For –40°C ≤TJ≤125°C 380

VIN - VOUT mV

IOUT = 150mA 26 35

For –40°C ≤TJ≤125°C 45

Dropout voltage

SOT(4),(5) IOUT = 1.5 A 260 320

For –40°C ≤TJ≤125°C 435

IOUT = 150 mA 3 9

For –40°C ≤TJ≤125°C 10

Ground pin current in normal

IGND mA

operation mode IOUT = 1.5 A 3 9

For –40°C ≤TJ≤125°C 10

VSD ≤0.3V 0.01 10

Ground pin current in shutdown

IGND µA

mode -40°C ≤TJ≤85°C 50

IOUT(PK) Peak output current VO≥VO(NOM) – 4% 1.8 A

SHORT CIRCUIT PROTECTION

ISC Short circuit current 3.2 A

SHUTDOWN INPUT

VSDT Rising from 0.3 V until 1.3

Output = ON

For –40°C ≤TJ≤125°C 2

VSDT Shutdown threshold V

VSDT Falling from 2 V until 1.3

Output = OFF

For –40°C ≤TJ≤125°C 0.3

TdOFF Turnoff delay IOUT = 1.5 A 20 µs

TdON Turnon delay IOUT = 1.5 A 25 µs

ISD SD input current VSD = VIN 1 nA

ERROR PIN

See(6) 10%

VTThreshold For –40°C ≤TJ≤125°C 5% 16%

See(6) 5%

VTH Threshold hysteresis For –40°C ≤TJ≤125°C 2% 8%

(1) Limits are specified by testing, design, or statistical correlation.

(2) Typical numbers are at 25°C and represent the most likely parametric norm.

(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.

Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line

and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the

output voltage tolerance specification.

(4) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value.

Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5 V, the drop-out voltage is

nothing but the input to output differential, since the minimum input voltage is 2.5 V.

(5) The SOT-223 package devices have slightly higher dropout due to increased bond wire resistance.

(6) ERROR threshold and hysteresis are specified as percentage of regulated output voltage. See ERROR Flag Operation.

Product Folder Links: LP3852 LP3855

LP3852

LP3855

www.ti.com

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

Electrical Characteristics (continued)

Unless otherwise specified: VIN = VOUT(NOM) + 1 V, IOUT = 10 mA, COUT = 10 µF, VSD = 2 V, TJ= 25°C.

PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT

Isink = 100 µA 0.02

VEF(Sat) ERROR pin saturation V

For –40°C ≤TJ≤125°C 0.1

Td Flag reset delay 1 µs

Ilk ERROR pin leakage current 1 nA

Imax ERROR pin sink current VError = 0.5 V 1 mA

AC PARAMETERS

VIN = VOUT + 1 V

COUT = 10 µF 73

VOUT = 3.3V, f = 120 Hz

PSRR Ripple rejection dB

VIN = VOUT + 0.5 V

COUT = 10 µF 57

VOUT = 3.3V, f = 120 Hz

ρn(l/f) Output noise density f = 120 Hz 0.8 µV

BW = 10Hz – 100 kHz 150

VOUT = 2.5 V

enOutput noise voltage µV (rms)

BW = 300 Hz – 300 kHz 100

VOUT = 2.5 V

Product Folder Links: LP3852 LP3855

-40 -20 0 20 40 60 80 100 125

JUNCTION TEMPERATURE (oC)

0.5

1.5

2.5

DC LOAD REGULATION (mV/A)

-40 -20 0 20 40 60 80 100 125

JUNCTION TEMPERATURE (oC)

0.5

1.5

2.5

' VOUT/VOLT CHANGE in VIN (mV)

SHUTDOWN IQ (PA)

TEMPERATURE (oC)

-40 -20 0 20 40 60 80 100 125

0.001

0.01

0.1

ERROR THRESHOLD (% of VOUT)

JUNCTION TEMPERATURE (oC)

-40 -20 0 20 40 60 80 100 125

0 0.5 11.5

100

200

300

400

500

600

OUTPUT LOAD CURRENT (A)

DROPOUT VOLTAGE (mV)

25oC

-40oC

125oC

1.8 2.3 2.8 3.3 3.8 4.3 5.0

OUTPUT VOLTAGE (V)

GROUND PIN CURRENT (mA)_

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

www.ti.com

8.6 Typical Characteristics

Unless otherwise specified: TJ= 25°C, COUT = 10 µF, CIN = 10 µF, SD pin is tied to VIN, VOUT = 2.5 V, VIN = VOUT(NOM) + 1 V,

IOUT = 10 mA.

IOUT = 1.5 A

Figure 2. Ground Current vs Output Voltage

Figure 1. Dropout Voltage vs Output Load Current

Figure 4. ERROR Threshold vs Junction Temperature

Figure 3. SD IQvs Junction Temperature

Figure 5. DC Load Reg. vs Junction Temperature Figure 6. DC Line Regulation vs Temperature

Product Folder Links: LP3852 LP3855

VOUT

100mV/DIV

ILOAD

1A/DIV

TIME (50Ps/DIV)

MAGNITUDE

IOUT

@ 1A

IOUT

1A/DIV

VOUT

100 mV/DIV VOUT = 2.5V

TIME (2 Ps/DIV)

VOUT

100mV/DIV

ILOAD

1A/DIV

TIME (50Ps/DIV)

MAGNITUDE

VOUT

100mV/DIV

ILOAD

1A/DIV

TIME (50Ps/DIV)

MAGNITUDE

VIN (V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

VOUT (V)

125oC

25oC

-40oC

FREQUENCY (Hz)

0.000

0.500

1.000

1.500

2.000

2.500

3.000

100 1k 10k 100k

IL = 100mA

CIN = COUT = 10PF

NOISE (PV/ Hz

(

LP3852

LP3855

www.ti.com

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

Typical Characteristics (continued)

Unless otherwise specified: TJ= 25°C, COUT = 10 µF, CIN = 10 µF, SD pin is tied to VIN, VOUT = 2.5 V, VIN = VOUT(NOM) + 1 V,

IOUT = 10 mA.

Figure 8. Noise vs Frequency

Figure 7. VIN vs VOUT Over Temperature

CIN = COUT = 100 µF, OSCON CIN = COUT = 100 µF, POSCAP

Figure 9. Load Transient Response Figure 10. Load Transient Response

CIN = 2 X 10 µF Ceramic

CIN = COUT = 100 µF, Tantalum COUT = 2 X 10µF Ceramic

Figure 12. Load Transient Response

Figure 11. Load Transient Response

Product Folder Links: LP3852 LP3855

IOUT

@ 1A

VOUT

@ 2.5V

TIME (1 Ps/DIV)

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

www.ti.com

Typical Characteristics (continued)

Unless otherwise specified: TJ= 25°C, COUT = 10 µF, CIN = 10 µF, SD pin is tied to VIN, VOUT = 2.5 V, VIN = VOUT(NOM) + 1 V,

IOUT = 10 mA.

CIN = 2 X 10 µF Ceramic

COUT = 2 X 10µF Ceramic

Figure 13. Load Transient Response

Product Folder Links: LP3852 LP3855

LP3852

LP3855

www.ti.com

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

9 Detailed Description

9.1 Overview

The LP3852 and LP3855 series of fast ultra-low dropout linear regulators operate from a 2.5-V to 7-V input

supply. A wide range of preset output voltage options are available. These ultra-low dropout linear regulators

respond very quickly to step changes in load, which makes them suitable for low voltage microprocessor

applications. The LP3852 and LP3855 are developed on a CMOS process which allows low quiescent current

operation independent of output load current. This CMOS process also allows the LP3852 and LP3855 to

operate under extremely low dropout conditions.

9.2 Functional Block Diagrams

Figure 14. LP3852 Block Diagram

Figure 15. LP3855 Block Diagram

Product Folder Links: LP3852 LP3855

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

www.ti.com

9.3 Feature Description

9.3.1 SENSE Pin

In applications where the regulator output is not very close to the load, LP3855 can provide better remote load

regulation using the SENSE pin. Figure 16 depicts the advantage of the SENSE option. The LP3852 regulates

the voltage at the OUT pin. Hence, the voltage at the remote load will be the regulator output voltage minus the

drop across the trace resistance. For example, in the case of a 3.3-V output, if the trace resistance is 100 mΩ,

the voltage at the remote load will be 3.15 V with 1.5 A of load current, ILOAD. The LP3855 regulates the voltage

at the SENSE pin. Connecting the SENSE pin to the remote load will provide regulation at the remote load, as

shown in Figure 16. If the SENSE pin is not required, the SENSE pin must be connected to the OUT pin.

Figure 16. Improving Remote Load Regulation Using LP3855

9.3.2 SHUTDOWN (SD) Operation

A CMOS Logic low level signal at the SD pin will turn off the regulator. SD must be actively terminated through a

10-kΩpullup resistor for a proper operation. If this pin is driven from a source that actively pulls high and low

(such as a CMOS rail-to-rail comparator), the pullup resistor is not required. This pin must be tied to VIN if not

used.

The SD pin threshold has no voltage hysteresis. If the SD pin is actively driven, the voltage transition must rise

and fall cleanly and promptly.

9.3.3 Dropout Voltage

The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within

2% of the nominal output voltage. For CMOS LDOs, the dropout voltage is the product of the load current and

the Rds(on) of the internal MOSFET.

9.3.4 Reverse Current Path

The internal MOSFET in LP3852 and LP3855 has an inherent parasitic diode. During normal operation, the input

voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is

pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets

forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to

200-mA continuous and 1-A peak.

9.3.5 Short-Circuit Protection

The LP3852 and LP3855 are short-circuit protected and in the event of a peak overcurrent condition, the short-

circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts

down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the

thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to for power

dissipation calculations.

Product Folder Links: LP3852 LP3855

LP3852

LP3855

www.ti.com

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

Feature Description (continued)

9.3.6 ERROR Flag Operation

The LP3852 and LP3855 produce a logic low signal at the ERROR pin when the output drops out of regulation

due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing

diagram in Figure 17 shows the relationship between the ERROR flag and the output voltage. In this example,

the input voltage is changed to demonstrate the functionality of the ERROR Flag.

The internal ERROR comparator has an open drain output stage; thus, the ERROR pin should be pulled high

through a pullup resistor. Although the ERROR flag pin can sink current of 1 mA, this current is energy drain

from the input supply. Hence, the value of the pullup resistor should be in the range of 10 kΩto 1 MΩ.The

ERROR pin must be connected to ground if this function is not used. It should also be noted that when the

shutdown pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown

mode.

Figure 17. ERROR Operation

9.4 Device Functional Modes

9.4.1 Operation with VOUT(TARGET) + 0.1 V ≤VIN ≤7 V

The device operate if the input voltage is equal to, or exceeds VOUT(TARGET) + 0.1 V. At input voltages below the

minimum VIN requirement, the devices do not operate correctly and output voltage may not reach target value.

9.4.2 Operation With SD Pin Control

A CMOS Logic low level signal at the SD pin will turn off the regulator. The SD pin must be actively terminated

through a 10-kΩpullup resistor for a proper operation.

Product Folder Links: LP3852 LP3855

OUT

GND

LP3855-2.5 COUT*

10 PF

CIN*

INPUT VOUT

10 PF

SD** SENSE

2.5V, 1.5A

3.3V ± 10%

* TANTALUM OR CERAMIC

OUTIN

GND

LP3852-2.5 COUT*

10 PF

CIN*

INPUT VOUT

10 PF

ERROR**

SD** ERROR

2.5V, 1.5A

3.3V ± 10%

* TANTALUM OR CERAMIC

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

www.ti.com

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The LP3852 and LP3855 devices can provide 1.5-A output current with 2.5-V to 7-V input. A minimum 10-uF

output capacitor is required for loop stability. An input capacitor of at least 10 µF is required . Pin SD must be

tied to input if not used. For LP3852, ERROR pin should be pulled high through a pullup resistor. For LP3855, if

the sense option is not required , the SENSE pin must be connected to the OUT pin.

10.2 Typical Applications

Figure 18. LP3852 Typical Application

Figure 19. LP3855 Typical Application

10.2.1 Design Requirements

DESIGN PARAMETERS VALUE

Input voltage 3.3 V, ±10%

Output voltage 2.5 V, ±3%

Output current 1.5 A (maximum)

Input capacitor 10 µF (minimum)

Output capacitor 10 µF (minimum)

ERROR pullup resistor (LP3852 only) 10 kΩ

10.2.2 Detailed Design Procedure

10.2.2.1 External Capacitors

Like any low dropout regulator, external capacitors are required to assure stability. These capacitors must be

correctly selected for proper performance.

10.2.2.1.1 Input Capacitor

An input capacitor of at least 10 µF is required. Ceramic or tantalum may be used, and capacitance may be

increased without limit.

Product Folder Links: LP3852 LP3855

MAX. ALLOWABLE CERAMIC

OUTPUT CAPACITANCE (PF)

CERAMIC INPUT CAPACITANCE (PF)

100 1000

100

IL = 1.5A

COUT ESR (:)

LOAD CURRENT (A)

STABLE REGION

COUT > 10 PF

012

.001

.01

0.1

1.0

LP3852

LP3855

www.ti.com

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

10.2.2.1.2 Output Capacitor

An output capacitor is required for loop stability. It must be located less than 1 cm from the device and connected

directly to the output and ground pins using traces which have no other currents flowing through them (see

Layout Guidelines).

The minimum amount of output capacitance that can be used for stable operation is 10 µF. For general usage

across all load currents and operating conditions, the part was characterized using a 10-µF tantalum input

capacitor. The minimum and maximum stable equivalent series resistance (ESR) range for the output capacitor

was then measured which kept the device stable, assuming any output capacitor whose value is greater than 10

µF (see Figure 20).

Figure 20. ESR Curve For COUT (with 10-µF Tantalum Input Capacitor)

It should be noted that it is possible to operate the part with an output capacitor whose ESR is below these limits,

assuming that sufficient ceramic input capacitance is provided. This will allow stable operation using ceramic

output capacitors (see Operation with Ceramic Output Capacitors).

10.2.2.2 Operation with Ceramic Output Capacitors

LP385X voltage regulators can operate with ceramic output capacitors if the values of the input and output

capacitors are selected appropriately. The total ceramic output capacitance must be equal to or less than a

specified maximum value in order for the regulator to remain stable over all operating conditions. This maximum

amount of ceramic output capacitance is dependent upon the amount of ceramic input capacitance used as well

as the load current of the application. This relationship is shown in Figure 21, which graphs the maximum stable

value of ceramic output capacitance as a function of ceramic input capacitance for load currents of 1.5 A.

Figure 21. Maximum Ceramic Output Capacitance vs Ceramic Input Capacitance

If the maximum load current is 1.5 A and a 10-µF ceramic input capacitor is used, the regulator will be stable with

ceramic output capacitor values from 10 µF up to about 150 µF. When calculating the total ceramic output

capacitance present in an application, it is necessary to include any ceramic bypass capacitors connected to the

regulator output.

Product Folder Links: LP3852 LP3855

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

www.ti.com

10.2.2.3 Selecting A Capacitor

It is important to note that capacitance tolerance and variation with temperature must be taken into consideration

when selecting a capacitor so that the minimum required amount of capacitance is provided over the full

operating temperature range. In general, a good tantalum capacitor will show very little capacitance variation with

temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also

typically have large temperature variation of capacitance value.

Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics,

as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors.

Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so

severe they may not be feasible for some applications (see Capacitor Characteristics).

10.2.2.4 Capacitor Characteristics

10.2.2.4.1 Ceramic

For values of capacitance in the 10-µF to 100-µF range, ceramics are usually larger and more costly than

tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR

(typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a

function of voltage and temperature.

Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or

Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V

also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of

the temperature range.

X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically

maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of

course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.

10.2.2.4.2 Tantalum

Solid tantalum capacitors are typically recommended for use on the output because their ESR is very close to

the ideal value required for loop compensation.

Tantalum capacitors also have good temperature stability: a good quality tantalum capacitor will typically show a

capacitance value that varies less than 10-15% across the full temperature range of 125°C to −40°C. ESR will

vary only about 2X going from the high to low temperature limits.

The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if

the ESR of the capacitor is near the upper limit of the stability range at room temperature).

10.2.2.4.3 Aluminum

This capacitor type offers the most capacitance for the money. The disadvantages are that they are larger in

physical size, not widely available in surface mount, and have poor AC performance (especially at higher

frequencies) due to higher ESR and ESL.

Compared by size, the ESR of an aluminum electrolytic is higher than either tantalum or ceramic, and it also

varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X

when going from 25°C down to −40°C.

It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which

indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance

specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP385X. Derating must be

applied to the manufacturer's ESR specification, since it is typically only valid at room temperature.

Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating

temperature where ESR is maximum.

Product Folder Links: LP3852 LP3855

VOUT

100mV/DIV

ILOAD

1A/DIV

TIME (50Ps/DIV)

MAGNITUDE

VOUT

100mV/DIV

ILOAD

1A/DIV

TIME (50Ps/DIV)

MAGNITUDE

LP3852

LP3855

www.ti.com

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

10.2.2.5 Turnon Characteristics For Output Voltages Programmed to 2 V or Below

As VIN increases during start-up, the regulator output will track the input until VIN reaches the minimum operating

voltage (typically about 2.2 V). For output voltages programmed to 2 V or below, the regulator output may

momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2 V

are not affected by this behavior.

10.2.2.6 Output Noise

Noise is specified in two ways:

•Spot Noise or Output Noise Density is the RMS sum of all noise sources, measured at the regulator output, at

a specific frequency (measured with a 1-Hz bandwidth). This type of noise is usually plotted on a curve as a

function of frequency.

•Total Output Noise or Broad-Band Noise is the RMS sum of spot noise over a specified bandwidth, usually

several decades of frequencies.

Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz, and

total output noise is measured in µVRMS.

The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a

low frequency component and a high frequency component, which depend strongly on the silicon area and

quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the

current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a

smaller package. Increasing the current drawn by the internal reference increases the total supply current

(ground pin current). Using an optimized trade-off of ground pin current and die size, LP3852 and LP3855

achieve low noise performance and low quiescent-current operation.

The total output noise specification for LP3852 and LP3855 is presented in the Electrical Characteristics table.

The Output noise density at different frequencies is represented by a curve under Typical Characteristics.

10.2.3 Application Curves

CIN = COUT = 10 µF, OSCON CIN = COUT = 10 µF, Tantalum

Figure 22. Load Transient Response Figure 23. Load Transient Response

11 Power Supply Recommendations

The LP3852 and LP3855 devices are designed to operate from an input voltage supply range between 2.5 V and

7 V. The input voltage range provides adequate headroom in order for the device to have a regulated output.

This input supply must be well regulated. An input capacitor of at least 10 μF is required.

Product Folder Links: LP3852 LP3855

Ground

IN OUT

SENSE

Input

Capacitor Output

Capacitor

Pull-up

Resistor

Ground

IN OUT

SD ERROR

Input

Capacitor Output

Capacitor

Pull-up

Resistor Pull-up

Resistor

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

www.ti.com

12 Layout

12.1 Layout Guidelines

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.

The input and output capacitors must be directly connected to the IN, OUT, and ground pins of the regulator

using traces which do not have other currents flowing in them (Kelvin connect).

The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and ground

pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its

capacitors have a "single point ground".

It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane

were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground

potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground

technique for the regulator and its capacitors fixed the problem.

Since high current flows through the traces going into IN and coming from OUT, Kelvin connect the capacitor

leads to these pins so there is no voltage drop in series with the input and output capacitors.

12.2 Layout Example

Figure 24. LP3852 TO-263 Package Typical Layout

Figure 25. LP3855 TO-263 Package Typical Layout

Product Folder Links: LP3852 LP3855

LP3852

LP3855

www.ti.com

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

12.3 RFI and/or EMI Susceptibility

Radio frequency interference (RFI) and electromagnetic interference (EMI) can degrade any integrated circuit

performance because of the small dimensions of the geometries inside the device. In applications where circuit

sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must

be taken to ensure that this does not affect the device regulator.

If RFI and/or EMI noise is present on the input side of the regulator (such as applications where the input source

comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the IN pin of

the device.

If a load is connected to the device output which switches at high speed (such as a clock), the high-frequency

current pulses required by the load must be supplied by the capacitors on the device output. Since the bandwidth

of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that

frequency. This means the effective output impedance of the device at frequencies above 100 kHz is determined

only by the output capacitor or capacitors.

In applications where the load is switching at high speed, the output of the IC may need RF isolation from the

load. It is recommended that some inductance be placed between the output capacitor and the load, and good

RF bypass capacitors be placed directly across the load.

PCB layout is also critical in high noise environments, since RFI and/or EMI is easily radiated directly into PC

traces. Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate

path. At MHz frequencies, ground planes begin to look inductive and RFI and/or EMI can cause ground bounce

across the ground plane.

In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not

radiate directly into adjacent layers which carry analog power and ground.

12.4 Power Dissipation/Heatsinking

The LP3852 and LP3855 can deliver a continuous current of 1.5 A over the full operating temperature range. A

heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of

the application. Under all possible conditions, the junction temperature must be within the range specified under

operating conditions. The total power dissipation of the device is given by:

PD= (VIN −VOUT)IOUT+ (VIN)IGND

where

• IGND is the operating ground current of the device (specified under Electrical Characteristics). (1)

The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the

application, and the maximum allowable junction temperature (TJmax):

TRmax = TJmax −TAmax (2)

The maximum allowable value for junction to ambient thermal resistance, RθJA, can be calculated using the

formula:

RθJA = TRmax / PD(3)

The LP3852 and LP3855 are available in TO-220 and TO-263 packages. The thermal resistance depends on

amount of copper area or heat sink, and on air flow. If the maximum allowable value of RθJA calculated in

Equation 3 is ≥60 °C/W for TO-220 package and ≥60°C/W for TO-263 package, no heatsink is needed since

the package can dissipate enough heat to satisfy these requirements. If the value for allowable RθJA falls below

these limits, a heat sink is required.

12.4.1 Heatsinking TO-220 Package

The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on

a PC board. If a copper plane is to be used, the values of RθJA will be same as shown in next section for TO-263

package.

The heatsink to be used in the application should have a heatsink to ambient thermal resistance,

RθHA≤RθJA −RθCH −RθJC.

Product Folder Links: LP3852 LP3855

LP3852

LP3855

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

www.ti.com

Power Dissipation/Heatsinking (continued)

In this equation, RθCH is the thermal resistance from the case to the surface of the heat sink, and RθJC is the

thermal resistance from the junction to the surface of the case. RθJC is about 3°C/W for a TO-220 package. The

value for RθCH depends on method of attachment, insulator, etc. RθCH varies between 1.5°C/W to 2.5°C/W. If the

exact value is unknown, 2°C/W can be assumed.

12.4.2 Heatsinking TO-263 Package

The TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are soldered

to the copper plane for heat sinking. Figure 26 shows a curve for the RθJA of TO-263 package for different copper

area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking.

Figure 26. RθJA vs Copper (1 Ounce) Area for TO-263 package

As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The

minimum value for RθJA for the TO-263 package mounted to a PCB is 32°C/W.

Figure 27 shows the maximum allowable power dissipation for TO-263 packages for different ambient

temperatures, assuming RθJA is 35°C/W and the maximum junction temperature is 125°C.

Figure 27. Maximum Power Dissipation vs Ambient Temperature for TO-263 Package

Product Folder Links: LP3852 LP3855

LP3852

LP3855

www.ti.com

SNVS174I –FEBRUARY 2003–REVISED FEBRUARY 2015

13 Device and Documentation Support

13.1 Related Links

Table 1 lists quick access links. Categories include technical documents, support and community resources,

tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

LP3852 Click here Click here Click here Click here Click here

LP3855 Click here Click here Click here Click here Click here

13.2 Trademarks

All trademarks are the property of their respective owners.

13.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: LP3852 LP3855

PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3852EMP-1.8 NRND SOT-223 NDC 5 1000 TBD Call TI Call TI -40 to 125 LHTB

LP3852EMP-1.8/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHTB

LP3852EMP-2.5 NRND SOT-223 NDC 5 1000 TBD Call TI Call TI -40 to 125 LHUB

LP3852EMP-2.5/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHUB

LP3852EMP-3.3 NRND SOT-223 NDC 5 1000 TBD Call TI Call TI -40 to 125 LHVB

LP3852EMP-3.3/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHVB

LP3852EMP-5.0/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHXB

LP3852EMPX-1.8/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHTB

LP3852ES-1.8/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3852ES

-1.8

LP3852ES-2.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3852ES

-2.5

LP3852ES-3.3 NRND DDPAK/

TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3852ES

-3.3

LP3852ES-3.3/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3852ES

-3.3

LP3852ES-5.0/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3852ES

-5.0

LP3852ESX-1.8/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3852ES

-1.8

LP3852ESX-2.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3852ES

-2.5

LP3852ESX-3.3/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3852ES

-3.3

LP3852ESX-5.0/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3852ES

-5.0

LP3852ET-1.8/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3852ET

-1.8

PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2017

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3852ET-2.5/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3852ET

-2.5

LP3852ET-3.3/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3852ET

-3.3

LP3852ET-5.0/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3852ET

-5.0

LP3855EMP-1.8/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHYB

LP3855EMP-2.5/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LHZB

LP3855EMP-3.3/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LJ1B

LP3855EMP-5.0/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LJ2B

LP3855EMPX-5.0/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LJ2B

LP3855ES-1.8/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3855ES

-1.8

LP3855ES-2.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3855ES

-2.5

LP3855ES-3.3/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3855ES

-3.3

LP3855ES-5.0/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3855ES

-5.0

LP3855ESX-1.8/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3855ES

-1.8

LP3855ESX-2.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3855ES

-2.5

LP3855ESX-3.3/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3855ES

-3.3

LP3855ESX-5.0/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3855ES

-5.0

LP3855ET-1.8/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3855ET

-1.8

LP3855ET-3.3/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3855ET

-3.3

PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2017

Addendum-Page 3

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP3855ET-5.0/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP3855ET

-5.0

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP3852EMP-1.8 SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3852EMP-1.8/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3852EMP-2.5 SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3852EMP-2.5/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3852EMP-3.3 SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3852EMP-3.3/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3852EMP-5.0/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3852EMPX-1.8/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3852ESX-1.8/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3852ESX-2.5/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3852ESX-3.3/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3852ESX-5.0/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3855EMP-1.8/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3855EMP-2.5/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3855EMP-3.3/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 1

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP3855EMP-5.0/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3855EMPX-5.0/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3

LP3855ESX-1.8/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3855ESX-2.5/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3855ESX-3.3/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP3855ESX-5.0/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP3852EMP-1.8 SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3852EMP-1.8/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3852EMP-2.5 SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3852EMP-2.5/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3852EMP-3.3 SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3852EMP-3.3/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3852EMP-5.0/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3852EMPX-1.8/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 2

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP3852ESX-1.8/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3852ESX-2.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3852ESX-3.3/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3852ESX-5.0/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3855EMP-1.8/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3855EMP-2.5/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3855EMP-3.3/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3855EMP-5.0/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0

LP3855EMPX-5.0/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0

LP3855ESX-1.8/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3855ESX-2.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3855ESX-3.3/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP3855ESX-5.0/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 3

MECHANICAL DATA

NDC0005A

www.ti.com

MECHANICAL DATA

NDH0005D

www.ti.com

MECHANICAL DATA

KTT0005B

www.ti.com

BOTTOM SIDE OF PACKAGE

TS5B (Rev D)

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its

semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers

should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated

circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and

services.

Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is

accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced

documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements

different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the

associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers

remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have

full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products

used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with

respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous

consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and

take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will

thoroughly test such applications and the functionality of such TI products as used in such applications.

TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,

including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to

assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any

way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource

solely for this purpose and subject to the terms of this Notice.

TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI

products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,

enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically

described in the published documentation for a particular TI Resource.

Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that

include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE

TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY

RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or

endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR

REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO

ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL

PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,

INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF

PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,

DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN

CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949

and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.

Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such

products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards

and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must

ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in

life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.

Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life

support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all

medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.

TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).

Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications

and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory

requirements in connection with such selection.

Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-

compliance with the terms and provisions of this Notice.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

LP3855EMP-1.8 LP3855EMP-1.8/NOPB LP3855EMP-2.5 LP3855EMP-2.5/NOPB LP3855EMP-3.3 LP3855EMP-

3.3/NOPB LP3855EMP-5.0 LP3855EMP-5.0/NOPB LP3855EMPX-1.8 LP3855EMPX-1.8/NOPB LP3855EMPX-2.5

LP3855EMPX-2.5/NOPB LP3855EMPX-3.3 LP3855EMPX-3.3/NOPB LP3855EMPX-5.0 LP3855EMPX-5.0/NOPB

LP3855EMPX-ADJ LP3855ES-1.8 LP3855ES-1.8/NOPB LP3855ES-2.5 LP3855ES-2.5/NOPB LP3855ES-3.3

LP3855ES-3.3/NOPB LP3855ES-5.0 LP3855ES-5.0/NOPB LP3855ES-ADJ LP3855ESX-1.8 LP3855ESX-1.8/NOPB

LP3855ESX-2.5 LP3855ESX-2.5/NOPB LP3855ESX-3.3 LP3855ESX-3.3/NOPB LP3855ESX-5.0 LP3855ESX-

5.0/NOPB LP3855ESX-ADJ LP3855ET-1.8 LP3855ET-1.8/NOPB LP3855ET-2.5 LP3855ET-2.5/NOPB LP3855ET-

3.3 LP3855ET-3.3/NOPB LP3855ET-5.0 LP3855ET-5.0/NOPB