AD8131ARMZ-REEL7 - Analog Devices

Low Cost, High Speed

Differential Driver

AD8131

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

High speed

400 MHz, −3 dB full power bandwidth

2000 V/μs slew rate

Fixed gain of 2 with no external components

Internal common-mode feedback to improve gain and phase

balance: −60 dB @ 10 MHz

Separate input to set the common-mode output voltage

Low distortion: 68 dB SFDR @ 5 MHz 200 Ω load

Power supply range +2.7 V to ±5 V

APPLICATIONS

Video line driver

Digital line driver

Low power differential ADC driver

Differential in/out level shifting

Single-ended input to differential output driver

FUNCTIONAL BLOCK DIAGRAM

NC = NO CONNECT

AD8131

750Ω750Ω

1.5kΩ1.5kΩ

–D

OCM

V+

+OUT

V–

–OUT

01072-001

Figure 1.

GENERAL DESCRIPTION

The AD8131 is a differential or single-ended input to

differential output driver requiring no external components for

a fixed gain of 2. The AD8131 is a major advancement over op

amps for driving signals over long lines or for driving

differential input ADCs. The AD8131 has a unique internal

feedback feature that provides output gain and phase matching

that are balanced to −60 dB at 10 MHz, reducing radiated EMI

and suppressing harmonics. Manufactured on the Analog

Devices, Inc. next generation XFCB bipolar process, the

AD8131 has a −3 dB bandwidth of 400 MHz and delivers a

differential signal with very low harmonic distortion.

The AD8131 is a differential driver for the transmission of

high-speed signals over low-cost twisted pair or coax cables.

The AD8131 can be used for either analog or digital video

signals or for other high-speed data transmission. The AD8131

driver is capable of driving either Cat3 or Cat5 twisted pair or

coax with minimal line attenuation. The AD8131 has

considerable cost and performance improvements over discrete

line driver solutions.

The AD8131 can replace transformers in a variety of applications,

preserving low frequency and dc information. The AD8131 does

not have the susceptibility to magnetic interference and hysteresis

of transformers. It is smaller, easier to work with, and has the high

reliability associated with ICs.

–

–30

–40

–50

–60

–70

–80 1 10 100 1000

BALANCE ERROR (dB)

FREQUENCY (MHz)

ΔVOUT, dm = 2V p-p

ΔVOUT, cm/ΔVOUT, dm

VS = +5V

VS = ±5V

01072-002

Figure 2. Output Balance Error vs. Frequency

The AD8131’s differential output also helps balance the input

for differential ADCs, optimizing the distortion performance of

the ADCs. The common-mode level of the differential output is

adjustable by a voltage on the VOCM pin, easily level-shifting the

input signals for driving single-supply ADCs with dual supply

signals. Fast overload recovery preserves sampling accuracy.

The AD8131 is available in both SOIC and MSOP packages for

operation over −40°C to +125°C.

AD8131

Rev. B | Page 2 of 20

TABLE OF CONTENTS

Specifications..................................................................................... 3

±DIN to ±OUT Specifications...................................................... 3

VOCM to ±OUT Specifications..................................................... 4

±DIN to ±OUT Specifications...................................................... 5

VOCM to ±OUT Specifications..................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Operational Description................................................................ 15

Theory of Operation ...................................................................... 16

Analyzing an Application Circuit............................................. 16

Closed-Loop Gain...................................................................... 16

Estimating the Output Noise Voltage...................................... 16

Calculating the Input Impedance of an

Application Circuit..................................................................... 16

Input Common-Mode Voltage Range in

Single-Supply Applications ....................................................... 17

Setting the Output Common-Mode Voltage.......................... 17

Driving a Capacitive Load......................................................... 17

Applications..................................................................................... 18

Twisted-Pair Line Driver........................................................... 18

3 V Supply Differential A-to-D Driver.................................... 18

Unity-Gain, Single-Ended-to-Differential Driver ................. 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

6/05—Rev. A to Rev. B

Updated Format..................................................................Universal

Changed Upper Operating Limit .....................................Universal

Changes to Ordering Guide .......................................................... 20

AD8131

Rev. B | Page 3 of 20

SPECIFICATIONS

±DIN TO ±OUT SPECIFICATIONS

25°C, VS = ±5 V, VOCM = 0 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label

descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Large Signal Bandwidth VOUT = 2 V p-p 400 MHz

−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 320 MHz

Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 85 MHz

Slew Rate VOUT = 2 V p-p, 10% to 90% 2000 V/μs

Settling Time 0.1%, VOUT = 2 V p-p 14 ns

Overdrive Recovery Time VIN = 5 V to 0 V Step 5 ns

NOISE/HARMONIC PERFORMANCE

Second Harmonic VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω −68 dBc

OUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω −63 dBc

OUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −95 dBc

OUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −79 dBc

Third Harmonic VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω −94 dBc

OUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω −70 dBc

OUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −101 dBc

OUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −77 dBc

IMD 20 MHz, RL, dm = 800 Ω −54 dBc

IP3 20 MHz, RL, dm = 800 Ω 30 dBm

Voltage Noise (RTO) f = 20 MHz 25 nV/√Hz

Differential Gain Error NTSC, RL, dm = 150 Ω 0.01 %

Differential Phase Error NTSC, RL, dm = 150 Ω 0.06 degrees

INPUT CHARACTERISTICS

Input Resistance Single-ended input 1.125 kΩ

Differential input 1.5 kΩ

Input Capacitance 1 pF

Input Common-Mode Voltage −7.0 to +5.0 V

CMRR ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±0.5 V −70 dB

OUTPUT CHARACTERISTICS

Offset Voltage (RTO) VOS, dm = VOUT, dm; VDIN+ = VDIN− = VOCM = 0 V ±2 ±7 mV

MIN to TMAX variation ±8 μV/°C

OCM = float ±4 mV

MIN to TMAX variation ±10 μV/°C

Output Voltage Swing Maximum ΔVOUT; single-ended output −3.6 to +3.6 V

Linear Output Current 60 mA

Gain ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = ±0.5 V 1.97 2 2.03 V/V

Output Balance Error ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V −70 dB

AD8131

Rev. B | Page 4 of 20

VOCM TO ±OUT SPECIFICATIONS

25°C, VS = ±5 V, VOCM = 0 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label

descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth ΔVOCM = 600 mV 210 MHz

Slew Rate VOCM = −1 V to +1 V 500 V/μs

DC PERFORMANCE

Input Voltage Range ±3.6 V

Input Resistance 120 kΩ

Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 0 V ±1.5 ±7 mV

OCM = float ±2.5 mV

Input Bias Current 0.5 μA

VOCM CMRR ΔVOUT, dm/ΔVOCM; ΔVOCM = ±0.5 V −60 dB

Gain ΔVOUT, cm/ΔVOCM; ΔVOCM = ±1 V 0.988 1 1.012 V/V

POWER SUPPLY

Operating Range ±1.4 ± 5.5 V

Quiescent Current VDIN+ = VDIN− = VOCM = 0 V 10.5 11.5 12.5 mA

MIN to TMAX variation 25 μA/°C

Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = ±1 V −70 −56 dB

OPERATING TEMPERATURE RANGE −40 +125 °C

AD8131

Rev. B | Page 5 of 20

±DIN TO ±OUT SPECIFICATIONS

25°C, VS = 5 V, VOCM = 2.5 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label

descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Large Signal Bandwidth VOUT = 2 V p-p 385 MHz

−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 285 MHz

Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 65 MHz

Slew Rate VOUT = 2 V p-p, 10% to 90% 1600 V/μs

Settling Time 0.1%, VOUT = 2 V p-p 18 ns

Overdrive Recovery Time VIN = 5 V to 0 V Step 5 ns

NOISE/HARMONIC PERFORMANCE

Second Harmonic VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω −67 dBc

VOUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω −56 dBc

VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −94 dBc

VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −77 dBc

Third Harmonic VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω −74 dBc

VOUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω −67 dBc

VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −95 dBc

VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −74 dBc

IMD 20 MHz, RL, dm = 800 Ω −51 dBc

IP3 20 MHz, RL, dm = 800 Ω 29 dBm

Voltage Noise (RTO) f = 20 MHz 25 nV/√Hz

Differential Gain Error NTSC, RL, dm = 150 Ω 0.02 %

Differential Phase Error NTSC, RL, dm = 150 Ω 0.08 degrees

INPUT CHARACTERISTICS

Input Resistance Single-ended input 1.125 kΩ

Differential input 1.5 kΩ

Input Capacitance

1 pF

Input Common-Mode Voltage

−1.0 to +4.0 V

CMRR ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±0.5 V −70 dB

OUTPUT CHARACTERISTICS

Offset Voltage (RTO) VOS, dm = VOUT, dm; VDIN+ = VDIN− = VOCM = 2.5 V ±3 ±7 mV

TMIN to TMAX variation ±8 μV/°C

VOCM = float ±4 mV

TMIN to TMAX variation ±10 μV/°C

Output Voltage Swing Maximum ΔVOUT; single-ended output 1.0 to 3.7 V

Linear Output Current

45 mA

Gain ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = ±0.5 V 1.96 2 2.04 V/V

Output Balance Error ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V −62 dB

AD8131

Rev. B | Page 6 of 20

VOCM TO ±OUT SPECIFICATIONS

25°C, VS = 5 V, VOCM = 2.5 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label

descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.

Table 4.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth ΔVOCM = 600 mV 200 MHz

Slew Rate VOCM = 1.5 V to 3.5 V 450 V/μs

DC PERFORMANCE

Input Voltage Range

1.0 to 3.7 V

Input Resistance

30 kΩ

Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 2.5 V ±5 ±12 mV

VOCM = float ±10 mV

Input Bias Current

0.5 μA

VOCM CMRR ΔVOUT, dm/ΔVOCM; ΔVOCM = 2.5 V ±0.5 V −60 dB

Gain ΔVOUT, cm/ΔVOCM; ΔVOCM = 2.5 V ±1 V 0.985 1 1.015 V/V

POWER SUPPLY

Operating Range 2.7 11 V

Quiescent Current VDIN+ = VDIN− = VOCM = 2.5 V 9.25 10.25 11.25 mA

TMIN to TMAX variation 20 μA/°C

Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = ±0.5 V −70 −56 dB

OPERATING TEMPERATURE RANGE −40 +125 °C

AD8131

Rev. B | Page 7 of 20

ABSOLUTE MAXIMUM RATINGS

Table 5.1

Parameter Rating

Supply Voltage ±5.5 V

VOCM ±VS

Internal Power Dissipation 250 mW

Operating Temperature Range −40°C to +125°C

Storage Temperature Range −65°C to +150°C

Lead Temperature (Soldering 10 sec) 300°C

1 Thermal resistance measured on SEMI standard 4-layer board.

8-lead SOIC: θJA = 121°C/W.

8-lead MSOP: θJA = 142°C/W.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only, functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

AMBIENT TEMPERATURE (°C)

–50

= 150°C

2.0

1.5

1.0

MAXIMUM POWER DISSIPATION (W)

8-LEAD SOIC

PACKAGE

–20 10 100 130

8-LEAD

MSOP

PACKAGE

0.5

40 70

01072-044

Figure 3. Plot of Maximum Power Dissipation vs. Temperature

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD8131

Rev. B | Page 8 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC = NO CONNECT

AD8131

750Ω750Ω

1.5kΩ1.5kΩ

–DIN

VOCM

V+

+OUT

+DIN

V–

–OUT

01072-003

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 −DIN Negative Input.

2 VOCM Common-Mode Output Voltage. Voltage applied to this pin sets the common-mode output voltage with a ratio of

1:1. For example, 1 V dc on VOCM will set the dc bias level on +OUT and −OUT to 1 V.

3 V+ Positive Supply Voltage.

4 +OUT Positive Output. Note: the voltage at −DIN is inverted at +OUT.

5 −OUT Negative Output. Note: the voltage at +DIN is inverted at −OUT.

6 V− Negative Supply Voltage.

7 NC No Connect.

8 +DIN Positive Input.

AD8131

Rev. B | Page 9 of 20

TYPICAL PERFORMANCE CHARACTERISTICS

AD8131

L, dm

= 200Ω

24.9Ω

49.9Ω

1500Ω

750Ω

01072-004

Figure 5. Basic Test Circuit

–3

GAIN (dB)

1 10 100 1000

FREQUENCY (MHz)

VOUT = 200mV p-p

VS = ±5V

MSOP

SOIC

01072-005

Figure 6. Small Signal Frequency Response

–3

GAIN (dB)

1 10 100 1000

FREQUENCY (MHz)

OUT

= 200mV p-p

= +5V

= ±5V

01072-006

Figure 7. Small Signal Frequency Response

–3

GAIN (dB)

1 10 100 1000

FREQUENCY (MHz)

OUT

= 2V p-p

= ±5V

MSOP

SOIC

01072-007

Figure 8. Large Signal Frequency Response

–3

GAIN (dB)

1 10 100 1000

FREQUENCY (MHz)

OUT

= 2V p-p

= +5V

= ±5V

01072-008

Figure 9. Large Signal Frequency Response

AD8131

24.9Ω

49.9Ω

1500Ω

750Ω

LPF 300Ω

300Ω

HPF

= 50Ω

2:1 TRANSFORMER

01072-009

Figure 10. Harmonic Distortion Test Circuit (RL, dm = 800 Ω)

AD8131

Rev. B | Page 10 of 20

–

–60

–70

–80

–90

–100

–110

DISTORT ION (dBc)

40 50 60 70

FRE QUENCY ( MHz )

0102030

L, dm

= 800 Ω

OUT, dm

= 1V p-p

HD3 (V

= 3V)

HD3 (V

= 5V)

HD2 ( V

= 3V)

HD2 (V

= 5V)

01072-010

Figure 11. Harmonic Distortion vs. Frequency

40 50 60 70

FREQUENCY (MHz)

0102030

–40

–50

–60

–70

–80

–100

–110

DISTORTION (dBc)

–90

RL, dm = 800Ω

VOUT, dm = 2V p-p HD3 (VS = ±5V)

HD3 (VS = +5V)

HD2 (VS = ±5V)

HD2 (VS = +5V)

01072-011

Figure 12. Harmonic Distortion vs. Frequency

–55

–65

–75

–85

–95

–105

–115 3456

DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

012

DISTORTION (dBc)

= ±5V

L, dm

= 800ΩHD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz) HD3 (F = 5MHz)

01072-012

Figure 13. Harmonic Distortion vs. Differential Output Voltage

–

–60

–70

–80

–90

–100

–110

DISTORTION (dBc)

2.5 3.0 3.5 4.0

DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

1.0 1.5 2.00.50

= 5V

L, dm

= 800Ω

HD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

01072-013

Figure 14. Harmonic Distortion vs. Differential Output Voltage

–50

–60

–70

–80

–90

–100

–110

DISTORTION (dBc)

1.25 1.5 1.75

DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

0.75 1.00.500.25

= 3V

L, dm

= 800Ω

HD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

01072-014

Figure 15. Harmonic Distortion vs. Differential Output Voltage

–50

–60

–70

–80

–90

–100

–110

DISTORTION (dBc)

700 800 900 1000

LOAD

(Ω)

400 500 600300200

= ±5V

OUT, dm

= 2V p-p

HD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

01072-015

Figure 16. Harmonic Distortion vs. RLOAD

AD8131

Rev. B | Page 11 of 20

–

–60

–70

–80

–90

–100

–110

DISTORTION (dBc)

700 800 900 1000

LOAD

(Ω)

400 500 600300200

= 5V

OUT, dm

= 2V p-p

HD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

01072-016

Figure 17. Harmonic Distortion vs. RLOAD

–50

–60

–70

–80

–90

–100

–110

DISTORTION (dBc)

700 800 900 1000

LOAD

(Ω)

400 500 600300200

= 3V

OUT, dm

= 1V p-p HD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz) HD3 (F = 5MHz)

01072-017

Figure 18. Harmonic Distortion vs. RLOAD

–10

–20

–30

–40

49.5 50.0 50.5

OUT

(dBm)

FREQUENCY (MHz)

–50

–60

–70

–80

–90

–100

–110

= 500MHz

= ±5V

L, dm

= 800Ω

01072-018

Figure 19. Intermodulation Distortion

INTERCEPT (dBm)

50 60 70 80

FREQUENCY (MHz)

20 30 40100

= +5V

= ±5V

L, dm

= 800Ω

01072-019

Figure 20. Third Order Intercept vs. Frequency

5ns

OUT, dm

= ±5V

OUT+

OUT–

+DIN

01072-020

Figure 21. Large Signal Transient Response

5ns

40mV

= +5V

= ±5V

01072-021

Figure 22. Small Signal Transient Response

AD8131

Rev. B | Page 12 of 20

5ns

400mV

= +5V

= ±5V

OUT

= 2V p-p

01072-022

Figure 23. Large Signal Transient Response

5ns300mV

OUT

= 1.5V p-p

= 3V

01072-023

Figure 24. Large Signal Transient Response

4ns

= ±5V

2mV/DIV

1V/DIV

OUT, dm

+DIN

01072-024

Figure 25. 0.1% Settling Time

AD8131

24.9Ω

49.9Ω

1500Ω

750Ω

24.9Ω

24.9ΩC

150Ω

01072-025

Figure 26. Capacitor Load Drive Test Circuit

1.25ns

400mV

= ±5V

= 20pF

= 5pF

= 0pF

01072-026

Figure 27. Large Signal Transient Response for Various Capacitor Loads

–10

–20

–30

–40

1 100 1000

PSRR (dB)

FREQUENCY (MHz)

–50

–60

–70

–80 10

ΔV

OUT, dm

ΔV

+PSRR

= ±5V, +5V)

–PSRR

= ±5V)

01072-027

Figure 28. PSRR vs. Frequency

AD8131

Rev. B | Page 13 of 20

AD8131

24.9Ω

1500Ω

750Ω

100Ω

OUT, dm

OUT, cm

01072-028

Figure 29. CMRR Test Circuit

–20

–30

–40

–50

–60

–70

–80 1 10 100 1000

CMRR (dB)

FREQUENCY (MHz)

= ±5V

IN, cm

= 1V p-p

ΔV

OUT, dm

/ΔV

IN, cm

ΔV

OUT, cm

/ΔV

IN, cm

01072-029

Figure 30. CMRR vs. Frequency

100

0.11 10 100

IMPEDANCE (Ω)

FREQUENCY (MHz)

SINGLE-ENDED OUTPUT

= +5V

= ±5V

01072-030

Figure 31. Single-Ended ZOUT vs. Frequency

AD8131

1500Ω

750Ω

100Ω

24.9Ω

49.9Ω

01072-031

Figure 32. Output Balance Error Test Circuit

–20

–30

–40

–50

–60

–70

–80 1 10 100 1000

BALANCE ERROR (dB)

FREQUENCY (MHz)

ΔV

OUT, dm

= 2V p-p

ΔV

OUT, cm

/ΔV

OUT, dm

= +5V

= ±5V

01072-032

Figure 33. Output Balance Error vs. Frequency

SUPPLY CURRENT (mA)

–50 –20 10 40

TEMPERATURE (°C)

70 100 130

01072-034

= ±5V

= +5V

Figure 34. Quiescent Current vs. Temperature

AD8131

Rev. B | Page 14 of 20

–20

–30

–40

–50

–60

–70

–80

1 10 100 1000

CMRR (dB)

FREQUENCY (MHz)

–90

ΔV

OUT, cm

ΔV

OCM

= ±5V

ΔV

OCM

= 600mV p-p

ΔV

OCM

= 2V p-p

01072-037

110

NOISE (nV/

√

Hz)

0.1k 1k 10k 100k

FREQUENCY (Hz)1M 10M 100M

= ±5V

01072-035

Figure 37. VOCM CMRR vs. Frequency

Figure 35. Voltage Noise vs. Frequency

–3

–6

–9 1 10 100 1000

GAIN (dB)

FREQUENCY (MHz)

ΔV

OUT, cm

ΔV

OCM

= ±5V

ΔV

OCM

= 600mV p-p

ΔV

OCM

= 2V p-p

01072-036

400mV 5ns

= 5V

OCM

= –1V TO +1V V

OUT, cm

01072-038

Figure 38. VOCM Transient Response

Figure 36. VOCM Gain Response

AD8131

Rev. B | Page 15 of 20

OPERATIONAL DESCRIPTION

AD8131

L, dm

OUT, dm

–OUT

+OUT

–OUT

+OUT

+IN

–IN

–D

OCM

01072-039

Figure 39. Circuit Definitions

Differential voltage refers to the difference between two node

voltages. For example, the output differential voltage (or

equivalently output differential-mode voltage) shown in

Figure 39 is defined as

(

)

OUTOUT

dmOUT VVV −+ −=

V+OUT and V–OUT refer to the voltages at the +OUT and −OUT

terminals with respect to a common reference.

Common-mode voltage refers to the average of two node

voltages. The output common-mode voltage is defined as

(

)

,OUTOUTcmOUT VVV −+

Balance is a measure of how well differential signals are

matched in amplitude and exactly 180 degrees apart in phase.

Balance is most easily determined by placing a well-matched

resistor divider between the differential voltage nodes and

comparing the magnitude of the signal at the divider’s midpoint

with the magnitude of the differential signal. By this definition,

output balance is the magnitude of the output common-mode

voltage divided by the magnitude of the output differential-

mode voltage.

dmOUT

cmOUT

ErrorBalanceOutput

AD8131

Rev. B | Page 16 of 20

THEORY OF OPERATION

The AD8131 differs from conventional op amps in that it has

two outputs whose voltages move in opposite directions. Like

an op amp, it relies on high open-loop gain and negative

feedback to force these outputs to the desired voltages. The

AD8131 behaves much like a standard voltage feedback op amp

and makes it easy to perform single-ended-to-differential

conversion, common-mode level-shifting, and amplification of

differential signals.

Previous discrete and integrated differential driver designs used

two independent amplifiers and two independent feedback

loops, one to control each of the outputs. When these circuits

are driven from a single-ended source, the resulting outputs are

typically not well balanced. Achieving a balanced output

typically required exceptional matching of the amplifiers and

feedback networks.

DC common-mode level shifting has also been difficult with

previous differential drivers. Level shifting required the use of a

third amplifier and feedback loop to control the output

common-mode level. Sometimes the third amplifier has also

been used to attempt to correct an inherently unbalanced

circuit. Excellent performance over a wide frequency range has

proven difficult with this approach.

The AD8131 uses two feedback loops to separately control the

differential and common-mode output voltages. The differential

feedback, set by internal resistors, controls only the differential

output voltage. The common-mode feedback controls only the

common-mode output voltage. This architecture makes it easy

to arbitrarily set the common-mode output level. It is forced, by

internal common-mode feedback, to be equal to the voltage

applied to the VOCM input, without affecting the differential

output voltage.

The AD8131 architecture results in outputs that are very highly

balanced over a wide frequency range without requiring

external components or adjustments. The common-mode

feedback loop forces the signal component of the output

common-mode voltage to be zeroed. The result is nearly

perfectly balanced differential outputs, of identical amplitude

and exactly 180 degrees apart in phase.

ANALYZING AN APPLICATION CIRCUIT

The AD8131 uses high open-loop gain and negative feedback to

force its differential and common-mode output voltages in such

a way as to minimize the differential and common-mode error

voltages. The differential error voltage is defined as the voltage

between the differential inputs labeled +IN and −IN in

Figure 39. For most purposes, this voltage can be assumed to be

zero. Similarly, the difference between the actual output

common-mode voltage and the voltage applied to VOCM can also

be assumed to be zero. Starting from these two assumptions,

any application circuit can be analyzed.

CLOSED-LOOP GAIN

The differential mode gain of the circuit in Figure 39 can be

described by the following equation:

2==

dmIN,

dmOUT,

where RF = 1.5 kΩ and RG = 750 Ω nominally.

ESTIMATING THE OUTPUT NOISE VOLTAGE

Similar to the case of a conventional op amp, the differential

output errors (noise and offset voltages) can be estimated by

multiplying the input referred terms, at +IN and −IN, by the

circuit noise gain. The noise gain is defined as

31 =

⎟

⎠

⎞

⎜

⎝

⎛

The total output referred noise for the AD8131, including the

contributions of RF, RG, and op amp, is nominally 25 nV/√Hz

at 20 MHz.

CALCULATING THE INPUT IMPEDANCE OF AN

APPLICATION CIRCUIT

The effective input impedance of a circuit such as that in

Figure 39, at +DIN and −DIN, will depend on whether the

amplifier is being driven by a single-ended or differential signal

source. For balanced differential input signals, the input

impedance (RIN, dm) between the inputs (+DIN and −DIN) is

k5.12

dmIN RR

In the case of a single-ended input signal (for example if −DIN is

grounded and the input signal is applied to +DIN), the input

impedance becomes

()

Ω=

⎟

⎠

⎞

⎜

⎝

⎛

+×

−

=k 125.1

dmIN

The input impedance is effectively higher than it would be for a

conventional op amp connected as an inverter because a

fraction of the differential output voltage appears at the inputs

as a common-mode signal, partially bootstrapping the voltage

across the input resistor RG.

AD8131

Rev. B | Page 17 of 20

INPUT COMMON-MODE VOLTAGE RANGE IN

SINGLE-SUPPLY APPLICATIONS

The AD8131 is optimized for level-shifting ground referenced

input signals. For a single-ended input this would imply, for

example, that the voltage at −DIN in Figure 39 would be zero

volts when the amplifier’s negative power supply voltage (at V−)

was also set to zero volts.

SETTING THE OUTPUT COMMON-MODE VOLTAGE

The AD8131’s VOCM pin is internally biased at a voltage

approximately equal to the midsupply point (average value of

the voltages on V+ and V−). Relying on this internal bias results

in an output common-mode voltage that is within about 25 mV

of the expected value.

In cases where more accurate control of the output common-

mode level is required, it is recommended that an external

source, or resistor divider (made up of 10 kΩ resistors), be used.

DRIVING A CAPACITIVE LOAD

A purely capacitive load can react with the pin and bondwire

inductance of the AD8131 resulting in high frequency ringing

in the pulse response. One way to minimize this effect is to

place a small resistor in series with the amplifier’s outputs as

shown in Figure 26.

AD8131

Rev. B | Page 18 of 20

APPLICATIONS

TWISTED-PAIR LINE DRIVER

The AD8131 has on-chip resistors that provide for a gain of 2

without any external parts. Several on-chip resistors are

trimmed to ensure that the gain is accurate, the common-mode

rejection is good, and the output is well balanced. This makes

the AD8131 very suitable as a single-ended-to-differential

twisted-pair line driver.

Figure 40 shows a circuit of an AD8131 driving a twisted-pair

line, like a Category 3 or Category 5 (Cat3 or Cat5), that is

already installed in many buildings for telephony and data

communications. The characteristic impedance of such a

transmission line is usually about 100 Ω. The outstanding

balance of the AD8131 output will minimize the common-

mode signal and therefore the amount of EMI generated by

driving the twisted pair.

The two resistors in series with each output terminate the line at

the transmit end. Since the impedances of the outputs of the

AD8131 are very low, they can be thought of as a short-circuit,

and the two terminating resistors form a 100 Ω termination at

the transmit end of the transmission line. The receive end is

directly terminated by a 100 Ω resistor across the line.

This back-termination of the transmission line divides the

output signal by two. The fixed gain of 2 of the AD8131 will

create a net unity gain for the system from end to end.

In this case, the input signal is provided by a signal generator

with an output impedance of 50 Ω. This is terminated with a

49.9 Ω resistor near +DIN of the AD8131. The effective parallel

resistance of the source and termination is 25 Ω.The 24.9 Ω

resistor from −DIN to ground matches the +DIN source

impedance and minimizes any dc and gain errors.

If +DIN is driven by a low-impedance source over a short

distance, such as the output of an op amp, then no termination

resistor is required at +DIN. In this case, the −DIN can be directly

tied to ground.

AD8131

24.9Ω

49.9Ω100Ω

0.1

49.9

0.1

+5V

–5V

RECEIVER

01072-040

Figure 40. Single-Ended-to-Differential 100 Ω Line Driver

3 V SUPPLY DIFFERENTIAL A-TO-D DRIVER

Many newer ADCs can run from a single 3 V supply, which can

save significant system power. In order to increase the dynamic

range at the analog input, they have differential inputs, which

double the dynamic range with respect to a single-ended input.

An added benefit of using a differential input is that the

distortion can be improved.

The low distortion and ability to run from a single 3 V supply make

the AD8131 suited as an A-to-D driver for some 10-bit, single-

supply applications. Figure 41 shows a schematic for a circuit for an

AD8131 driving an AD9203, a 10-bit, 40 MSPS ADC.

The common mode of the AD8131 output is set at midsupply

by the voltage divider connected to VOCM, and ac-bypassed with

a 0.1 μF capacitor. This provides for maximum dynamic range

between the supplies at the output of the AD8131. The 110 Ω

resistors at the AD8131 output, along with the shunt capacitors

form a one pole, low-pass filter for lowering noise and

antialiasing.

AD8131

LPF

+3V 1

20pF

AD9203

AVDD DRVDD

AINP

AINN

AVSS DRVSS

27 1

DIGITAL

OUTPUTS

0.1 F

10 F

0.1 F

110Ω

24.9Ω

49.9Ω

10kΩ

OCM

01072-041

Figure 41. Test Circuit for AD8131 Driving an AD9203, 10-Bit, 40 MSPS ADC

Figure 42 shows an FFT plot that was taken from the combined

devices at an analog input frequency of 2.5 MHz and a 40 MSPS

sampling rate. The performance of the AD8131 compares very

favorably with a center-tapped transformer drive, which has

typically been the best way to drive this ADC. The AD8131 has

the advantage of maintaining dc performance, which a

transformer solution cannot provide.

AD8131

Rev. B | Page 19 of 20

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

OUT

(dBm)

2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0

FREQUENCY (MHz)

01072-042

Figure 42. FFT Plot for AD8131/AD9203

UNITY-GAIN, SINGLE-ENDED-TO-DIFFERENTIAL

DRIVER

If it is not necessary to offset the output common-mode voltage

(via the VOCM pin), then the AD8131 can make a simple unity-

gain single-ended-to-differential amplifier that does not require

any external components. Figure 43 shows the schematic for

this circuit.

–

INPUT

OUT

+OUT

49.9Ω

10 F

0.1 F

10 F

0.1 F

+5V

–5V

AD8131

01072-043

Figure 43. Unity Gain, Single-Ended-to-Differential Amplifier

As shown above, when −DIN is left floating, there is 100%

feedback of +OUT to −IN via the internal feedback resistor.

This contrasts with the typical gain of 2 operation where −DIN is

grounded and one third of the +OUT is fed back to −IN. The

result is a closed-loop differential gain of 1.

Upon careful observation, it can be seen that only +DIN and VOCM

are referenced to ground. The ground voltage at VOCM is the

reference for this circuit. In this unity gain configuration, if a dc

voltage is applied to VOCM to shift the common-mode voltage, a

differential dc voltage will be created at the output, along with the

common-mode voltage change. Thus, this configuration cannot

be used when it is desired to offset the common-mode voltage of

the output with respect to the input at +DIN.

AD8131

Rev. B | Page 20 of 20

OUTLINE DIMENSIONS

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)× 45°

8°

0°

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)

BSC

6.20 (0.2440)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012-AA

Figure 44. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

0.80

0.60

0.40

8°

0°

4.90

BSC

PIN 1 0.65 BSC

3.00

BSC

SEATING

PLANE

0.15

0.00

0.38

0.22

1.10 MAX

3.00

BSC

COPLANARITY

0.10

0.23

0.08

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 45. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8131AR −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8

AD8131AR-REEL −40°C to +125°C 8-Lead SOIC, 13” Tape and Reel R-8

AD8131AR-REEL7 −40°C to +125°C 8-Lead SOIC, 7” Tape and Reel R-8

AD8131ARZ1−40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8

AD8131ARZ-REEL1−40°C to +125°C 8-Lead SOIC, 13” Tape and Reel R-8

AD8131ARZ-REEL71−40°C to +125°C 8-Lead SOIC, 7” Tape and Reel R-8

AD8131ARM −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 HJA

AD8131ARM-REEL −40°C to +125°C 8-Lead MSOP, 13” Tape and Reel RM-8 HJA

AD8131ARM-REEL7 −40°C to +125°C 8-Lead MSOP, 7” Tape and Reel RM-8 HJA

AD8131ARMZ1−40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 HJA#

AD8131ARMZ-REEL1−40°C to +125°C 8-Lead MSOP, 13” Tape and Reel RM-8 HJA#

AD8131ARMZ-REEL71−40°C to +125°C 8-Lead MSOP, 7” Tape and Reel RM-8 HJA#

1 Z = Pb-free part, # denotes Pb-free part; may be top or bottom marked.

registered trademarks are the property of their respective owners.

C01072–0–6/05(B)