Functional Diagram
* Pin 3 is the anode of the internal LED and must be left unconnected
for guaranteed data sheet performance. Pin 7 is not connected
internally.
** A 0.1 μF bypass capacitor must be connected between pins 1 and
4, and 5 and 8.
Description
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-772X or HCPL-072X optocouplers
utilize the latest CMOS IC technology to achieve out-
standing performance with very low power consump-
tion. The HCPL-772X/072X require only two bypass ca-
pacitors for complete CMOS compatability.
Basic building blocks of the HCPL-772X/072X are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver IC
which supplies current to the LED. The detector IC incor-
porates an integrated photodiode, a high-speed tran-
simpedance amplier, and a voltage comparator with an
output driver.
Features
x +5 V CMOS compatibility
x 20 ns maximum prop. delay skew
x High speed: 25 MBd
x 40 ns max. prop. delay
x 10 kV/μs minimum common mode rejection
x –40 to 85°C temperature range
x Safety and regulatory approvals
UL recognized
– 3750 Vrms for 1 min. per UL 1577
– 5000 Vrms for 1 min. per UL 1577
(for HCPL-772X option 020)
CSA component acceptance notice #5
IEC/EN/DIN EN 60747-5-2
– VIORM = 630 Vpeak for HCPL-772X option 060
– VIORM = 560 Vpeak for HCPL-072X option 060
Applications
x Digital eldbus isolation: CC-Link, DeviceNet, Pro-
bus, SDS
x AC plasma display panel level shifting
x Multiplexed data transmission
x Computer peripheral interface
x Microprocessor system interface
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
HCPL-0720, HCPL-7720, HCPL-0721 and HCPL-7721
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
TRUTH TABLE
POSITIVE LOGIC
VILED1 Vo OUTPUT
HOFF H
LON L
8
7
6
1
3
SHIELD 5
2
4
**VDD1
VI
*
GND1
VDD2**
VO
GND2
NC*
IO
LED1
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
2
Selection Guide
8-Pin DIP Small Outline
(300 Mil) SO-8 Data Rate PWD
HCPL-7721 HCPL-0721 25 MB 6 ns
HCPL-7720 HCPL-0720 25 MB 8 ns
Ordering Information
HCPL-0720, HCPL-0721, HCPL-7720 and HCPL-7721 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part RoHS non RoHS Surface Gull Tape UL 5000 Vrms/ IEC/EN/DIN
Number Compliant Compliant Package Mount Wing & Reel 1 Minute rating EN 60747-5-2 Quantity
-000E no option 50 per tube
-300E #300 X X 50 per tube
-500E #500 X X X 1000 per reel
HCPL-7720
-020E -020 300 mil X 50 per tube
HCPL-7721
-320E -320 DIP-8 X X X 50 per tube
-520E -520 X X X X 1000 per reel
-060E #060 X 50 per tube
-360E #360 X X X 50 per tube
-560E #560 X X X X 1000 per reel
-000E no option X X 100 per tube
HCPL-0720
-500E #500 SO-8 X X X 1500 per reel
HCPL-0721
-060E #060 X X X 100 per tube
-560E #560 X X X X 1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7720-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with
IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant.
Example 2:
HCPL-0721 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
3
Package Outline Drawing
HCPL-772X 8-Pin DIP Package
9.65 ± 0.25
(0.380 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXXV
YYWW
DATE CODE
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
5° TYP. 0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
*OPTION 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
OPTION 060 CODE*
3.56 ± 0.13
(0.140 ± 0.005)
4
Package Outline Drawing
HCPL-772X Package with Gull Wing Surface Mount Option 300
Package Outline Drawing
HCPL-072X Outline Drawing (Small Outline SO-8 Package)
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.65 ± 0.25
(0.380 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
1.080 ± 0.320
(0.043 ± 0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
XXXV
YWW
8765
4321
5.994 ± 0.203
(0.236 ± 0.008)
3.937 ± 0.127
(0.155 ± 0.005)
0.406 ± 0.076
(0.016 ± 0.003) 1.270
(0.050)BSC
5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005) 1.524
(0.060)
45° X 0.432
(0.017)
0.228 ± 0.025
(0.009 ± 0.001)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
0.305
(0.012)MIN.
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
0.203 ± 0.102
(0.008 ± 0.004)
7°
PIN ONE
0 ~ 7°
*
*
7.49 (0.295)
1.9 (0.075)
0.64 (0.025)
LAND PATTERN RECOMMENDATION
5
Regulatory Information
The HCPL-772X/072X have been approved by the following organizations:
UL
Recognized under UL 1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884Teil 2):2003-01. (Option 060 only)
Solder Reow Thermal Prole
Pb-Free IR Prole
0
TIME (SECONDS)
TEMPERATURE (°C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160°C
140°C
150°C
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
SOLDERING
TIME
200°C
PREHEATING TIME
150°C, 90 + 30 SEC.
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
217 °C
RAMP-DOWN
6 °C/SEC. MAX.
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
260 +0/-5 °C
t 25 °C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
t
p
t
s
PREHEAT
60 to 180 SEC.
t
L
T
L
T
smax
T
smin
25
T
p
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
T
smax
= 200 °C, T
smin
= 150 °C
Note: Non-halide ux should be used.
Note: Non-halide ux should be used.
6
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimen sions are needed as a starting point for the equip-
ment designer when determining the circuit insulation
requirements. However, once mounted on a printed
circuit board, minimum creepage and clearance require-
ments must be met as specied for individual equipment
standards. For creepage, the shortest distance path along
Insulation and Safety Related Specications
Value
Parameter Symbol 772X 072X Units Conditions
Minimum External Air L(I01) 7.1 4.9 mm Measured from input terminals to output
Gap (Clearance) terminals, shortest distance through air.
Minimum External L(I02) 7.4 4.8 mm Measured from input terminals to output
Tracking (Creepage) terminals, shortest distance path along body.
Minimum Internal Plastic 0.08 0.08 mm Insulation thickness between emitter and
Gap (Internal Clearance) detector; also known as distance through
insulation.
Tracking Resistance CTI ≥175 ≥175 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking
Index)
Isolation Group IIIa IIIa Material Group
(DIN VDE 0110, 1/89, Table 1)
the surface of a printed circuit board between the solder
llets of the input and output leads must be considered.
There are recommended techniques such as grooves
and ribs which may be used on a printed circuit board to
achieve desired creepage and clearances. Creepage and
clearance distances will also change depending on fac-
tors such as pollution degree and insulation level.
7
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)
HCPL-772X HCPL-072X
Description Symbol Option 060 Option 060 Units
Installation classication per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms I-IV I-IV
for rated mains voltage ≤300 V rms I-IV I-III
for rated mains voltage ≤450 V rms I-III
Climatic Classication 55/85/21 55/85/21
Pollution Degree (DIN VDE 0110/1.89) 2 2
Maximum Working Insulation Voltage VIORM 630 560 V peak
Input to Output Test Voltage, Method b† VPR 1181 1050 V peak
VIORM x 1.875 = VPR, 100% Production
Test with tm = 1 sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a† VPR 945 840 V peak
VIORM x 1.5 = VPR, Type and Sample Test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage† VIOTM 6000 4000 V peak
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature TS 175 150 °C
Input Current IS,INPUT 230 150 mA
Output Power PS,OUTPUT 600 600 mW
Insulation Resistance at TS, V10 = 500 V RIO ≥109 ≥109 Ω
† Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations
section IEC/EN/DIN EN 60747-5-2, for a detailed description.
Note:
These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured
by means of protective circuits.
The surface mount classication is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Figure
Storage Temperature TS –55 125 °C
Ambient Operating Temperature[1] T
A –40 +85 °C
Supply Voltages VDD1, VDD2 0 6.0 Volts
Input Voltage VI –0.5 VDD1 +0.5 Volts
Output Voltage VO –0.5 VDD2 +0.5 Volts
Average Output Current IO 10 mA
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
Solder Reow Temperature Prole See Solder Reow Temperature Prole Section
Recommended Operating Conditions
Parameter Symbol Min. Max. Units Figure
Ambient Operating Temperature TA –40 +85 °C
Supply Voltages VDD1, VDD2 4.5 5.5 V
Logic High Input Voltage VIH 2.0 VDD1 V 1, 2
Logic Low Input Voltage VIL 0.0 0.8 V
Input Signal Rise and Fall Times tr, tf 1.0 ms
8
Electrical Specications
Test conditions that are not specied can be anywhere within the recommended operating range.
All typical specications are at TA = +25°C, VDD1 = VDD2 = +5 V.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
DC Specications
Logic Low Input IDD1L 6.0 10.0 mA VI = 0 V 2
Supply Current
Logic High Input IDD1H 1.5 3.0 mA VI = VDD1
Supply Current
Output Supply Current IDD2L 5.5 9.0 mA
IDD2H 7.0 9.0
Input Current II –10 10 μA
Logic High Output VOH 4.4 5.0 V IO = -20 μA, VI = VIH 1, 2
Voltage 4.0 4.8 IO = -4 mA, VI = VIH
Logic Low Output VOL 0 0.1 V IO = 20 μA, VI = VIL
Voltage
0.1 V
IO = 400 μA, VI = VIL
0.5 1.0 IO = 4 mA, VI = VIL
Switching Specications
Propagation Delay Time tPHL 20 40 ns CL = 15 pF 3, 6 3
to Logic Low Output CMOS Signal Levels
Propagation Delay Time tPLH 23 40
to Logic High Output
Pulse Width PW 40
Data Rate 25 MBd
Pulse Width Distortion PWD
7721/0721
3 6 ns 7 4
|tPHL - tPLH|
7720/0720
3 8 ns
Propagation Delay Skew tPSK 20 5
Output Rise Time tR 9 ns
(10 - 90%)
Output Fall Time tF 8 ns
(90 - 10%)
Common Mode |CMH| 10 20 kV/μs VI = VDD1, VO > 6
Transient Immunity at 0.8 VDD1,
Logic High Output VCM = 1000 V
Common Mode |CML| 10 20 VI = 0 V, VO > 0.8 V,
Transient Immunity at VCM = 1000 V
Logic Low Output
Input Dynamic Power CPD1 60 pF 7
Dissipation
Capacitance
Output Dynamic Power CPD2 10
Dissipation
Capacitance
9
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality.
2. The LED is ON when VI is low and OFF when VI is high.
3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
4. PWD is dened as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
5. tPSK is equal to the magnitude of the worst case dierence in tPHL and/or tPLH that will be seen between units at any given temperature within
the recommended operating conditions.
6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common
mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising
and falling common mode voltage edges.
7. Unloaded dynamic power dissipation is calculated as follows: CPD * VDD2 * f + IDD * VDD, where f is switching frequency in MHz.
8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
9. In accordance with UL1577, each HCPL-072X is proof tested by applying an insulation test voltage ≥4500 VRMS for 1 second (leakage detection
current limit, II-O ≤5 μA). Each HCPL-772X is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detection
current limit. II-O ≤ 5 μA.)
10. The Input-Output Momentary With stand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specication or Avago Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.”
11. CI is the capacitance measured at pin 2 (VI).
Figure 1. Typical output voltage vs. input volt-
age.
Figure 2. Typical input voltage switching thresh-
old vs. input supply voltage.
Figure 3. Typical propagation delays vs. tem-
perature.
V
O
(V)
0
0
V
I
(V)
5
4
1
4123
5
3
2
0 °C
25 °C
85 °C
V
ITH
(V)
4.5
1.6
V
DD1
(V)
5.5
2.1
1.7
5.254.75 5
2.2
2.0
1.8
1.9
0 °C
25 °C
85 °C
TPLH, TPHL (ns)
0
15
TA (C)
80
27
17
6020 30
29
25
19
21
10 40 50 70
23
TPLH
TPHL
Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary 072X VISO 3750 Vrms RH ≤50%, 8, 9,
Withstand Voltage 772X 3750 t = 1 min., 10
Option 020 5000 TA = 25°C
Resistance RI-O 1012 Ω VI-O = 500 Vdc 8
(Input-Output)
Capacitance CI-O 0.6 pF f = 1 MHz
(Input-Output)
Input Capacitance CI 3.0 11
Input IC Junction-to-Case -772XT
jci 145 °C/W Thermocouple
Thermal Resistance -072X 160 located at center
Output IC Junction-to-Case -772X Tjco 140 underside of package
Thermal Resistance -072X 135
Package Power Dissipation PPD 150 mW
10
Figure 4. Typical pulse width distortion vs.
temperature.
Figure 5. Typical rise time vs. temperature. Figure 6. Typical fall time vs. temperature.
Figure 7. Typical propagation delays vs. output
load capacitance.
Figure 8. Typical pulse width distortion vs.
output load capacitance.
Figure 9. Thermal derating curve, dependence of safety limiting value with case temperature per
IEC/EN/DIN EN 60747-5-2.
PWD
(ns)
0
0
T
A
(C)
80
3
6020
4
1
40
2
T
R
(ns)
0
8
T
A
(C)
80
10
6020
11
9
40
T
F
(ns)
0
2
T
A
(C)
80
6
6020
7
3
40
5
4
OUTPUT POWER – PS, INPUT CURRENT – IS
0
0
TA – CASE TEMPERATURE – °C
20050
400
12525 75 100 150
600
800
200
100
300
500
700
175
(150)
PS (mW)
IS (mA)
SURFACE MOUNT SO8 PRODUCT
TPLH, TPHL (ns)
15
15
CI (pF)
50
27
40
29
17
30
23
21
2520 35 45
19
25
TPLH
TPHL
PWD (ns)
15
0
CI (pF)
50
5
40
6
1
30
3
2520 35 45
2
4
OUTPUT POWER – PS, INPUT CURRENT – IS
0
0
TA – CASE TEMPERATURE – °C
20050
400
12525 75 100 150
600
800
200
100
300
500
700
175
(230)
PS (mW)
IS (mA)
STANDARD 8 PIN DIP PRODUCT
11
Application Information
Bypassing and PC Board Layout
The HCPL-772X/072X optocouplers are extremely easy
to use. No external interface circuitry is required because
the HCPL-772X/072X use high-speed CMOS IC technol-
ogy allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 10, the only external components
Figure 10. Recommended printed circuit board layout.
Figure 11. Recommended printed circuit board layout.
Propagation Delay, Pulse-Width Distortion and Propagation Delay
Skew
Propagation Delay is a gure of merit which describes
how quickly a logic signal propagates through a sys-
tem. The propaga tion delay from low to high (tPLH) is the
amount of time required for an input signal to propa-
gate to the output, causing the output to change from
Figure 12.
INPUT
t
PLH
t
PHL
OUTPUT
V
I
V
O
10%
90%90%
10%
V
OH
V
OL
0 V
50%
5 V CMOS
2.5 V CMOS
7
5
6
8
2
3
4
1
GND2
C1 C2
NC
VDD2
NC VO
VDD1
VI
72X
YWW
C1, C2 = 0.01 μF TO 0.1 μF
GND1
V
DD2
C1 C2
72X
YWW
V
O
GND
2
V
DD1
V
I
GND
1
C1, C2 = 0.01 μF TO 0.1 μF
required for proper operation are two bypass capaci-
tors. Capacitor values should be between 0.01 μF and
0.1 μF. For each capacitor, the total lead length between
both ends of the capacitor and the power-supply pins
should not exceed 20 mm. Figure 11 illustrates the rec-
ommended printed circuit board layout for the HPCL-
772X/072X.
low to high. Similarly, the propagation delay from high
to low (tPHL) is the amount of time required for the input
signal to propagate to the output, causing the output to
change from high to low. See Figure 12.
12
Figure 13. Propagation delay skew waveform. Figure 14. Parallel data transmission example.
Propagation delay skew repre sents the uncertainty of
where an edge might be after being sent through an op-
tocoupler. Figure 14 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these consider-
ations, the absolute minimum pulse width that can be sent
through optocouplers in a parallel application is twice tPSK.
Pulse-width distortion (PWD) is the dierence between
tPHL and tPLH and often determines the maxi mum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being trans mitted. Typical-
ly, PWD on the order of 20 - 30% of the minimum pulse
width is tolerable.
Propagation delay skew, tPSK, is an important parameter
to con sider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of opto-
couplers, dierences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at dier-
ent times. If this dierence in propagation delay is large
enough it will determine the maximum rate at which
parallel data can be sent through the optocouplers.
50%
50%
t
PSK
V
I
V
O
V
I
V
O
2.5 V,
CMOS
2.5 V,
CMOS
DATA
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
t
PSK
t
PSK
Propagation delay skew is dened as the dierence be-
tween the minimum and maximum propa gation delays,
either tPLH or tPHL, for any given group of optocoup lers
which are operating under the same conditions (i.e., the
same drive current, supply volt age, output load, and op-
erating temperature). As illustrated in Figure 13, if the in-
puts of a group of optocouplers are switched either ON
or OFF at the same time, tPSK is the dierence between
the shortest propagation delay, either tPLH or tPHL, and
the longest propagation delay, either tPLH or tPHL.
As mentioned earlier, tPSK can determine the maximum
parallel data transmission rate. Figure 14 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the opto-
couplers. The gure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked o of the rising edge of
the clock.
A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.
The HCPL-772X/072X optocouplers oer the advantage
of guaranteed specications for propagation delays,
pulse-width distortion, and propagation delay skew
over the recommended temperature and power supply
ranges.
13
Figure 15. Typical eld bus communication physical model.
Digital Field Bus Communication Networks
To date, despite its many draw backs, the 4 - 20 mA ana-
log current loop has been the most widely accepted
standard for implementing process control systems. In
today’s manufacturing environment, however, automat-
ed systems are expected to help manage the process,
not merely monitor it. With the advent of digital eld bus
communication networks such as CC-Link, DeviceNet,
PROFIBUS, and Smart Distributed Systems (SDS), gone
are the days of constrained information. Controllers can
CONTROLLER
TRANSCEIVER
OPTICAL
ISOLATION
BUS
INTERFACE
TRANSCEIVER
OPTICAL
ISOLATION
BUS
INTERFACE
TRANSCEIVER
OPTICAL
ISOLATION
BUS
INTERFACE
TRANSCEIVER
OPTICAL
ISOLATION
BUS
INTERFACE
TRANSCEIVER
OPTICAL
ISOLATION
BUS
INTERFACE
FIELD BUS
XXXXXX
YYY
SENSOR
DEVICE
CONFIGURATION
MOTOR
STARTER
MOTOR
CONTROLLER
now receive multiple readings from eld devices (sen-
sors, actuators, etc.) in addition to diagnostic informa-
tion.
The physical model for each of these digital eld bus
communica tion networks is very similar as shown in
Figure 15. Each includes one or more buses, an interface
unit, optical isolation, transceiver, and sensing and/or ac-
tuating devices.
14
Optical Isolation for Field Bus Networks
To recognize the full benets of these networks, each
recom mends providing galvanic isolation using Avago
optocouplers. Since network communication is bi-direc-
tional (involving receiving data from and transmitting
data onto the network), two Avago optocouplers are
needed. By providing galvanic isolation, data integrity is
retained via noise reduction and the elimination of false
signals. In addition, the network receives maximum pro-
tection from power system faults and ground loops.
Within an isolated node, such as the DeviceNet Node
shown in Figure 16, some of the node’s components are
referenced to a ground other than V- of the network.
NODE/APP SPECIFIC
uP/CAN
HCPL
772x/072x
HCPL
772x/072x
TRANSCEIVER
LOCAL
NODE
SUPPLY
5 V REG.
NETWORK
POWER
SUPPLY
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
GALVANIC
ISOLATION
BOUNDARY
AC LINE
DRAIN/SHIELD
SIGNAL
POWER
Figure 16. Typical DeviceNet Node.
These components could include such things as devices
with serial ports, parallel ports, RS232 and RS485 type
ports. As shown in Figure 16, power from the network is
used only for the transceiver and input (network) side of
the optocouplers.
Isolation of nodes connected to any of the three types of
digital eld bus networks is best achieved by using the
HCPL-772X/072X optocouplers. For each network, the
HCPL-772X/072X satisify the critical propagation delay
and pulse width distortion require ments over the tem-
perature range of 0°C to +85°C, and power supply volt-
age range of 4.5 V to 5.5 V.
15
Implementing CC-Link with the HCPL-772X/072X
CC-Link (Control and Communication Link) is developed
to merge control and information in the low-level net-
work (eld network) by PCs, thereby making the mul-
tivendor environment a reality. It has data control and
message-exchange function, as well as bit control func-
tion, and operates at the speed up to 10 Mbps.
Figure 17. Recommended CC-Link application circuit.
VDD1
HCPL-7720#500
0.1 μ
VI
GND1
VDD2
VO
GND
GND1
RD1
10 K
VDD1
(5 V)
0.1 μ
GND2
VDD2
(5 V)
VDD2
HCPL-7720#500
0.1 μ
VO
GND
VDD1
VI
GND
SD
0.1 μ
VOE
HCPL-2611#560
VO
NC
+
–
NC
0.1 μ
MPU
BOARD
OUTPUT
390
HC14
HC14
1 K
VOE
HCPL-2611#560
VO
GND
NC
+
–
NC
0.1 μ SDGATEON
390
HC14
HC14
1 K
10 K
10 K
GND
VDD
VDD
VCC
VCC
GND
GND
SN75ALS181NS
FIL
DA
DB
DG
SLD
FG
A
B
Y
Z
D
DE
RE
R
Power Supplies and Bypassing
The recommended CC-Link circuit is shown in Figure
17. Since the HCPL-772X/072X are fully compatible with
CMOS logic level signals, the optocoupler is connected
directly to the transceiver. Two bypass capacitors (with
values between 0.01 μF and 0.1 μF) are required and
should be located as close as possible to the input and
output power supply pins of the HCPL-772X/072X. For
each capacitor, the total lead length between both ends
of capacitor and the power supply pins should not ex-
ceed 20 mm. The bypass capacitors are required be-
cause of the high speed digital nature of the signals in-
side the optocoupler.
16
Implementing DeviceNet and SDS with the HCPL-772X/072X
With transmission rates up to 1 Mbit/s, both DeviceNet
and SDS are based upon the same broadcast-oriented,
communica tions protocol — the Controller Area Network
(CAN). Three types of isolated nodes are recommended
for use on these networks: Isolated Node Powered by
the Network (Figure 18), Isolated Node with Transceiver
Powered by the Network (Figure 19), and Isolated Node
Providing Power to the Network (Figure 20).
Figure 18. Isolated node powered by the network.
NODE/APP SPECIFIC
uP/CAN
HCPL
772x/072x
HCPL
772x/072x
TRANSCEIVER
REG.
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
GALVANIC
ISOLATION
BOUNDARY
DRAIN/SHIELD
SIGNAL
POWER
ISOLATED
SWITCHING
POWER
SUPPLY
NETWORK
POWER
SUPPLY
Isolated Node with Transceiver Powered by the Network
Figure 19 shows a node powered by both the network
and another source. In this case, the trans ceiver and iso-
lated (network) side of the two optocouplers are pow-
ered by the network. The rest of the node is powered by
the AC line which is very benecial when an application
requires a signicant amount of power. This method is
also desirable as it does not heavily load the network.
More importantly, the unique “dual-inverting” design of
the HCPL-772X/072X ensure the network will not “lock-
up” if either AC line power to the node is lost or the node
powered-o. Specically, when input power (VDD1) to the
HCPL-772X/072X located in the transmit path is eliminat-
ed, a RECESSIVE bus state is ensured as the HCPL-772X/
072X output voltage (VO) go HIGH.
Isolated Node Powered by the Network
This type of node is very exible and as can be seen in
Figure 18, is regarded as “isolated” because not all of its
components have the same ground reference. Yet, all
compo nents are still powered by the network. This node
contains two regulators: one is isolated and powers the
CAN controller, node-specic application and isolated
(node) side of the two optocoup lers while the other is
non-isolated. The non-isolated regulator supplies the
transceiver and the non-isolated (network) half of the
two optocouplers.
*Bus V+ Sensing
It is suggested that the Bus V+ sense block shown in Fig-
ure 19 be implemented. A locally powered node with an
un-powered isolated Physical Layer will accumulate er-
rors and become bus-o if it attempts to transmit. The
Bus V+ sense signal would be used to change the BOI at-
tribute of the DeviceNet Object to the “auto-reset” (01)
value. Refer to Volume 1, Section 5.5.3. This would cause
the node to continually reset until bus power was detect-
ed. Once power was detected, the BOI attribute would
be returned to the “hold in bus-o” (00) value. The BOI
attribute should not be left in the “auto-reset” (01) value
since this defeats the jabber protection capability of the
CAN error connement. Any inexpensive low frequency
optical isolator can be used to implement this feature.
17
Figure 20. Isolated node providing power to the network.
Isolated Node Providing Power to the Network
Figure 20 shows a node providing power to the network.
The AC line powers a regulator which provides ve (5)
volts locally. The AC line also powers a 24 volt isolated
supply, which powers the network, and another ve-volt
regulator, which, in turn, powers the transceiver and iso-
lated (network) side of the two optocouplers. This meth-
od is recommended when there are a limited number of
devices on the network that don’t require much power,
thus eliminating the need for separate power supplies.
NODE/APP SPECIFIC
uP/CAN
HCPL
772x/072x
HCPL
772x/072x
TRANSCEIVER
5 V REG.
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
GALVANIC
ISOLATION
BOUNDARY
AC LINE
DRAIN/SHIELD
SIGNAL
POWER
ISOLATED
SWITCHING
POWER
SUPPLY
5 V REG.
DEVICENET NODE
Figure 19. Isolated node with transceiver powered by the network.
NODE/APP SPECIFIC
uP/CAN
HCPL
772x/072x
HCPL
772x/072x
TRANSCEIVER
NON ISO
5 V
REG.
NETWORK
POWER
SUPPLY
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
GALVANIC
ISOLATION
BOUNDARY
AC LINE
DRAIN/SHIELD
SIGNAL
POWER
*HCPL
772x/072x
* OPTIONAL FOR BUS V + SENSE
More importantly, the unique “dual-inverting” design of
the HCPL-772X/072X ensure the network will not “lock-
up” if either AC line power to the node is lost or the node
powered-o. Specically, when input power (VDD1) to the
HCPL-772X/072X located in the transmit path is eliminat-
ed, a RECESSIVE bus state is ensured as the HCPL-772X/
072X output voltage (VO) go HIGH.
18
Power Supplies and Bypassing
The recommended DeviceNet application circuit is
shown in Figure 21. Since the HCPL-772X/072X are fully
compatible with CMOS logic level signals, the optocoup-
ler is connected directly to the CAN transceiver. Two by-
pass capacitors (with values between 0.01 and 0.1 μF)
are required and should be located as close as possible
Figure 21. Recommended DeviceNet application circuit.
Implementing PROFIBUS with the HCPL-772X/072X
An acronym for Process Fieldbus, PROFIBUS is essentially
a twisted-pair serial link very similar to RS-485 capable
of achieving high-speed communi cation up to 12 MBd.
As shown in Figure 22, a PROFIBUS Control ler (PBC) es-
tablishes the connec tion of a eld automation unit (con-
trol or central processing station) or a eld device to
the transmission medium. The PBC consists of the line
transceiver, optical isolation, frame character transmit-
ter/receiver (UART), and the FDL/APP processor with the
interface to the PROFIBUS user.
PROFIBUS USER:
CONTROL STATION
(CENTRAL PROCESSING)
OR FIELD DEVICE
USER INTERFACE
FDL/APP
PROCESSOR
TRANSCEIVER
OPTICAL ISOLATION
UART
PBC
MEDIUM
8
7
6
1
3
5
2
4
VDD1
VIN
GND1
VDD2
VO
GND2
HCPL-772x
HCPL-072x
4
3
2
5
7
1
6
8
GND2
VO
VDD2
GND1
VIN
VDD1
HCPL-772x
HCPL-072x
GND
ISO 5 V
ISO 5 V
0.01 μF
RX0
0.01 μF
TX0 0.01
μF
0.01
μF
TxD
CANH
REF
RXD
82C250
VCC
GND
Rs
CANL
C4
0.01 μF
+
VREF
LINEAR OR
SWITCHING
REGULATOR
5 V
5 V
++
R1
1 M
C1
0.01 μF
500 V
D1
30 V
5 V+
4 CAN+
3 SHIELD
2 CAN–
1 V–
GALVANIC
ISOLATION
BOUNDARY
Figure 22. PROFIBUS Controller (PBC).
to the input and output power-supply pins of the HCPL-
772X/072X. For each capacitor, the total lead length be-
tween both ends of the capacitor and the power supply
pins should not exceed 20 mm. The bypass capac itors
are required because of the high-speed digital nature of
the signals inside the optocoupler.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. Obsoletes AV01-0565EN
AV02-0876EN - March 15, 2011
Power Supplies and Bypassing
The recommended PROFIBUS application circuit is
shown in Figure 23. Since the HCPL-772X/072X are fully
compatible with CMOS logic level signals, the optocoup-
ler is connected directly to the transceiver. Two bypass
capacitors (with values between 0.01 and 0.1 μF) are
required and should be located as close as possible to
the input and output power-supply pins of the HCPL-
772X/072X. For each capacitor, the total lead length be-
tween both ends of the capacitor and the power supply
pins should not exceed 20 mm. The bypass capac itors
are required because of the high-speed digital nature of
the signals inside the optocoupler.
Being very similar to multi-station RS485 systems, the
HCPL-061N optocoupler provides a transmit disable
function which is necessary to make the bus free after
each master/slave transmission cycle. Specically, the
HCPL-061N disables the transmitter of the line driver by
putting it into a high state mode. In addition, the HCPL-
061N switches the RX/TX driver IC into the listen mode.
The HCPL-061N oers HCMOS compatibility and the
high CMR performance (1 kV/μs at VCM = 1000 V) es-
sential in industrial communication interfaces.
Figure 23. Recommended PROFIBUS application circuit.
1
2
3
8
6
4
7
5
V
DD2
V
O
GND
2
V
DD1
V
IN
GND
1
HCPL-772x
HCPL-072x
8
7
6
1
3
5
2
4
V
DD1
V
IN
GND
1
V
DD2
V
O
GND
2
HCPL-772x
HCPL-072x
5 V
0.01 μF
0.01 μF
0.01
μF
0.01
μF
R
A
SN75176B
V
CC
GND
DE
B
0.01
μF
ISO 5 V
1 M
0.01 μF
+
–
GALVANIC
ISOLATION
BOUNDARY
5 V ISO 5 V
RE
D
1
4
3
2
Rx
ISO 5 V
Tx
8
7
6
1
3
5
2
4
ANODE
V
CC
V
O
GND
5 V
0.01
μF
ISO 5 V
Tx ENABLE CATHODE
V
E
680 Ω
HCPL-061N
1, 0 kΩ
5
7
6
8
RT SHIELD