1
TM
File Number 4847
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 |Intersil and Design is a trademark of Intersil Corporation. |Copyright © Intersil Corporation 2000
HUF75823D3, HUF75823D3S
14A, 150V, 0.150 Ohm, N-Channel,
UltraFET Power MOSFET
Packaging
Symbol
Features
• Ultra Low On-Resistance
-r
DS(ON) = 0.150Ω, VGS =10V
• Simulation Models
- Temperature Compensated PSPICE™ and SABER©
Electrical Models
- Spice and SABER© Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Ordering Information
Absolute Maximum Ratings TC= 25oC, Unless Otherwise Specified
JEDEC TO-251AA JEDEC TO-252AA
DRAIN
(FLANGE)
DRAIN
SOURCE
GATE
HUF75823D3
GATE
SOURCE
DRAIN
(FLANGE)
HUF75823D3S
D
G
S
PART NUMBER PACKAGE BRAND
HUF75823D3 TO-251AA 75823D
HUF75823D3S TO-252AA 75823D
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF75823D3ST.
HUF75823D3, HUF75823D3S UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 150 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 150 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Drain Current
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
14
10
Figure 4
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
0.57 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Data Sheet April 2000
2
Electrical Specifications TC= 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 150 - - V
Zero Gate Voltage Drain Current IDSS VDS = 140V, VGS = 0V - - 1 µA
VDS = 135V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
Drain to Source On Resistance rDS(ON) ID= 14A, VGS = 10V (Figure 9) - 0.125 0.150 Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case RθJC TO-251 and TO-252 - - 1.76 oC/W
Thermal Resistance Junction to
Ambient RθJA - - 100 oC/W
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 75V, ID = 14A
VGS =10V,
RGS = 12Ω
(Figures 18, 19)
- - 48 ns
Turn-On Delay Time td(ON) - 7.7 - ns
Rise Time tr-24-ns
Turn-Off Delay Time td(OFF) -45-ns
Fall Time tf-26-ns
Turn-Off Time tOFF - - 105 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 75V,
ID = 14A,
Ig(REF) = 1.0mA
(Figures 13, 16, 17)
-4354nC
Gate Charge at 10V Qg(10) VGS = 0V to 10V - 23 29 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 1.5 1.9 nC
Gate to Source Gate Charge Qgs - 3.4 - nC
Gate to Drain "Miller" Charge Qgd - 8.8 - nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
- 800 - pF
Output Capacitance COSS - 180 - pF
Reverse Transfer Capacitance CRSS -65-pF
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 14A - - 1.25 V
ISD = 7A - - 1.00 V
Reverse Recovery Time trr ISD = 14A, dISD/dt = 100A/µs - - 150 ns
Reverse Recovered Charge QRR ISD = 14A, dISD/dt = 100A/µs - - 750 nC
HUF75823D3, HUF75823D3S
3
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
T
C
, CASE TEMPERATURE (
o
C)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
9
15
50 75 100 125 150
025
I
D
, DRAIN CURRENT (A)
T
C
, CASE TEMPERATURE (
o
C)
V
GS
= 10V
175
3
6
12
0.1
1
2
10
-4
10
-3
10
-2
10
-1
10
0
10
1
0.0110
-5
t, RECTANGULAR PULSE DURATION (s)
Z
θJC
, NORMALIZED
THERMAL IMPEDANCE
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
P
DM
t
1
t
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
100
200
10 10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-5
I
DM
, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
T
C
= 25
o
C
I = I
25
175 - T
C
150
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
V
GS
= 10V
HUF75823D3, HUF75823D3S
4
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
10
10 300
100
1
1V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
T
J
= MAX RATED
T
C
= 25
o
C
SINGLE PULSE
100
100µs
10ms
1ms
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
0.5
80
0.001 0.01 0.1 10
I
AS
, AVALANCHE CURRENT (A)
t
AV
, TIME IN AVALANCHE (ms)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
1
10
1
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R ≠ 0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
0.5
0
12
20
28
234 6
I
D,
DRAIN CURRENT (A)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= 25
o
C
T
J
= -55
o
C
5
4
16
24
8
0
12
20
28
4
16
24
8
01234
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
V
GS
= 10V
V
GS
= 6V
0.4
0.8
1.2
1.6
2.8
-80 -40 0 40 80 120 200
NORMALIZED DRAIN TO SOURCE
T
J
, JUNCTION TEMPERATURE (
o
C)
ON RESISTANCE
V
GS
= 10V, I
D
= 14A
PULSE DURATION =
80µs
DUTY CYCLE = 0.5% MAX
160
2.0
2.4
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 200
NORMALIZED GATE
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
= V
DS
, I
D
= 250µA
THRESHOLD VOLTAGE
160
HUF75823D3, HUF75823D3S
5
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves (Continued)
0.9
1.0
1.1
1.2
-80 -40 0 40 80 120 200
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250µA
160
10
100
1000
3000
0.1 1.0 10 100
C, CAPACITANCE (pF)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
=C
GS
+ C
GD
C
RSS
=C
GD
C
OSS
≅ C
DS
+ C
GD
0
2
4
6
8
10
020
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DD
= 75V
Q
g
, GATE CHARGE (nC)
I
D
= 14A
I
D
= 7A
WAVEFORMS IN
DESCENDING ORDER:
10 15 255
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
HUF75823D3, HUF75823D3S
6
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF75823D3, HUF75823D3S
7
PSPICE Electrical Model
.SUBCKT HUF75823 2 1 3 ; rev 18 February 2000
CA 12 8 1.2e-9
CB 15 14 1.3e-9
CIN 6 8 7.4e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 157.1
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 3.11e-9
LSOURCE 3 7 3.72e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.7e-2
RGATE 9 20 2.13
RLDRAIN 2 5 10
RLGATE 1 9 31.1
RLSOURCE 3 7 37.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.0e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*25),3))}
.MODEL DBODYMOD D (IS = 6.5e-13 RS = 1.06e-2 XTI = 5 TRS1 = 2.4e-3 TRS2 = 1.5e-6 CJO = 8.0e-10 TT = 1.1e-7 M = 0.6)
.MODEL DBREAKMOD D (RS = 2.0 TRS1 = 2.0e-3 TRS2 = 1.0e-6)
.MODEL DPLCAPMOD D (CJO = 8.9e-10 IS = 1e-30 M = 0.8)
.MODEL MMEDMOD NMOS (VTO = 3.36 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.13)
.MODEL MSTROMOD NMOS (VTO = 3.84 KP = 63 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.89 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 21.3 )
.MODEL RBREAKMOD RES (TC1 = 1.08e-3 TC2 = -6.0e-7)
.MODEL RDRAINMOD RES (TC1 = 1.1e-2 TC2 = 2.7e-5)
.MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 2.0e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.8e-3 TC2 = -9.0e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.1e-3 TC2 = -9.0e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.8 VOFF= -2.4)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.4 VOFF= -5.8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.8 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.8)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF75823D3, HUF75823D3S
8
SABER Electrical Model
REV 18 February 2000
template huf75823 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 6.5e-13, rs = 1.06e-2, xti = 5, trs1 = 2.4e-3, trs2 = 1.5e-6, cjo = 8.0e-10, tt = 1.1e-7, m = 0.6)
dp..model dbreakmod = (rs = 2.0, trs1 = 2.0e-3, trs2 = 1.0e-6)
dp..model dplcapmod = (cjo = 8.9e-10, is = 10e-30, m = 0.8)
m..model mmedmod = (type=_n, vto = 3.36, kp = 5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.84, kp = 63, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.89, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.8, voff = -2.4)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.4, voff = -5.8)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.8, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.8)
c.ca n12 n8 = 1.2e-9
c.cb n15 n14 = 1.3e-9
c.cin n6 n8 = 7.4e-10
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 3.11e-9
l.lsource n3 n7 = 3.72e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.08e-3, tc2 = -6.0e-7
res.rdrain n50 n16 = 7.7e-2, tc1 = 1.1e-2, tc2 = 2.7e-5
res.rgate n9 n20 = 2.13
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 31.1
res.rlsource n3 n7 = 37.2
res.rslc1 n5 n51 = 1e-6, tc1 = 3.5e-3, tc2 = 2.0e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.0e-2, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.1e-3, tc2 = -9.0e-7
res.rvthres n22 n8 = 1, tc1 = -2.8e-3, tc2 = -9.0e-6
spe.ebreak n11 n7 n17 n18 = 157.1
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/25))** 3))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF75823D3, HUF75823D3S
9
SPICE Thermal Model
REV 25 October 1999
HUF75823D
CTHERM1 th 6 1.40e-3
CTHERM2 6 5 5.55e-3
CTHERM3 5 4 5.65e-3
CTHERM4 4 3 6.10e-3
CTHERM5 3 2 9.80e-3
CTHERM6 2 tl 7.70e-2
RTHERM1 th 6 1.10e-2
RTHERM2 6 5 5.80e-2
RTHERM3 5 4 1.35e-1
RTHERM4 4 3 3.60e-1
RTHERM5 3 2 4.13e-1
RTHERM6 2 tl 4.30e-1
SABER Thermal Model
SABER thermal model HUF75823D
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.40e-3
ctherm.ctherm2 6 5 = 5.55e-3
ctherm.ctherm3 5 4 = 5.65e-3
ctherm.ctherm4 4 3 = 6.10e-3
ctherm.ctherm5 3 2 = 9.80e-3
ctherm.ctherm6 2 tl = 7.70e-2
rtherm.rtherm1 th 6 = 1.10e-2
rtherm.rtherm2 6 5 = 5.80e-2
rtherm.rtherm3 5 4 = 1.35e-1
rtherm.rtherm4 4 3 = 3.60e-1
rtherm.rtherm5 3 2 = 4.13e-1
rtherm.rtherm6 2 tl = 4.30e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF75823D3, HUF75823D3S
10
HUF75823D3, HUF75823D3S
TO-252AA
SURFACE MOUNT JEDEC TO-252AA PLASTIC PACKAGE
TO-252AA
16mm TAPE AND REEL
b2
E
D
L3
L
e
b1
b
13
A
L
c
SEATING
BACK VIEW
2
H1A1
b3
e1J1
L1
TERM. 4 0.265
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
(6.7)
0.265 (6.7)
0.070 (1.8)
0.118 (3.0)
0.063 (1.6) TYP
0.090 (2.3) TYP
PLANE
SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX
A 0.086 0.094 2.19 2.38 -
A10.018 0.022 0.46 0.55 4, 5
b 0.028 0.032 0.72 0.81 4, 5
b10.033 0.045 0.84 1.14 4
b20.205 0.215 5.21 5.46 4, 5
b30.190 - 4.83 - 2
c 0.018 0.022 0.46 0.55 4, 5
D 0.270 0.295 6.86 7.49 -
E 0.250 0.265 6.35 6.73 -
e 0.090 TYP 2.28 TYP 7
e10.180 BSC 4.57 BSC 7
H10.035 0.045 0.89 1.14 -
J10.040 0.045 1.02 1.14 -
L 0.100 0.115 2.54 2.92 -
L10.020 - 0.51 - 4 , 6
L20.025 0.040 0.64 1.01 3
L30.170 - 4.32 - 2
NOTES:
1. These dimensions are within allowable dimensions of Rev. B of
JEDEC TO-252AA outline dated 9-88.
2. L3and b3dimensions establish a minimum mounting surface for
terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L1 is the terminal length for soldering.
7. Positionofleadtobemeasured0.090inches(2.28mm)frombottom
of dimension D.
8. Controlling dimension: Inch.
9. Revision 11 dated 1-00.
2.0mm
4.0mm1.5mm
DIA. HOLE
8.0mm
16mm
USER DIRECTION OF FEED
C
L
1.75mm
330mm 50mm
13mm
22.4mm
16.4mm
COVER TAPE
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
11
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HUF75823D3, HUF75823D3S
TO-251AA
3 LEAD JEDEC TO-251AA PLASTIC PACKAGE
b2
EA
c
SEATING
L1
D
L
b
e
123
b1
H1
J1
A1
e1
TERM. 4
PLANE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.086 0.094 2.19 2.38 -
A10.018 0.022 0.46 0.55 3, 4
b 0.028 0.032 0.72 0.81 3, 4
b10.033 0.045 0.84 1.14 3
b20.205 0.215 5.21 5.46 3, 4
c 0.018 0.022 0.46 0.55 3, 4
D 0.270 0.295 6.86 7.49 -
E 0.250 0.265 6.35 6.73 -
e 0.090 TYP 2.28 TYP 5
e10.180 BSC 4.57 BSC 5
H10.035 0.045 0.89 1.14 -
J10.040 0.045 1.02 1.14 6
L 0.355 0.375 9.02 9.52 -
L10.075 0.090 1.91 2.28 2
NOTES:
1. These dimensions are within allowable dimensions of Rev. C of
JEDEC TO-251AA outline dated 9-88.
2. Solder finish uncontrolled in this area.
3. Dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder plating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bot-
tom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bot-
tom of dimension D.
7. Controlling dimension: Inch.
8. Revision 3 dated 1-00.