TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 D D D D D D D D D 100 120 150 200 250 ns ns ns ns ns 16-Bit Output For Use in Microprocessor-Based Systems Very High-Speed SNAP! Pulse Programming Power-Saving CMOS Technology 3-State Output Buffers 400-mV Minimum DC Noise Immunity With Standard TTL Loads Latchup Immunity of 250 mA on All Input and Output Pins No Pullup Resistors Required Low Power Dissipation - Active . . . 275 mW Worst Case - Standby . . . 0.55 mW Worst Case (CMOS-Input Levels) Temperature Range Options PIN NOMENCLATURE A0 - A15 DQ0 - DQ15 E G GND NC PGM VCC VPP Address Inputs Inputs (programming) / Outputs Chip Enable Output Enable Ground No Internal Connection Program 5-V Power Supply 13-V Power Supply DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 G 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 VCC PGM NC A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 FN PACKAGE ( TOP VIEW ) 6 5 DQ12 DQ11 DQ10 DQ9 DQ8 GND NC DQ7 DQ6 DQ5 DQ4 4 3 PGM NC A15 A14 '27C/PC210A-10 '27C/ PC210A-12 '27C/ PC210A-15 '27C/ PC210A-20 '27C/ PC210A-25 1 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5 18 19 20 21 22 23 24 25 26 27 28 G NC A0 A1 A2 A3 A4 D D D VPP E DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 GND DQ13 DQ14 DQ15 E VPP NC VCC D J PACKAGE ( TOP VIEW ) Organization . . . 65 536 by 16 Bits Single 5-V Power Supply Operationally Compatible With Existing Megabit EPROMs 40-Pin Dual-In-Line Package and 44-Lead Plastic Leaded Chip Carrier All Inputs / Outputs Fully TTL Compatible 10% VCC Tolerance Maximum Access / Minimum Cycle Time DQ3 DQ2 DQ1 DQ0 D D D Pins 11 and 30 (J package) and pins 12 and 34 (FN package) must be connected externally to ground. Only in program mode Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 1 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 description The TMS27C210A series are 65 536 by 16-bit (1 048 576-bit), ultraviolet-light erasable, electrically programmable read-only memories (EPROMs). The TMS27PC210A series are 65 536 by 16-bit (1 048 576-bit), one-time programmable (OTP) electrically programmable read-only memories (PROMs). These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs ( including program data inputs) can be driven by Series 74 TTL circuits without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external resistors. The TMS27C210A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C210A is offered with two choices of temperature ranges, 0C to 70C (JL suffix) and - 40C to 85C (JE suffix). See Table 1. The TMS27PC210A OTP PROM is offered in a 44-pin plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing ( FN suffix). The TMS27PC210A is offered with two choices of temperature ranges, 0C to 70C ( FNL suffix) and -40C to 85C ( FNE suffix). See Table 1. Table 1. Temperature Range Suffixes EPROM AND OTP PROM SUFFIX FOR OPERATING FREE-AIR TEMPERATURE RANGES 0C to 70C - 40C to 85C TMS27C210A-xx JL JE TMS27PC210A-xx FNL FNE These EPROMs and OTP PROMs operate from a single 5-V supply ( in the read mode), they are ideal for use in microprocessor based systems. One other (13 V) supply is needed for programming. All programming signals are TTL level. For programming outside the system, existing EPROM programmers can be used. operation The seven modes of operation for the TMS27C210A and TMS27PC210A are listed in Table 2. The read mode requires a single 5-V supply. All inputs are TTL level except for VPP during programming (13 V), and 12 V on A9 for signature mode. 2 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 Table 2. Operation Modes MODE FUNCTION E READ OUTPUT DISABLE STANDBY PROGRAMMING VERIFY PROGRAM INHIBIT SIGNATURE MODE VIH X VIL VIH VIL VIL VIL VIH X VIL VIL VIH VPP X X VCC VCC G VIL VIL PGM X VIL VIH X VPP VCC A9 VCC VCC VCC VCC VCC VCC X X A0 X X X X VPP VCC X VCC X VPP VCC X X X X X VH VIL VH VIH CODE DQ0 - DQ15 Data Out Hi-Z Hi-Z Data In Data Out Hi-Z MFG DEVICE 97 AB X can be VIL or VIH. VH = 12 V 0.5 V. read/output disable When the outputs of two or more TMS27C210As or TMS27PC210As are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from competing outputs of the other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other devices in the circuit must have their outputs disabled by applying a high level signal to one of these pins. latchup immunity Latchup immunity on the TMS27C210A and TMS27PC210A is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced to industry standard TTL or MOS logic devices. The input / output layout approach controls latchup without compromising performance or packing density. For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the HVCMOS EPROM Family", available through TI Sales Offices. power down Active ICC supply current can be reduced from 50 mA to 500 A by applying a high TTL input on E and to 100 A by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state. erasure (TMS27C210A) Before programming, the TMS27C210A is erased by exposing the chip through the transparent lid to a high intensity ultraviolet light (wavelength 2537 A). The recommended minimum exposure dose (UV intensity x exposure time) is 15-W*s / cm2. A typical 12-mW / cm2, filterless UV lamp erases the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C210A the window should be covered with an opaque label. initializing (TMS27PC210A) The OTP TMS27PC210A PROM is provided with all bits in the logic high state then logic lows are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 3 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 SNAP! Pulse programming The TMS27C210A and TMS27PC210A are programmed using the TI SNAP! Pulse programming algorithm (shown in the flow chart in Figure 1), which can program in a nominal time of seven seconds. Actual programming time varies as a function of the programmer used. The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (s) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-s pulses per byte are provided before a failure is recognized. The programming mode is achieved when VPP = 13 V, VCC = 6.5 V, E = VIL, G = VIH. Data is presented in parallel (16 bits) on pins DQ0 through DQ15. Once addresses and data are stable, PGM is pulsed low. More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with VCC = VPP = 5 V 10%. program inhibit Programming can be inhibited by maintaining a high level input on the E or PGM pins. program verify Programmed bits can be verified with VPP = 13 V when G = VIL, E = VIL, and PGM = VIH. signature mode The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. DQ0 - DQ7 contain the valid codes. All other addresses must be held low. The signature code for these devices is 97AB. A0 low selects the manufacturer's code 97 ( Hex), and A0 high selects the device code AB (Hex), as shown in Table 3. Table 3. Signature Mode IDENTIFIER PINS A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Manufacturer Code 1 1 97 Device Code 1 1 AB VIL 1 0 0 1 0 1 VIH 1 0 1 0 1 0 E = G = VIL, A9 = VH, A1 - A8 = VIL, A10 - A15 = VIL, VPP = VCC, PGM = VIH or VIL. 4 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 HEX TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 Start Address = First Location VCC = 6.5 V 0.25 V, VPP = 13 V 0.25 V Program Mode Program One Pulse = tw = 100 s Last Address? Increment Address No Yes Address = First Location X=0 Program One Pulse = tw = 100 s No Increment Address Verify One Byte Fail X=X+1 X = 10? Interactive Mode Pass No Last Address? Yes Yes VCC = VPP = 5 V 0.5 V Compare All Bytes to Original Data Device Failed Fail Final Verification Pass Device Passed Figure 1. SNAP! Pulse Programming Flowchart POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 5 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 logic symbol EPROM 65 536 x 16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 E 21 0 22 A 19 23 A 18 24 A 17 25 A 16 26 A 15 27 A 14 28 A 13 A 12 A 10 32 A 9 33 A 8 34 A 7 35 A 6 36 A 5 37 A 4 A 3 29 A 31 2 0 65 535 15 [PWR DWN] & G 20 EN This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12. 6 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 14 V Input voltage range (see Note 1): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to VCC + 1 V A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 13.5 V Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to VCC + 1 V Operating free-air temperature range ('27C210A-_ _JL, '27PC210A-_ _FNL) . . . . . . . . . . . . . . 0 C to 70C Operating free-air temperature range ('27C210A-_ _JE, '27PC210A-_ _FNE) . . . . . . . . . . . . - 40 C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. recommended operating conditions TMS27C/PC210A-10 TMS27C / PC210A-12 TMS27C / PC210A-15 TMS27C / PC210A-20 TMS27C / PC210A-25 Read mode (see Note 2) UNIT MIN NOM MAX 4.5 5 5.5 6.25 6.5 6.75 VCC Supply voltage VPP Supply voltage VIH High level dc input voltage High-level VIL Low level dc input voltage Low-level TA Operating free-air temperature '27C210A-_ _JL '27PC210A-_ _FNL 0 70 C TA Operating free-air temperature '27C210A-_ _JE, '27PC210A-_ _FNE - 40 85 C SNAP! Pulse programming algorithm Read mode SNAP! Pulse programming algorithm TTL CMOS TTL CMOS VCC - 0.6 12.75 2 VCC - 0.2 - 0.5 - 0.5 VCC 13 V VCC+0.6 13.25 V VCC+0.5 VCC+0.5 V 0.8 GND+0.2 V NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted into or removed from the board when VPP or VCC is applied. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 7 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 electrical characteristics over recommended ranges of operating conditions PARAMETER TEST CONDITIONS MIN MAX UNIT VOH High level dc output voltage High-level IOH = - 20 A IOH = - 2 mA VOL Low level dc output voltage Low-level IOL = 2.1 mA IOL = 20 A 0.4 II IO Input current (leakage) VI = 0 V to 5.5 V VO = 0 V to VCC 1 A Output current (leakage) 1 A IPP1 IPP2 VPP supply current VPP supply current (during program pulse) VPP = VCC = 5.5 V VPP = 13 V 10 A 50 mA TTL-input level ICC1 VCC supply current (standby) CMOS-input level ICC2 VCC supply current (active) VCC - 0.2 2.4 V V 0.1 VCC = 5.5 V, VCC = 5.5 V, E = VIH 500 E = VCC 100 VCC = 5.5 V, E = VIL, tcycle = minimum cycle time, outputs open 50 A mA Minimum cycle time = maximum address access time. capacitance over recommended temperature, f = 1 MHz ranges of PARAMETER CI supply voltage and TEST CONDITIONS Input capacitance operating MIN VI = 0 V, f = 1 MHz VO = 0 V, f = 1 MHz CO Output capacitance Capacitance measurements are made on a sample basis only. Typical values are at TA = 25C and nominal voltages. free-air TYP MAX 8 12 pF 12 15 pF UNIT switching characteristics over full ranges of recommended operating conditions (see Notes 3 and 4) PARAMETER TEST CONDITIONS '27C210A-10 '27PC210A-10 MIN MAX '27C210A-12 '27PC210A-12 MIN MAX '27C210A-15 '27PC210A-15 MIN MAX '27C210A-20 '27PC210A-20 MIN MAX '27C210A-25 '27PC210A-25 MIN UNIT MAX ta(A) Access time from address 100 120 150 200 250 ns ta(E) Access time from chip enable 100 120 150 200 250 ns ten(G) Output enable time from G 55 55 75 75 100 ns tdis Output disable time from G or E, whichever occurs first 60 ns tv(A) Output data valid time after change of address, E, or G, whichever occurs first CL = 100 pF, 1 Series 74 TTL load, Input tr 20 ns, Input tf 20 ns 0 50 0 0 0 50 0 0 60 0 0 60 0 0 ns Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested. NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low (see Figure 2). 4. Common test conditions apply for tdis except during programming. 8 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 switching characteristics for programming: VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25C (see Note 3) PARAMETER tdis(G) ten(G) Output disable time from G MIN MAX UNIT 0 100 ns 150 ns Output enable time from G NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low (See Figure 2). timing requirements for programming SNAP! Pulse programming algorithm MIN NOM MAX UNIT 95 100 105 s tw(PGM) tsu(A) Pulse duration, program Setup time, address 2 s tsu(E) tsu(G) Setup time, E 2 s Setup time, G 2 s tsu(D) tsu(VPP) Setup time, data 2 s Setup time, VPP 2 s tsu(VCC) th(A) Setup time, VCC 2 s Hold time, address 0 s th(D) Hold time, data 2 s NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low (See Figure 2). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 9 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 PARAMETER MEASUREMENT INFORMATION 2.08 V RL = 800 Output Under Test CL = 100 pF (see Note A) 2.4 V 2V 0.8 V 0.4 V 2V 0.8 V NOTES: A. CL includes probe and fixture capacitance. B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs and outputs. Figure 2. The ac Testing Output Load Circuit and ac Waveform VIH A0 - A15 Addresses Valid VIL VIH E VIL ta(E) VIH G ten(G) ta(A) VIL tdis tv(A) VOH DQ0 - DQ15 Output Valid Hi-Z Hi-Z VOL Figure 3. Read-Cycle Timing 10 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 PROGRAMMING INFORMATION Verify Program A0 - A15 Address N+1 Address Stable tsu(A) DQ0 - DQ15 VIH VIL th(A) VIH / VOH Data-Out Valid Data-In Stable VIL / VOL tdis(G) tsu(D) VPP VPP VCC tsu(VPP) VCC VCC VCC tsu(VCC) VIH E VIL th(D) tsu(E) VIH PGM VIL tsu(G) tw(PGM) ten(G) VIH G VIL tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer. 13-V VPP and 6.5-V VCC for SNAP! Pulse programming. Figure 4. Program-Cycle Timing (SNAP! Pulse Programming) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 11 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 14 8 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 12 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 J (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE 24 PIN SHOWN B 13 24 C 12 1 Lens Protrusion 0.010 (0,25) MAX 0.065 (1,65) 0.045 (1,14) 0.090 (2,29) 0.060 (1,53) 0.018 (0,46) MIN 0.175 (4,45) 0.140 (3,56) A Seating Plane 0- 10 0.125 (3,18) MIN 0.022 (0,56) 0.014 (0,36) 0.100 (2,54) A B C 28 24 PINS** NARR DIM 0.012 (0,30) 0.008 (0,20) NARR WIDE 32 WIDE NARR 40 WIDE NARR WIDE MAX 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) MIN 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) MAX 1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53) MIN 1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61) MAX 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) MIN 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 4040084 / B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 13 TMS27C210A 65536 BY 16-BIT UV ERASABLE TMS27PC210A 65536 BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES SMLS310D- NOVEMBER 1990 - REVISED SEPTEMBER 1997 14 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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