SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm,
Stratum 3, Elite Platform™ Precision Super-TCXO
Description
The SiT5357 is a ±100 ppb precision MEMS Super-TCXO
that is fully compliant to Telcordia GR-1244-CORE Stratum
3 oscillator specifications. Engineered for best dynamic
performance, the SiT5357 is ideal for high reliability
telecom, wireless and networking, industrial, precision
GNSS and audio/video applications.
Leveraging SiTime’s unique DualMEMS™ temperature
sensing and TurboCompensation™ technologies, the
SiT5357 delivers the best dynamic performance for timing
stability in the presence of environmental stressors such as
air flow, temperature perturbation, vibration, shock, and
electromagnetic interference. This device also integrates
multiple on-chip regulators to filter power supply noise,
eliminating the need for a dedicated external LDO.
The SiT5357 offers three device configurations that can be
ordered using Ordering Codes for:
The SiT5357 can be factory programmed for any
combination of frequency, stability, voltage, and pull range.
Programmability enables designers to optimize clock
configurations while eliminating long lead times and
customization costs associated with quartz devices where
each frequency is custom built.
Refer to Manufacturing Guideline for proper reflow profile
and PCB cleaning recommendations to ensure best
performance.
Features
◼ Output 60–189 MHz, and 208–220 MHz, in 1 Hz steps
◼ Factory programmable options for short lead time
◼ Best dynamic stability under airflow, thermal shock
▪ ±100 ppb stability across temperature
▪ ±1 ppb/C typical frequency slope (ΔF/ΔT)
▪ 1.5e-11 ADEV at 10 second averaging time
◼ -40°C to +105°C operating temperature
◼ No activity dips or micro jumps
◼ Resistant to shock, vibration and board bending
◼ On-chip regulators eliminate the need for external LDOs
◼ 2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage
◼ LVCMOS output
◼ Digital frequency pulling (DCTCXO) via I2C
▪ Digital control of output frequency and pull range
▪ Up to ±3200 ppm pull range
▪ Frequency pull resolution down to 5 ppt
◼ 2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage
◼ LVCMOS output
◼ RoHS and REACH compliant
◼ Pb-free, Halogen-free, Antimony-free
Applications
◼ 4G/5G radio, Small cell
◼ IEEE1588 boundary and grandmaster clocks
◼ Synchronous Ethernet
◼ Optical transport – SONET/SDH, OTN, Stratum 3
◼ DOCSIS 3.x remote PHY
◼ Precision GNSS systems
◼ Test and measurement
Block Diagram
Figure 1. SiT5357 Block Diagram
5.0 mm x 3.2 mm Package Pinout
OE / VC / NC 1
2
3
456
7
8
910
SCL / NC
NC
GND
NC
NC
VDD
CLK
A0 / NC
SDA / NC
Figure 2. Pin Assignments (Top view)
(Refer to Table 11 for Pin Descriptions)
Rev 1.06
May 10, 2020
www.sitime.com
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 2 of 37
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Ordering Information
The part number guide illustrated below is for reference only, in which boxes identify order codes having more than one option.
To customize and build an exact part number, use the SiTime Part Number Generator. To validate the part number, use the
SiTime Part Number Decoder.
Frequency Stability
"Q": for ±0.1 ppm
"P": for ±0.2 ppm
"N": for ±0.25 ppm
Part Family
Silicon Revision Letter
Pull Range – DCTCXO mode only
"T": ±6.25 ppm
"R": ±10 ppm
"Q": ±12.5 ppm
"M": ±25 ppm
"B": ±50 ppm
"C": ±80 ppm
"E": ±100 ppm
"F": ±125 ppm
"G": ±150 ppm
"H": ±200 ppm
"X": ±400 ppm
"L": ±600 ppm
"Y": ±800 ppm
"S": ±1200 ppm
"Z": ±1600 ppm
"U": ±3200 ppm
Supply Voltage
"25": 2.5 V ±10%
"28": 2.8 V ±10%
"30": 3.0 V ±10%
"33": 3.3 V ±10%
Pin 1 Function – DCTCXO mode only
"I": Output Enable
"J": No Connect, software OE control
Temperature Range
"I": Industrial, -40 to 85°C
"C": Extended Commercial, -20 to 70°C
"E": Extended Industrial, -40 to 105°C
Package Size "F": 5.0 mm x 3.2 mm Pin 1 Function – TCXO mode only
"E": Output Enable
"N": No Connect
I2C Address Mode – DCTCXO mode only
“0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”, “9”, “A”, “B”,
“C”, “D”, “E”, “F”: Order code representing hex
value of I2C address. When the I2C address is
factory programmed using this code, pin A0 is no
connect (NC).
“G”: I2C pin addressable mode. Address is set by
the logic on A0 pin.
Packaging
"T": 12 mm Tape & Reel, 3 ku reel
"Y": 12 mm Tape & Reel, 1 ku reel
“X”: 12 mm Tape & Reel, 250 u reel
(blank): bulk[2]
Frequency
60.000001 MHz to 189.000000 MHz
208.000000 MHz to 220.000000 MHz
Output Waveform "-" : LVCMOS[1]
SiT5357AC - FQ - 33 E 0 - 98.123456 T
SiT5357AC - FQ - 33 V T - 98.123456 T
SiT5357AC - FQG33 J R - 98.123456 T
TCXO
VCTCXO
DCTCXO
Notes:
1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in Table 1 (Electrical Characteristics). Contact SiTime for other rise/fall time
options for best EMI or driving multiple loads. For differential outputs, contact SiTime.
2. Bulk is available for sampling only.
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 3 of 37
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TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features ....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics .............................................................................................................................................................. 4
Device Configurations and Pin-outs ............................................................................................................................................. 9
Pin-out Top Views................................................................................................................................................................. 9
Test Circuit Diagrams for LVCMOS Outputs .............................................................................................................................. 10
Waveforms ................................................................................................................................................................................. 11
Timing Diagrams ........................................................................................................................................................................ 11
Stability Diagrams ...................................................................................................................................................................... 11
Typical Performance Plots ......................................................................................................................................................... 12
Architecture Overview ................................................................................................................................................................ 15
Frequency Stability ............................................................................................................................................................. 15
Output Frequency and Format ............................................................................................................................................ 15
Output Frequency Tuning ................................................................................................................................................... 15
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 16
Device Configurations ................................................................................................................................................................ 16
TCXO Configuration ........................................................................................................................................................... 16
VCTCXO Configuration ...................................................................................................................................................... 17
DCTCXO Configuration ...................................................................................................................................................... 18
VCTCXO-Specific Design Considerations ................................................................................................................................. 19
Linearity .............................................................................................................................................................................. 19
Control Voltage Bandwidth ................................................................................................................................................. 19
FV Characteristic Slope KV ................................................................................................................................................. 19
Pull Range, Absolute Pull Range ........................................................................................................................................ 20
DCTCXO-Specific Design Considerations ................................................................................................................................. 21
Pull Range and Absolute Pull Range .................................................................................................................................. 21
Output Frequency ............................................................................................................................................................... 22
I2C Control Registers .......................................................................................................................................................... 24
Register Descriptions .......................................................................................................................................................... 24
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 24
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 25
Register Address: 0x02. DIGITAL PULL RANGE CONTROL[18] ........................................................................................ 26
Serial Interface Configuration Description .......................................................................................................................... 27
Serial Signal Format ........................................................................................................................................................... 27
Parallel Signal Format ........................................................................................................................................................ 28
Parallel Data Format ........................................................................................................................................................... 28
I2C Timing Specification ...................................................................................................................................................... 30
I2C Device Address Modes ................................................................................................................................................. 31
Schematic Example ............................................................................................................................................................ 32
Dimensions and Patterns ........................................................................................................................................................... 33
Layout Guidelines ...................................................................................................................................................................... 34
Manufacturing Guidelines .......................................................................................................................................................... 34
Additional Information ................................................................................................................................................................ 35
Revision History ......................................................................................................................................................................... 36
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 4 of 37
www.sitime.com
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3V Vdd.
Table 1. Output Characteristics
Parameters
Min.
Typ.
Max.
Unit
Condition
Frequency Coverage
Nominal Output Frequency Range
60.000001
–
189
MHz
208
–
220
MHz
Temperature Range
Operating Temperature Range
-20
–
+70
°C
Extended Commercial, ambient temperature
-40
–
+85
°C
Industrial, ambient temperature
-40
–
+105
°C
Extended Industrial, ambient temperature
Frequency Stability - Stratum 3+ Grade
Frequency Stability over
Temperature
–
–
±0.1
ppm
Referenced to (max frequency + min frequency)/2 over the
rated temperature range, in TCXO, DCTCXO, or VCTCXO
(VCTCXO with ±6.25 ppm pull range, Vc=Vdd/2)
Initial Tolerance
–
–
±0.3
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
Supply Voltage Sensitivity
–
±0.7
±3.6
ppb
Vdd ±5%
Output Load Sensitivity
–
±0.2
±1.5
ppb
15 pF ±10%
Frequency vs. Temperature Slope
–
±0.9
±2
ppb/°C
0.5°C/min temperature ramp rate, -20 to 85°C
–
±1
±3.5
ppb/°C
0.5°C/min temperature ramp rate, -40 to -20°C
–
±0.9
±3.3
ppb/°C
0.5°C/min temperature ramp rate, 85 to 105°C
Dynamic Frequency Change during
Temperature Ramp
–
±0.008
±0.02
ppb/s
0.5°C/min temperature ramp rate, -20 to 85°C
–
±0.01
±0.035
ppb/s
0.5°C/min temperature ramp rate, -40 to -20°C
–
±0.008
±0.028
ppb/s
0.5°C/min temperature ramp rate, 85 to 105°C
24-hour holdover Stability
–
–
±0.15
ppm
Inclusive of frequency variation due to temperature, ±10%
supply variation, ±1.5 pF load variation and 24-hour aging
Hysteresis Over Temperature
–
±25
±42
ppb
-40 to 105°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 13, contact SiTime for lower hysteresis
–
±15
±27
ppb
-40 to 85°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 13, contact SiTime for lower hysteresis
–
±10
±20
ppb
-20 to 70°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 13, contact SiTime for lower hysteresis
One-Day Aging
–
±0.5
±2.0
ppb
At 85°C, after 30-days of continued operation. Aging is
measured with respect to day 31.
One-Year Aging
–
±57
±230
ppb
At 85°C, after 2-days of continued operation. Aging is
measured with respect to day 3.
5-Year Aging
–
±73
±320
ppb
10-Year Aging
–
±80
±360
ppb
20-Year Aging
–
±87
±400
ppb
Allan deviation
–
1.5e-11
–
–
10 second averaging time [3]
Frequency Stability - Stratum 3 Grade
Initial Tolerance
–
–
±1
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
Supply Voltage Sensitivity
–
±4.7
±10.4
ppb
Vdd ±5%
Output Load Sensitivity
–
±1.3
±4.2
ppb
15 pF ±10%
Frequency Stability over
Temperature
–
–
±0.2
ppm
Referenced to (max frequency + min frequency)/2 over the
rated temperature range. Vc=Vdd/2 for VCTCXO
–
–
±0.25
ppm
Frequency vs. Temperature Slope
–
±6.4
±10
ppb/°C
-40 to 105°C
Dynamic Frequency Change during
Temperature Ramp
–
±0.05
±0.08
ppb/s
0.5°C/min temperature ramp rate
24-hour holdover Stability
–
–
±0.28
ppm
Inclusive of frequency variation due to temperature, ±10%
supply variation, ±1.5 pF load variation and 24-hour aging
One-Day Aging
–
±3
±5
ppb
At 25°C, after 30-days of continued operation. Aging is
measured with respect to day 31
One-Year Aging
–
±1
–
ppm
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
20-Year Aging
–
±2
–
ppm
20-Year Total Stability
–
–
±4.6
ppm
Complies with Stratum 3, per GR-1244-CORE. Actual
performance is better
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 5 of 37
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Table 1. Output Characteristics (continued)
Parameters
Min.
Typ.
Max.
Unit
Condition
LVCMOS Output Characteristics
Duty Cycle
45
–
55
%
60 to 150 MHz
42
–
55
%
150 to 189 MHz, 200 to 220 MHz
Rise/Fall Time
0.8
1.2
1.9
ns
10% - 90% Vdd
Output Voltage High
90%
–
–
Vdd
IOH = +3 mA
Output Voltage Low
–
–
10%
Vdd
IOL = -3 mA
Output Impedance
–
17
–
Ohms
Impedance looking into output buffer, Vdd = 3.3 V
–
17
–
Ohms
Impedance looking into output buffer, Vdd = 3.0 V
–
18
–
Ohms
Impedance looking into output buffer, Vdd = 2.8 V
–
19
–
Ohms
Impedance looking into output buffer, Vdd = 2.5 V
Start-up Characteristics
Start-up Time
–
2.5
3.5
ms
Time to first pulse, measured from the time Vdd reaches
90% of its final value. Vdd ramp time = 100 µs from 0 V to
Vdd
Output Enable Time
–
–
285
ns
See Timing Diagrams section below
Time to Rated Frequency Stability
–
5
45
ms
Time to first accurate pulse within rated stability, measured
from the time Vdd reaches 90% of its final value. Vdd
ramp time = 100 µs
Note:
3. Measured 2 hours after startup in a temperature chamber with a constant temperature in still air.
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 6 of 37
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Table 2. DC Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Supply Voltage
Supply Voltage
Vdd
2.25
2.5
2.75
V
Contact SiTime for 2.25 V to 3.63 V continuous supply
voltage support
2.52
2.8
3.08
V
2.7
3.0
3.3
V
2.97
3.3
3.63
V
Current Consumption
Current Consumption
Idd
–
48
62
mA
F_nom = 100 MHz, No Load, TCXO and DCTCXO modes
–
52
66
mA
F_nom = 100 MHz, No Load, VCTCXO mode
OE Disable Current
I_od
–
45
52
mA
OE = GND, output weakly pulled down. TCXO, DCTCXO
–
49
56
mA
OE = GND, output weakly pulled down. VCTCXO mode
Table 3. Input Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Input Characteristics – OE Pin
Input Impedance
Z_in
75
–
–
kΩ
Internal pull up to Vdd
Input High Voltage
VIH
70%
–
–
Vdd
Input Low Voltage
VIL
–
–
30%
Vdd
Frequency Tuning Range – Voltage Control or I2C mode
Pull Range
PR
±6.25
–
–
ppm
VCTCXO mode. Contact SiTime for ±12.5 and ±25 ppm
±6.25
±10
±12.5
±25
±50
±80
±100
±125
±150
±200
±400
±600
±800
±1200
±1600
±3200
–
–
ppm
DCTCXO mode
Absolute Pull Range[4]
APR
±5.31
–
–
ppm
±0.1 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±3.05
–
–
ppm
±0.2 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±3.00
–
–
ppm
±0.25 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
Upper Control Voltage
VC_U
90%
–
–
Vdd
VCTCXO mode
Lower Control Voltage
VC_L
–
–
10%
Vdd
VCTCXO mode
Control Voltage Input Impedance
VC_z
8
–
–
MΩ
VCTCXO mode
Control Voltage Input Bandwidth
VC_bw
–
10
–
kHz
VCTCXO mode; contact SiTime for other bandwidth options
Frequency Control Polarity
F_pol
Positive
VCTCXO mode
Pull Range Linearity
PR_lin
–
0.5
1.0
%
VCTCXO mode
I2C Interface Characteristics, 200 Ohm, 550 pF (Max I2C Bus Load)
Bus Speed
F_I2C
≤ 400
kHz
Over rated frequency range (F_rated)
≤ 1000
kHz
Over operating frequency range (F_oper)
Input Voltage Low
VIL_I2C
–
–
30%
Vdd
DCTCXO mode
Input Voltage High
VIH_I2C
70%
–
–
Vdd
DCTCXO mode
Output Voltage Low
VOL_I2C
–
–
0.4
V
DCTCXO mode
Input Leakage current
IL
0.5
–
24
µA
0.1 VDD< VOUT < 0.9 VDD. Includes typical leakage current
from 200 kΩ pull resister to VDD. DCTCXO mode
Input Capacitance
CIN
–
–
5
pF
DCTCXO mode
Note:
4. PR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to Table 14 for APR with respect to other pull range options.
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 7 of 37
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Table 4. Jitter & Phase Noise, -40°C to 85°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.48
ps
F_nom = 100 MHz, Integration bandwidth = 12 kHz to 20 MHz
RMS Period Jitter
T_jitt_per
–
1.0
1.8
ps
F_nom = 100 MHz, population 10 k
Peak Cycle-to-Cycle Jitter
T_jitt_cc
–
6.6
13.4
ps
F_nom = 100 MHz, population 1 k, measured as absolute
value
Phase Noise
1 Hz offset
–
-61
-54
dBc/Hz
F_nom = 100 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
–
-89
-83
dBc/Hz
100 Hz offset
–
-107
-103
dBc/Hz
1 kHz offset
–
-128
-124
dBc/Hz
10 kHz offset
–
-133
-131
dBc/Hz
100 kHz offset
–
-133
-130
dBc/Hz
1 MHz offset
–
-150
-146
dBc/Hz
5 MHz offset
–
-157
-151
dBc/Hz
10 MHz offset
–
-157
-152
dBc/Hz
20 MHz offset
–
-159
-152
dBc/Hz
Spurious
T_spur
–
-91
-86
dBc
F_nom = 100 MHz, 1 kHz to 40 MHz offsets
Table 5. Jitter & Phase Noise, -40°C to 105°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Phase Jitter (random)
T_phj
–
0.31
0.50
ps
F_nom = 100 MHz, Integration bandwidth = 12 kHz to 20 MHz
RMS Period Jitter
T_jitt_per
–
1.0
1.8
ps
F_nom = 100 MHz, population 10 k
Peak Cycle-to-Cycle Jitter
T_jitt_cc
–
6.6
13.4
ps
F_nom = 100 MHz, population 1 k, measured as absolute
value
Phase Noise
1 Hz offset
–
-61
-54
dBc/Hz
F_nom = 100 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
10 Hz offset
–
-89
-83
dBc/Hz
100 Hz offset
–
-107
-103
dBc/Hz
1 kHz offset
–
-128
-124
dBc/Hz
10 kHz offset
–
-133
-131
dBc/Hz
100 kHz offset
–
-133
-130
dBc/Hz
1 MHz offset
–
-150
-144
dBc/Hz
5 MHz offset
–
-157
-150
dBc/Hz
10 MHz offset
–
-157
-150
dBc/Hz
20 MHz offset
–
-159
-150
dBc/Hz
Spurious
T_spur
–
-91
-85
dBc
F_nom = 100 MHz, 1 kHz to 40 MHz offsets
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 8 of 37
www.sitime.com
Table 6. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Test Conditions
Value
Unit
Storage Temperature
-65 to 125
°C
Continuous Power Supply Voltage Range (Vdd)
-0.5 to 4
V
Human Body Model (HBM) ESD Protection
JESD22-A114
2000
V
Soldering Temperature (follow standard Pb-free soldering guidelines)
260
°C
Junction Temperature[5]
130
°C
Input Voltage, Maximum
Any input pin
Vdd + 0.3
V
Input Voltage, Minimum
Any input pin
-0.3
V
Note:
5. Exceeding this temperature for an extended period of time may damage the device.
Table 7. Thermal Considerations[6]
Package
JA[7] (°C/W)
JC, Bottom (°C/W)
Ceramic 5.0 mm x 3.2 mm
54
15
Note:
6. Measured in still air. Refer to JESD51 for θJA and θJC definitions.
7. Devices soldered on a JESD51 2s2p compliant board.
Table 8. Maximum Operating Junction Temperature[8]
Max Operating Temperature (ambient)
Maximum Operating Junction Temperature
70°C
80°C
85°C
95°C
105°C
115°C
Note:
8. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 9. Environmental Compliance
Parameter
Test Conditions
Value
Unit
Mechanical Shock Resistance
MIL-STD-883F, Method 2002
30000
g
Mechanical Vibration Resistance
MIL-STD-883F, Method 2007
70
g
Temperature Cycle
JESD22, Method A104
–
–
Solderability
MIL-STD-883F, Method 2003
–
–
Moisture Sensitivity Level
MSL1 @260°C
–
–
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 9 of 37
www.sitime.com
Device Configurations and Pin-outs
Table 10. Device Configurations
Configuration
Pin 1
Pin 5
I2C Programmable Parameters
TCXO
OE/NC
NC
–
VCTCXO
VC
NC
–
DCTCXO
OE/NC
A0/NC
Frequency Pull Range, Frequency Pull Value, Output Enable control.
Pin-out Top Views
OE/NC 1
2
3
456
7
8
910
NC
NC
GND
NC
NC
VDD
CLK
NC
NC
Figure 3. TCXO
VC 1
2
3
456
7
8
910
NC
NC
GND
NC
NC
VDD
CLK
NC
NC
Figure 4. VCTCXO
OE / NC 1
2
3
456
7
8
910
SCL
NC
GND
NC
NC
VDD
CLK
A0 / NC
SDA
Figure 5. DCTCXO
Table 11. Pin Description
Pin
Symbol
I/O
Internal Pull-up/Pull Down
Resistor
Function
1
OE/NC[11]/VC
OE – Input
100 kΩ Pull-Up
H[9]: specified frequency output
L: output is high impedance. Only output driver is disabled.
No Connect
–
H or L or Open: No effect on output frequency or other device functions
VC – Input
–
Control Voltage in VCTCXO Mode
2
SCL / NC[11]
SCL – Input
200 kΩ Pull-Up
I2C serial clock input.
No Connect
H or L or Open: No effect on output frequency or other device functions
3
NC[11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
4
GND
Power
–
Connect to ground
5
A0 / NC[11]
A0 – Input
100 kΩ Pull-Up
Device I2C address when the address selection mode is via the A0 pin.
This pin is NC when the I2C device address is specified in the ordering
code.
A0 Logic Level I2C Address
0 1100010
1 1101010
NC – No Connect
–
H or L or Open: No effect on output frequency or other device functions.
6
CLK
Output
–
LVCMOS
7
NC[11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
8
NC[11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
9
VDD
Power
–
Connect to power supply[10]
10
SDA / NC[11]
SDA – Input/Output
200 kΩ Pull Up
I2C Serial Data.
NC – No Connect
–
H or L or Open: No effect on output frequency or other device functions.
Notes:
9. In OE mode for noisy environments, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use
the NC option.
10. A 0.1 μF capacitor in parallel with a 10 μF capacitor are required between VDD and GND. The 0.1 μF capacitor is recommended to place close to the
device, and place the 10 μF capacitor less than 2 inches away.
11. All NC pins can be left floating and do not need to be soldered down.
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 10 of 37
www.sitime.com
Test Circuit Diagrams for LVCMOS Outputs
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Vdd
OE Function
CLK
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
10µF
0.1µF
+
-
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Control
Voltage
VC Function
CLK
15pF
(including probe
and fixture
capacitance)
Figure 6. LVCMOS Test Circuit (OE Function)
Figure 7. LVCMOS Test Circuit (VC Function)
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Any state
or floating
NC Function
CLK
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
Figure 8. LVCMOS Test Circuit (NC Function)
9 8 7 6
1 2 3 4
510
Power
Supply
VDD Test Point
Any state
or floating NC
Function
CLK
SCL
SDA[11]
15pF
(including probe
and fixture
capacitance)
10µF
0.1µF
+
-
A0/NC
Figure 9. LVCMOS Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements
Note:
12. SDA is open-drain and may require pull-up resistor if not present in I2C test setup.
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 11 of 37
www.sitime.com
Waveforms
90 % Vdd
50 % Vdd
10 % Vdd
tr tf
High Pulse
(TH) Low Pulse
(TL)
Period
Figure 10. LVCMOS Waveform Diagram[13]
Note:
13. Duty Cycle is computed as Duty Cycle = TH/Period.
Timing Diagrams
90% Vdd Vdd
Vdd Pin
Voltage
CLK Output
T_start
T_start: Time to start from power-off
HZ
Figure 11. Startup Timing
50% Vdd
Vdd
OE Voltage
CLK Output
T_oe
T_oe: Time to re-enable the clock output
HZ
Figure 12. OE Enable Timing (OE Mode Only)
Stability Diagrams
Figure 13. Illustration of hysteresis, where ΔF is max
frequency difference between up and down cycles
across temperature
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 12 of 37
www.sitime.com
Typical Performance Plots
Figure 14. ADEV (±0.1 ppm) [14]
Figure 15. TDEV (0.1 Hz loop bandwidth, ±0.1 ppm) [14]
Figure 16. MTIE (0.1 Hz loop bandwidth, ±0.1 ppm) [14]
Figure 17. Frequency vs Temperature (±0.1 ppm), 105°C
Figure 18. Freq. vs. Temp. Slope (ΔF/ΔT), ±0.1 ppm device
Figure 19. VCTCXO frequency pull characteristic
Figure 20. 1-day aging rate after 30 days, 0.1 ppm device
Figure 21. Frequency drift after 30 days [15]
1E-11
1E-10
110 100 1000
Allan Deviation
Time (s)
Breezy Air Still Air
1E-12
1E-11
1E-10
1E-09
1E-08
0.033 0.33 3.3 33 330
TDEV (s)
Averaging time (s)
Breezy Air Still Air ITU-T G.8262, EEC2
1E-11
1E-10
1E-09
1E-08
1E-07
0.33 3.3 33 330 3300
MTIE (s)
Observation interval (s)
Breezy Air Still Air ITU-T G.8262, EEC2
-100
-50
0
50
100
-40 -20 0 20 40 60 80 100
Frequency deviation (ppb)
Temperature (°C)
2.5 3.3
-2.5
-1.5
-0.5
0.5
1.5
2.5
-40 -20 0 20 40 60 80 100
Frequency vs. Temperature
Slope (ppb/°C)
Temperature (°C)
2.5 V 3.3 V
-10
-8
-6
-4
-2
0
2
4
6
8
10
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Frequency deviation (ppm)
Control Voltage (V)
-5
-4
-3
-2
-1
0
1
2
3
4
5
30 35 40 45 50 55 60
Aging rate (ppb/day)
Day
-50
-40
-30
-20
-10
0
10
20
30
40
50
30
Frequency drift (ppb)
Day
605040
SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Rev 1.06
Page 13 of 37
www.sitime.com
Typical Performance Plots (continued)
Figure 22. Load sensitivity (±0.1 ppm)
Figure 23. VDD sensitivity (±0.1 ppm)
Figure 24. Duty Cycle (LVCMOS)
Figure 25. IDD DCTCXO (LVCMOS)
Figure 26. IDD TCXO (LVCMOS)
Figure 27. IDD VCTCXO (LVCMOS)
Figure 28. RMS Phase Jitter, DCTCXO, TCXO (LVCMOS)
Figure 29. RMS Period Jitter (LVCMOS)
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.25
-10 -5 0 5 10
Frequency sensitivity (ppb)
Load variation (%)
2.5 V 3.3 V
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-10 -5 0 5 10
Frequency sensitivity (ppb)
Power supply voltage variation (%)
2.5 V 3.3 V
45
47
49
51
53
55
70 90 110 130 150 170 190 210
Duty cycle (%)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
40
42
44
46
48
50
52
54
56
58
70 90 110 130 150 170 190 210
Current consumption (mA)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
40
42
44
46
48
50
52
54
56
58
70 90 110 130 150 170 190 210
Current consumption (mA)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
46
48
50
52
54
56
58
60
70 90 110 130 150 170 190 210
Current consumption (mA)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
0
100
200
300
400
500
70 90 110 130 150 170 190 210
Phase Jitter (fs RMS)
Frequency (MHz)
2.5 V 2.8 V 3.0 V 3.3 V
0.50
0.70
0.90
1.10
1.30
1.50
1.70
1.90
70 90 110 130 150 170 190 210
Period Jitter (ps MS)
Frequency (MHz)
2.5 V 3.3 V