Integrated Circuit Systems, Inc. ICS951703 Frequency Generator & Integrated Buffers for Celeron & PII/IIITM Block Diagram 2 48MHz (2:1) VCH_CLK XTAL OSC PLL1 Spread Spectrum REF VDDREF X1 X2 GND GND 3V66-0 3V66-1 3V66-2 VDD3V66 PCI_STOP# PCICLK_F PCICLK1 GND PCICLK2 PCICLK3 VDDPCI PCICLK4 PCICLK5 PCICLK6 GND AVDD AGND GND 48MHz_1 48MHz_2 VDD48 FS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND IOPAIC-0 IOAPIC-1 VDDL CPU0 VDDL CPU1 CPU2 GND GND SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 SDRAM_F VDDSDR VCH_CLK VDD CPU_STOP# FS2 PD# SCLK SDATA FS1 56-Pin 300-mil SSOP and TSSOP Functionality PLL2 X1 X2 Pin Configuration ICS951703 Recommended Application: Mobile applications Output Features: * 3 CPU (2.5V) (100MHz) * 7 SDRAM (3.3V) (1 free running SDCLK) (100MHz) * 7 PCI (3.3 V) @ 33.3MHz, (1 free running) * 2 IOAPIC (2.5V) @ 33.3 MHz * 2 (3.3V) @ 48 MHz - 1 USB clock (3.3V) (48MHz non-SSC) - 1 DOT clock (3.3V) (48MHz non-SSC) * 1 VCH clock (3.3V) 48 MHz non-SSC, or 66 MHz CPU-SSC * 3 3V66 (3.3V) (66MHz) * 1 REF (3.3V) @ 14.318 MHz Features: * Supports spread spectrum modulation, 0 to -0.5% down spread. * Support power management: PCI_STOP#, CPU_STOP# and power down Mode * I2C interface for clock output control Skew Specifications: * CPU-CPU <150psec * PCI-PCI <500psec * SDRAM-SDRAM <250psec * CPU-SDRAM <350psec * CPU-PCI 1-4nsec * CPU-3V66 1-4nsec REF CPU DIVDER Stop SDRAM DIVDER I2C Stop FS2 FS1 FS0 0 0 X X 0 1 1 0 1 CPUCLK 0 2 6 Function Tristate Test Active CPU = 100MHz SDRAM = 100MHz CPUCLK (2:1) SDRAM (5:0) SDRAM_F SDATA SCLK Control Logic IOAPIC DIVDER 2 IOAPIC (1:0) FS (2:0) PD# PCI_STOP# CPU_STOP# Config. PCI DIVDER Stop 7 PCICLK (6:1) PCICLK_F Reg. 3V66 DIVDER 3 951703 Rev B 10/29/01 Third party brands and names are the property of their respective owners. 3V66 (2:0) Power Groups VDD48= 48MHz, PLL2 AVDD = Analog VDD for CPU PLL VDDREF = REF, Xtal Osc. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS951703 General Description The ICS9250-31 is a single chip clock solution for mobile applications, providing all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-31 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Pin Configuration PIN NUMBER 1 3 4 5, 6, 14, 21, 23, 24, 41, 47, 48, 56 9, 8, 7 2, 10, 17, 22, 27, 35, 37, 44 P I N NA M E TYPE DESCRIPTION REF X1 X2 OUT IN OUT 3.3V, 14.318MHz reference clock output. Crystal input. Crystal output. GND PWR Ground 3V66 (2:0) OUT 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B VDD PWR 3.3V power supply 11 P C I _ S TO P # IN 12 20, 19, 18, 16, 15, 13 25 PCICLK_F OUT Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low Free running 3.3V PCI clock output not affected by PCI_STOP# PCICLK (6:1) OUT 3.3V PCI clock outputs 48MHz_1 OUT 26 48MHz_2 OUT 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s f o r U S B 3 . 3 V fi x e d 4 8 M H z c l o c k o u t p u t . S t r o n g e r o u t p u t f o r g r a p h i c s / v i d e o interface (DOT) (minimum 1V/ns edge rate) Function Select pins. Determines CPU frequency, all output functionality. Please refer to Functionality table on page 3. Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Stops CPUCLK[0] at logic 0 level, when input low. CPUCLK(2:1) are not affected. 3.3V selectable 48MHz non-SSC or 66.67MHz SSC clock output. 33, 29, 28 FS (2:0) IN 30 31 SDATA SCLK I/O IN 32 PD# IN 34 C P U _ S TO P # IN 36 39, 40, 42, 43, 45, 46 38 49,50,52 51, 53 54, 55 VCH_CLK OUT SDRAM (5:0) OUT SDRAM_F OUT 3.3V output running 100MHz. All SDRAM outputs can be turned off through I2C 3.3V free running 100MHz SDRAM, cannot be turned off through I2C CPUCLK (2:0) OUT 2.5V Host bus clock output 100MHz depending on FS (2:0) pins. VDDL IOAPIC (1:0) PWR OUT 2.5V power supply for CPU & IOAPIC 2.5V clock outputs running at 33.3MHz. 2 ICS951703 Maximum Allowed Current Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 2.625V All static inputs = Vddq3 or GND Condition Max 3.3V supply consumption Max discrete cap loads, Vddq2 = 3.465V All static inputs = Vddq3 or GND Powerdown Mode (PWRDWN# = 0) 1mA 1mA Full Active 66MHz FS[1:0] = 00 60mA 170mA Full Active 100MHz FS[1:0] = 01 75mA 170mA Full Active 133MHz FS[1:0] = 10 90mA 170mA CPU to SDRAM @ 133MHz FS[1:0] = 11 90mA 185mA Clock Enable Configuration PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK VCH REF, 48MHz Osc VCOs 0 LOW LOW LOW LOW LOW LOW LOW OFF OFF 1 ON ON ON ON ON ON ON ON ON Functionality Table FS2 FS1 FS0 CPU MHz SDRAM MHz 3V66 MHz PCI MHz 48MHz REF MHz IOAPIC MHz Tristate 0 X 0 Tristate Tristate Tristate Tristate Tristate Tristate 0 X 1 TCLK/2 TCLK/2 TCLK/3 TCLK/6 TCLK/2 TCLK TCLK/6 1 0 1 100 100 66 33 48 14.318 33 3 ICS951703 Byte 0: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Pin# 36 49 50 52 Bit 3 <> Bit 2 Bit 1 Bit 0 26 25 - Name VCH_CLK CPU2 CPU1 CPU0 Spread Spectrum (1=enabled) 48MHz_2 48MHz_1 Reserved PWD 1 1 1 1 Description (Active/Inactive)* (Active/Inactive) (Active/Inactive) (Active/Inactive) 1 (Active/Inactive) 1 1 0 (Active/Inactive) (Active/Inactive) (Active/Inactive) PWD 0 0 1 1 1 1 1 1 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) PWD 1 1 1 0 0 0 0 0 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Notes: Reserved bits must be wirtten as "0". *Readback of the bit is always "0". Byte 1: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 39 40 42 43 45 46 Name Reserved Reserved SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Byte 2: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 9 8 7 - Name 3V66-2 3V66-1 3V66-0 Reserved Reserved Reserved Reserved Reserved Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 3. Undefined bit can be wirtten with either a "1" or "0". 4 ICS951703 Byte 3: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 18 16 15 13 - Name PWD 0 1 1 1 1 1 1 Reserved PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 Reserved 0 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Byte 4: Control Register (1 = enable, 0 = disable) Bit Pin# Bit 7 36 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - Name PWD VCH_CLK 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 Description 0 = 48MHz non-SSC 1 = 66MHz SSC (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 5 ICS951703 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Timing Relationship Table1 Group CPU 100MHz SDRAM 100MHz Offset Tolerance CPU to SDRAM CPU to 3V66 0.0ns 1-4ns 350ps 3V66 to PCI 0.0ns 500ps CPU to PCI 1-4ns Electrical Characteristics - Input/Supply/Common Output Parameters T A = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%(unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX Input High Voltage VIH 2 VDD+0.3 VSS-0.3 0.8 Input Low Voltage VIL VIN = VDD -5 5 Input High Current IIH IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 Input Low Current VIN = 0 V; Inputs with pull-up resistors -200 IIL2 Operating Supply IDD3.3OP CPU=SD=100MHz 230 250 Current for 3.3V Power down Current IDD3.3PD 0.085 1 for 3.3V Operating Supply IDD2.5OP CPU=SD=100MHz 32 50 Current for 2.5V Power down Current IDD2.5PD 1 10 for 2.5V Input Frequency VDD = 3.3 V 14.318 Fi 7 Pin Inductance Lpin Logic Inputs 5 CIN Output pin capacitance 6 COUT Input Capacitance1 X1 & X2 pins 27 45 CINX Transition time1 1 Settling time Clk Stabilization1 Delay1 1 Ttrans Ts TSTAB tPZH,tPZL tPHZ,tPLZ UNITS V V A A A mA mA mA A MHz nH pF pF pF To 1st crossing of target frequency 3 ms From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency Output enable delay (all outputs) Output disable delay (all outputs) 3 3 10 10 ms ms ns ns Guaranteed by design, not 100% tested in production. 6 1 1 ICS951703 Electrical Characteristics - CPU T A = 0 - 70C; VDDL=2.5V +/-5% ; CL = 10-20 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance RD SP 2B 1 Output Impedance Output High Voltage Ou tput Low Voltage Output High Current Ou tput Low Current RD SN 2B VO H 2B VO L 2B IO H 2 B IO L 2 B Ris e Time t r2 B Fall Time Duty Cycle Skew Jitter 1 SYM BOL t f2B 1 1 1 d t2 B 1 t s k2B 1 t jcyc-cy c 1 CONDITIONS M IN TYP VO = VD D *(0.5) 13.5 27 45 VO = VD D *(0.5) IO H = -1 mA IO L = 1 mA V O H @ MIN = 1.0 V, V O H @ MA X = 2.375 V VO L @ MIN = 1.2 V, VO L @ M A X = 0.3 V 13.5 2 27 45 0.4 -27 30 V V mA mA VO L = 0.4 V, VO H = 2.0 V 0.4 0.94 1.6 ns VO H = 2.0 V, VO L = 0.4 V 0.4 1.07 1.6 ps VT = 1.25 V 45 50.6 55 % VT = 1.25 V 74 150 ps VT = 1.25 V 180 250 ps -27 27 M AX UNITS Guaranteed by des ign, not 100% tes ted in production. Electrical Characteristics - 3V66 T A = 0 - 70C; VDD=3.3V +/-5% ; CL = 10-30 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance RD SP 1 1 Output Impedance RD SN 1 Output High Voltage VO H Ou tput Low Voltage Output High Current Ou tput Low Current Ris e Time Fall Time Duty Cycle Skew Jitter 1 SYM BOL VO L t r1 t f1 1 1 TYP VO = VD D *(0.5) 12 22 55 VO = VD D *(0.5) 12 22 55 IO H = -1 mA 2.4 0.55 V -33 -33 mA VO L @ MIN = 1.95 V, VO L @ MA X = 0.4 V 30 38 mA VO L = 0.4 V, VO H = 2.4 V 0.5 1.3 2 ns VO H = 2.4 V, VO L = 0.4 V 0.5 1.4 2 ns VT = 1.5 V 45 47.5 55 % VT = 1.5 V 117 175 ps VT = 1.5 V 160 500 ps V O H @ MIN = 1.0 V, V O H @ MA X = 3.135 V 1 1 1 t sk 1 1 t jcyc-cy c 1 M AX UNITS V IO L = 1 mA 1 d t1 M IN 1 IO H IO L 1 CONDITIONS Guaranteed by des ign, not 100% tes ted in production. 7 ICS951703 Electrical Characteristics - IOAPIC T A = 0 - 70C; VDDL=2.5V +/-5% ; CL = 10-20 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance RD SP 2B 1 Output Impedance Output High Voltage Ou tput Low Voltage Output High Current Ou tput Low Current RD SN 2B VO H 2B VO L 2B IO H 2 B IO L 2 B Ris e Time t r2 B Fall Time Duty Cycle 1 SYM BOL t f2B 1 1 1 d t2 B 1 1 Skew t s k2B Jitter t jcyc-cy c 1 CONDITIONS M IN TYP VO = VD D *(0.5) 13.5 27 45 VO = VD D *(0.5) IO H = -1 mA IO L = 1 mA V O H @ MIN = 1.0 V, V O H @ MA X = 2.375 V VO L @ MIN = 1.2 V, VO L @ M A X = 0.3 V 13.5 2 27 45 0.4 -27 30 V V mA mA VO L = 0.4 V, VO H = 2.0 V 0.4 1.1 1.6 ns VO H = 2.0 V, VO L = 0.4 V 0.4 1.15 1.6 ps VT = 1.25 V 45 49.5 55 % VT = 1.25 V 10 250 ps VT = 1.25 V 80 500 ps -27 27 M AX UNITS Guaranteed by des ign, not 100% tes ted in production. Electrical Characteristics - SDRAM T A = 0 - 70C; VDD=3.3V +/-5% ; CL = 10-20 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance Output Impedance Output High Voltage Ou tput Low Voltage Output High Current Ou tput Low Current Ris e Time Fall Time Duty Cycle Skew Jitter 1 SYM BOL RD SP 1 1 RD N P 1 VO H VO L t r1 t f1 1 1 1 1 t sk 1 1 t jcyc-cy c TYP VO = VD D *(0.5) 10 15 24 VO = VD D *(0.5) 10 15 24 IO H = -1 mA 2.4 1 M AX UNITS V 0.4 V O H @ MIN = 2.0 V, V O H @ MA X = 3.135 V 1 1 d t1 M IN IO L = 1 mA 1 IO H IO L 1 CONDITIONS -54 V -46 mA 53 mA VO L @ MIN = 1.0 V, VO L @ M A X = 0.4 V 54 VO L = 0.4 V, VO H = 2.0 V 0.4 1.1 1.6 ns VO H = 2.0 V, VO L = 0.4 V 0.4 1.3 1.6 ns VT = 1.5 V 45 50 55 % VT = 1.5 V 50 250 ps VT = 1.5 V 150 250 ps Guaranteed by des ign, not 100% tes ted in production. 8 ICS951703 Electrical Characteristics - PCI T A = 0 - 70C; VDD=3.3V +/-5% ; CL = 10-30 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance Output Impedance Output High Voltage Ou tput Low Voltage Output High Current Ou tput Low Current Ris e Time Fall Time Duty Cycle Skew Jitter 1 SYM BOL RD SP 1 1 RD SN 1 VO H VO L t r1 t f1 1 1 TYP VO = VD D *(0.5) 12 22 55 VO = VD D *(0.5) 12 22 55 IO H = -1 mA 2.4 0.55 V -33 -33 mA VO L @ MIN = 1.95 V, VO L @ MA X = 0.4 V 30 38 mA VO L = 0.4 V, VO H = 2.4 V 0.5 1.35 2 ns VO H = 2.4 V, VO L = 0.4 V 0.5 1.3 2 ns VT = 1.5 V 45 50.5 55 % VT = 1.5 V 150 500 ps VT = 1.5 V 110 500 ps V O H @ MIN = 1.0 V, V O H @ MA X = 3.135 V 1 1 1 t sk 1 1 t jcyc-cy c 1 M AX UNITS V IO L = 1 mA 1 d t1 M IN 1 IO H IO L 1 CONDITIONS Guaranteed by des ign, not 100% tes ted in production. Electrical Characteristics - REF, 48M Hz T A = 0 - 70C; VDD=3.3V +/-5% ; CL = 10-20 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance Output Impedance Output High Voltage Ou tput Low Voltage Output High Current Ou tput Low Current RD SP 1 VO H VO L IO L 1 1 1 t f1 Duty Cycle d t1 M IN TYP VO = VD D *(0.5) 20 33 60 VO = VD D *(0.5) 20 33 60 IO H = -1 mA 2.4 V O H @ MIN = 1.0 V, V O H @ MA X = 3.135 V 1 VO L @ MIN = 1.95 V, VO L @ MA X = 0.4 V 1 1 t sk 1 1 t jcyc-cy c 0.4 V -29 -23 mA 29 27 mA VO L = 0.4 V, VO H = 2.4V 0.5 1.8 4 ns VO H = 2.4 V, VO L = 0.4 V 0.5 1.75 4 ns VT = 1.5 V 45 51.5 55 % N/A ps 1000 ps VT = 1.5 V 1 M AX UNITS V IO L = 1 mA 1 t r1 CONDITIONS 1 IO H Fall Time Jitter 1 RD SN 1 Ris e Time Skew 1 SYM BOL VT = 1.5 V 600 Guaranteed by des ign, not 100% tes ted in production. 9 ICS951703 Electrical Characteristics - VCH T A = 0 - 70C; VDD=3.3V +/-5% ; CL = 10-30 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance Output Impedance Output High Voltage Ou tput Low Voltage Output High Current Ou tput Low Current Ris e Time Fall Time Duty Cycle Skew Jitter 1 SYM BOL RD SP 1 1 RD SN 1 VO H VO L t r1 t f1 1 1 TYP VO = VD D *(0.5) 12 22 55 VO = VD D *(0.5) 12 22 55 IO H = -1 mA 2.4 0.55 V -33 -33 mA VO L @ MIN = 1.95 V, VO L @ MA X = 0.4 V 30 38 mA VO L = 0.4 V, VO H = 2.4 V 0.5 0.8 2 ns VO H = 2.4 V, VO L = 0.4 V 0.5 1 2 ns VT = 1.5 V 45 50.6 55 % N/A ps 250 ps V O H @ MIN = 1.0 V, V O H @ MA X = 3.135 V 1 1 1 t sk 1 1 t jcyc-cy c VT = 1.5 V 1 M AX UNITS V IO L = 1 mA 1 d t1 M IN 1 IO H IO L 1 CONDITIONS VT = 1.5 V 220 Guaranteed by des ign, not 100% tes ted in production. 10 ICS951703 0ns 10ns 20ns 30ns Cycle Repeats CPU 100MHz SDRAM 100MHz 3.3V 66MHz PCI 33MHz IOAPIC 33MHz REF 14.318MHz USB 48MHz Group Offset Waveforms 11 40ns ICS951703 Power Down Waveform 0ns 25ns 1 50ns 2 VCO Internal CPU 100MHz 3.3V 66MHz PCI 33MHz APIC 33MHz PD# SDRAM 100MHz REF 14.318MHZ 48MHZ Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz 12 ICS951703 CPU_STOP# Timing Diagram CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS951703. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS951703. 3. All other clocks continue to run undisturbed. (including SDRAM outputs). 13 ICS951703 PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS951703. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS951703 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS951703 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS951703. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state. 14 ICS951703 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: * * * * * * * * * * * * * * * * Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 15 ICS951703 c N L E1 INDEX AREA SYMBOL E A A1 b c D E E1 e h L N 1 2 h x 45 D A A1 -Ce SEATING PLANE N .10 (.004) C 56 b In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8 D (inch) MIN .720 MAX .730 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS951703yF-T Example: ICS XXXXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 16 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS951703 c N In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 L E1 INDEX AREA E 1 2 D A A2 A1 -Ce VARIATIONS N SEATING PLANE b 56 aaa C D mm. MIN 13.90 D (inch) MAX 14.10 MIN .547 MAX .555 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information ICS951703yG-T Example: ICS XXXXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 17 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.