Integrated
Circuit
Systems, Inc. ICS951703
Third party brands and names are the property of their respective owners.
Block Diagram
951703 Rev B 10/29/01
Recommended Application:
Mobile applications
Output Features:
• 3 CPU (2.5V) (100MHz)
• 7 SDRAM (3.3V) (1 free running SDCLK) (100MHz)
• 7 PCI (3.3 V) @ 33.3MHz, (1 free running)
• 2 IOAPIC (2.5V) @ 33.3 MHz
• 2 (3.3V) @ 48 MHz
- 1 USB clock (3.3V) (48MHz non-SSC)
- 1 DOT clock (3.3V) (48MHz non-SSC)
• 1 VCH clock (3.3V) 48 MHz non-SSC,
or 66 MHz CPU-SSC
• 3 3V66 (3.3V) (66MHz)
• 1 REF (3.3V) @ 14.318 MHz
Features:
• Supports spread spectrum modulation,
0 to -0.5% down spread.
• Support power management: PCI_STOP#,
CPU_STOP# and power down Mode
•I
2C interface for clock output control
Skew Specifications:
• CPU-CPU <150psec
• PCI-PCI <500psec
• SDRAM-SDRAM <250psec
• CPU-SDRAM <350psec
• CPU-PCI 1-4nsec
• CPU-3V66 1-4nsec
Functionality
Pin Configuration
56-Pin 300-mil SSOP and TSSOP
REF
VDDREF
X1
X2
GND
GND
3V66-0
3V66-1
3V66-2
VDD3V66
PCI_STOP#
PCICLK_F
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
AVDD
AGND
GND
48MHz_1
48MHz_2
VDD48
FS0
GND
IOPAIC-0
IOAPIC-1
VDDL
CPU0
VDDL
CPU1
CPU2
GND
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
SDRAM_F
VDDSDR
VCH_CLK
VDD
CPU_STOP#
FS2
PD#
SCLK
SDATA
FS1
ICS951703
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Power Groups
VDD48= 48MHz, PLL2
AVDD = Analo g VDD for CPU PLL
VDDREF = REF, Xtal Osc.
PLL2
PLL1
Spread
Spectrum
48MHz (2:1)
CPUCLK 0
SDRAM (5:0)
IOAPIC (1:0)
VCH_CLK
PCICLK (6:1)
SDRAM_F
CPUCLK (2:1)
PCICLK_F
3V66 (2:0)
3
7
2
6
2
2
X1
X2 XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
I2C
Stop
Stop
Stop
Control
Logic
Config.
Reg.
REF
SDATA
SCLK
FS (2:0)
PD#
PCI_STOP#
CPU_STOP#
2SF1SF0SFnoitcnuF
0X0 etatsirT
0X1tseT
101 zHM001=UPCevitcA zHM001=MARDS
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS951703
The ICS9250-31 is a single chip clock solution for mobile applications, providing all necessary clock signals for
such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This
simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-31 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
General Description
Pin Configuration
REBMUNNIPEMANNIPEPYTNOITPIRCSED
1FERTUO.tuptuokcolcecnereferzHM813.41,V3.3
31XNI.tupnilatsyrC
42XTUO.tuptuolatsyrC
,32,12,41,6,5 65,84,74,14,42 DNGRWPdnuorG
7,8,9)0:2(66V3TUOBUHrofstuptuokcolczHM66dexiFV3.3
,22,71,01,2 44,73,53,72 DDVRWPylppusrewopV3.3
11#POTS_ICPNI,level0cigoltaskcolcF_KLCICPehtsedisebsKLCICPllaspotS woltupninehw
21F_KLCICPTUO#POTS_ICPybdetceffatontuptuokcolcICPV3.3gninnureerF
,61,81,91,02 31,51 )1:6(KLCICPTUOstuptuokcolcICPV3.3
521_zHM84TUOBSUrofstuptuokcolczHM84dexiFV3.3
622_zHM84TUO oediv/scihpargroftuptuoregnortS.tuptuokcolczHM84dexifV3.3 )etaregdesn/V1muminim()TOD(ecafretni
82,92,33)0:2(SFNI.ytilanoitcnuftuptuolla,ycneuqerfUPCsenimreteD.sniptceleSnoitcnuF .3egapnoelbatytilanoitcnuFotreferesaelP
03ATADSO/IIrofnipataD
2
tnarelotV5yrtiucricC
13KLCSNIIfonipkcolC
2
tnarelotV5yrtiucricC
23#DPNI
otniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA dnaOCVehtdnadelbasideraskcolclanretniehT.etatsrewopwola ebtonlliwnwodrewopehtfoycnetalehT.deppotseralatsyrceht .sm3nahtretaerg
43#POTS_UPCNIera)1:2(KLCUPC.woltupninehw,level0cigolta]0[KLCUPCspotS .detceffaton
63KLC_HCVTUO.tuptuokcolcCSSzHM76.66roCSS-nonzHM84elbatcelesV3.3
,34,24,04,93 64,54 )0:5(MARDSTUO MARDSllA.zHM001gninnurtuptuoV3.3 Ihguorhtffodenrutebnacstuptuo
2
C
83F_MARDSTUO ,MARDSzHM001gninnureerfV3.3 Ihguorhtffodenrutebtonnac
2
C
25,05,94)0:2(KLCUPCTUO.snip)0:2(SFnognidnepedzHM001tuptuokcolcsubtsoHV5.2
35,15LDDVRWPCIPAOI&UPCrofylppusrewopV5.2
55,45)0:1(CIPAOITUO.zHM3.33tagninnurstuptuokcolcV5.2
3
ICS951703
Maximum Allowed Current
Clock Enable Configuration
#DPKLCUPCMARDSCIPAOIzHM66KLCICPHCV ,FER zHM84 csOsOCV
0WOLWOLWOLWOLWOLWOLWOLFFOFFO
1NONONONONONONONONO
Functionality Table
noitidnoC
noitpmusnocylppusV5.2xaM ,sdaolpacetercsidxaM V526.2=2qddV DNGro3qddV=stupnicitatsllA
noitpmusnocylppusV3.3xaM ,sdaolpacetercsidxaM V564.3=2qddV DNGro3qddV=stupnicitatsllA
edoMnwodrewoP )0=#NWDRWP( ≤Am1 ≤Am1
zHM66evitcAlluF 00=]0:1[SF Am06Am071
zHM001evitcAlluF 10=]0:1[SF Am57Am071
zHM331evitcAlluF 01=]0:1[SF Am09Am071
@MARDSotUPC zHM331 11=]0:1[SF Am09Am581
2SF1SF0SF UPC zHM MARDS zHM 66V3 zHM ICP zHM zHM84 FER zHM CIPAOI zHM
0X 0 etatsirTetatsirTetatsirTetatsirTetatsirTetatsirT etatsirT
0X 1 2/KLCT2/KLCT3/KLCT6/KLCT2/KLCTKLCT6/KLCT
10 1 001001663384813.4133
4
ICS951703
Byte 0: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
Byte 2: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
tiB#niPemaNDWPnoitpircseD
7tiB63KLC_HCV1*)evitcanI/evitcA(
6tiB942UPC1)evitcanI/evitcA(
5tiB051UPC1)evitcanI/evitcA(
4tiB250UPC1)evitcanI/evitcA(
3tiB><murtcepSdaerpS )delbane=1( 1)evitcanI/evitcA(
2tiB622_zHM841)evitcanI/evitcA(
1tiB521_zHM841)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
tiB#niPemaNDWPnoitpircseD
7tiB- devreseR0)evitcanI/evitcA(
6tiB- devreseR0)evitcanI/evitcA(
5tiB935MARDS1)evitcanI/evitcA(
4tiB044MARDS1)evitcanI/evitcA(
3tiB243MARDS1)evitcanI/evitcA(
2tiB342MARDS1)evitcanI/evitcA(
1tiB541MARDS1)evitcanI/evitcA(
0tiB640MARDS1)evitcanI/evitcA(
Notes:
Reserved bits must be wirtten as "0".
*Readback of the bit is always "0".
tiB#niPemaNDWPnoitpircseD
7tiB9 2-66V31)evitcanI/evitcA(
6tiB8 1-66V31)evitcanI/evitcA(
5tiB7 0-66V31)evitcanI/evitcA(
4tiB- devreseR0)evitcanI/evitcA(
3tiB- devreseR0)evitcanI/evitcA(
2tiB- devreseR0)evitcanI/evitcA(
1tiB- devreseR0)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
5
ICS951703
Byte 3: Control Register
(1 = enable, 0 = disable)
Byte 4: Control Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPnoitpircseD
7tiB63KLC_HCV0 CSS-nonzHM84=0 CSSzHM66=1
6tiB- devreseR0)evitcanI/evitcA(
5tiB- devreseR0)evitcanI/evitcA(
4tiB- devreseR0)evitcanI/evitcA(
3tiB- devreseR0)evitcanI/evitcA(
2tiB- devreseR0)evitcanI/evitcA(
1tiB- devreseR0)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
tiB#niPemaNDWPnoitpircseD
7tiB- devreseR0)evitcanI/evitcA(
6tiB026KLCICP1)evitcanI/evitcA(
5tiB915KLCICP1)evitcanI/evitcA(
4tiB814KLCICP1)evitcanI/evitcA(
3tiB613KLCICP1)evitcanI/evitcA(
2tiB512KLCICP1)evitcanI/evitcA(
1tiB311KLCICP1)evitcanI/evitcA(
0tiB
-devreseR0
)evitcanI/evitcA(
6
ICS951703
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V DD +0.5 V
Ambient Operating Temperature. . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 1 15°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Group Timing Relationship Table1
puorGzHM001UPC zHM001MARDS
tesffOecnareloT
MARDSotUPCsn0.0sp053
66V3otUPCsn4-1
ICPot66V3sn0.0sp005
ICPotUPCsn4-1
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%(unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Volt a ge VIH 2V
DD+0.3 V
Input Low Voltage VIL VSS-0.3 0.8 V
Input High Current IIH VIN = VDD -5 5 µA
IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 µA
IIL2 VIN = 0 V; Inputs with pull-up resistors -200 µA
Operating Supply
Current f or 3.3V IDD3.3OP CPU=SD=100MHz 230 250 mA
Power do wn Current
for 3.3V IDD3.3PD 0.085 1 mA
Operating Supply
Current f or 2.5V IDD2.5OP CPU=SD=100MHz 32 50 mA
Power do wn Current
for 2.5V IDD2.5PD 110
µA
Input Frequency FiVDD = 3.3 V 14.318 MHz
Pin Inductance L
p
in 7nH
CIN Logic Inputs 5 pF
COUT Output pin capacitance 6 pF
CINX X1 & X2 pins 27 45 pF
Tr ansit ion time1Ttrans To 1st crossing of target frequency 3 ms
Settling time1TsFrom 1st crossing to 1% target frequency 3 ms
Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target frequency 3 ms
tPZH,tPZL Output enable delay (all outputs) 1 10 ns
tPHZ,tPLZ Output disable delay (all outputs) 1 10 ns
1Guaranteed by design, not 100% tested in production.
Input Low Current
Delay1
Input Capacitance1
7
ICS951703
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL=2.5V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP2B1 VO = VDD*(0.5) 13.5 27 45 Ω
Output Impedance RDSN2B1VO = VDD*(0.5) 13.5 27 45 Ω
Output High Voltage VOH2B IOH = -1 mA 2 V
Output Low Voltage VOL2B IOL = 1 mA 0.4 V
Output High Current IOH2B V OH@MIN = 1.0 V, V OH@MAX = 2.375 V -27 -27 mA
Output Low Current IOL2B VOL @M IN = 1.2 V, VOL @MAX = 0.3 V 27 30 mA
Rise Tim e tr2B1VOL = 0.4 V, VOH = 2.0 V 0.4 0.94 1.6 ns
Fall Time tf2 B1VOH = 2.0 V, VOL = 0.4 V 0.4 1.07 1.6 ps
Duty Cycle dt2B1VT = 1.25 V 45 50.6 55 %
Skew tsk2B1VT = 1.25 V 74 150 ps
Jitter tjcyc-cyc1VT = 1.25 V 180 250 ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwis e specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP11VO = VDD*(0.5) 12 22 55 Ω
Output Impedance RDSN11VO = VDD*(0.5) 12 22 55 Ω
Output High Voltage VOH1IOH = -1 mA 2.4 V
Output Low Voltage VOL1IOL = 1 mA 0.55 V
Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA
Output Low Current IOL1VOL @MIN = 1.95 V, VOL @M AX = 0.4 V 30 38 mA
Rise Tim e tr11VOL = 0.4 V, VOH = 2.4 V 0.5 1.3 2 ns
Fall Time tf1 1VOH = 2.4 V, VOL = 0.4 V 0.5 1.4 2 ns
Duty Cycle dt11VT = 1.5 V 45 47.5 5 5 %
Skew tsk11VT = 1.5 V 117 175 ps
Jitter tjcyc-cyc1VT = 1.5 V 160 500 ps
1Guaranteed by design, not 100% tested in production.
8
ICS951703
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL=2.5V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP2B1 VO = VDD*(0.5) 13.5 27 45 Ω
Output Impedance RDSN2B1VO = VDD*(0.5) 13.5 27 45 Ω
Output High Voltage VOH2B IOH = -1 mA 2 V
Output Low Voltage VOL2B IOL = 1 mA 0.4 V
Output High Current IOH2B V OH@MIN = 1.0 V, V OH@MAX = 2.375 V -27 -27 mA
Output Low Current IOL2B VOL @M IN = 1.2 V, VOL @MAX = 0.3 V 27 30 mA
Rise Tim e tr2B1VOL = 0.4 V, VOH = 2.0 V 0.4 1.1 1.6 ns
Fall Time tf2 B1VOH = 2.0 V, VOL = 0.4 V 0.4 1.15 1.6 ps
Duty Cycle dt2B1VT = 1.25 V 45 49.5 55 %
Skew tsk2B1VT = 1.25 V 10 250 ps
Jitter tjcyc-cyc1VT = 1.25 V 80 500 ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwis e specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP11VO = VDD*(0.5) 10 15 24 Ω
Output Impedance RDNP11VO = VDD*(0.5) 10 15 24 Ω
Output High Voltage VOH1IOH = -1 mA 2.4 V
Output Low Voltage VOL1IOL = 1 mA 0.4 V
Output High Current IOH1V OH@MIN = 2.0 V, V OH@MAX = 3.135 V -54 -46 mA
Output Low Current IOL1VOL @MIN = 1.0 V, VOL @MAX = 0.4 V 54 53 mA
Rise Tim e tr11VOL = 0.4 V, VOH = 2.0 V 0.4 1.1 1.6 ns
Fall Time tf1 1VOH = 2.0 V, VOL = 0.4 V 0.4 1.3 1.6 ns
Duty Cycle dt11VT = 1.5 V 45 50 5 5 %
Skew tsk11VT = 1.5 V 50 250 ps
Jitter tjcyc-cyc1VT = 1.5 V 150 250 ps
1Guaranteed by design, not 100% tested in production.
9
ICS951703
Electrical Characteristics - PCI
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP11VO = VDD*(0.5) 12 22 55 Ω
Output Impedance RDSN11VO = VDD*(0.5) 12 22 55 Ω
Output High Voltage VOH1IOH = -1 mA 2.4 V
Output Low Voltage VOL1IOL = 1 mA 0.55 V
Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA
Output Low Current IOL1VOL @MIN = 1.95 V, VOL @M AX = 0.4 V 30 38 mA
Rise Tim e tr11VOL = 0.4 V, VOH = 2.4 V 0.5 1.35 2 ns
Fall Time tf1 1VOH = 2.4 V, VOL = 0.4 V 0.5 1.3 2 ns
Duty Cycle dt11VT = 1.5 V 45 50.5 55 %
Skew tsk11VT = 1.5 V 150 500 ps
Jitter tjcyc-cyc1VT = 1.5 V 110 500 ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP11VO = VDD*(0.5) 20 33 60 Ω
Output Impedance RDSN11VO = VDD*(0.5) 20 33 60 Ω
Output High Voltage VOH1IOH = -1 mA 2.4 V
Output Low Voltage VOL1IOL = 1 mA 0.4 V
Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA
Output Low Current IOL1VOL @MIN = 1.95 V, VOL @M AX = 0.4 V 29 27 mA
Rise Tim e tr11VOL = 0.4 V, VOH = 2.4V 0.5 1.8 4 ns
Fall Time tf1 1VOH = 2.4 V, VOL = 0.4 V 0.5 1.75 4 ns
Duty Cycle dt11VT = 1.5 V 45 51.5 55 %
Skew tsk11VT = 1.5 V N/A ps
Jitter tjcyc-cyc1VT = 1.5 V 600 1000 ps
1Guaranteed by design, not 100% tested in production.
10
ICS951703
Electrical Characteristics - VCH
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP11VO = VDD*(0.5) 12 22 55 Ω
Output Impedance RDSN11VO = VDD*(0.5) 12 22 55 Ω
Output High Voltage VOH1IOH = -1 mA 2.4 V
Output Low Voltage VOL1IOL = 1 mA 0.55 V
Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -33 -33 mA
Output Low Current IOL1VOL @MIN = 1.95 V, VOL @M AX = 0.4 V 30 38 mA
Rise Tim e tr11VOL = 0.4 V, VOH = 2.4 V 0.5 0.8 2 ns
Fall Time tf1 1VOH = 2.4 V, VOL = 0.4 V 0.5 1 2 ns
Duty Cycle dt11VT = 1.5 V 45 50.6 55 %
Skew tsk11VT = 1.5 V N/A ps
Jitter tjcyc-cyc1VT = 1.5 V 220 250 ps
1Guaranteed by design, not 100% tested in production.
11
ICS951703
Group Offset Waveforms
Cycle Repeats
0ns
CPU 100MHz
SDRAM 100MHz
3.3V 66MHz
PCI 33MHz
IOAPIC 33MHz
REF 14.318MHz
USB 48MHz
10ns 20ns 30ns 40ns
12
ICS951703
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
VCO Internal
0ns
12
25ns 50ns
CPU 100MHz
3.3V 66MHz
PCI 33MHz
APIC 33MHz
PD#
SDRAM 100MHz
REF 14.318MHZ
48MHZ
13
ICS951703
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS951703. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clo ck.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS951703.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
14
ICS951703
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS951703. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS951703 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (def ined as inside the ICS951703 de vice.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS951703.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
15
ICS951703
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3(H)
A
C
K
Byte Count
ACK Byte 0
ACK Byte 1
ACK Byte 2
ACK Byte 3
ACK Byte 4
ACK Byte 5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2(H)
A
C
K
Dummy Command Code ACK
Dummy Byte Count
A
C
K
Byte 0 ACK
Byte 1 ACK
Byte 2 ACK
Byte 3 ACK
Byte 4
A
C
K
Byte 5 ACK
Stop Bit
How to Write:
16
ICS951703
INDEX
AREA
INDEX
AREA
12
1 2
N
D
h x 45°
h x 45°
E1 E
SEATING
PLANE
SEATING
PLANE
A1
A
e
-C-
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
α
0° 8° 0° 8°
MIN MAX MIN MAX
56 18.31 18.55 .720 .730
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
SYMBOL In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Ordering Information
ICS951703yF-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package T ype
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device T ype
Prefix
ICS = Standard Device
Example:
ICS XXXXXX y F - PPP - T
17
ICS951703
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil) (0.020 mil)
MIN MAX MIN MAX
A--1.20--.047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa -- 0.10 -- .004
V
ARIATIONS
MIN MAX MIN MAX
56 13.90 14.10 .547 .555
10-0039
SYMBOL In Millimeters In Inches
COMMON DIM ENSI ONS COMMON DI MENSIO NS
SEE VARIATIONS SEE VARIATIONS
8.10 BAS IC 0.319 B ASIC
0.50 BAS IC 0.020 B ASIC
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Ordering Information
ICS951703yG-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package T ype
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device T ype
Prefix
ICS = Standard Device
Example:
ICS XXXXXX y G - PPP - T
