1
FEATURES APPLICATIONS
DESCRIPTION
VIN
NC
NC
ENA
GND
VSENSE
BOOT
PH
TPS5420
VIN VOUT
95
60
70
80
90
100
0 0.5 11.5 2.5 3
Efficiency − %
I OutputCurrent A
O--
EfficiencyvsOutputCurrent
SimplifiedSchematic
2
50
55
65
75
85
VI=12V
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007www.ti.com
2-A, WIDE INPUT RANGE, STEP-DOWN SWIFT™ CONVERTER
•Consumer: Set-top Box, DVD, LCD Displays2
•Wide Input Voltage Range: 5.5 V to 36 V
•Industrial and Car Audio Power Supplies•Up to 2-A Continuous (3-A Peak) Output
•Battery Chargers, High Power LED SupplyCurrent
•12-V/24-V Distributed Power Systems•High Efficiency up to 95% Enabled by 110-m Ω
Integrated MOSFET Switch•Wide Output Voltage Range: Adjustable Downto 1.22 V with 1.5% Initial Accuracy
As a member of the SWIFT™ family of DC/DCregulators, the TPS5420 is a high-output-current•Internal Compensation Minimizes External
PWM converter that integrates a low resistance highParts Count
side N-channel MOSFET. Included on the substrate•Fixed 500-kHz Switching Frequency for Small
with the listed features is a high performance voltageFilter Size
error amplifier that provides tight voltage regulationaccuracy under transient conditions; an•Improved Line Regulation and Transient
undervoltage-lockout circuit to prevent start-up untilResponse by Input Voltage Feed Forward
the input voltage reaches 5.5 V; an internally set•System Protected by Over Current Limiting,
slow-start circuit to limit inrush currents; and a voltageOver Voltage Protection and Thermal
feed-forward circuit to improve the transientShutdown
response. Using the ENA pin, shutdown supply•– 40 °C to 125 °C Operating Junction
current is reduced to 18 μA typically. Other featuresTemperature Range include an active-high enable, overcurrent limiting,overvoltage protection and thermal shutdown. To•Available in Small 8-Pin SOIC Package
reduce design complexity and external component•For SWIFT Documentation, Application Notes
count, the TPS5420 feedback loop is internallyand Design Software, See the TI Website at
compensated.www.ti.com/swift
The TPS5420 device is available in an easy to use8-pin SOIC package. TI provides evaluation modulesand the SWIFT™ Designer software tool to aid inquickly achieving high-performance power supplydesigns to meet aggressive equipment developmentcycles.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SWIFT is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
(1) (2)
RECOMMENDED OPERATING CONDITIONS
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
J
INPUT VOLTAGE OUTPUT VOLTAGE PACKAGE
(1)
PART NUMBER
– 40 °C to 125 °C 5.5 V to 36 V Adjustable to 1.22 V SOIC (D)
(2)
TPS5420D
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) The D package is available taped and reeled. Add an R suffix to the device type (i.e., TPS5420DR).
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE UNIT
VIN – 0.3 to 40
(3)
BOOT – 0.3 to 50PH (steady-state) – 0.6 to 40
(3)
V
I
Input voltage range EN – 0.3 to 7 VVSENSE – 0.3 to 3BOOT-PH 10PH (transient < 10 ns) – 1.2I
O
Source current PH Internally LimitedI
lkg
Leakage current PH 10 μAT
J
Operating virtual junction temperature range – 40 to 150 °CT
stg
Storage temperature – 65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.(3) Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.
THERMAL IMPEDANCEPACKAGE
JUNCTION-TO-AMBIENT
8 Pin D
(3)
75 °C/W
(1) Maximum power dissipation may be limited by overcurrent protection.(2) Power rating at a specific ambient temperature T
A
should be determined with a junction temperature of 125 °C. This is the point wheredistortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at orbelow 125 °C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for moreinformation.
(3) Test board conditions:a. 3 in x 3 in, 2 layers, thickness: 0.062 inch.b. 2 oz. copper traces located on the top and bottom of the PCB.
MIN NOM MAX UNIT
V
I
Input voltage range, VIN 5.5 36 VT
J
Operating junction temperature – 40 125 °C
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ELECTRICAL CHARACTERISTICS
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
T
J
= – 40 °C to 125 °C, VIN = 5.5 V to 36 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VSENSE = 2 V, Not switching, PH pin
3 4.4 mAopenI
Q
Quiescent current
Shutdown, ENA = 0 V 18 50 μA
UNDERVOLTAGE LOCK OUT (UVLO)
Start threshold voltage, UVLO 5.3 5.5 VHysteresis voltage, UVLO 330 mV
VOLTAGE REFERENCE
T
J
= 25 °C 1.202 1.221 1.239Voltage reference accuracy VI
O
= 0 A – 2 A 1.196 1.221 1.245
OSCILLATOR
Internally set free-running frequency 400 500 600 kHzMinimum controllable on time 150 200 nsMaximum duty cycle 87% 89%
ENABLE (ENA PIN)
Start threshold voltage, ENA 1.3 VStop threshold voltage, ENA 0.5 VHysteresis voltage, ENA 450 mVInternal slow-start time (0 ~ 100%) 6.6 8 10 ms
CURRENT LIMIT
Current limit 3 4 5 ACurrent limit hiccup time 13 16 20 ms
THERMAL SHUTDOWN
Thermal shutdown trip point 135 162 °CThermal shutdown hysteresis 14 °C
OUTPUT MOSFET
VIN = 5.5 V 150r
DS(on)
High side power MOSFET switch m ΩVIN = 10 V - 36 V 110 230
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PIN ASSIGNMENTS
1
2
3
4
8
7
6
5
BOOT
NC
NC
VSENSE
PH
VIN
GND
ENA
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
D PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTIONNAME NO.
BOOT 1 Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH pin.NC 2, 3 Not connected internally.VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider.ENA 5 On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.GND 6 Ground.
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramicVIN 7
capacitor.PH 8 Source of the high side power MOSFET. Connected to external inductor and diode.
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TYPICAL CHARACTERISTICS
-50 -25 0 25 125
T − JunctionTemperature − C
J
o
1007550
V =12V
I
3
3.5
3.25
I OperatingQuiescentCurrent − mA
Q−
2.5
2.75
460
-50 -25 0 25 125
T − JunctionTemperature − C
J
o
1007550
460
470
530
500
520
510
fOscillatorFrequency − kHz
−
480
490
120
180
150
170
160
MinimumControllableOnTime − ns
130
140
-50 -25 0 25 125
T − JunctionTemperature − C
J
o
1007550
-50 -25 0 25 125
T − JunctionTemperature − C
J
o
1007550
1.22
1.23
1.225
V VoltageReference − V
ref −
1.21
1.215
1.22
1.23
1.225
V VoltageReference − V
ref −
1.21
1.215
V =12V
I
-50 -25 0 25 125
T − JunctionTemperature − C
J
o
1007550
80
180
150
170
160
r On-StateResistance − m
DS(on) W−
90
120
130
140
100
110
8
9
8.5
tInternalSlowStartTime − ms
SS −
7
7.5
-50 -25 0 25 125
T − JunctionTemperature − C
J
o
1007550
7.5
8
7.5
MinimumDutyRatio − %
7
7.25
-50 -25 0 25 125
T − JunctionTemperature − C
J
o
1007550
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
OSCILLATOR FREQUENCY OPERATING QUIESCENT CURRENT MINIMUM CONTROLLABLE ON TIMEvs vs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2. Figure 3.
VOLTAGE REFERENCE ON STATE RESISTANCE INTERNAL SLOW START TIMEvs vs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 4. Figure 5. Figure 6.
MINIMUM CONTROLLABLE DUTYSHUTDOWN QUIESCENT CURRENT RATIOvs vsINPUT VOLTAGE JUNCTION TEMPERATURE
Figure 7. Figure 8.
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APPLICATION INFORMATION
FUNCTIONAL BLOCK DIAGRAM
VIN
UVLO
ENABLE
Thermal
Protection
Reference
Overcurrent
GateDrive
Oscillator
Ramp
Generator
VREF
PH
ENA
GND
SHDN
SHDN
BOOT
Z1
Z2SHDN
SHDN
SHDN
SHDN
VIN
SHDN
HICCUP
HICCUP
SHDN
SHDN
NC
FeedForward
BOOT
NC
VIN
VOUT
5 µA
1.221VBandgap SlowStart Boot
Regulator
Error
Amplifier
Gain=25
PWM
Comparator
Protection
Gate
Driver
Control
VSENSE
112.5%VREF
VSENSE OVP
DETAILED DESCRIPTION
Oscillator Frequency
Voltage Reference
Enable (ENA) and Internal Slow Start
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switchingfrequency allows less output inductance for the same output ripple requirement resulting in a smaller outputinductor.
The voltage reference system produces a precision reference signal by scaling the output of a temperaturestable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of1.221 V at room temperature.
The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the thresholdvoltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulledbelow the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pinto ground or to any voltage less than 0.5 V disables the regulator and activate the shutdown mode. Thequiescent current of the TPS5420 in shutdown mode is typically 18 μA.
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Undervoltage Lockout (UVLO)
Boost Capacitor (BOOT)
Output Feedback (VSENSE)
Internal Compensation
Voltage Feed Forward
FeedForwardGain= VIN
Ramppk-pk
(1)
Pulse-Width-Modulation (PWM) Control
Overcurrent Limiting
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an applicationrequires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limitthe start-up inrush current, an internal slow start circuit is used to ramp up the reference voltage from 0 V to itsfinal value linearly. The internal slow start time is 8 ms typically.
The TPS5420 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the inputvoltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and theinternal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO startthreshold voltage is reached, the internal slow start is released and device start-up begins. The device operatesuntil VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
Connect a 0.01 μF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides thegate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stablevalues over temperature.
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor dividernetwork to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltagereference 1.221 V.
The TPS5420 implements internal compensation to simplify the regulator design. Since the TPS5420 usesvoltage mode control, a type 3 compensation network has been designed on chip to provide a high crossoverfrequency and a high phase margin for good stability. See the Internal Compensation Network in the applicationssection for more details.
The internal voltage feed forward provides a constant DC power stage gain despite any variations with the inputvoltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forwardvaries the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain areconstant at the feed forward gain, i.e.
The typical feed forward gain of TPS5420 is 25.
The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedbackvoltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier andcompensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by thePWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle.Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. Thedrain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If thedrain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The systemwill ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid anyturn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off forthe rest of the cycle after a propagation delay. The overcurrent limiting scheme is called cycle-by-cycle currentlimiting.
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Overvoltage Protection
Thermal Shutdown
PCB Layout
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happenwhen using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e. hiccup modeovercurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-sideMOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts undercontrol of the slow start circuit.
The TPS5420 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering fromoutput fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltageand a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-sideMOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-sideMOSFET will be enabled again.
The TPS5420 protects itself from overheating with an internal thermal shutdown circuit. If the junctiontemperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-sideMOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junctiontemperature drops 14 °C below the thermal shutdown trip point.
Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop areaformed by the bypass capacitor connections, the VIN pin, and the TPS5420 ground pin. The best way to do thisis to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypasscapacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7 μF ceramicwith a X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC to connect the GND pin of the deviceand the anode of the catch diode. The GND pin should be tied to the PCB ground by connecting it to the groundarea under the device as shown in Figure 9 .
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection isthe switching node, the inductor should be located close to the PH pin, and the area of the PCB conductorminimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device tominimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin asshown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The componentplacements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep theloop formed by the PH pin, Lout, Cout and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do notroute this trace too close to the PH trace. Due to the size of the IC package and the device pinout, the trace mayneed to be routed under the output capacitor. The routing may be done on an alternate layer if a trace under theoutput capacitor is not desired.
If the grounding scheme shown is used via a connection to a different layer to route to the ENA pin.
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BOOT
NC
NC
VSENSE
PH
VIN
GND
ENA
VOUT
PH
Vin
TOPSIDEGROUND AREA
VIA toGroundPlane
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
CATCH
DIODE
SignalVIA
Routefeedback
traceundertheoutput
filtercapacitororon
theotherlayer.
RESISTOR
DIVIDER
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
Figure 9. Design Layout
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Alldimensionsininches
0.220
0.050
0.026
0.080
Application Circuits
10V-35V
L1
33 Hm
GND VSNS
VIN
NC
NC
ENA BOOT
PH
C4
4.7 FmD1
B340A
C2
0.01 Fm
R2
3.24kW
R1
10kW
VIN
+
C1
4.7 Fm
U1
TPS5420D TP5
5V
7
1
5
8
2
4
3
6
VOUT
C3
100 Fm
(SeeNote A)
ENA
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
Figure 10. TPS5420 Land Pattern
Figure 11 shows the schematic for a typical TPS5420 application. The TPS5420 can provide up to 2-A outputcurrent at a nominal output voltage of 5 V.
A. C3 = Tantalum AVX TPSD107M010R0080
Figure 11. Application Circuit, 10-V — 35 V to 5-V
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Design Procedure
DVIN =
()
IOUT(MAX) x0.25
+IOUT(MAX) MAX
xESR
CBULK SW
xƒ
(2)
ICIN +
IOUT(MAX)
2
(3)
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
The following design procedure can be used to select component values for the TPS5420. Alternately, theSWIFT™ Designer Software may be used to generate a complete design. The SWIFT™ Designer Software usesan iterative design procedure and accesses a comprehensive database of components when generating adesign. This section presents a simplified discussion of the design process.
To begin the design process, a few parameters must be determined. The designer must know the following:•Input voltage range•Output voltage•Input ripple voltage•Output ripple voltage•Output current rating•Operating frequency
Design Parameters
For this design example, use the following as the input parameters:DESIGN PARAMETER
(1)
EXAMPLE VALUE
Input voltage range 10 V to 36 VOutput voltage 5 VInput ripple voltage 300 mVOutput ripple voltage 30 mVOutput current rating 2 AOperating frequency 500 kHz
(1) As an additional constraint, the design is set up to be small size and low component height.
Switching Frequency
The switching frequency for the TPS5420 is internally set to 500 kHz. It is not possible to adjust the switchingfrequency.
Input Capacitors
The TPS5420 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.The recommended value for the decoupling capacitor is 10 μF. A high quality ceramic type X5R or X7R isrequired. For some applications, a smaller value decoupling capacitor may be used, if the input voltage andcurrent ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,including ripple. For this design, two 4.7 μF capacitors, C1 and C4 are used to allow for smaller 1812 case sizeto be used while maintaining a 50 V rating.
This input ripple voltage can be approximated by Equation 2 :
Where I
OUT(MAX)
is the maximum load current, f
SW
is the switching frequency, C
I
is the input capacitor value andESR
MAX
is the maximum series resistance of the input capacitor.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this is approximated byEquation 3 :
In this example, the calculated input ripple voltage is 118 mV, and the RMS ripple current is 1.0 A. The maximumvoltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitorsare rated for 50 V, and the ripple current capacity for each is 3 A at 500 kHz, providing ample margin. The actualmeasured input ripple voltage may be larger than the calculated value due to the output impedance of the inputvoltage source and parasitics associated with the layout.
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LMIN =
()
VOUT IN(MAX) OUT
xV -V
VIN(max) IND OUT SW
xK xI xF x0.8
(4)
IL(RMS) +I2
OUT(MAX))1
12 ǒVOUT ǒVIN(MAX)*VOUTǓ
VIN(MAX) LOUT FSW 0.8Ǔ2
Ǹ
(5)
IL(PK) =I +
OUT(MAX)
()
V V V
OUT IN(MAX) OUT
x -
1.6 xV xL xF
IN(MAX) OUT SW
(6)
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
CAUTION:
The maximum ratings for voltage and current are not to be exceeded under anycircumstance.
Additionally, some bulk capacitance may be needed, especially if the TPS5420 circuit is not located withinapproximately 2 inches from the input voltage source. The value for this capacitor is not critical but it should berated to handle the maximum input voltage including ripple voltage and should filter the output so that input ripplevoltage is acceptable.
Output Filter Components
Two components need to be selected for the output filter, L1 and C2. Since the TPS5420 is an internallycompensated device, a limited range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 4 :
K
IND
is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.Three things need to be considered when determining the amount of ripple current in the inductor: the peak topeak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current,and the amount of ripple current determines at what point the circuit becomes discontinuous. For designs usingthe TPS5420, K
IND
of 0.2 to 0.3 yields good results. Low output ripple voltages is obtained when paired with theproper output capacitor, the peak switch current is below the current limit set point, and low load currents can besourced before discontinuous operation.
For this design example, use K
IND
= 0.2, and the minimum inductor value is 27 μH. The standard value used inthis design is 33 μH.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.The RMS inductor current can be found from Equation 5 :
and the peak inductor current can be determined using Equation 6 :
For this design, the RMS inductor current is 2.002 A, and the peak inductor current is 2.16 A. The choseninductor is a Coilcraft MSS1260-333 type. The nominal inductance is 33 μH. It has a saturation current rating of2.2 A and a RMS current rating of 2.7 A, which meets the requirements. Inductor values for use with theTPS5420 are in the range of 10 μH to 100 μH.
Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalentseries resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is importantbecause along with the inductor ripple current it determines the amount of output ripple voltage. The actual valueof the output capacitor is not critical, but some practical limits do exist. Consider the relationship between thedesired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to the
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fCO +fLC2
85 VOUT
(7)
COUT +1
3357 LOUT fCO VOUT
(8)
ESRMAX +1
2p COUT fCO
(9)
VPP(MAX)=
()
ESR xV V V
MAX OUT IN(MAX) OUT
x -
NC IN(MAX) OUT SW
xV xL xF x0.8
(10)
1x
ICOUT(RMS) =Ö12
[ ]
VOUT IN(MAX) OUT
xV -V
VIN(MAX) OUT SW
xL -F x0.8xNC
()
(11)
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
design of the internal compensation, it is recommended to keep the closed loop crossover frequency in the range3 kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this designexample, the intended closed loop crossover frequency is between 2590 Hz and 24 kHz, and below the ESRzero of the output capacitor. Under these conditions, the closed loop crossover frequency is related to the LCcorner frequency as:
and the desired output capacitor value for the output filter to:
For a desired crossover of 18 kHz and a 33- μH inductor, the calculated value for the output capacitor is 100 μF.The capacitor type should be chosen so that the ESR zero is above the loop crossover. The maximum ESR is:
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initialdesign parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable outputripple voltage:
Where:
ΔV
PP
is the desired peak-to-peak output ripple.N
C
is the number of parallel output capacitors.F
SW
is the switching frequency.
The minimum ESR of the output capacitor should also be considered. For a good phase margin, if the ESR iszero when the ESR is at its minimum, it should not be above the internal compensation poles at 24 kHz and54 kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus onehalf the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in theoutput capacitor is given by Equation 11 :
Where:
N
C
is the number of output capacitors in parallel.F
SW
is the switching frequency.
For this design example, a single 100- μF output capacitor is chosen for C3. The calculated RMS ripple current is143 mA and the maximum ESR required is 88 m Ω. A capacitor that meets these requirements is a AVXTPSD107M010R0080, rated at 10 V with a maximum ESR of 80 m Ωand a ripple current rating of 1.369 A. Thiscapacitor results in a peak-to-peak output ripple of 26 mV using equation 10. An additional small 0.1- μF ceramicbypass capacitor may also used, but is not included in this design.
Other capacitor types can be used with the TPS5420, depending on the needs of the application.
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS5420
www.ti.com
R2 +R1 1.221
VOUT *1.221
(12)
+
10V-21V
L1
27 Hm
GND
VSNS
NC
NC
ENA
BOOT
PH D1
B340A
C2
0.01 Fm
R2
3.24kW
R1
10kW
VIN
C1
10 Fm
U1
TPS5420D TP5
5V
7
1
5
8
2
4
3
6
VOUT
VIN
ENA
C3
100 Fm
(SeeNote A)
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
Output Voltage Setpoint
The output voltage of the TPS5420 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.Calculate the R2 resistor value for the output voltage of 5 V using Equation 12 :
For any TPS5420 design, start with an R1 value of 10 k Ω. R2 is then 3.24 k Ω.
Boot Capacitor
The boot capacitor should be 0.01 μF.
Catch Diode
The TPS5420 is designed to operate using an external catch diode between PH and GND. The selected diodemust meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximumvoltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half thepeak-to-peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to notethat the catch diode conduction time is typically longer than the high-side FET on time; therefore, the diodeparameters improve the overall efficiency. Additionally, check that the device chosen is capable of dissipating thepower losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage of 40 V, forward current of3 A, and a forward voltage drop of 0.5 V.
Additional Circuits
Figure 12 shows an application circuit using a wide input voltage range. The design parameters are similar tothose given for the design example, with a larger value output inductor and a lower closed loop crossoverfrequency.
A. C3 = Tantalum AVX TPSD107M010R0080
Figure 12. 10-V — 21-V Input to 5-V Output Application Circuit
Circuit Using Ceramic Output Filter Capacitors
Figure 13 shows an application circuit using all ceramic capacitors for the input and output filters which generatesa 3.3-V output from a 10-V to 24-V input. The design procedure is similar to those given for the design example,except for the selection of the output filter capacitor values and the design of the additional compensationcomponents required to stabilize the circuit.
14 Submit Documentation Feedback Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS5420
www.ti.com
VIN10 24V-
C1
4.7 Fm
L1
18 Hm
R1
10kW
R2
5.9kW
R3
549 W
C6
1800pF
U1
TPS5420D
VIN
GND VSNS
PH
BOOT
PwPd
EN
3.3V
VOUT
C2
0.01 Fm
D1
MRBS340
C4
47 Fm
C7
0.1 Fm
C4
150pF
VIN
7
1
2
4
5
8
3
6
9
ENA
NC
NC
C3
47 Fm
C (MIN)
O³1
2
(2 x7000)xLpO
(13)
F =
LC
1
2 LpO O
xC (EFF)Ö
(14)
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
Figure 13. Ceramic Output Filter Capacitors Circuit
Output Filter Component Selection
Using Equation 11 , the minimum inductor value is 17.9 μH. A value of 18 μH is chosen for this design.
When using ceramic output filer capacitors, the recommended LC resonant frequency should be no more than7 kHz. Since the output inductor is already selected at 18 μH, this limits the minimum output capacitor value to:
The minimum capacitor value is calculated to be 29 μF. For this circuit a larger value of capacitor yields bettertransient response. Two 47 μF output capacitors are used for C3 and C4. It is important to note that the actualcapacitance of ceramic capacitors decreases with applied voltage. In this example, the output voltage is set to3.3 V, minimizing this effect.
External Compensation Network
When using ceramic output capacitors, additional circuitry is required to stabilize the closed loop system. For thiscircuit, the external components are R3, C5, C6, and C7. To determine the value of these components, firstcalculate the LC resonant frequency of the output filter:
For this example the effective resonant frequency is calculated as 4109 Hz
The network composed of R1, R2, R3, C5, C6, and C7 has two poles and two zeros that are used to tailor theoverall response of the feedback network to accommodate the use of the ceramic output capacitors. The poleand zero locations are given by the following equations:
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS5420
www.ti.com
Fp1=500000x
VO
FLC
(15)
Fz1=0.7xFLC
(16)
Fz2=2.5xFLC
(17)
C7= 1
2 xFp1x(R1||R2)p
(18)
R3= 1
2 xFz1xC7p
(19)
C6= 1
2 xFz2xR1p
(20)
ADVANCED INFORMATION
Output Voltage Limitations
VOUTMAX +0.87 ǒǒVINMIN *IOMAX 0.230Ǔ)VDǓ*ǒIOMAX RLǓ*VD
(21)
VOUTMIN +0.12 ǒǒVINMAX *IOMIN 0.110Ǔ)VDǓ*ǒIOMIN RLǓ*VD
(22)
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined byEquation 17 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower.Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage ascalculated usingEquation 12 . For this design R1 = 10 k Ωand R2 = 5.90 k Ω. With Fp1 = 426 Hz, Fz1 = 2708 Hzand Fz2 = 8898 Hz, the values of R3, C6 and C7 are determined using Equation 18 ,Equation 19 , andEquation 20 :
For this design, using the closest standard values, C7 is 0.1 μF, R3 is 590 Ω, and C6 is 1800 pF. C5 is added toimprove load regulation performance. It is effectively in parallel with C6 in the location of the second polefrequency, so it should be small in relationship to C6. C5 should be less the 1/10 the value of C6. For thisexample, 150 pF works well.
For additional information on external compensation of the TPS5420 or other wide voltage range SWIFT devices,see SLVA237 Using TPS5410/20/30/31 With Aluminum/Ceramic Output Capacitors
Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any giveninput voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%and is given by:
Where:
V
INMIN
= minimum input voltageI
OMAX
= maximum load currentV
D
= catch diode forward voltage.R
L
= output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. Theapproximate minimum output voltage for a given input voltage and minimum load current is given by:
Where:
V
INMAX
= maximum input voltageI
OMIN
= minimum load currentV
D
= catch diode forward voltage.R
L
= output inductor series resistance.This equation assumes nominal on resistance for the high side FET and accounts for worst case variation ofoperating frequency set point. Any design operating near the operational limits of the device should bechecked to assure proper functionality.
16 Submit Documentation Feedback Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS5420
www.ti.com
Internal Compensation Network
H(s) +ǒ1)s
2p Fz1Ǔ ǒ1)s
2p Fz2Ǔ
ǒs
2p Fp0Ǔ ǒ1)s
2p Fp1Ǔ ǒ1)s
2p Fp2Ǔ ǒ1)s
2p Fp3Ǔ
(23)
Thermal Calculations
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
The design equations given in the example circuit can be used to generate circuits using the TPS5420. Thesedesigns are based on certain assumptions, and always select output capacitors within a limited range of ESRvalues. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of theTPS5420. Equation 23 gives the nominal frequency response of the internal voltage-mode type III compensationnetwork:
Where
Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 HzFp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHzFp3 represents the non-ideal parasitics effect.
Using this information along with the desired output voltage, feed forward gain and output filter characteristics,the closed loop transfer function can be derived.
The following formulas show how to estimate the device power dissipation under continuous conduction modeoperations. They should not be used if the device is working at light loads in the discontinuous conduction mode.Conduction Loss: Pcon = I
OUT
2
x R
DS(on)
x V
OUT
/ V
INSwitching Loss: Psw = V
IN
x I
OUT
x 0.01Quiescent Current Loss: Pq = V
IN
x 0.01Total Loss: Ptot = Pcon + Psw + PqGiven T
A
=> Estimated Junction Temperature: T
J
= T
A
+ Rth x PtotGiven T
JMAX
= 125 °C => Estimated Maximum Ambient Temperature: T
AMAX
= T
JMAX
– Rth x Ptot
Copyright © 2006 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS5420
www.ti.com
PERFORMANCE GRAPHS
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 0.5 1 1.5 22.5 3
I -OutputCurrent- A
O
OutputRegulation-%
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 0.5 1 1.5 22.5 3
V -InputVoltage-V
I
OutputRegulation-%
I = 0 A
O
I =1 A
O
I =2 A
O
75
80
85
90
95
100
0 0.5 1 1.5 2 2.5 3
I -OutputCurrent- A
O
Efficiency-%
V =15V
I
V =12V
I
V =18V
IV =19.8V
I
V =10.8V
I
t-Time=200 μs/Div
I A/Div
OUT =500m
VOUT =50mV/Div(ACCoupled)
PH=5V/Div
V =100mV/Div(ACCoupled)
IN
t -Time-1 s/Divm
PH=5V/Div
V =20mV/Div(ACCoupled)
OUT
t -Time-1 s/Divm
t-Time=5ms/Div
V =2V/Div
OUT
V =10V/Div
IN
t-Time=5ms/Div
V =2V/Div
OUT
ENA =2V/Div
TPS5420
SLVS642C – APRIL 2006 – REVISED OCTOBER 2007
The performance graphs in Figure 14 -Figure 20 are applicable to the circuit in Figure 11 . T
A
= 25 °C. unlessotherwise specified.
Figure 14. Efficiency vs. Output Figure 15. Output Regulation % vs. Figure 16. Input Regulation % vs.Current Output Current Input Voltage
Figure 17. Input Voltage Ripple Figure 18. Output Voltage Ripple Figure 19. Transient Response, Ioand PH Node, I
O
= 3 A and PH Node, I
O
= 3 A Step 0.5 to 1.5 A
Figure 20. Startup Waveform, V
IN
Figure 21. Startup Waveform, ENAand V
OUT
and V
OUT
18 Submit Documentation Feedback Copyright © 2006 – 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS5420
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS5420D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS5420DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS5420DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS5420DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS5420 :
•Automotive: TPS5420-Q1
•Enhanced Product: TPS5420-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS5420DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS5420DR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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