SPICE D e vice Model Si9948AEY
Siliconix 1
4/18/01
Document: 70517
Dual P-Channel Enhancement-Mode MOSFE T
Characteristics
• P-channel Vertical DMOS
• Macro-Model (Subcircuit)
• Level 3 MOS
• Applicable for Both Linear and Switchmode
• Applicable Over a -55 to 125°C Temperature Range
• Models Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
Description
The attached SPICE Model describes typical electrical
characteristics of the n-channel vertical DMOS. The
subcircuit model was extracted and optimized over a
25°C to 125°C temperature range under pulse
conditions for 0 to -10 volt gate drives. Saturated output
impedance model accuracy has been maximized for gate
biases near threshold. A novel gate-to-drain feedback
capacitor network is used to model gate charge
characteristics while avoiding convergence problems of
switched Cgd model. Model parameter values are
optimized to provide a best fit to measured electrical
data and are not intended as an exact physical
description of a device.
Model Subcircuit
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to
th e appropriate data sheet of t he same nu mber for guarant eed sp ecification limits.
SPICE D e vice Model Si9948AEY
Siliconix 2
4/18/01
Document: 70517
Model Evaluation
P-Channel Device (TJ=25°C Unless Otherwise Noted)
Parameter Symbol Test Conditions Typ Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID= -250µA2V
On-State Drain CurrentaID(on) VDS = -5V, VGS = -10 V 30 A
Drain-Source On-State ResistancearDS(on) VGS = -10V, ID = -2.6A0.15 Ω
VGS = -4.5V, ID = -2.1A0.20 Ω
Forward Transconductanceagfs VDS = -15V, ID = -2.6A5.3 S
Diode Forward VoltageaVSD IS = -2A, VGS=0V 0.81 V
Dynamic
Total Gate ChargebQg9.5
Gate-Source ChargebQgs VDS= -30V, VGS= -10V,
ID= -2.6A2.5 nC
Gate-Drain ChargebQgd 1.8
Turn-On Delay Timeb,c td(on) 1.1
Rise Ti meb,c trVDD= -30V, RL= 30Ω7.4
Turn-Off Delay Timeb,c td(off) ID≅ -1A, VGEN= -10V,
RG= 6Ω22 ns
Fall Timeb,c tf8
Reverse Recovery Time trr IS= -2A, di/dt=100A/µs50
Notes:
a) Pulse test: Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%.
b) Independent of operating temperature.
c) Include only parasitic components presented in the model circuit
SPICE D e vice Model Si9948AEY
Siliconix 3
4/18/01
Document: 70517
Comparison of Model with Measured Data
(TJ=25°C Unless Otherwise Noted)
Si9948AEY
0
3
6
9
12
15
ID - Drain Current (A)
0 1 2 3 4 5
VDS - Drain-to-Source Voltage (V)
Vgs= 10,7,6 V
Vgs=3 V
Vgs=4V
Vgs=5 V
0
3
6
9
12
15
ID - Drain Current (A)
0 1 2 3 4 5 6
VGS - Gate-to-Source (V)
25C
125C
-55C
0
200
400
600
800
Capacitance (pF)
0 10 20 30 40 50 60
VDS - Drain-to-Source Voltage ( V )
Ciss
Coss
Crss
0.0
6.0
12.0
18.0
24.0
30.0
Vds (V)
0.0
2.0
4.0
6.0
8.0
10.0
Vgs (V)
0 2 4 6 8 10
Qg (nC)
Vgs
Vds
0
0.8
1.6
2.4
3.2
4
Sqrt (IDsat) (A)
0
0.2
0.4
0.6
0.8
1
rDS(on) - On-Resistance (Ohm)
0 2 4 6 8 10
VGS - Gate-to-Source Voltage (V)
Sqrt( IDsat)
rDS(on)
0
0.1
0.2
0.3
0.4
rDS(on) - On-Resistance (Ohm)
0 3 6 9 12 15
ID - Drain Current (A)
Vgs = 10V
Vgs = 4.5V
