SPICE Device Model Si9948AEY Dual P-Channel Enhancement-Mode MOSFET Characteristics * P-channel Vertical DMOS * Macro-Model (Subcircuit) * Level 3 MOS * Applicable for Both Linear and Switchmode * Applicable Over a -55 to 125C Temperature Range * Models Gate Charge, Transient, and Diode Reverse Recovery Characteristics Description The attached SPICE Model describes typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model was extracted and optimized over a 25C to 125C temperature range under pulse conditions for 0 to -10 volt gate drives. Saturated output impedance model accuracy has been maximized for gate biases near threshold. A novel gate-to-drain feedback capacitor network is used to model gate charge characteristics while avoiding convergence problems of switched Cgd model. Model parameter values are optimized to provide a best fit to measured electrical data and are not intended as an exact physical description of a device. Model Subcircuit This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Siliconix 4/18/01 Document: 70517 1 SPICE Device Model Si9948AEY Model Evaluation P-Channel Device (TJ=25C Unless Otherwise Noted) Parameter Static Gate Threshold Voltage On-State Drain Currenta Drain-Source On-State Resistancea Symbol Test Conditions Typ Unit VGS(th) ID(on) rDS(on) VDS = VGS, ID= -250A VDS = -5V, VGS = -10 V VGS = -10V, ID = -2.6A VGS = -4.5V, ID = -2.1A VDS = -15V, ID = -2.6A IS = -2A, VGS=0V 2 30 0.15 0.20 5.3 0.81 V A S V 9.5 2.5 nC 1.8 1.1 7.4 22 ns Forward Transconductancea Diode Forward Voltagea Dynamic Total Gate Chargeb Gate-Source Chargeb gfs VSD Gate-Drain Chargeb Turn-On Delay Timeb,c Rise Timeb,c Turn-Off Delay Timeb,c Qgd td(on) tr td(off) Fall Timeb,c Reverse Recovery Time tf trr Qg Qgs VDS= -30V, VGS= -10V, ID= -2.6A VDD= -30V, RL= 30 ID -1A, VGEN= -10V, RG= 6 IS= -2A, di/dt=100A/s 8 50 Notes: a) Pulse test: Pulse Width 300 sec, Duty Cycle 2%. b) Independent of operating temperature. c) Include only parasitic components presented in the model circuit Siliconix 4/18/01 Document: 70517 2 SPICE Device Model Si9948AEY Comparison of Model with Measured Data (TJ=25C Unless Otherwise Noted) 15 Vgs= 10,7,6 V 15 125C 12 ID - Drain Current (A) ID - Drain Current (A) Vgs=5 V 9 Vgs=4V 6 3 12 Vgs=3 V -55C 9 6 3 25C 0 0 0 1 2 3 4 5 VDS - Drain-to-Source Voltage (V) 2.4 0.6 1.6 rDS(on) - On-Resistance (Ohm) Sqrt (IDsat) (A) 0.8 0.4 0.8 0.2 rDS(on) 0 0 2 4 6 VGS - Gate-to-Source Voltage (V) 8 2 3 4 5 6 0.4 1 Sqrt( IDsat) 3.2 1 VGS - Gate-to-Source (V) rDS(on) - On-Resistance (Ohm) 4 0 0.3 Vgs = 4.5V 0.2 Vgs = 10V 0.1 0 10 0 0 800 3 6 9 ID - Drain Current (A) 12 15 30.0 10.0 Vds 200 Coss 0 18.0 6.0 12.0 4.0 6.0 2.0 0.0 0 10 20 30 40 50 VDS - Drain-to-Source Voltage ( V ) Siliconix 4/18/01 Document: 70517 60 0 2 4 6 Qg (nC) 8 3 Si9948AEY 8.0 0.0 10 Vgs (V) 400 Crss Vgs 24.0 Vds (V) Capacitance (pF) Ciss 600