DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 DAC121S101QML 12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output Check for Samples: DAC121S101QML FEATURES DESCRIPTION * * * * * * * * * * The DAC121S101 is a full-featured, general purpose 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7 V to 5.5 V supply and consumes just 177 A of current at 3.6 V. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 20 MHz over the specified supply voltage range and is compatible with standard SPI, QSPI, MICROWIRE and DSP interfaces. 1 2 Total Ionizing Dose 100 krad(Si) Single Event Latch-up 120 MeV-cm2/mg Guaranteed Monotonicity Low Power Operation Rail-to-Rail Voltage Output Power-on Reset to Zero Volts Output SYNC Interrupt Facility Wide power supply range (+2.7 V to +5.5 V) Small Packages Power Down Feature The supply voltage for the DAC121S101 serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt. APPLICATIONS * * * * Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage & Current Sources Programmable Attenuators The low power consumption and small packages of the DAC121S101 make it an excellent choice for use in battery operated equipment. The DAC121S101 operates over the extended temperature range of -55C to +125C. KEY SPECIFICATIONS * * * * * * Resolution: 12 bits DNL: +0.21, -0.10 LSB (typ) Output Settling Time: 12.5 s (typ) Zero Code Error: 2.1 mV (typ) Full-Scale Error: -0.04 %FS (typ) Power Dissipation - Normal Mode: 0.52 mW (3.6 V) / 1.19 mW (5.5 V) typ - Power Down Mode: 0.014 W (3.6 V) / 0.033 W (5.5 V) typ See Radiation Environments environment information. for dose rate Connection Diagram Top View VA 1 10 N/C 2 9 GND DIN N/C 3 8 SCLK VOUT 4 7 SYNC N/C 5 6 N/C Figure 1. 10 Lead CLGA Package See Package Number NAC0010A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2012, Texas Instruments Incorporated DAC121S101QML SNAS410D - MAY 2008 - REVISED APRIL 2012 www.ti.com Block Diagram VA GND POWER-ON RESET DAC121S101 REF(+) REF(-) DAC REGISTER 12 12-BIT DAC BUFFER VOUT 12 POWER-DOWN CONTROL LOGIC INPUT CONTROL LOGIC SYNC SCLK 5k 100k DIN These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Supply Voltage, VA 6.5 V -0.3 V to (VA + 0.3 V) Voltage on any Input Pin Input Current at Any Pin (3) 10 mA Maximum Output Current (4) 10 mA VOUT Pin in Powerdown Mode 1.0 mA Package Input Current (3) 20 mA Power Dissipation at TA = 25C See (5) Maximum Junction Temperature 175C Lead Temperature CLGA package (Soldering 10 Seconds) 260C -65C to +150C Storage Temperature Package Weight (Typical) CLGA package ESD Tolerance (1) (2) (3) (4) (5) (6) 2 220 mg (6) Class 3A (5000 V) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = 0 V, unless otherwise specified When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. Maximum Output Current may not exceed 10 mA. At VDD = 5.5 V the minimum external resistive load can be no less than 550 , (360 at VDD = 3.6 V). The absolute maximum junction temperature (TJmax) for this device is 175C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA) / JA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5 k resistor. Machine model is 220 pF discharged through ZERO Ohms. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 Operating Ratings (1) (2) -55C to +125C Operating Temperature Range Supply Voltage, VA +2.7 V to 5.5 V Any Input Voltage (3) -0.1 V to (VA + 0.1 V) Output Load 0 to 1500 pF SCLK Frequency (1) (2) (3) Up to 20 MHz Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = 0 V, unless otherwise specified The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV. For example, if VA is 2.7 VDC, ensure that -100 mV input voltages 2.8 VDC to ensure accurate conversions. See Figure 2. Package Thermal Resistance Package JA (Still Air) JC 10-lead CLGA Package on 2 layer, 1oz. PCB 214C/W 25.7C/W Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup Description 1 Static tests at Temp ( C) +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Setting time at +25 13 Setting time at +125 14 Setting time at -55 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML 3 DAC121S101QML SNAS410D - MAY 2008 - REVISED APRIL 2012 www.ti.com DAC121S101 Electrical Characteristics DC Parameters The following specifications apply for VA = +2.7 V to +5.5 V, RL = , CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25C, unless otherwise specified. Parameter Test Conditions Notes Typical (1) Min Max Units Subgroups STATIC PERFORMANCE Resolution See (2) 12 Bits Monotonicity See (2) 12 Bits INL Integral Non-Linearity Over Decimal codes 48 to 4047 DNL Differential Non-Linearity VA = 2.7 V to 5.5 V ZE Zero Code Error IOUT = 0 +2.12 FSE Full-Scale Error IOUT = 0 -0.04 Gain Error All ones Loaded to DAC register -0.11 1.0 GE ZCED TC GE VA = 3 V VA = 5 V -8.0 +0.21 -0.10 See (2) Zero Code Error Drift Gain Error Tempco 2.75 See (2) 8.0 LSB 1, 2, 3 +1.0 LSB 1, 2, 3 LSB 1, 2, 3 +15 mV 1, 2, 3 -1.0 %FSR 1, 2, 3 %FSR 1, 2, 3 -0.7 -20 V/C -0.7 ppm/C -1.0 ppm/C OUTPUT CHARACTERISTICS IPD SINK ZCO FSO Vout Pin in Powerdown Mode All PD Modes See (2) Output Voltage Range See (2) Zero Code Output Full Scale Output Maximum Load Capacitance 4 1.0 mA VA V VA = 3 V, IOUT = 10 A 2.0 6 mV 1, 2, 3 VA = 3 V, IOUT = 100 A 4 10 mV 1, 2, 3 VA = 5 V, IOUT = 10 A 2 8 mV 1, 2, 3 VA = 5 V, IOUT = 100 A 4 9 mV 1, 2, 3 VA = 3 V, IOUT = 10 A 2.997 2.990 V 1, 2, 3 VA = 3 V, IOUT = 100 A 2.991 2.985 V 1, 2, 3 VA = 5 V, IOUT = 10 A 4.994 4.985 V 1, 2, 3 VA = 5 V, IOUT = 100 A 4.992 4.985 V 1, 2, 3 RL = 1500 pF 1500 pF RL = 2 k See (2) DC Output Impedance (1) (2) 0 8 16 1, 2, 3 Typical figures are at TJ = 25C, and represent most likely parametric norms. This parameter is guaranteed by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 DAC121S101 Electrical Characteristics DC Parameters (Continued) The following specifications apply for VA = +2.7 V to +5.5 V, RL = , CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25C, unless otherwise specified. Parameter Test Conditions Notes Typical (1) Min Max Units Subgroups 6 -200 LOGIC INPUT IIN Input Current VIL Input Low Voltage VIH Input High Voltage CIN Input Capacitance +200 nA 1, 2, 3 VA = 5 V 0.8 V 1, 2, 3 VA = 3 V 0.5 V 1, 2, 3 VA = 5 V 2.4 V 1, 2, 3 VA = 3 V 2.1 V 1, 2, 3 See (2) 5 pF POWER REQUIREMENTS IA PC IOUT / IA (1) (2) Normal Mode fSCLK = 20 MHz 5.5 V 216 270 A 1, 2, 3 3.6 V 145 200 A 1, 2, 3 Normal Mode fSCLK = 10 MHz 5.5 V 185 230 A 1, 2, 3 3.6 V 132 175 A 1, 2, 3 Normal Mode fSCLK = 0 5.5 V 150 190 A 1, 2, 3 3.6 V 115 160 A 1, 2, 3 All PD Modes, fSCLK = 20 MHz 5.5 V 22 60 A 1, 2, 3 3.6 V 12 30 A 1, 2, 3 All PD Modes, fSCLK = 10 MHz 5.5 V 12 40 A 1, 2, 3 3.6 V 6 20 A 1, 2, 3 All PD Modes, fSCLK = 0 5.5 V .006 1.0 A 1, 2, 3 3.6 V .004 1.0 A 1, 2, 3 Normal Mode fSCLK = 20 MHz 5.5 V 1.19 1.49 mW 0.52 .72 mW Normal Mode fSCLK = 10 MHz 5.5 V 1.02 1.27 mW 0.47 .63 mW Normal Mode fSCLK = 0 5.5 V 0.82 1.05 mW 0.41 .58 mW All PD Modes, fSCLK = 20 MHz 5.5 V 0.12 .33 mW 0.07 .11 mW All PD Modes, fSCLK = 10 MHz 5.5 V 0.04 .22 mW 0.02 .08 mW All PD Modes, fSCLK = 0 5.5 V 0.033 5.5 W 0.014 3.6 W Supply Current (output unloaded) Power Consumption (output unloaded) Power Efficiency ILOAD = 2 mA 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V See (2) See (2) See (2) See (2) See (2) See (2) See (2) 91 % 94 % Typical figures are at TJ = 25C, and represent most likely parametric norms. This parameter is guaranteed by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML 5 DAC121S101QML SNAS410D - MAY 2008 - REVISED APRIL 2012 www.ti.com DAC121S101 Electrical Characteristics AC and Timing Characteristics The following specifications apply for VA = +2.7 V to +5.5 V, RL = , CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25C, unless otherwise specified. Parameter fSCLK SCLK Frequency CL 200 pF CL = 500 pF ts CL 200 pF (See Figure 4) 1/fSCLK Units Subgroups 20 MHz 9, 10, 11 15 s 9, 10, 11 12.5 15 s 9, 10, 11 00Fh to FF0h code change, RL = 12.5 15 s 9, 10, 11 12.5 15 s 9, 10, 11 Code change from 800h to 7FFh VA = 5 V VA = 3 V See (2) 1 V/s See (2) 12 nV-sec See (2) 0.5 nV-sec .65 s 1.1 s See (2) SCLK Cycle Time (See Figure 4) 50 ns 9, 10, 11 SCLK High time (See Figure 4) 20 ns 9, 10, 11 tL SCLK Low Time (See Figure 4) 20 ns 9, 10, 11 tSUCL Set-up Time SYNC to SCLK Rising Edge (See Figure 4) 0 ns 9, 10, 11 tSUD Data Set-Up Time (See Figure 4) 6 ns 9, 10, 11 tDHD Data Hold Time (See Figure 4) 4.5 ns 9, 10, 11 VA = 5.5 V (See Figure 4) 10 ns 9, 10, 11 VA = 2.7 V (See Figure 4) 18 ns 9, 10, 11 VA = 5.5 V (See Figure 4) 37 ns 9, 10, 11 VA = 2.7 V (See Figure 4) 36 ns 9, 10, 11 tSYNC 6 See (2) Max tH tCS (1) (2) Min 12.5 Digital Feedthrough Wake-Up Time Typical (1) FF0 to 00F code change, RL = Output Slew Rate Glitch Impulse tWU Notes Output Voltage Settling Time CL = 500 pF SR Test Conditions SCLK fall to rise of SYNC SYNC High Time Typical figures are at TJ = 25C, and represent most likely parametric norms. This parameter is guaranteed by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 DAC121S101 Electrical Characteristics Radiation Electrical Characteristics (1) The following specifications apply for VA = +2.7 V to +5.5 V, RL = , CL = 200 pF to GND, fSCLK = 20 MHz, input code range 48 to 4047. Parameter Test Conditions Min Max Units Subgroups POWER REQUIREMENTS Supply Current (output unloaded) IA (1) Normal Mode fSCLK = 20 MHz 5.5 V 325 A 1 3.6 V 250 A 1 Normal Mode fSCLK = 10 MHz 5.5 V 300 A 1 3.6 V 225 A 1 Normal Mode fSCLK = 0 5.5 V 275 A 1 3.6 V 200 A 1 All PD Modes, fSCLK = 20 MHz 5.5 V 125 A 1 3.6 V 100 A 1 All PD Modes, fSCLK = 10 MHz 5.5 V 115 A 1 3.6 V 95 A 1 All PD Modes, fSCLK = 0 5.5 V 100 A 1 3.6 V 100 A 1 Pre and post irradiation limits are identical to those listed in the "DC Parameters" and "AC and Timing Characteristics" tables, except as listed in the "Radiation Electrical Characteristics" table. When performing post irradiation electrical measurements for any RHA level, TA = +25C. See Radiation Environments for dose rate and test conditions. DAC121S101 Electrical Characteristics Operating Life Test Delta Parameters TA at 25C (1) Parameter INL ts IA (1) Max Units Integral non-linearity Test Conditions 2 LBS Output voltage settling time 5 A Normal Mode, VA = 5.5V fSCLK = 20 MHz 10 A Normal Mode, VA = 3.6V fSCLK = 20 MHz 6 A Normal Mode, VA = 5.5V fSCLK = 10 MHz 10 A Normal Mode, VA = 3.6V fSCLK = 10 MHz 6 A Normal Mode, VA = 5.5V fSCLK = 0 8 A Normal Mode, VA = 3.6V fSCLK = 0 6 A All PD Modes, VA = 5.5V fSCLK = 20 MHz 2 A All PD Modes, VA = 3.6V fSCLK = 20 MHz 1 A All PD Modes, VA = 5.5V fSCLK = 10 MHz 1 A All PD Modes, VA = 3.6V fSCLK = 10 MHz 1 A All PD Modes, VA = 5.5V fSCLK = 0 0.1 A All PD Modes, VA = 3.6V fSCLK = 0 0.1 A Supply Current (output unloaded) Min These parameters are worse case drift. Deltas are performed at room temperature Post OP Life. All other parameters no Deltas are required. I/O TO INTERNAL CIRCUITRY GND Figure 2. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML 7 DAC121S101QML SNAS410D - MAY 2008 - REVISED APRIL 2012 www.ti.com Specification Definitions DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 4096 = VA / 4096. DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus. FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded into the DAC and the value of VA x 4095 / 4096. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error. GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables. LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is LSB = VREF / 2n (1) where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 12 for the DAC121S101. MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output stability maintained. MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load. SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated. WAKE-UP TIME is the time for the output to exit power-down mode. This is the time measured from the falling edge of 16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0 V. ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered. 8 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 Transfer Characteristic FSE 4095 x VA 4096 GE = FSE - ZE FSE = GE + ZE OUTPUT VOLTAGE ZE 0 0 4095 DIGITAL INPUT CODE Figure 3. Input / Output Transfer Characteristic Timing Diagram SCLK 1 tSUCL 13 14 15 16 tL tH tCS | tSYNC 2 | | 1 / fSCLK | SYNC DB15 DB0 | DIN | | tDHD tSUD Figure 4. DAC121S101 Timing Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML 9 DAC121S101QML SNAS410D - MAY 2008 - REVISED APRIL 2012 www.ti.com Typical Performance Characteristics fSCLK = 20 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 10 DNL at VA = 2.7V DNL at VA = 5.5V Figure 5. Figure 6. INL at VA = 2.7V INL at VA = 5.5V Figure 7. Figure 8. DNL vs. VA INL vs. VA Figure 9. Figure 10. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 Typical Performance Characteristics (continued) fSCLK = 20 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 2.7V DNL vs. fSCLK 5.5V DNL vs. fSCLK Figure 11. Figure 12. 2.7V DNL vs. Clock Duty Cycle 5.5V DNL vs. Clock Duty Cycle Figure 13. Figure 14. 2.7V DNL vs. Temperature 5.5V DNL vs. Temperature Figure 15. Figure 16. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML 11 DAC121S101QML SNAS410D - MAY 2008 - REVISED APRIL 2012 www.ti.com Typical Performance Characteristics (continued) fSCLK = 20 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 12 2.7V INL vs. fSCLK 5.5V INL vs. fSCLK Figure 17. Figure 18. 2.7V INL vs. Clock Duty Cycle 5.5V INL vs. Clock Duty Cycle Figure 19. Figure 20. 2.7V INL vs. Temperature 5.5V INL vs. Temperature Figure 21. Figure 22. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 Typical Performance Characteristics (continued) fSCLK = 20 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated Zero Code Error vs. fSCLK Zero Code Error vs. Temperature Figure 23. Figure 24. Full-Scale Error vs. fSCLK Full-Scale Error vs. Temperature Figure 25. Figure 26. Supply Current vs. VA Supply Current vs. Temperature Figure 27. Figure 28. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML 13 DAC121S101QML SNAS410D - MAY 2008 - REVISED APRIL 2012 www.ti.com Typical Performance Characteristics (continued) fSCLK = 20 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 14 5V Glitch Response Power-On Reset Figure 29. Figure 30. 3V Wake-Up Time 5V Wake-Up Time Figure 31. Figure 32. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 FUNCTIONAL DESCRIPTION DAC SECTION The DAC121S101 is fabricated on a CMOS process with an architecture that consists of switches and a resistor string that are followed by an output buffer. The power supply serves as the reference voltage. The input coding is straight binary with an ideal output voltage of: VOUT = VA x (D / 4096) (2) where D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value between 0 and 4095. RESISTOR STRING The simplified resistor string is shown in Figure 33. Conceptually, this string consists of 4096 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. This configuration guarantees that the DAC is monotonic. VA R R R To Output Amplifier R R Figure 33. DAC Resistor String OUTPUT AMPLIFIER The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0V to VA. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the amplifier are described in the Electrical Tables. SERIAL INTERFACE The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See the Timing Diagram for information on a write sequence. A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be brought high for the minimum specified time before the next write sequence as a falling edge of SYNC can initiate the next write cycle. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML 15 DAC121S101QML SNAS410D - MAY 2008 - REVISED APRIL 2012 www.ti.com Since the SYNC and DIN buffers draw more current when they are high, they should be idled low between write sequences to minimize power consumption. INPUT SHIFT REGISTER The input shift register, Figure 34, has sixteen bits. The first two bits are "don't cares" and are followed by two bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing Diagram, Figure 4. DB15 (MSB) X DB0 (LSB) X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 0 0 1 1 0 Normal Operation 1 5 k: to GND 0 100 k: to GND 1 High Impedance Power-Down Modes Figure 34. Input Register Contents Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation or in the output voltage. POWER-ON RESET The power-on reset circuit controls the output voltage during power-up. Upon application of power the DAC register is filled with zeros and the output voltage is 0 Volts and remains there until a valid write sequence is made to the DAC. POWER-DOWN MODES The DAC121S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the control register. Table 1. Modes of Operation DB13 DB12 Operating Mode 0 0 Normal Operation 0 1 Power-Down with 5k to GND 1 0 Power-Down with 100k to GND 1 1 Power-Down with Hi-Z When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of these bits the supply current drops to its power-down level and the output is pulled down with either a 5k or a 100k resistor, or is in a high impedance state, as described in Table 1. The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the power-down modes. Minimum power consumption is achieved in the power-down mode with SCLK disabled and SYNC and DIN idled low. 16 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 Applications Information The simplicity of the DAC121S101 implies ease of use. However, it is important to recognize that any data converter that utilizes its supply voltage as its reference voltage will have essentially zero PSRR (Power Supply Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device. DSP/MICROPROCESSOR INTERFACING Interfacing the DAC121S101 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process. ADSP-2101/ADSP2103 Interfacing Figure 35 shows a serial interface between the DAC121S101 and the ADSP-2101/ADSP2103. The DSP should be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled. ADSP-2101/ ADSP2103 TFS DT SCLK DAC121S101 SYNC DIN SCLK Figure 35. ADSP-2101/2103 Interface 80C51/80L51 Interface A serial interface between the DAC121S101 and the 80C51/80L51 microcontroller is shown in Figure 36. The SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line P3.3. This line is taken low when data is to transmitted to the DAC121S101. Since the 80C51/80L51 transmits 8bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the 80C51/80L51 transmits data with the LSB first while the DAC121S101 requires data with the MSB first. 80C51/80L51 P3.3 DAC121S101 SYNC TXD SCLK RXD DIN Figure 36. 80C51/80L51 Interface 68HC11 Interface A serial interface between the DAC121S101 and the 68HC11 microcontroller is shown in Figure 37. The SYNC line of the DAC121S101 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51. The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the second byte of data to the DAC, after which PC7 should be raised to end the write sequence. 68HC11 DAC121S101 PC7 SCK MOSI SYNC SCLK DIN Figure 37. 68HC11 Interface Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML 17 DAC121S101QML SNAS410D - MAY 2008 - REVISED APRIL 2012 www.ti.com Microwire Interface Figure 38 shows an interface between a Microwire compatible device and the DAC121S101. Data is clocked out on the rising edges of the SCLK signal. MICROWIRE DEVICE DAC121S101 CS SYNC SK SCLK SO DIN Figure 38. Microwire Interface USING REFERENCES AS POWER SUPPLIES Recall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage. Since the DAC121S101 consumes very little power, a reference source may be used as the supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise regulators can also be used for the power supply of the DAC121S101. Listed below are a few power supply options for the DAC121S101. LM4130 The LM4130 reference, with its 0.05% accuracy over temperature, is a good choice as a power source for the DAC121S101. Its primary disadvantage is the lack of 3 V and 5 V versions. However, the 4.096 V version is useful if a 0 to 4.095 V output range is desirable or acceptable. Bypassing the LM4130 VIN pin with a 0.1 F capacitor and the VOUT pin with a 2.2 F capacitor will improve stability and reduce output noise. The LM4130 comes in a space-saving 5-pin SOT23. Input Voltage LM4130-4.1 C2 2.2 PF C1 0.1 PF DAC121S101 SYNC VOUT = 0V to 4.095V DIN SCLK Figure 39. The LM4130 as a power supply LM4050 Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a power regulator for the DAC121S101. It does not come in a 3 Volt version, but 4.096 V and 5 V versions are available. It comes in a space-saving 3-pin SOT23. Input Voltage R VZ LM4050-4.1 or LM4050-5.0 0.47 PF DAC121S101 SYNC VOUT = 0V to 5V DIN SCLK Figure 40. The LM4050 as a power supply 18 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 The minimum resistor value in the circuit of Figure 40 should be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the DAC121S101 draws zero current. The maximum resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum DAC121S101 current in full operation. The conditions for minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the DAC121S101 draws its maximum current. These conditions can be summarized as R(min) = ( VIN(max) - VZ(min) / (IA(min) + IZ(max)) (3) R(max) = ( VIN(min) - VZ(max) / (IA(max) + IZ(min) ) (4) and where VZ(min) and VZ(max) are the nominal LM4050 output voltages the LM4050 output tolerance over temperature, IZ(max) is the maximum allowable current through the LM4050, IZ(min) is the minimum current required by the LM4050 for proper regulation, IA(max) is the maximum DAC121S101 supply current, and IA(min) is the minimum DAC121S101 supply current. LP3985 The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good choice for applications that do not require a precision reference for the DAC121S101. It comes in 3.0V, 3.3V and 5V versions, among others, and sports a low 30 V noise specification at low frequencies. Since low frequency noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages. Input Voltage LP3985 1 PF 0.1 PF 0.01 PF DAC121S101 SYNC VOUT = 0V to 5V DIN SCLK Figure 41. Using the LP3985 regulator An input capacitance of 1.0F without any ESR requirement is required at the LP3985 input, while a 1.0F ceramic capacitor with an ESR requirement of 5m to 500m is required at the output. Careful interpretation and understanding of the capacitor specification is required to ensure correct device operation. LP2980 The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon grade. It is available in 3.0V, 3.3V and 5V versions, among others. Input Voltage VIN ON / OFF LP2980 VOUT 1 PF DAC121S101 SYNC VOUT = 0V to 5V DIN SCLK Figure 42. Using the LP2980 regulator Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML 19 DAC121S101QML SNAS410D - MAY 2008 - REVISED APRIL 2012 www.ti.com Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1.0F over temperature, but values of 2.2F or more will provide even better performance. The ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be too high at low temperatures. BIPOLAR OPERATION The DAC121S101 is designed for single supply operation and thus has a unipolar output. However, a bipolar output may be obtained with the circuit in Figure 43. This circuit will provide an output voltage range of 5 Volts. A rail-to-rail amplifier should be used if the amplifier supplies are limited to 5V. 10 pF R2 +5V +5V 10 PF R1 + - 0.1 PF 5V + DAC121S101 -5V SYNC VOUT DIN SCLK Figure 43. Bipolar Operation The output voltage of this circuit for any code is found to be VO = (VA x (D / 4096) x ((R1 + R2) / R1) - VA x R2 / R1) (5) where D is the input code in decimal form. With VA = 5V and R1 = R2, VO = (10 x D / 4096) - 5V (6) A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2. Table 2. Some Rail-to-Rail Amplifiers AMP PKGS LMC7111 DIP-8 SOT23-5 Typ VOS Typ ISUPPLY 0.9 mV 25 A LM7301 SO-8 SOT23-5 0.03 mV 620 A LM8261 SOT23-5 0.7 mV 1 mA LAYOUT, GROUNDING, AND BYPASSING For best accuracy and minimum noise, the printed circuit board containing the DAC121S101 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes should be located in the same board layer. There should be a single ground plane. A single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate ground planes must be connected in one place, preferably near the DAC121S101. Special care is required to guarantee that digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous return path below their traces. The DAC121S101 power supply should be bypassed with a 10F and a 0.1F capacitor as close as possible to the device with the 0.1F right at the device supply pin. The 10F capacitor should be a tantalum type and the 0.1F capacitor should be a low ESL, low ESR type. The power supply for the DAC121S101 should only be used for analog circuits. 20 Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML DAC121S101QML www.ti.com SNAS410D - MAY 2008 - REVISED APRIL 2012 Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. The clock and data lines should have controlled impedances. Radiation Environments Careful consideration should be given to environmental conditions when using a product in a radiation environment. Total Ionizing Dose The products with the radiation hardness assurance (RHA) levels listed in the Ordering Information table listed on the front page are qualified for low dose rate environments only. DAC121S101WGRQV 5962R0722601VZA This product is tested and qualified per MIL-STD-883 Test Method 1019, Condition A and the "Extended room temperature anneal test" where a high dose irradiation followed by a room temperature anneal is used to simulate a dose rate of 0.027 rad(Si)/s and is qualified for environments with radiation levels of 0.027 rad(Si)/s or lower. DAC121S101WGRLV 5962R0722602VZA This product is tested and qualified per MIL-STD-883 Test Method 1019, Condition D at a dose rate of 0.01 rad(Si)/s and are qualified for environments with radiation levels of 0.01 rad(Si)/s or lower. Single Event Latch-Up and Functional Interrupt One time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in the Key Specifications section on the front page is the maximum LET tested. A test report is available upon request. Single Event Upset A report on single event upset (SEU) is available upon request. Submit Documentation Feedback Copyright (c) 2008-2012, Texas Instruments Incorporated Product Folder Links: DAC121S101QML 21 PACKAGE OPTION ADDENDUM www.ti.com 1-Mar-2013 PACKAGING INFORMATION Orderable Device Status (1) 5962R0722601VZA ACTIVE Package Type Package Pins Package Qty Drawing CLGA NAC 10 Eco Plan Lead/Ball Finish (2) TBD MSL Peak Temp Op Temp (C) Top-Side Markings (3) A42 SNPB Level-1-NA-UNLIM (4) -55 to 125 DAC121S101 WGRQMLV Q 5962R07226 01VZA ACO 01VZA >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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