FUJITSU SEMICONDUCTOR DATA SHEET AE1E MEMORY CMOS 4 x 2 M x 8 BIT SYNCHRONOUS DYNAMIC RAM MB81F64842D-75/-102/-10 CMOS 4-Bank x 2,097,152-Word x 8 Bit Synchronous Dynamic Random Access Memory DESCRIPTION The Fujitsu MB81F64842D is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing 67,108,864 memory cells accessible in a 8-bit format. The MB81F64842D features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB81F64842D SDRAM is designed to reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing constraints, and may improve data bandwidth of memory as much as 5 times more than a standard DRAM. The MB81F64842D is ideally suited for workstations, personal computers, laser printers, high resolution graphic adapters/accelerators and other applications where an extremely large memory and bandwidth are required and where a simple interface is needed. PRODUCT LINE & FEATURES Parameter MB81F64842D -75 -102 -10 3 - 3 - 3 clk min. 2 - 2 - 2 clk min. 3 - 3 - 3 clk min. 133 MHz max. 100 MHz max. 100 MHz max. Burst Mode Cycle Time 7.5 ns min. 10 ns min. 10 ns min. Access Time from Clock (CL = 3) 6 ns max. 6 ns max. (CL = 2) 6 ns max. 210 mA max. 180 mA max. 160 mA max. Power Down Mode Curren (ICC2P) 1 mA max. 1 mA max. 1 mA max. Self Refresh Current (ICC6) 1 mA max. 1 A max. 1 mA max. CL - tRCD - tRP Clock Frequency Operating Current (2 banks active) * * * * * Single +3.3 V Supply 0.3 V tolerance LVTTL compatible I/O 4 K refresh cycles every 64 ms Four bank operation Burst read/write operation and burst read/single write operation capability * Standard and low power versions * Programmable burst type, burst length, and CAS latency * Auto-and Self-refresh (every 15.6 s) * CKE power down mode * Output Enable and Input Data Mask MB81F64842D-75/-102/-10 PACKAGE Plastic TSOP(II) Package Marking side (FPT-54P-M02) (Normal Bend) Package and Ordering Information - 54-pin plastic (400 mil) TSOP-II, order as MB81F64842D-xxxFN 2 MB81F64842D-75/-102/-10 PIN ASSIGNMENTS AND DESCRIPTIONS 54-Pin TSOP(II) (TOP VIEW) <Normal Bend: FPT-54P-M02> VCC DQ0 VCCQ N.C. DQ1 VSSQ N.C. DQ2 VCCQ N.C. DQ3 VSSQ N.C. VCC N.C. WE CAS RAS CS A13 A12 A10/AP A0 A1 A2 A3 VCC 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VSS DQ7 VSSQ N.C. DQ6 VCCQ N.C. DQ5 VSSQ N.C. DQ4 VCCQ N.C. VSS N.C. DQM CLK CKE N.C. A11 A9 A8 A7 A6 A5 A4 VSS (Marking side) Pin Number Symbol Function 1, 3, 9, 14, 27, 43, 49 VCC, VCCQ 2, 5, 8, 11, 44, 47, 50, 53 DQ0 to DQ7 Data I/O 6, 12, 28, 41, 46, 52, 54 VSS, VSSQ * Ground 4, 7, 10, 13, 15, 36, 40, 42, 45, 48, 51 N.C. No Connection 16 WE Write Enable 17 CAS Column Address Strobe 18 RAS Row Address Strobe 19 CS 20, 21 A13 (BA0), A12 (BA1) 22 AP 22, 23, 24, 25, 26, 29, 30, 31, 32, 33, 34, 35 A0 to A11 Address Input 37 CKE Clock Enable 38 CLK Clock Input 39 DQM Input Mask/Output Enable Supply Voltage Chip Select Bank Select (Bank Address) Auto Precharge Enable * Row: A0 to A11 * Column: A0 to A8 * : These pins are connected internally in the chip. 3 MB81F64842D-75/-102/-10 BLOCK DIAGRAM Fig. 1 - MB81F64842D BLOCK DIAGRAM CLK To each block BANK-3 CLOCK BUFFER BANK-2 CKE BANK-1 BANK-0 RAS CS RAS CONTROL SIGNAL LATCH CAS COMMAND DECODER WE CAS WE DRAM CORE MODE REGISTER (4,096 x 512 x 8) A0 to A11, A10/AP ADDRESS BUFFER/ REGISTER ROW ADDR. A12 (BA1) A13 (BA0) COLUMN ADDRESS COUNTER DQM I/O DATA BUFFER/ REGISTER DQ0 to DQ7 4 COL. ADDR. I/O VCC VCCQ VSS/VSSQ MB81F64842D-75/-102/-10 FUNCTIONAL TRUTH TABLE Note 1 COMMAND TRUTH TABLE Note 2, 3, and 4 CKE Function Notes Symbol CS RAS CAS WE n-1 n A13, A12 A11 (BA) A10 (AP) A9 A8 to A0 Device Deselect *5 DESL H X H X X X X X X X X No Operation *5 NOP H X L H H H X X X X X BST H X L H H L X X X X X Burst Stop Read *6 READ H X L H L H V X L X V Read with Auto-precharge *6 READA H X L H L H V X H X V Write *6 H X L H L L V X L X V Write with Auto-precharge *6 WRITA H X L H L L V X H X V Bank Active (RAS) *7 ACTV H X L L H H V V V V V Precharge Single Bank PRE H X L L H L V X L X X Precharge All Banks PALL H X L L H L X X H X X MRS H X L L L L L L L V V Mode Register Set Notes: *1. *2. *3. *4. *5. *6. *7. *8. *9. *8, 9 WRIT V = Valid, L = Logic Low, H = Logic High, X = either L or H. All commands assumes no CSUS command on previous rising edge of clock. All commands are assumed to be valid state transitions. All inputs are latched on the rising edge of clock. NOP and DESL commands have the same effect on the part. READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has been activated (ACTV command). Refer to STATE DIAGRAM. ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL command). Required after power up. MRS command should only be issued after all banks have been precharged (PRE or PALL command). Refer to STATE DIAGRAM. 5 MB81F64842D-75/-102/-10 DQM TRUTH TABLE CKE Function Command DQM n-1 n Data Write/Output Enable ENBL H X L Data Mask/Output Disable MASK H X H CKE TRUTH TABLE Current State CKE Function Notes Symbol Bank Active Clock Suspend Mode Entry*1, 4 Any Clock Suspend Continue (Except Idle) Clock Suspend Clock Suspend Mode Exit Idle Auto-refresh Command Idle Self-refresh Entry *1 Power Down Entry A13, A10 A12 A11 (AP) (BA) A9 to A0 n-1 n H L X X X X X X X X L L X X X X X X X X L H X X X X X X X X *2 REF H H L L L H X X X X *2, 3 SELF H L L L L H X X X X L H L H H H X X X X L H H X X X X X X X H L L H H H X X X X H L H X X X X X X X L H L H H H X X X X L H H X X X X X X X Self Refresh Self-refresh Exit Idle CSUS CS RAS CAS WE SELFX *3 PD Power Down Power Down Exit Notes: *1. *2. *3. *4. 6 The CSUS command requires that at least one bank is active. Refer to STATE DIAGRAM. REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL command). Refer to STATE DIAGRAM. SELF and PD commands should only be issued after the last read data have been appeared on DQ. NOP or DSEL commands should only be issued after CSUS and PRE(or PALL) commands asserted at the same time. MB81F64842D-75/-102/-10 OPERATION COMMAND TABLE (Applicable to single bank) Current State Idle Bank Active CS RAS CAS WE Addr Command Function Notes H X X X X DESL NOP L H H H X NOP NOP L H H L X BST NOP L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA Illegal *2 L L H H BA, RA ACTV L L H L BA, AP PRE/PALL NOP *6 L L L H X REF/SELF Auto-refresh or Self-refresh *3 L L L L MODE MRS Mode Register Set (Idle after tRSC) H X X X X DESL NOP L H H H X NOP NOP L H H L X BST NOP L H L H BA, CA, AP READ/READA Begin Read; Determine AP L H L L BA, CA, AP WRIT/WRITA Begin Write; Determine AP L L H H BA, RA ACTV L L H L BA, AP PRE/PALL Precharge; Determine Precharge Type L L L H X REF/SELF Illegal L L L L MODE MRS Illegal Bank Active after tRCD Illegal *3, 7 *2 (Continued) 7 MB81F64842D-75/-102/-10 Current State Read Write CS RAS CAS WE Addr Command Function Notes H X X X X DESL NOP (Continue Burst to End Bank Active) L H H H X NOP NOP (Continue Burst to End Bank Active) L H H L X BST Burst Stop Bank Active L H L H BA, CA, AP READ/READA Terminate Burst, New Read; Determine AP L H L L BA, CA, AP WRIT/WRITA Terminate Burst, Start Write; Determine AP *4 L L H H BA, RA ACTV Illegal *2 L L H L BA, AP PRE/PALL Terminate Burst, Precharge Idle; Determine Precharge Type L L L H X REF/SELF Illegal L L L L MODE MRS Illegal H X X X X DESL NOP (Continue Burst to End Bank Active) L H H H X NOP NOP (Continue Burst to End Bank Active) L H H L X BST Burst Stop Bank Active L H L H BA, CA, AP READ/READA Terminate Burst, Start Read; Determine AP L H L L BA, CA, AP WRIT/WRITA Terminate Burst, New Write; Determine AP L L H H BA, RA ACTV L L H L BA, AP PRE/PALL Terminate Burst, Precharge; Determine Precharge Type L L L H X REF/SELF Illegal L L L L MODE MRS Illegal Illegal *2 (Continued) 8 MB81F64842D-75/-102/-10 Current State Read with Autoprecharge Write with Autoprecharge CS RAS CAS WE Addr Command Function Notes H X X X X DESL NOP (Continue Burst to End Precharge Idle) L H H H X NOP NOP (Continue Burst to End Precharge Idle) L H H L X BST Illegal L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA Illegal *2 L L H H BA, RA ACTV Illegal *2 L L H L BA, AP PRE/PALL Illegal *2 L L L H X REF/SELF Illegal L L L L MODE MRS Illegal H X X X X DESL NOP (Continue Burst to End Precharge Idle) L H H H X NOP NOP (Continue Burst to End Precharge Idle) L H H L X BST Illegal L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA Illegal *2 L L H H BA, RA ACTV Illegal *2 L L H L BA, AP PRE/PALL Illegal *2 L L L H X REF/SELF Illegal L L L L MODE MRS Illegal (Continued) 9 MB81F64842D-75/-102/-10 Current State Precharge Bank Activating CS RAS CAS WE Addr Command Function Notes H X X X X DESL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L X BST NOP (Idle after tRP) L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA Illegal *2 L L H H BA, RA ACTV Illegal *2 L L H L BA, AP PRE/PALL NOP (PALL may affect other bank) *5 L L L H X REF/SELF Illegal L L L L MODE MRS Illegal H X X X X DESL NOP (Bank Active after tRCD) L H H H X NOP NOP (Bank Active after tRCD) L H H L X BST NOP (Bank Active after tRCD) L H L H BA, CA, AP READ/READA Illegal *2 L H L L BA, CA, AP WRIT/WRITA Illegal *2 L L H H BA, RA ACTV Illegal *2 L L H L BA, AP PRE/PALL Illegal *2 L L L H X REF/SELF Illegal L L L L MODE MRS Illegal (Continued) 10 MB81F64842D-75/-102/-10 (Continued) Current State Refreshing Mode Register Setting CS RAS CAS WE Addr Command Function H X X X X DESL NOP (Idle after tRC) L H H X X NOP/BST NOP (Idle after tRC) L H L X X L L H X X ACTV/ PRE/PALL Illegal L L L X X REF/SELF/ MRS Illegal H X X X X DESL NOP (Idle after tRSC) L H H H X NOP NOP (Idle after tRSC) L H H L X BST Illegal L H L X X L L X X X Notes READ/READA/ Illegal WRIT/WRITA READ/READA/ Illegal WRIT/WRITA ACTV/PRE/ PALL/REF/ SELF/MRS Illegal ABBREVIATIONS: RA = Row Address CA = Column Address BA = Bank Address AP = Auto Precharge 11 MB81F64842D-75/-102/-10 COMMAND TRUTH TABLE FOR CKE Current State Selfrefresh Selfrefresh Recovery CKE n-1 CKE n CS RAS CAS WE Addr H X X X X X X Invalid L H H X X X X Exit Self-refresh (Self-refresh Recovery Idle after tRC) L H L H H H X Exit Self-refresh (Self-refresh Recovery Idle after tRC) L H L H H L X Illegal L H L H L X X Illegal L H L L X X X Illegal L L X X X X X NOP (Maintain Self-refresh) L X X X X X X Invalid H H H X X X X Idle after tRC H H L H H H X Idle after tRC H H L H H L X Illegal H H L H L X X Illegal H H L L X X X Illegal H H X X X X X Illegal H L X X X X X Illegal Function Notes (Continued) 12 MB81F64842D-75/-102/-10 Current State Power Down All Banks Idle CKE n-1 CKE n CS RAS CAS WE Addr H X X X X X X L H H X X X X L H L H H H X L L X X X X X NOP (Maintain Power Down Mode) L H L L X X X Illegal L H L H L X X Illegal H H H X X X MODE Refer to the Operation Command Table. H H L H X X MODE Refer to the Operation Command Table. H H L L H X MODE Refer to the Operation Command Table. H H L L L H X H H L L L L MODE H L H X X X X Power Down H L L H H H X Power Down H L L H H L X Illegal H L L H L X X Illegal H L L L H X X Illegal H L L L L H X Self-refresh H L L L L L X Illegal L X X X X X X Invalid Function Notes Invalid Exit Power Down Mode Idle Auto-refresh Refer to the Operation Command Table. (Continued) 13 MB81F64842D-75/-102/-10 (Continued) Current State CKE n-1 CKE n CS RAS CAS WE Addr Bank Active Bank Activating Read/Write H H X X X X X Refer to the Operation Command Table. H L X X X X X Begin Clock Suspend next cycle L X X X X X X Invalid H X X X X X X Invalid L H X X X X X Exit Clock Suspend next cycle L L X X X X X Maintain Clock Suspend L X X X X X X Invalid H H X X X X X Refer to the Operation Command Table. H L X X X X X Illegal Clock Suspend Any State Other Than Listed Above Notes: *1. *2. *3. *4. *5. *6. *7. 14 Function Notes All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle. Illegal means don't used command. If used, power up sequence be asserted after power shut down. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state of that bank. Illegal if any bank is not idle. Must satisfy bus contention, bus turn around, and/or write recovery requirements. NOP to bank precharging or in idle state. May precharge bank spesified by BA (and AP). SELF command should only be issued after the last read data have been appeared on DQ. MRS command should only be issued on condition that all DQ are in Hi-Z. MB81F64842D-75/-102/-10 FUNCTIONAL DESCRIPTION SDRAM BASIC FUNCTION Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode, and mode register. The synchronized operation is the fundamental difference. An SDRAM uses a clock input for the synchronization, where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each operation of DRAM is determined by their timing phase differences while each operation of SDRAM is determined by commands and all operations are referenced to a positive clock edge. Fig. 3 shows the basic timing diagram differences between SDRAMs and DRAMs. The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column addresses for the first access is set, following addresses are automatically generated by the internal column address counter. The mode register is to justify the SDRAM operation and function into desired system conditions. MODE REGISTER TABLE shows how SDRAM can be configured for system requirement by mode register programming. CLOCK (CLK) and CLOCK ENABLE (CKE) All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During idle state (all banks have been precharged), the Power Down mode (standby) is entered with CKE = Low and this will make extremely low standby current. CHIP SELECT (CS) CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, command signals are negated but internal operation such as burst cycle will not be suspended. If such a control isn't needed, CS can be tied to ground level. COMMAND INPUT (RAS, CAS and WE) Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operation, such as Row address strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at a rising edge of the CLK determines SDRAM operation. Refer to FUNCTIONAL TRUTH TABLE in page 5. ADDRESS INPUT (A0 to A11) Address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix. A total of fourteen address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV), twelve Row addresses are initially latched and the remainder of nine Column addresses are then latched by a Column address strobe command of either a Read command (READ or READA) or Write command (WRIT or WRITA). BANK SELECT (A12, A13) This SDRAM has four banks and each bank is organized as 2 M words by 8-bit. Bank selection by A13, A12 occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT or WRITA), and precharge command (PRE). 15 MB81F64842D-75/-102/-10 DATA INPUT AND OUTPUT (DQ0 to DQ7) Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input: tRAC ; from the bank active command when tRCD (min) is satisfied. (This parameter is reference only.) tCAC ; from the read command when tRCD is greater than tRCD (min). (This parameter is reference only.) tAC ; from the clock edge after tRAC and tCAC. The polarity of the output data is identical to that of the input. Data is valid between access time (determined by the three conditions above) and the next positive clock edge (tOH). DATA I/O MASK (DQM) DQM is an active high enable input and has an output disable and input mask function. During burst cycle and when DQM = High is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. BURST MODE OPERATION AND BURST TYPE The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address and by automatic strobing column address. Access time and cycle time of Burst mode is specified as tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which defines burst type and burst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: Current Stage Next Stage Burst Read Burst Read Burst Read Burst Write Method (Assert the following command) Read Command 1st Step Mask Command (Normally 3 clock cycles) 2nd Step Write Command after lOWD Burst Write Burst Write Write Command Burst Write Burst Read Read Command Burst Read Precharge Precharge Command Burst Write Precharge Precharge Command The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address (= 0). The interleave mode is a scrambled decoding scheme for A0 and A2. If the first access of column address is even (0), the next address will be odd (1), or vice-versa. (Continued) 16 MB81F64842D-75/-102/-10 (Continued) When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write operation. The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address (= 0). Burst Length 2 4 8 Starting Column Address A2 A 1 A 0 Sequential Mode Interleave X X 0 0-1 0-1 X X 1 1-0 1-0 X 0 0 0-1-2-3 0-1-2- 3 X 0 1 1-2-3-0 1-0-3-2 X 1 0 2-3-0-1 2-3-0-1 X 1 1 3-0-1-2 3-2-1-0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 FULL COLUMN BURST AND BURST STOP COMMAND (BST) The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same column. If burst mode reaches end of column address, then it wraps round to first column address (= 0) and continues to count until interrupted by the news read (READ) /write (WRIT), precharge (PRE), or burst stop (BST) command. The selection of Auto-precharge option is illegal during the full column burst operation except write command at BURST READ & SINGLE WRITE mode. The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to Bank Active. When read mode is interrupted by BST command, the output will be in High-Z. For the detail rule, please refer to TIMING DIAGRAM - 8. When write mode is interrupted by BST command, the data to be applied at the same time with BST command will be ignored. BURST READ & SINGLE WRITE The burst read and single write mode provides single word write operation regardless of its burst length. In this mode, burst read operation does not be affected by this mode. 17 MB81F64842D-75/-102/-10 PRECHARGE AND PRECHARGE OPTION (PRE, PALL) SDRAM memory core is the same as conventional DRAMs', requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE). With the Precharge command, SDRAM will automatically be in standby state after precharge time (tRP). The precharged bank is selected by combination of AP and A12, A13 when Precharge command is asserted. If AP = High, all banks are precharged regardless of A12, A13 (PALL). If AP = Low, a bank to be selected by A12, A13 is precharged (PRE). The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command assertion. This auto precharge is entered by AP = High when a read or write command is asserted. Refer to FUNCTIONAL TRUTH TABLE. AUTO-REFRESH (REF) Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be asserted every 16 s or a total 4096 refresh commands within a 64 ms period. SELF-REFRESH ENTRY (SELF) Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the refresh function until cancelled by SELFX. The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once SDRAM enters the self-refresh mode, all inputs except for CKE will be "don't care" (either logic high or low level state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF command should only be issued after last read data has been appeared on DQ. SELF-REFRESH EXIT (SELFX) To exit self-refresh mode, apply minimum tPDE after CKE brought high, and then the NOP command (NOP) or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High within one tRC period after tPDE. Refer to Timing Diagram for the detail. It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period. MODE REGISTER SET (MRS) The mode register of SDRAM provides a variety of different operations. The register consists of four operation fields; Burst Length, Burst Type, CAS latency, and Operation Code. Refer to MODE REGISTER TABLE in page 33. The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power). MRS command should only be issued on condition that all DQ is in Hi-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field after initialization of SDRAM. Refer to POWER-UP INITIALIZATION below. 18 MB81F64842D-75/-102/-10 POWER-UP INITIALIZATION The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input. 2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 s. 3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL). 4. Assert minimum of 2 Auto-refresh command (REF). 5. Program the mode register by Mode Register Set command (MRS). In addition, it is recommended DQM and CKE to track VCC to insure that output is High-Z state. The Mode Register Set command (MRS) can be set before 2 Auto-refresh command (REF). 19 MB81F64842D-75/-102/-10 Fig. 2 - BASIC TIMING FOR CONVENTIONAL DRAM VS SYNCHRONOUS DYNAMIC RAM <SDRAM> Active Read/Write Precharge CLK CKE H H H tHI tSI CS RAS CAS H : Read WE L : Write Address BA *(A13, A12) RA BA *(A13, A12) CA CAS Latency = 2 BA *(A13, A12) AP (A10) DQ Burst Length = 4 <Conventional DRAM> Row Adress Select RAS CAS DQ 20 Column Address Select Precharge MB81F64842D-75/-102/-10 tRCD tRCD 1 *2 READA BL + tRP tDAL PALL tRP REF SELFX tRCD tRCD tRAS tRAS 4 1 1 *1 4 *2 tWR 1 1 tDPL tRP *2 BL + tRP BL + tRP tDAL tDAL tDPL *3 *3 *3 tRP tRP tRP tRP tRP tRP tRP tRP tRC tRC tRC tRC tRC tRC tRC tRC tRC tRC *3 Notes: *1. *2. *3. *4. tRSC tDAL *3 tRP tRSC *2 tWR PRE tRSC BL + tRP WRIT WRITA 1 tRSC *4 *1 READ SELF ACTV REF *4 PALL WRITA WRIT tRSC READA tRSC PRE MRS READ First command ACTV Second command (same bank) MRS MINIMUM CLOCK LATENCY OR DELAY TIME FOR 1 BANK OPERATION *3 tRP *3 *3 Assume no I/O conflict. If tRP tCK, minimum latency is a sum of BL + CL. Assume output is in High-Z state. Assume tRAS is satisfied. Illegal Command 21 MB81F64842D-75/-102/-10 *1 ACTV tRRD *1 READ 1 *9 *1 *4 BL+ tRP READA *2 1 *9 *1 *4 BL+ tRP WRITA 1 *1 PRE tRP *2 *2 *2 *1 1 1 1 REF SELF *2 tRAS *7 *8 1 *1 *4 1 BL+ tRP *7 1 *8 *1 1 1 BL+ tRP *2 1 *2 1 tRAS *1 BL+ tRP *1 tRP *5 *1 tRP *1 *6 *1 *6 PALL tRP tRP 1 1 tRP tRP REF tRC tRC tRC tRC tRC tRC SELFX tRC tRC tRC tRC Notes: *1. *2. *3. *4. *5. *6. *7. *8. *9. Assume other bank (second command will be asserted) is in idle state. Assume other bank (second command will be asserted) is in active state. Assume no I/O conflict. If tRP tCK, minimum latency is a sum of BL + CL. Assume PALL command does not affect any operation on other banks. Assume output is in High-Z state. Assume tRAS of other bank (second command will be asserted) is satisfied. Assume tRAS (ACTV to PALL) is satisfied. If other bank (second command will be asserted) should be interrupted, tRAS of own bank is satisfied. Illegal Command 22 *1 *4 BL+ tRP 1 *2 *2 1 PALL WRITA 1 *7 *2 1 *2 *2 1 *2 *3 *2 *2 tRSC 1 4 1 tRSC *2 *3 *2 *3 *2 tRSC 1 4 4 1 1 *2 *3 *2 tRSC *2 1 4 1 1 *1 1 1 1 *2 *2 *2 *1 *1 WRIT 1 1 1 *2 *2 1 WRIT tRSC READA tRSC PRE MRS READ First command ACTV Second command (other bank) MRS MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION MB81F64842D-75/-102/-10 Fig. 3 - STATE DIAGRAM (Simplified for Single BANK Operation State Diagram) MRS SELF MODE REGISTER SET SELF REFRESH SELFX IDLE REF CKE\(PD) CKE AUTO REFRESH ACTV POWER DOWN CKE\ BANK ACTIVE SUSPEND BANK ACTIVE CKE BST BST READ WRIT READ WRIT WRITA CKE\ CKE CKE\ CKE READA WRITE WITH AUTO PRECHARGE PRE or PALL POWER ON READ CKE\ CKE WRIT WRITA WRITE SUSPEND READA READ WRITE PRE or PALL WRITA PRE or PALL WRITE SUSPEND READ SUSPEND READA READ WITH CKE\ AUTO CKE PRECHARGE READ SUSPEND PRE or PALL PRECHARGE POWER APPLIED DEFINITION OF ALLOWS Manual Input Automatic Sequence 23 MB81F64842D-75/-102/-10 ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Value Unit Voltage of VCC Supply Relative to VSS VCC, VCCQ -0.5 to +4.6 V Voltage at Any Pin Relative to VSS VIN, VOUT -0.5 to +4.6 V Short Circuit Output Current IOUT 50 mA Power Dissipation PD 1.3 W TSTG -55 to +125 C Storage Temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS (Referenced to VSS) Parameter Notes Symbol Min. Typ. Max. Unit VCC, VCCQ 3.0 3.3 3.6 V VSS, VSSQ 0 0 0 V Supply Voltage Input High Voltage *1 VIH 2.0 -- VCC + 0.5 V Input Low Voltage *2 VIL -0.5 -- 0.8 V TA 0 -- 70 C Ambient Temperature Notes: *1. *2. Overshoot limit: VIH (max) = VCC +1.5 V with a pulsewidth 5 ns. Undershoot limit: VIL (min) = -1.5 V with a pulsewidth 5 ns. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. CAPACITANCE (TA = 25C, f = 1 MHz) Parameter 24 Symbol Min. Typ. Max. Unit Input Capacitance, Except for CLK CIN1 2.5 -- 5.0 pF Input Capacitance for CLK CIN2 2.5 -- 4.0 pF I/O Capacitance CI/O 4.0 -- 6.5 pF MB81F64842D-75/-102/-10 DC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Note 1, 2 Parameter Output High Voltage Output Low Voltage Symbol Condition VOH(DC) VOL(DC) IOH = -2 mA IOL = 2 mA 0 V VIN VCC; All other pins not under test = 0 V 0 V VIN VCC; Data out disabled Burst: Length = 4 tRC = min for BL = 4 tCK = min One bank active Outputs open Addresses changed up to 3-times during tRC (min) 0 V VIN VCC Input Leakage Current (Any Input) ILI Output Leakage Current ILO MB81F64842D-75 MB81F64842D-102 ICC1S MB81F64842D-10 Operating Current (Average Power Supply Current) MB81F64842D-75 MB81F64842D-102 ICC1D MB81F64842D-10 ICC2P ICC2PS Precharge Standby Current (Power Supply Current) MB81F64842D-75 MB81F64842D-102 ICC2N MB81F64842D-10 ICC2NS Burst: Length = 4 (each Bank) tRC = min for BL = 4 (each Bank) tCK = min 2 banks active Outputs open Addresses changed up to 6-times during tRC (min) 0 V VIN VCC CKE = VIL All banks idle tCK = min Power down mode 0 V VIN VCC CKE = VIL All banks idle CLK = VIH or VIL Power down mode 0 V VIN VCC Value Unit Min. 2.4 -- Max. -- 0.4 -5 5 A -5 5 A V V 120 -- 110 mA 100 210 -- 180 mA 160 -- 1.0 mA -- 1.0 mA CKE = VIH All banks idle, tCK = min NOP commands only, Input signals (except to CMD) are changed one time during 3 clock cycles 0 V VIN VCC -- CKE = VIH All banks idle CLK = VIH or VIL Input signal are stable 0 V VIN VCC -- 25 20 mA 20 5 mA (Continued) 25 MB81F64842D-75/-102/-10 (Continued) Parameter Symbol ICC3P ICC3PS Active Standby Current (Power Supply Current) MB81F64842D-75 MB81F64842D-102 ICC3N MB81F64842D-10 ICC3NS MB81F64842D-75 Burst mode Current MB81F64842D-102 (Average Power Supply Current) MB81F64842D-10 26 ICC4 MB81F64842D-75 Refresh Current #1 MB81F64842D-102 (Average Power Supply Current) MB81F64842D-10 ICC5 Refresh Current #2 (Average Power Supply Current) ICC6 Condition CKE = VIL Any bank active tCK = min 0 V VIN VCC CKE = VIL Any bank active CLK = VIH or VIL 0 V VIN VCC CKE = VIH Any bank active tCK = min NOP commands only, Input signals (except to CMD) are changed one time during 3 clock cycles 0 V VIN VCC CKE = VIH Any bank active CLK = VIH or VIL 0 V VIN VCC tCK = min Burst Length = 4 Outputs open Multiple-banks active Gapless data 0 V VIN VCC Auto-refresh; tCK = min tRC = min 0 V VIN VCC Self-refresh; tCK = min CKE 0.2 V 0 V VIN VCC Value Unit Min. Max. -- 4 mA -- 3 mA 30 -- 25 mA 25 -- 10 mA 140 -- 120 mA 120 -- 170 160 mA 150 -- 1 mA MB81F64842D-75/-102/-10 AC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Note 2, 3, 4 MB81F64842D-75 Parameter Notes MB81F64842D-102 MB81F64842D-10 Symbol Unit Min. CL = 2 tCK2 Max. 11 Min. 10 -- Clock Period Max. Min. Max. 15 -- tCK3 7.5 Clock High Time tCH 2.5 -- 3 -- 3 -- ns Clock Low Time tCL 2.5 -- 3 -- 3 -- ns Input Setup Time tSI 2 -- 2 -- 2 -- ns Input Hold Time tHI 1 -- 1 -- 1 -- ns 8 ns 6 ns -- ns 8 ns 6 ns CL = 3 Access Time from Clock (tCK = min) CL = 2 tAC2 *5, 6 7 -- CL = 3 Output in Low-Z 0 -- 3 CL = 3 6 0 -- 0 6 3 6 tHZ3 ns -- 6 7 tHZ2 *7 10 -- 6 tAC3 tLZ CL = 2 Output in High-Z 10 ns -- 3 6 ns CL = 2 Output Hold Time tOH 3 -- 3 -- 3 -- CL = 3 ns Time between Auto-Refresh command interval tREFI -- 15.6 -- 15.6 -- 15.6 s Time between Refresh tREF -- 64 -- 64 -- 64 ms tT 0.5 2 0.5 2 0.5 2 ns tCKSP 2.5 -- 3 -- 3 -- ns Transition Time CKE Setup Time for Power Down Exit Time 27 MB81F64842D-75/-102/-10 BASE VALUES FOR CLOCK COUNT/LATENCY MB81F64842D-75 Parameter Notes MB81F64842D-10 Unit Min. Max. Min. Max. Min. Max. tRC 66 -- 70 -- 80 -- ns RAS Precharge Time tRP 22 -- 20 -- 30 -- ns RAS Active Time tRAS 44 100000 50 100000 50 100000 ns tRCD 22 -- 20 -- 30 -- ns Write Recovery Time tWR 7.5 -- 10 -- 10 -- ns RAS to RAS Bank Active Delay Time tRRD 15 -- 20 -- 20 -- ns Data-in to Precharge Lead Time tDPL 7.5 -- 10 -- 10 -- ns CL=2 tDAL2 1 cyc + tRP -- 1 cyc + tRP -- 1 cyc + tRP -- ns CL=3 tDAL3 2 cyc + tRP -- 2 cyc + tRP -- 2 cyc + tRP -- ns tRSC 15 -- 20 -- 20 -- ns RAS Cycle Time RAS to CAS Delay Time *8 *9 Data-in to Active/Refresh Command Period Mode Resister Set Cycle Time CLOCK COUNT FORMULA Clock 28 MB81F64842D-102 Symbol Note 10 Base Value Clock Period (Round off a whole number) MB81F64842D-75/-102/-10 LATENCY - FIXED VALUES (The latency values on these parameters are fixed regardless of clock period.) Parameter Symbol MB81F64842D-75 MB81F64842D-102 MB81F64842D-10 Unit CKE to Clock Disable lCKE 1 1 1 cycle DQM to Output in High-Z lDQZ 2 2 2 cycle DQM to Input Data Delay lDQD 0 0 0 cycle Last Output to Write Command Delay lOWD 2 2 2 cycle Write Command to Input Data Delay lDWD 0 0 0 cycle Precharge to Output in High-Z Delay CL = 2 lROH2 2 2 2 cycle CL = 3 lROH3 3 3 3 cycle Burst Stop Command to Output in High-Z Delay CL = 2 lBSH2 2 2 2 cycle CL = 3 lBSH3 3 3 3 cycle CAS to CAS Delay (min) lCCD 1 1 1 cycle CAS Bank Delay (min) lCBD 1 1 1 cycle Notes: *1. *2. *3. *4. *5. *6. *7. *8. *9. *10. Notes ICC depends on the output termination or load conditions, clock cycle rate, signal clocking rate; the specified values are obtained with the output open and no termination register. An initial pause (DESL or NOP) of 200 s is required after power-up followed by a minimum of eight Auto-refresh cycles. AC characteristics assume tT = 1 ns and 50 pF of capacitive load. 1.4 V is the reference level for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max). (See Fig. 5) Maximum value of CL = 2 depends on tCK. tAC also specifies the access time at burst mode except for first access. Specified where output buffer is no longer driven. tOH, tLZ, and tHZ define the times at which the output level achieves 200 mV. Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP). Operation within the tRCD (min) ensures that access time is detetermined by tRCD (min) + tAC (max); If tRCD is greater than the specified tRCD (min), access time is determined by tAC. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). 29 MB81F64842D-75/-102/-10 Fig. 4 - EXAMPLE OF AC TEST LOAD CIRCUIT R1 = 50 Output 1.4 V CL = 50 pF LVTTL Note: AC characteristics are measured in this condition. This load circuits are not applicable for VOH and VOL. 30 MB81F64842D-75/-102/-10 Fig. 5 - TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME tCK tCH tCL 2.0 V 1.4 V CLK 0.8 V tSI tHI 2.0 V Input (Control, Addr. & Data) 1.4 V 0.8 V tAC tHZ tOH tLZ 2.4 V Output 1.4 V 0.4 V Note: Reference level of input signal is 1.4 V for LVTTL. Access time is measured at 1.4 V for LVTTL. Fig. 6 - TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT CLK Don't Care tCKSP (min) 1 clock (min) CKE Command Don't Care NOP NOP ACTV 31 MB81F64842D-75/-102/-10 Fig. 7 - TIMING DIAGRAM, PULSE WIDTH CLK Input (Control) tRC, tRP, tRAS, tRCD, tWR, tREF, tDPL, tDAL, tRSC, tRRD, tCKSP COMMAND COMMAND Note: These parameter are a limit value of the rising edge of the clock from one command input to next input. tCKSP is the latency value from the rising edge of CKE. Measurement reference voltage is 1.4 V. Fig. 8 - TIMING DIAGRAM, ACCESS TIME CLK tRAC RAS tRCD tCAC CAS (CAS Latency -1) x tCK tAC DQ (Output) Note: tRAC and tCAC are reference values. Data can be obtained after both tCAC = (CL-1) x tCK and tAC is satisfied. 32 Q (Valid) MB81F64842D-75/-102/-10 MODE REGISTER TABLE MODE REGISTER SET A13 A12 A11 A10 A9 A8 A7 0 0 0 0 Opcode 0 0 A9 0 1 A6 A5 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 A6 A5 A4 CL A4 CAS Latency 0 1 0 1 0 1 0 1 Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Op-code Burst Read & Burst Write Burst Read & Single Write A3 A2 A1 BT A0 ADDRESS MODE REGISTER BL Burst Length A2 0 0 0 0 1 1 1 1 A3 0 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 BT = 0 BT = 1 1 2 4 8 Reserved Reserved Reserved Full Column Reserved 2 4 8 Reserved Reserved Reserved Reserved Burst Type Sequential (Wrap round, Binary-up) Interleave (Wrap round, Binary-up) Notes: 1. When A9 = 1, burst length at Write is always one regardless of BL value. 2. BL = 1 and Full Column are not applicable to the interleave mode. 33 MB81F64842D-75/-102/-10 TIMING DIAGRAM - 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4) CLK CKE *1 ICKE (1 clock)*1 ICKE (1 clock) CLK (Internal) *2 DQ (Read) Q1 DQ (Write) D1 Q2 *2 *2 (NO CHANGE) NOT *3 WRITTEN D2 *2 Q3 (NO CHANGE) NOT *3 WRITTEN D3 Q4 D4 Notes: *1. The latency of CKE (lCKE) is one clock. *2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output remain the same data. *3. During the write mode, data at the next clock of CSUS command is ignored. TIMING DIAGRAM - 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT CLK 1 clock (min) tCKSP CKE Command NOP *1 PD(NOP) *2 DON'T CARE NOP *3 NOP *3 ACTV tREF (max) Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode. *2. Precharge command can be posted in conjunction with CKE after the last read data have been appeared on DQ. *3. The ACTV command can be latched after tCKSP (min) + 1 clock (min). It is recommended to apply NOP command in conjunction with CKE. 34 MB81F64842D-75/-102/-10 TIMING DIAGRAM - 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY CLK RAS ICCD (1 clock) tRCD (min) ICCD ICCD ICCD CAS Address COLUMN ADDRESS ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS Note: CAS to CAS address delay can be one or more clock period. TIMING DIAGRAM - 4 : DIFFERENT BANK ADDRESS INPUT DELAY CLK tRRD (min) RAS tRCD (min) ICBD ICBD CAS tRCD (min) Address A12, A13(BA) ROW ADDRESS ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS Bank 0 Bank 1 Bank 0 Bank 1 Bank 0 Bank 1 35 MB81F64842D-75/-102/-10 TIMING DIAGRAM - 5 : DQM - INPUT MASK AND OUTPUT DISABLE (@ BL = 4) CLK DQM (@ Read) IDQZ (2 clocks) DQ (@ Read) Q1 Q2 Hi-Z Q4 End of burst DQM (@ Write) IDQD (same clock) DQ (@ Write) D1 MASKED D3 D4 End of burst TIMING DIAGRAM - 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK) CLK tRAS (min) Command 36 ACTV PRECHARGE MB81F64842D-75/-102/-10 TIMING DIAGRAM - 7 : READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4) CLK Command PRECHARGE IROH (2 clocks) DQ Command Q1 Hi-Z PRECHARGE IROH (2 clocks) DQ Q1 Command Q2 Hi-Z PRECHARGE IROH (2 clocks) DQ Q1 Q2 Command Hi-Z Q3 PRECHARGE No effect (end of burst) DQ Q1 Q2 Q3 Q4 Note: In case of CL = 2, the lROH is 2 clock. In case of CL = 3, the lROH is 3 clock. 37 MB81F64842D-75/-102/-10 TIMING DIAGRAM - 8 : READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL = Full Column) CLK Command (CL = 2) BST lBSH (2 clocks) DQ Qn-2 Qn-1 Command (CL = 3) Qn Qn+1 Hi-Z BST lBSH (3 clocks) Hi-Z DQ Qn-2 Qn-1 Qn Qn+1 Qn+2 TIMING DIAGRAM - 9 : WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ CL = 2) CLK Command DQ 38 BST LAST DATA-IN Masked by BST COMMAND MB81F64842D-75/-102/-10 TIMING DIAGRAM - 10 : WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 3) CLK Command ACTIVE PRECHARGE tDPL (min) DQ DATA-IN LAST DATA-IN tRP (min) MASKED by PRE Note: The precharge command (PRE) should only be issued after the tDPL of final data input, is satisfied. TIMING DIAGRAM - 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 3, BL = 4) CLK IOWD (2 clocks) Command DQM Write Read Note 1 Note 2 Note 3 IDQZ (2 clocks) DQ IDWD (same clock) DATA IN DATA OUT DATA IN Masked Notes: 1. First DQM makes high-impedance state High-Z between last output and first input data. 2. Second DQM makes internal output data mask to avoid bus contention. 3. Third DQM in illustrated above also makes internal output data mask. If burst read ends (final data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus contention. 39 MB81F64842D-75/-102/-10 TIMING DIAGRAM - 12 : WRITE TO READ TIMING (EXAMPLE @ CL = 3, BL = 4) CLK tWR (min) Command WRITE READ DQM (CL-1) x tCK DQ D1 D2 D3 Masked by Read tAC (max) Q1 Note: Read command should be issued after tWR of final data input is satisfied if read command is applied to the same bank. 40 Q2 MB81F64842D-75/-102/-10 TIMING DIAGRAM - 13 : READ WITH AUTO-PRECHARGE (EXAPLE @ CL = 2, BL = 2 Applied to same bank) CLK tRAS (min) Command ACTV tRP (min) READA NOP or DESL 2 clocks *1 (same value as BL) ACTV BL+tRP (min) *2 DQM DQ Q1 Q2 Notes: *1. Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the same as Burst Length (BL) after the READA command is asserted. *2. Next ACTV command should be issued after BL+tRP (min) from READA command. TIMING DIAGRAM - 14 : WRITE WITH AUTO-PRECHARGE (EXAMPLE @ CL = 2, BL = 2 Applied to same bank) tRAS (min) CLK tDPL (min) *1 tDAL (min) BL+tRP (min) *5 Command ACTV WRITA NOP or DESL ACTV DQM DQ D1 D2 Notes: *1. Precharge at write with Auto-precharge is started after the tDPL from the end of burst. *2. Even if the final data is masked by DQM, the precharge does not start the clock of final data input. *3. Once auto precharge command is asserted, no new command within the same bank can be issued. *4. Auto-precharge command doesn't affect at full column burst operation except Burst READ & Single Write. *5. Next command should be issued after BL+ tRP (min) at CL = 2, BL+1+tRP (min) at CL = 3 from WRITA command. 41 MB81F64842D-75/-102/-10 TIMING DIAGRAM - 15 : AUTO-REFRESH TIMING CLK Command REF *1 NOP *3 NOP *4 NOP REF tRC (min) A12, A13(BA) Command *4 NOP tRC (min) DON'T CARE BA DON'T CARE Notes: *1. All banks should be precharged prior to the first Auto-refresh command (REF). *2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter. *3. Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode. *4. Any activation command such as ACTV or MRS command other than REF command should be asserted after tRC from the last REF comand. TIMING DIAGRAM - 16 : SELF-REFRESH ENTRY AND EXIT TIMING CLK tCKSP (min) tSI (min) CKE tRC (min) *4 Command NOP *1 SELF DON'T CARE NOP *2 SELFX NOP *3 Command Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry command (SELF). *2. The Self-refresh Exit command (SELFX) is latched after tCKSP (min). It is recommended to apply NOP command in conjunction with CKE. *3. Either NOP or DESL command can be used during tRC period. *4. CKE should be held high within one tRC period after tCKSP. 42 MB81F64842D-75/-102/-10 TIMING DIAGRAM - 17 : MODE REGISTER SET TIMING CLK tRSC Command Address MRS MODE NOP or DESL ACTV ROW ADDRESS Notes: The Mode Register Set command (MRS) should only be asserted after all banks have been precharged. 43 MB81F64842D-75/-102/-10 PACKAGE DIMENSION 54-pin plastic TSOP(II) (FPT-54P-M02) *: Resin protrusion. (Each side: 0.15 (.006) MAX) Dimensions in mm (inches) 44 MB81F64842D-75/-102/-10 MEMO 45 MB81F64842D-75/-102/-10 MEMO 46 MB81F64842D-75/-102/-10 MEMO 47 MB81F64842D-75/-102/-10 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9804 FUJITSU LIMITED Printed in Japan 48 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.