i.MX28 Applications Processor Reference Manual Document Number: MCIMX28RM Rev 2, 08/2013 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1 Product Overview 1.1 i.MX28 Overview.........................................................................................................................................................95 1.2 Hardware Features........................................................................................................................................................95 1.3 i.MX28 Product Features..............................................................................................................................................100 1.3.1 ARM9 CPU Subsystem...............................................................................................................................102 1.3.2 System Buses...............................................................................................................................................102 1.3.2.1 AXI Bus Segments...................................................................................................................103 1.3.2.2 AHB Buses...............................................................................................................................104 1.3.2.3 APB Buses...............................................................................................................................105 1.3.3 On-Chip RAM and ROM.............................................................................................................................105 1.3.4 On-Chip One-Time-Programmable (OCOTP) ROM..................................................................................106 1.3.5 External Memory Controller (EMI).............................................................................................................107 1.3.6 Interrupt Collector........................................................................................................................................108 1.3.7 Default First-Level Page Table....................................................................................................................108 1.3.8 DMA Controller...........................................................................................................................................108 1.3.9 Clock Generation Subsystem.......................................................................................................................109 1.3.10 Power Management Unit.............................................................................................................................110 1.3.11 Ethernet Interfaces.......................................................................................................................................110 1.3.12 CAN Interfaces............................................................................................................................................111 1.3.13 USB Interfaces.............................................................................................................................................111 1.3.14 General-Purpose Media Interface (GPMI)...................................................................................................112 1.3.15 Hardware Acceleration for ECC for Robust External Storage....................................................................112 1.3.15.1 Bose Ray-Choudhury Hocquenghem ECC Engine.................................................................113 1.3.16 Data Co-Processor (DCP)--Memory Copy, Crypto....................................................................................113 1.3.17 I2C Interface................................................................................................................................................114 1.3.18 General-Purpose Input/Output (GPIO)........................................................................................................114 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 3 Section number 1.3.19 Title Page Display and Capture Processing..................................................................................................................114 1.3.19.1 Display Controllers / LCD Interfaces (LCDIF).......................................................................115 1.3.19.2 Pixel Processing Pipeline (PXP)..............................................................................................116 1.3.20 SPDIF Transmitter.......................................................................................................................................117 1.3.21 Dual Serial Audio Interfaces........................................................................................................................117 1.3.22 Rotary Decoder............................................................................................................................................118 1.3.23 UARTs.........................................................................................................................................................118 1.3.24 Low-Resolution ADC, Touch-Screen Interface and Temperature Sensor...................................................118 1.3.25 High Speed ADC (HSADC) Controller.......................................................................................................119 1.3.26 Pulse Width Modulator (PWM) Controller.................................................................................................119 Chapter 2 ARM CPU Complex 2.1 Overview.......................................................................................................................................................................121 2.2 ARM 926 Processor Core.............................................................................................................................................121 2.3 JTAG Debugger............................................................................................................................................................124 2.4 2.3.1 JTAG READ ARM ID (TAP).....................................................................................................................125 2.3.2 JTAG Hardware Reset.................................................................................................................................125 2.3.3 JTAG Interaction with CPUCLK.................................................................................................................125 Embedded Trace Macrocell (ETM) Interface...............................................................................................................125 Chapter 3 Default First-level Page Table (DFLPT) 3.1 Default First-Level Page Table (DFLPT) Overview....................................................................................................127 3.2 Operation.......................................................................................................................................................................128 3.2.1 Top-Level Symbol and Functional Overview..............................................................................................130 3.2.2 Memory Map................................................................................................................................................131 3.2.3 Default First-Level Page Table PIO Register Map Entry 2048...................................................................134 Chapter 4 Memory Map 4.1 Memory Map Overview................................................................................................................................................135 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 4 Freescale Semiconductor, Inc. Section number Title Page Chapter 5 Interrupt Collector (ICOLL) 5.1 Interrupt Collector (ICOLL) Overview........................................................................................................................139 5.2 Operation.......................................................................................................................................................................140 5.2.1 Nesting of Multi-Level IRQ Interrupts........................................................................................................143 5.2.2 FIQ Generation............................................................................................................................................145 5.2.3 Interrupt Sources..........................................................................................................................................146 5.2.4 CPU Wait-for-Interrupt Mode.....................................................................................................................149 5.3 Behavior During Reset..................................................................................................................................................151 5.4 Programmable Registers...............................................................................................................................................151 5.4.1 Interrupt Collector Interrupt Vector Address Register (HW_ICOLL_VECTOR)......................................158 5.4.2 Interrupt Collector Level Acknowledge Register (HW_ICOLL_LEVELACK).........................................159 5.4.3 Interrupt Collector Control Register (HW_ICOLL_CTRL)........................................................................160 5.4.4 Interrupt Collector Interrupt Vector Base Address Register (HW_ICOLL_VBASE).................................162 5.4.5 Interrupt Collector Status Register (HW_ICOLL_STAT)...........................................................................163 5.4.6 Interrupt Collector Raw Interrupt Input Register 0 (HW_ICOLL_RAW0)................................................164 5.4.7 Interrupt Collector Raw Interrupt Input Register 1 (HW_ICOLL_RAW1)................................................164 5.4.8 Interrupt Collector Raw Interrupt Input Register 2 (HW_ICOLL_RAW2)................................................165 5.4.9 Interrupt Collector Raw Interrupt Input Register 3 (HW_ICOLL_RAW3)................................................166 5.4.10 Interrupt Collector Interrupt Register 0 (HW_ICOLL_INTERRUPT0).....................................................167 5.4.11 Interrupt Collector Interrupt Register 1 (HW_ICOLL_INTERRUPT1).....................................................168 5.4.12 Interrupt Collector Interrupt Register 2 (HW_ICOLL_INTERRUPT2).....................................................170 5.4.13 Interrupt Collector Interrupt Register 3 (HW_ICOLL_INTERRUPT3).....................................................171 5.4.14 Interrupt Collector Interrupt Register 4 (HW_ICOLL_INTERRUPT4).....................................................173 5.4.15 Interrupt Collector Interrupt Register 5 (HW_ICOLL_INTERRUPT5).....................................................174 5.4.16 Interrupt Collector Interrupt Register 6 (HW_ICOLL_INTERRUPT6).....................................................176 5.4.17 Interrupt Collector Interrupt Register 7 (HW_ICOLL_INTERRUPT7).....................................................177 5.4.18 Interrupt Collector Interrupt Register 8 (HW_ICOLL_INTERRUPT8).....................................................179 5.4.19 Interrupt Collector Interrupt Register 9 (HW_ICOLL_INTERRUPT9).....................................................180 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 5 Section number Title Page 5.4.20 Interrupt Collector Interrupt Register 10 (HW_ICOLL_INTERRUPT10).................................................182 5.4.21 Interrupt Collector Interrupt Register 11 (HW_ICOLL_INTERRUPT11).................................................183 5.4.22 Interrupt Collector Interrupt Register 12 (HW_ICOLL_INTERRUPT12).................................................185 5.4.23 Interrupt Collector Interrupt Register 13 (HW_ICOLL_INTERRUPT13).................................................186 5.4.24 Interrupt Collector Interrupt Register 14 (HW_ICOLL_INTERRUPT14).................................................188 5.4.25 Interrupt Collector Interrupt Register 15 (HW_ICOLL_INTERRUPT15).................................................189 5.4.26 Interrupt Collector Interrupt Register 16 (HW_ICOLL_INTERRUPT16).................................................191 5.4.27 Interrupt Collector Interrupt Register 17 (HW_ICOLL_INTERRUPT17).................................................192 5.4.28 Interrupt Collector Interrupt Register 18 (HW_ICOLL_INTERRUPT18).................................................194 5.4.29 Interrupt Collector Interrupt Register 19 (HW_ICOLL_INTERRUPT19).................................................195 5.4.30 Interrupt Collector Interrupt Register 20 (HW_ICOLL_INTERRUPT20).................................................197 5.4.31 Interrupt Collector Interrupt Register 21 (HW_ICOLL_INTERRUPT21).................................................198 5.4.32 Interrupt Collector Interrupt Register 22 (HW_ICOLL_INTERRUPT22).................................................200 5.4.33 Interrupt Collector Interrupt Register 23 (HW_ICOLL_INTERRUPT23).................................................201 5.4.34 Interrupt Collector Interrupt Register 24 (HW_ICOLL_INTERRUPT24).................................................203 5.4.35 Interrupt Collector Interrupt Register 25 (HW_ICOLL_INTERRUPT25).................................................204 5.4.36 Interrupt Collector Interrupt Register 26 (HW_ICOLL_INTERRUPT26).................................................206 5.4.37 Interrupt Collector Interrupt Register 27 (HW_ICOLL_INTERRUPT27).................................................207 5.4.38 Interrupt Collector Interrupt Register 28 (HW_ICOLL_INTERRUPT28).................................................209 5.4.39 Interrupt Collector Interrupt Register 29 (HW_ICOLL_INTERRUPT29).................................................210 5.4.40 Interrupt Collector Interrupt Register 30 (HW_ICOLL_INTERRUPT30).................................................212 5.4.41 Interrupt Collector Interrupt Register 31 (HW_ICOLL_INTERRUPT31).................................................213 5.4.42 Interrupt Collector Interrupt Register 32 (HW_ICOLL_INTERRUPT32).................................................215 5.4.43 Interrupt Collector Interrupt Register 33 (HW_ICOLL_INTERRUPT33).................................................216 5.4.44 Interrupt Collector Interrupt Register 34 (HW_ICOLL_INTERRUPT34).................................................218 5.4.45 Interrupt Collector Interrupt Register 35 (HW_ICOLL_INTERRUPT35).................................................219 5.4.46 Interrupt Collector Interrupt Register 36 (HW_ICOLL_INTERRUPT36).................................................221 5.4.47 Interrupt Collector Interrupt Register 37 (HW_ICOLL_INTERRUPT37).................................................222 5.4.48 Interrupt Collector Interrupt Register 38 (HW_ICOLL_INTERRUPT38).................................................224 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 6 Freescale Semiconductor, Inc. Section number Title Page 5.4.49 Interrupt Collector Interrupt Register 39 (HW_ICOLL_INTERRUPT39).................................................225 5.4.50 Interrupt Collector Interrupt Register 40 (HW_ICOLL_INTERRUPT40).................................................227 5.4.51 Interrupt Collector Interrupt Register 41 (HW_ICOLL_INTERRUPT41).................................................228 5.4.52 Interrupt Collector Interrupt Register 42 (HW_ICOLL_INTERRUPT42).................................................230 5.4.53 Interrupt Collector Interrupt Register 43 (HW_ICOLL_INTERRUPT43).................................................231 5.4.54 Interrupt Collector Interrupt Register 44 (HW_ICOLL_INTERRUPT44).................................................233 5.4.55 Interrupt Collector Interrupt Register 45 (HW_ICOLL_INTERRUPT45).................................................234 5.4.56 Interrupt Collector Interrupt Register 46 (HW_ICOLL_INTERRUPT46).................................................236 5.4.57 Interrupt Collector Interrupt Register 47 (HW_ICOLL_INTERRUPT47).................................................237 5.4.58 Interrupt Collector Interrupt Register 48 (HW_ICOLL_INTERRUPT48).................................................239 5.4.59 Interrupt Collector Interrupt Register 49 (HW_ICOLL_INTERRUPT49).................................................240 5.4.60 Interrupt Collector Interrupt Register 50 (HW_ICOLL_INTERRUPT50).................................................242 5.4.61 Interrupt Collector Interrupt Register 51 (HW_ICOLL_INTERRUPT51).................................................243 5.4.62 Interrupt Collector Interrupt Register 52 (HW_ICOLL_INTERRUPT52).................................................245 5.4.63 Interrupt Collector Interrupt Register 53 (HW_ICOLL_INTERRUPT53).................................................246 5.4.64 Interrupt Collector Interrupt Register 54 (HW_ICOLL_INTERRUPT54).................................................248 5.4.65 Interrupt Collector Interrupt Register 55 (HW_ICOLL_INTERRUPT55).................................................249 5.4.66 Interrupt Collector Interrupt Register 56 (HW_ICOLL_INTERRUPT56).................................................251 5.4.67 Interrupt Collector Interrupt Register 57 (HW_ICOLL_INTERRUPT57).................................................252 5.4.68 Interrupt Collector Interrupt Register 58 (HW_ICOLL_INTERRUPT58).................................................254 5.4.69 Interrupt Collector Interrupt Register 59 (HW_ICOLL_INTERRUPT59).................................................255 5.4.70 Interrupt Collector Interrupt Register 60 (HW_ICOLL_INTERRUPT60).................................................257 5.4.71 Interrupt Collector Interrupt Register 61 (HW_ICOLL_INTERRUPT61).................................................258 5.4.72 Interrupt Collector Interrupt Register 62 (HW_ICOLL_INTERRUPT62).................................................260 5.4.73 Interrupt Collector Interrupt Register 63 (HW_ICOLL_INTERRUPT63).................................................261 5.4.74 Interrupt Collector Interrupt Register 64 (HW_ICOLL_INTERRUPT64).................................................263 5.4.75 Interrupt Collector Interrupt Register 65 (HW_ICOLL_INTERRUPT65).................................................264 5.4.76 Interrupt Collector Interrupt Register 66 (HW_ICOLL_INTERRUPT66).................................................266 5.4.77 Interrupt Collector Interrupt Register 67 (HW_ICOLL_INTERRUPT67).................................................267 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 7 Section number Title Page 5.4.78 Interrupt Collector Interrupt Register 68 (HW_ICOLL_INTERRUPT68).................................................269 5.4.79 Interrupt Collector Interrupt Register 69 (HW_ICOLL_INTERRUPT69).................................................270 5.4.80 Interrupt Collector Interrupt Register 70 (HW_ICOLL_INTERRUPT70).................................................272 5.4.81 Interrupt Collector Interrupt Register 71 (HW_ICOLL_INTERRUPT71).................................................273 5.4.82 Interrupt Collector Interrupt Register 72 (HW_ICOLL_INTERRUPT72).................................................275 5.4.83 Interrupt Collector Interrupt Register 73 (HW_ICOLL_INTERRUPT73).................................................276 5.4.84 Interrupt Collector Interrupt Register 74 (HW_ICOLL_INTERRUPT74).................................................278 5.4.85 Interrupt Collector Interrupt Register 75 (HW_ICOLL_INTERRUPT75).................................................279 5.4.86 Interrupt Collector Interrupt Register 76 (HW_ICOLL_INTERRUPT76).................................................281 5.4.87 Interrupt Collector Interrupt Register 77 (HW_ICOLL_INTERRUPT77).................................................282 5.4.88 Interrupt Collector Interrupt Register 78 (HW_ICOLL_INTERRUPT78).................................................284 5.4.89 Interrupt Collector Interrupt Register 79 (HW_ICOLL_INTERRUPT79).................................................285 5.4.90 Interrupt Collector Interrupt Register 80 (HW_ICOLL_INTERRUPT80).................................................287 5.4.91 Interrupt Collector Interrupt Register 81 (HW_ICOLL_INTERRUPT81).................................................288 5.4.92 Interrupt Collector Interrupt Register 82 (HW_ICOLL_INTERRUPT82).................................................290 5.4.93 Interrupt Collector Interrupt Register 83 (HW_ICOLL_INTERRUPT83).................................................291 5.4.94 Interrupt Collector Interrupt Register 84 (HW_ICOLL_INTERRUPT84).................................................293 5.4.95 Interrupt Collector Interrupt Register 85 (HW_ICOLL_INTERRUPT85).................................................294 5.4.96 Interrupt Collector Interrupt Register 86 (HW_ICOLL_INTERRUPT86).................................................296 5.4.97 Interrupt Collector Interrupt Register 87 (HW_ICOLL_INTERRUPT87).................................................297 5.4.98 Interrupt Collector Interrupt Register 88 (HW_ICOLL_INTERRUPT88).................................................299 5.4.99 Interrupt Collector Interrupt Register 89 (HW_ICOLL_INTERRUPT89).................................................300 5.4.100 Interrupt Collector Interrupt Register 90 (HW_ICOLL_INTERRUPT90).................................................302 5.4.101 Interrupt Collector Interrupt Register 91 (HW_ICOLL_INTERRUPT91).................................................303 5.4.102 Interrupt Collector Interrupt Register 92 (HW_ICOLL_INTERRUPT92).................................................305 5.4.103 Interrupt Collector Interrupt Register 93 (HW_ICOLL_INTERRUPT93).................................................306 5.4.104 Interrupt Collector Interrupt Register 94 (HW_ICOLL_INTERRUPT94).................................................308 5.4.105 Interrupt Collector Interrupt Register 95 (HW_ICOLL_INTERRUPT95).................................................309 5.4.106 Interrupt Collector Interrupt Register 96 (HW_ICOLL_INTERRUPT96).................................................311 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 8 Freescale Semiconductor, Inc. Section number Title Page 5.4.107 Interrupt Collector Interrupt Register 97 (HW_ICOLL_INTERRUPT97).................................................312 5.4.108 Interrupt Collector Interrupt Register 98 (HW_ICOLL_INTERRUPT98).................................................314 5.4.109 Interrupt Collector Interrupt Register 99 (HW_ICOLL_INTERRUPT99).................................................315 5.4.110 Interrupt Collector Interrupt Register 100 (HW_ICOLL_INTERRUPT100).............................................317 5.4.111 Interrupt Collector Interrupt Register 101 (HW_ICOLL_INTERRUPT101).............................................318 5.4.112 Interrupt Collector Interrupt Register 102 (HW_ICOLL_INTERRUPT102).............................................320 5.4.113 Interrupt Collector Interrupt Register 103 (HW_ICOLL_INTERRUPT103).............................................321 5.4.114 Interrupt Collector Interrupt Register 104 (HW_ICOLL_INTERRUPT104).............................................323 5.4.115 Interrupt Collector Interrupt Register 105 (HW_ICOLL_INTERRUPT105).............................................324 5.4.116 Interrupt Collector Interrupt Register 106 (HW_ICOLL_INTERRUPT106).............................................326 5.4.117 Interrupt Collector Interrupt Register 107 (HW_ICOLL_INTERRUPT107).............................................327 5.4.118 Interrupt Collector Interrupt Register 108 (HW_ICOLL_INTERRUPT108).............................................329 5.4.119 Interrupt Collector Interrupt Register 109 (HW_ICOLL_INTERRUPT109).............................................330 5.4.120 Interrupt Collector Interrupt Register 110 (HW_ICOLL_INTERRUPT110).............................................332 5.4.121 Interrupt Collector Interrupt Register 111 (HW_ICOLL_INTERRUPT111).............................................333 5.4.122 Interrupt Collector Interrupt Register 112 (HW_ICOLL_INTERRUPT112).............................................335 5.4.123 Interrupt Collector Interrupt Register 113 (HW_ICOLL_INTERRUPT113).............................................336 5.4.124 Interrupt Collector Interrupt Register 114 (HW_ICOLL_INTERRUPT114).............................................338 5.4.125 Interrupt Collector Interrupt Register 115 (HW_ICOLL_INTERRUPT115).............................................339 5.4.126 Interrupt Collector Interrupt Register 116 (HW_ICOLL_INTERRUPT116).............................................341 5.4.127 Interrupt Collector Interrupt Register 117 (HW_ICOLL_INTERRUPT117).............................................342 5.4.128 Interrupt Collector Interrupt Register 118 (HW_ICOLL_INTERRUPT118).............................................344 5.4.129 Interrupt Collector Interrupt Register 119 (HW_ICOLL_INTERRUPT119).............................................345 5.4.130 Interrupt Collector Interrupt Register 120 (HW_ICOLL_INTERRUPT120).............................................347 5.4.131 Interrupt Collector Interrupt Register 121 (HW_ICOLL_INTERRUPT121).............................................348 5.4.132 Interrupt Collector Interrupt Register 122 (HW_ICOLL_INTERRUPT122).............................................350 5.4.133 Interrupt Collector Interrupt Register 123 (HW_ICOLL_INTERRUPT123).............................................351 5.4.134 Interrupt Collector Interrupt Register 124 (HW_ICOLL_INTERRUPT124).............................................353 5.4.135 Interrupt Collector Interrupt Register 125 (HW_ICOLL_INTERRUPT125).............................................354 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 9 Section number Title Page 5.4.136 Interrupt Collector Interrupt Register 126 (HW_ICOLL_INTERRUPT126).............................................356 5.4.137 Interrupt Collector Interrupt Register 127 (HW_ICOLL_INTERRUPT127).............................................357 5.4.138 Interrupt Collector Debug Register 0 (HW_ICOLL_DEBUG)...................................................................359 5.4.139 Interrupt Collector Debug Read Register 0 (HW_ICOLL_DBGREAD0)..................................................360 5.4.140 Interrupt Collector Debug Read Register 1 (HW_ICOLL_DBGREAD1)..................................................361 5.4.141 Interrupt Collector Debug Flag Register (HW_ICOLL_DBGFLAG).........................................................362 5.4.142 Interrupt Collector Debug Read Request Register 0 (HW_ICOLL_DBGREQUEST0).............................363 5.4.143 Interrupt Collector Debug Read Request Register 1 (HW_ICOLL_DBGREQUEST1).............................363 5.4.144 Interrupt Collector Debug Read Request Register 2 (HW_ICOLL_DBGREQUEST2).............................364 5.4.145 Interrupt Collector Debug Read Request Register 3 (HW_ICOLL_DBGREQUEST3).............................365 5.4.146 Interrupt Collector Version Register (HW_ICOLL_VERSION)................................................................365 Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.1 Overview.......................................................................................................................................................................367 6.2 APBH DMA..................................................................................................................................................................369 6.3 Implementation Examples............................................................................................................................................374 6.3.1 NAND Read Status Polling Example..........................................................................................................374 6.4 Behavior During Reset..................................................................................................................................................376 6.5 Programmable Registers...............................................................................................................................................376 6.5.1 AHB to APBH Bridge Control and Status Register 0 (HW_APBH_CTRL0)............................................382 6.5.2 AHB to APBH Bridge Control and Status Register 1 (HW_APBH_CTRL1)............................................384 6.5.3 AHB to APBH Bridge Control and Status Register 2 (HW_APBH_CTRL2)............................................387 6.5.4 AHB to APBH Bridge Channel Register (HW_APBH_CHANNEL_CTRL).............................................392 6.5.5 AHB to APBH DMA Device Assignment Register (HW_APBH_DEVSEL)............................................394 6.5.6 AHB to APBH DMA burst size (HW_APBH_DMA_BURST_SIZE).......................................................395 6.5.7 AHB to APBH DMA Debug Register (HW_APBH_DEBUG)..................................................................396 6.5.8 APBH DMA Channel 0 Current Command Address Register (HW_APBH_CH0_CURCMDAR)...........397 6.5.9 APBH DMA Channel 0 Next Command Address Register (HW_APBH_CH0_NXTCMDAR)...............398 6.5.10 APBH DMA Channel 0 Command Register (HW_APBH_CH0_CMD)....................................................399 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 10 Freescale Semiconductor, Inc. Section number Title Page 6.5.11 APBH DMA Channel 0 Buffer Address Register (HW_APBH_CH0_BAR).............................................401 6.5.12 APBH DMA Channel 0 Semaphore Register (HW_APBH_CH0_SEMA)................................................402 6.5.13 AHB to APBH DMA Channel 0 Debug Information (HW_APBH_CH0_DEBUG1)................................403 6.5.14 AHB to APBH DMA Channel 0 Debug Information (HW_APBH_CH0_DEBUG2)................................405 6.5.15 APBH DMA Channel 1 Current Command Address Register (HW_APBH_CH1_CURCMDAR)...........406 6.5.16 APBH DMA Channel 1 Next Command Address Register (HW_APBH_CH1_NXTCMDAR)...............407 6.5.17 APBH DMA Channel 1 Command Register (HW_APBH_CH1_CMD)....................................................407 6.5.18 APBH DMA Channel 1 Buffer Address Register (HW_APBH_CH1_BAR).............................................409 6.5.19 APBH DMA Channel 1 Semaphore Register (HW_APBH_CH1_SEMA)................................................410 6.5.20 AHB to APBH DMA Channel 1 Debug Information (HW_APBH_CH1_DEBUG1)................................411 6.5.21 AHB to APBH DMA Channel 1 Debug Information (HW_APBH_CH1_DEBUG2)................................413 6.5.22 APBH DMA Channel 2 Current Command Address Register (HW_APBH_CH2_CURCMDAR)...........414 6.5.23 APBH DMA Channel 2 Next Command Address Register (HW_APBH_CH2_NXTCMDAR)...............414 6.5.24 APBH DMA Channel 2 Command Register (HW_APBH_CH2_CMD)....................................................415 6.5.25 APBH DMA Channel 2 Buffer Address Register (HW_APBH_CH2_BAR).............................................417 6.5.26 APBH DMA Channel 2 Semaphore Register (HW_APBH_CH2_SEMA)................................................418 6.5.27 AHB to APBH DMA Channel 2 Debug Information (HW_APBH_CH2_DEBUG1)................................418 6.5.28 AHB to APBH DMA Channel 2 Debug Information (HW_APBH_CH2_DEBUG2)................................421 6.5.29 APBH DMA Channel 3 Current Command Address Register (HW_APBH_CH3_CURCMDAR)...........422 6.5.30 APBH DMA Channel 3 Next Command Address Register (HW_APBH_CH3_NXTCMDAR)...............422 6.5.31 APBH DMA Channel 3 Command Register (HW_APBH_CH3_CMD)....................................................423 6.5.32 APBH DMA Channel 3 Buffer Address Register (HW_APBH_CH3_BAR).............................................425 6.5.33 APBH DMA Channel 3 Semaphore Register (HW_APBH_CH3_SEMA)................................................426 6.5.34 AHB to APBH DMA Channel 3 Debug Information (HW_APBH_CH3_DEBUG1)................................426 6.5.35 AHB to APBH DMA Channel 3 Debug Information (HW_APBH_CH3_DEBUG2)................................429 6.5.36 APBH DMA Channel 4 Current Command Address Register (HW_APBH_CH4_CURCMDAR)...........430 6.5.37 APBH DMA Channel 4 Next Command Address Register (HW_APBH_CH4_NXTCMDAR)...............430 6.5.38 APBH DMA Channel 4 Command Register (HW_APBH_CH4_CMD)....................................................431 6.5.39 APBH DMA Channel 4 Buffer Address Register (HW_APBH_CH4_BAR).............................................433 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 11 Section number Title Page 6.5.40 APBH DMA Channel 4 Semaphore Register (HW_APBH_CH4_SEMA)................................................434 6.5.41 AHB to APBH DMA Channel 4 Debug Information (HW_APBH_CH4_DEBUG1)................................434 6.5.42 AHB to APBH DMA Channel 4 Debug Information (HW_APBH_CH4_DEBUG2)................................437 6.5.43 APBH DMA Channel 5 Current Command Address Register (HW_APBH_CH5_CURCMDAR)...........438 6.5.44 APBH DMA Channel 5 Next Command Address Register (HW_APBH_CH5_NXTCMDAR)...............438 6.5.45 APBH DMA Channel 5 Command Register (HW_APBH_CH5_CMD)....................................................439 6.5.46 APBH DMA Channel 5 Buffer Address Register (HW_APBH_CH5_BAR).............................................441 6.5.47 APBH DMA Channel 5 Semaphore Register (HW_APBH_CH5_SEMA)................................................442 6.5.48 AHB to APBH DMA Channel 5 Debug Information (HW_APBH_CH5_DEBUG1)................................442 6.5.49 AHB to APBH DMA Channel 5 Debug Information (HW_APBH_CH5_DEBUG2)................................445 6.5.50 APBH DMA Channel 6 Current Command Address Register (HW_APBH_CH6_CURCMDAR)...........446 6.5.51 APBH DMA Channel 6 Next Command Address Register (HW_APBH_CH6_NXTCMDAR)...............446 6.5.52 APBH DMA Channel 6 Command Register (HW_APBH_CH6_CMD)....................................................447 6.5.53 APBH DMA Channel 6 Buffer Address Register (HW_APBH_CH6_BAR).............................................449 6.5.54 APBH DMA Channel 6 Semaphore Register (HW_APBH_CH6_SEMA)................................................450 6.5.55 AHB to APBH DMA Channel 6 Debug Information (HW_APBH_CH6_DEBUG1)................................450 6.5.56 AHB to APBH DMA Channel 6 Debug Information (HW_APBH_CH6_DEBUG2)................................453 6.5.57 APBH DMA Channel 7 Current Command Address Register (HW_APBH_CH7_CURCMDAR)...........454 6.5.58 APBH DMA Channel 7 Next Command Address Register (HW_APBH_CH7_NXTCMDAR)...............454 6.5.59 APBH DMA Channel 7 Command Register (HW_APBH_CH7_CMD)....................................................455 6.5.60 APBH DMA Channel 7 Buffer Address Register (HW_APBH_CH7_BAR).............................................457 6.5.61 APBH DMA Channel 7 Semaphore Register (HW_APBH_CH7_SEMA)................................................458 6.5.62 AHB to APBH DMA Channel 7 Debug Information (HW_APBH_CH7_DEBUG1)................................458 6.5.63 AHB to APBH DMA Channel 7 Debug Information (HW_APBH_CH7_DEBUG2)................................461 6.5.64 APBH DMA Channel 8 Current Command Address Register (HW_APBH_CH8_CURCMDAR)...........462 6.5.65 APBH DMA Channel 8 Next Command Address Register (HW_APBH_CH8_NXTCMDAR)...............462 6.5.66 APBH DMA Channel 8 Command Register (HW_APBH_CH8_CMD)....................................................463 6.5.67 APBH DMA Channel 8 Buffer Address Register (HW_APBH_CH8_BAR).............................................465 6.5.68 APBH DMA Channel 8 Semaphore Register (HW_APBH_CH8_SEMA)................................................466 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 12 Freescale Semiconductor, Inc. Section number Title Page 6.5.69 AHB to APBH DMA Channel 8 Debug Information (HW_APBH_CH8_DEBUG1)................................466 6.5.70 AHB to APBH DMA Channel 8 Debug Information (HW_APBH_CH8_DEBUG2)................................469 6.5.71 APBH DMA Channel 9 Current Command Address Register (HW_APBH_CH9_CURCMDAR)...........470 6.5.72 APBH DMA Channel 9 Next Command Address Register (HW_APBH_CH9_NXTCMDAR)...............470 6.5.73 APBH DMA Channel 9 Command Register (HW_APBH_CH9_CMD)....................................................471 6.5.74 APBH DMA Channel 9 Buffer Address Register (HW_APBH_CH9_BAR).............................................473 6.5.75 APBH DMA Channel 9 Semaphore Register (HW_APBH_CH9_SEMA)................................................474 6.5.76 AHB to APBH DMA Channel 9 Debug Information (HW_APBH_CH9_DEBUG1)................................474 6.5.77 AHB to APBH DMA Channel 9 Debug Information (HW_APBH_CH9_DEBUG2)................................477 6.5.78 APBH DMA channel 10 Current Command Address Register (HW_APBH_CH10_CURCMDAR).......478 6.5.79 APBH DMA channel 10 Next Command Address Register (HW_APBH_CH10_NXTCMDAR)............478 6.5.80 APBH DMA channel 10 Command Register (HW_APBH_CH10_CMD).................................................479 6.5.81 APBH DMA channel 10 Buffer Address Register (HW_APBH_CH10_BAR)..........................................481 6.5.82 APBH DMA channel 10 Semaphore Register (HW_APBH_CH10_SEMA).............................................482 6.5.83 AHB to APBH DMA channel 10 Debug Information (HW_APBH_CH10_DEBUG1).............................482 6.5.84 AHB to APBH DMA channel 10 Debug Information (HW_APBH_CH10_DEBUG2).............................485 6.5.85 APBH DMA Channel 11 Current Command Address Register (HW_APBH_CH11_CURCMDAR).......486 6.5.86 APBH DMA Channel 11 Next Command Address Register (HW_APBH_CH11_NXTCMDAR)...........486 6.5.87 APBH DMA Channel 11 Command Register (HW_APBH_CH11_CMD)................................................487 6.5.88 APBH DMA Channel 11 Buffer Address Register (HW_APBH_CH11_BAR).........................................489 6.5.89 APBH DMA Channel 11 Semaphore Register (HW_APBH_CH11_SEMA)............................................490 6.5.90 AHB to APBH DMA Channel 11 Debug Information (HW_APBH_CH11_DEBUG1)............................490 6.5.91 AHB to APBH DMA Channel 11 Debug Information (HW_APBH_CH11_DEBUG2)............................493 6.5.92 APBH DMA channel 12 Current Command Address Register (HW_APBH_CH12_CURCMDAR).......494 6.5.93 APBH DMA channel 12 Next Command Address Register (HW_APBH_CH12_NXTCMDAR)............494 6.5.94 APBH DMA channel 12 Command Register (HW_APBH_CH12_CMD).................................................495 6.5.95 APBH DMA channel 12 Buffer Address Register (HW_APBH_CH12_BAR)..........................................497 6.5.96 APBH DMA channel 12 Semaphore Register (HW_APBH_CH12_SEMA).............................................498 6.5.97 AHB to APBH DMA channel 12 Debug Information (HW_APBH_CH12_DEBUG1).............................498 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 13 Section number Title Page 6.5.98 AHB to APBH DMA channel 12 Debug Information (HW_APBH_CH12_DEBUG2).............................501 6.5.99 APBH DMA Channel 13 Current Command Address Register (HW_APBH_CH13_CURCMDAR).......502 6.5.100 APBH DMA Channel 13 Next Command Address Register (HW_APBH_CH13_NXTCMDAR)...........502 6.5.101 APBH DMA Channel 13 Command Register (HW_APBH_CH13_CMD)................................................503 6.5.102 APBH DMA Channel 13 Buffer Address Register (HW_APBH_CH13_BAR).........................................505 6.5.103 APBH DMA Channel 13 Semaphore Register (HW_APBH_CH13_SEMA)............................................506 6.5.104 AHB to APBH DMA Channel 13 Debug Information (HW_APBH_CH13_DEBUG1)............................506 6.5.105 AHB to APBH DMA Channel 13 Debug Information (HW_APBH_CH13_DEBUG2)............................509 6.5.106 APBH DMA channel 14 Current Command Address Register (HW_APBH_CH14_CURCMDAR).......510 6.5.107 APBH DMA channel 14 Next Command Address Register (HW_APBH_CH14_NXTCMDAR)............510 6.5.108 APBH DMA channel 14 Command Register (HW_APBH_CH14_CMD).................................................511 6.5.109 APBH DMA channel 14 Buffer Address Register (HW_APBH_CH14_BAR)..........................................513 6.5.110 APBH DMA channel 14 Semaphore Register (HW_APBH_CH14_SEMA).............................................514 6.5.111 AHB to APBH DMA channel 14 Debug Information (HW_APBH_CH14_DEBUG1).............................514 6.5.112 AHB to APBH DMA channel 14 Debug Information (HW_APBH_CH14_DEBUG2).............................517 6.5.113 APBH DMA channel 15 Current Command Address Register (HW_APBH_CH15_CURCMDAR).......518 6.5.114 APBH DMA channel 15 Next Command Address Register (HW_APBH_CH15_NXTCMDAR)............518 6.5.115 APBH DMA channel 15 Command Register (HW_APBH_CH15_CMD).................................................519 6.5.116 APBH DMA channel 15 Buffer Address Register (HW_APBH_CH15_BAR)..........................................521 6.5.117 APBH DMA channel 15 Semaphore Register (HW_APBH_CH15_SEMA).............................................522 6.5.118 AHB to APBH DMA channel 15 Debug Information (HW_APBH_CH15_DEBUG1).............................522 6.5.119 AHB to APBH DMA channel 15 Debug Information (HW_APBH_CH15_DEBUG2).............................525 6.5.120 APBH Bridge Version Register (HW_APBH_VERSION).........................................................................525 Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 7.1 AHB-to-APBX Bridge Overview.................................................................................................................................527 7.2 APBX DMA..................................................................................................................................................................529 7.3 DMA Chain Example...................................................................................................................................................533 7.4 Behavior During Reset..................................................................................................................................................535 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 14 Freescale Semiconductor, Inc. Section number 7.5 Title Page Programmable Registers...............................................................................................................................................535 7.5.1 AHB to APBX Bridge Control Register 0 (HW_APBX_CTRL0)..............................................................541 7.5.2 AHB to APBX Bridge Control Register 1 (HW_APBX_CTRL1)..............................................................542 7.5.3 AHB to APBX Bridge Control and Status Register 2 (HW_APBX_CTRL2)............................................545 7.5.4 AHB to APBX Bridge Channel Register (HW_APBX_CHANNEL_CTRL).............................................550 7.5.5 AHB to APBX DMA Device Assignment Register (HW_APBX_DEVSEL)............................................551 7.5.6 APBX DMA Channel 0 Current Command Address Register (HW_APBX_CH0_CURCMDAR)...........553 7.5.7 APBX DMA Channel 0 Next Command Address Register (HW_APBX_CH0_NXTCMDAR)...............553 7.5.8 APBX DMA Channel 0 Command Register (HW_APBX_CH0_CMD)....................................................554 7.5.9 APBX DMA Channel 0 Buffer Address Register (HW_APBX_CH0_BAR).............................................556 7.5.10 APBX DMA Channel 0 Semaphore Register (HW_APBX_CH0_SEMA)................................................557 7.5.11 AHB to APBX DMA Channel 0 Debug Information (HW_APBX_CH0_DEBUG1)................................558 7.5.12 AHB to APBX DMA Channel 0 Debug Information (HW_APBX_CH0_DEBUG2)................................560 7.5.13 APBX DMA Channel 1 Current Command Address Register (HW_APBX_CH1_CURCMDAR)...........561 7.5.14 APBX DMA Channel 1 Next Command Address Register (HW_APBX_CH1_NXTCMDAR)...............561 7.5.15 APBX DMA Channel 1 Command Register (HW_APBX_CH1_CMD)....................................................562 7.5.16 APBX DMA Channel 1 Buffer Address Register (HW_APBX_CH1_BAR).............................................564 7.5.17 APBX DMA Channel 1 Semaphore Register (HW_APBX_CH1_SEMA)................................................565 7.5.18 AHB to APBX DMA Channel 1 Debug Information (HW_APBX_CH1_DEBUG1)................................566 7.5.19 AHB to APBX DMA Channel 1 Debug Information (HW_APBX_CH1_DEBUG2)................................568 7.5.20 APBX DMA Channel 2 Current Command Address Register (HW_APBX_CH2_CURCMDAR)...........569 7.5.21 APBX DMA Channel 2 Next Command Address Register (HW_APBX_CH2_NXTCMDAR)...............569 7.5.22 APBX DMA Channel 2 Command Register (HW_APBX_CH2_CMD)....................................................570 7.5.23 APBX DMA Channel 2 Buffer Address Register (HW_APBX_CH2_BAR).............................................572 7.5.24 APBX DMA Channel 2 Semaphore Register (HW_APBX_CH2_SEMA)................................................572 7.5.25 AHB to APBX DMA Channel 2 Debug Information (HW_APBX_CH2_DEBUG1)................................573 7.5.26 AHB to APBX DMA Channel 2 Debug Information (HW_APBX_CH2_DEBUG2)................................576 7.5.27 APBX DMA Channel 3 Current Command Address Register (HW_APBX_CH3_CURCMDAR)...........576 7.5.28 APBX DMA Channel 3 Next Command Address Register (HW_APBX_CH3_NXTCMDAR)...............577 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 15 Section number Title Page 7.5.29 APBX DMA Channel 3 Command Register (HW_APBX_CH3_CMD)....................................................577 7.5.30 APBX DMA Channel 3 Buffer Address Register (HW_APBX_CH3_BAR).............................................579 7.5.31 APBX DMA Channel 3 Semaphore Register (HW_APBX_CH3_SEMA)................................................580 7.5.32 AHB to APBX DMA Channel 3 Debug Information (HW_APBX_CH3_DEBUG1)................................580 7.5.33 AHB to APBX DMA Channel 3 Debug Information (HW_APBX_CH3_DEBUG2)................................583 7.5.34 APBX DMA Channel 4 Current Command Address Register (HW_APBX_CH4_CURCMDAR)...........583 7.5.35 APBX DMA Channel 4 Next Command Address Register (HW_APBX_CH4_NXTCMDAR)...............584 7.5.36 APBX DMA Channel 4 Command Register (HW_APBX_CH4_CMD)....................................................584 7.5.37 APBX DMA Channel 4 Buffer Address Register (HW_APBX_CH4_BAR).............................................586 7.5.38 APBX DMA Channel 4 Semaphore Register (HW_APBX_CH4_SEMA)................................................587 7.5.39 AHB to APBX DMA Channel 4 Debug Information (HW_APBX_CH4_DEBUG1)................................588 7.5.40 AHB to APBX DMA Channel 4 Debug Information (HW_APBX_CH4_DEBUG2)................................590 7.5.41 APBX DMA Channel 5 Current Command Address Register (HW_APBX_CH5_CURCMDAR)...........591 7.5.42 APBX DMA Channel 5 Next Command Address Register (HW_APBX_CH5_NXTCMDAR)...............591 7.5.43 APBX DMA Channel 5 Command Register (HW_APBX_CH5_CMD)....................................................592 7.5.44 APBX DMA Channel 5 Buffer Address Register (HW_APBX_CH5_BAR).............................................594 7.5.45 APBX DMA Channel 5 Semaphore Register (HW_APBX_CH5_SEMA)................................................594 7.5.46 AHB to APBX DMA Channel 5 Debug Information (HW_APBX_CH5_DEBUG1)................................595 7.5.47 AHB to APBX DMA Channel 5 Debug Information (HW_APBX_CH5_DEBUG2)................................598 7.5.48 APBX DMA Channel 6 Current Command Address Register (HW_APBX_CH6_CURCMDAR)...........598 7.5.49 APBX DMA Channel 6 Next Command Address Register (HW_APBX_CH6_NXTCMDAR)...............599 7.5.50 APBX DMA Channel 6 Command Register (HW_APBX_CH6_CMD)....................................................599 7.5.51 APBX DMA Channel 6 Buffer Address Register (HW_APBX_CH6_BAR).............................................601 7.5.52 APBX DMA Channel 6 Semaphore Register (HW_APBX_CH6_SEMA)................................................602 7.5.53 AHB to APBX DMA Channel 6 Debug Information (HW_APBX_CH6_DEBUG1)................................603 7.5.54 AHB to APBX DMA Channel 6 Debug Information (HW_APBX_CH6_DEBUG2)................................605 7.5.55 APBX DMA Channel 7 Current Command Address Register (HW_APBX_CH7_CURCMDAR)...........606 7.5.56 APBX DMA Channel 7 Next Command Address Register (HW_APBX_CH7_NXTCMDAR)...............606 7.5.57 APBX DMA Channel 7 Command Register (HW_APBX_CH7_CMD)....................................................607 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 16 Freescale Semiconductor, Inc. Section number Title Page 7.5.58 APBX DMA Channel 7 Buffer Address Register (HW_APBX_CH7_BAR).............................................609 7.5.59 APBX DMA Channel 7 Semaphore Register (HW_APBX_CH7_SEMA)................................................610 7.5.60 AHB to APBX DMA Channel 7 Debug Information (HW_APBX_CH7_DEBUG1)................................610 7.5.61 AHB to APBX DMA Channel 7 Debug Information (HW_APBX_CH7_DEBUG2)................................613 7.5.62 APBX DMA Channel 8 Current Command Address Register (HW_APBX_CH8_CURCMDAR)...........613 7.5.63 APBX DMA Channel 8 Next Command Address Register (HW_APBX_CH8_NXTCMDAR)...............614 7.5.64 APBX DMA Channel 8 Command Register (HW_APBX_CH8_CMD)....................................................614 7.5.65 APBX DMA Channel 8 Buffer Address Register (HW_APBX_CH8_BAR).............................................616 7.5.66 APBX DMA Channel 8 Semaphore Register (HW_APBX_CH8_SEMA)................................................617 7.5.67 AHB to APBX DMA Channel 8 Debug Information (HW_APBX_CH8_DEBUG1)................................618 7.5.68 AHB to APBX DMA Channel 8 Debug Information (HW_APBX_CH8_DEBUG2)................................620 7.5.69 APBX DMA Channel 9 Current Command Address Register (HW_APBX_CH9_CURCMDAR)...........621 7.5.70 APBX DMA Channel 9 Next Command Address Register (HW_APBX_CH9_NXTCMDAR)...............621 7.5.71 APBX DMA Channel 9 Command Register (HW_APBX_CH9_CMD)....................................................622 7.5.72 APBX DMA Channel 9 Buffer Address Register (HW_APBX_CH9_BAR).............................................624 7.5.73 APBX DMA Channel 9 Semaphore Register (HW_APBX_CH9_SEMA)................................................625 7.5.74 AHB to APBX DMA Channel 9 Debug Information (HW_APBX_CH9_DEBUG1)................................625 7.5.75 AHB to APBX DMA Channel 9 Debug Information (HW_APBX_CH9_DEBUG2)................................628 7.5.76 APBX DMA Channel 10 Current Command Address Register (HW_APBX_CH10_CURCMDAR).......628 7.5.77 APBX DMA Channel 10 Next Command Address Register (HW_APBX_CH10_NXTCMDAR)...........629 7.5.78 APBX DMA Channel 10 Command Register (HW_APBX_CH10_CMD)................................................629 7.5.79 APBX DMA Channel 10 Buffer Address Register (HW_APBX_CH10_BAR).........................................631 7.5.80 APBX DMA Channel 10 Semaphore Register (HW_APBX_CH10_SEMA)............................................632 7.5.81 AHB to APBX DMA Channel 10 Debug Information (HW_APBX_CH10_DEBUG1)............................633 7.5.82 AHB to APBX DMA Channel 10 Debug Information (HW_APBX_CH10_DEBUG2)............................635 7.5.83 APBX DMA Channel 11 Current Command Address Register (HW_APBX_CH11_CURCMDAR).......636 7.5.84 APBX DMA Channel 11 Next Command Address Register (HW_APBX_CH11_NXTCMDAR)...........636 7.5.85 APBX DMA Channel 11 Command Register (HW_APBX_CH11_CMD)................................................637 7.5.86 APBX DMA Channel 11 Buffer Address Register (HW_APBX_CH11_BAR).........................................639 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 17 Section number Title Page 7.5.87 APBX DMA Channel 11 Semaphore Register (HW_APBX_CH11_SEMA)............................................639 7.5.88 AHB to APBX DMA Channel 11 Debug Information (HW_APBX_CH11_DEBUG1)............................640 7.5.89 AHB to APBX DMA Channel 11 Debug Information (HW_APBX_CH11_DEBUG2)............................643 7.5.90 APBX DMA Channel 12 Current Command Address Register (HW_APBX_CH12_CURCMDAR).......643 7.5.91 APBX DMA Channel 12 Next Command Address Register (HW_APBX_CH12_NXTCMDAR)...........644 7.5.92 APBX DMA Channel 12 Command Register (HW_APBX_CH12_CMD)................................................644 7.5.93 APBX DMA Channel 12 Buffer Address Register (HW_APBX_CH12_BAR).........................................646 7.5.94 APBX DMA Channel 12 Semaphore Register (HW_APBX_CH12_SEMA)............................................647 7.5.95 AHB to APBX DMA Channel 12 Debug Information (HW_APBX_CH12_DEBUG1)............................648 7.5.96 AHB to APBX DMA Channel 12 Debug Information (HW_APBX_CH12_DEBUG2)............................650 7.5.97 APBX DMA Channel 13 Current Command Address Register (HW_APBX_CH13_CURCMDAR).......651 7.5.98 APBX DMA Channel 13 Next Command Address Register (HW_APBX_CH13_NXTCMDAR)...........651 7.5.99 APBX DMA Channel 13 Command Register (HW_APBX_CH13_CMD)................................................652 7.5.100 APBX DMA Channel 13 Buffer Address Register (HW_APBX_CH13_BAR).........................................654 7.5.101 APBX DMA Channel 13 Semaphore Register (HW_APBX_CH13_SEMA)............................................654 7.5.102 AHB to APBX DMA Channel 13 Debug Information (HW_APBX_CH13_DEBUG1)............................655 7.5.103 AHB to APBX DMA Channel 13 Debug Information (HW_APBX_CH13_DEBUG2)............................658 7.5.104 APBX DMA Channel 14 Current Command Address Register (HW_APBX_CH14_CURCMDAR).......658 7.5.105 APBX DMA Channel 14 Next Command Address Register (HW_APBX_CH14_NXTCMDAR)...........659 7.5.106 APBX DMA Channel 14 Command Register (HW_APBX_CH14_CMD)................................................659 7.5.107 APBX DMA Channel 14 Buffer Address Register (HW_APBX_CH14_BAR).........................................661 7.5.108 APBX DMA Channel 14 Semaphore Register (HW_APBX_CH14_SEMA)............................................662 7.5.109 AHB to APBX DMA Channel 14 Debug Information (HW_APBX_CH14_DEBUG1)............................663 7.5.110 AHB to APBX DMA Channel 14 Debug Information (HW_APBX_CH14_DEBUG2)............................665 7.5.111 APBX DMA Channel 15 Current Command Address Register (HW_APBX_CH15_CURCMDAR).......666 7.5.112 APBX DMA Channel 15 Next Command Address Register (HW_APBX_CH15_NXTCMDAR)...........666 7.5.113 APBX DMA Channel 15 Command Register (HW_APBX_CH15_CMD)................................................667 7.5.114 APBX DMA Channel 15 Buffer Address Register (HW_APBX_CH15_BAR).........................................669 7.5.115 APBX DMA Channel 15 Semaphore Register (HW_APBX_CH15_SEMA)............................................669 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 18 Freescale Semiconductor, Inc. Section number Title Page 7.5.116 AHB to APBX DMA Channel 15 Debug Information (HW_APBX_CH15_DEBUG1)............................670 7.5.117 AHB to APBX DMA Channel 15 Debug Information (HW_APBX_CH15_DEBUG2)............................673 7.5.118 APBX Bridge Version Register (HW_APBX_VERSION).........................................................................673 Chapter 8 Pin Descriptions 8.1 Pin Descriptions Overview...........................................................................................................................................675 8.2 Pin Definitions for 289-pin BGA..................................................................................................................................676 8.3 Functional Pin Groups..................................................................................................................................................684 Chapter 9 Pin Control and GPIO (PinCtrl) 9.1 Pin Control and GPIO Overview..................................................................................................................................701 9.2 Operation.......................................................................................................................................................................702 9.2.1 Reset Configuration.....................................................................................................................................703 9.2.2 Pin Interface Multiplexing...........................................................................................................................703 9.2.3 9.2.2.1 Pin Drive Strength Selection....................................................................................................713 9.2.2.2 Pin Voltage Selection...............................................................................................................713 9.2.2.3 Pullup Selection.......................................................................................................................714 GPIO Interface.............................................................................................................................................715 9.2.3.1 Output Operation......................................................................................................................716 9.2.3.2 Input Operation........................................................................................................................717 9.2.3.3 Input Interrupt Operation.........................................................................................................718 9.3 Behavior During Reset..................................................................................................................................................721 9.4 Pin Control Memory Map/Register Definition.............................................................................................................722 9.4.1 PINCTRL Block Control Register (HW_PINCTRL_CTRL)......................................................................726 9.4.2 PINCTRL Pin Mux Select Register 0 (HW_PINCTRL_MUXSEL0).........................................................727 9.4.3 PINCTRL Pin Mux Select Register 1 (HW_PINCTRL_MUXSEL1).........................................................729 9.4.4 PINCTRL Pin Mux Select Register 2 (HW_PINCTRL_MUXSEL2).........................................................732 9.4.5 PINCTRL Pin Mux Select Register 3 (HW_PINCTRL_MUXSEL3).........................................................734 9.4.6 PINCTRL Pin Mux Select Register 4 (HW_PINCTRL_MUXSEL4).........................................................737 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 19 Section number Title Page 9.4.7 PINCTRL Pin Mux Select Register 5 (HW_PINCTRL_MUXSEL5).........................................................740 9.4.8 PINCTRL Pin Mux Select Register 6 (HW_PINCTRL_MUXSEL6).........................................................742 9.4.9 PINCTRL Pin Mux Select Register 7 (HW_PINCTRL_MUXSEL7).........................................................745 9.4.10 PINCTRL Pin Mux Select Register 8 (HW_PINCTRL_MUXSEL8).........................................................747 9.4.11 PINCTRL Pin Mux Select Register 9 (HW_PINCTRL_MUXSEL9).........................................................750 9.4.12 PINCTRL Pin Mux Select Register 10 (HW_PINCTRL_MUXSEL10).....................................................751 9.4.13 PINCTRL Pin Mux Select Register 11 (HW_PINCTRL_MUXSEL11).....................................................754 9.4.14 PINCTRL Pin Mux Select Register 12 (HW_PINCTRL_MUXSEL12).....................................................756 9.4.15 PINCTRL Pin Mux Select Register 13 (HW_PINCTRL_MUXSEL13).....................................................759 9.4.16 PINCTRL Drive Strength and Voltage Register 0 (HW_PINCTRL_DRIVE0).........................................761 9.4.17 PINCTRL Drive Strength and Voltage Register 1 (HW_PINCTRL_DRIVE1).........................................764 9.4.18 PINCTRL Drive Strength and Voltage Register 2 (HW_PINCTRL_DRIVE2).........................................765 9.4.19 PINCTRL Drive Strength and Voltage Register 3 (HW_PINCTRL_DRIVE3).........................................769 9.4.20 PINCTRL Drive Strength and Voltage Register 4 (HW_PINCTRL_DRIVE4).........................................771 9.4.21 PINCTRL Drive Strength and Voltage Register 5 (HW_PINCTRL_DRIVE5).........................................775 9.4.22 PINCTRL Drive Strength and Voltage Register 6 (HW_PINCTRL_DRIVE6).........................................778 9.4.23 PINCTRL Drive Strength and Voltage Register 7 (HW_PINCTRL_DRIVE7).........................................782 9.4.24 PINCTRL Drive Strength and Voltage Register 8 (HW_PINCTRL_DRIVE8).........................................785 9.4.25 PINCTRL Drive Strength and Voltage Register 9 (HW_PINCTRL_DRIVE9).........................................789 9.4.26 PINCTRL Drive Strength and Voltage Register 10 (HW_PINCTRL_DRIVE10).....................................792 9.4.27 PINCTRL Drive Strength and Voltage Register 11 (HW_PINCTRL_DRIVE11).....................................795 9.4.28 PINCTRL Drive Strength and Voltage Register 12 (HW_PINCTRL_DRIVE12).....................................797 9.4.29 PINCTRL Drive Strength and Voltage Register 13 (HW_PINCTRL_DRIVE13).....................................801 9.4.30 PINCTRL Drive Strength and Voltage Register 14 (HW_PINCTRL_DRIVE14).....................................805 9.4.31 PINCTRL Drive Strength and Voltage Register 15 (HW_PINCTRL_DRIVE15).....................................808 9.4.32 PINCTRL Drive Strength and Voltage Register 16 (HW_PINCTRL_DRIVE16).....................................811 9.4.33 PINCTRL Drive Strength and Voltage Register 17 (HW_PINCTRL_DRIVE17).....................................815 9.4.34 PINCTRL Drive Strength and Voltage Register 18 (HW_PINCTRL_DRIVE18).....................................818 9.4.35 PINCTRL Drive Strength and Voltage Register 19 (HW_PINCTRL_DRIVE19).....................................820 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 20 Freescale Semiconductor, Inc. Section number Title Page 9.4.36 PINCTRL Bank 0 Pull Up Resistor Enable Register (HW_PINCTRL_PULL0)........................................821 9.4.37 PINCTRL Bank 1 Pull Up Resistor Enable Register (HW_PINCTRL_PULL1)........................................823 9.4.38 PINCTRL Bank 2 Pull Up Resistor Enable Register (HW_PINCTRL_PULL2)........................................826 9.4.39 PINCTRL Bank 3 Pull Up Resistor Enable Register (HW_PINCTRL_PULL3)........................................828 9.4.40 PINCTRL Bank 4 Pull Up Resistor Enable Register (HW_PINCTRL_PULL4)........................................831 9.4.41 PINCTRL Bank 5 Pad Keeper Disable Register (HW_PINCTRL_PULL5)..............................................833 9.4.42 PINCTRL Bank 6 Pad Keeper Disable Register (HW_PINCTRL_PULL6)..............................................836 9.4.43 PINCTRL Bank 0 Data Output Register (HW_PINCTRL_DOUT0).........................................................838 9.4.44 PINCTRL Bank 1 Data Output Register (HW_PINCTRL_DOUT1).........................................................839 9.4.45 PINCTRL Bank 2 Data Output Register (HW_PINCTRL_DOUT2).........................................................840 9.4.46 PINCTRL Bank 3 Data Output Register (HW_PINCTRL_DOUT3).........................................................840 9.4.47 PINCTRL Bank 4 Data Output Register (HW_PINCTRL_DOUT4).........................................................842 9.4.48 PINCTRL Bank 0 Data Input Register (HW_PINCTRL_DIN0)................................................................842 9.4.49 PINCTRL Bank 1 Data Input Register (HW_PINCTRL_DIN1)................................................................843 9.4.50 PINCTRL Bank 2 Data Input Register (HW_PINCTRL_DIN2)................................................................844 9.4.51 PINCTRL Bank 3 Data Input Register (HW_PINCTRL_DIN3)................................................................845 9.4.52 PINCTRL Bank 4 Data Input Register (HW_PINCTRL_DIN4)................................................................846 9.4.53 PINCTRL Bank 0 Data Output Enable Register (HW_PINCTRL_DOE0)................................................847 9.4.54 PINCTRL Bank 1 Data Output Enable Register (HW_PINCTRL_DOE1)................................................847 9.4.55 PINCTRL Bank 2 Data Output Enable Register (HW_PINCTRL_DOE2)................................................848 9.4.56 PINCTRL Bank 3 Data Output Enable Register (HW_PINCTRL_DOE3)................................................849 9.4.57 PINCTRL Bank 4 Data Output Enable Register (HW_PINCTRL_DOE4)................................................850 9.4.58 PINCTRL Bank 0 Interrupt Select Register (HW_PINCTRL_PIN2IRQ0)................................................851 9.4.59 PINCTRL Bank 1 Interrupt Select Register (HW_PINCTRL_PIN2IRQ1)................................................852 9.4.60 PINCTRL Bank 2 Interrupt Select Register (HW_PINCTRL_PIN2IRQ2)................................................852 9.4.61 PINCTRL Bank 3 Interrupt Select Register (HW_PINCTRL_PIN2IRQ3)................................................853 9.4.62 PINCTRL Bank 4 Interrupt Select Register (HW_PINCTRL_PIN2IRQ4)................................................855 9.4.63 PINCTRL Bank 0 Interrupt Mask Register (HW_PINCTRL_IRQEN0)....................................................856 9.4.64 PINCTRL Bank 1 Interrupt Mask Register (HW_PINCTRL_IRQEN1)....................................................856 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 21 Section number Title Page 9.4.65 PINCTRL Bank 2 Interrupt Mask Register (HW_PINCTRL_IRQEN2)....................................................857 9.4.66 PINCTRL Bank 3 Interrupt Mask Register (HW_PINCTRL_IRQEN3)....................................................858 9.4.67 PINCTRL Bank 4 Interrupt Mask Register (HW_PINCTRL_IRQEN4)....................................................859 9.4.68 PINCTRL Bank 0 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL0)...................................860 9.4.69 PINCTRL Bank 1 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL1)...................................861 9.4.70 PINCTRL Bank 2 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL2)...................................862 9.4.71 PINCTRL Bank 3 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL3)...................................862 9.4.72 PINCTRL Bank 4 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL4)...................................864 9.4.73 PINCTRL Bank 0 Interrupt Polarity Register (HW_PINCTRL_IRQPOL0)..............................................864 9.4.74 PINCTRL Bank 1 Interrupt Polarity Register (HW_PINCTRL_IRQPOL1)..............................................865 9.4.75 PINCTRL Bank 2 Interrupt Polarity Register (HW_PINCTRL_IRQPOL2)..............................................866 9.4.76 PINCTRL Bank 3 Interrupt Polarity Register (HW_PINCTRL_IRQPOL3)..............................................867 9.4.77 PINCTRL Bank 4 Interrupt Polarity Register (HW_PINCTRL_IRQPOL4)..............................................868 9.4.78 PINCTRL Bank 0 Interrupt Status Register (HW_PINCTRL_IRQSTAT0)...............................................869 9.4.79 PINCTRL Bank 1 Interrupt Status Register (HW_PINCTRL_IRQSTAT1)...............................................870 9.4.80 PINCTRL Bank 2 Interrupt Status Register (HW_PINCTRL_IRQSTAT2)...............................................870 9.4.81 PINCTRL Bank 3 Interrupt Status Register (HW_PINCTRL_IRQSTAT3)...............................................871 9.4.82 PINCTRL Bank 4 Interrupt Status Register (HW_PINCTRL_IRQSTAT4)...............................................873 9.4.83 PINCTRL EMI Slice ODT Control (HW_PINCTRL_EMI_ODT_CTRL)................................................874 9.4.84 PINCTRL EMI Slice DS Control (HW_PINCTRL_EMI_DS_CTRL).......................................................878 Chapter 10 Clock Generation and Control (CLKCTRL) 10.1 Clock Generation and Control (CLKCTRL) Overview................................................................................................881 10.2 Clock Structure.............................................................................................................................................................881 10.2.1 Table of System Clocks...............................................................................................................................882 10.2.2 Logical Diagram of Clock Domains............................................................................................................884 10.2.3 Clock Domain Description...........................................................................................................................886 10.2.3.1 CLK_P, CLK_H.......................................................................................................................886 10.2.3.2 CLK_EMI................................................................................................................................887 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 22 Freescale Semiconductor, Inc. Section number Title 10.2.3.3 10.3 Page System Clocks..........................................................................................................................887 CLKCTRL Digital Clock Divider................................................................................................................................888 10.3.1 Integer Clock Divide Mode..........................................................................................................................888 10.3.2 Fractional Clock Divide Mode.....................................................................................................................888 10.3.2.1 Fractional Clock Divide Example, Divide by 3.5....................................................................889 10.3.2.1.1 10.3.3 Fractional ClockDivide Example, Divide by 3/8................................................889 Gated Clock Divide Mode...........................................................................................................................890 10.4 Clock Frequency Management.....................................................................................................................................891 10.5 Analog Clock Control...................................................................................................................................................891 10.6 CPU and EMI Clock Programming..............................................................................................................................892 10.7 Chip Reset.....................................................................................................................................................................893 10.8 Programmable Registers...............................................................................................................................................893 10.8.1 System PLL0, System/USB0 PLL Control Register 0 (HW_CLKCTRL_PLL0CTRL0)...........................895 10.8.2 System PLL0, System/USB0 PLL Control Register 1 (HW_CLKCTRL_PLL0CTRL1)...........................897 10.8.3 System PLL1, USB1 PLL Control Register 0 (HW_CLKCTRL_PLL1CTRL0).......................................898 10.8.4 System PLL1, USB1 PLL Control Register 1 (HW_CLKCTRL_PLL1CTRL1).......................................900 10.8.5 System PLL2, Ethernet PLL Control Register 0 (HW_CLKCTRL_PLL2CTRL0)....................................902 10.8.6 CPU Clock Control Register (HW_CLKCTRL_CPU)...............................................................................903 10.8.7 AHB, APBH Bus Clock Control Register (HW_CLKCTRL_HBUS)........................................................905 10.8.8 APBX Clock Control Register (HW_CLKCTRL_XBUS)..........................................................................908 10.8.9 XTAL Clock Control Register (HW_CLKCTRL_XTAL)..........................................................................910 10.8.10 Synchronous Serial Port0 Clock Control Register (HW_CLKCTRL_SSP0).............................................912 10.8.11 Synchronous Serial Port1 Clock Control Register (HW_CLKCTRL_SSP1).............................................913 10.8.12 Synchronous Serial Port2 Clock Control Register (HW_CLKCTRL_SSP2).............................................914 10.8.13 Synchronous Serial Port3 Clock Control Register (HW_CLKCTRL_SSP3).............................................916 10.8.14 General-Purpose Media Interface Clock Control Register (HW_CLKCTRL_GPMI)................................917 10.8.15 SPDIF Clock Control Register (HW_CLKCTRL_SPDIF).........................................................................918 10.8.16 EMI Clock Control Register (HW_CLKCTRL_EMI)................................................................................919 10.8.17 SAIF0 Clock Control Register (HW_CLKCTRL_SAIF0)..........................................................................921 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 23 Section number Title Page 10.8.18 SAIF1 Clock Control Register (HW_CLKCTRL_SAIF1)..........................................................................923 10.8.19 CLK_DIS_LCDIF Clock Control Register (HW_CLKCTRL_DIS_LCDIF).............................................924 10.8.20 ETM Clock Control Register (HW_CLKCTRL_ETM)..............................................................................925 10.8.21 ENET Clock Control Register (HW_CLKCTRL_ENET)...........................................................................927 10.8.22 HSADC Clock Control Register (HW_CLKCTRL_HSADC)....................................................................928 10.8.23 FLEXCAN Clock Control Register (HW_CLKCTRL_FLEXCAN)..........................................................929 10.8.24 Fractional Clock Control Register 0 (HW_CLKCTRL_FRAC0)...............................................................931 10.8.25 Fractional Clock Control Register 1 (HW_CLKCTRL_FRAC1)...............................................................933 10.8.26 Clock Frequency Sequence Control Register (HW_CLKCTRL_CLKSEQ)..............................................935 10.8.27 System Reset Control Register (HW_CLKCTRL_RESET)........................................................................937 10.8.28 ClkCtrl Status (HW_CLKCTRL_STATUS)...............................................................................................939 10.8.29 ClkCtrl Version (HW_CLKCTRL_VERSION)..........................................................................................939 Chapter 11 Power Supply 11.1 Overview.......................................................................................................................................................................941 11.2 DC-DC Converters........................................................................................................................................................943 11.2.1 11.3 DC-DC Operation........................................................................................................................................943 11.2.1.1 Brownout/Error Detection........................................................................................................943 11.2.1.2 DC-DC Extended Battery Life Features..................................................................................945 Linear Regulators..........................................................................................................................................................947 11.3.1 USB Compliance Features...........................................................................................................................947 11.3.2 5V to Battery Power Interaction..................................................................................................................948 11.3.2.1 Battery Power to 5-V Power....................................................................................................948 11.3.2.2 5-V Power to Battery Power....................................................................................................948 11.3.2.3 5-V Power and Battery Power.................................................................................................949 11.3.3 Power-Up Sequence.....................................................................................................................................949 11.3.4 Power-Down Sequence................................................................................................................................950 11.3.4.1 11.3.5 Powered-Down State................................................................................................................951 Reset Sequence............................................................................................................................................951 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 24 Freescale Semiconductor, Inc. Section number 11.4 Title Page PSWITCH Pin Functions..............................................................................................................................................951 11.4.1 Power On......................................................................................................................................................951 11.4.2 Power Down.................................................................................................................................................952 11.4.3 Software Functions/Recovery Mode............................................................................................................952 11.5 Battery Monitor.............................................................................................................................................................953 11.6 Battery Charger.............................................................................................................................................................954 11.7 11.5.1 Battery Detection...............................................................................................................................................955 11.8 Silicon Speed Sensor.....................................................................................................................................................956 11.9 Thermal-Overload Protection Circuit...........................................................................................................................956 11.10 Bandgap Reference Generator......................................................................................................................................957 11.11 Interrupts.......................................................................................................................................................................957 11.12 Power Memory Map/Register Definition.....................................................................................................................957 11.12.1 Power Control Register (HW_POWER_CTRL).........................................................................................959 11.12.2 DC-DC 5V Control Register (HW_POWER_5VCTRL)............................................................................961 11.12.3 DC-DC Minimum Power and Miscellaneous Control Register (HW_POWER_MINPWR)......................964 11.12.4 Battery Charge Control Register (HW_POWER_CHARGE).....................................................................966 11.12.5 VDDD Supply Targets and Brownouts Control Register (HW_POWER_VDDDCTRL)..........................969 11.12.6 VDDA Supply Targets and Brownouts Control Register (HW_POWER_VDDACTRL)..........................971 11.12.7 VDDIO Supply Targets and Brownouts Control Register (HW_POWER_VDDIOCTRL).......................973 11.12.8 VDDMEM Supply Targets Control Register (HW_POWER_VDDMEMCTRL)......................................976 11.12.9 DC-DC Converter 4.2V Control Register (HW_POWER_DCDC4P2)......................................................978 11.12.10 DC-DC Miscellaneous Register (HW_POWER_MISC).............................................................................980 11.12.11 DC-DC Duty Cycle Limits Control Register (HW_POWER_DCLIMITS)................................................982 11.12.12 Converter Loop Behavior Control Register (HW_POWER_LOOPCTRL)................................................983 11.12.13 Power Subsystem Status Register (HW_POWER_STS).............................................................................986 11.12.14 Transistor Speed Control and Status Register (HW_POWER_SPEED).....................................................989 11.12.15 Battery Level Monitor Register (HW_POWER_BATTMONITOR)..........................................................990 11.12.16 Power Module Reset Register (HW_POWER_RESET).............................................................................991 11.12.17 Power Module Debug Register (HW_POWER_DEBUG)..........................................................................993 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 25 Section number Title Page 11.12.18 Power Module Thermal Reset Register (HW_POWER_THERMAL)........................................................994 11.12.19 Power Module USB1 Manual Controls Register (HW_POWER_USB1CTRL).........................................995 11.12.20 Power Module Special Register (HW_POWER_SPECIAL)......................................................................996 11.12.21 Power Module Version Register (HW_POWER_VERSION)....................................................................997 11.12.22 Analog Clock Control Register (HW_POWER_ANACLKCTRL).............................................................997 11.12.23 POWER Reference Control Register (HW_POWER_REFCTRL).............................................................999 Chapter 12 Boot Modes 12.1 Overview.......................................................................................................................................................................1003 12.2 Boot Modes...................................................................................................................................................................1004 12.3 12.2.1 Boot Pins Definition and Mode Selection....................................................................................................1005 12.2.2 Boot Mode Selection Map...........................................................................................................................1005 OTP eFuse and Persistent Bit Definitions....................................................................................................................1006 12.3.1 OTP eFuse....................................................................................................................................................1006 12.3.2 Persistent Bits...............................................................................................................................................1011 12.4 Memory Map................................................................................................................................................................1012 12.5 General Boot Procedure................................................................................................................................................1013 12.6 Program Image..............................................................................................................................................................1013 12.6.1 Image Vector Table (IVT)...........................................................................................................................1014 12.6.1.1 12.6.2 12.7 12.6.2.1 Write Data Command..............................................................................................................1019 12.6.2.2 Check Data Command.............................................................................................................1021 12.6.2.3 NOP Command........................................................................................................................1022 ROM Vector Table Addresses.....................................................................................................................1024 Constructing Boot Image (SB Files) to Be Loaded by ROM.......................................................................................1024 12.8.1 12.9 Device Configuration Data (DCD)..............................................................................................................1016 High Assurance Boot (HAB)........................................................................................................................................1023 12.7.1 12.8 Image Vector Table Structure..................................................................................................1015 ROM Commands.........................................................................................................................................1025 I2C Boot Mode.............................................................................................................................................................1027 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 26 Freescale Semiconductor, Inc. Section number Title Page 12.10 SPI Boot Mode..............................................................................................................................................................1027 12.10.1 SSP Pin Configuration.................................................................................................................................1028 12.10.2 Media Format...............................................................................................................................................1028 12.10.3 SSP...............................................................................................................................................................1029 12.11 SD/MMC Boot Mode...................................................................................................................................................1030 12.11.1 Boot Control Block (BCB) Data Structure..................................................................................................1032 12.11.2 Master Boot Record (MBR) Media Format.................................................................................................1032 12.11.3 eMMC Fast Boot Media Format..................................................................................................................1033 12.11.4 eSD Fast Boot Media Format.......................................................................................................................1034 12.11.5 Device Identification....................................................................................................................................1034 12.12 NAND Boot Mode........................................................................................................................................................1034 12.12.1 Raw NAND Device Boot.............................................................................................................................1034 12.12.1.1 Search Area..............................................................................................................................1035 12.12.1.2 Search Count............................................................................................................................1035 12.12.1.3 Search Stride............................................................................................................................1035 12.12.1.4 Boot Control Blocks (BCB).....................................................................................................1035 12.12.1.5 Redundant Boot Support in ROM NAND driver.....................................................................1037 12.12.1.6 NAND Patch Boot using FCB.................................................................................................1038 12.12.1.7 Expected NAND Layout..........................................................................................................1038 12.12.1.8 Firmware Configuration Block................................................................................................1041 12.12.1.9 Single Error Correct and Double Error Detect (SEC-DED) Hamming...................................1042 12.12.1.10 Firmware Layout on the NAND..............................................................................................1042 12.12.1.11 Recovery From a Failed Boot Firmware Image Read.............................................................1043 12.12.1.12 Bad Block Handling in the ROM.............................................................................................1043 12.12.1.13 Firmware Configuration Block Structure and Definitions.......................................................1045 12.12.1.14 Discovered Bad Block Table Header Layout Block Structure and Definitions.......................1047 12.12.1.15 Discovered Bad Block Table Layout Block Structure and Definitions...................................1048 12.12.2 Typical NAND Page Organization..............................................................................................................1048 12.12.2.1 BCH ECC Page Organization..................................................................................................1048 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 27 Section number 12.12.3 Title Page 12.12.2.2 Metadata...................................................................................................................................1050 12.12.2.3 efuses/OTP bits used by ROM NAND Driver.........................................................................1050 ONFi BA NAND Device Boot....................................................................................................................1051 12.13 USB Boot Driver...........................................................................................................................................................1052 12.13.1 Boot Loader Transaction Controller (BLTC)..............................................................................................1052 12.13.2 Plug-in Transaction Controller (PITC)........................................................................................................1052 12.13.3 USB IDs and Serial Number........................................................................................................................1053 12.13.4 USB Recovery Mode...................................................................................................................................1053 Chapter 13 Data Co-Processor (DCP) 13.1 Data Co-Processor (DCP) Overview............................................................................................................................1055 13.1.1 13.2 DCP Limitations for Software.....................................................................................................................1057 Operation.......................................................................................................................................................................1058 13.2.1 Memory Copy, Blit, and Fill Functionality..................................................................................................1058 13.2.2 Advanced Encryption Standard (AES)........................................................................................................1059 13.2.2.1 Key Storage..............................................................................................................................1059 13.2.2.2 AES OTP Key..........................................................................................................................1059 13.2.2.3 Encryption Modes....................................................................................................................1060 13.2.3 Hashing........................................................................................................................................................1061 13.2.4 One Time Programmable (OTP) Key..........................................................................................................1062 13.2.5 Managing DCP Channel Arbitration and Performance...............................................................................1062 13.2.6 13.2.5.1 DCP Arbitration.......................................................................................................................1062 13.2.5.2 Channel Recovery Timers........................................................................................................1063 Programming Channel Operations...............................................................................................................1063 13.2.6.1 Virtual Channels......................................................................................................................1064 13.2.6.2 Context Switching....................................................................................................................1065 13.2.6.3 Working with Semaphores.......................................................................................................1066 13.2.6.4 Work Packet Structure.............................................................................................................1067 13.2.6.4.1 Next Command Address Field............................................................................1067 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 28 Freescale Semiconductor, Inc. Section number 13.2.7 13.3 Title Page 13.2.6.4.2 Control0 Field.....................................................................................................1068 13.2.6.4.3 Control1 Field.....................................................................................................1070 13.2.6.4.4 Source Buffer......................................................................................................1070 13.2.6.4.5 Destination Buffer...............................................................................................1071 13.2.6.4.6 Buffer Size Field.................................................................................................1071 13.2.6.4.7 Payload Pointer...................................................................................................1071 13.2.6.4.8 Status...................................................................................................................1072 13.2.6.4.9 Payload................................................................................................................1072 Programming DCP Functions......................................................................................................................1074 13.2.7.1 Basic Memory Copy Programming Example..........................................................................1074 13.2.7.2 Basic Hash Operation Programming Example........................................................................1075 13.2.7.3 Basic Cipher Operation Programming Example......................................................................1076 13.2.7.4 Multi-Buffer Scatter/Gather Cipher and Hash Operation Programming Example..................1078 Programmable Registers...............................................................................................................................................1081 13.3.1 DCP Control Register 0 (HW_DCP_CTRL)...............................................................................................1083 13.3.2 DCP Status Register (HW_DCP_STAT).....................................................................................................1086 13.3.3 DCP Channel Control Register (HW_DCP_CHANNELCTRL).................................................................1088 13.3.4 DCP Capability 0 Register (HW_DCP_CAPABILITY0)...........................................................................1090 13.3.5 DCP Capability 1 Register (HW_DCP_CAPABILITY1)...........................................................................1091 13.3.6 DCP Context Buffer Pointer (HW_DCP_CONTEXT)...............................................................................1092 13.3.7 DCP Key Index (HW_DCP_KEY)..............................................................................................................1092 13.3.8 DCP Key Data (HW_DCP_KEYDATA)....................................................................................................1093 13.3.9 DCP Work Packet 0 Status Register (HW_DCP_PACKET0)....................................................................1094 13.3.10 DCP Work Packet 1 Status Register (HW_DCP_PACKET1)....................................................................1094 13.3.11 DCP Work Packet 2 Status Register (HW_DCP_PACKET2)....................................................................1098 13.3.12 DCP Work Packet 3 Status Register (HW_DCP_PACKET3)....................................................................1099 13.3.13 DCP Work Packet 4 Status Register (HW_DCP_PACKET4)....................................................................1099 13.3.14 DCP Work Packet 5 Status Register (HW_DCP_PACKET5)....................................................................1100 13.3.15 DCP Work Packet 6 Status Register (HW_DCP_PACKET6)....................................................................1100 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 29 Section number 13.4 Title Page 13.3.16 DCP Channel 0 Command Pointer Address Register (HW_DCP_CH0CMDPTR)....................................1101 13.3.17 DCP Channel 0 Semaphore Register (HW_DCP_CH0SEMA)..................................................................1102 13.3.18 DCP Channel 0 Status Register (HW_DCP_CH0STAT)............................................................................1103 13.3.19 DCP Channel 0 Options Register (HW_DCP_CH0OPTS).........................................................................1105 13.3.20 DCP Channel 1 Command Pointer Address Register (HW_DCP_CH1CMDPTR)....................................1106 13.3.21 DCP Channel 1 Semaphore Register (HW_DCP_CH1SEMA)..................................................................1107 13.3.22 DCP Channel 1 Status Register (HW_DCP_CH1STAT)............................................................................1108 13.3.23 DCP Channel 1 Options Register (HW_DCP_CH1OPTS).........................................................................1110 13.3.24 DCP Channel 2 Command Pointer Address Register (HW_DCP_CH2CMDPTR)....................................1111 13.3.25 DCP Channel 2 Semaphore Register (HW_DCP_CH2SEMA)..................................................................1112 13.3.26 DCP Channel 2 Status Register (HW_DCP_CH2STAT)............................................................................1113 13.3.27 DCP Channel 2 Options Register (HW_DCP_CH2OPTS).........................................................................1115 13.3.28 DCP Channel 3 Command Pointer Address Register (HW_DCP_CH3CMDPTR)....................................1116 13.3.29 DCP Channel 3 Semaphore Register (HW_DCP_CH3SEMA)..................................................................1117 13.3.30 DCP Channel 3 Status Register (HW_DCP_CH3STAT)............................................................................1118 13.3.31 DCP Channel 3 Options Register (HW_DCP_CH3OPTS).........................................................................1120 13.3.32 DCP Debug Select Register (HW_DCP_DBGSELECT)............................................................................1121 13.3.33 DCP Debug Data Register (HW_DCP_DBGDATA)..................................................................................1121 13.3.34 DCP Page Table Register (HW_DCP_PAGETABLE)...............................................................................1122 13.3.35 DCP Version Register (HW_DCP_VERSION)..........................................................................................1122 Disclaimer.....................................................................................................................................................................1123 Chapter 14 External Memory Interface (EMI) 14.1 Overview.......................................................................................................................................................................1125 14.1.1 14.2 Block Diagram.............................................................................................................................................1125 EMI Address Mapping..................................................................................................................................................1126 14.2.1 DDR SDRAM Address Mapping Options...................................................................................................1127 14.2.2 Maximum Address Space............................................................................................................................1127 14.2.3 Memory Mapping to Address Space............................................................................................................1127 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 30 Freescale Semiconductor, Inc. Section number 14.3 14.4 Title Page EMI Clocking...............................................................................................................................................................1128 14.3.1 General System Behavior.............................................................................................................................1128 14.3.2 Changing Input Clock Frequency................................................................................................................1128 EMI AHB and AXI Interface........................................................................................................................................1130 14.4.1 AHB-AXI Bridges.......................................................................................................................................1130 14.4.2 AXI Interfaces..............................................................................................................................................1130 14.4.2.1 Internal Command Handling....................................................................................................1130 14.4.2.2 AHB Signal to AXI Signal Translation...................................................................................1132 14.4.2.3 Configured Options..................................................................................................................1132 14.4.3 Port Clocking...............................................................................................................................................1134 14.4.4 AXI Interface FIFOs....................................................................................................................................1135 14.4.5 AXI Write Response Channel......................................................................................................................1136 14.4.6 AHB Register Port.......................................................................................................................................1137 14.4.7 AXI Transactions.........................................................................................................................................1137 14.4.8 Exclusive Access..........................................................................................................................................1137 14.4.9 14.4.8.1 Initiating an Exclusive Access Request...................................................................................1138 14.4.8.2 Verifying the Request..............................................................................................................1138 14.4.8.3 Validity of an Exclusive Request.............................................................................................1138 14.4.8.4 Read Commands to Exclusive Access Regions.......................................................................1139 14.4.8.5 Non-Exclusive Write Commands to Exclusive Access Regions.............................................1139 14.4.8.6 Exclusive Writes......................................................................................................................1140 14.4.8.7 Passing Exclusive Access Check.............................................................................................1140 14.4.8.8 Failing Exclusive Access Check..............................................................................................1140 Error Responses...........................................................................................................................................1141 14.4.9.1 AXI Error Response.................................................................................................................1141 14.4.9.2 AXI Error Reporting................................................................................................................1141 14.4.10 Arbiter..........................................................................................................................................................1141 14.4.11 Write Data Queue.........................................................................................................................................1142 14.4.12 DRAM Command Processing......................................................................................................................1142 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 31 Section number 14.4.13 14.5 Latency.........................................................................................................................................................1142 14.5.1 Arbitration Overview...................................................................................................................................1145 14.5.2 Understanding Round-Robin Arbitration.....................................................................................................1145 14.5.3 Understanding Port Priority.........................................................................................................................1146 14.5.4 Understanding Port Bandwidth....................................................................................................................1146 14.5.5 Understanding Port Bandwidth Hold-Off....................................................................................................1149 14.5.6 Priority Round-Robin Arbitration Summary...............................................................................................1150 14.5.7 Arbitration Examples...................................................................................................................................1151 14.5.8 Configuring and Programming for Priority Round-Robin Arbitration........................................................1152 14.5.8.1 Definition of the Statistics Window and the Number of Counters..........................................1153 14.5.8.2 Command Priority, Port Bandwidth, and Bandwidth Overflow..............................................1153 Command Queue with Placement Logic.....................................................................................................1153 Core Command Queue with Placement Logic..............................................................................................................1154 14.6.1 14.6.2 14.7 Page EMI Multi-Port Arbiter.................................................................................................................................................1144 14.5.9 14.6 Title Rules of the Placement Algorithm...............................................................................................................1154 14.6.1.1 Address Collision/Data Coherency Violation..........................................................................1154 14.6.1.2 Source ID Collision..................................................................................................................1155 14.6.1.3 Write Buffer Collision.............................................................................................................1155 14.6.1.4 Priority.....................................................................................................................................1156 14.6.1.5 Bank Splitting..........................................................................................................................1156 14.6.1.6 Read/Write Grouping...............................................................................................................1156 Command Execution Order After Placement..............................................................................................1157 14.6.2.1 Command Aging......................................................................................................................1157 14.6.2.2 High-Priority Command Swapping.........................................................................................1158 DDR PHY.....................................................................................................................................................................1159 14.7.1 High Level Block Diagram..........................................................................................................................1159 14.7.2 DFI...............................................................................................................................................................1160 14.7.3 I/O Timing of Address and Command.........................................................................................................1160 14.7.4 Data Slice Overview....................................................................................................................................1162 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 32 Freescale Semiconductor, Inc. Section number 14.8 Title Page 14.7.5 Read Data Capture.......................................................................................................................................1163 14.7.6 Synchronize Read Data From delayed_dqs to emi_clk Domain.................................................................1163 14.7.7 Write Data Path............................................................................................................................................1165 14.7.8 Write Data Path Low-Latency Option ........................................................................................................1166 14.7.9 Digital DLL and the Delay-Line..................................................................................................................1167 14.7.10 Configure output enable of I/O Control.......................................................................................................1169 Programmable Registers...............................................................................................................................................1171 14.8.1 DRAM Control Register 00 (HW_DRAM_CTL00)...................................................................................1179 14.8.2 AXI Monitor Control (HW_DRAM_CTL01).............................................................................................1180 14.8.3 DRAM Control Register 02 (HW_DRAM_CTL02)...................................................................................1181 14.8.4 DRAM Control Register 03 (HW_DRAM_CTL03)...................................................................................1181 14.8.5 DRAM Control Register 04 (HW_DRAM_CTL04)...................................................................................1182 14.8.6 DRAM Control Register 05 (HW_DRAM_CTL05)...................................................................................1182 14.8.7 DRAM Control Register 06 (HW_DRAM_CTL06)...................................................................................1183 14.8.8 DRAM Control Register 07 (HW_DRAM_CTL07)...................................................................................1183 14.8.9 DRAM Control Register 08 (HW_DRAM_CTL08)...................................................................................1184 14.8.10 DRAM Control Register 09 (HW_DRAM_CTL09)...................................................................................1186 14.8.11 AXI0 Debug 0 (HW_DRAM_CTL10)........................................................................................................1186 14.8.12 AXI0 Debug 1 (HW_DRAM_CTL11)........................................................................................................1187 14.8.13 AXI1 Debug 0 (HW_DRAM_CTL12)........................................................................................................1187 14.8.14 AXI1 Debug 1 (HW_DRAM_CTL13)........................................................................................................1188 14.8.15 AXI2 Debug 0 (HW_DRAM_CTL14)........................................................................................................1188 14.8.16 AXI2 Debug 1 (HW_DRAM_CTL15)........................................................................................................1189 14.8.17 DRAM Control Register 16 (HW_DRAM_CTL16)...................................................................................1190 14.8.18 DRAM Control Register 17 (HW_DRAM_CTL17)...................................................................................1192 14.8.19 DRAM Control Register 21 (HW_DRAM_CTL21)...................................................................................1194 14.8.20 DRAM Control Register 22 (HW_DRAM_CTL22)...................................................................................1195 14.8.21 DRAM Control Register 23 (HW_DRAM_CTL23)...................................................................................1197 14.8.22 DRAM Control Register 24 (HW_DRAM_CTL24)...................................................................................1197 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 33 Section number Title Page 14.8.23 DRAM Control Register 25 (HW_DRAM_CTL25)...................................................................................1198 14.8.24 DRAM Control Register 26 (HW_DRAM_CTL26)...................................................................................1199 14.8.25 DRAM Control Register 27 (HW_DRAM_CTL27)...................................................................................1201 14.8.26 DRAM Control Register 28 (HW_DRAM_CTL28)...................................................................................1203 14.8.27 DRAM Control Register 29 (HW_DRAM_CTL29)...................................................................................1204 14.8.28 DRAM Control Register 30 (HW_DRAM_CTL30)...................................................................................1205 14.8.29 DRAM Control Register 31 (HW_DRAM_CTL31)...................................................................................1207 14.8.30 DRAM Control Register 32 (HW_DRAM_CTL32)...................................................................................1209 14.8.31 DRAM Control Register 33 (HW_DRAM_CTL33)...................................................................................1210 14.8.32 DRAM Control Register 34 (HW_DRAM_CTL34)...................................................................................1212 14.8.33 DRAM Control Register 35 (HW_DRAM_CTL35)...................................................................................1214 14.8.34 DRAM Control Register 36 (HW_DRAM_CTL36)...................................................................................1216 14.8.35 DRAM Control Register 37 (HW_DRAM_CTL37)...................................................................................1217 14.8.36 DRAM Control Register 38 (HW_DRAM_CTL38)...................................................................................1219 14.8.37 DRAM Control Register 39 (HW_DRAM_CTL39)...................................................................................1220 14.8.38 DRAM Control Register 40 (HW_DRAM_CTL40)...................................................................................1221 14.8.39 DRAM Control Register 41 (HW_DRAM_CTL41)...................................................................................1221 14.8.40 DRAM Control Register 42 (HW_DRAM_CTL42)...................................................................................1222 14.8.41 DRAM Control Register 43 (HW_DRAM_CTL43)...................................................................................1223 14.8.42 DRAM Control Register 44 (HW_DRAM_CTL44)...................................................................................1223 14.8.43 DRAM Control Register 45 (HW_DRAM_CTL45)...................................................................................1224 14.8.44 DRAM Control Register 48 (HW_DRAM_CTL48)...................................................................................1225 14.8.45 DRAM Control Register 49 (HW_DRAM_CTL49)...................................................................................1226 14.8.46 DRAM Control Register 50 (HW_DRAM_CTL50)...................................................................................1228 14.8.47 DRAM Control Register 51 (HW_DRAM_CTL51)...................................................................................1229 14.8.48 DRAM Control Register 52 (HW_DRAM_CTL52)...................................................................................1231 14.8.49 DRAM Control Register 53 (HW_DRAM_CTL53)...................................................................................1232 14.8.50 DRAM Control Register 54 (HW_DRAM_CTL54)...................................................................................1234 14.8.51 DRAM Control Register 55 (HW_DRAM_CTL55)...................................................................................1235 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 34 Freescale Semiconductor, Inc. Section number Title Page 14.8.52 DRAM Control Register 56 (HW_DRAM_CTL56)...................................................................................1236 14.8.53 DRAM Control Register 58 (HW_DRAM_CTL58)...................................................................................1237 14.8.54 DRAM Control Register 59 (HW_DRAM_CTL59)...................................................................................1238 14.8.55 DRAM Control Register 60 (HW_DRAM_CTL60)...................................................................................1238 14.8.56 DRAM Control Register 61 (HW_DRAM_CTL61)...................................................................................1239 14.8.57 DRAM Control Register 62 (HW_DRAM_CTL62)...................................................................................1240 14.8.58 DRAM Control Register 63 (HW_DRAM_CTL63)...................................................................................1241 14.8.59 DRAM Control Register 64 (HW_DRAM_CTL64)...................................................................................1241 14.8.60 DRAM Control Register 65 (HW_DRAM_CTL65)...................................................................................1242 14.8.61 DRAM Control Register 66 (HW_DRAM_CTL66)...................................................................................1243 14.8.62 DRAM Control Register 67 (HW_DRAM_CTL67)...................................................................................1244 14.8.63 DRAM Control Register 68 (HW_DRAM_CTL68)...................................................................................1245 14.8.64 DRAM Control Register 69 (HW_DRAM_CTL69)...................................................................................1246 14.8.65 DRAM Control Register 70 (HW_DRAM_CTL70)...................................................................................1247 14.8.66 DRAM Control Register 71 (HW_DRAM_CTL71)...................................................................................1248 14.8.67 DRAM Control Register 72 (HW_DRAM_CTL72)...................................................................................1250 14.8.68 DRAM Control Register 73 (HW_DRAM_CTL73)...................................................................................1250 14.8.69 DRAM Control Register 74 (HW_DRAM_CTL74)...................................................................................1251 14.8.70 DRAM Control Register 75 (HW_DRAM_CTL75)...................................................................................1251 14.8.71 DRAM Control Register 76 (HW_DRAM_CTL76)...................................................................................1252 14.8.72 DRAM Control Register 77 (HW_DRAM_CTL77)...................................................................................1253 14.8.73 DRAM Control Register 78 (HW_DRAM_CTL78)...................................................................................1253 14.8.74 DRAM Control Register 79 (HW_DRAM_CTL79)...................................................................................1254 14.8.75 DRAM Control Register 80 (HW_DRAM_CTL80)...................................................................................1255 14.8.76 DRAM Control Register 81 (HW_DRAM_CTL81)...................................................................................1255 14.8.77 DRAM Control Register 82 (HW_DRAM_CTL82)...................................................................................1256 14.8.78 DRAM Control Register 83 (HW_DRAM_CTL83)...................................................................................1257 14.8.79 DRAM Control Register 84 (HW_DRAM_CTL84)...................................................................................1259 14.8.80 DRAM Control Register 85 (HW_DRAM_CTL85)...................................................................................1260 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 35 Section number Title Page 14.8.81 DRAM Control Register 86 (HW_DRAM_CTL86)...................................................................................1261 14.8.82 DRAM Control Register 87 (HW_DRAM_CTL87)...................................................................................1262 14.8.83 DRAM Control Register 88 (HW_DRAM_CTL88)...................................................................................1263 14.8.84 DRAM Control Register 89 (HW_DRAM_CTL89)...................................................................................1263 14.8.85 DRAM Control Register 90 (HW_DRAM_CTL90)...................................................................................1264 14.8.86 DRAM Control Register 91 (HW_DRAM_CTL91)...................................................................................1265 14.8.87 DRAM Control Register 92 (HW_DRAM_CTL92)...................................................................................1265 14.8.88 DRAM Control Register 93 (HW_DRAM_CTL93)...................................................................................1266 14.8.89 DRAM Control Register 94 (HW_DRAM_CTL94)...................................................................................1267 14.8.90 DRAM Control Register 95 (HW_DRAM_CTL95)...................................................................................1267 14.8.91 DRAM Control Register 96 (HW_DRAM_CTL96)...................................................................................1268 14.8.92 DRAM Control Register 97 (HW_DRAM_CTL97)...................................................................................1268 14.8.93 DRAM Control Register 98 (HW_DRAM_CTL98)...................................................................................1269 14.8.94 DRAM Control Register 99 (HW_DRAM_CTL99)...................................................................................1270 14.8.95 DRAM Control Register 100 (HW_DRAM_CTL100)...............................................................................1271 14.8.96 DRAM Control Register 101 (HW_DRAM_CTL101)...............................................................................1272 14.8.97 DRAM Control Register 102 (HW_DRAM_CTL102)...............................................................................1273 14.8.98 DRAM Control Register 103 (HW_DRAM_CTL103)...............................................................................1274 14.8.99 DRAM Control Register 104 (HW_DRAM_CTL104)...............................................................................1274 14.8.100 DRAM Control Register 105 (HW_DRAM_CTL105)...............................................................................1275 14.8.101 DRAM Control Register 106 (HW_DRAM_CTL106)...............................................................................1275 14.8.102 DRAM Control Register 107 (HW_DRAM_CTL107)...............................................................................1276 14.8.103 DRAM Control Register 108 (HW_DRAM_CTL108)...............................................................................1276 14.8.104 DRAM Control Register 109 (HW_DRAM_CTL109)...............................................................................1277 14.8.105 DRAM Control Register 110 (HW_DRAM_CTL110)...............................................................................1277 14.8.106 DRAM Control Register 111 (HW_DRAM_CTL111)...............................................................................1278 14.8.107 DRAM Control Register 112 (HW_DRAM_CTL112)...............................................................................1278 14.8.108 DRAM Control Register 113 (HW_DRAM_CTL113)...............................................................................1279 14.8.109 DRAM Control Register 114 (HW_DRAM_CTL114)...............................................................................1279 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 36 Freescale Semiconductor, Inc. Section number Title Page 14.8.110 DRAM Control Register 115 (HW_DRAM_CTL115)...............................................................................1280 14.8.111 DRAM Control Register 116 (HW_DRAM_CTL116)...............................................................................1280 14.8.112 DRAM Control Register 117 (HW_DRAM_CTL117)...............................................................................1281 14.8.113 DRAM Control Register 118 (HW_DRAM_CTL118)...............................................................................1281 14.8.114 DRAM Control Register 119 (HW_DRAM_CTL119)...............................................................................1282 14.8.115 DRAM Control Register 120 (HW_DRAM_CTL120)...............................................................................1282 14.8.116 DRAM Control Register 121 (HW_DRAM_CTL121)...............................................................................1283 14.8.117 DRAM Control Register 122 (HW_DRAM_CTL122)...............................................................................1283 14.8.118 DRAM Control Register 123 (HW_DRAM_CTL123)...............................................................................1284 14.8.119 DRAM Control Register 124 (HW_DRAM_CTL124)...............................................................................1284 14.8.120 DRAM Control Register 125 (HW_DRAM_CTL125)...............................................................................1285 14.8.121 DRAM Control Register 126 (HW_DRAM_CTL126)...............................................................................1285 14.8.122 DRAM Control Register 127 (HW_DRAM_CTL127)...............................................................................1286 14.8.123 DRAM Control Register 128 (HW_DRAM_CTL128)...............................................................................1286 14.8.124 DRAM Control Register 129 (HW_DRAM_CTL129)...............................................................................1287 14.8.125 DRAM Control Register 130 (HW_DRAM_CTL130)...............................................................................1287 14.8.126 DRAM Control Register 131 (HW_DRAM_CTL131)...............................................................................1288 14.8.127 DRAM Control Register 132 (HW_DRAM_CTL132)...............................................................................1288 14.8.128 DRAM Control Register 133 (HW_DRAM_CTL133)...............................................................................1289 14.8.129 DRAM Control Register 134 (HW_DRAM_CTL134)...............................................................................1289 14.8.130 DRAM Control Register 135 (HW_DRAM_CTL135)...............................................................................1290 14.8.131 DRAM Control Register 136 (HW_DRAM_CTL136)...............................................................................1290 14.8.132 DRAM Control Register 137 (HW_DRAM_CTL137)...............................................................................1291 14.8.133 DRAM Control Register 138 (HW_DRAM_CTL138)...............................................................................1291 14.8.134 DRAM Control Register 139 (HW_DRAM_CTL139)...............................................................................1292 14.8.135 DRAM Control Register 140 (HW_DRAM_CTL140)...............................................................................1292 14.8.136 DRAM Control Register 141 (HW_DRAM_CTL141)...............................................................................1293 14.8.137 DRAM Control Register 142 (HW_DRAM_CTL142)...............................................................................1293 14.8.138 DRAM Control Register 143 (HW_DRAM_CTL143)...............................................................................1294 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 37 Section number Title Page 14.8.139 DRAM Control Register 144 (HW_DRAM_CTL144)...............................................................................1294 14.8.140 DRAM Control Register 145 (HW_DRAM_CTL145)...............................................................................1295 14.8.141 DRAM Control Register 146 (HW_DRAM_CTL146)...............................................................................1295 14.8.142 DRAM Control Register 147 (HW_DRAM_CTL147)...............................................................................1296 14.8.143 DRAM Control Register 148 (HW_DRAM_CTL148)...............................................................................1296 14.8.144 DRAM Control Register 149 (HW_DRAM_CTL149)...............................................................................1297 14.8.145 DRAM Control Register 150 (HW_DRAM_CTL150)...............................................................................1297 14.8.146 DRAM Control Register 151 (HW_DRAM_CTL151)...............................................................................1298 14.8.147 DRAM Control Register 152 (HW_DRAM_CTL152)...............................................................................1298 14.8.148 DRAM Control Register 153 (HW_DRAM_CTL153)...............................................................................1299 14.8.149 DRAM Control Register 154 (HW_DRAM_CTL154)...............................................................................1299 14.8.150 DRAM Control Register 155 (HW_DRAM_CTL155)...............................................................................1300 14.8.151 DRAM Control Register 156 (HW_DRAM_CTL156)...............................................................................1300 14.8.152 DRAM Control Register 157 (HW_DRAM_CTL157)...............................................................................1301 14.8.153 DRAM Control Register 158 (HW_DRAM_CTL158)...............................................................................1301 14.8.154 DRAM Control Register 159 (HW_DRAM_CTL159)...............................................................................1302 14.8.155 DRAM Control Register 160 (HW_DRAM_CTL160)...............................................................................1302 14.8.156 DRAM Control Register 161 (HW_DRAM_CTL161)...............................................................................1303 14.8.157 DRAM Control Register 162 (HW_DRAM_CTL162)...............................................................................1303 14.8.158 DRAM Control Register 163 (HW_DRAM_CTL163)...............................................................................1304 14.8.159 DRAM Control Register 164 (HW_DRAM_CTL164)...............................................................................1305 14.8.160 DRAM Control Register 171 (HW_DRAM_CTL171)...............................................................................1306 14.8.161 DRAM Control Register 172 (HW_DRAM_CTL172)...............................................................................1308 14.8.162 DRAM Control Register 173 (HW_DRAM_CTL173)...............................................................................1309 14.8.163 DRAM Control Register 174 (HW_DRAM_CTL174)...............................................................................1310 14.8.164 DRAM Control Register 175 (HW_DRAM_CTL175)...............................................................................1311 14.8.165 DRAM Control Register 176 (HW_DRAM_CTL176)...............................................................................1313 14.8.166 DRAM Control Register 177 (HW_DRAM_CTL177)...............................................................................1314 14.8.167 DRAM Control Register 178 (HW_DRAM_CTL178)...............................................................................1315 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 38 Freescale Semiconductor, Inc. Section number Title Page 14.8.168 DRAM Control Register 179 (HW_DRAM_CTL179)...............................................................................1316 14.8.169 DRAM Control Register 180 (HW_DRAM_CTL180)...............................................................................1317 14.8.170 DRAM Control Register 181 (HW_DRAM_CTL181)...............................................................................1318 14.8.171 DRAM Control Register 182 (HW_DRAM_CTL182)...............................................................................1320 14.8.172 DRAM Control Register 183 (HW_DRAM_CTL183)...............................................................................1322 14.8.173 DRAM Control Register 184 (HW_DRAM_CTL184)...............................................................................1324 14.8.174 DRAM Control Register 185 (HW_DRAM_CTL185)...............................................................................1326 14.8.175 DRAM Control Register 186 (HW_DRAM_CTL186)...............................................................................1328 14.8.176 DRAM Control Register 187 (HW_DRAM_CTL187)...............................................................................1330 14.8.177 DRAM Control Register 188 (HW_DRAM_CTL188)...............................................................................1332 14.8.178 DRAM Control Register 189 (HW_DRAM_CTL189)...............................................................................1333 Chapter 15 General-Purpose Media Interface(GPMI) 15.1 General-Purpose Media Interface Overview................................................................................................................1335 15.2 GPMI NAND Mode......................................................................................................................................................1336 15.2.1 Multiple NAND Support..............................................................................................................................1337 15.2.2 GPMI NAND Timing and Clocking............................................................................................................1338 15.2.3 Basic NAND Timing...................................................................................................................................1338 15.2.4 High-Speed NAND Timing.........................................................................................................................1338 15.2.5 NAND Command and Address Timing Example........................................................................................1341 15.2.6 Hardware BCH Interface.............................................................................................................................1341 15.3 Behavior During Reset..................................................................................................................................................1342 15.4 Programmable Registers...............................................................................................................................................1342 15.4.1 GPMI Control Register 0 (HW_GPMI_CTRL0).........................................................................................1343 15.4.2 GPMI Compare Register (HW_GPMI_COMPARE)..................................................................................1346 15.4.3 GPMI Integrated ECC Control Register (HW_GPMI_ECCCTRL)............................................................1346 15.4.4 GPMI Integrated ECC Transfer Count Register (HW_GPMI_ECCCOUNT)............................................1348 15.4.5 GPMI Payload Address Register (HW_GPMI_PAYLOAD)......................................................................1348 15.4.6 GPMI Auxiliary Address Register (HW_GPMI_AUXILIARY)................................................................1349 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 39 Section number Title Page 15.4.7 GPMI Control Register 1 (HW_GPMI_CTRL1).........................................................................................1349 15.4.8 GPMI Timing Register 0 (HW_GPMI_TIMING0).....................................................................................1352 15.4.9 GPMI Timing Register 1 (HW_GPMI_TIMING1).....................................................................................1353 15.4.10 GPMI DMA Data Transfer Register (HW_GPMI_DATA).........................................................................1353 15.4.11 GPMI Status Register (HW_GPMI_STAT)................................................................................................1354 15.4.12 GPMI Debug Information Register (HW_GPMI_DEBUG).......................................................................1357 15.4.13 GPMI Version Register (HW_GPMI_VERSION)......................................................................................1357 Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 16.1 Overview.......................................................................................................................................................................1359 16.2 Operation.......................................................................................................................................................................1361 16.2.1 BCH Limitations and Assumptions.............................................................................................................1362 16.2.2 Flash Page Layout........................................................................................................................................1363 16.2.3 Determining the ECC layout for a device....................................................................................................1365 16.2.4 16.2.3.1 4K+218 flash, 10 bytes metadata, 512 byte data blocks, separate metadata...........................1365 16.2.3.2 4K+128 flash, 10 bytes metadata, 512 byte data blocks, separate metadata...........................1366 Data Buffers in System Memory.................................................................................................................1366 16.3 Memory to Memory (Loopback) Operation.................................................................................................................1369 16.4 Programming the BCH/GPMI Interfaces......................................................................................................................1370 16.4.1 16.4.2 16.4.3 BCH Encoding for NAND Writes...............................................................................................................1371 16.4.1.1 DMA Structure Code Example................................................................................................1373 16.4.1.2 Using the BCH Encoder...........................................................................................................1378 BCH Decoding for NAND Reads................................................................................................................1379 16.4.2.1 DMA Structure Code Example................................................................................................1383 16.4.2.2 Using the Decoder....................................................................................................................1386 Interrupts......................................................................................................................................................1388 16.5 Behavior During Reset..................................................................................................................................................1389 16.6 BCH Memory Map/Register Definition.......................................................................................................................1389 16.6.1 Hardware BCH ECC Accelerator Control Register (BCH_CTRL).............................................................1391 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 40 Freescale Semiconductor, Inc. Section number Title Page 16.6.2 Hardware ECC Accelerator Status Register 0 (BCH_STATUS0)..............................................................1393 16.6.3 Hardware ECC Accelerator Mode Register (BCH_MODE).......................................................................1394 16.6.4 Hardware BCH ECC Loopback Encode Buffer Register (BCH_ENCODEPTR).......................................1395 16.6.5 Hardware BCH ECC Loopback Data Buffer Register (BCH_DATAPTR)................................................1395 16.6.6 Hardware BCH ECC Loopback Metadata Buffer Register (BCH_METAPTR).........................................1396 16.6.7 Hardware ECC Accelerator Layout Select Register (BCH_LAYOUTSELECT).......................................1396 16.6.8 Hardware BCH ECC Flash 0 Layout 0 Register (BCH_FLASH0LAYOUT0)...........................................1397 16.6.9 Hardware BCH ECC Flash 0 Layout 1 Register (BCH_FLASH0LAYOUT1)...........................................1399 16.6.10 Hardware BCH ECC Flash 1 Layout 0 Register (BCH_FLASH1LAYOUT0)...........................................1399 16.6.11 Hardware BCH ECC Flash 1 Layout 1 Register (BCH_FLASH1LAYOUT1)...........................................1401 16.6.12 Hardware BCH ECC Flash 2 Layout 0 Register (BCH_FLASH2LAYOUT0)...........................................1401 16.6.13 Hardware BCH ECC Flash 2 Layout 1 Register (BCH_FLASH2LAYOUT1)...........................................1403 16.6.14 Hardware BCH ECC Flash 3 Layout 0 Register (BCH_FLASH3LAYOUT0)...........................................1403 16.6.15 Hardware BCH ECC Flash 3 Layout 1 Register (BCH_FLASH3LAYOUT1)...........................................1405 16.6.16 Hardware BCH ECC Debug Register0 (BCH_DEBUG0)..........................................................................1405 16.6.17 KES Debug Read Register (BCH_DBGKESREAD)..................................................................................1407 16.6.18 Chien Search Debug Read Register (BCH_DBGCSFEREAD)..................................................................1408 16.6.19 Syndrome Generator Debug Read Register (BCH_DBGSYNDGENREAD).............................................1408 16.6.20 Bus Master and ECC Controller Debug Read Register (BCH_DBGAHBMREAD)..................................1409 16.6.21 Block Name Register (BCH_BLOCKNAME)............................................................................................1409 16.6.22 BCH Version Register (BCH_VERSION)..................................................................................................1410 Chapter 17 Synchronous Serial Ports (SSP) 17.1 Overview.......................................................................................................................................................................1411 17.2 External Pins.................................................................................................................................................................1412 17.3 Bit Rate Generation.......................................................................................................................................................1413 17.4 Frame Format for SPI and SSI......................................................................................................................................1413 17.5 Motorola SPI Mode.......................................................................................................................................................1414 17.5.1 SPI DMA Mode...........................................................................................................................................1414 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 41 Section number 17.5.2 Title Page Motorola SPI Frame Format........................................................................................................................1414 17.5.2.1 Clock Polarity..........................................................................................................................1415 17.5.2.2 Clock Phase..............................................................................................................................1415 17.5.3 Motorola SPI Format with Polarity=0, Phase=0..........................................................................................1415 17.5.4 Motorola SPI Format with Polarity=0, Phase=1..........................................................................................1416 17.5.5 Motorola SPI Format with Polarity=1, Phase=0..........................................................................................1417 17.5.6 Motorola SPI Format with Polarity=1, Phase=1..........................................................................................1419 17.6 Winbond SPI Mode.......................................................................................................................................................1420 17.7 Texas Instruments Synchronous Serial Interface (SSI) Mode......................................................................................1421 17.8 SD/SDIO/MMC Mode..................................................................................................................................................1422 17.9 17.8.1 SD/MMC Command/Response Transfer.....................................................................................................1422 17.8.2 SD/MMC Data Block Transfer....................................................................................................................1424 17.8.2.1 SD/MMC Multiple Block Transfers........................................................................................1425 17.8.2.2 eMMC DDR operation.............................................................................................................1426 17.8.2.3 SD/MMC Block Transfer CRC Protection..............................................................................1426 17.8.3 eMMC Boot Operation................................................................................................................................1426 17.8.4 SDIO Interrupts............................................................................................................................................1427 17.8.5 SD/MMC Mode Error Handling..................................................................................................................1427 17.8.6 SD/MMC Clock Control..............................................................................................................................1429 Behavior During Reset..................................................................................................................................................1430 17.10 Programmable Registers...............................................................................................................................................1430 17.10.1 SSP Control Register 0 (HW_SSP_CTRL0)...............................................................................................1431 17.10.2 SD/MMC Command Register 0 (HW_SSP_CMD0)...................................................................................1434 17.10.3 SD/MMC Command Register 1 (HW_SSP_CMD1)...................................................................................1437 17.10.4 Transfer Count Register (HW_SSP_XFER_SIZE).....................................................................................1438 17.10.5 SD/MMC BLOCK SIZE and COUNT Register (HW_SSP_BLOCK_SIZE).............................................1438 17.10.6 SD/MMC Compare Reference (HW_SSP_COMPREF).............................................................................1439 17.10.7 SD/MMC compare mask (HW_SSP_COMPMASK)..................................................................................1439 17.10.8 SSP Timing Register (HW_SSP_TIMING)................................................................................................1439 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 42 Freescale Semiconductor, Inc. Section number 17.10.9 Title Page SSP Control Register 1 (HW_SSP_CTRL1)...............................................................................................1440 17.10.10 SSP Data Register (HW_SSP_DATA)........................................................................................................1443 17.10.11 SD/MMC Card Response Register 0 (HW_SSP_SDRESP0)......................................................................1444 17.10.12 SD/MMC Card Response Register 1 (HW_SSP_SDRESP1)......................................................................1444 17.10.13 SD/MMC Card Response Register 2 (HW_SSP_SDRESP2)......................................................................1445 17.10.14 SD/MMC Card Response Register 3 (HW_SSP_SDRESP3)......................................................................1445 17.10.15 SD/MMC Double Data Rate Control Register (HW_SSP_DDR_CTRL)...................................................1445 17.10.16 SD/MMC DLL Control Register (HW_SSP_DLL_CTRL)........................................................................1447 17.10.17 SSP Status Register (HW_SSP_STATUS)..................................................................................................1448 17.10.18 SD/MMC DLL Status Register (HW_SSP_DLL_STS)..............................................................................1451 17.10.19 SSP Debug Register (HW_SSP_DEBUG)..................................................................................................1452 17.10.20 SSP Version Register (HW_SSP_VERSION).............................................................................................1455 Chapter 18 Boundary Scan Interface 18.1 Boundary Scan Interface...............................................................................................................................................1457 Chapter 19 Digital Control (DIGCTL) and On-Chip RAM 19.1 Overview.......................................................................................................................................................................1459 19.2 SRAM Controls............................................................................................................................................................1460 19.3 Miscellaneous Controls.................................................................................................................................................1461 19.4 19.3.1 Performance Monitoring..............................................................................................................................1461 19.3.2 High-Entropy PRN Seed..............................................................................................................................1462 19.3.3 Write-Once Register....................................................................................................................................1462 19.3.4 Microseconds Counter.................................................................................................................................1462 Programmable Registers...............................................................................................................................................1462 19.4.1 DIGCTL Control Register (HW_DIGCTL_CTRL)....................................................................................1465 19.4.2 DIGCTL Status Register (HW_DIGCTL_STATUS)..................................................................................1469 19.4.3 Free-Running HCLK Counter Register (HW_DIGCTL_HCLKCOUNT)..................................................1472 19.4.4 On-Chip RAM Control Register (HW_DIGCTL_RAMCTRL)..................................................................1473 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 43 Section number Title Page 19.4.5 EMI Status Register (HW_DIGCTL_EMI_STATUS)................................................................................1474 19.4.6 On-Chip Memories Read Margin Register (HW_DIGCTL_READ_MARGIN)........................................1475 19.4.7 Software Write-Once Register (HW_DIGCTL_WRITEONCE).................................................................1476 19.4.8 BIST Control Register (HW_DIGCTL_BIST_CTL)..................................................................................1476 19.4.9 DIGCTL Status Register (HW_DIGCTL_BIST_STATUS).......................................................................1479 19.4.10 Entropy Register (HW_DIGCTL_ENTROPY)...........................................................................................1483 19.4.11 Entropy Latched Register (HW_DIGCTL_ENTROPY_LATCHED)........................................................1484 19.4.12 Digital Control Microseconds Counter Register (HW_DIGCTL_MICROSECONDS).............................1484 19.4.13 Digital Control Debug Read Test Register (HW_DIGCTL_DBGRD).......................................................1485 19.4.14 Digital Control Debug Register (HW_DIGCTL_DBG)..............................................................................1485 19.4.15 USB LOOP BACK (HW_DIGCTL_USB_LOOPBACK)..........................................................................1486 19.4.16 SRAM Status Register 0 (HW_DIGCTL_OCRAM_STATUS0)...............................................................1488 19.4.17 SRAM Status Register 1 (HW_DIGCTL_OCRAM_STATUS1)...............................................................1489 19.4.18 SRAM Status Register 2 (HW_DIGCTL_OCRAM_STATUS2)...............................................................1489 19.4.19 SRAM Status Register 3 (HW_DIGCTL_OCRAM_STATUS3)...............................................................1490 19.4.20 SRAM Status Register 4 (HW_DIGCTL_OCRAM_STATUS4)...............................................................1491 19.4.21 SRAM Status Register 5 (HW_DIGCTL_OCRAM_STATUS5)...............................................................1491 19.4.22 SRAM Status Register 6 (HW_DIGCTL_OCRAM_STATUS6)...............................................................1492 19.4.23 SRAM Status Register 7 (HW_DIGCTL_OCRAM_STATUS7)...............................................................1493 19.4.24 SRAM Status Register 8 (HW_DIGCTL_OCRAM_STATUS8)...............................................................1493 19.4.25 SRAM Status Register 9 (HW_DIGCTL_OCRAM_STATUS9)...............................................................1494 19.4.26 SRAM Status Register 10 (HW_DIGCTL_OCRAM_STATUS10)...........................................................1495 19.4.27 SRAM Status Register 11 (HW_DIGCTL_OCRAM_STATUS11)...........................................................1496 19.4.28 SRAM Status Register 12 (HW_DIGCTL_OCRAM_STATUS12)...........................................................1496 19.4.29 SRAM Status Register 13 (HW_DIGCTL_OCRAM_STATUS13)...........................................................1498 19.4.30 Digital Control Scratch Register 0 (HW_DIGCTL_SCRATCH0)..............................................................1499 19.4.31 Digital Control Scratch Register 1 (HW_DIGCTL_SCRATCH1)..............................................................1499 19.4.32 Digital Control ARM Cache Register (HW_DIGCTL_ARMCACHE)......................................................1500 19.4.33 Debug Trap Control and Status for AHB Layer 0 and 3 (HW_DIGCTL_DEBUG_TRAP).......................1501 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 44 Freescale Semiconductor, Inc. Section number 19.4.34 Title Page Debug Trap Range Low Address for AHB Layer 0 (HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW).................................................................................1503 19.4.35 Debug Trap Range High Address for AHB Layer 0 (HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH)................................................................................1504 19.4.36 Debug Trap Range Low Address for AHB Layer 3 (HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW).................................................................................1504 19.4.37 Debug Trap Range High Address for AHB Layer 3 (HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH)................................................................................1505 19.4.38 Freescale Copyright Identifier Register (HW_DIGCTL_FSL)...................................................................1505 19.4.39 Digital Control Chip Revision Register (HW_DIGCTL_CHIPID).............................................................1506 19.4.40 AHB Statistics Control Register (HW_DIGCTL_AHB_STATS_SELECT)..............................................1507 19.4.41 AHB Layer 1 Transfer Count Register (HW_DIGCTL_L1_AHB_ACTIVE_CYCLES)..........................1508 19.4.42 AHB Layer 1 Performance Metric for Stalled Bus Cycles Register (HW_DIGCTL_L1_AHB_DATA_STALLED)..........................................................................................1508 19.4.43 AHB Layer 1 Performance Metric for Valid Bus Cycles Register (HW_DIGCTL_L1_AHB_DATA_CYCLES)............................................................................................1509 19.4.44 AHB Layer 2 Transfer Count Register (HW_DIGCTL_L2_AHB_ACTIVE_CYCLES)..........................1510 19.4.45 AHB Layer 2 Performance Metric for Stalled Bus Cycles Register (HW_DIGCTL_L2_AHB_DATA_STALLED)..........................................................................................1510 19.4.46 AHB Layer 2 Performance Metric for Valid Bus Cycles Register (HW_DIGCTL_L2_AHB_DATA_CYCLES)............................................................................................1511 19.4.47 AHB Layer 3 Transfer Count Register (HW_DIGCTL_L3_AHB_ACTIVE_CYCLES)..........................1512 19.4.48 AHB Layer 3 Performance Metric for Stalled Bus Cycles Register (HW_DIGCTL_L3_AHB_DATA_STALLED)..........................................................................................1512 19.4.49 AHB Layer 3 Performance Metric for Valid Bus Cycles Register (HW_DIGCTL_L3_AHB_DATA_CYCLES)............................................................................................1513 19.4.50 Default First Level Page Table Movable PTE Locator 0 (HW_DIGCTL_MPTE0_LOC).........................1513 19.4.51 Default First-Level Page Table Movable PTE Locator 1 (HW_DIGCTL_MPTE1_LOC).........................1514 19.4.52 Default First-Level Page Table Movable PTE Locator 2 (HW_DIGCTL_MPTE2_LOC).........................1515 19.4.53 Default First-Level Page Table Movable PTE Locator 3 (HW_DIGCTL_MPTE3_LOC).........................1516 19.4.54 Default First-Level Page Table Movable PTE Locator 4 (HW_DIGCTL_MPTE4_LOC).........................1517 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 45 Section number Title Page 19.4.55 Default First-Level Page Table Movable PTE Locator 5 (HW_DIGCTL_MPTE5_LOC).........................1518 19.4.56 Default First-Level Page Table Movable PTE Locator 6 (HW_DIGCTL_MPTE6_LOC).........................1519 19.4.57 Default First-Level Page Table Movable PTE Locator 7 (HW_DIGCTL_MPTE7_LOC).........................1520 19.4.58 Default First-Level Page Table Movable PTE Locator 8 (HW_DIGCTL_MPTE8_LOC).........................1521 19.4.59 Default First-Level Page Table Movable PTE Locator 9 (HW_DIGCTL_MPTE9_LOC).........................1522 19.4.60 Default First-Level Page Table Movable PTE Locator 10 (HW_DIGCTL_MPTE10_LOC).....................1522 19.4.61 Default First-Level Page Table Movable PTE Locator 11 (HW_DIGCTL_MPTE11_LOC).....................1523 19.4.62 Default First-Level Page Table Movable PTE Locator 12 (HW_DIGCTL_MPTE12_LOC).....................1524 19.4.63 Default First-Level Page Table Movable PTE Locator 13 (HW_DIGCTL_MPTE13_LOC).....................1525 19.4.64 Default First-Level Page Table Movable PTE Locator 14 (HW_DIGCTL_MPTE14_LOC).....................1526 19.4.65 Default First-Level Page Table Movable PTE Locator 15 (HW_DIGCTL_MPTE15_LOC).....................1527 Chapter 20 On-Chip OTP (OCOTP) Controller 20.1 OCOTP Overview.........................................................................................................................................................1529 20.2 Operation.......................................................................................................................................................................1530 20.2.1 Software Read Sequence..............................................................................................................................1533 20.2.2 Software Write Sequence.............................................................................................................................1534 20.2.3 Write Postamble...........................................................................................................................................1535 20.2.4 Shadow Registers and Hardware Capability Bus........................................................................................1536 20.3 Behavior During Reset..................................................................................................................................................1537 20.4 OCOTP Memory Map/Register Definition..................................................................................................................1537 20.4.1 OTP Controller Control Register (HW_OCOTP_CTRL)...........................................................................1539 20.4.2 OTP Controller Write Data Register (HW_OCOTP_DATA).....................................................................1541 20.4.3 Value of OTP Bank0 Word0 (Customer) (HW_OCOTP_CUST0).............................................................1542 20.4.4 Value of OTP Bank0 Word1 (Customer) (HW_OCOTP_CUST1).............................................................1542 20.4.5 Value of OTP Bank0 Word2 (Customer) (HW_OCOTP_CUST2).............................................................1543 20.4.6 Value of OTP Bank0 Word3 (Customer) (HW_OCOTP_CUST3).............................................................1543 20.4.7 Value of OTP Bank0 Word4 (Crypto Key) (HW_OCOTP_CRYPTO0)....................................................1544 20.4.8 Value of OTP Bank0 Word5 (Crypto Key) (HW_OCOTP_CRYPTO1)....................................................1544 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 46 Freescale Semiconductor, Inc. Section number Title Page 20.4.9 Value of OTP Bank0 Word6 (Crypto Key) (HW_OCOTP_CRYPTO2)....................................................1545 20.4.10 Value of OTP Bank0 Word7 (Crypto Key) (HW_OCOTP_CRYPTO3)....................................................1546 20.4.11 HW Capability Shadow Register 0 (HW_OCOTP_HWCAP0)..................................................................1546 20.4.12 HW Capability Shadow Register 1 (HW_OCOTP_HWCAP1)..................................................................1547 20.4.13 HW Capability Shadow Register 2 (HW_OCOTP_HWCAP2)..................................................................1547 20.4.14 HW Capability Shadow Register 3 (HW_OCOTP_HWCAP3)..................................................................1547 20.4.15 HW Capability Shadow Register 4 (HW_OCOTP_HWCAP4)..................................................................1548 20.4.16 HW Capability Shadow Register 5 (HW_OCOTP_HWCAP5)..................................................................1548 20.4.17 SW Capability Shadow Register (HW_OCOTP_SWCAP).........................................................................1549 20.4.18 Customer Capability Shadow Register (HW_OCOTP_CUSTCAP)...........................................................1549 20.4.19 LOCK Shadow Register OTP Bank 2 Word 0 (HW_OCOTP_LOCK)......................................................1551 20.4.20 Value of OTP Bank2 Word1 (Freescale OPS0) (HW_OCOTP_OPS0)......................................................1555 20.4.21 Value of OTP Bank2 Word2 (Freescale OPS1) (HW_OCOTP_OPS1)......................................................1555 20.4.22 Value of OTP Bank2 Word3 (Freescale OPS2) (HW_OCOTP_OPS2)......................................................1556 20.4.23 Value of OTP Bank2 Word4 (Freescale OPS3) (HW_OCOTP_OPS3)......................................................1556 20.4.24 Value of OTP Bank2 Word5 Freescale OPS4 (HW_OCOTP_OPS4)........................................................1557 20.4.25 Value of OTP Bank2 Word6 Freescale OPS5 (HW_OCOTP_OPS5)........................................................1557 20.4.26 Value of OTP Bank2 Word7 Freescale OPS6 (HW_OCOTP_OPS6)........................................................1558 20.4.27 Shadow Register for OTP Bank3 Word0 (ROM Use 0) (HW_OCOTP_ROM0).......................................1558 20.4.28 Shadow Register for OTP Bank3 Word1 (ROM Use 1) (HW_OCOTP_ROM1).......................................1561 20.4.29 Shadow Register for OTP Bank3 Word2 (ROM Use 2) (HW_OCOTP_ROM2).......................................1564 20.4.30 Shadow Register for OTP Bank3 Word3 (ROM Use 3) (HW_OCOTP_ROM3).......................................1564 20.4.31 Shadow Register for OTP Bank3 Word4 (ROM Use 4) (HW_OCOTP_ROM4).......................................1565 20.4.32 Shadow Register for OTP Bank3 Word5 (ROM Use 5) (HW_OCOTP_ROM5).......................................1567 20.4.33 Shadow Register for OTP Bank3 Word6 (ROM Use 6) (HW_OCOTP_ROM6).......................................1567 20.4.34 Shadow Register for OTP Bank3 Word7 (ROM Use 7) (HW_OCOTP_ROM7).......................................1568 20.4.35 Shadow Register for OTP Bank4 Word0 (Data Use 0) (HW_OCOTP_SRK0)..........................................1570 20.4.36 Shadow Register for OTP Bank4 Word1 (Data Use 1) (HW_OCOTP_SRK1)..........................................1571 20.4.37 Shadow Register for OTP Bank4 Word2 (Data Use 2) (HW_OCOTP_SRK2)..........................................1571 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 47 Section number Title Page 20.4.38 Shadow Register for OTP Bank4 Word3 (Data Use 3) (HW_OCOTP_SRK3)..........................................1572 20.4.39 Shadow Register for OTP Bank4 Word4 (Data Use 4) (HW_OCOTP_SRK4)..........................................1572 20.4.40 Shadow Register for OTP Bank4 Word5 (Data Use 5) (HW_OCOTP_SRK5)..........................................1573 20.4.41 Shadow Register for OTP Bank4 Word6 (Data Use 6) (HW_OCOTP_SRK6)..........................................1573 20.4.42 Shadow Register for OTP Bank4 Word7 (Data Use 7) (HW_OCOTP_SRK7)..........................................1574 20.4.43 OTP Controller Version Register (HW_OCOTP_VERSION)....................................................................1574 Chapter 21 Performance Monitor (PERFMON) 21.1 Overview.......................................................................................................................................................................1575 21.2 Operation.......................................................................................................................................................................1576 21.3 Programmable Registers...............................................................................................................................................1577 21.3.1 PerfMon Control Register (HW_PERFMON_CTRL)................................................................................1578 21.3.2 PerfMon Master Enable Register (HW_PERFMON_MASTER_EN)........................................................1580 21.3.3 PerfMon Trap Range Low Address Register (HW_PERFMON_TRAP_ADDR_LOW)...........................1582 21.3.4 PerfMon Trap Range High Address Register (HW_PERFMON_TRAP_ADDR_HIGH).........................1582 21.3.5 PerfMon Latency Threshold Register (HW_PERFMON_LAT_THRESHOLD).......................................1583 21.3.6 PerfMon AXI Active Cycle Count Register (HW_PERFMON_ACTIVE_CYCLE).................................1583 21.3.7 PerfMon Transfer Count Register (HW_PERFMON_TRANSFER_COUNT)..........................................1584 21.3.8 PerfMon Total Latency Count Register (HW_PERFMON_TOTAL_LATENCY)....................................1584 21.3.9 PerfMon Total Data Count Register (HW_PERFMON_DATA_COUNT)................................................1585 21.3.10 PerfMon Maximum Latency Register (HW_PERFMON_MAX_LATENCY)..........................................1585 21.3.11 PerfMon Debug Register (HW_PERFMON_DEBUG)..............................................................................1586 21.3.12 PerfMon Version Register (HW_PERFMON_VERSION).........................................................................1587 Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits 22.1 RTC Overview..............................................................................................................................................................1589 22.2 Programming and Enabling the RTC Clock.................................................................................................................1592 22.3 RTC Persistent Register Copy Control.........................................................................................................................1593 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 48 Freescale Semiconductor, Inc. Section number 22.4 Title Page Real-Time Clock Function............................................................................................................................................1594 22.4.1 Behavior During Reset.................................................................................................................................1595 22.5 Millisecond Resolution Timing Function.....................................................................................................................1595 22.6 Alarm Clock Function...................................................................................................................................................1595 22.7 Watchdog Reset Function.............................................................................................................................................1596 22.8 Programmable Registers...............................................................................................................................................1596 22.8.1 Real-Time Clock Control Register (HW_RTC_CTRL)..............................................................................1597 22.8.2 Real-Time Clock Status Register (HW_RTC_STAT).................................................................................1599 22.8.3 Real-Time Clock Milliseconds Counter (HW_RTC_MILLISECONDS)...................................................1601 22.8.4 Real-Time Clock Seconds Counter (HW_RTC_SECONDS).....................................................................1602 22.8.5 Real-Time Clock Alarm Register (HW_RTC_ALARM)............................................................................1603 22.8.6 Watchdog Timer Register (HW_RTC_WATCHDOG)...............................................................................1604 22.8.7 Persistent State Register 0 (HW_RTC_PERSISTENT0)............................................................................1604 22.8.8 Persistent State Register 1 (HW_RTC_PERSISTENT1)............................................................................1607 22.8.9 Persistent State Register 2 (HW_RTC_PERSISTENT2)............................................................................1608 22.8.10 Persistent State Register 3 (HW_RTC_PERSISTENT3)............................................................................1608 22.8.11 Persistent State Register 4 (HW_RTC_PERSISTENT4)............................................................................1609 22.8.12 Persistent State Register 5 (HW_RTC_PERSISTENT5)............................................................................1610 22.8.13 Real-Time Clock Debug Register (HW_RTC_DEBUG)............................................................................1610 22.8.14 Real-Time Clock Version Register (HW_RTC_VERSION).......................................................................1612 Chapter 23 Timers and Rotary Decoder (TIMROT) 23.1 Timers and Rotary Decoder (TIMROT) Overview......................................................................................................1615 23.2 Timer.............................................................................................................................................................................1616 23.2.1 Fixed count mode.........................................................................................................................................1616 23.2.2 Match count mode........................................................................................................................................1618 23.2.3 Using External Signals as Inputs.................................................................................................................1620 23.2.4 Timer 3 and Duty Cycle Mode....................................................................................................................1620 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 49 Section number 23.3 Page Rotary Decoder.............................................................................................................................................................1622 23.3.1 23.4 Title Behavior During Reset.................................................................................................................................1625 Programmable Registers...............................................................................................................................................1625 23.4.1 Rotary Decoder Control Register (HW_TIMROT_ROTCTRL).................................................................1626 23.4.2 Rotary Decoder Up/Down Counter Register (HW_TIMROT_ROTCOUNT)............................................1629 23.4.3 Timer 0 Control and Status Register (HW_TIMROT_TIMCTRL0)...........................................................1630 23.4.4 Timer 0 Runing Count Register (HW_TIMROT_RUNNING_COUNT0).................................................1632 23.4.5 Timer 0 Fixed Count Register (HW_TIMROT_FIXED_COUNT0)..........................................................1632 23.4.6 Timer 0 Match Count Register (HW_TIMROT_MATCH_COUNT0).......................................................1633 23.4.7 Timer 1 Control and Status Register (HW_TIMROT_TIMCTRL1)...........................................................1633 23.4.8 Timer 1 Runing Count Register (HW_TIMROT_RUNNING_COUNT1).................................................1635 23.4.9 Timer 1 Fixed Count Register (HW_TIMROT_FIXED_COUNT1)..........................................................1636 23.4.10 Timer 1 Match Count Register (HW_TIMROT_MATCH_COUNT1).......................................................1636 23.4.11 Timer 2 Control and Status Register (HW_TIMROT_TIMCTRL2)...........................................................1637 23.4.12 Timer 2 Runing Count Register (HW_TIMROT_RUNNING_COUNT2).................................................1639 23.4.13 Timer 2 Fixed Count Register (HW_TIMROT_FIXED_COUNT2)..........................................................1639 23.4.14 Timer 2 Match Count Register (HW_TIMROT_MATCH_COUNT2).......................................................1640 23.4.15 Timer 3 Control and Status Register (HW_TIMROT_TIMCTRL3)...........................................................1640 23.4.16 Timer 3 Running Count Register (HW_TIMROT_RUNNING_COUNT3)...............................................1643 23.4.17 Timer 3 Count Register (HW_TIMROT_FIXED_COUNT3).....................................................................1644 23.4.18 Timer 3 Match Count Register (HW_TIMROT_MATCH_COUNT3).......................................................1644 23.4.19 TIMROT Version Register (HW_TIMROT_VERSION)...........................................................................1645 Chapter 24 Debug UART (DUART) 24.1 Debug UART Overview...............................................................................................................................................1647 24.2 Operation.......................................................................................................................................................................1649 24.2.1 Fractional Baud Rate Divider......................................................................................................................1649 24.2.2 UART Character Frame...............................................................................................................................1649 24.2.3 Data Transmission or Reception..................................................................................................................1650 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 50 Freescale Semiconductor, Inc. Section number 24.3 Title Page 24.2.4 Error Bits......................................................................................................................................................1651 24.2.5 Overrun Bit..................................................................................................................................................1651 24.2.6 Disabling the FIFOs.....................................................................................................................................1651 Programmable Registers...............................................................................................................................................1652 24.3.1 UART Data Register (HW_UARTDBG_DR).............................................................................................1653 24.3.2 UART Receive Status Register (Read) / Error Clear Register (Write) (HW_UARTDBG_ECR)..............1654 24.3.3 UART Flag Register (HW_UARTDBG_FR)..............................................................................................1655 24.3.4 UART IrDA Low-Power Counter Register (HW_UARTDBG_ILPR).......................................................1656 24.3.5 UART Integer Baud Rate Divisor Register (HW_UARTDBG_IBRD)......................................................1657 24.3.6 UART Fractional Baud Rate Divisor Register (HW_UARTDBG_FBRD)................................................1657 24.3.7 UART Line Control Register, HIGH Byte (HW_UARTDBG_H)..............................................................1658 24.3.8 UART Control Register (HW_UARTDBG_CR)........................................................................................1659 24.3.9 UART Interrupt FIFO Level Select Register (HW_UARTDBG_IFLS).....................................................1661 24.3.10 UART Interrupt Mask Set/Clear Register (HW_UARTDBG_IMSC)........................................................1662 24.3.11 UART Raw Interrupt Status Register (HW_UARTDBG_RIS)..................................................................1664 24.3.12 UART Masked Interrupt Status Register (HW_UARTDBG_MIS)............................................................1666 24.3.13 UART Interrupt Clear Register (HW_UARTDBG_ICR)...........................................................................1668 24.3.14 UART DMA Control Register (HW_UARTDBG_DMACR).....................................................................1669 Chapter 25 Controller Area Network (FlexCAN) 25.1 FlexCAN Introduction..................................................................................................................................................1671 25.2 Overview.......................................................................................................................................................................1672 25.3 25.2.1 Features........................................................................................................................................................1673 25.2.2 Modes of Operation.....................................................................................................................................1674 Message Buffer Structure.............................................................................................................................................1675 25.3.1 25.4 Rx FIFO Structure........................................................................................................................................1678 Functional Description..................................................................................................................................................1681 25.4.1 Overview......................................................................................................................................................1681 25.4.2 Transmit Process..........................................................................................................................................1681 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 51 Section number Title 25.4.3 Arbitration Process.......................................................................................................................................1682 25.4.4 Receive Process............................................................................................................................................1683 25.4.5 Matching Process.........................................................................................................................................1685 25.4.6 Data Coherence............................................................................................................................................1687 25.4.6.1 Message Buffer Deactivation.......................................................................................................................1688 25.4.8 Message Buffer Lock Mechanism...............................................................................................................1689 25.4.9 Rx FIFO.......................................................................................................................................................1690 25.4.10 CAN Protocol Related Features...................................................................................................................1691 25.4.10.1 Remote Frames........................................................................................................................1691 25.4.10.2 Overload Frames......................................................................................................................1692 25.4.10.3 Time Stamp..............................................................................................................................1692 25.4.10.4 Protocol Timing.......................................................................................................................1692 25.4.10.5 Arbitration and Matching Timing............................................................................................1695 Modes of Operation Details.........................................................................................................................1696 25.4.11.1 Freeze Mode.............................................................................................................................1696 25.4.11.2 Module Disable Mode .............................................................................................................1697 25.4.11.3 Stop Mode................................................................................................................................1697 25.4.11.4 Interrupts..................................................................................................................................1698 Initialization/Application Information..........................................................................................................................1699 25.5.1 25.6 Transmission Abort Mechanism..............................................................................................1687 25.4.7 25.4.11 25.5 Page FlexCAN Initialization Sequence................................................................................................................1699 Programmable Registers...............................................................................................................................................1701 25.6.1 Module Configuration Register (HW_CAN_MCR)....................................................................................1702 25.6.2 Control Register (HW_CAN_CTRL)..........................................................................................................1704 25.6.3 Free Running Timer (HW_CAN_TIMER)..................................................................................................1707 25.6.4 Rx Global Mask (HW_CAN_RXGMASK)................................................................................................1707 25.6.5 Rx 14 Mask (HW_CAN_RX14MASK)......................................................................................................1708 25.6.6 Rx 15 Mask (HW_CAN_RX15MASK)......................................................................................................1709 25.6.7 Error Counter Register (HW_CAN_ECR)..................................................................................................1709 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 52 Freescale Semiconductor, Inc. Section number Title Page 25.6.8 Error and Status Register (HW_CAN_ESR)...............................................................................................1711 25.6.9 Interrupt Masks 2 Register (HW_CAN_IMASK2).....................................................................................1713 25.6.10 Interrupt Masks 1 Register (HW_CAN_IMASK1).....................................................................................1714 25.6.11 Interrupt Flags 2 Register (HW_CAN_IFLAG2)........................................................................................1714 25.6.12 Interrupt Flags 1 Register (HW_CAN_IFLAG1)........................................................................................1715 25.6.13 Glitch Filter Width Register (HW_CAN_GFWR)......................................................................................1715 25.6.14 CAN Messager Buffer Registers (HW_CAN_MBn)...................................................................................1716 25.6.15 Rx Individual Mask Registers (HW_CAN_RXIMRn)................................................................................1716 Chapter 26 Ethernet Controller (ENET) 26.1 26.2 Overview.......................................................................................................................................................................1719 26.1.1 Block Diagram.............................................................................................................................................1719 26.1.2 Features........................................................................................................................................................1720 Unified DMA Block Guide...........................................................................................................................................1720 26.2.1 26.2.2 Introduction..................................................................................................................................................1721 26.2.1.1 Overview..................................................................................................................................1721 26.2.1.2 Features....................................................................................................................................1722 26.2.1.3 Modes of Operation.................................................................................................................1722 26.2.1.3.1 Legacy Mode......................................................................................................1722 26.2.1.3.2 Enhanced Mode..................................................................................................1722 Functional Description.................................................................................................................................1722 26.2.2.1 Legacy Buffer Descriptor Models............................................................................................1723 26.2.2.1.1 Legacy FEC Receive Buffer Descriptor.............................................................1723 26.2.2.1.1.1 Bit-15 E......................................................................................1723 26.2.2.1.1.2 Bit-14 RO1.................................................................................1723 26.2.2.1.1.3 Bit-13 W.....................................................................................1724 26.2.2.1.1.4 Bit-12 RO2.................................................................................1724 26.2.2.1.1.5 Bit-11 L......................................................................................1724 26.2.2.1.1.6 Bit-10 and Bit 9 --.....................................................................1724 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 53 Section number Title Page 26.2.2.1.1.7 Bit-8 M.......................................................................................1724 26.2.2.1.1.8 Bit-7 BC......................................................................................1724 26.2.2.1.1.9 Bit-6 MC.....................................................................................1724 26.2.2.1.1.10 Bit-5 LG......................................................................................1724 26.2.2.1.1.11 Bit-4 NO.....................................................................................1725 26.2.2.1.1.12 Bit-3 --.......................................................................................1725 26.2.2.1.1.13 Bit-2 CR......................................................................................1725 26.2.2.1.1.14 Bit-1 OV.....................................................................................1725 26.2.2.1.1.15 Bit-0 TR......................................................................................1725 26.2.2.1.1.16 Data Length................................................................................1725 26.2.2.1.1.17 RX Data Buffer Pointer - A[31:16]............................................1725 26.2.2.1.1.18 RX Data Buffer Pointer - A[15:0]..............................................1725 26.2.2.1.2 Legacy FEC Transmit Buffer Descriptor............................................................1726 26.2.2.1.2.1 Bit-15 R......................................................................................1726 26.2.2.1.2.2 Bit-14 TO1..................................................................................1726 26.2.2.1.2.3 Bit-13 W.....................................................................................1726 26.2.2.1.2.4 Bit-12 TO2..................................................................................1726 26.2.2.1.2.5 Bit-11 L......................................................................................1726 26.2.2.1.2.6 Bit-10 TC....................................................................................1727 26.2.2.1.2.7 Bit-9 ABC...................................................................................1727 26.2.2.1.2.8 Bit 8-0 --....................................................................................1727 26.2.2.1.2.9 Data Length................................................................................1727 26.2.2.1.2.10 TX Data Buffer Pointer A[31:16]...............................................1727 26.2.2.1.2.11 TX Data Buffer Pointer A[15:0].................................................1727 26.2.2.2 Enhanced Buffer Descriptor Models........................................................................................1727 26.2.2.2.1 Enhanced uDMA Receive Buffer Descriptor.....................................................1727 26.2.2.2.1.1 Offset + 0 Bit 15:0......................................................................1728 26.2.2.2.1.2 Data Length................................................................................1728 26.2.2.2.1.3 RX Data Buffer Pointer A[31:16]..............................................1728 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 54 Freescale Semiconductor, Inc. Section number Title Page 26.2.2.2.1.4 RX Data Buffer Pointer A[15:0]................................................1728 26.2.2.2.1.5 Offset + 8 Bit 15 ME..................................................................1728 26.2.2.2.1.6 Offset + 8 Bit 14 --....................................................................1729 26.2.2.2.1.7 Offset + 8 Bit 10 PE...................................................................1729 26.2.2.2.1.8 Offset + 8 - Bit 9 CE..................................................................1729 26.2.2.2.1.9 Offset + 8 - Bit 8 UC.................................................................1729 26.2.2.2.1.10 Offset + 8 - Bit 7 INT................................................................1729 26.2.2.2.1.11 Offset + A - Bit 5 ICE................................................................1729 26.2.2.2.1.12 Offset + A - Bit 4 PCR...............................................................1729 26.2.2.2.1.13 Offset + A - Bit 3 --..................................................................1730 26.2.2.2.1.14 Offset + A - Bit 2 VLAN...........................................................1730 26.2.2.2.1.15 Offset + A - Bit 1 IPV6..............................................................1730 26.2.2.2.1.16 Offset + A - Bit 0 FRAG...........................................................1730 26.2.2.2.1.17 Offset + C - Bit [15:11] Header Length.....................................1730 26.2.2.2.1.18 Offset + C - Bit [7:0] Protocol Type..........................................1730 26.2.2.2.1.19 Offset + E - Bit [15:0] Payload Checksum................................1731 26.2.2.2.1.20 Offset + 0x10 - Bit 15 BDU.......................................................1731 26.2.2.2.1.21 1588 Timestamp [31:0]..............................................................1731 26.2.2.2.2 Enhanced uDMA Transmit Buffer Descriptor....................................................1731 26.2.2.2.2.1 Offset + 0 - Bit 15:0....................................................................1731 26.2.2.2.2.2 Offset + 2 - Data Length.............................................................1732 26.2.2.2.2.3 Offset + 4 and Offset + 6 - TX Data Buffer Pointer...................1732 26.2.2.2.2.4 Offset + 8 Bit 15 "-"...................................................................1732 26.2.2.2.2.5 Offset + 8 Bit 14 "INT"..............................................................1732 26.2.2.2.2.6 Offset + 8 Bit 13 "TS"................................................................1732 26.2.2.2.2.7 Offset + 8 Bit 12 "PINS"............................................................1732 26.2.2.2.2.8 Offset + 8 Bit 11 "IINS".............................................................1732 26.2.2.2.2.9 Offset + A Bit 15 "TXE"............................................................1733 26.2.2.2.2.10 Offset + A Bit 14 "-"..................................................................1733 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 55 Section number Title Page 26.2.2.2.2.11 Offset + A Bit 13 "UE"..............................................................1733 26.2.2.2.2.12 Offset + A Bit 12 "EE"...............................................................1733 26.2.2.2.2.13 Offset + A Bit 11 "FE"...............................................................1733 26.2.2.2.2.14 Offset + A Bit 10 "LCE"............................................................1733 26.2.2.2.2.15 Offset + A Bit 9 "OE"................................................................1733 26.2.2.2.2.16 Offset + A Bit 8 "TSE"...............................................................1734 26.2.2.2.2.17 Offset + 0x10 - Bit 15 "BDU"....................................................1734 26.2.2.2.2.18 1588 Timestamp [31:0]..............................................................1734 26.3 Ethernet ENET-MAC Core...........................................................................................................................................1734 26.3.1 Introduction..................................................................................................................................................1734 26.3.2 10 100Mbps Ethernet ENET-MAC Core Features......................................................................................1736 26.3.2.1 Ethernet MAC Features...........................................................................................................1736 26.3.2.2 IP Protocol Performance Optimization Features.....................................................................1737 26.3.2.3 IEEE 1588 Functions...............................................................................................................1738 26.3.3 ENET-MAC Core Block Diagram...............................................................................................................1738 26.3.4 Ethernet MAC Frame Formats.....................................................................................................................1739 26.3.5 26.3.4.1 Overview..................................................................................................................................1739 26.3.4.2 Pause Frames............................................................................................................................1741 26.3.4.3 Magic Packets..........................................................................................................................1742 IP and Higher Layers Frame Format............................................................................................................1742 26.3.5.1 Definitions................................................................................................................................1742 26.3.5.2 Ethernet Types.........................................................................................................................1742 26.3.5.3 IPv4 Datagram Format.............................................................................................................1743 26.3.5.4 IPv6 Datagram Format.............................................................................................................1744 26.3.5.5 ICMP Datagram Format...........................................................................................................1745 26.3.5.6 UDP Datagram Format............................................................................................................1745 26.3.5.7 TCP Datagram Format.............................................................................................................1746 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 56 Freescale Semiconductor, Inc. Section number 26.3.6 Title IEEE 1588 Message Formats.......................................................................................................................1747 26.3.6.1 26.3.6.2 26.3.7 Transport Encapsulation..........................................................................................................1747 26.3.6.1.1 UDP/IP................................................................................................................1747 26.3.6.1.2 Native Ethernet (PTPv2).....................................................................................1747 PTP Header..............................................................................................................................1748 26.3.6.2.1 PTPv1 Header.....................................................................................................1748 26.3.6.2.2 PTPv2 Header.....................................................................................................1749 MAC Receive...............................................................................................................................................1750 26.3.7.1 Overview..................................................................................................................................1750 26.3.7.2 Collision Detection in Half Duplex Mode...............................................................................1751 26.3.7.3 Preamble Processing................................................................................................................1752 26.3.7.4 MAC Address Check...............................................................................................................1752 26.3.7.5 26.3.8 Page 26.3.7.4.1 Overview.............................................................................................................1752 26.3.7.4.2 Unicast Address Check.......................................................................................1752 26.3.7.4.3 Multicast and Unicast Address Resolution.........................................................1753 26.3.7.4.4 Broadcast Address Reject...................................................................................1753 26.3.7.4.5 Miss-Bit Implementation....................................................................................1754 Frame Length Type Verification..............................................................................................1754 26.3.7.5.1 Payload Length Check........................................................................................1754 26.3.7.5.2 Frame Length Check...........................................................................................1755 26.3.7.6 VLAN Frames Processing.......................................................................................................1755 26.3.7.7 Pause Frame Termination........................................................................................................1755 26.3.7.8 CRC Check..............................................................................................................................1755 26.3.7.9 Frame Padding Remove...........................................................................................................1756 MAC Transmit.............................................................................................................................................1756 26.3.8.1 Overview..................................................................................................................................1756 26.3.8.2 Frame Payload Padding...........................................................................................................1757 26.3.8.3 MAC Address Insertion...........................................................................................................1758 26.3.8.4 CRC-32 generation..................................................................................................................1758 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 57 Section number 26.3.9 26.3.10 26.3.11 Title Page 26.3.8.5 Inter Packet Gap.......................................................................................................................1758 26.3.8.6 Collision Detection and Handling - Half Duplex Operation Only...........................................1759 Full Duplex Flow Control Operation...........................................................................................................1760 26.3.9.1 Overview..................................................................................................................................1760 26.3.9.2 Remote Device Congestion......................................................................................................1761 26.3.9.3 Local Device / FIFO Congestion.............................................................................................1761 Magic Packet Detection...............................................................................................................................1763 26.3.10.1 Overview..................................................................................................................................1763 26.3.10.2 Sleep Mode..............................................................................................................................1763 26.3.10.3 Magic Packet Detection...........................................................................................................1763 26.3.10.4 Wakeup....................................................................................................................................1764 IP Accelerator Functions..............................................................................................................................1764 26.3.11.1 Checksum Calculation.............................................................................................................1764 26.3.11.2 Additional Padding Processing................................................................................................1765 26.3.11.3 32-bit Ethernet Payload Alignment..........................................................................................1766 26.3.11.4 Received Frame Discard..........................................................................................................1766 26.3.11.5 IPv4 Fragments........................................................................................................................1767 26.3.11.6 IP Version 6 IPv6 Support.......................................................................................................1768 26.3.11.6.1 Receive Processing.............................................................................................1768 26.3.11.6.2 Transmit Processing............................................................................................1768 26.3.12 26.3.13 Resets and Stop Controls.............................................................................................................................1768 26.3.12.1 Hardware Reset........................................................................................................................1768 26.3.12.2 Soft Reset.................................................................................................................................1769 26.3.12.3 Graceful Stop...........................................................................................................................1769 26.3.12.4 Graceful Transmit Stop (GTS).................................................................................................1769 26.3.12.5 Graceful Receive Stop (GRS)..................................................................................................1770 26.3.12.6 Graceful Stop Interrupt (GRA)................................................................................................1770 IEEE 1588 Functions...................................................................................................................................1771 26.3.13.1 Overview..................................................................................................................................1771 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 58 Freescale Semiconductor, Inc. Section number Title 26.3.13.2 Page Adjustable Timer Module........................................................................................................1771 26.3.13.2.1 Overview.............................................................................................................1771 26.3.13.2.2 Adjustable Timer Implementation......................................................................1772 26.3.14 26.3.15 26.3.13.3 Timer Synchronization for Multi-Port Implementations.........................................................1773 26.3.13.4 Transmit Timestamping...........................................................................................................1774 26.3.13.5 Receive Timestamping.............................................................................................................1774 26.3.13.6 Time Synchronization..............................................................................................................1774 26.3.13.7 Capture/Compare Block...........................................................................................................1775 FIFO Thresholds..........................................................................................................................................1775 26.3.14.1 Overview..................................................................................................................................1775 26.3.14.2 Receive FIFO...........................................................................................................................1775 26.3.14.3 Transmit FIFO..........................................................................................................................1777 Loopback Options........................................................................................................................................1778 26.3.15.1 26.3.16 26.3.17 26.3.18 26.3.19 Overview..................................................................................................................................1778 FIFO Protection............................................................................................................................................1779 26.3.16.1 Transmit FIFO Underflow.......................................................................................................1779 26.3.16.2 Transmit FIFO Overflow.........................................................................................................1780 26.3.16.3 Receive FIFO Overflow...........................................................................................................1780 PHY Management Interface.........................................................................................................................1781 26.3.17.1 Overview..................................................................................................................................1781 26.3.17.2 MDIO Frame Format...............................................................................................................1781 26.3.17.3 MDIO Clock Generation..........................................................................................................1782 26.3.17.4 MDIO Operation......................................................................................................................1782 26.3.17.5 MDIO Buffer Connection........................................................................................................1783 MII Interface................................................................................................................................................1784 26.3.18.1 Transmit...................................................................................................................................1784 26.3.18.2 Transmit with Collision - Half Duplex....................................................................................1784 26.3.18.3 Receive.....................................................................................................................................1785 MII Interface Timing Characteristics...........................................................................................................1785 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 59 Section number 26.4 Title Page Programmable Registers...............................................................................................................................................1787 26.4.1 ENET MAC Interrupt Event Register (HW_ENET_MAC_EIR)................................................................1793 26.4.2 ENET MAC Interrupt Mask Register (HW_ENET_MAC_EIMR)............................................................1794 26.4.3 ENET MAC Receive Descriptor Active Register (HW_ENET_MAC_RDAR).........................................1795 26.4.4 ENET MAC Transmit Descriptor Active Register (HW_ENET_MAC_TDAR).......................................1796 26.4.5 ENET MAC Control Register (HW_ENET_MAC_ECR)..........................................................................1798 26.4.6 ENET MAC MII Management Frame Register (HW_ENET_MAC_MMFR)...........................................1799 26.4.7 ENET MAC MII Speed Control Register (HW_ENET_MAC_MSCR).....................................................1801 26.4.8 ENET MAC MIB Control/Status Register (HW_ENET_MAC_MIBC)....................................................1802 26.4.9 ENET MAC Receive Control Register (HW_ENET_MAC_RCR)............................................................1803 26.4.10 ENET MAC Transmit Control Register (HW_ENET_MAC_TCR)...........................................................1805 26.4.11 ENET MAC Physical Address Lower Register (HW_ENET_MAC_PALR).............................................1806 26.4.12 ENET MAC Physical Address Upper Register (HW_ENET_MAC_PAUR).............................................1807 26.4.13 ENET MAC Opcode/Pause Duration Register (HW_ENET_MAC_OPD)................................................1807 26.4.14 ENET MAC Descriptor Individual Upper Address Register (HW_ENET_MAC_IAUR).........................1807 26.4.15 ENET MAC Descriptor Individual Lower Address Register (HW_ENET_MAC_IALR).........................1808 26.4.16 ENET MAC Descriptor Group Upper Address Register (HW_ENET_MAC_GAUR)..............................1808 26.4.17 ENET MAC Descriptor Group Lower Address Register (HW_ENET_MAC_GALR)..............................1809 26.4.18 ENET MAC Transmit FIFO Watermark and Store and Forward Control Register (HW_ENET_MAC_TFW_SFCR)...............................................................................................................1809 26.4.19 ENET MAC FIFO Receive Bound Register (HW_ENET_MAC_FRBR)..................................................1810 26.4.20 ENET MAC FIFO Receive FIFO Start Register (HW_ENET_MAC_FRSR)............................................1811 26.4.21 ENET MAC Pointer to Receive Descriptor Ring Register (HW_ENET_MAC_ERDSR).........................1812 26.4.22 ENET MAC Pointer to Transmit Descriptor Ring Register (HW_ENET_MAC_ETDSR)........................1813 26.4.23 ENET MAC Maximum Receive Buffer Size Register (HW_ENET_MAC_EMRBR)..............................1814 26.4.24 ENET MAC Receive FIFO Section Full Threshold Register (HW_ENET_MAC_RX_SECTION_FULL)...............................................................................................1814 26.4.25 ENET MAC Receive FIFO Section Empty Threshold Register (HW_ENET_MAC_RX_SECTION_EMPTY)...........................................................................................1815 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 60 Freescale Semiconductor, Inc. Section number 26.4.26 Title Page ENET MAC Receive FIFO Almost Empty Threshold Register (HW_ENET_MAC_RX_ALMOST_EMPTY)...........................................................................................1815 26.4.27 ENET MAC Receive FIFO Almost Full Thresholdt Register (HW_ENET_MAC_RX_ALMOST_FULL)...............................................................................................1816 26.4.28 ENET MAC Transmit FIFO Section Empty Threshold Register (HW_ENET_MAC_TX_SECTION_EMPTY)...........................................................................................1816 26.4.29 ENET MAC Transmit FIFO Almost Empty Threshold Register (HW_ENET_MAC_TX_ALMOST_EMPTY)............................................................................................1817 26.4.30 ENET MAC Transmit FIFO Almost Full Threshold Register (HW_ENET_MAC_TX_ALMOST_FULL)...............................................................................................1817 26.4.31 ENET MAC Transmit Inter-Packet Gap Register (HW_ENET_MAC_TX_IPG_LENGTH)....................1818 26.4.32 ENET MAC Frame Truncation Length Register (HW_ENET_MAC_TRUNC_FL).................................1818 26.4.33 ENET MAC Accelerator Transmit Function Configuration Register (HW_ENET_MAC_IPACCTXCONF).......................................................................................................1819 26.4.34 ENET MAC Accelerator Receive Function Configuration Register (HW_ENET_MAC_IPACCRXCONF).......................................................................................................1821 26.4.35 ENET MAC RMON Tx packet drop (HW_ENET_MAC_RMON_T_DROP)..........................................1822 26.4.36 ENET MAC RMON Tx packet count (HW_ENET_MAC_RMON_T_PACKETS)..................................1823 26.4.37 ENET MAC RMON Tx Broadcast Packets (HW_ENET_MAC_RMON_T_BC_PKT)............................1823 26.4.38 ENET MAC RMON Tx Multicast Packets (HW_ENET_MAC_RMON_T_MC_PKT)............................1823 26.4.39 ENET MAC RMON Tx Packets w CRC/Align error (HW_ENET_MAC_RMON_T_CRC_ALIGN).....1824 26.4.40 ENET MAC RMON Tx Packets < 64 bytes, good CRC (HW_ENET_MAC_RMON_T_UNDERSIZE).1824 26.4.41 ENET MAC RMON Tx Packets > MAX_FL bytes, good CRC (HW_ENET_MAC_RMON_T_OVERSIZE).............................................................................................1825 26.4.42 ENET MAC RMON Tx Packets < 64 bytes, bad CRC (HW_ENET_MAC_RMON_T_FRAG)..............1825 26.4.43 ENET MAC RMON Tx Packets > MAX_FL bytes, bad CRC (HW_ENET_MAC_RMON_T_JAB)......1825 26.4.44 ENET MAC RMON Tx collision count (HW_ENET_MAC_RMON_T_COL)........................................1826 26.4.45 ENET MAC RMON Tx 64 byte packets (HW_ENET_MAC_RMON_T_P64).........................................1826 26.4.46 ENET MAC RMON Tx 65 to 127 byte packets (HW_ENET_MAC_RMON_T_P65TO127N)...............1827 26.4.47 ENET MAC RMON Tx 128 to 255 byte packets (HW_ENET_MAC_RMON_T_P128TO255N)...........1827 26.4.48 ENET MAC RMON Tx 256 to 511 byte packets (HW_ENET_MAC_RMON_T_P256TO511)..............1827 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 61 Section number Title Page 26.4.49 ENET MAC RMON Tx 512 to 1023 byte packets (HW_ENET_MAC_RMON_T_P512TO1023)..........1828 26.4.50 ENET MAC RMON Tx 1024 to 2047 byte packets (HW_ENET_MAC_RMON_T_P1024TO2047)......1828 26.4.51 ENET MAC RMON Tx packets w > 2048 bytes (HW_ENET_MAC_RMON_T_P_GTE2048)..............1829 26.4.52 ENET MAC RMON Tx Octets (HW_ENET_MAC_RMON_T_OCTETS)..............................................1829 26.4.53 ENET MAC Frames Transmitted count drop (HW_ENET_MAC_IEEE_T_DROP).................................1829 26.4.54 ENET MAC Frames Transmitted OK (HW_ENET_MAC_IEEE_T_FRAME_OK).................................1830 26.4.55 ENET MAC Frames Transmitted with Single Collision (HW_ENET_MAC_IEEE_T_1COL)................1830 26.4.56 ENET MAC Frames Transmitted with Multiple Collisions (HW_ENET_MAC_IEEE_T_MCOL)..........1831 26.4.57 ENET MAC Frames Transmitted after Deferral Delay (HW_ENET_MAC_IEEE_T_DEF).....................1831 26.4.58 ENET MAC Frames Transmitted with Late Collision (HW_ENET_MAC_IEEE_T_LCOL)...................1831 26.4.59 ENET MAC Frames Transmitted with Excessive Collisions (HW_ENET_MAC_IEEE_T_EXCOL)......1832 26.4.60 ENET MAC Frames Transmitted with Tx FIFO Underrun (HW_ENET_MAC_IEEE_T_MACERR).....1832 26.4.61 ENET MAC Frames Transmitted with Carrier Sense Error (HW_ENET_MAC_IEEE_T_CSERR).........1833 26.4.62 ENET MAC Frames Transmitted with SQE Error (HW_ENET_MAC_IEEE_T_SQE)............................1833 26.4.63 ENET MAC Frames Transmitted flow control (HW_ENET_MAC_IEEE_T_FDXFC)............................1834 26.4.64 ENET MAC Frames Transmitted error (HW_ENET_MAC_IEEE_T_OCTETS_OK)..............................1834 26.4.65 ENET MAC RMON Rx packet count (HW_ENET_MAC_RMON_R_PACKETS).................................1835 26.4.66 ENET MAC RMON Rx Broadcast Packets (HW_ENET_MAC_RMON_R_BC_PKT)...........................1835 26.4.67 ENET MAC RMON Rx Multicast Packets (HW_ENET_MAC_RMON_R_MC_PKT)...........................1835 26.4.68 ENET MAC RMON Rx Packets w CRC/Align error (HW_ENET_MAC_RMON_R_CRC_ALIGN).....1836 26.4.69 ENET MAC RMON Rx Packets < 64 bytes, good CRC (HW_ENET_MAC_RMON_R_UNDERSIZE) 1836 26.4.70 ENET MAC RMON Rx Packets > MAX_FL, good CRC (HW_ENET_MAC_RMON_R_OVERSIZE).1837 26.4.71 ENET MAC RMON Rx Packets < 64 bytes, bad CRC (HW_ENET_MAC_RMON_R_FRAG)..............1837 26.4.72 ENET MAC RMON Rx Packets > MAX_FL bytes, bad CRC (HW_ENET_MAC_RMON_R_JAB)......1838 26.4.73 ENET MAC RMON Rx 64 byte packets (HW_ENET_MAC_RMON_R_P64)........................................1838 26.4.74 ENET MAC RMON Rx 65 to 127 byte packets (HW_ENET_MAC_RMON_R_P65TO127)..................1839 26.4.75 ENET MAC RMON Rx 128 to 255 byte packets (HW_ENET_MAC_RMON_R_P128TO255)..............1839 26.4.76 ENET MAC RMON Rx 256 to 511 byte packets (HW_ENET_MAC_RMON_R_P256TO511)..............1840 26.4.77 ENET MAC RMON Rx 512 to 1023 byte packets (HW_ENET_MAC_RMON_R_P512TO1023)..........1840 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 62 Freescale Semiconductor, Inc. Section number Title Page 26.4.78 ENET MAC RMON Rx 1024 to 2047 byte packets (HW_ENET_MAC_RMON_R_P1024TO2047)......1841 26.4.79 ENET MAC RMON Rx packets w > 2048 bytes (HW_ENET_MAC_RMON_R_P_GTE2048)..............1841 26.4.80 ENET MAC RMON Rx Octets (HW_ENET_MAC_RMON_R_OCTETS)..............................................1842 26.4.81 ENET MAC Frames Received count drop (HW_ENET_MAC_IEEE_R_DROP).....................................1842 26.4.82 ENET MAC Frames Received OK (HW_ENET_MAC_IEEE_R_FRAME_OK).....................................1843 26.4.83 ENET MAC Frames Received with CRC Error (HW_ENET_MAC_IEEE_R_CRC)...............................1843 26.4.84 ENET MAC Frames Received with Alignment Error (HW_ENET_MAC_IEEE_R_ALIGN)..................1844 26.4.85 ENET MAC Frames Received overflow (HW_ENET_MAC_IEEE_R_MACERR).................................1844 26.4.86 ENET MAC Frames Received flow control (HW_ENET_MAC_IEEE_R_FDXFC)................................1845 26.4.87 ENET MAC Frames Received error (HW_ENET_MAC_IEEE_R_OCTETS_OK)..................................1845 26.4.88 ENET MAC IEEE1588 Timer Control Register (HW_ENET_MAC_ATIME_CTRL).............................1846 26.4.89 ENET MAC IEEE1588 Timer value Register (HW_ENET_MAC_ATIME).............................................1848 26.4.90 ENET MAC IEEE1588 Offsetvalue for one-shot event generation Register (HW_ENET_MAC_ATIME_EVT_OFFSET)............................................................................................1848 26.4.91 ENET MAC IEEE1588 Timer Period Register (HW_ENET_MAC_ATIME_EVT_PERIOD).................1849 26.4.92 ENET MAC IEEE1588 Correction counter wrap around value Register (HW_ENET_MAC_ATIME_CORR).........................................................................................................1850 26.4.93 ENET MAC IEEE1588 Clock period of the timestamping clock (ts_clk) in nanoseconds and correction increment Register (HW_ENET_MAC_ATIME_INC)..............................................................................1851 26.4.94 ENET MAC IEEE1588 Timestamp of the last Frame Register (HW_ENET_MAC_TS_TIMESTAMP). 1852 26.4.95 ENET MAC Supplemental MAC Address 0 (HW_ENET_MAC_SMAC_0_0)........................................1852 26.4.96 ENET MAC Supplemental MAC Address 0 (HW_ENET_MAC_SMAC_0_1)........................................1853 26.4.97 ENET MAC Supplemental MAC Address 1 (HW_ENET_MAC_SMAC_1_0)........................................1853 26.4.98 ENET MAC Supplemental MAC Address 1 (HW_ENET_MAC_SMAC_1_1)........................................1854 26.4.99 ENET MAC Supplemental MAC Address 2 (HW_ENET_MAC_SMAC_2_0)........................................1854 26.4.100 ENET MAC Supplemental MAC Address 2 (HW_ENET_MAC_SMAC_2_1)........................................1855 26.4.101 ENET MAC Supplemental MAC Address 3 (HW_ENET_MAC_SMAC_3_0)........................................1855 26.4.102 ENET MAC Supplemental MAC Address 3 (HW_ENET_MAC_SMAC_3_1)........................................1856 26.4.103 ENET MAC Compare register 0 (HW_ENET_MAC_COMP_REG_0).....................................................1856 26.4.104 ENET MAC Compare register 1 (HW_ENET_MAC_COMP_REG_1).....................................................1857 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 63 Section number Title Page 26.4.105 ENET MAC Compare register 2 (HW_ENET_MAC_COMP_REG_2).....................................................1857 26.4.106 ENET MAC Compare register 3 (HW_ENET_MAC_COMP_REG_3).....................................................1858 26.4.107 ENET MAC Capture register 0 (HW_ENET_MAC_CAPT_REG_0)........................................................1858 26.4.108 ENET MAC Capture register 1 (HW_ENET_MAC_CAPT_REG_1)........................................................1859 26.4.109 ENET MAC Capture register 2 (HW_ENET_MAC_CAPT_REG_2)........................................................1859 26.4.110 ENET MAC Capture register 3 (HW_ENET_MAC_CAPT_REG_3)........................................................1860 26.4.111 ENET MAC IEEE1588 Interrupt register. (HW_ENET_MAC_CCB_INT)..............................................1860 26.4.112 ENET MAC IEEE1588 Interrupt enable mask register (HW_ENET_MAC_CCB_INT_MASK).............1862 Chapter 27 Inter IC (I2C) 27.1 I2C Overview................................................................................................................................................................1865 27.2 Operation.......................................................................................................................................................................1867 27.2.1 I2C Interrupt Sources...................................................................................................................................1867 27.2.2 I2C Bus Protocol..........................................................................................................................................1868 27.2.3 27.3 27.4 27.2.2.1 Simple Device Transactions.....................................................................................................1870 27.2.2.2 Typical EEPROM Transactions...............................................................................................1871 27.2.2.3 Master Mode Protocol..............................................................................................................1872 27.2.2.4 Clock Generation.....................................................................................................................1873 27.2.2.5 Master Mode Operation...........................................................................................................1873 27.2.2.6 Slave Mode Protocol................................................................................................................1878 Programming Examples...............................................................................................................................1882 27.2.3.1 Five Byte Master Write Using DMA.......................................................................................1882 27.2.3.2 Reading 256 bytes from an EEPROM.....................................................................................1883 Internal Interface Modes...............................................................................................................................................1886 27.3.1 PIO Mode.....................................................................................................................................................1886 27.3.2 PIO Queue Mode.........................................................................................................................................1887 Behavior During Reset..................................................................................................................................................1888 27.4.1 Pinmux Selection During Reset...................................................................................................................1888 27.4.1.1 Correct and Incorrect Reset Examples.....................................................................................1889 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 64 Freescale Semiconductor, Inc. Section number 27.5 Title Page Programmable Registers...............................................................................................................................................1889 27.5.1 I2C Control Register 0 (HW_I2C_CTRL0).................................................................................................1890 27.5.2 I2C Timing Register 0 (HW_I2C_TIMING0).............................................................................................1893 27.5.3 I2C Timing Register 1 (HW_I2C_TIMING1).............................................................................................1894 27.5.4 I2C Timing Register 2 (HW_I2C_TIMING2).............................................................................................1895 27.5.5 I2C Control Register 1 (HW_I2C_CTRL1).................................................................................................1896 27.5.6 I2C Status Register (HW_I2C_STAT)........................................................................................................1900 27.5.7 I2C Queue control reg. (HW_I2C_QUEUECTRL).....................................................................................1905 27.5.8 I2C Queue Status Register. (HW_I2C_QUEUESTAT)..............................................................................1906 27.5.9 I2C Queue command reg (HW_I2C_QUEUECMD)..................................................................................1908 27.5.10 I2C Controller Read Data Register for queue mode only. (HW_I2C_QUEUEDATA)..............................1911 27.5.11 I2C Controller DMA Read and Write Data Register (HW_I2C_DATA)....................................................1911 27.5.12 I2C Device Debug Register 0 (HW_I2C_DEBUG0)..................................................................................1912 27.5.13 I2C Device Debug Register 1 (HW_I2C_DEBUG1)..................................................................................1914 27.5.14 I2C Version Register (HW_I2C_VERSION)..............................................................................................1916 Chapter 28 Pulse-Width Modulator (PWM) Controller 28.1 Pulse Width Modulator (PWM) Overview...................................................................................................................1919 28.2 Operation.......................................................................................................................................................................1919 28.2.1 XTAL OSC Driving Mode..........................................................................................................................1922 28.2.2 HSADC Driving Mode................................................................................................................................1924 28.2.3 Multi-Chip Attachment Mode......................................................................................................................1925 28.2.4 Channel 2 Analog Enable Function.............................................................................................................1926 28.2.5 Channel Output Cutoff Using Module Clock Gate......................................................................................1926 28.3 Behavior During Reset..................................................................................................................................................1927 28.4 Programmable Registers...............................................................................................................................................1927 28.4.1 PWM Control and Status Register (HW_PWM_CTRL).............................................................................1928 28.4.2 PWM Channel 0 Active Register (HW_PWM_ACTIVE0)........................................................................1931 28.4.3 PWM Channel 0 Period Register (HW_PWM_PERIOD0).........................................................................1931 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 65 Section number Title Page 28.4.4 PWM Channel 1 Active Register (HW_PWM_ACTIVE1)........................................................................1933 28.4.5 PWM Channel 1 Period Register (HW_PWM_PERIOD1).........................................................................1934 28.4.6 PWM Channel 2 Active Register (HW_PWM_ACTIVE2)........................................................................1936 28.4.7 PWM Channel 2 Period Register (HW_PWM_PERIOD2).........................................................................1937 28.4.8 PWM Channel 3 Active Register (HW_PWM_ACTIVE3)........................................................................1939 28.4.9 PWM Channel 3 Period Register (HW_PWM_PERIOD3).........................................................................1939 28.4.10 PWM Channel 4 Active Register (HW_PWM_ACTIVE4)........................................................................1941 28.4.11 PWM Channel 4 Period Register (HW_PWM_PERIOD4).........................................................................1942 28.4.12 PWM Channel 5 Active Register (HW_PWM_ACTIVE5)........................................................................1944 28.4.13 PWM Channel 5 Period Register (HW_PWM_PERIOD5).........................................................................1945 28.4.14 PWM Channel 6 Active Register (HW_PWM_ACTIVE6)........................................................................1947 28.4.15 PWM Channel 6 Period Register (HW_PWM_PERIOD6).........................................................................1947 28.4.16 PWM Channel 7 Active Register (HW_PWM_ACTIVE7)........................................................................1949 28.4.17 PWM Channel 7 Period Register (HW_PWM_PERIOD7).........................................................................1950 28.4.18 PWM Version Register (HW_PWM_VERSION).......................................................................................1952 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.1 3-Port Ethernet Switch Features...................................................................................................................................1955 29.2 Block Diagram..............................................................................................................................................................1956 29.3 Switch Configuration....................................................................................................................................................1957 29.4 29.3.1 Overview......................................................................................................................................................1957 29.3.2 Passthrough Mode........................................................................................................................................1959 29.3.3 Switch Mode................................................................................................................................................1959 29.3.4 Port 0 Input Buffer.......................................................................................................................................1960 29.3.5 Port 0 Input Backpressure/Congestion Indication.......................................................................................1961 Switch Functional Description......................................................................................................................................1962 29.4.1 Overview......................................................................................................................................................1962 29.4.2 VLAN Input Processing Function................................................................................................................1963 29.4.2.1 Overview..................................................................................................................................1963 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 66 Freescale Semiconductor, Inc. Section number Title Page 29.4.2.2 Terms and Definitions..............................................................................................................1963 29.4.2.3 Configuration Information.......................................................................................................1963 29.4.2.4 Modes of Operation.................................................................................................................1964 29.4.2.4.1 Frame Processing................................................................................................1964 29.4.2.4.2 Mode 1 -- Single Tagging with Passthrough......................................................1964 29.4.2.4.3 Mode 2 -- Single Tagging with Replace.............................................................1964 29.4.2.4.4 Mode 3 -- Double Tagging with Passthrough.....................................................1964 29.4.2.4.5 Mode 4 -- Double Tagging with Replace...........................................................1965 29.4.3 IP Snooping..................................................................................................................................................1965 29.4.4 TCP/UDP Port Number Snooping...............................................................................................................1965 29.4.5 VLAN Output Processing Function.............................................................................................................1966 29.4.6 29.4.7 29.4.5.1 Overview..................................................................................................................................1966 29.4.5.2 Configuration Information.......................................................................................................1966 29.4.5.3 Modes of Operation.................................................................................................................1967 29.4.5.3.1 Overview.............................................................................................................1967 29.4.5.3.2 Mode 0: disabled.................................................................................................1967 29.4.5.3.3 Mode 1: Strip Mode............................................................................................1967 29.4.5.3.4 Mode 2: Tag Thru Mode.....................................................................................1967 29.4.5.3.5 Mode 3: Transparent Mode.................................................................................1967 Frame Classification and Priority Resolution..............................................................................................1967 29.4.6.1 Overview..................................................................................................................................1967 29.4.6.2 VLAN Priority Look-Up..........................................................................................................1968 29.4.6.3 Ipv4 and Ipv6 Priority Look Up...............................................................................................1968 29.4.6.3.1 Overview.............................................................................................................1968 29.4.6.3.2 Classification Table Programming Model..........................................................1969 29.4.6.4 Priority Resolution...................................................................................................................1970 29.4.6.5 Bridge Control Protocol Identification....................................................................................1971 Input Port Selection......................................................................................................................................1971 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 67 Section number 29.4.8 29.4.9 29.4.10 Title Page Layer 2 Look Up Engine..............................................................................................................................1971 29.4.8.1 Overview..................................................................................................................................1971 29.4.8.2 Hash Code................................................................................................................................1972 29.4.8.3 Address Memory......................................................................................................................1972 Layer 2 Lookup Tasks Overview.................................................................................................................1973 29.4.9.1 MAC Address Lookup.............................................................................................................1973 29.4.9.2 Forced Forwarding...................................................................................................................1974 29.4.9.3 Learning...................................................................................................................................1974 29.4.9.4 Migration..................................................................................................................................1976 29.4.9.5 Aging........................................................................................................................................1976 Frame Forwarding Tasks.............................................................................................................................1977 29.4.10.1 Overview..................................................................................................................................1977 29.4.10.2 VLAN Domain Verification....................................................................................................1978 29.4.10.3 Broadcast Multicast VLAN Domain Resolution.....................................................................1978 29.4.10.3.1 Overview.............................................................................................................1978 29.4.10.3.2 VLAN Resolution Table.....................................................................................1979 29.4.10.3.3 VLAN Switching and Resolution Mechanism...................................................1979 29.4.10.4 Port Mirroring..........................................................................................................................1980 29.4.10.5 Protocol Snooping....................................................................................................................1981 29.4.10.6 Bridge Protocol Frame Resolution...........................................................................................1982 29.4.10.6.1 Overview.............................................................................................................1982 29.4.10.6.2 Input Port Blocking.............................................................................................1982 29.4.10.6.3 Input Port Learning Disable................................................................................1982 29.4.10.6.4 Management Port Forwarding............................................................................1982 29.4.10.6.5 Management Frame Forwarding.........................................................................1983 29.4.10.7 Congestion Resolution.............................................................................................................1983 29.4.10.7.1 Overview.............................................................................................................1983 29.4.10.7.2 Unique Destination (one input to one output).....................................................1983 29.4.10.7.3 Multiple Destinations (Flooding)........................................................................1983 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 68 Freescale Semiconductor, Inc. Section number Title 29.4.10.8 29.5 29.6 29.7 Page Switching.................................................................................................................................1984 Output Frame Queuing.................................................................................................................................................1984 29.5.1 Overview......................................................................................................................................................1984 29.5.2 Cell and Queue Concept..............................................................................................................................1985 29.5.3 Write Control Module..................................................................................................................................1986 29.5.4 Cell Factory Module....................................................................................................................................1986 29.5.5 Output Queue Manager................................................................................................................................1987 29.5.5.1 Overview..................................................................................................................................1987 29.5.5.2 Weighted Fair Queuing scheduling algorithm.........................................................................1987 29.5.6 Congestion Management..............................................................................................................................1987 29.5.7 Implementation Notes..................................................................................................................................1988 Reset and Stop Functions..............................................................................................................................................1988 29.6.1 Stop Controls................................................................................................................................................1988 29.6.2 Port Disable..................................................................................................................................................1988 29.6.3 Port 0 Input Protection.................................................................................................................................1989 29.6.4 Port 1,2 Input Protection..............................................................................................................................1990 29.6.5 DMA Bus Error............................................................................................................................................1990 Firmware Architecture and Tasks.................................................................................................................................1990 29.7.1 Overview......................................................................................................................................................1990 29.7.2 Firmware Environment................................................................................................................................1990 29.7.3 Firmware Overview.....................................................................................................................................1990 29.7.3.1 Application Main.....................................................................................................................1991 29.7.3.2 Learning Task..........................................................................................................................1991 29.7.3.3 Timer Task...............................................................................................................................1991 29.7.3.4 Aging Task...............................................................................................................................1991 29.8 FIFO Interface Data Structure......................................................................................................................................1991 29.9 Programmable Registers...............................................................................................................................................1992 29.9.1 ENET SWI revision (HW_ENET_SWI_REVISION).................................................................................1998 29.9.2 ENET SWI lookup MAC address memory start (HW_ENET_SWI_LOOKUP_MEMORY_START).....1999 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 69 Section number Title Page 29.9.3 ENET SWI Scratch Register (HW_ENET_SWI_SCRATCH)...................................................................1999 29.9.4 ENET SWI Port Enable Bits. (HW_ENET_SWI_PORT_ENA).................................................................2000 29.9.5 ENET SWI Verify VLAN domain. (HW_ENET_SWI_VLAN_VERIFY)................................................2002 29.9.6 ENET SWI Default broadcast resolution. (HW_ENET_SWI_BCAST_DEFAULT_MASK)...................2003 29.9.7 ENET SWI Default multicast resolution. (HW_ENET_SWI_MCAST_DEFAULT_MASK)...................2004 29.9.8 ENET SWI Define port in blocking state and enable or disable learning. (HW_ENET_SWI_INPUT_LEARN_BLOCK)..........................................................................................2006 29.9.9 ENET SWI Bridge Management Port Configuration. (HW_ENET_SWI_MGMT_CONFIG)..................2007 29.9.10 ENET SWI Defines several global configuration settings. (HW_ENET_SWI_MODE_CONFIG)...........2009 29.9.11 ENET SWI Define behavior of VLAN input manipulation function (HW_ENET_SWI_VLAN_IN_MODE)......................................................................................................2010 29.9.12 ENET SWI Define behavior of VLAN output manipulation function (HW_ENET_SWI_VLAN_OUT_MODE)..................................................................................................2011 29.9.13 ENET SWI Enable the input processing according to the VLAN_IN_MODE for a port (HW_ENET_SWI_VLAN_IN_MODE_ENA)...........................................................................................2012 29.9.14 ENET SWI The VLAN type field value to expect to identify a VLAN tagged frame. (HW_ENET_SWI_VLAN_TAG_ID).........................................................................................................2013 29.9.15 ENET SWI Port Mirroring configuration. (HW_ENET_SWI_MIRROR_CONTROL).............................2014 29.9.16 ENET SWI Port Mirroring Egress port definitions. (HW_ENET_SWI_MIRROR_EG_MAP).................2015 29.9.17 ENET SWI Port Mirroring Ingress port definitions. (HW_ENET_SWI_MIRROR_ING_MAP)..............2016 29.9.18 ENET SWI Ingress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ISRC_0)..2018 29.9.19 ENET SWI Ingress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ISRC_1)..2018 29.9.20 ENET SWI Ingress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_IDST_0)......................................................................................................2019 29.9.21 ENET SWI Ingress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_IDST_1)......................................................................................................2019 29.9.22 ENET SWI Egress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ESRC_0). 2020 29.9.23 ENET SWI Egress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ESRC_1). 2020 29.9.24 ENET SWI Egress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_EDST_0).....................................................................................................2021 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 70 Freescale Semiconductor, Inc. Section number 29.9.25 Title Page ENET SWI Egress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_EDST_1).....................................................................................................2021 29.9.26 ENET SWI Count Value for Mirror filtering. (HW_ENET_SWI_MIRROR_CNT)..................................2021 29.9.27 ENET SWI Memory Manager Status. (HW_ENET_SWI_OQMGR_STATUS).......................................2022 29.9.28 ENET SWI Low Memory threshold. (HW_ENET_SWI_QMGR_MINCELLS).......................................2024 29.9.29 ENET SWI Statistic providing the lowest number of free cells reached in memory (HW_ENET_SWI_QMGR_ST_MINCELLS)............................................................................................2024 29.9.30 ENET SWI Port Congestion status (internal). (HW_ENET_SWI_QMGR_CONGEST_STAT)...............2025 29.9.31 ENET SWI Switch input and output interface status (internal). (HW_ENET_SWI_QMGR_IFACE_STAT)...............................................................................................2027 29.9.32 ENET SWI Queue weights for each queue. (HW_ENET_SWI_QM_WEIGHTS)....................................2028 29.9.33 ENET SWI Define congestion threshold for Port0 backpressure. (HW_ENET_SWI_QMGR_MINCELLSP0)...............................................................................................2029 29.9.34 ENET SWI Enable forced forwarding for a frame processed from port 0 (HW_ENET_SWI_FORCE_FWD_P0).......................................................................................................2029 29.9.35 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP1)...........................................................................................................2031 29.9.36 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP2)...........................................................................................................2032 29.9.37 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP3)...........................................................................................................2033 29.9.38 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP4)...........................................................................................................2035 29.9.39 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP5)...........................................................................................................2036 29.9.40 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP6)...........................................................................................................2038 29.9.41 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP7)...........................................................................................................2039 29.9.42 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP8)...........................................................................................................2041 29.9.43 ENET SWI IP Snooping function1 (HW_ENET_SWI_IPSNOOP1).........................................................2042 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 71 Section number Title Page 29.9.44 ENET SWI IP Snooping function2 (HW_ENET_SWI_IPSNOOP2).........................................................2044 29.9.45 ENET SWI IP Snooping function3 (HW_ENET_SWI_IPSNOOP3).........................................................2045 29.9.46 ENET SWI IP Snooping function4 (HW_ENET_SWI_IPSNOOP4).........................................................2046 29.9.47 ENET SWI IP Snooping function5 (HW_ENET_SWI_IPSNOOP5).........................................................2047 29.9.48 ENET SWI IP Snooping function6 (HW_ENET_SWI_IPSNOOP6).........................................................2048 29.9.49 ENET SWI IP Snooping function7 (HW_ENET_SWI_IPSNOOP7).........................................................2050 29.9.50 ENET SWI IP Snooping function8 (HW_ENET_SWI_IPSNOOP8).........................................................2051 29.9.51 ENET SWI Port 0 VLAN priority resolution map (HW_ENET_SWI_VLAN_PRIORITY0)...................2052 29.9.52 ENET SWI Port 1 VLAN priority resolution map (HW_ENET_SWI_VLAN_PRIORITY1)...................2053 29.9.53 ENET SWI Port 2 VLAN priority resolution map (HW_ENET_SWI_VLAN_PRIORITY2)...................2054 29.9.54 ENET SWI IPv4 and IPv6 priority resolution table programming (HW_ENET_SWI_IP_PRIORITY)....2054 29.9.55 ENET SWI Port 0 Priority resolution configuration (HW_ENET_SWI_PRIORITY_CFG0)....................2056 29.9.56 ENET SWI Port 1 Priority resolution configuration (HW_ENET_SWI_PRIORITY_CFG1)....................2057 29.9.57 ENET SWI Port 2 Priority resolution configuration (HW_ENET_SWI_PRIORITY_CFG2)....................2058 29.9.58 ENET SWI Port 0 VLAN-ID field for VLAN input manipulation function (HW_ENET_SWI_SYSTEM_TAGINFO0)...............................................................................................2060 29.9.59 ENET SWI Port 1 VLAN-ID field for VLAN input manipulation function (HW_ENET_SWI_SYSTEM_TAGINFO1)...............................................................................................2060 29.9.60 ENET SWI Port 2 VLAN-ID field for VLAN input manipulation function (HW_ENET_SWI_SYSTEM_TAGINFO2)...............................................................................................2061 29.9.61 ENET SWI VLAN domain resolution entry 0. (HW_ENET_SWI_VLAN_RES_TABLE_0)...................2061 29.9.62 ENET SWI VLAN domain resolution entry 1. (HW_ENET_SWI_VLAN_RES_TABLE_1)...................2062 29.9.63 ENET SWI VLAN domain resolution entry 2. (HW_ENET_SWI_VLAN_RES_TABLE_2)...................2063 29.9.64 ENET SWI VLAN domain resolution entry 3. (HW_ENET_SWI_VLAN_RES_TABLE_3)...................2064 29.9.65 ENET SWI VLAN domain resolution entry 4. (HW_ENET_SWI_VLAN_RES_TABLE_4)...................2065 29.9.66 ENET SWI VLAN domain resolution entry 5. (HW_ENET_SWI_VLAN_RES_TABLE_5)...................2066 29.9.67 ENET SWI VLAN domain resolution entry 6. (HW_ENET_SWI_VLAN_RES_TABLE_6)...................2067 29.9.68 ENET SWI VLAN domain resolution entry 7. (HW_ENET_SWI_VLAN_RES_TABLE_7)...................2068 29.9.69 ENET SWI VLAN domain resolution entry 8. (HW_ENET_SWI_VLAN_RES_TABLE_8)...................2069 29.9.70 ENET SWI VLAN domain resolution entry 9. (HW_ENET_SWI_VLAN_RES_TABLE_9)...................2070 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 72 Freescale Semiconductor, Inc. Section number Title Page 29.9.71 ENET SWI VLAN domain resolution entry 10. (HW_ENET_SWI_VLAN_RES_TABLE_10)...............2071 29.9.72 ENET SWI VLAN domain resolution entry 11. (HW_ENET_SWI_VLAN_RES_TABLE_11)...............2072 29.9.73 ENET SWI VLAN domain resolution entry 12. (HW_ENET_SWI_VLAN_RES_TABLE_12)...............2073 29.9.74 ENET SWI VLAN domain resolution entry 13. (HW_ENET_SWI_VLAN_RES_TABLE_13)...............2074 29.9.75 ENET SWI VLAN domain resolution entry 14. (HW_ENET_SWI_VLAN_RES_TABLE_14)...............2075 29.9.76 ENET SWI VLAN domain resolution entry 15. (HW_ENET_SWI_VLAN_RES_TABLE_15)...............2076 29.9.77 ENET SWI VLAN domain resolution entry 16. (HW_ENET_SWI_VLAN_RES_TABLE_16)...............2077 29.9.78 ENET SWI VLAN domain resolution entry 17. (HW_ENET_SWI_VLAN_RES_TABLE_17)...............2078 29.9.79 ENET SWI VLAN domain resolution entry 18. (HW_ENET_SWI_VLAN_RES_TABLE_18)...............2079 29.9.80 ENET SWI VLAN domain resolution entry 19. (HW_ENET_SWI_VLAN_RES_TABLE_19)...............2080 29.9.81 ENET SWI VLAN domain resolution entry 20. (HW_ENET_SWI_VLAN_RES_TABLE_20)...............2081 29.9.82 ENET SWI VLAN domain resolution entry 21. (HW_ENET_SWI_VLAN_RES_TABLE_21)...............2082 29.9.83 ENET SWI VLAN domain resolution entry 22. (HW_ENET_SWI_VLAN_RES_TABLE_22)...............2083 29.9.84 ENET SWI VLAN domain resolution entry 23. (HW_ENET_SWI_VLAN_RES_TABLE_23)...............2084 29.9.85 ENET SWI VLAN domain resolution entry 24. (HW_ENET_SWI_VLAN_RES_TABLE_24)...............2085 29.9.86 ENET SWI VLAN domain resolution entry 25. (HW_ENET_SWI_VLAN_RES_TABLE_25)...............2086 29.9.87 ENET SWI VLAN domain resolution entry 26. (HW_ENET_SWI_VLAN_RES_TABLE_26)...............2087 29.9.88 ENET SWI VLAN domain resolution entry 27. (HW_ENET_SWI_VLAN_RES_TABLE_27)...............2088 29.9.89 ENET SWI VLAN domain resolution entry 28. (HW_ENET_SWI_VLAN_RES_TABLE_28)...............2089 29.9.90 ENET SWI VLAN domain resolution entry 29. (HW_ENET_SWI_VLAN_RES_TABLE_29)...............2090 29.9.91 ENET SWI VLAN domain resolution entry 30. (HW_ENET_SWI_VLAN_RES_TABLE_30)...............2091 29.9.92 ENET SWI VLAN domain resolution entry 31. (HW_ENET_SWI_VLAN_RES_TABLE_31)...............2092 29.9.93 ENET SWI Total number of incoming frames processed (HW_ENET_SWI_TOTAL_DISC).................2093 29.9.94 ENET SWI Sum of bytes of frames counted in TOTAL_DISC (HW_ENET_SWI_TOTAL_BYT_DISC)...................................................................................................2094 29.9.95 ENET SWI Total number of incoming frames processed (HW_ENET_SWI_TOTAL_FRM)..................2094 29.9.96 ENET SWI Sum of bytes of frames counted in TOTAL_FRM (HW_ENET_SWI_TOTAL_BYT_FRM)...................................................................................................2094 29.9.97 ENET SWI Port 0 Outgoing frames discarded due to output Queue congestion (HW_ENET_SWI_ODISC0).......................................................................................................................2095 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 73 Section number 29.9.98 Title Page ENET SWI Port 0 incoming frames discarded due to mismatching or missing VLAN id (HW_ENET_SWI_IDISC_VLAN0)...........................................................................................................2095 29.9.99 ENET SWI Port 0 incoming frames discarded due to missing vlan tag (HW_ENET_SWI_IDISC_UNTAGGED0)................................................................................................2096 29.9.100 ENET SWI Port 0 incoming frames discarded (after learning) as port is configured in blocking mode (HW_ENET_SWI_IDISC_BLOCKED0)...................................................................................................2096 29.9.101 ENET SWI Port 1 Outgoing frames discarded due to output Queue congestion (HW_ENET_SWI_ODISC1).......................................................................................................................2097 29.9.102 ENET SWI Port 1 incoming frames discarded due to mismatching or missing VLAN id (HW_ENET_SWI_IDISC_VLAN1)...........................................................................................................2097 29.9.103 ENET SWI Port 1 incoming frames discarded due to missing vlan tag (HW_ENET_SWI_IDISC_UNTAGGED1)................................................................................................2097 29.9.104 ENET SWI Port 1 incoming frames discarded (after learning) as port is configured in blocking mode (HW_ENET_SWI_IDISC_BLOCKED1)...................................................................................................2098 29.9.105 ENET SWI Port 2 Outgoing frames discarded due to output Queue congestion (HW_ENET_SWI_ODISC2).......................................................................................................................2098 29.9.106 ENET SWI Port 2 incoming frames discarded due to mismatching or missing VLAN id (HW_ENET_SWI_IDISC_VLAN2)...........................................................................................................2099 29.9.107 ENET SWI Port 2 incoming frames discarded due to missing vlan tag (HW_ENET_SWI_IDISC_UNTAGGED2)................................................................................................2099 29.9.108 ENET SWI Port 2 incoming frames discarded (after learning) as port is configured in blocking mod (HW_ENET_SWI_IDISC_BLOCKED2)...................................................................................................2100 29.9.109 ENET SWI Interrupt Event Register (HW_ENET_SWI_EIR)...................................................................2100 29.9.110 ENET SWI Interrupt Mask Register (HW_ENET_SWI_EIMR)................................................................2101 29.9.111 ENET SWI Pointer to Receive Descriptor Ring (HW_ENET_SWI_ERDSR)...........................................2103 29.9.112 ENET SWI Pointer to Transmit Descriptor Ring (HW_ENET_SWI_ETDSR)..........................................2104 29.9.113 ENET SWI Maximum Receive Buffer Size (HW_ENET_SWI_EMRBR)................................................2104 29.9.114 ENET SWI Receive Descriptor Active Register (HW_ENET_SWI_RDAR)............................................2105 29.9.115 ENET SWI Transmit Descriptor Active Register (HW_ENET_SWI_TDAR)...........................................2105 29.9.116 ENET SWI Learning Records A (0) and B (1) (HW_ENET_SWI_LRN_REC_0)....................................2105 29.9.117 ENET SWI Learning Record B(1) (HW_ENET_SWI_LRN_REC_1).......................................................2106 29.9.118 ENET SWI Learning data available status. (HW_ENET_SWI_LRN_STATUS).......................................2107 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 74 Freescale Semiconductor, Inc. Section number Title Page 29.9.119 ENET SWI lookup MAC address memory end (HW_ENET_SWI_LOOKUP_MEMORY_END)...........2108 Chapter 30 Application UART (AUART) 30.1 Application UART Overview.......................................................................................................................................2109 30.2 Operation.......................................................................................................................................................................2111 30.2.1 Fractional Baud Rate Divider......................................................................................................................2112 30.2.2 Automatic Baud Rate Detection..................................................................................................................2112 30.2.3 UART Character Frame...............................................................................................................................2113 30.2.4 DMA Operation...........................................................................................................................................2113 30.2.5 Data Transmission or Reception..................................................................................................................2113 30.2.6 Error Bits......................................................................................................................................................2114 30.2.7 Overrun Bit..................................................................................................................................................2114 30.2.8 Disabling the FIFOs.....................................................................................................................................2115 30.3 Behavior During Reset..................................................................................................................................................2115 30.4 Programmable Registers...............................................................................................................................................2116 30.4.1 UART Receive DMA Control Register (HW_UARTAPP_CTRL0)..........................................................2116 30.4.2 UART Transmit DMA Control Register (HW_UARTAPP_CTRL1).........................................................2117 30.4.3 UART Control Register (HW_UARTAPP_CTRL2)..................................................................................2118 30.4.4 UART Line Control Register (HW_UARTAPP_LINECTRL)...................................................................2121 30.4.5 UART Line Control 2 Register (HW_UARTAPP_LINECTRL2)..............................................................2122 30.4.6 UART Interrupt Register (HW_UARTAPP_INTR)....................................................................................2124 30.4.7 UART Data Register (HW_UARTAPP_DATA)........................................................................................2126 30.4.8 UART Status Register (HW_UARTAPP_STAT).......................................................................................2128 30.4.9 UART Debug Register (HW_UARTAPP_DEBUG)..................................................................................2130 30.4.10 UART Version Register (HW_UARTAPP_VERSION).............................................................................2131 30.4.11 UART AutoBaud Register (HW_UARTAPP_AUTOBAUD)....................................................................2132 Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.1 Overview.......................................................................................................................................................................2135 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 75 Section number 31.2 Title Page Functional Description..................................................................................................................................................2138 31.2.1 Difference between OTG and HOST...........................................................................................................2138 31.2.2 USB Programmed I/O (PIO) Target Interface.............................................................................................2138 31.2.3 USB DMA Interface....................................................................................................................................2138 31.2.4 USB UTM Interface.....................................................................................................................................2139 31.2.4.1 31.2.5 USB Controller Flowcharts..........................................................................................................................2139 31.2.5.1 31.2.6 Digital/Analog Loopback Test Mode......................................................................................2139 References................................................................................................................................2142 USB Operation Model.................................................................................................................................2143 31.2.6.1 31.2.6.2 OTG Operations.......................................................................................................................2143 31.2.6.1.1 Register Bits........................................................................................................2143 31.2.6.1.2 Hardware Assist .................................................................................................2144 31.2.6.1.2.1 Auto-Reset .................................................................................2145 31.2.6.1.2.2 Data-Pulse ..................................................................................2145 31.2.6.1.2.3 B-Disconnect to A-Connect.......................................................2145 Host Data Structures................................................................................................................2146 31.2.6.2.1 Periodic Frame List.............................................................................................2147 31.2.6.2.2 Asynchronous List Queue Head Pointer.............................................................2149 31.2.6.2.3 Isochronous (High-Speed) Transfer Descriptor (iTD)........................................2149 31.2.6.2.4 31.2.6.2.3.1 Next Link Pointer.......................................................................2150 31.2.6.2.3.2 iTD Transaction Status and Control List....................................2151 31.2.6.2.3.3 iTD Buffer Page Pointer List (Plus)...........................................2152 Split Transaction Isochronous Transfer Descriptor (siTD)................................2154 31.2.6.2.4.1 Next Link Pointer.......................................................................2154 31.2.6.2.4.2 siTD Endpoint Capabilities/Characteristics...............................2155 31.2.6.2.4.3 siTD Transfer State.....................................................................2156 31.2.6.2.4.4 siTD Buffer Pointer List (plus)...................................................2157 31.2.6.2.4.5 siTD Back Link Pointer..............................................................2157 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 76 Freescale Semiconductor, Inc. Section number Title 31.2.6.2.5 31.2.6.2.6 31.2.6.2.7 31.2.6.3 Page Queue Element Transfer Descriptor (qTD)........................................................2158 31.2.6.2.5.1 Next qTD Pointer.......................................................................2159 31.2.6.2.5.2 Alternate Next qTD Pointer........................................................2159 31.2.6.2.5.3 qTD Token..................................................................................2160 31.2.6.2.5.4 qTD Buffer Page Pointer List.....................................................2163 Queue Head.........................................................................................................2163 31.2.6.2.6.1 Queue Head Horizontal Link Pointer.........................................2164 31.2.6.2.6.2 Queue Head Endpoint Capabilities/Characteristics....................2165 31.2.6.2.6.3 Transfer Overlay-Queue Head...................................................2167 Periodic Frame Span Traversal Node (FSTN)....................................................2168 31.2.6.2.7.1 FSTN Normal Path Pointer .......................................................2169 31.2.6.2.7.2 FSTN Back Path Link Pointer ...................................................2169 Host Operational Model ..........................................................................................................2170 31.2.6.3.1 Host Controller Initialization .............................................................................2170 31.2.6.3.2 Port Routing and Control ...................................................................................2171 31.2.6.3.2.1 Port Routing Control through EHCI Configured (CF) Bit ........2173 31.2.6.3.2.2 Port Routing Control through PortOwner and Disconnect Event ..........................................................................................2174 31.2.6.3.2.3 31.2.6.3.3 31.2.6.3.4 VBUS Power Control.........................................................................................2177 31.2.6.3.3.1 Port Power .................................................................................2177 31.2.6.3.3.2 Port Reporting Over-Current .....................................................2178 Suspend/Resume-Host Operational Model ........................................................2179 31.2.6.3.4.1 31.2.6.3.5 Example Port Routing State Machine .......................................2176 Port Suspend/Resume ................................................................2180 Schedule Traversal Rules ...................................................................................2182 31.2.6.3.5.1 Example - Preserving Micro-Frame Integrity ...........................2184 31.2.6.3.6 Periodic Schedule Frame Boundaries vs Bus Frame Boundaries ......................2186 31.2.6.3.7 Periodic Schedule ...............................................................................................2189 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 77 Section number Title 31.2.6.3.8 31.2.6.3.9 Page Managing Isochronous Transfers Using iTDs ...................................................2190 31.2.6.3.8.1 Host Controller Operational Model for iTDs ............................2191 31.2.6.3.8.2 Software Operational Model for iTDs .......................................2193 Asynchronous Schedule .....................................................................................2196 31.2.6.3.9.1 Adding Queue Heads to Asynchronous Schedule......................2197 31.2.6.3.9.2 Removing Queue Heads from Asynchronous Schedule ...........2198 31.2.6.3.9.3 Empty Asynchronous Schedule Detection ................................2200 31.2.6.3.9.4 Restarting Asynchronous Schedule Before EOF ......................2201 31.2.6.3.9.5 Asynchronous schedule traversal: Start Event...........................2204 31.2.6.3.9.6 Reclamation Status Bit (USBSTS Register) ..............................2205 31.2.6.3.10 Operational Model for Nak Counter...................................................................2205 31.2.6.3.10.1 Nak Count Reload Control ........................................................2207 31.2.6.3.11 Managing Control/Bulk/Interrupt Transfers through Queue Heads...................2209 31.2.6.3.11.1 Fetch Queue Head .....................................................................2211 31.2.6.3.11.2 Advance Queue .........................................................................2211 31.2.6.3.11.3 Execute Transaction ..................................................................2212 31.2.6.3.11.4 Write Back qTD ........................................................................2219 31.2.6.3.11.5 Follow Queue Head Horizontal Pointer ....................................2219 31.2.6.3.11.6 Buffer Pointer List Use for Data Streaming with qTDs ............2220 31.2.6.3.11.7 Adding Interrupt Queue Heads to the Periodic Schedule ..........2222 31.2.6.3.11.8 Managing Transfer Complete Interrupts from Queue Heads ....2222 31.2.6.3.12 Ping Control........................................................................................................2223 31.2.6.3.13 Split Transactions ...............................................................................................2224 31.2.6.3.13.1 Split Transactions for Asynchronous Transfers ........................2225 31.2.6.3.13.2 Split Transaction Interrupt .........................................................2227 31.2.6.3.13.3 Split Transaction Isochronous ...................................................2243 31.2.6.3.14 Host Controller Pause.........................................................................................2260 31.2.6.3.15 Port Test Modes -Host Operational Model.........................................................2261 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 78 Freescale Semiconductor, Inc. Section number Title Page 31.2.6.3.16 Interrupts-Host Operational Model.....................................................................2261 31.2.6.3.16.1 Transfer/Transaction Based Interrupts ......................................2263 31.2.6.3.16.2 Host Controller Event Interrupts ...............................................2265 31.2.6.4 EHCI Deviation........................................................................................................................2267 31.2.6.4.1 Embedded Transaction Translator Function.......................................................2268 31.2.6.4.1.1 Capability Registers....................................................................2268 31.2.6.4.1.2 Operational Registers.................................................................2269 31.2.6.4.1.3 Discovery-EHCI Deviation........................................................2269 31.2.6.4.1.4 Data Structures...........................................................................2269 31.2.6.4.1.5 Operational Model......................................................................2270 31.2.6.4.2 Device Operation................................................................................................2273 31.2.6.4.3 USB_USBMODE Register.................................................................................2273 31.2.6.4.4 31.2.6.4.3.1 Non-Zero Fields the Register File..............................................2273 31.2.6.4.3.2 SOF Interrupt..............................................................................2273 Embedded Design Interface................................................................................2273 31.2.6.4.4.1 31.2.6.4.5 31.2.6.5 Miscellaneous variations from EHCI..................................................................2274 31.2.6.4.5.1 Programmable Physical Interface Behaviour.............................2274 31.2.6.4.5.2 Discovery....................................................................................2274 31.2.6.4.5.3 Port Test Mode...........................................................................2275 Device Data Structures.............................................................................................................2275 31.2.6.5.1 31.2.6.5.2 31.2.6.6 Frame Adjust Register................................................................2273 Endpoint Queue Head (dQH)..............................................................................2276 31.2.6.5.1.1 Endpoint Capabilities/Characteristics........................................2277 31.2.6.5.1.2 Transfer Overlay-Endpoint Queue Head....................................2278 31.2.6.5.1.3 Current dTD Pointer...................................................................2278 31.2.6.5.1.4 Set-up Buffer..............................................................................2279 Endpoint Transfer Descriptor (dTD)..................................................................2279 Device Operational Model.......................................................................................................2281 31.2.6.6.1 Device Controller Initialization..........................................................................2281 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 79 Section number Title 31.2.6.6.2 31.2.6.6.3 31.2.6.6.4 31.2.6.6.5 31.2.6.6.6 31.3 Page Port State and Control.........................................................................................2282 31.2.6.6.2.1 Bus Reset....................................................................................2284 31.2.6.6.2.2 Suspend/Resume.........................................................................2285 31.2.6.6.2.3 Managing Endpoints...................................................................2287 31.2.6.6.2.4 Endpoint Initialization................................................................2287 31.2.6.6.2.5 Stalling........................................................................................2288 31.2.6.6.2.6 Data Toggle ...............................................................................2289 Operational Model For Packet Transfers............................................................2291 31.2.6.6.3.1 Interrupt/Bulk Endpoint Operational Model..............................2291 31.2.6.6.3.2 Control Endpoint Operation Model............................................2293 31.2.6.6.3.3 Isochronous Endpoint Operational Model..................................2296 Managing Queue Heads......................................................................................2299 31.2.6.6.4.1 Queue Head Initialization...........................................................2300 31.2.6.6.4.2 Operational Model For Setup Transfers.....................................2300 Managing Transfers with Transfer Descriptors..................................................2301 31.2.6.6.5.1 Software Link Pointers...............................................................2301 31.2.6.6.5.2 Building a Transfer Descriptor...................................................2302 31.2.6.6.5.3 Executing A Transfer Descriptor................................................2302 31.2.6.6.5.4 Transfer Completion...................................................................2303 31.2.6.6.5.5 Flushing/De-priming an Endpoint..............................................2304 31.2.6.6.5.6 Device Error Matrix...................................................................2305 Servicing Interrupts.............................................................................................2305 31.2.6.6.6.1 High-Frequency Interrupts.........................................................2305 31.2.6.6.6.2 Low-Frequency Interrupts..........................................................2306 31.2.6.6.6.3 Error Interrupts...........................................................................2306 Programmable Registers...............................................................................................................................................2307 31.3.1 Identification Register (HW_USBCTRL_ID).............................................................................................2309 31.3.2 General Hardware Parameters Register (HW_USBCTRL_HWGENERAL)..............................................2310 31.3.3 Host Hardware Parameters Register (HW_USBCTRL_HWHOST)...........................................................2311 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 80 Freescale Semiconductor, Inc. Section number Title Page 31.3.4 Device Hardware Parameters Register (HW_USBCTRL_HWDEVICE)...................................................2312 31.3.5 TX Buffer Hardware Parameters Register (HW_USBCTRL_HWTXBUF)...............................................2313 31.3.6 RX Buffer Hardware Parameters Register (HW_USBCTRL_HWRXBUF)...............................................2314 31.3.7 General-Purpose Timer 0 Load (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER0LD).....2315 31.3.8 General-Purpose Timer 0 Control (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER0CTRL).........................................................................................................2316 31.3.9 General-Purpose Timer 1 Load (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER1LD).....2317 31.3.10 General-Purpose Timer 1 Control (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER1CTRL).........................................................................................................2318 31.3.11 System Bus Configuration (Non-EHCI-Compliant) Register (HW_USBCTRL_SBUSCFG)...................2319 31.3.12 Capability Length and HCI Version (EHCI-Compliant) Register (HW_USBCTRL_CAPLENGTH).......2320 31.3.13 Host Control Structural Parameters (EHCI-Compliant with Extensions) Register (HW_USBCTRL_HCSPARAMS)..............................................................................................................2321 31.3.14 Host Control Capability Parameters (EHCI-Compliant) Register (HW_USBCTRL_HCCPARAMS)......2323 31.3.15 Device Interface Version Number (Non-EHCI-Compliant) Register (HW_USBCTRL_DCIVERSION). 2325 31.3.16 Device Control Capability Parameters (Non-EHCI-Compliant) Register (HW_USBCTRL_DCCPARAMS)..............................................................................................................2325 31.3.17 USB Command Register (HW_USBCTRL_USBCMD).............................................................................2327 31.3.18 USB Status Register (HW_USBCTRL_USBSTS)......................................................................................2331 31.3.19 USB Interrupt Enable Register (HW_USBCTRL_USBINTR)...................................................................2336 31.3.20 USB Frame Index Register (HW_USBCTRL_FRINDEX).........................................................................2339 31.3.21 Frame List Base Address Register (Host Controller mode) (HW_USBCTRL_PERIODICLISTBASE)...2340 31.3.22 USB Device Address Register (Device Controller mode) (HW_USBCTRL_DEVICEADDR).................2342 31.3.23 Next Asynchronous Address Register (Host Controller mode) (HW_USBCTRL_ASYNCLISTADDR). 2343 31.3.24 Endpoint List Address Register (Device Controller mode) (HW_USBCTRL_ENDPOINTLISTADDR). 2344 31.3.25 Embedded TT Asynchronous Buffer Status and Control Register (Host Controller mode) (HW_USBCTRL_TTCTRL).......................................................................................................................2345 31.3.26 Programmable Burst Size Register (HW_USBCTRL_BURSTSIZE).........................................................2346 31.3.27 Host Transmit Pre-Buffer Packet Timing Register (HW_USBCTRL_TXFILLTUNING)........................2347 31.3.28 Inter-Chip Control Register (HW_USBCTRL_IC_USB)...........................................................................2349 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 81 Section number Title Page 31.3.29 ULPI Viewport Register (HW_USBCTRL_ULPI).....................................................................................2351 31.3.30 Endpoint NAK Register (HW_USBCTRL_ENDPTNAK).........................................................................2352 31.3.31 Endpoint NAK Enable Register (HW_USBCTRL_ENDPTNAKEN)........................................................2353 31.3.32 Port Status and Control 1 Register (HW_USBCTRL_PORTSC1).............................................................2355 31.3.33 OTG Status and Control Register (HW_USBCTRL_OTGSC)...................................................................2363 31.3.34 USB Device Mode Register (HW_USBCTRL_USBMODE).....................................................................2367 31.3.35 Endpoint Setup Status Register (HW_USBCTRL_ENDPTSETUPSTAT)................................................2369 31.3.36 Endpoint Initialization Register (HW_USBCTRL_ENDPTPRIME)..........................................................2369 31.3.37 Endpoint De-Initialize Register (HW_USBCTRL_ENDPTFLUSH)..........................................................2371 31.3.38 Endpoint Status Register (HW_USBCTRL_ENDPTSTAT).......................................................................2372 31.3.39 Endpoint Complete Register (HW_USBCTRL_ENDPTCOMPLETE)......................................................2373 31.3.40 Endpoint Control 0 Register (HW_USBCTRL_ENDPTCTRL0)...............................................................2375 31.3.41 Endpoint Control 1 Register (HW_USBCTRL_ENDPTCTRL1)...............................................................2378 31.3.42 Endpoint Control 2 Register (HW_USBCTRL_ENDPTCTRL2)...............................................................2382 31.3.43 Endpoint Control 3 Register (HW_USBCTRL_ENDPTCTRL3)...............................................................2384 31.3.44 Endpoint Control 4 Register (HW_USBCTRL_ENDPTCTRL4)...............................................................2386 31.3.45 Endpoint Control 5 Register (HW_USBCTRL_ENDPTCTRL5)...............................................................2388 31.3.46 Endpoint Control 6 Register (HW_USBCTRL_ENDPTCTRL6)...............................................................2390 31.3.47 Endpoint Control 7 Register (HW_USBCTRL_ENDPTCTRL7)...............................................................2392 Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.1 USB PHY Overview.....................................................................................................................................................2395 32.2 Operation.......................................................................................................................................................................2396 32.2.1 UTMI...........................................................................................................................................................2397 32.2.2 Digital Transmitter.......................................................................................................................................2397 32.2.3 Digital Receiver...........................................................................................................................................2397 32.2.4 Analog Receiver...........................................................................................................................................2397 32.2.4.1 HS Differential Receiver..........................................................................................................2398 32.2.4.2 Squelch Detector......................................................................................................................2399 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 82 Freescale Semiconductor, Inc. Section number 32.2.5 32.2.6 32.3 32.4 Title Page 32.2.4.3 LS/FS Differential Receiver.....................................................................................................2399 32.2.4.4 HS Disconnect Detector...........................................................................................................2399 32.2.4.5 USB Plugged-In Detector........................................................................................................2399 32.2.4.6 Single-Ended USB_DP Receiver.............................................................................................2400 32.2.4.7 Single-Ended USB_DN Receiver............................................................................................2400 32.2.4.8 9X Oversample Module...........................................................................................................2400 Analog Transmitter......................................................................................................................................2400 32.2.5.1 Switchable High-Speed 45 Termination Resistors................................................................2400 32.2.5.2 Low-Speed/Full-Speed Differential Driver.............................................................................2401 32.2.5.3 High-Speed Differential Driver...............................................................................................2401 32.2.5.4 Switchable 1.5K USB_DP Pullup Resistor...........................................................................2401 32.2.5.5 Switchable 15K USB_DP Pulldown Resistor.......................................................................2401 Recommended Register Configuration for USB Certification....................................................................2403 USB PHY Memory Map/Register Definition...............................................................................................................2403 32.3.1 USB PHY Power-Down Register (USBPHY_PWDn)................................................................................2405 32.3.2 USB PHY Transmitter Control Register (USBPHY_TXn).........................................................................2407 32.3.3 USB PHY Receiver Control Register (USBPHY_RXn).............................................................................2408 32.3.4 USB PHY General Control Register (USBPHY_CTRLn)..........................................................................2410 32.3.5 USB PHY Status Register (USBPHY_STATUS).......................................................................................2413 32.3.6 USB PHY Debug Register (USBPHY_DEBUGn)......................................................................................2415 32.3.7 UTMI Debug Status Register 0 (USBPHY_DEBUG0_STATUS).............................................................2417 32.3.8 UTMI Debug Status Register 1 (USBPHY_DEBUG1n)............................................................................2418 32.3.9 UTMI RTL Version (USBPHY_VERSION)..............................................................................................2419 USB Analog Memory Map/Register Definition...........................................................................................................2419 32.4.1 Chip Silicon Version (USB_ANALOG_DIGPROG)..................................................................................2421 32.4.2 USB VBUS Detect Register (USB_ANALOG_USB1_VBUS_DETECTn)..............................................2422 32.4.3 USB Charger Detect Register (USB_ANALOG_USB1_CHRG_DETECTn)............................................2423 32.4.4 USB VBUS Detect Status Register (USB_ANALOG_USB1_VBUS_DETECT_STAT)..........................2425 32.4.5 USB Charger Detect Status Register (USB_ANALOG_USB1_CHRG_DETECT_STAT).......................2427 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 83 Section number Title Page 32.4.6 USB Misc Register (USB_ANALOG_USB1_MISCn)...............................................................................2428 32.4.7 USB VBUS Detect Register (USB_ANALOG_USB2_VBUS_DETECTn)..............................................2429 32.4.8 USB Charger Detect Register (USB_ANALOG_USB2_CHRG_DETECTn)............................................2431 32.4.9 USB VBUS Detect Status Register (USB_ANALOG_USB2_VBUS_DETECT_STAT)..........................2433 32.4.10 USB Charger Detect Status Register (USB_ANALOG_USB2_CHRG_DETECT_STAT).......................2435 32.4.11 USB Misc Register (USB_ANALOG_USB2_MISCn)...............................................................................2436 Chapter 33 LCD Interface (LCDIF) 33.1 LCD Interface (LCDIF) Overview...............................................................................................................................2439 33.2 Operation.......................................................................................................................................................................2440 33.2.1 Bus Interface Mechanisms...........................................................................................................................2441 33.2.1.1 Bus Master Operation in Write/Display Modes.......................................................................2442 33.2.1.2 DMA Operation in MPU Read Mode......................................................................................2443 33.2.2 Write Datapath.............................................................................................................................................2443 33.2.3 Read Datapath..............................................................................................................................................2448 33.2.4 LCDIF Interrupts..........................................................................................................................................2451 33.2.5 Initializing the LCDIF..................................................................................................................................2452 33.2.6 33.2.5.1 Write Modes.............................................................................................................................2452 33.2.5.2 MPU Read Mode.....................................................................................................................2453 MPU Interface..............................................................................................................................................2454 33.2.6.1 33.2.7 VSYNC Interface.........................................................................................................................................2456 33.2.7.1 33.2.8 Code Example to initialize LCDIF in VSYNC mode..............................................................2457 DOTCLK Interface......................................................................................................................................2458 33.2.8.1 33.3 Code Example to Initialize the LCDIF in MPU Write Mode..................................................2456 Code Example..........................................................................................................................2459 33.2.9 ITU-R BT.656 Digital Video Interface (DVI).............................................................................................2459 33.2.10 LCDIF Pin Usage by Interface Mode..........................................................................................................2460 Behavior During Reset..................................................................................................................................................2464 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 84 Freescale Semiconductor, Inc. Section number 33.4 Title Page Programmable Registers...............................................................................................................................................2464 33.4.1 LCDIF General Control Register (HW_LCDIF_CTRL).............................................................................2465 33.4.2 LCDIF General Control1 Register (HW_LCDIF_CTRL1).........................................................................2469 33.4.3 LCDIF General Control2 Register (HW_LCDIF_CTRL2).........................................................................2472 33.4.4 LCDIF Horizontal and Vertical Valid Data Count Register (HW_LCDIF_TRANSFER_COUNT)..........2476 33.4.5 LCD Interface Current Buffer Address Register (HW_LCDIF_CUR_BUF)..............................................2476 33.4.6 LCD Interface Next Buffer Address Register (HW_LCDIF_NEXT_BUF)................................................2477 33.4.7 LCD Interface Timing Register (HW_LCDIF_TIMING)...........................................................................2477 33.4.8 LCDIF VSYNC Mode and Dotclk Mode Control Register0 (HW_LCDIF_VDCTRL0)...........................2478 33.4.9 LCDIF VSYNC Mode and Dotclk Mode Control Register1 (HW_LCDIF_VDCTRL1)...........................2480 33.4.10 LCDIF VSYNC Mode and Dotclk Mode Control Register2 (HW_LCDIF_VDCTRL2)...........................2481 33.4.11 LCDIF VSYNC Mode and Dotclk Mode Control Register3 (HW_LCDIF_VDCTRL3)...........................2481 33.4.12 LCDIF VSYNC Mode and Dotclk Mode Control Register4 (HW_LCDIF_VDCTRL4)...........................2482 33.4.13 Digital Video Interface Control0 Register (HW_LCDIF_DVICTRL0)......................................................2484 33.4.14 Digital Video Interface Control1 Register (HW_LCDIF_DVICTRL1)......................................................2484 33.4.15 Digital Video Interface Control2 Register (HW_LCDIF_DVICTRL2)......................................................2485 33.4.16 Digital Video Interface Control3 Register (HW_LCDIF_DVICTRL3)......................................................2486 33.4.17 Digital Video Interface Control4 Register (HW_LCDIF_DVICTRL4)......................................................2487 33.4.18 RGB to YCbCr 4:2:2 CSC Coefficient0 Register (HW_LCDIF_CSC_COEFF0)......................................2488 33.4.19 RGB to YCbCr 4:2:2 CSC Coefficient1 Register (HW_LCDIF_CSC_COEFF1)......................................2489 33.4.20 RGB to YCbCr 4:2:2 CSC Coefficent2 Register (HW_LCDIF_CSC_COEFF2).......................................2490 33.4.21 RGB to YCbCr 4:2:2 CSC Coefficient3 Register (HW_LCDIF_CSC_COEFF3)......................................2491 33.4.22 RGB to YCbCr 4:2:2 CSC Coefficient4 Register (HW_LCDIF_CSC_COEFF4)......................................2492 33.4.23 RGB to YCbCr 4:2:2 CSC Offset Register (HW_LCDIF_CSC_OFFSET)................................................2492 33.4.24 RGB to YCbCr 4:2:2 CSC Limit Register (HW_LCDIF_CSC_LIMIT)....................................................2493 33.4.25 LCD Interface Data Register (HW_LCDIF_DATA)...................................................................................2494 33.4.26 Bus Master Error Status Register (HW_LCDIF_BM_ERROR_STAT).....................................................2495 33.4.27 CRC Status Register (HW_LCDIF_CRC_STAT).......................................................................................2495 33.4.28 LCD Interface Status Register (HW_LCDIF_STAT).................................................................................2496 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 85 Section number Title Page 33.4.29 LCD Interface Version Register (HW_LCDIF_VERSION).......................................................................2497 33.4.30 LCD Interface Debug0 Register (HW_LCDIF_DEBUG0).........................................................................2498 33.4.31 LCD Interface Debug1 Register (HW_LCDIF_DEBUG1).........................................................................2501 33.4.32 LCD Interface Debug2 Register (HW_LCDIF_DEBUG2).........................................................................2502 Chapter 34 Pixel Pipeline (PXP) 34.1 34.2 34.3 Pixel Pipeling (PXP) Overview....................................................................................................................................2503 34.1.1 Image Support..............................................................................................................................................2504 34.1.2 Block Size Selection....................................................................................................................................2505 34.1.3 PXP Limitations/Issues................................................................................................................................2505 Operation.......................................................................................................................................................................2506 34.2.1 Pixel Handling..............................................................................................................................................2507 34.2.2 S0 Cropping/Masking..................................................................................................................................2508 34.2.3 Scaling..........................................................................................................................................................2511 34.2.4 Color Space Conversion (CSC)...................................................................................................................2512 34.2.5 Overlays.......................................................................................................................................................2513 34.2.6 Alpha Blending............................................................................................................................................2514 34.2.7 Color Key.....................................................................................................................................................2515 34.2.8 Raster Operations (ROPs)............................................................................................................................2516 34.2.9 Rotation........................................................................................................................................................2517 34.2.10 In-place Rendering.......................................................................................................................................2519 34.2.11 Interlaced Video Support.............................................................................................................................2520 34.2.12 Queueing Frame Operations........................................................................................................................2521 Examples.......................................................................................................................................................................2522 34.3.1 Basic QVGA Example.................................................................................................................................2522 34.3.2 Basic QVGA with Overlays.........................................................................................................................2523 34.3.3 Cropped QVGA Example............................................................................................................................2525 34.3.4 Upscale QVGA to VGA with Overlays.......................................................................................................2527 34.3.5 Downscale VGA to WQVGA (480x272) to fill screen...............................................................................2529 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 86 Freescale Semiconductor, Inc. Section number 34.3.6 34.4 Title Page Downscale VGA to QVGA with Overlapping Overlays.............................................................................2531 Programmable Registers...............................................................................................................................................2534 34.4.1 PXP Control Register 0 (HW_PXP_CTRL)................................................................................................2537 34.4.2 PXP Status Register (HW_PXP_STAT)......................................................................................................2540 34.4.3 Output Frame Buffer Pointer (HW_PXP_OUTBUF)..................................................................................2542 34.4.4 Output Frame Buffer Pointer #2 (HW_PXP_OUTBUF2)...........................................................................2542 34.4.5 PXP Output Buffer Size (HW_PXP_OUTSIZE).........................................................................................2543 34.4.6 PXP Source 0 (video) Input Buffer Pointer (HW_PXP_S0BUF)................................................................2544 34.4.7 Source 0 U/Cb or 2 Plane UV Input Buffer Pointer (HW_PXP_S0UBUF)................................................2544 34.4.8 Source 0 V/Cr Input Buffer Pointer (HW_PXP_S0VBUF).........................................................................2545 34.4.9 PXP Source 0 (video) Buffer Parameters (HW_PXP_S0PARAM)............................................................2545 34.4.10 Source 0 Background Color (HW_PXP_S0BACKGROUND)...................................................................2546 34.4.11 Source 0 Cropping Register (HW_PXP_S0CROP).....................................................................................2547 34.4.12 Source 0 Scale Factor Register (HW_PXP_S0SCALE)..............................................................................2548 34.4.13 Source 0 Scale Offset Register (HW_PXP_S0OFFSET)............................................................................2549 34.4.14 Color Space Conversion Coefficient Register 0 (HW_PXP_CSCCOEFF0)...............................................2550 34.4.15 Color Space Conversion Coefficient Register 1 (HW_PXP_CSCCOEFF1)...............................................2551 34.4.16 Color Space Conversion Coefficient Register 2 (HW_PXP_CSCCOEFF2)...............................................2552 34.4.17 PXP Next Frame Pointer (HW_PXP_NEXT).............................................................................................2553 34.4.18 PXP S0 Color Key Low (HW_PXP_S0COLORKEYLOW)......................................................................2555 34.4.19 PXP S0 Color Key High (HW_PXP_S0COLORKEYHIGH).....................................................................2556 34.4.20 PXP Overlay Color Key Low (HW_PXP_OLCOLORKEYLOW)............................................................2556 34.4.21 PXP Overlay Color Key High (HW_PXP_OLCOLORKEYHIGH)...........................................................2557 34.4.22 PXP Debug Control Register (HW_PXP_DEBUGCTRL).........................................................................2558 34.4.23 PXP Debug Register (HW_PXP_DEBUG).................................................................................................2559 34.4.24 PXP Version Register (HW_PXP_VERSION)...........................................................................................2560 34.4.25 PXP Overlay 0 Buffer Pointer (HW_PXP_OL0)........................................................................................2560 34.4.26 PXP Overlay 0 Size (HW_PXP_OL0SIZE)................................................................................................2561 34.4.27 PXP Overlay 0 Parameters (HW_PXP_OL0PARAM)...............................................................................2562 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 87 Section number Title Page 34.4.28 PXP Overlay 0 Parameters 2 (HW_PXP_OL0PARAM2)..........................................................................2564 34.4.29 PXP Overlay 1 Buffer Pointer (HW_PXP_OL1)........................................................................................2564 34.4.30 PXP Overlay 1 Size (HW_PXP_OL1SIZE)................................................................................................2565 34.4.31 PXP Overlay 1 Parameters (HW_PXP_OL1PARAM)...............................................................................2565 34.4.32 PXP Overlay 1 Parameters 2 (HW_PXP_OL1PARAM2)..........................................................................2567 34.4.33 PXP Overlay 2 Buffer Pointer (HW_PXP_OL2)........................................................................................2568 34.4.34 PXP Overlay 2 Size (HW_PXP_OL2SIZE)................................................................................................2568 34.4.35 PXP Overlay 2 Parameters (HW_PXP_OL2PARAM)...............................................................................2569 34.4.36 PXP Overlay 2 Parameters 2 (HW_PXP_OL2PARAM2)..........................................................................2571 34.4.37 PXP Overlay 3 Buffer Pointer (HW_PXP_OL3)........................................................................................2572 34.4.38 PXP Overlay 3 Size (HW_PXP_OL3SIZE)................................................................................................2572 34.4.39 PXP Overlay 3 Parameters (HW_PXP_OL3PARAM)...............................................................................2573 34.4.40 PXP Overlay 3 Parameters 2 (HW_PXP_OL3PARAM2)..........................................................................2575 34.4.41 PXP Overlay 4 Buffer Pointer (HW_PXP_OL4)........................................................................................2575 34.4.42 PXP Overlay 4 Size (HW_PXP_OL4SIZE)................................................................................................2576 34.4.43 PXP Overlay 4 Parameters (HW_PXP_OL4PARAM)...............................................................................2576 34.4.44 PXP Overlay 4 Parameters 2 (HW_PXP_OL4PARAM2)..........................................................................2578 34.4.45 PXP Overlay 5 Buffer Pointer (HW_PXP_OL5)........................................................................................2579 34.4.46 PXP Overlay 5 Size (HW_PXP_OL5SIZE)................................................................................................2579 34.4.47 PXP Overlay 5 Parameters (HW_PXP_OL5PARAM)...............................................................................2580 34.4.48 PXP Overlay 5 Parameters 2 (HW_PXP_OL5PARAM2)..........................................................................2582 34.4.49 PXP Overlay 6 Buffer Pointer (HW_PXP_OL6)........................................................................................2583 34.4.50 PXP Overlay 6 Size (HW_PXP_OL6SIZE)................................................................................................2583 34.4.51 PXP Overlay 6 Parameters (HW_PXP_OL6PARAM)...............................................................................2584 34.4.52 PXP Overlay 6 Parameters 2 (HW_PXP_OL6PARAM2)..........................................................................2586 34.4.53 PXP Overlay 7 Buffer Pointer (HW_PXP_OL7)........................................................................................2586 34.4.54 PXP Overlay 7 Size (HW_PXP_OL7SIZE)................................................................................................2587 34.4.55 PXP Overlay 7 Parameters (HW_PXP_OL7PARAM)...............................................................................2587 34.4.56 PXP Overlay 7 Parameters 2 (HW_PXP_OL7PARAM2)..........................................................................2589 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 88 Freescale Semiconductor, Inc. Section number Title Page Chapter 35 Serial Audio Interface (SAIF) 35.1 Serial Audio Interface (SAIF) Overview......................................................................................................................2591 35.2 Operation.......................................................................................................................................................................2592 35.3 35.2.1 Sample Rate Programming and Codec Clocking Operation........................................................................2593 35.2.2 Transmit Operation......................................................................................................................................2597 35.2.3 Receive Operation........................................................................................................................................2598 35.2.4 DMA Interface.............................................................................................................................................2599 35.2.5 PCM Data FIFO...........................................................................................................................................2599 35.2.6 Serial Frame Formats...................................................................................................................................2600 35.2.7 Pin Timing....................................................................................................................................................2601 Programmable Registers...............................................................................................................................................2602 35.3.1 SAIF Control Register (HW_SAIF_CTRL)................................................................................................2603 35.3.2 SAIF Status Register (HW_SAIF_STAT)...................................................................................................2607 35.3.3 SAIF Data Register (HW_SAIF_DATA)....................................................................................................2609 35.3.4 SAIF Version Register (HW_SAIF_VERSION).........................................................................................2611 Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) 36.1 Overview.......................................................................................................................................................................2613 36.2 Operation.......................................................................................................................................................................2613 36.3 36.2.1 Interrupts......................................................................................................................................................2617 36.2.2 Clocking.......................................................................................................................................................2617 36.2.3 DMA Operation...........................................................................................................................................2618 36.2.4 PIO Debug Mode.........................................................................................................................................2620 Programmable Registers...............................................................................................................................................2622 36.3.1 SPDIF Control Register (HW_SPDIF_CTRL)............................................................................................2622 36.3.2 SPDIF Status Register (HW_SPDIF_STAT)..............................................................................................2624 36.3.3 SPDIF Frame Control Register (HW_SPDIF_FRAMECTRL)...................................................................2626 36.3.4 SPDIF Sample Rate Register (HW_SPDIF_SRR)......................................................................................2627 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 89 Section number Title Page 36.3.5 SPDIF Debug Register (HW_SPDIF_DEBUG)..........................................................................................2628 36.3.6 SPDIF Write Data Register (HW_SPDIF_DATA).....................................................................................2630 36.3.7 SPDIF Version Register (HW_SPDIF_VERSION)....................................................................................2631 Chapter 37 High-Speed ADC (HSADC) 37.1 Overview.......................................................................................................................................................................2633 37.2 High-Speed ADC Block Features.................................................................................................................................2634 37.3 37.2.1 Sample Rate and Sample Precision..............................................................................................................2635 37.2.2 Trigger Modes..............................................................................................................................................2635 37.2.3 APBH-DMA Channel..................................................................................................................................2635 37.2.4 Synchronization with PWM Block..............................................................................................................2635 37.2.5 Clock Domains.............................................................................................................................................2635 37.2.6 Sample Precision, Endian, Half-word Swap and Bits Left-Shift.................................................................2636 Operation.......................................................................................................................................................................2636 37.3.1 Trigger Modes..............................................................................................................................................2638 37.3.2 Sample Data Bits Left Shift.........................................................................................................................2639 37.3.3 Bits Location................................................................................................................................................2639 37.3.4 Configuration of APBH-DMA.....................................................................................................................2640 37.3.5 Configuration of PWM................................................................................................................................2640 37.3.6 Configuration of High-speed ADC..............................................................................................................2641 37.3.7 Interrupt Sources..........................................................................................................................................2641 37.3.8 Working Modes............................................................................................................................................2642 37.3.8.1 Single Mode.............................................................................................................................2642 37.3.8.2 Loop Mode...............................................................................................................................2642 37.3.9 Debugging Information................................................................................................................................2642 37.3.10 Behavior During Reset.................................................................................................................................2643 37.4 Programming Example.................................................................................................................................................2643 37.5 Programmable Registers...............................................................................................................................................2644 37.5.1 HSADC Control Register 0 (HW_HSADC_CTRL0).................................................................................2644 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 90 Freescale Semiconductor, Inc. Section number Title Page 37.5.2 HSADC Control Register 1 (HW_HSADC_CTRL1).................................................................................2648 37.5.3 HSADC Control Register 2 (HW_HSADC_CTRL2).................................................................................2651 37.5.4 HSADC Sequence Samples Number Register (HW_HSADC_SEQUENCE_SAMPLES_NUM).............2652 37.5.5 HSADC Sequence Number Register (HW_HSADC_SEQUENCE_NUM)...............................................2653 37.5.6 HSADC FIFO Data Register (HW_HSADC_FIFO_DATA)......................................................................2654 37.5.7 HSADC Debug Information 0 Register (HW_HSADC_DBG_INFO0).....................................................2654 37.5.8 HSADC Debug Information 1 Register (HW_HSADC_DBG_INFO1).....................................................2655 37.5.9 HSADC Debug Information 2 Register (HW_HSADC_DBG_INFO2).....................................................2656 37.5.10 HSADC Version Register (HW_HSADC_VERSION)...............................................................................2656 Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface 38.1 LRADC Overview........................................................................................................................................................2659 38.2 Operation.......................................................................................................................................................................2661 38.2.1 External Temperature Sensing with a Diode...............................................................................................2662 38.2.2 Internal Die Temperature Sensing...............................................................................................................2663 38.2.3 Scheduling Conversions...............................................................................................................................2664 38.2.4 Delay Channels............................................................................................................................................2664 38.3 Channel Threshold Detection.......................................................................................................................................2665 38.4 Behavior During Reset..................................................................................................................................................2666 38.5 Programmable Registers...............................................................................................................................................2669 38.5.1 LRADC Control Register 0 (HW_LRADC_CTRL0).................................................................................2671 38.5.2 LRADC Control Register 1 (HW_LRADC_CTRL1).................................................................................2673 38.5.3 LRADC Control Register 2 (HW_LRADC_CTRL2).................................................................................2677 38.5.4 LRADC Control Register 3 (HW_LRADC_CTRL3).................................................................................2680 38.5.5 LRADC Status Register (HW_LRADC_STATUS)....................................................................................2682 38.5.6 LRADC 0 Result Register (HW_LRADC_CH0)........................................................................................2685 38.5.7 LRADC 1 Result Register (HW_LRADC_CH1)........................................................................................2687 38.5.8 LRADC 2 Result Register (HW_LRADC_CH2)........................................................................................2689 38.5.9 LRADC 3 Result Register (HW_LRADC_CH3)........................................................................................2691 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 91 Section number Title Page 38.5.10 LRADC 4 Result Register (HW_LRADC_CH4)........................................................................................2693 38.5.11 LRADC 5 Result Register (HW_LRADC_CH5)........................................................................................2695 38.5.12 LRADC 6 Result Register (HW_LRADC_CH6)........................................................................................2697 38.5.13 LRADC 7 (BATT) Result Register (HW_LRADC_CH7)..........................................................................2699 38.5.14 LRADC Scheduling Delay 0 (HW_LRADC_DELAY0)............................................................................2701 38.5.15 LRADC Scheduling Delay 1 (HW_LRADC_DELAY1)............................................................................2702 38.5.16 LRADC Scheduling Delay 2 (HW_LRADC_DELAY2)............................................................................2704 38.5.17 LRADC Scheduling Delay 3 (HW_LRADC_DELAY3)............................................................................2705 38.5.18 LRADC Debug Register 0 (HW_LRADC_DEBUG0)...............................................................................2707 38.5.19 LRADC Debug Register 1 (HW_LRADC_DEBUG1)...............................................................................2708 38.5.20 LRADC Battery Conversion Register (HW_LRADC_CONVERSION)....................................................2709 38.5.21 LRADC Control Register 4 (HW_LRADC_CTRL4).................................................................................2711 38.5.22 LRADC Theshold0 Register (HW_LRADC_THRESHOLD0)..................................................................2715 38.5.23 LRADC Theshold1 Register (HW_LRADC_THRESHOLD1)..................................................................2716 38.5.24 LRADC Version Register (HW_LRADC_VERSION)...............................................................................2718 Chapter 39 Register Macro Usage 39.1 Overview.......................................................................................................................................................................2719 39.2 Definitions.....................................................................................................................................................................2719 39.3 Background...................................................................................................................................................................2720 39.3.1 Multi-Instance Blocks..................................................................................................................................2721 39.3.1.1 Examples..................................................................................................................................2721 39.4 Naming Convention......................................................................................................................................................2722 39.5 Examples.......................................................................................................................................................................2723 39.5.1 Setting 1-Bit Wide Field..............................................................................................................................2723 39.5.2 Clearing 1-Bit Wide Field............................................................................................................................2724 39.5.3 Toggling 1-Bit Wide Field...........................................................................................................................2724 39.5.4 Modifying n-Bit Wide Field........................................................................................................................2724 39.5.5 Modifying Multiple Fields...........................................................................................................................2724 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 92 Freescale Semiconductor, Inc. Section number Title Page 39.5.6 Writing Entire Register (All Fields Updated at Once).................................................................................2725 39.5.7 Reading a Bit Field......................................................................................................................................2725 39.5.8 Reading Entire Register...............................................................................................................................2725 39.5.9 Accessing Multiple Instance Register..........................................................................................................2725 39.5.10 Correct Way to Soft Reset a Block..............................................................................................................2726 39.5.10.1 Pinmux Selection During Reset...............................................................................................2726 39.5.10.1.1 Correct and Incorrect Reset Examples................................................................2726 39.6 Summary Preferred.......................................................................................................................................................2727 39.7 Summary Alternate Syntax...........................................................................................................................................2727 39.8 Assembly Example.......................................................................................................................................................2728 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 93 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 94 Freescale Semiconductor, Inc. Chapter 1 Product Overview 1.1 i.MX28 Overview The i.MX28 is a low-power, high performance application and a multi-media processor aimed at the following market segments: * Human Machine Interface (HMI) panels: industrial, home. * Industrial drive, PLC, I/O control display, factory robotics display. * Graphical remote controls. * Handheld scanners and printers. * Electronic point-of-sale (POS) terminals. * Smart energy gateways/meters. * Media gateways. * Portable medical devices. * Media phones, VoIP. * Automotive infotainment. 1.2 Hardware Features The Hardware Features of the i.MX28 are as follows: * ARM926 CPU Running at greater than 450 MHz at 1.45 V * Integrated ARM926EJ-S CPU * 32-Kbyte data cache and 16-Kbyte instruction cache i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 95 Hardware Features * ARM Embedded Trace Macrocell (ETM CoreSight 9) * Parallel JTAG interface * Resistor-less boot mode selection using integrated OTP values * 128 Kbytes of Integrated Low-Power On-Chip RAM * 128 Kbytes of Integrated Mask-Programmable On-Chip ROM * High Performance and Flexible External Memory Interface (EMI) * Supports DDR2-400 (1.8 V), LP-DDR1-400 (1.8 V) and LV-DDR2-400 (1.5 V) * 16-bit data-width with up to two chip-selects * Rich arbitration features and high-performance AXI & AHB bus interface * Integrated ODT and control for DDR2 applications * Up to 200 MHz DDR clock frequency with voltage over drive * 1280 bits of On-Chip One-Time-Programmable (OCOTP) ROM * Two 802.3 compatible 10/100 Ethernet MAC supporting IEEE(R) 1588 protocols and one 3-port L2 switch * Two FlexCAN2 interfaces supported * Full Implementation of the CAN protocol specification, Version 2.0B * 64 Message Buffers of zero to eight bytes data length * Low power modes, with programmable wake up on bus activity * Two instances of Universal Serial Bus (USB) High-Speed -- Up to 480 Mb/s * One USB 2.0 on-the-go (OTG) device/host and one USB 2.0 host * Fully integrated high/full/low-speed/ Physical Layer Protocol (PHY) * OTG capable (uncertified by USB-IF) * Power Management Units * Single DC-DC switched converter supporting Li-Ion batteries. * Features multi-channel outputs for VDDIO (3.3 V), VDDD (1.2 V), VDD1P5 (1.5 V), VDDA (1.8 V) and regulated 4.2 V source * 1.5 V linear regulator with programmable current limits for load and battery charge circuits i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 96 Freescale Semiconductor, Inc. Chapter 1 Product Overview * Silicon speed and temperature sensors enable adaptive power management over temperature and silicon process * Integrated temperature based power shut-down safety modes * Optimized for very long battery life * 16-Channel Low-Resolution ADC * Seven independent channels and nine dedicated channels * 4/5 wires resistive touchscreen controller * 8 x 8 key pad panel matrix * Temperature sensor controller * Absolute accuracy of 1.3% * Up to 0.5% with bandgap calibration * Single Channel High Speed ADC (HSADC) * Up to 2 Msps sample rate * Sample precision configurable for 8/10/12 bits * Three trigger modes supporting to start ADC conversion * Security Features * Read-only unique ID for digital rights management algorithms * Secure boot using 128-bit AES hardware decryption * SHA-1 and SHA-256 hashing hardware * Customer-programmed (OTP) 128 bit AES key is never visible to software * High Assurance Boot (HAB4) * Wide Assortment of External Media Interfaces * Up to eight NAND Flash memories with hardware management of device interleaving * High-speed MMC, secure digital (SD) * Hardware BCH ECC engine allowing for up to 20-bit correction with programmable NAND page layout. * Dual Peripheral Bus Bridges with 32 DMA Channels i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 97 Hardware Features * Multiple peripheral clock domains to save power while optimizing performance * Direct Memory Access (DMA) with sophisticated linked DMA command architecture saves power and off-loads the CPU * Highly Flexible Display Controller * Up to 24-bit RGB (DOTCK) modes * Up to 24-bit system-mode including VSYNC and WSYNC modes * 8-bit data ITU-R/BT.656 D1 digital video stream output mode (PAL/NTSC), with on-the-fly RGB to YCbCr color-space-conversion * Flexible input formats * Pixel Processing Pipeline (PXP) * Provides full path from color-space conversion, scaling, alpha-blending to rotation without intermediate memory access * Bi-linear scaling algorithm with cropping and letterboxing with up to 4:1 downscaling (720p to QVGA for example) * Alpha-blend, color-keying * Memory efficient block-based rotation engine * Supports up to eight overlays * 8 x 8 and 16 x 16 programmable block size for DRAM bus-width matching resulting in optimized efficiency. * Data Co-Processor (DCP) * AES 128-bit encryption/decryption * SHA-1 and SHA256 hashing * High-speed memory copy * Bit Blit * Six Universal Asynchronous Receiver-Transmitters (UARTs) * Five high-speed application UARTs operating up to 3.25 Mb/s with hardware flow control, dual DMA and auto baud-rate detection * Debug UART operates at up to 115 Kb/s using programmed I/O * Two I2C Master/Slave Interfaces i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 98 Freescale Semiconductor, Inc. Chapter 1 Product Overview * Up to 400 Kb/s * DMA control of an entire EEPROM or other device read/write transaction without CPU intervention * PIO and PIO queue modes controlled by CPU. In PIO queue mode, commands and data are queued up with FIFOs * Both 7-bit and 10-bit device address supported in master mode. Programmable 7-bit address employed in slave mode * Four Synchronous Serial Ports (for SPI, MMC, SDIO, Triflash) * Up to 52 MHz external SSP clock for SD/MMC mode * 1-bit, 4-bit and 8-bit MMC/SD/SDIO modes * Compliant with SDIO Rev. 2.0 * Support eMMC4.3 and eMMC4.4 * SPI with single, dual and quad modes * Four-Channel 32-Bit Timer with Rotary Decoder * Eight-Channel Pulse Width Modulator (PWM) * Real-Time Clock * Alarm clock can turn the system on * Uses the existing 24-MHz XTAL for low cost or optional low power crystal (32.768 KHz or 32.0 KHz), customer-selectable through OTP * SPDIF Transmitter * Dual Serial Audio Interface (SAIF), Three Stereo Pairs * Full-duplex stereo transmit and stereo receive operations * Cell phone baseband processor connection and external ADCs and DACs * Bluetooth hands-free connection (with full-duplex voice) * Analog I/O for peripheral bus breakouts * I2S, left-justified, right-justified, PCM, and non-standard formats * Customer-Programmable One-Time-Programmable (OTP) ROM through Integrated eFuse Block * Resistorless boot mode selection i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 99 i.MX28 Product Features * 128-bit boot mode crypto key * Boot mode specification of NAND characteristics for device that the customer is soldering to the board. This means no more costly delays waiting for new device support in the boot ROM. * Fully software-programmable and accessible * Flexible I/O Pins * All digital pins have drive-strength controls as described in Pin Drive Strength Selection. * Almost all non-EMI digital pins have general-purpose input/output (GPIO) mode * Offered in 289-Pin Ball Grid Array (BGA) 1.3 i.MX28 Product Features The following figure shows the block diagram of a typical system based on the i.MX28. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 100 Freescale Semiconductor, Inc. Chapter 1 Product Overview Host, Debug, Bluetooth, GPS USB PHY USB (HS/FS/LS) USB 2.0 USB Host USB 2.0 USB Device/Host 5+1 UARTs eePROM Sensors 2 x I2C UI: LED/Switches NAND Flash SLC/MLC Beep, LED, Control RGB, 68/80, BT.601/BT.656 Dual 10/100 Ethernet, IEEE1588 50MHz PLL (ENET) AXI/AHB/APB Busses ETM 4 x Timers /1 x ROT ICOLL 2x SAIF TX/RX SPDIF TX JTAG I/O Pin Multiplexer General Purpose Input/Output SD, SDIO, MMC, CE-ATA, SPI, SSI PLLs and CLKGEN 50MHz/25MHz Clock Output for Ethernet PHY GPIO / Pin Cntl UI: Rotary SPDIF Out Dual XTAL, USB ,WDog RTC, ALARM USB PHY USB (HS/FS/LS) OTP 1.25Kbit Serial Audio In/Out Class-D 32.0/32.768 kHz & 24.0 MHz Crystals USB FS/HS Host/Device USB Host Cellular Connectivity 4 x SSP 16 KB I$ High- Speed ADC 32 KB D$ Temperature DSP ARM926EJ-S 454 MHz Thermal Protection LowResolution ADC x16 Media Interface Controller ECC (20-bit) On-Chip ROM 32 K x 32 bits (128 KB) Pulse Width Modulator LCD Interface 2 x FlexCAN EMI 3-Channel DC-DC / 5-Channel LDO APBH/APBX DMA UI: Buttons, Touch-Screen 1.2V 1.5V 1.8V 3.3V 4.2V 5 V Input (USB or Wall Supply) Pixel Pipeline L2 Switch 16-bit LP-DDR1-400, DDR2-400 LV-DDR2-400 Battery Charger Data CoProcessor (Memcpy/Crypto) Ethernet MAC Controller Controller Area Network On-Chip RAM 4x8Kx 32 bits (128 KB) 1-2MHz Data E.g. Linear Image Sensor i.MX28x Rechargeable Li-ION Battery Key: - Mixed signal - Applications processing and peripherals Figure 1-1. System Block Diagram The i.MX28 features low power consumption to enable long battery life in portable applications. The integrated power management unit includes highly-efficient on-chip DC-DC converters. The power management unit also includes an intelligent battery charger and detector for Li-Ion cells and is designed to support Adaptive Voltage Control (AVC), which can reduce the system power consumption by half. AVC also allows the chip to operate at a higher peak CPU operating frequency than typical voltage control systems. The DC-DC converters and the clock generators can be reprogrammed on-thefly to trade off power versus performance dynamically. To provide the maximum application flexibility, the i.MX28 integrates a wide range of I/ O ports. It can efficiently interface to nearly any type of flash memory, serial bus, LCD or HDMI/MHL transmitter. It is also ready for advanced connectivity applications such as Bluetooth, WiFi and Cellular Data Model through its integrated 4-bit SDIO controller, high-speed (3.25 Mb/s) UARTs and secondary USB host PHY. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 101 i.MX28 Product Features An ARM926EJ-S CPU with 16K I$ & 32K D$ L1-caches and 128 Kbytes of on-chip SRAM provides the processing power needed to support advanced features such as web browsing and portable gaming (together with graphics and video processing hardware). Contact the local Freescale representative for more information on the software board support packages available for the i.MX28. Execution always begins in on-chip ROM after reset, unless overridden by the debugger. A number of devices are programmed only at initialization or application state change, such as DC-DC converter voltages, clock generator settings and so on. Certain other devices either operate in a crystal clock domain or have significant portions that operate in a crystal clock domain, for example, ADC, PLLs and so on. These devices operate on a slower speed asynchronous peripheral bus. Write posting in the ARM core, additional write post buffering in the peripheral AHB, and set/clear operations at the device registers make these operations efficient. 1.3.1 ARM9 CPU Subsystem The on-chip RISC processor core is an ARM926EJ-S CPU. This CPU implements the ARM v5TE instruction set architecture. This CPU has two instructions sets, a 32-bit instruction set used in the ARM state and a 16-bit instruction set used in the Thumb state. The core offers the choice of running in the ARM state or the Thumb state or a mix of the two states. This enables optimization for both code density and performance. ARM studies indicate that Thumb code is typically 65% the size of the equivalent ARM code, while providing 160% of the effective performance in a constrained memory bandwidth applications. The ARM CPU is described in Overview. The ARM RISC CPU is the central controller for the entire SOC, as shown in System Buses. * AHB1--Used for ARM instruction fetches * AHB2--Used for ARM data load/stores 1.3.2 System Buses The i.MX28 uses buses based on ARM's Advanced Microcontroller Bus Architecture (AMBA) for the on-chip peripherals. The AMBA2 specification (http://www.arm.com/ products/solutions/AMBA_Spec.html) outlines two bus types: AHB and APB. The AMBA3 specification (http://www.arm.com/products/solutions/axi_Spec.html) additionally outlines the AXI fabric. The three bus types are explained as follows: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 102 Freescale Semiconductor, Inc. Chapter 1 Product Overview * AXI is the highest-performance AMBA bus that supports de-coupled R/W channels, multiple outstanding transactions, and out-of-order data capability. This leads to higher performance and more efficient use of external memory. * AHB is a higher-performance bus that supports multiple masters such as the CPU and DMA controllers. * The APB is a lower-speed peripheral bus. As shown below, the i.MX28 uses a three-layer AHB, one AXI 64bit bus and two APB buses (APBH and APBX). M M S S M M S APBX Bridge/DMA APBH Bridge/DMA S S uDMA0 M S 2xMAC + Switch ETM9 Coresight M ARM 926 32K+16K (D$) (I$) 32 AHB Instr Fetch M 32 AHB M S Data R/Write 32K SRAM 32K SRAM 32K SRAM ETM9 slave DUART SPDIF TX DFLPT CAN0 DIGCTL AUART0 UTM1 DRAM_REGS CAN1 GPMI AUART1 UTM2 HSADC ICOLL AUART2 POWER OCOTP AUART3 PINCTRL AUART4 SSP0 I2C0 LRADC OCRAM Controller (word intlv) SSP1 I2C1 TIMROT SSP2 SAIF0 CLKCTRL SSP3 SAIF1 128K OCROM 64 M 32K SRAM 32 AHB0 64 M 64 M 64 M 64 S 32 32 32 64 SYNC/ ASYNCH SYNC/ ASYNCH SYNC/ ASYNCH SYNC/ ASYNCH DCP BCH PXP LCDIF PERFMON S S APBX (v3) - 24MHz uDMA1 AHB_ARB3 S (SW) M S AHB_ARB2 S (MAC1) AHB_ARB1 APB 3:1 ahb2apbs S (MAC0) M ASYNC APBH (v3) - 200MHz USB0 S Axi0 (PL301 4x2) - 200MHz USB1 PWM RTC S S S EMI - DDR2-400, LV-DDR2-400, LP-DDR1-400 16-bit Figure 1-2. i.MX28 SOC System Buses 1.3.2.1 AXI Bus Segments The AXI0 bus-segment on the i.MX28 provides several high-bandwidth/performancecritical peripherals, a tightly-coupled and efficient interface to Port-0 of the external memory controller. The peripherals are as follows: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 103 i.MX28 Product Features * DCP (Crypto/Memcpy) * Pixel Processing Pipeline (PXP) * Display Controller (LCDIF) * BCH-ECC Engine i.MX28 also contains one bus performance monitor modules (PERFMON). There is one PERFMON per AXI segment. The key features of the PERFMON are as follows: * Real-time performance statistics collection on three AXI buses * Single or multiple master transactions monitoring * Various interrupts support: address trap, latency threshold and so on * AXI protocol and out-of-order sequence support * Parameterized performance monitor for scalability 1.3.2.2 AHB Buses The AHB is the main high-performance system bus and is implemented in three layers, as follows: * Layer 1 (AHB1)--CPU instruction access to OCRAM, OCROM * Layer 2 (AHB2)--CPU data access to OCRAM, OCROM, all bridges, Ethernet, USB and DFLPT slaves * Layer 3 (AHB3)--APBH DMA, APBX DMA, Ethernet and USB masters The ARM926 instruction bus (AHB1) is a single-master layer as the ARM926 data bus (AHB2). The AHB3 has multiple masters, as shown in Figure 1-2. The ARM926 data bus connects to all the slaves in the system, including RAMs, ROMs, bridge slaves, Ethernet and USB slaves. The APB peripherals can act as AHB slaves through the AHB-APB bridge. The AHB has nine slaves: * USB slave * Ethernet slave * On-chip RAM * On-chip ROM i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 104 Freescale Semiconductor, Inc. Chapter 1 Product Overview * Default first-level page table * Two APB bridges Each layer of the AHB bus allows one active transaction at a time. A transaction is initiated by a master, controlled by an arbiter, and serviced by the slave at the corresponding address. A transaction can be as short as a single byte, or as long as a CPU cache line (32 bytes). For the USB, a transaction can be much longer, up to 512 bytes. AHB bus clock is named as the abbreviated "HCLK" or "clk_h" in the reference manual. 1.3.2.3 APB Buses There are two APB buses on the i.MX28: * APBH - The APBH (H DMA) is an AMBA2 APB system peripheral bus. This bus comprises of the APBH peripherals such as those accessed through the APBH DMA engine. The APBH peripherals are typically high-speed I/Os. * APBX - The APBX (X DMA) is an AMBA2 APB system peripheral bus. This bus is asynchronous to other system buses. This bus comprises of the APBX peripherals such as those accessed through the APBX DMA engine. The APBX peripherals are typically low speed I/Os or analog control related. The "H" in APBH denotes that the APBH is synchronous to AHB's HCLK, as compared to APBX, which runs on the crystal-derived XCLK. The APBX bus clock is named as the abbreviated "XCLK" or "clk_x" in the reference manual. The ARM926 data bus connects to all the slaves in the system, including RAMs, ROMs, bridge slaves, USB and Ethernet slaves. 1.3.3 On-Chip RAM and ROM The device includes 128 KB of on-chip RAM (OCRAM) implemented as four physical banks. It adopts a 4-port, word interleaved topology to maximize performance in a multilayer bus system. The device also includes 128 KB of on-chip mask-programmable ROM. The ROM contains initialization code written by Freescale Inc. to handle the initial boot and hardware initialization. Software in this ROM offers a large number of boot configuration options, including manufacturing boot modes for burn-in and tester operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 105 i.MX28 Product Features Other boot modes are responsible for loading the application code from off-chip into the on-chip RAM. It supports initial program loading from a number of sources: * NAND Flash devices * SD2.0/MMC4.4, 4.3,4.2 * SPI from EEPROM devices or NOR Flash devices * USB recovery mode * I2C At power-on time, the first instruction executed by the ARM core comes from this ROM. The reset boot vector is located at 0xFFFF0000. The on-chip boot code includes a firmware recovery mode. If the device fails to boot from NAND Flash, or hard drive, for example, the device will attempt to boot from a PC host connected to its USB port. The ROM boot loader can be restricted to boot only properly certified load packages. This function is enabled by an OTP bit. Additional laser fuse bits select one of the 16 customer keys, which are further modified by laser fuses. A polynomial LSFR is used to decrypt the supplied boot package. A second polynomial computes an authentication code for the load package. If the decrypted package does not compute the correct authentication code, then the boot loader will enter recovery mode and attempt to boot from the USB device. See Boot Modes for more information. Memory Map Overview shows the memory map as seen by the processor. Any blank entries indicate that nothing is mapped at that address. No accesses should be made to these addresses because the results are indeterminate. The Decode Block column indicates the decode group to which each peripheral belongs. Most peripherals reside on the APBH, APBX and Axi0 (through AHB0). 1.3.4 On-Chip One-Time-Programmable (OCOTP) ROM The device contains 1280 bits of One-Time-Programmable (OTP) ROM. The OTP is segmented into five distinct physical banks. Each bank is further divided logically into eight 32-bit words. The OTP serves several functions: * Housing of hardware and software capability bits (copied into shadow registers). * Housing of Freescale operations and unique-ID fields. * Housing the customer-programmable cryptography key. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 106 Freescale Semiconductor, Inc. Chapter 1 Product Overview * Four words for customer general use. * A 32-bit word is dedicated to controller read and write locking of the various OTP regions (copied into a shadow register). * Storage of various ROM configuration bits. * Storage of HAB data. Access to the OTP is done through a memory-mapped APBH slave interface. Each of the 32 words is memory-mapped on APBH for the purpose of reading (requires a bankopening sequence). Writing to the OTP is done through an address and data interface, where software provides the OTP word number (one of 32) and a programming mask. See OCOTP Overview for more information. 1.3.5 External Memory Controller (EMI) The i.MX28 contains a fully embedded DRAM controller solution including a multi-port AXI & AHB arbiter, control and PHY. The key features are as follows: * Support for DDR2 (1.8 V), LP-DDR1 (1.8 V) and LV-DDR2 (1.5 V) up to 200 MHz clock rate (400 MHz data-rate). * Support for up to 1024 MB with any combination of DRAMs up to two chip-enables. * Fully pipelined command, read and write data interfaces to the memory controller. * Advanced bank look-ahead features for high memory throughput. * Front-end interface to three AHB ports and one AXI port with optimized buffering for high-bandwidth capability. * A programmable register interface to control memory device parameters. * Full initialization of memory on memory controller reset. * Delay-Line for reliable data capture timing across process, temperature and all supported voltage ranges. * Integrated On Device Termination (ODT) for DDR2 applications. * Supports all levels of power modes for various device types. See Overview for more information on the EMI. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 107 i.MX28 Product Features 1.3.6 Interrupt Collector The i.MX28 contains a 128-bit vectored interrupt collector for the CPU's IRQ input and a separate non-vectored interrupt collection mechanism for the CPU's FIQ input. Each interrupt can be assigned to one of the four levels of priority. The interrupt collector supports nesting of interrupts that preempt an interrupt service routine running at a lower priority level. Each of the 128 interrupts is assigned its own 32-bit programming register and can be set for HW source IRQ, SW source IRQ or HW source FIQ. See Interrupt Collector (ICOLL) Overview for additional information. 1.3.7 Default First-Level Page Table The device contains a default first-level page table (DFLPT) implemented as an AHB slave. This device provides an economical way to present 16 Kbytes of L1 page table entry data to the ARM CPU's MMU. This page-table is connected to the AHB bus at base address 0x800C0000. The DFLPT provides 16 movable and scalable entries such that each entry can span up to128 locations. This allows the DFLPT to be used for systems with large external memories. See Default First-Level Page Table (DFLPT) Overview for additional information. 1.3.8 DMA Controller Many peripherals on the i.MX28 use direct memory access (DMA) transfers. Some peripherals, such as the USB controller, make high random accesses to the system memory for a large number of descriptor, queue heads, and packet payload transfers. This high random access nature is supported by integrating a dedicated DMA into the USB controller and connecting it directly to the high-speed AHB bus. Similarly, the DCP (crypto/memcpy), BCH-ECC and LCD controller (legacy DMA mode) devices contain their own bus masters to allow more random accesses to the system memory. Other peripherals have small number of high sequential transactions, for example the ADC streams, SPDIF transmitter, and so on. These devices share a centralized address generation and a data transfer function that allows them to share a single shared master on the AHB. As mentioned previously, there are two AMBA peripheral buses on the i.MX28: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 108 Freescale Semiconductor, Inc. Chapter 1 Product Overview * The APBH bus runs at 200 MHz clock domain. * The APBX bus runs in an independent XCLK clock domain that can be slowed down significantly for power reduction. See Overview and AHB-to-APBX Bridge Overview for more detailed information. The two bridge DMAs are controlled through linked DMA command lists. The CPU sets up the DMA command chains before starting the DMA. The DMA command chains include set-up information for a peripheral and associated DMA channel. The DMA controller reads the DMA command, writes any peripheral set up, informs the peripheral to start running and then transfers data, all without CPU intervention. The CPU can add commands to the end of a chain to keep data moving without interventions. The linked DMA command architecture off loads most of the real-time aspects of I/O control from the CPU to the DMA controller. This provides better system performance, while allowing longer interrupt latency tolerances for the CPU. 1.3.9 Clock Generation Subsystem The i.MX28 uses several different clock domains to provide clocks to various subsystems, as shown in Figure 10-1. These clocks are either derived from the 24-MHz crystal or from one of the integrated high-speed PLLs. There are three PLLs in the i.MX28: * PLL0 - 480 MHz with multiple phase-fractional and integer post-dividers used to clock the AXI and APB buses (except for APBX), I/O peripherals, multimedia/ display hardware and the external memory interface. It also acts as the primary PLL for USB0. * PLL1 - 480 MHz dedicated purely for USB1. * PLL2 - 50 MHz dedicated to the Ethernet hardware with additional post-divider for lower frequencies. See Clock Generation and Control (CLKCTRL) Overview for additional information about the system clock architecture. The system also includes a real-time clock that can use either the 24-MHz system crystal or an optional low power crystal oscillator running at either 32.768 KHz or 32.0 KHz (customer-configurable through OTP). An integrated watchdog reset timer is also available for automatic recovery from an errant code execution. See RTC Overview for more information about these features. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 109 i.MX28 Product Features 1.3.10 Power Management Unit The i.MX28 contains a sophisticated Power Management Unit (PMU), including one integrated DC-DC converter, four linear regulators, one regulated 4.2 V output and battery chargers. The PMU can operate from a Li-Ion battery using the DC-DC converters or a 5-V supply using the linear regulators and can automatically switch between them without interrupting the operation. The PMU includes circuits for battery and system voltage brownout detection, as well as the on-chip temperature, digital speed, and process monitoring. In addition, there exist safety features such as thermal shut-down and battery charge current cut-off based on the external thermistor (through LRADC). The integrated PMU converter can be used to provide programmable power for the device as well as the entire application on up to five rails: * VDD4P2 (nominal 4.2 V) -- when connected to 5 V source, can source the DC-DCs * VDDIO (nominal 3.3 V) -- DC-DC or linear-regulator from 5 V * VDDA (nominal 1.8 V) -- DC-DC or linear-regulator from VDDIO * VDD1P5 (nominal 1.5 V) -- linear-regulator from VDDIO for LVDDR2 * VDDD (nominal 1.2 V) -- DC-DC or linear-regulator from VDDA The 4.2 V regulated output also allows the programmable current limits: * Total load plus battery charge current (5 V limit) * Battery charge current * Load current -- for both on-chip and off-chip circuits The 4.2 V circuit is capable of adjusting distribution of current supply between the load and the battery-charger depending on the programmed current-limits and the load conditions. For example, when the battery charging exceeds the 5 V current limit, the 4.2 V regulator steals the current from the battery-charger circuit and diverts it to the load circuit. The converter can be configured to operate from the standard Li-Ion battery up to 4.2 V. These converters use off-chip reactive components (L/C) in a pulse-width or frequency-modulated DC-DC converter. The real-time clock includes an alarm function that can be used to wake-up the DC-DC converters, which then wakes up the rest of the system. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 110 Freescale Semiconductor, Inc. Chapter 1 Product Overview 1.3.11 Ethernet Interfaces The i.MX28 includes extensive Ethernet connectivity support. Ethernet controller includes two programmable 10/100 IEEE 802.3 Ethernet MACs. There is one time stamping module for each MAC to support Ethernet applications requiring precise timing references for incoming and outgoing frames to implement a distributed time synchronization protocol such as the IEEE 1588. In addition to this, a hardware 3-port switch is supported for either redundancy (dual cables) or daisy-chaining (packet forwarding) to support automatic extension of control networks. Two unified DMA blocks allows backward compatibility to legacy FEC interface (note that all uDMA programming is performed through the MAC0 and MAC1 register interfaces). 1.3.12 CAN Interfaces The i.MX28 includes dual FlexCAN2 controllers which are compatible with the CAN 2.0B protocol specification [Ref. 1]. The CAN Protocol Interface (CPI) manages the serial communication on the CAN bus, requesting RAM access for receiving and transmitting message frames, validating received messages and performing error handling. The Message Buffer Management (MBM) handles Message Buffer selection for reception and transmission, taking care of arbitration and ID matching algorithms. 1.3.13 USB Interfaces The i.MX28 includes two high-speed Universal Serial Bus (USB) version 2.0 controllers and integrated USB Transceiver Macrocell Interface (UTMI) PHYs. The i.MX28 device interface can be attached to USB 2.0 hosts and hubs running in the USB 2.0 high-speed mode at 480 Mbits per second. It can be attached to USB 2.0 full-speed interfaces at 12 Mbits per second. Note that a dual-device configuration is not supported. The USB controllers and integrated PHYs support high-speed Host modes for peer-topeer file interchange. The USB controller can also be configured as a high-speed host. The USB subsystem is designed to make efficient use of system resources within the i.MX28. It contains a random-access DMA engine that reduces the interrupt load on the system and reduces the total bus bandwidth that must be dedicated to service the five onchip physical endpoints. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 111 i.MX28 Product Features Each USB is a dynamically configured port that can support up to seven RX and seven TX endpoints besides EP0, each of which may be configured for bulk, interrupt, or isochronous transfers. The USB configuration information is read from on-chip memory through the USB controller's DMA. See Overview and USB PHY Overview for more information. 1.3.14 General-Purpose Media Interface (GPMI) The chip includes a general-purpose media interface (GPMI) controller that supports NAND devices (all packages). The NAND Flash interface provides a state machine that provides all the logic necessary to perform DMA functions between on-chip or off-chip RAM and up to eight NAND Flash devices. The controller and DMA are sophisticated enough to manage the sharing of a single 8-bit wide data bus among eight NAND devices, without detailed CPU intervention. This allows the i.MX28 to provide unprecedented levels of NAND performance. The general-purpose media interface can be described as two fairly independent devices in one. The three operating modes are integrated into one overall state machine that can freely intermix cycles to different device types on the media interface. There are eight chip selects on the media interface. Each chip select can be programmed to have a different type device installed. The GPMI pin timings are based on a dedicated clock divider from PLL0, allowing the CPU clock divider to change without affecting the GPMI. See General-Purpose Media Interface Overview for more information. 1.3.15 Hardware Acceleration for ECC for Robust External Storage The hardware ECC accelerator provides a forward error-correction function for improving the reliability of various storage media that may be attached to the i.MX28. Modern high-density NAND Flash devices presume the existence of forward errorcorrection algorithms to correct some soft and/or hard bit errors within the device, allowing higher device yields and, therefore, lower NAND device costs. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 112 Freescale Semiconductor, Inc. Chapter 1 Product Overview The i.MX28 contains an Error Correction Code (ECC) hardware engine implementing the Bose Ray-Choudhury Hocquenghem algorithm for up to 20 bits of correction. The ECC engine is tightly coupled to the GPMI and has a dedicated programming model and a DMA structure. 1.3.15.1 Bose Ray-Choudhury Hocquenghem ECC Engine The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is capable of correcting from 2 to 20 single bit errors within a block of data not larger than about 900 bytes (512 bytes is typical) in applications such as protecting data and resources stored on modern NAND Flash devices. The correction level in the BCH block is programmable to provide flexibility for varying applications and configurations of flash page size. The design can be programmed to encode protection of 2, 4, 8, 10, 12, 14, 16, 18, or 20 bit errors when writing into the flash and to correct the corresponding number of errors on decode. The correction level when decoding MUST be programmed to the same correction level as that was used during the encode phase. BCH-codes are a type of block-code, which implies that all error-correction is performed over a block of N-symbols. The BCH operation will be performed over GF (213 = 8192), which is the Galois Field consisting of 8191 one-bit symbols. BCH encoding (or encode for any block-code) can be performed by either of the two algorithms: systematic encoding or multiplicative encoding. Systematic encoding is the process of reading all the symbols which constitute a block. These symbols are divided continuously by the generator polynomial for the GF (8192) and the resulting t parity symbols are appended to the block to create a BCH codeword (where t is the number of correctable bits). The BCH sits on the AXI fabric with close coupling to both the GPMI and the external memory controller. See Overview for more information. 1.3.16 Data Co-Processor (DCP)--Memory Copy, Crypto The device contains a data co-processor consisting of four virtual channels. Each channel is essentially a memory-to-memory copy engine. The linked list control structure can be used to move the byte-aligned blocks of data from a source to the destination. In the process of copying from one place to another, the DCP can be programmed to encrypt or decrypt the block using AES-128 in one of the several chaining modes. An SHA-1 or SHA256 hash can be calculated as part of the memory-copy operation. See Data Co-Processor (DCP) Overview for more information. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 113 i.MX28 Product Features 1.3.17 I2C Interface The i.MX28 contains two two-wire SMB/I2C bus interfaces. Each interface can act either as a slave or a master on the SMB interface. The on-chip ROM supports boot operations from I2C mastered EEPROMs, as well as slave I2C boot mode. I2C flexibly supports three transaction modes: DMA, PIO and PIO queue modes. See I2C Overview for more information. 1.3.18 General-Purpose Input/Output (GPIO) The i.MX28 contains 124 GPIO pins in the 289-pin BGA package. Most digital pins (except for EMI pins) that are available for specific functions are also available as GPIO pins if they are not otherwise used in a particular application. All GPIO pins support both 1.8V and 3.3V VDDIO. See Pin Control and GPIO Overview for more information. 1.3.19 Display and Capture Processing In order to support a variety of multimedia-rich use-cases, the i.MX28 contains a powerful and flexible display and capture sub-system comprised of the following components: * Pixel Processing Pipeline (PXP) * Display Controller (LCDIF) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 114 Freescale Semiconductor, Inc. Chapter 1 Product Overview 8 x Overlays RGB (S1) Video YUV (S0) PXP Block CSC + Scale Colorkey / Alpha-Blend Rotation LCDIF Block Display Out (RGB, System, BT.656) To LCD Pins Figure 1-3. i.MX28 Display System 1.3.19.1 Display Controllers / LCD Interfaces (LCDIF) The device contains the LCDIF display controller module which connects to the AXI bus. Some of the key features of the LCDIFs are as follows: * Very flexible display support which allows for connection to a wide variety of display interfaces. * AXI master on the AXI bus segment with large efficient request sizes and support for outstanding transfer requests. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 115 i.MX28 Product Features * Ability to drive 24-bit RGB/DOTCK displays up to WVGA at 60 Hz. High robustness guaranteed by 512-pixel FIFO with under-run recovery. * Support for full 24-bit system mode (8080/6080/VSYNC/WSYNC). * ITU-R/BT.656 compliant D1 digital video output mode with on-the-fly RGB to YCbCr color-space-conversion. This output mode is suitable for driving the external TV-Encoder. * Support for a wide variety of input and output formats that allows for conversion between input and output (for example, RGB565 input to RGB888 output). Also support for packed byte formats. The APB DMA mode still exists for backward compatibility, but is not recommended for driving displays larger than QVGA (320 x 240). See LCD Interface (LCDIF) Overview for more information. 1.3.19.2 Pixel Processing Pipeline (PXP) The PXP performs all necessary post display frame pre-processing in hardware with minimal CPU overhead. The PXP operation and features can be described as follows: * The PXP can be programmed to operate in either 8 x 8 or 16 x 16 block modes. When using 32-bit memories with the EMI, 16 x16 block mode is recommended to allow for efficient memory access. Because the PXP accesses the blocks by requesting a line of block, a 16-pixel fetch (one line of a block) will make full use of a 16-byte burst on the EMI. * The background image (for example, decoded video frames) is read from an external memory (single-plane YUV, dual-plane Y/UV and three plane Y/U/V inter-leaved source buffer formats are supported) into the internal buffers as either 8 x 8 or 16 x16 pixel blocks. These buffers are then fed into a color-space converter (for example, YUV to RGB) followed by the scaling engine which utilizes an advanced bi-linear weighted scaling algorithm. The scaling operation is defined in terms of the output image (through programmable offsets and cropping registers). The output of the scaler is fed into yet another internal buffer called S0. If the background image is already in the RGB color-space, it is assumed to be scaled appropriately for the required output format and can thus be read directly into the internal S0 buffer. In order to maintain the efficient use of an external memory, only the relevant (visible) portion of the background image is fetched. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 116 Freescale Semiconductor, Inc. Chapter 1 Product Overview * The scaled RGB image (in the internal S0 buffer) can be blended with up to eight programmable overlays. The co-ordinates of the overlays can once again be described in terms of the resultant output image. Each overlay can have either a global programmable opacity or a per-pixel resolution if constructed with RGB color-space. In addition to this, each overlay can have a relative priority level such that when constructing the output image, the PXP only fetches the visible overlay in the current 8 x 8 or 16 x16 block. The overlays are fetched into the internal S1 buffer. Alpha blending is performed on the S0 and S1 buffers to generate the blended output into the internal S3 buffer. Other operations such as BITBLT and colorkeying can also be performed at this stage. * The final stage of the PXP operation is the rotator which can perform flips and 90, 180 and 270 rotations. The rotator operates on the 8 x 8 or 16 x16 pixel blocks in the S3 buffer to maximize external memory fetch efficiency. It writes 8 x 8 or 16 x16 blocks to the external memory in this final stage. * The PXP supports scaling down up to 4:1 in single-pass mode. This is useful for scaling 720p decoded content to a QVGA display. The PXP can also be used to further scale down images using a multi-pass approach which is enabled by the ability of the PXP to write YUV output. See Pixel Pipeling (PXP) Overview for more information on the PXP. 1.3.20 SPDIF Transmitter The device includes a Sony-Phillips Digital Interface Format (SPDIF) transmitter. It includes independent sample-rate conversion hardware so that the A/D, D/A and SPDIF can run simultaneously. The SPDIF has a dedicated DMA channel. The SPDIF has its own clock divider from the PLL. See FlexCAN Introduction for more information. 1.3.21 Dual Serial Audio Interfaces The i.MX28 SOC includes two Serial Audio Interfaces (SAIF), each with three stereo pairs. The pin multiplexing scheme for i.MX28 allows a stereo transmitter and a stereo receiver to be connected to external devices, either D/A and A/D converters or to a host processor, such as a cell phone or BlueTooth controller. See Serial Audio Interface (SAIF) Overview for more information. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 117 i.MX28 Product Features 1.3.22 Rotary Decoder An automatic rotary decoder function is integrated into the chip. Two digital inputs are monitored to determine which is leading and by how much. In addition, the hardware automatically determines the period for rotary inputs. See Timers and Rotary Decoder (TIMROT) Overview for more information. 1.3.23 UARTs There are six UARTs (similar to 16550 UART) provided; five for application use and one for debug. The application UARTs are high-speed devices capable of running up to 3.25 Mbits per second with 16-byte receive and transmit FIFOs. The application UARTs support DMA and flow control (RTS/CTS). The debug UART does not use DMA channels. See Application UART Overview and Debug UART Overview for more information. 1.3.24 Low-Resolution ADC, Touch-Screen Interface and Temperature Sensor The LRADC provides 16 physical channels of 12-bit resolution for analog-to-digital conversion. Only eight "virtual" channels can be used at one time, but those eight channels can be mapped to any of the 16 physical channels. Some physical channels have dedicated inputs: * Channel 15--VDD5V * Channel 14--Bandgap reference * Channel 13--VDDD * Channel 12--VDDA * Channel 11--VTH * Channel 10--Sample VDDIO * Channel 8 and 9--Internal temperature sense input * Channel 7--Battery i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 118 Freescale Semiconductor, Inc. Chapter 1 Product Overview The USB_DN/DP inputs can only be sampled with the LRADC in non-USB mode (see HW_USBPHY_CTRL_DATA_ON_LRADC). The remaining seven channels are available for other uses and can be used for resistive button sense, touch-screens or other analog input. Channels 0 and 1 have integrated drivers for external temperature monitor thermistors. Channels 2-6 have integrated drivers for resistive touch-screens. The LRADC provides typical performance of 12-bit no-missing-codes, 9-bit SNR, and 1% absolute accuracy (limited by the bandgap reference). See LRADC Overview for more information. 1.3.25 High Speed ADC (HSADC) Controller The high-speed ADC module is designed for driving the linear image scanner sensor (for example, TOSHIBA TCD1304DG linear image scanner sensor). It can also support some other general user cases which need to sample analog source with up to 2 Msps data rate and then move the sample data to the external memory. The high-speed ADC module integrates an 12-bit analog ADC module. This analog ADC module can support up to 2 Msps sample rate. In order to improve the flexibility, the high-speed ADC module can co-work with PWM module which can generate driving signals of external device such as the linear image scanner sensor. The PWM can also generate trigger signal which is synchronous with high-speed ADC module to start the conversion of ADC. An APBHDMA channel is connected to the high-speed ADC module to move the sample data from the asynchronous FIFO inside the high-speed ADC module to the external memory. 1.3.26 Pulse Width Modulator (PWM) Controller The device contains eight PWM output controllers that can be used in place of GPIO pins. Applications include LED brightness control, HSADC signal driving and highvoltage generators for electroluminescent lamp (EL) display backlights. Independent output control of each phase allows 0, 1, or high impedance to be independently selected for the active and inactive phases. Individual outputs can be run in lock step with guaranteed non-overlapping portions for differential drive applications. See Pulse Width Modulator (PWM) Overview for more information. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 119 i.MX28 Product Features i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 120 Freescale Semiconductor, Inc. Chapter 2 ARM CPU Complex 2.1 Overview This chapter describes the ARM CPU included on the i.MX28 and includes sections on the processor core, the JTAG debugger, and the embedded trace macrocell (ETM) interface. 2.2 ARM 926 Processor Core The on-chip Reduced Instruction Set Computer (RISC) processor core is an ARM926EJS CPU. This CPU implements the ARM v5TE instruction set architecture, which includes the enhanced DSP instructions. The ARM9EJ-S has two instruction sets: a 32-bit instruction set used in the ARM state and a 16-bit instruction set used in the Thumb state. The core offers the choice of running in the ARM state or the Thumb state or a mix of the two. This enables optimization for both code density and performance. ARM studies indicate that Thumb code is typically 65% the size of an equivalent ARM code, while providing 160% of the effective performance in constrained memory bandwidth applications. A block diagram of the ARM926EJ-S core is shown in Figure 2-1. See http://www.arm.com/documentation/ARMProcessor_Cores/index.html to download the following ARM documentation on the ARM926EJ-S core: * ARM926EJ-S Technical Reference Manual, DDI0198D * ARM926EJ-S Development Chip Reference Manual, DDI0287A i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 121 ARM 926 Processor Core The ARM9 core has a total of 37 programmer-visible registers, including 31 generalpurpose 32-bit registers, six 32-bit status registers, and a 32-bit program counter, as shown in Figure 2-2. In ARM state, 16 general-purpose registers and one or two status registers are accessible at any one time. In privileged modes, mode-specific banked registers become available. The ARM state register set contains 16 directly addressable registers, r0 through r15. An additional register, the Current Program Status Register (CPSR), contains condition code flags and the current mode bits. Registers r0-r13 are general-purpose registers used to hold data and address values, with r13 being used as a stack pointer. Register r14 is used as the subroutine link register (lr) to hold the return address. Register r15 holds the program counter (PC). The Thumb state register set is a subset of the ARM register set. The programmer has access to eight general-purpose registers, r0-r7, the PC (ARM r15), the stack pointer (ARM r13), the link register (ARM r14), and the CPSR. Exceptions arise whenever the normal flow of program execution has to be temporarily suspended, for example, to service an interrupt from a peripheral. Before attempting to handle an exception, the ARM core preserves the current processor state, so that the original program can resume when the handler is finished. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 122 Freescale Semiconductor, Inc. Chapter 2 ARM CPU Complex Unused Unused ARM926EJ-S Instruction TCM Interface Embedded Trace Macrocell (ETM) Interface Instruction Cache (16Kbytes) ARM9EJ-S Core MMU Data TCM Interface Data Cache (32Kbytes ) Write Buffer MMU Control Logic and Bus Interface Unit VINITHI IRQ AMBA AHB Interface FIQ Interrupts Integrated Coprocessor AHB1 AMBA AHB Interface AHB2 Figure 2-1. ARM926 RISC Processor Core The following exceptions are recognized by the core: * SWI--Software interrupt * UNDEF--Undefined instruction * PABT--Instruction prefetch abort * FIQ--Fast peripheral interrupt i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 123 JTAG Debugger * IRQ--Normal peripheral interrupt * DABT--Data abort * RESET--Reset * BKPT--Breakpoint The vector table pointing to these interrupts can be located at physical address 0x00000000 or 0xFFFF0000. The i.MX28 maps its 64-Kbyte on-chip ROM to the address 0xFFFF0000 to 0xFFFFFFFF. The core is hardwired to use the high address vector table at hard reset (core port VINITHI =1). The ARM 926 core includes a 16-Kbyte instruction cache and a 32-Kbyte data cache and has two master interfaces to the AMBA AHB, as shown below. Thumb mode high registers Thumb mode low registers The i.MX28 always operates in a little-endian mode. r0 r1 r2 r3 r4 r5 r6 r7 r8 r8 r9 r9 r10 r10 r11 r11 r12 r12 r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) spsr spsr spsr spsr spsr FIQ IRQ ABORT SVC undef r15 (pc) cpsr USER Figure 2-2. ARM Programmable Registers 2.3 JTAG Debugger The TAP controller of the ARM core in the i.MX28 performs the standard debugger instructions. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 124 Freescale Semiconductor, Inc. Chapter 2 ARM CPU Complex 2.3.1 JTAG READ ARM ID (TAP) The TAP controller returns the following 32-bit data value in response to a JTAG READ ID instruction: 0x079264F3 when the pin DEBUG=1 (JTAG interface works for ARM debugging). 2.3.2 JTAG Hardware Reset The JTAG reset instruction can be accomplished by writing 0xDEADC0DE to ETM address 0x70. The ETM is on scan chain 6. The bitstream is 0xF0DEADC0DE. The digital wide reset does not affect the DC-DC converters or the contents of the persistent registers in the analog side of the RTC. 2.3.3 JTAG Interaction with CPUCLK Because the JTAG clock is sampled from the processor clock CPUCLK, there are cases in which the behavior of CPUCLK affects the ability to make use of JTAG. Specifically, the JTAG block will not function as expected if: * CPUCLK is stalled due to an interrupt * CPUCLK is less than 3x the JTAG clock * CPUCLK is disabled for any reason 2.4 Embedded Trace Macrocell (ETM) Interface The i.MX28 includes a stand-alone ARM CoreSight Embedded Trace Macrocell, ETM9CSSingle, which provides a instruction trace and a data trace for the ARM9 microprocessor. For more details, see the CoreSight ETM9 Technical Reference Manual. Also, see the pin list in the data sheet for pinout information. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 125 Embedded Trace Macrocell (ETM) Interface i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 126 Freescale Semiconductor, Inc. Chapter 3 Default First-level Page Table (DFLPT) 3.1 Default First-Level Page Table (DFLPT) Overview The DFLPT provides a unique method of implementing the ARM MMU first-level page table (L1PT) using a hardware-based approach. The ARM MMU L1PT must consist of 4096 page-table entries (PTE), each of which maps to a 1-Mbyte section of the 4-Gbyte system memory. Each PTE consists of a 32-bit descriptor, such that 16 Kbytes of memory is required to implement the L1PT. Using 16 Kbytes of system memory for the L1PT can be an issue for memory-constrained embedded systems (especially those without SDRAM). The DFLPT implements a very sparse L1PT in hardware, as shown in Figure 3-1. This is achieved by having sixteen movable and expandable page table entries (MPTE) that are fully programmable and one semi-programmable fixed PTE. Any of the sixteen MPTEs can be bound to 4095 of the 4096 sections using sixteen locator registers in the DIGCTL block (Default First Level Page Table Movable PTE Locator 0 (HW_DIGCTL_MPTE0_LOC)). This implementation, although sparse, is very useful in low-memory applications. For small SDRAM systems (where the L1PT would typically be placed in SDRAM), the DFLPT provides significant speed and power advantages (as well as saving 16 Kbytes). For larger DRAM system, it provides a performance advantage. Large memory systems are accommodated through the spanning option (for example, in cases such as multimedia buffers, large amounts of memory are typically marked with the same attributes, and the memory is contiguous physically). Using the DFLPT, a level-one descriptor fetch takes two HCLK cycles to complete. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 127 Operation OCROM ARM Core Slave OCRAM Data Master Slave EMI Slave AHB Layer 2 Slave USB Slave Default First-Level Page Table Slave APBH Bridge Slave APBX Bridge Figure 3-1. Default First-Level Page Table (DFLPT) Block Diagram 3.2 Operation The DFLPT provides the following features as part of the memory management within the i.MX28 embedded software system: * 16-Kbyte AHB slave located at addresses 0x800C_0000-0x800C_3FFF supports the required 4K L1 PTEs. To use the DFLPT, point the ARM TTB to 0x800C_0000. * Only 32-bit word accesses are supported. * All AHB burst types are supported. * Each access has a fixed 1-cycle AHB wait state. * Bus errors are supported when accessing an unbound PTE (that is, an address not bound to an MPTE or spanned MPTE). * Sixteen fully programmable (value and location) page table entries. All 32-bits are programmable. The location/binding of each MPTE is determined through the HW_DIGCTL_MPTEn_LOC register fields in the DIGCTL module. The span (1-128 MB) of MPTE is determined through the HW_DIGCTL_MPTEn_SPAN register fields in the DIGCTL module. In addition, each of the sixteen entries can be disabled through HW_DIGCTL_MPTEn_DIS if less than sixteen entries are required (this avoids the need to bind an entry to some unused area of physical memory): * When an entry is disabled (through HW_DIGCTL_MPTEn_DIS), it cannot be bound, so programming its HW_DIGCTL_MPTEn_LOC field has no effect. This means that another entry which is not disabled (HW_DIGCTL_MPTEn_DIS=0) can have the same value for HW_DIGCTL_MPTEn_LOC as the disabled entry. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 128 Freescale Semiconductor, Inc. Chapter 3 Default First-level Page Table (DFLPT) * A read from an unbound PTE returns 0x0000_0000. When the MMU is enabled, this results in a section translation fault if the read is the result of a page-walk. * When using the span feature, the entire span is bound to the MPTE. This means that up to 128 32-bit word locations/addresses can be bound to any MPTE (see below for a more detailed explanation). * A write to an un-bound PTE shall result in a slave error, which shall in turn result in an ARM data-abort. Note that when writing to a PTE encompassed in a span, the descriptor will apply to the span of the MPTE with the exception of the base-address, which only applies to the base MPTE (at location LOC). Subsequent base addresses within a span are generated linearly from this LOC value (see below). * Each MPTE has a reset value of 0x0000_0000. * One fixed PTE at location 2048 covers the i.MX28 PIO and register space. The location is fixed as virtual = real, is non-cacheable, and includes programmable bufferable, domain, and AP fields. * Each MPTE requires a location register, such that it can be mapped to any of the 4K L1 section descriptors. In addition, each of these location registers can be programmed to be bound to up to 128 locations each (covering up to 128 MB of physical each). These location registers (HW_DIGCTL_MPTEn where n = 0...15) are located in the DIGCTL module. Refer to Default First Level Page Table Movable PTE Locator 0 (HW_DIGCTL_MPTE0_LOC) for a description of the MPTEn_LOC registers. * Each HW_DIGCTL_MPTEn_LOC must be programmed with a 12-bit value that corresponds to one of the 4K section entries. Once programmed, the AHB physical address of the MPTE is determined as: 0x800C_0000 + (HW_DIGCTL_MPTEn_LOC << 2) HW_DIGCTL_MPTEn_LOC = 0x000 - 0xFFF * The reset state of each HW_DIGCTL_MPTEn_LOC register is n (n = 0...15), for example, HW_DIGCTL_MPTE3_LOC has reset value of 0x0000_0003. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 129 Operation * None of the MPTEn_LOC registers should be programmed to 0x800 (2048). This corresponds to the fixed entry that covers the i.MX28 register space. * No checking/status is given for incorrect programming (for example, overlap). If multiple MPTEs are programmed to the same address in the DFLPT, the behavior is non-deterministic. The only exception is that all but one of the entries has DIS=1 set (disabled). * The spanning feature can be enabled by adjusting the value of HW_DIGCTL_MPTEn_SPAN. This is a 3-bit value which determines the size of the span as 2^SPAN. This means that any access to the L1PT within the span will have the following properties: * The span allows any MPTE to bind to a range of MPTEn_LOC * 4 through to (MPTEn_LOC + (2^SPAN - 1) ) * 4, where SPAN is an integer from 0 to 7. * Because spanning binds a single MPTE to multiple L1PT entries, the DFLPT must generate unique base addresses for each spanned entry, otherwise each 1 MB section would map to the same physical section. The DFLPT achieves this by assuming contiguous 1 MB section addressing for all sections covered within a span. 3.2.1 Top-Level Symbol and Functional Overview The DFLPT connects to the AHB as shown in Figure 3-2. Note that due to the internal pipelining (single wait-state), the bus interfaces have little or no combinatorial logic. The read and address paths connect directly to the registers. The write-path connects to the register bank through one level 1-hot muxing. All address and locator decodes are also performed using 1-hot logic. Offset address generated from the AHB address (for purposes of generating spanned base addresses) use a registered version of the AHB address. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 130 Freescale Semiconductor, Inc. Chapter 3 Default First-level Page Table (DFLPT) APBH APBH Bridge MPTEn_LOC / SPAN DIGCTL MPTEn_DIS DFLPT ahb_addr, ahb_trans, ahb_write, ahb_ready_in Locate/Span Logic Reg Select Movable PTE regs (MPTE0-15) + Span base-addr Gen ahb_wdata AHB Layer 2 (ARM D$) ahb_resp, ahb_ready_out State Logic ahb_rdata Entry 2048 (PIO) 17:1 Read data mux Figure 3-2. DFLPT System Level Block Diagram 3.2.2 Memory Map The virtual memory view of the DFLPT can be seen in the figure below. This example shows how a MPTE can be spanned and how it will appear to the ARM MMU. In this example, MPTE0 is set as follows: * HW_DIGCTL_MPTE0_DIS = 0x0 * HW_DIGCTL_MPTE0_SPAN = 0x2 * HW_DIGCTL_MPTE0_LOC = 0x700 * TTB (0xBASE) = 0x800C_0000 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 131 Operation Based on these settings, MPTE0 spans 22=4 entries in the page table. Because only one LOC value is specified, the DFLPT must generate section base-address values for each location in the span as a linear offset to the base LOC. Even though this represents some constraint in the view of virtual-to-physical memory mapping, it is quite common in an embedded system to have large chunks of virtual memory to be contiguous. Virtual Address 0xFFFXXXXX @0x800C3FFC FLPT Address PTE 0x801-0xFFF available for MPTE1-15 PTE 2048 (non-cacheable, V==R) PTE 0x900-0xFFF available for MPTE1-15 0x703XXXXX @0x800C1C0C 0x702XXXXX @0x800C1C08 0x701XXXXX @0x800C1C04 0x700XXXXX @0x800C1C00 AR926 MMU Translation Table Base Register Base-address=0x703 Base-address=0x702 Base-address=0x701 MPTE0_LOC=0x700, MPTE0_SPAN=2 PIO Automatically return Base-address = LOC + 3, DFLPT returns value (MPTE0 + (3 << 20)) Automatically return Base-address = LOC + 2, DFLPT returns value (MPTE0 + (2 << 20)) Automatically return Base-address = LOC + 1, DFLPT returns value (MPTE0 + (1 << 20)) MPTE0 with base of 0x700 and span of 2^SPAN = 4, Returns Base-address = LOC, DFLPT returns value MPTE0 PTE 0x000-0x6FF available for MPTE1-15 @0x800C0000 0x000XXXXX Figure 3-3. DFLPT Virtual Memory Map The table below lists the page-table entries available in the DFLPT. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 132 Freescale Semiconductor, Inc. Chapter 3 Default First-level Page Table (DFLPT) Table 3-1. Default First-Level Page Table REGISTE R NAME ADDRESS DESCRIPTION MPTE15 0x800C0000 + (HW_DIGCTL_MPTE15_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE15_LOC + 2^SPAN)<<2) Moveable PTE15 + ((Address[13:2] HW_DIGCTL_MPTE15_LOC) << 20) MPTE14 0x800C0000 + (HW_DIGCTL_MPTE14_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE14_LOC + 2^SPAN)<<2) Moveable PTE14 + ((Address[13:2] HW_DIGCTL_MPTE14_LOC) << 20) MPTE13 0x800C0000 + (HW_DIGCTL_MPTE13_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE13_LOC + 2^SPAN)<<2) Moveable PTE13 + ((Address[13:2] HW_DIGCTL_MPTE13_LOC) << 20) MPTE12 0x800C0000 + (HW_DIGCTL_MPTE12_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE12_LOC + 2^SPAN)<<2) Moveable PTE12 + ((Address[13:2] HW_DIGCTL_MPTE12_LOC) << 20) MPTE11 0x800C0000 + (HW_DIGCTL_MPTE11_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE11_LOC + 2^SPAN)<<2) Moveable PTE11 + ((Address[13:2] HW_DIGCTL_MPTE11_LOC) << 20) MPTE10 0x800C0000 + (HW_DIGCTL_MPTE10_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE10_LOC + 2^SPAN)<<2) Moveable PTE10 + ((Address[13:2] HW_DIGCTL_MPTE10_LOC) << 20) MPTE9 0x800C0000 + (HW_DIGCTL_MPTE9_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE9_LOC + 2^SPAN)<<2) Moveable PTE9 + ((Address[13:2] HW_DIGCTL_MPTE9_LOC) << 20) MPTE8 0x800C0000 + (HW_DIGCTL_MPTE8_LOC <<2) <= Address< 0x800C0000 + ((HW_DIGCTL_MPTE8_LOC + 2^SPAN)<<2) Moveable PTE8 + ((Address[13:2] HW_DIGCTL_MPTE8_LOC) << 20) MPTE7 0x800C0000 + (HW_DIGCTL_MPTE7_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE7_LOC + 2^SPAN)<<2) Moveable PTE7 + ((Address[13:2] HW_DIGCTL_MPTE7_LOC) << 20) MPTE6 0x800C0000 + (HW_DIGCTL_MPTE6_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE6_LOC + 2^SPAN)<<2) Moveable PTE6 + ((Address[13:2] HW_DIGCTL_MPTE6_LOC) << 20) MPTE5 0x800C0000 + (HW_DIGCTL_MPTE5_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE5_LOC + 2^SPAN)<<2) Moveable PTE5 + ((Address[13:2] HW_DIGCTL_MPTE5_LOC) << 20) MPTE4 0x800C0000 + (HW_DIGCTL_MPTE4_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE4_LOC + 2^SPAN)<<2) Moveable PTE4 + ((Address[13:2] HW_DIGCTL_MPTE4_LOC) << 20) MPTE3 0x800C0000 + (HW_DIGCTL_MPTE3_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE3_LOC + 2^SPAN)<<2) Moveable PTE3 + ((Address[13:2] HW_DIGCTL_MPTE3_LOC) << 20) MPTE2 0x800C0000 + (HW_DIGCTL_MPTE2_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE2_LOC + 2^SPAN)<<2) Moveable PTE2 + ((Address[13:2] HW_DIGCTL_MPTE2_LOC) << 20) MPTE1 0x800C0000 + (HW_DIGCTL_MPTE1_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE1_LOC + 2^SPAN)<<2) Moveable PTE1 + ((Address[13:2] HW_DIGCTL_MPTE1_LOC) << 20) MPTE0 0x800C0000 + (HW_DIGCTL_MPTE0_LOC <<2) <= Address < 0x800C0000 + ((HW_DIGCTL_MPTE0_LOC + 2^SPAN)<<2) Moveable PTE0 + ((Address[13:2] HW_DIGCTL_MPTE0_LOC) << 20) Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 133 Operation Table 3-1. Default First-Level Page Table (continued) REGISTE R NAME ADDRESS DESCRIPTION PTE_2048 0x800C2000 PTE 2048 is semi-programmable, as shown in Default First-Level Page Table PIO Register Map Entry 2048. 3.2.3 Default First-Level Page Table PIO Register Map Entry 2048 The 1-Mbyte PIO region at physical address 0x800XXXXX is mapped as "virtual equal real" by the default first-level page table PTE_2048, as shown below. DFLPT_PTE_2048 0x800C2000 Table 3-2. First-Level Page Table Entry 2048 (0x80000000-0x800FFFFF) at 0x800C2000 31 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 Virtual == Real Section, i.e., 0x80000 1 6 1 5 1 4 1 3 1 2 1 1 1 0 AP 0 9 0 8 0 0 7 0 6 DOMAIN 0 5 0 4 0 3 0 2 1 C B 0 1 0 0 10 Table 3-3. PTE 2048 Bit Field Descriptions BITS Label RW reset Definition 31:12 POINTER RO 0x80000 This section points to 0x80000000 and is always available. 11:10 AP RW 0x3 Initially set to 0x3 for allowing ALL accesses. Set to other values as desired. 9 ALWAYS_ZERO RO 0x0 Always reads back a 0. 8:5 DOMAIN RW 0x0 Set as desired. 4 ALWAYS_ONE RO 0x1 Always reads back a 1, as required in ARM926 Technical Reference Manual. 3 CACHEABLE RO 0x0 Always reads back a 0 (uncached). 2 BUFFERABLE RW 0x0 Always reads back a 0 (unbuffered). 1:0 FIRST_LEVEL RO 0x2 Always reads back 0x2 for section descriptor. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 134 Freescale Semiconductor, Inc. Chapter 4 Memory Map 4.1 Memory Map Overview The following table shows the memory map as seen by the processor. Any blank entries indicate that nothing is mapped at that address. No accesses should be made to these addresses since the results are indeterminate. The Decode Block column indicates the decode group to which each peripheral belongs. Most peripherals reside on the APBH or APBX peripheral buses. Table 4-1. Address Map for i.MX28 DECODE BLOCK AHB APBH DEVICE MNEMONIC START ADDRESS END ADDRESS SIZE On-Chip RAM OCRAM 0x00000000 0x0001FFFF 128K B On-Chip RAM alias OCRAM 0x00020000 0x7FFFFFFF External Memory EMI 0x40000000 0x7FFFFFFF 1GB Interrupt Controller ICOLL 0x80000000 0x80001FFF 8KB High Resolution ADC HSADC 0x80002000 0x80003FFF 8KB APBH DMA APBH 0x80004000 0x80005FFF 8KB Performance Monitor PERFMON 0x80006000 0x800067FF 2KB 0x80006800 0x80006FFF 2KB 0x80007000 0x800077FF 2KB 0x80007800 0x80007FFF 2KB 0x80008000 0x80009FFF 8KB BCH ECC BCH 0x8000A000 0x8000BFFF 8KB General Purpose Media Interface GPMI 0x8000C000 0x8000DFFF 8KB 0x8000E000 0x8000FFFF 8KB Sync Serial Port 0 SSP0 0x80010000 0x80011FFF 8KB Sync Serial Port 1 SSP1 0x80012000 0x80013FFF 8KB Sync Serial Port 2 SSP2 0x80014000 0x80015FFF 8KB Sync Serial Port 3 SSP3 0x80016000 0x80017FFF 8KB Pin Control PINCTRL 0x80018000 0x80019FFF 8KB Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 135 Memory Map Overview Table 4-1. Address Map for i.MX28 (continued) DECODE BLOCK DEVICE Digital Control APBX MNEMONIC DIGCTL START ADDRESS END ADDRESS SIZE 0x8001A000 0x8001BFFF 8KB 0x8001C000 0x8001DFFF 8KB 0x8001E000 0x8001FFFF 8KB 0x80020000 0x80021FFF 8KB ETM ETM 0x80022000 0x80023FFF 8KB APBX DMA APBX 0x80024000 0x80025FFF 8KB 0x80026000 0x80027FFF 8KB Data CoProcessor DCP 0x80028000 0x80029FFF 8KB Pixel Pipeline PXP 0x8002A000 0x8002BFFF 8KB One Time Prog Controller OCOTP 0x8002C000 0x8002DFFF 8KB AXI Control AXI_AHB0 0x8002E000 0x8002FFFF 8KB LCD Interface LCDIF 0x80030000 0x80031FFF 8KB CAN0 CAN0 0x80032000 0x80033FFF 8KB CAN1 CAN1 0x80034000 0x80035FFF 8KB 0x80036000 0x80037FFF 8KB 0x80038000 0x80039FFF 8KB 0x8003A000 0x8003BFFF 8KB SIMDBG SIMDBG 0x8003C000 0x8003C1ff SIMGPMISEL SIMGPMISEL 0x8003C200 0x8003C2ff SIMSSPSEL SIMSSPSEL 0x8003C300 0x8003C3ff SIMMEMSEL SIMMEMSEL 0x8003C400 0x8003C4ff GPIOMON GPIOMON 0x8003C500 0x8003C5ff SIMENET SIMENET 0x8003C700 0x8003C7ff ARMJTAG ARMJTAG 0x8003C800 0x8003C8ff Clock Controller CLKCTRL 0x80040000 0x80041FFF 8KB Serial Audio Interface 0 SAIF0 0x80042000 0x80043FFF 8KB Power Control POWER 0x80044000 0x80045FFF 8KB Serial Audio Interface 1 SAIF1 0x80046000 0x80047FFF 8KB Low Resolution ADC LRADC 0x80048000 0x80049FFF 8KB 0x8004A000 0x8004BFFF 8KB 0x8004C000 0x8004DFFF 8KB 0x8004E000 0x8004FFFF 8KB 0x80050000 0x80051FFF 8KB 0x80052000 0x80053FFF 8KB Sony/Phillips Digital Interface SPDIF 0x80054000 0x80055FFF 8KB Real Time Clock RTC 0x80056000 0x80057FFF 8KB Inter-Integrated Circuit 0 I2C0 0x80058000 0x80059FFF 8KB Inter-Integrated Circuit 1 I2C1 0x8005A000 0x8005BFFF 8KB 0x8005C000 0x8005DFFF 8KB Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 136 Freescale Semiconductor, Inc. Chapter 4 Memory Map Table 4-1. Address Map for i.MX28 (continued) DECODE BLOCK DEVICE Pulse Width Modulation AHB PWM START ADDRESS END ADDRESS SIZE 0x8005E000 0x8005FFFF 8KB 0x80060000 0x80061FFF 8KB 0x80062000 0x80063FFF 8KB 0x80064000 0x80065FFF 8KB 0x80066000 0x80067FFF 8KB Timers/Rotary TIMROT 0x80068000 0x80069FFF 8KB Application UART 0 UARTAPP0 0x8006A000 0x8006BFFF 8KB Application UART 1 UARTAPP1 0x8006C000 0x8006DFFF 8KB Application UART 2 UARTAPP2 0x8006E000 0x8006FFFF 8KB Application UART 3 UARTAPP3 0x80070000 0x80071FFF 8KB Application UART 4 UARTAPP4 0x80072000 0x80073FFF 8KB Debug Uart UARTDBG 0x80074000 0x80075FFF 8KB 0x80076000 0x80077FFF 8KB 0x80078000 0x80079FFF 8KB 0x8007A000 0x8007BFFF 8KB Univeral Serial Bus Physical IF USBPHY0 0x8007C000 0x8007DFFF 8KB Univeral Serial Bus Physical IF USBPHY1 0x8007E000 0x8007FFFF 8KB USB Controller 0 USBCTRL0 0x80080000 0x8008FFFF 64KB USB Controller 1 USBCTRL1 0x80090000 0x8009FFFF 64KB 0x800A0000 0x800AFFFF 64KB 0x800B0000 0x800BFFFF 64KB 0x800C0000 0x800CFFFF 64KB 0x800D0000 0x800DFFFF 64KB Default First-Level Page Table AHB MNEMONIC DFLPT External Memory Interface (REG) DRAM 0x800E0000 0x800EFFFF 64KB ENET MAC0 ENET 0x800F0000 0x800F3FFF 16KB ENET MAC1 ENET 0x800F4000 0x800F7FFF 16KB ENT Switch SWITCH 0x800F8000 0x800FFFFF 32KB On-Chip ROM OCROM 0xC0000000 0xFFFFFFFF 128K B i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 137 Memory Map Overview i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 138 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.1 Interrupt Collector (ICOLL) Overview The ARM9 CPU core has two interrupt input lines, IRQ and FIQ. As shown in the following figure, the Interrupt Collector (ICOLL) can steer any of the 128 interrupt sources to either the FIQn or IRQn lines of the ARM9 CPU. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 139 Operation 0 . . . 127 HW Int Sources HW_ICOLL_INTERRUPT0-127[ENFIQ] HW_ICOLL_INTERRUPT0-127[ENABLE] HW_ICOLL_RAW0-3 HW_ICOLL_RAW0-3 HW_ICOLL_RAW0-3 HW_ICOLL_RAW0-3 128 128 HW_ICOLL_INTERRUPT0-127[SOFTIRQ] 128 128 128 128 HW_ICOLL_INTERRUPT0-127[PRIORITY] 128 128 128 Priority Encoder OR x128 Vector Address = Vector Base Address + 4 * Source Bit Number FIQ IRQ HW_ICOLL_VECTOR ARM9 Figure 5-1. Interrupt Collector System Diagram 5.2 Operation Within an individual interrupt request line (IRQ only), the ICOLL offers four-level priority (above base level) for each of its interrupt sources. Preemption of a lower priority interrupt by a higher priority is supported (interrupt nesting). Interrupts assigned to the same level are serviced in a strict linear priority order within level from lowest to highest interrupt source bit number. FIQ interrupts are neither prioritized nor vectorized. All the interrupt lines can be configured as a FIQ. If more than one is routed to the FIQ, then they must be discriminated by a software. It is highly recommended to reserve FIQ assignment to time critical events such as voltage brownouts or timers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 140 Freescale Semiconductor, Inc. HW_ICOLL_INTERRUPT33[SOFTIRQ] 1:4 32 . . . 63 HW_ICOLL_RAW1 (Read-Only) HW_ICOLL_INTERRUPT33[ENABLE] APBH AHB HW_ICOLL_INTERRUPT33[PRIORITY] HW_ICOLL_VECTOR HW_ICOLL_VBASE (Vector Table Base Addr ) Vector Address = Vector Base Address + 4 * Source Bit Number Chapter 5 Interrupt Collector (ICOLL) IRQ FIQ ARM 926 HW_ICOLL_INTERRUPT33[ENFIQ] Other sources Figure 5-2. Interrupt Collector IRQ/FIQ Logic for Source 33 For a single interrupt source bit, there is an enable bit that gates it to the priority logic (HW_ICOLL_INTERRUPTn[ENABLE]). A software interrupt bit per source bit can be used to force an interrupt at the appropriate priority level directed to the corresponding vector address. Each source can be applied to one of the four interrupt levels. The enable bit, FIQ-enable, the software interrupt bit, and the two-bit priority level specification for each interrupt source bit are contained with a single programmable register for each interrupt. The path from any interrupt source to the FIQ or IRQ logic is shown in Figure 5-2 using HW_ICOLL_INTERRUPT33 as an example. The data path for generating the vector address (readable by software) for the IRQ generation portion of the interrupt collector is implemented as a multicycle path, as shown in Figure 5-3. The interrupt sources are continuously sampled in the holding register until one or more arrive. The FSM causes the holding register to stop sampling i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 141 Operation while a vector address is computed. Each interrupt source bit is applied to one of the four levels based on the two-bit priority specification of each source bit. When the holding register closes, there can be more than one newly arrived source bit. Thus, the source bits could be assigned such that more than one interrupt level is requesting an interrupt. The pipeline first determines the highest level requesting interrupt service. All interrupt requests on that level are presented to the linear priority encoder. The result of this stage is a six-bit number corresponding to the source bit number of the highest priority requesting an interrupt. This six-bit source number is used to compute the vector address as follows: VectorAddress = VectorBase + (Pitch * SourceBitNumber) Pitch = 4,8, 12,16,20,24, or 28 as desired, see HW_CTRL_VECTOR_PITCH. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 142 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Multicycle Path 3x APBH AHB HW_ICOLL_VECTOR Compute vector address Linear Priority Pick Hghest Level INTERRUPT37[SOFTIRQ] 1:4 INTERRUPT37[ENABLE] Holding Register INTERRUPT37[PRIORITY] (1x) 32 . . . 63 HW_ICOLL_RAW1 (Read-Only) FIQ FSM IRQ ARM9 [37] APB PIO Cycles INT Sources Figure 5-3. IRQ Control Flow 5.2.1 Nesting of Multi-Level IRQ Interrupts There are a number of very important interactions between the interrupt collector's FSM and the interrupt service routine (ISR) running on the CPU. See Figure 5-4. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 143 Operation As soon as the interrupt source is recognized in the holding register, the FSM delays two clocks, then grabs the vector address and asserts IRQ to the CPU. After the CPU enters the interrupt service routine, it must notify the interrupt collector as soon as possible. Software indicates the in-service state by writing to the HW_ICOLL_VECTOR register. The contents of the data bus on this write do not matter. Optionally, firmware can enable the ARM read side-effect mode. In this case, the in-service state is indicated as a side effect of having read the HW_ICOLL_VECTOR register at the exception vector (0xFFFF0018). At this point, the FSM reopens the holding register and scans for new interrupt sources. Any such IRQ sources are presented to the CPU, provided that they are at a level higher than any currently in-service level. Critical section Critical section Critical section Whenever the ARM CPU takes an IRQ exception, it turns off the IRQ enable in the CPU status register (CSR), as shown in Figure 5-4. If a higher priority interrupt is pending at this point, then another IRQ exception is taken. CSR IRQ IRQ IRQ LEVEL 3 IRQ LEVEL 2 IRQ LEVEL 1 ACKLEVEL0 ACKLEVEL2 Re-enable IRQ INSERVICE ACKLEVEL3 Re-enable IRQ Re-enable IRQ INSERVICE Base INSERVICE IRQ LEVEL 0 Figure 5-4. Nesting of Multi-Level IRQ Interrupts The example in shows going from the base to a level 0 ISR. When the ISR at level 0 was ready, it enabled IRQ interrupts. At this point, it nests IRQ interrupts up to a level 3 interrupt. The level 3 ISR marks its in-service state, which causes the interrupt collector to open the holding register to search for new interrupt sources. In this example, none i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 144 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) comes in, so the level 3 ISR completes. As part of the return process, the ISR disables IRQ interrupts, then acknowledges the level 3 service state. This is accomplished by writing the level number (3 in this case) to the interrupt collector's Level Acknowledge register. The interrupt collector resets the in-service bit for level 3. If this enables an IRQ at level 3, then it asserts IRQ and goes through the nesting process again. Since IRQ exceptions are masked in the level 3 ISR, this nesting does not take place until the level 3 ISR returns from interrupt. This return automatically re-enables IRQ exceptions. At this point, another exception could occur. Figure 5-4 shows a second nesting of the IRQ interrupt by the arrival of a level 2 interrupt source bit. Finally, the figure shows the point at which the level 0 ISR enters its critical section (masks IRQ) and acknowledges level 0 to the interrupt collector and returns from the interrupt. The FSM reverts to its BASE level state waiting for an interrupt request to arrive in the holding register. The waveform for the IRQ mask in the CPU status register (CSR) and the waveform for the IRQ input to the CPU as they relate to the interrupt collector action are shown in Figure 5-4. NOTE There is an inherent race condition between notifying the interrupt collector that an ISR has been entered and having that ISR re-enable IRQ exceptions in the CSR. The in-service notification can take a number of cycles to percolate through the write buffer, through the AHB and APB bridge and into the interrupt collector where it removes the IRQ assertion to the CPU. This ICOLL IRQ must be deasserted before the CSR IRQ on the CPU is re-enabled or the CPU will see a phantom interrupt. This is why the ARM vectored interrupt controller provides this in-service notification as a read side effect of the vector address read. Alternatively, the ISR can read the interrupt collector's CSR. The value received is unimportant, but the time required to do the read ensures that the write data has arrived at the interrupt collector. If firmware uses this method, it should allow clocks after the read for the FSM and for the CPU to recognize that the IRQ has been deasserted. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 145 Operation 5.2.2 FIQ Generation On this device, all interrupt sources can be configured as FIQ. This is controlled through the HW_ICOLL_INTERRUPTn[ENFIQ] register bit as shown in Figure 5-2. When enabled to the FIQ, the software interrupt associated with these bits can be used to generate the FIQ from these sources for test purposes. When an interrupt source is programmed as an FIQ, and IRQ cannot be generated from that source. 5.2.3 Interrupt Sources The following table lists all of the interrupt sources on the device. Use hw_irq.h to access these bits. Table 5-1. i.MX28 Interrupt Sources Source Number Interrupt Vector Description 0 batt_brownout_irq 0x0000 Power module battery brownout detect IRQ, recommend to set as FIQ. 1 vddd_brownout_irq 0x0004 Power module VDDD brownout detect IRQ, recommend to set as FIQ. 2 vddio_brownout_irq 0x0008 Power module VDDIO brownout detect IRQ, recommend to set as FIQ. 3 vdda_brownout_irq 0x000C Power module VDDA brownout detect IRQ, recommend to set as FIQ. 4 vdd5v_droop_irq 0x0010 5V Droop IRQ, recommend to be set as FIQ. 5 dcdc4p2_brownout_irq 0x0014 4.2V regulated supply brown-out IRQ, recommend to be set as FIQ. 6 vdd5v_irq 0x0018 IRQ on 5V connect or disconnect also OTG 4.2V 0x001C Reserved 7 8 can0_irq 0x0020 CAN0 IRQ. 9 can1_irq 0x0024 CAN1 IRQ. 10 lradc_touch_irq 0x0028 (Touch Screen) Touch detection IRQ. 11 0x002C Reserved 12 0x0030 Reserved 13 hsadc_irq 0x0034 HSADC IRQ. 14 lradc_thresh0_irq 0x0038 LRADC0 Threshold IRQ. 15 lradc_thresh1_irq 0x003C LRADC1 Threshold IRQ. 16 lradc_ch0_irq 0x0040 LRADC Channel 0 conversion complete IRQ. 17 lradc_ch1_irq 0x0044 LRADC Channel 1 conversion complete IRQ. 18 lradc_ch2_irq 0x0048 LRADC Channel 2 conversion complete IRQ. 19 lradc_ch3_irq 0x004C LRADC Channel 3 conversion complete IRQ. 20 lradc_ch4_irq 0x0050 LRADC Channel 4 conversion complete IRQ. 21 lradc_ch5_irq 0x0054 LRADC Channel 5 conversion complete IRQ. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 146 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Table 5-1. i.MX28 Interrupt Sources (continued) Source Number Interrupt Vector Description 22 lradc_ch6_irq 0x0058 LRADC Channel 6 conversion complete IRQ. 23 lradc_ch7_irq 0x005C LRADC Channel 7 conversion complete IRQ. 24 lradc_button0_irq 0x0060 LRADC Channel 0 button detection IRQ. 25 lradc_button1_irq 0x0064 LRADC Channel 1 button detection IRQ. 0x0068 Reserved 26 27 perfmon_irq 0x006C Performance monitor IRQ. 28 rtc_1msec_irq 0x0070 RTC 1ms event IRQ. 29 rtc_alarm_irq 0x0074 RTC alarm event IRQ. 0x0078 Reserved 30 31 comms_irq 0x007C JTAG debug communications port IRQ. 32 emi_error_irq 0x0080 External memory controller IRQ. 33 0x0084 Reserved 34 0x0088 Reserved 35 0x008C Reserved 36 0x0090 Reserved 37 reserved 0x0094 Reserved 38 lcdif_irq 0x0098 LCDIF IRQ. 39 pxp_irq 0x009C PXP IRQ. 40 0x00A0 Reserved 41 bch_irq 0x00A4 BCH consolidated IRQ. 42 gpmi_irq 0x00A8 GPMI internal error and status IRQ. 0x00AC Reserved 0x00B0 Reserved 0x00B4 SPDIF FIFO error IRQ. 0x00B8 Reserved 43 44 45 spdif_error_irq 46 47 duart_irq 0x00BC Debug UART IRQ. 48 timer0_irq 0x00C0 Timer0 IRQ, recommend to set as FIQ. 49 timer1_irq 0x00C4 Timer1 IRQ, recommend to set as FIQ. 50 timer2_irq 0x00C8 Timer2 IRQ, recommend to set as FIQ. 51 timer3_irq 0x00CC Timer3 IRQ, recommend to set as FIQ. 52 dcp_vmi_irq 0x00D0 DCP Channel 0 virtual memory page copy IRQ. 53 dcp_irq 0x00D4 DCP (per channel and CSC) IRQ. 54 dcp_secure_irq 0x00D8 DCP secure IRQ. 55 0x00DC Reserved 56 0x00E0 Reserved 57 0x00E4 Reserved 58 saif1_irq 0x00E8 SAIF1 FIFO & Service error IRQ. 59 saif0_irq 0x00EC SAIF0 FIFO & Service error IRQ. 60 0x00F0 Reserved 61 0x00F4 Reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 147 Operation Table 5-1. i.MX28 Interrupt Sources (continued) Source Number Vector Description 62 0x00F8 Reserved 63 0x00FC Reserved 64 0x0100 Reserved 65 0x0104 Reserved 0x0108 SPDIF DMA channel IRQ. 0x010C Reserved 66 Interrupt spdif_dma_irq 67 68 i2c0_dma_irq 0x0110 I2C0 DMA channel IRQ. 69 i2c1_dma_irq 0x0114 I2C1 DMA channel IRQ. 70 auart0_rx_dma_irq 0x0118 Application UART0 receiver DMA channel IRQ. 71 auart0_tx_dma_irq 0x011C Application UART0 transmitter DMA channel IRQ. 72 auart1_rx_dma_irq 0x0120 Application UART1 receiver DMA channel IRQ. 73 auart1_tx_dma_irq 0x0124 Application UART1 transmitter DMA 74 auart2_rx_dma_irq 0x0128 Application UART2 receiver DMA channel IRQ. 75 auart2_tx_dma_irq 0x012C Application UART2 transmitter DMA channel IRQ. 76 auart3_rx_dma_irq 0x0130 Application UART3 receiver DMA channel IRQ. 77 auart3_tx_dma_irq 0x0134 Application UART3 transmitter DMA channel IRQ. 78 auart4_rx_dma_irq 0x0138 Application UART4 receiver DMA channel IRQ. 79 auart4_tx_dma_irq 0x013C Application UART4 transmitter DMA channel IRQ. 80 saif0_dma_irq 0x0140 SAIF0 DMA channel IRQ. 81 saif1_dma_irq 0x0144 SAIF1 DMA channel IRQ. 82 ssp0_dma_irq 0x0148 SSP0 DMA channel IRQ. 83 ssp1_dma_irq 0x014C SSP1 DMA channel IRQ. 84 ssp2_dma_irq 0x0150 SSP2 DMA channel IRQ. 85 ssp3_dma_irq 0x0154 SSP3 DMA channel IRQ. 86 lcdif_dma_irq 0x0158 LCDIF DMA channel IRQ. 87 hsadc_dma_irq 0x015C HSADC DMA channel IRQ. 88 gpmi_dma_irq 0x0160 GPMI DMA channel IRQ. 89 digctl_debug_trap_irq 0x0164 Layer 0 or Layer 3 AHB address access trap IRQ. 0x0168 Reserved 90 91 0x016C Reserved 92 usb1_irq 0x0170 USB1 IRQ. 93 usb0_irq 0x0174 USB0 IRQ. 94 usb1_wakeup_irq 0x0178 UTM1 IRQ. 95 usb0_wakeup_irq 0x017C UTM0 IRQ. 96 ssp0_error_irq 0x0180 SSP0 device-level error and status IRQ. 97 ssp1_error_irq 0x0184 SSP1 device-level error and status IRQ. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 148 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Table 5-1. i.MX28 Interrupt Sources (continued) Source Number Interrupt Vector Description 98 ssp2_error_irq 0x0188 SSP2 device-level error and status IRQ. 99 ssp3_error_irq 0x018C SSP3 device-level error and status IRQ. 100 enet_swi_irq 0x0190 Switch IRQ. 101 enet_mac0_irq 0x0194 MAC0 IRQ. 102 enet_mac1_irq 0x0198 MAC1 IRQ. 103 enet_mac0_1588_irq 0x019C 1588 of MAC0 IRQ. 104 enet_mac1_1588_irq 0x01A0 1588 of MAC1 IRQ. 105 0x01A4 Reserved 106 0x01A8 Reserved 107 0x01AC Reserved 108 0x01B0 Reserved 109 0x01B4 Reserved 110 i2c1_error_irq 0x01B8 I2C1 device detected errors and line conditions IRQ. 111 i2c0_error_irq 0x01BC I2C0 device detected errors and line conditions IRQ. 112 auart0_irq 0x01C0 Application UART0 internal error IRQ. 113 auart1_irq 0x01C4 Application UART1 internal error IRQ. 114 auart2_irq 0x01C8 Application UART2 internal error IRQ. 115 auart3_irq 0x01CC Application UART3 internal error IRQ. 116 auart4_irq 0x01D0 Application UART4 internal error IRQ. 117 0x01D4 Reserved 118 0x01D8 Reserved 119 0x01DC Reserved 120 0x01E0 Reserved 121 0x01E4 Reserved 122 pinctrl5_irq 0x01E8 GPIO bank 5 interrupt IRQ. 123 pinctrl4_irq 0x01EC GPIO bank 4 interrupt IRQ. 124 pinctrl3_irq 0x01F0 GPIO bank 3 interrupt IRQ. 125 pinctrl2_irq 0x01F4 GPIO bank 2 interrupt IRQ. 126 pinctrl1_irq 0x01F8 GPIO bank 1 interrupt IRQ. 127 pinctrl0_irq 0x01FC GPIO bank 0 interrupt IRQ. 5.2.4 CPU Wait-for-Interrupt Mode To enable wait-for-interrupt mode, two distinct actions are required by the programmer. 1. Set the INTERRUPT_WAIT bit in the HW_CLKCTRL_CPUCLKCTRL register. This must be done through a RMW operation. For example: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 149 Operation uclkctrl = HW_CLKCTRL_CPUCLKCTRL_RD(); uclkctrl |= BM_CLKCTRL_CPUCLKCTRL_INTERRUPT_WAIT; HW_CLKCTRL_CPUCLKCTRL_WR(uclkctrl); 2. After setting the INTERRUPT_WAIT bit, a coprocessor instruction is required. asm ( // Note: R0 is used in the following example, but any usual register may be used. "mov R0, 0;" // Rd SBZ (should be zero) "mcr p15,0,r0,c7,c0,4;" //Drain write buffers, idle CPU clock & processor, and stop //processor at this instruction "nop"); // The lr sent to handler points here after RTI The coprocessor instruction sequence above enables an internal gating signal. This internal signal guarantees that write buffers are drained and ensures that the processor is in an idle state. On execution of the MCR coprocessor instruction, the CPU clock is stopped and the processor halts on the instruction--waiting for an interrupt to occur. The INTERRUPT_WAIT bit can be thought of as a Wait-for-Interrupt enable bit. Therefore, it must be set prior to the execution of the MCR instruction. It is recommended that, when the Wait-for-Interrupt mode is to be used, the INTERRUPT_WAIT bit be set at initialization time and left on. With the INTERRUPT_WAIT bit set, after the execution of the MCR WFI command, the processor halts on the MCR instruction. When an interrupt or FIQ occurs, the MCR instruction completes and the IRQ or FIQ handler is entered normally. The return link that is passed to the handler is automatically adjusted by the above MCR instruction, such that a normal return from an interrupt results in a continuous execution of the instruction immediately following the MCR. That is, the LR will contain the address of the MCR instruction plus eight, such that a typical return from an interrupt instruction (for example, subs pc, LR, 4) will return to the instruction immediately following the MCR (the NOP in the example above). Whenever the CPU is stopped because the clock control HW_CLKCTRL_ CPUCLKCTRL_INTERRUPT_WAIT bit is set and the MCR WFI instruction is executed, the CPU stops until an interrupt occurs. The actual condition that wakes up the CPU is determined by ORing together all enabled interrupt requests including those that are directed to the FIQ CPU input. The ICOLL_BUSY output signal from the ICOLL communicates this information to the clock control. This function does not pass through the normal ICOLL state machine. It starts the CPU clock as soon as an enabled interrupt arrives. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 150 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block, for additional information on using the SFTRST and CLKGATE bit fields. 5.4 Programmable Registers ICOLL Hardware Register Format Summary HW_ICOLL memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_0000 Interrupt Collector Interrupt Vector Address Register (HW_ICOLL_VECTOR) 32 R/W 0000_0000h 5.4.1/158 8000_0010 Interrupt Collector Level Acknowledge Register (HW_ICOLL_LEVELACK) 32 R/W 0000_0000h 5.4.2/159 8000_0020 Interrupt Collector Control Register (HW_ICOLL_CTRL) 32 R/W C003_0000h 5.4.3/160 8000_0040 Interrupt Collector Interrupt Vector Base Address Register (HW_ICOLL_VBASE) 32 R/W 0000_0000h 5.4.4/162 8000_0070 Interrupt Collector Status Register (HW_ICOLL_STAT) 32 R 0000_007Fh 5.4.5/163 8000_00A0 Interrupt Collector Raw Interrupt Input Register 0 (HW_ICOLL_RAW0) 32 R 0000_0000h 5.4.6/164 8000_00B0 Interrupt Collector Raw Interrupt Input Register 1 (HW_ICOLL_RAW1) 32 R 0000_0000h 5.4.7/164 8000_00C0 Interrupt Collector Raw Interrupt Input Register 2 (HW_ICOLL_RAW2) 32 R 0000_0000h 5.4.8/165 8000_00D0 Interrupt Collector Raw Interrupt Input Register 3 (HW_ICOLL_RAW3) 32 R 0000_0000h 5.4.9/166 8000_0120 Interrupt Collector Interrupt Register 0 (HW_ICOLL_INTERRUPT0) 32 R/W 0000_0000h 5.4.10/167 8000_0130 Interrupt Collector Interrupt Register 1 (HW_ICOLL_INTERRUPT1) 32 R/W 0000_0000h 5.4.11/168 8000_0140 Interrupt Collector Interrupt Register 2 (HW_ICOLL_INTERRUPT2) 32 R/W 0000_0000h 5.4.12/170 8000_0150 Interrupt Collector Interrupt Register 3 (HW_ICOLL_INTERRUPT3) 32 R/W 0000_0000h 5.4.13/171 8000_0160 Interrupt Collector Interrupt Register 4 (HW_ICOLL_INTERRUPT4) 32 R/W 0000_0000h 5.4.14/173 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 151 Programmable Registers HW_ICOLL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_0170 Interrupt Collector Interrupt Register 5 (HW_ICOLL_INTERRUPT5) 32 R/W 0000_0000h 5.4.15/174 8000_0180 Interrupt Collector Interrupt Register 6 (HW_ICOLL_INTERRUPT6) 32 R/W 0000_0000h 5.4.16/176 8000_0190 Interrupt Collector Interrupt Register 7 (HW_ICOLL_INTERRUPT7) 32 R/W 0000_0000h 5.4.17/177 8000_01A0 Interrupt Collector Interrupt Register 8 (HW_ICOLL_INTERRUPT8) 32 R/W 0000_0000h 5.4.18/179 8000_01B0 Interrupt Collector Interrupt Register 9 (HW_ICOLL_INTERRUPT9) 32 R/W 0000_0000h 5.4.19/180 8000_01C0 Interrupt Collector Interrupt Register 10 (HW_ICOLL_INTERRUPT10) 32 R/W 0000_0000h 5.4.20/182 8000_01D0 Interrupt Collector Interrupt Register 11 (HW_ICOLL_INTERRUPT11) 32 R/W 0000_0000h 5.4.21/183 8000_01E0 Interrupt Collector Interrupt Register 12 (HW_ICOLL_INTERRUPT12) 32 R/W 0000_0000h 5.4.22/185 8000_01F0 Interrupt Collector Interrupt Register 13 (HW_ICOLL_INTERRUPT13) 32 R/W 0000_0000h 5.4.23/186 8000_0200 Interrupt Collector Interrupt Register 14 (HW_ICOLL_INTERRUPT14) 32 R/W 0000_0000h 5.4.24/188 8000_0210 Interrupt Collector Interrupt Register 15 (HW_ICOLL_INTERRUPT15) 32 R/W 0000_0000h 5.4.25/189 8000_0220 Interrupt Collector Interrupt Register 16 (HW_ICOLL_INTERRUPT16) 32 R/W 0000_0000h 5.4.26/191 8000_0230 Interrupt Collector Interrupt Register 17 (HW_ICOLL_INTERRUPT17) 32 R/W 0000_0000h 5.4.27/192 8000_0240 Interrupt Collector Interrupt Register 18 (HW_ICOLL_INTERRUPT18) 32 R/W 0000_0000h 5.4.28/194 8000_0250 Interrupt Collector Interrupt Register 19 (HW_ICOLL_INTERRUPT19) 32 R/W 0000_0000h 5.4.29/195 8000_0260 Interrupt Collector Interrupt Register 20 (HW_ICOLL_INTERRUPT20) 32 R/W 0000_0000h 5.4.30/197 8000_0270 Interrupt Collector Interrupt Register 21 (HW_ICOLL_INTERRUPT21) 32 R/W 0000_0000h 5.4.31/198 8000_0280 Interrupt Collector Interrupt Register 22 (HW_ICOLL_INTERRUPT22) 32 R/W 0000_0000h 5.4.32/200 8000_0290 Interrupt Collector Interrupt Register 23 (HW_ICOLL_INTERRUPT23) 32 R/W 0000_0000h 5.4.33/201 8000_02A0 Interrupt Collector Interrupt Register 24 (HW_ICOLL_INTERRUPT24) 32 R/W 0000_0000h 5.4.34/203 8000_02B0 Interrupt Collector Interrupt Register 25 (HW_ICOLL_INTERRUPT25) 32 R/W 0000_0000h 5.4.35/204 8000_02C0 Interrupt Collector Interrupt Register 26 (HW_ICOLL_INTERRUPT26) 32 R/W 0000_0000h 5.4.36/206 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 152 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_02D0 Interrupt Collector Interrupt Register 27 (HW_ICOLL_INTERRUPT27) 32 R/W 0000_0000h 5.4.37/207 8000_02E0 Interrupt Collector Interrupt Register 28 (HW_ICOLL_INTERRUPT28) 32 R/W 0000_0000h 5.4.38/209 8000_02F0 Interrupt Collector Interrupt Register 29 (HW_ICOLL_INTERRUPT29) 32 R/W 0000_0000h 5.4.39/210 8000_0300 Interrupt Collector Interrupt Register 30 (HW_ICOLL_INTERRUPT30) 32 R/W 0000_0000h 5.4.40/212 8000_0310 Interrupt Collector Interrupt Register 31 (HW_ICOLL_INTERRUPT31) 32 R/W 0000_0000h 5.4.41/213 8000_0320 Interrupt Collector Interrupt Register 32 (HW_ICOLL_INTERRUPT32) 32 R/W 0000_0000h 5.4.42/215 8000_0330 Interrupt Collector Interrupt Register 33 (HW_ICOLL_INTERRUPT33) 32 R/W 0000_0000h 5.4.43/216 8000_0340 Interrupt Collector Interrupt Register 34 (HW_ICOLL_INTERRUPT34) 32 R/W 0000_0000h 5.4.44/218 8000_0350 Interrupt Collector Interrupt Register 35 (HW_ICOLL_INTERRUPT35) 32 R/W 0000_0000h 5.4.45/219 8000_0360 Interrupt Collector Interrupt Register 36 (HW_ICOLL_INTERRUPT36) 32 R/W 0000_0000h 5.4.46/221 8000_0370 Interrupt Collector Interrupt Register 37 (HW_ICOLL_INTERRUPT37) 32 R/W 0000_0000h 5.4.47/222 8000_0380 Interrupt Collector Interrupt Register 38 (HW_ICOLL_INTERRUPT38) 32 R/W 0000_0000h 5.4.48/224 8000_0390 Interrupt Collector Interrupt Register 39 (HW_ICOLL_INTERRUPT39) 32 R/W 0000_0000h 5.4.49/225 8000_03A0 Interrupt Collector Interrupt Register 40 (HW_ICOLL_INTERRUPT40) 32 R/W 0000_0000h 5.4.50/227 8000_03B0 Interrupt Collector Interrupt Register 41 (HW_ICOLL_INTERRUPT41) 32 R/W 0000_0000h 5.4.51/228 8000_03C0 Interrupt Collector Interrupt Register 42 (HW_ICOLL_INTERRUPT42) 32 R/W 0000_0000h 5.4.52/230 8000_03D0 Interrupt Collector Interrupt Register 43 (HW_ICOLL_INTERRUPT43) 32 R/W 0000_0000h 5.4.53/231 8000_03E0 Interrupt Collector Interrupt Register 44 (HW_ICOLL_INTERRUPT44) 32 R/W 0000_0000h 5.4.54/233 8000_03F0 Interrupt Collector Interrupt Register 45 (HW_ICOLL_INTERRUPT45) 32 R/W 0000_0000h 5.4.55/234 8000_0400 Interrupt Collector Interrupt Register 46 (HW_ICOLL_INTERRUPT46) 32 R/W 0000_0000h 5.4.56/236 8000_0410 Interrupt Collector Interrupt Register 47 (HW_ICOLL_INTERRUPT47) 32 R/W 0000_0000h 5.4.57/237 8000_0420 Interrupt Collector Interrupt Register 48 (HW_ICOLL_INTERRUPT48) 32 R/W 0000_0000h 5.4.58/239 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 153 Programmable Registers HW_ICOLL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_0430 Interrupt Collector Interrupt Register 49 (HW_ICOLL_INTERRUPT49) 32 R/W 0000_0000h 5.4.59/240 8000_0440 Interrupt Collector Interrupt Register 50 (HW_ICOLL_INTERRUPT50) 32 R/W 0000_0000h 5.4.60/242 8000_0450 Interrupt Collector Interrupt Register 51 (HW_ICOLL_INTERRUPT51) 32 R/W 0000_0000h 5.4.61/243 8000_0460 Interrupt Collector Interrupt Register 52 (HW_ICOLL_INTERRUPT52) 32 R/W 0000_0000h 5.4.62/245 8000_0470 Interrupt Collector Interrupt Register 53 (HW_ICOLL_INTERRUPT53) 32 R/W 0000_0000h 5.4.63/246 8000_0480 Interrupt Collector Interrupt Register 54 (HW_ICOLL_INTERRUPT54) 32 R/W 0000_0000h 5.4.64/248 8000_0490 Interrupt Collector Interrupt Register 55 (HW_ICOLL_INTERRUPT55) 32 R/W 0000_0000h 5.4.65/249 8000_04A0 Interrupt Collector Interrupt Register 56 (HW_ICOLL_INTERRUPT56) 32 R/W 0000_0000h 5.4.66/251 8000_04B0 Interrupt Collector Interrupt Register 57 (HW_ICOLL_INTERRUPT57) 32 R/W 0000_0000h 5.4.67/252 8000_04C0 Interrupt Collector Interrupt Register 58 (HW_ICOLL_INTERRUPT58) 32 R/W 0000_0000h 5.4.68/254 8000_04D0 Interrupt Collector Interrupt Register 59 (HW_ICOLL_INTERRUPT59) 32 R/W 0000_0000h 5.4.69/255 8000_04E0 Interrupt Collector Interrupt Register 60 (HW_ICOLL_INTERRUPT60) 32 R/W 0000_0000h 5.4.70/257 8000_04F0 Interrupt Collector Interrupt Register 61 (HW_ICOLL_INTERRUPT61) 32 R/W 0000_0000h 5.4.71/258 8000_0500 Interrupt Collector Interrupt Register 62 (HW_ICOLL_INTERRUPT62) 32 R/W 0000_0000h 5.4.72/260 8000_0510 Interrupt Collector Interrupt Register 63 (HW_ICOLL_INTERRUPT63) 32 R/W 0000_0000h 5.4.73/261 8000_0520 Interrupt Collector Interrupt Register 64 (HW_ICOLL_INTERRUPT64) 32 R/W 0000_0000h 5.4.74/263 8000_0530 Interrupt Collector Interrupt Register 65 (HW_ICOLL_INTERRUPT65) 32 R/W 0000_0000h 5.4.75/264 8000_0540 Interrupt Collector Interrupt Register 66 (HW_ICOLL_INTERRUPT66) 32 R/W 0000_0000h 5.4.76/266 8000_0550 Interrupt Collector Interrupt Register 67 (HW_ICOLL_INTERRUPT67) 32 R/W 0000_0000h 5.4.77/267 8000_0560 Interrupt Collector Interrupt Register 68 (HW_ICOLL_INTERRUPT68) 32 R/W 0000_0000h 5.4.78/269 8000_0570 Interrupt Collector Interrupt Register 69 (HW_ICOLL_INTERRUPT69) 32 R/W 0000_0000h 5.4.79/270 8000_0580 Interrupt Collector Interrupt Register 70 (HW_ICOLL_INTERRUPT70) 32 R/W 0000_0000h 5.4.80/272 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 154 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_0590 Interrupt Collector Interrupt Register 71 (HW_ICOLL_INTERRUPT71) 32 R/W 0000_0000h 5.4.81/273 8000_05A0 Interrupt Collector Interrupt Register 72 (HW_ICOLL_INTERRUPT72) 32 R/W 0000_0000h 5.4.82/275 8000_05B0 Interrupt Collector Interrupt Register 73 (HW_ICOLL_INTERRUPT73) 32 R/W 0000_0000h 5.4.83/276 8000_05C0 Interrupt Collector Interrupt Register 74 (HW_ICOLL_INTERRUPT74) 32 R/W 0000_0000h 5.4.84/278 8000_05D0 Interrupt Collector Interrupt Register 75 (HW_ICOLL_INTERRUPT75) 32 R/W 0000_0000h 5.4.85/279 8000_05E0 Interrupt Collector Interrupt Register 76 (HW_ICOLL_INTERRUPT76) 32 R/W 0000_0000h 5.4.86/281 8000_05F0 Interrupt Collector Interrupt Register 77 (HW_ICOLL_INTERRUPT77) 32 R/W 0000_0000h 5.4.87/282 8000_0600 Interrupt Collector Interrupt Register 78 (HW_ICOLL_INTERRUPT78) 32 R/W 0000_0000h 5.4.88/284 8000_0610 Interrupt Collector Interrupt Register 79 (HW_ICOLL_INTERRUPT79) 32 R/W 0000_0000h 5.4.89/285 8000_0620 Interrupt Collector Interrupt Register 80 (HW_ICOLL_INTERRUPT80) 32 R/W 0000_0000h 5.4.90/287 8000_0630 Interrupt Collector Interrupt Register 81 (HW_ICOLL_INTERRUPT81) 32 R/W 0000_0000h 5.4.91/288 8000_0640 Interrupt Collector Interrupt Register 82 (HW_ICOLL_INTERRUPT82) 32 R/W 0000_0000h 5.4.92/290 8000_0650 Interrupt Collector Interrupt Register 83 (HW_ICOLL_INTERRUPT83) 32 R/W 0000_0000h 5.4.93/291 8000_0660 Interrupt Collector Interrupt Register 84 (HW_ICOLL_INTERRUPT84) 32 R/W 0000_0000h 5.4.94/293 8000_0670 Interrupt Collector Interrupt Register 85 (HW_ICOLL_INTERRUPT85) 32 R/W 0000_0000h 5.4.95/294 8000_0680 Interrupt Collector Interrupt Register 86 (HW_ICOLL_INTERRUPT86) 32 R/W 0000_0000h 5.4.96/296 8000_0690 Interrupt Collector Interrupt Register 87 (HW_ICOLL_INTERRUPT87) 32 R/W 0000_0000h 5.4.97/297 8000_06A0 Interrupt Collector Interrupt Register 88 (HW_ICOLL_INTERRUPT88) 32 R/W 0000_0000h 5.4.98/299 8000_06B0 Interrupt Collector Interrupt Register 89 (HW_ICOLL_INTERRUPT89) 32 R/W 0000_0000h 5.4.99/300 8000_06C0 Interrupt Collector Interrupt Register 90 (HW_ICOLL_INTERRUPT90) 32 R/W 0000_0000h 5.4.100/302 8000_06D0 Interrupt Collector Interrupt Register 91 (HW_ICOLL_INTERRUPT91) 32 R/W 0000_0000h 5.4.101/303 8000_06E0 Interrupt Collector Interrupt Register 92 (HW_ICOLL_INTERRUPT92) 32 R/W 0000_0000h 5.4.102/305 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 155 Programmable Registers HW_ICOLL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_06F0 Interrupt Collector Interrupt Register 93 (HW_ICOLL_INTERRUPT93) 32 R/W 0000_0000h 5.4.103/306 8000_0700 Interrupt Collector Interrupt Register 94 (HW_ICOLL_INTERRUPT94) 32 R/W 0000_0000h 5.4.104/308 8000_0710 Interrupt Collector Interrupt Register 95 (HW_ICOLL_INTERRUPT95) 32 R/W 0000_0000h 5.4.105/309 8000_0720 Interrupt Collector Interrupt Register 96 (HW_ICOLL_INTERRUPT96) 32 R/W 0000_0000h 5.4.106/311 8000_0730 Interrupt Collector Interrupt Register 97 (HW_ICOLL_INTERRUPT97) 32 R/W 0000_0000h 5.4.107/312 8000_0740 Interrupt Collector Interrupt Register 98 (HW_ICOLL_INTERRUPT98) 32 R/W 0000_0000h 5.4.108/314 8000_0750 Interrupt Collector Interrupt Register 99 (HW_ICOLL_INTERRUPT99) 32 R/W 0000_0000h 5.4.109/315 8000_0760 Interrupt Collector Interrupt Register 100 (HW_ICOLL_INTERRUPT100) 32 R/W 0000_0000h 5.4.110/317 8000_0770 Interrupt Collector Interrupt Register 101 (HW_ICOLL_INTERRUPT101) 32 R/W 0000_0000h 5.4.111/318 8000_0780 Interrupt Collector Interrupt Register 102 (HW_ICOLL_INTERRUPT102) 32 R/W 0000_0000h 5.4.112/320 8000_0790 Interrupt Collector Interrupt Register 103 (HW_ICOLL_INTERRUPT103) 32 R/W 0000_0000h 5.4.113/321 8000_07A0 Interrupt Collector Interrupt Register 104 (HW_ICOLL_INTERRUPT104) 32 R/W 0000_0000h 5.4.114/323 8000_07B0 Interrupt Collector Interrupt Register 105 (HW_ICOLL_INTERRUPT105) 32 R/W 0000_0000h 5.4.115/324 8000_07C0 Interrupt Collector Interrupt Register 106 (HW_ICOLL_INTERRUPT106) 32 R/W 0000_0000h 5.4.116/326 8000_07D0 Interrupt Collector Interrupt Register 107 (HW_ICOLL_INTERRUPT107) 32 R/W 0000_0000h 5.4.117/327 8000_07E0 Interrupt Collector Interrupt Register 108 (HW_ICOLL_INTERRUPT108) 32 R/W 0000_0000h 5.4.118/329 8000_07F0 Interrupt Collector Interrupt Register 109 (HW_ICOLL_INTERRUPT109) 32 R/W 0000_0000h 5.4.119/330 8000_0800 Interrupt Collector Interrupt Register 110 (HW_ICOLL_INTERRUPT110) 32 R/W 0000_0000h 5.4.120/332 8000_0810 Interrupt Collector Interrupt Register 111 (HW_ICOLL_INTERRUPT111) 32 R/W 0000_0000h 5.4.121/333 8000_0820 Interrupt Collector Interrupt Register 112 (HW_ICOLL_INTERRUPT112) 32 R/W 0000_0000h 5.4.122/335 8000_0830 Interrupt Collector Interrupt Register 113 (HW_ICOLL_INTERRUPT113) 32 R/W 0000_0000h 5.4.123/336 8000_0840 Interrupt Collector Interrupt Register 114 (HW_ICOLL_INTERRUPT114) 32 R/W 0000_0000h 5.4.124/338 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 156 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_0850 Interrupt Collector Interrupt Register 115 (HW_ICOLL_INTERRUPT115) 32 R/W 0000_0000h 5.4.125/339 8000_0860 Interrupt Collector Interrupt Register 116 (HW_ICOLL_INTERRUPT116) 32 R/W 0000_0000h 5.4.126/341 8000_0870 Interrupt Collector Interrupt Register 117 (HW_ICOLL_INTERRUPT117) 32 R/W 0000_0000h 5.4.127/342 8000_0880 Interrupt Collector Interrupt Register 118 (HW_ICOLL_INTERRUPT118) 32 R/W 0000_0000h 5.4.128/344 8000_0890 Interrupt Collector Interrupt Register 119 (HW_ICOLL_INTERRUPT119) 32 R/W 0000_0000h 5.4.129/345 8000_08A0 Interrupt Collector Interrupt Register 120 (HW_ICOLL_INTERRUPT120) 32 R/W 0000_0000h 5.4.130/347 8000_08B0 Interrupt Collector Interrupt Register 121 (HW_ICOLL_INTERRUPT121) 32 R/W 0000_0000h 5.4.131/348 8000_08C0 Interrupt Collector Interrupt Register 122 (HW_ICOLL_INTERRUPT122) 32 R/W 0000_0000h 5.4.132/350 8000_08D0 Interrupt Collector Interrupt Register 123 (HW_ICOLL_INTERRUPT123) 32 R/W 0000_0000h 5.4.133/351 8000_08E0 Interrupt Collector Interrupt Register 124 (HW_ICOLL_INTERRUPT124) 32 R/W 0000_0000h 5.4.134/353 8000_08F0 Interrupt Collector Interrupt Register 125 (HW_ICOLL_INTERRUPT125) 32 R/W 0000_0000h 5.4.135/354 8000_0900 Interrupt Collector Interrupt Register 126 (HW_ICOLL_INTERRUPT126) 32 R/W 0000_0000h 5.4.136/356 8000_0910 Interrupt Collector Interrupt Register 127 (HW_ICOLL_INTERRUPT127) 32 R/W 0000_0000h 5.4.137/357 8000_1120 Interrupt Collector Debug Register 0 (HW_ICOLL_DEBUG) 32 R 0000_0000h 5.4.138/359 8000_1130 Interrupt Collector Debug Read Register 0 (HW_ICOLL_DBGREAD0) 32 R ECA9_4567h 5.4.139/360 8000_1140 Interrupt Collector Debug Read Register 1 (HW_ICOLL_DBGREAD1) 32 R 1356_DA98h 5.4.140/361 8000_1150 Interrupt Collector Debug Flag Register (HW_ICOLL_DBGFLAG) 32 R/W 0000_0000h 5.4.141/362 8000_1160 Interrupt Collector Debug Read Request Register 0 (HW_ICOLL_DBGREQUEST0) 32 R 0000_0000h 5.4.142/363 8000_1170 Interrupt Collector Debug Read Request Register 1 (HW_ICOLL_DBGREQUEST1) 32 R 0000_0000h 5.4.143/363 8000_1180 Interrupt Collector Debug Read Request Register 2 (HW_ICOLL_DBGREQUEST2) 32 R 0000_0000h 5.4.144/364 8000_1190 Interrupt Collector Debug Read Request Register 3 (HW_ICOLL_DBGREQUEST3) 32 R 0000_0000h 5.4.145/365 8000_11E0 Interrupt Collector Version Register (HW_ICOLL_VERSION) 32 R 0301_0000h 5.4.146/365 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 157 Programmable Registers 5.4.1 Interrupt Collector Interrupt Vector Address Register (HW_ICOLL_VECTOR) This register is read by the Interrupt Service Routine using a load PC instruction. The priority logic presents the vector address of the next IRQ interrupt to be processed by the CPU. The vector address is held until a new ISR is entered.. HW_ICOLL_VECTOR: 0x000 HW_ICOLL_VECTOR_SET: 0x004 HW_ICOLL_VECTOR_CLR: 0x008 HW_ICOLL_VECTOR_TOG: 0x00C This register mediates the vectored interrupt collectors interface with the CPU when it enters the IRQ exception trap. The exception trap should have a LDPC instruction from this address. EXAMPLE LDPC HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018 Address: 8000_0000h base + 0h offset = 8000_0000h Bit 31 30 29 28 27 26 25 R Bit 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RSRVD1 IRQVECTOR W Reset 23 IRQVECTOR W Reset 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_VECTOR field descriptions Field Description 31-2 IRQVECTOR This register presents the vector address for the interrupt currently active on the CPU IRQ input. Writing to this register notifies the interrupt collector that the interrupt service routine for the current interrupt has been entered (alternatively when ARM_RSE_MODE is set, reading this register is required). RSRVD1 Always write zeroes to this field. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 158 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.2 Interrupt Collector Level Acknowledge Register (HW_ICOLL_LEVELACK) The Interrupt Collector Level Acknowledge Register is used by software to indicate the completion of an interrupt on a specific level. This register is written to advance the ICOLL internal IRQ state machine. It advances from an in-service on a level state to the next pending interrupt level or to the idle state. This register is written at the very end of an interrupt service routine. If nesting is used then the CPU IRQ must be turned on before writing to this register to avoid a race condition in the CPU interrupt hardware. WARNING: the value written to the levelack register is decoded not binary, i.e. 8, 4, 2, 1. EXAMPLE HW_ICOLL_LEVELACK_WR(HW_ICOLL_LEVELACK__LEVEL3); Address: 8000_0000h base + 10h offset = 8000_0010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD1 R IRQLEVELACK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_LEVELACK field descriptions Field 31-4 RSRVD1 Description Any value can be written to this bitfield. Writes are ignored. IRQLEVELACK This bitfield is written by the processor to acknowledge the completion of an interrupt. The value written must correspond to the priority level of the completed interrupt 0x1 0x2 0x4 0x8 LEVEL0 -- level 0 LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 159 Programmable Registers 5.4.3 Interrupt Collector Control Register (HW_ICOLL_CTRL) The Interrupt Collector Control Register provides overall control of interrupts being routed to the CPU. This register is not at offset zero from the block base because that location is needed for single 32 bit instructions to be placed in the exception vector location. HW_ICOLL_CTRL: 0x020 HW_ICOLL_CTRL_SET: 0x024 HW_ICOLL_CTRL_CLR: 0x028 HW_ICOLL_CTRL_TOG: 0x02C This register handles the overall control of the interrupt collector, including soft reset and clock gate. In addition, it handles state machine variations like NO_NESTING and ARM read side effect processing on the vector address register. EXAMPLE HW_ICOLL_CTRL_CLR(BM_ICOLL_CTRL_SFTRST | BM_ICOLL_CTRL_SFTRST ); 28 27 26 25 24 21 20 19 18 17 16 VECTOR_PITCH IRQ_FINAL_ENABLE 29 FIQ_FINAL_ENABLE 30 ARM_RSE_MODE 31 NO_NESTING Bit BYPASS_FSM Address: 8000_0000h base + 20h offset = 8000_0020h 23 22 0 0 0 1 1 RSRVD3 SFTRST CLKGATE R 1 1 W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 160 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 HW_ICOLL_CTRL field descriptions Field 31 SFTRST Description When set to one, this bit causes a soft reset to the entire interrupt collector. This bit must be turned off for normal operation. 0x0 0x1 30 CLKGATE When set to one, this bit causes all clocks within the interrupt collector to be gated off. NOTE: Do not set this bit at the same time as SFTRST. Doing so, causes the soft reset to have no effect. Setting SFTRST will cause the CLKGATE bit to set automatically four clocks later. 0x0 0x1 29-24 RSRVD3 RUN -- Allow the interrupt collector to operate normally. IN_RESET -- Hold the interrupt collector in its reset state. RUN -- Enable clocks for normal operation of interrupt collector. NO_CLOCKS -- disable clocking within the interrupt collector. Always write zeroes to this bitfield. 23-21 When an interrupt occurs one of the 128 input requests becomes the winning bit number, i.e. 127. This bit VECTOR_PITCH field selects one of eight constant multiplier values to multiply the winning bit number. The multiplied bit number is added to the vector table base to become the vector address. 0x0 and 0x1 yield a multiplier of 4 bytes. 0x2 yields a multiplier of 8 bytes while 0x3 yields a multiplier of 12 bytes, that is, (8 + 4) bytes per step. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 20 BYPASS_FSM DEFAULT_BY4 -- one word pitch BY4 -- one word pitch BY8 -- two word pitch BY12 -- three word pitch BY16 -- four word pitch BY20 -- five word pitch BY24 -- six word pitch BY28 -- seven word pitch Set this bit to one to bypass the FSM control of the request holding register and the vector address. With this bit set to one, the vector address register is continuously updated as interrupt requests come in. Turn off all enable bits and walk once through the software interrupts, observing the vector address changes. Set to zero for normal operation. This control is included as a test mode, and is not intended for use by a real application. 0x0 0x1 NORMAL -- Normal BYPASS -- no FSM handshake with CPU Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 161 Programmable Registers HW_ICOLL_CTRL field descriptions (continued) Field 19 NO_NESTING Description Set this bit to one disable interrupt level nesting, that is, higher priority interrupt interrupting lower priority. For normal operation, set this bit to zero. 0x0 0x1 NORMAL -- Normal NO_NEST -- no support for interrupt nesting 18 ARM_RSE_ MODE Set this bit to one enable the ARM-style read side effect associated with the vector address register. In this mode, interrupt inservice is signalled by the read of the HW_ICOLL_VECTOR register to acquire the interrupt vector address. Set this bit to zero for normal operation, in which the ISR signals inservice explicitly by means of a write to the HW_ICOLL_VECTOR register. 17 FIQ_FINAL_ ENABLE Set this bit to one to enable the final FIQ output to the CPU. Set this bit to zero for testing the interrupt collector without causing actual CPU interrupts. 16 IRQ_FINAL_ ENABLE Set this bit to one to enable the final IRQ output to the CPU. Set this bit to zero for testing the interrupt collector without causing actual CPU interrupts. RSRVD1 0x0 0x1 0x0 0x1 DISABLE -- Disable ENABLE -- Enable DISABLE -- Disable ENABLE -- Enable Always write zeroes to this bitfield. 5.4.4 Interrupt Collector Interrupt Vector Base Address Register (HW_ICOLL_VBASE) This register is used by the priority logic to generate a unique vector address for each of the 80 interrupt request lines coming into the interrupt collector. The vector address is formed by multiplying the interrupt bit number by 4 and adding it to the vector base address. HW_ICOLL_VBASE: 0x040 HW_ICOLL_VBASE_SET: 0x044 HW_ICOLL_VBASE_CLR: 0x048 HW_ICOLL_VBASE_TOG: 0x04C This register provides a mechanism to specify the base address of the interrupt vector table. It is used in the computation of the value supplied in HW_ICOLL_VECTOR register. EXAMPLE HW_ICOLL_VBASE_WR(pInterruptVectorTable); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 162 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 40h offset = 8000_0040h Bit 31 30 29 28 27 26 25 R 23 22 21 20 19 18 17 16 TABLE_ADDRESS W Reset Bit 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RSRVD1 TABLE_ADDRESS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_VBASE field descriptions Field Description 31-2 TABLE_ ADDRESS This bitfield holds the upper 30 bits of the base address of the vector table. RSRVD1 Always write zeroes to this bitfield. 5.4.5 Interrupt Collector Status Register (HW_ICOLL_STAT) Read only view into various internal states, including the Vector number of the current interupt. This register is used to test interrupt collector state machine and its associated request holding register. EXAMPLE if(HW_ICOLL_STAT_VECTOR_NUMBER_READ() == 0x00000017) ISR_vector_23(); // ISR for vector 23 decimal, 17 hex Address: 8000_0000h base + 70h offset = 8000_0070h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RSRVD1 R 5 4 3 2 1 0 VECTOR_NUMBER W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 HW_ICOLL_STAT field descriptions Field 31-7 RSRVD1 VECTOR_ NUMBER Description Always write zeroes to this bitfield. Vector number of current interrupt. Multiply by 4 * HW_ICOLL_CTRL[VECTOR_PITCH] and add to vector base address to obtain the value in HW_ICOLL_VECTOR. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 163 Programmable Registers 5.4.6 Interrupt Collector Raw Interrupt Input Register 0 (HW_ICOLL_RAW0) The lower 32 interrupt hardware-source states are visible in this read-only register. HW_ICOLL_RAW0: 0x0A0 HW_ICOLL_RAW0_SET: 0x0A4 HW_ICOLL_RAW0_CLR: 0x0A8 HW_ICOLL_RAW0_TOG: 0x0AC This register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. Its purpose is to improve diagnostic observability. Note that these only capture the state of hardware interrupt sources. EXAMPLE ulTest = HW_ICOLL_RAW0.RAW_IRQS; Address: 8000_0000h base + A0h offset = 8000_00A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAW_IRQS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_RAW0 field descriptions Field RAW_IRQS Description read-only view of the lower 32 hardware interrupt request bits. 5.4.7 Interrupt Collector Raw Interrupt Input Register 1 (HW_ICOLL_RAW1) Interrupt hardware-source states 32-63 are visible in this read-only register. HW_ICOLL_RAW1: 0x0B0 HW_ICOLL_RAW1_SET: 0x0B4 HW_ICOLL_RAW1_CLR: 0x0B8 HW_ICOLL_RAW1_TOG: 0x0BC i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 164 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) This register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. The purpose is to improve diagnostic observability. Note that these only capture the state of hardware interrupt sources. EXAMPLE ulTest = HW_ICOLL_RAW0.RAW_IRQS; Address: 8000_0000h base + B0h offset = 8000_00B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAW_IRQS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_RAW1 field descriptions Field RAW_IRQS Description read-only view of hardware interrupt request bits 32-63. 5.4.8 Interrupt Collector Raw Interrupt Input Register 2 (HW_ICOLL_RAW2) Interrupt hardware-source states 64-95 are visible in this read-only register. HW_ICOLL_RAW2: 0x0C0 HW_ICOLL_RAW2_SET: 0x0C4 HW_ICOLL_RAW2_CLR: 0x0C8 HW_ICOLL_RAW2_TOG: 0x0CC This register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. The purpose is to improve diagnostic observability. Note that these only capture the state of hardware interrupt sources. EXAMPLE ulTest = HW_ICOLL_RAW0.RAW_IRQS; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 165 Programmable Registers Address: 8000_0000h base + C0h offset = 8000_00C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAW_IRQS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_RAW2 field descriptions Field Description RAW_IRQS read-only view of hardware interrupt request bits 64-95. 5.4.9 Interrupt Collector Raw Interrupt Input Register 3 (HW_ICOLL_RAW3) Interrupt hardware-source states 96-127 are visible in this read-only register. HW_ICOLL_RAW3: 0x0D0 HW_ICOLL_RAW3_SET: 0x0D4 HW_ICOLL_RAW3_CLR: 0x0D8 HW_ICOLL_RAW3_TOG: 0x0DC This register provides a read-only view of the raw interrupt request lines coming from various parts of the chip. The purpose is to improve diagnostic observability. Note that these only capture the state of hardware interrupt sources. EXAMPLE ulTest = HW_ICOLL_RAW0.RAW_IRQS; Address: 8000_0000h base + D0h offset = 8000_00D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAW_IRQS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_RAW3 field descriptions Field RAW_IRQS Description read-only view of hardware interrupt request bits 96-127. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 166 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.10 Interrupt Collector Interrupt Register 0 (HW_ICOLL_INTERRUPT0) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT0: 0x120 HW_ICOLL_INTERRUPT0_SET: 0x124 HW_ICOLL_INTERRUPT0_CLR: 0x128 HW_ICOLL_INTERRUPT0_TOG: 0x12C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT0_SET(0,0x00000001); Address: 8000_0000h base + 120h offset = 8000_0120h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 167 Programmable Registers HW_ICOLL_INTERRUPT0 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.11 Interrupt Collector Interrupt Register 1 (HW_ICOLL_INTERRUPT1) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT1: 0x130 HW_ICOLL_INTERRUPT1_SET: 0x134 HW_ICOLL_INTERRUPT1_CLR: 0x138 HW_ICOLL_INTERRUPT1_TOG: 0x13C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT1_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 168 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 130h offset = 8000_0130h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT1 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 169 Programmable Registers 5.4.12 Interrupt Collector Interrupt Register 2 (HW_ICOLL_INTERRUPT2) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT2: 0x140 HW_ICOLL_INTERRUPT2_SET: 0x144 HW_ICOLL_INTERRUPT2_CLR: 0x148 HW_ICOLL_INTERRUPT2_TOG: 0x14C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT2_SET(0,0x00000001); Address: 8000_0000h base + 140h offset = 8000_0140h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 170 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT2 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.13 Interrupt Collector Interrupt Register 3 (HW_ICOLL_INTERRUPT3) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT3: 0x150 HW_ICOLL_INTERRUPT3_SET: 0x154 HW_ICOLL_INTERRUPT3_CLR: 0x158 HW_ICOLL_INTERRUPT3_TOG: 0x15C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT3_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 171 Programmable Registers Address: 8000_0000h base + 150h offset = 8000_0150h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT3 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 172 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.14 Interrupt Collector Interrupt Register 4 (HW_ICOLL_INTERRUPT4) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT4: 0x160 HW_ICOLL_INTERRUPT4_SET: 0x164 HW_ICOLL_INTERRUPT4_CLR: 0x168 HW_ICOLL_INTERRUPT4_TOG: 0x16C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT4_SET(0,0x00000001); Address: 8000_0000h base + 160h offset = 8000_0160h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 173 Programmable Registers HW_ICOLL_INTERRUPT4 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.15 Interrupt Collector Interrupt Register 5 (HW_ICOLL_INTERRUPT5) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT5: 0x170 HW_ICOLL_INTERRUPT5_SET: 0x174 HW_ICOLL_INTERRUPT5_CLR: 0x178 HW_ICOLL_INTERRUPT5_TOG: 0x17C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT5_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 174 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 170h offset = 8000_0170h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT5 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 175 Programmable Registers 5.4.16 Interrupt Collector Interrupt Register 6 (HW_ICOLL_INTERRUPT6) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT6: 0x180 HW_ICOLL_INTERRUPT6_SET: 0x184 HW_ICOLL_INTERRUPT6_CLR: 0x188 HW_ICOLL_INTERRUPT6_TOG: 0x18C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT6_SET(0,0x00000001); Address: 8000_0000h base + 180h offset = 8000_0180h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 176 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT6 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.17 Interrupt Collector Interrupt Register 7 (HW_ICOLL_INTERRUPT7) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT7: 0x190 HW_ICOLL_INTERRUPT7_SET: 0x194 HW_ICOLL_INTERRUPT7_CLR: 0x198 HW_ICOLL_INTERRUPT7_TOG: 0x19C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT7_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 177 Programmable Registers Address: 8000_0000h base + 190h offset = 8000_0190h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT7 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 178 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.18 Interrupt Collector Interrupt Register 8 (HW_ICOLL_INTERRUPT8) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT8: 0x1A0 HW_ICOLL_INTERRUPT8_SET: 0x1A4 HW_ICOLL_INTERRUPT8_CLR: 0x1A8 HW_ICOLL_INTERRUPT8_TOG: 0x1AC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT8_SET(0,0x00000001); Address: 8000_0000h base + 1A0h offset = 8000_01A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 179 Programmable Registers HW_ICOLL_INTERRUPT8 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.19 Interrupt Collector Interrupt Register 9 (HW_ICOLL_INTERRUPT9) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT9: 0x1B0 HW_ICOLL_INTERRUPT9_SET: 0x1B4 HW_ICOLL_INTERRUPT9_CLR: 0x1B8 HW_ICOLL_INTERRUPT9_TOG: 0x1BC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT9_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 180 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 1B0h offset = 8000_01B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT9 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 181 Programmable Registers 5.4.20 Interrupt Collector Interrupt Register 10 (HW_ICOLL_INTERRUPT10) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT10: 0x1C0 HW_ICOLL_INTERRUPT10_SET: 0x1C4 HW_ICOLL_INTERRUPT10_CLR: 0x1C8 HW_ICOLL_INTERRUPT10_TOG: 0x1CC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT10_SET(0,0x00000001); Address: 8000_0000h base + 1C0h offset = 8000_01C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 182 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT10 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.21 Interrupt Collector Interrupt Register 11 (HW_ICOLL_INTERRUPT11) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT11: 0x1D0 HW_ICOLL_INTERRUPT11_SET: 0x1D4 HW_ICOLL_INTERRUPT11_CLR: 0x1D8 HW_ICOLL_INTERRUPT11_TOG: 0x1DC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT11_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 183 Programmable Registers Address: 8000_0000h base + 1D0h offset = 8000_01D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT11 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 184 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.22 Interrupt Collector Interrupt Register 12 (HW_ICOLL_INTERRUPT12) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT12: 0x1E0 HW_ICOLL_INTERRUPT12_SET: 0x1E4 HW_ICOLL_INTERRUPT12_CLR: 0x1E8 HW_ICOLL_INTERRUPT12_TOG: 0x1EC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT12_SET(0,0x00000001); Address: 8000_0000h base + 1E0h offset = 8000_01E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 185 Programmable Registers HW_ICOLL_INTERRUPT12 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.23 Interrupt Collector Interrupt Register 13 (HW_ICOLL_INTERRUPT13) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT13: 0x1F0 HW_ICOLL_INTERRUPT13_SET: 0x1F4 HW_ICOLL_INTERRUPT13_CLR: 0x1F8 HW_ICOLL_INTERRUPT13_TOG: 0x1FC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT13_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 186 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 1F0h offset = 8000_01F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT13 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 187 Programmable Registers 5.4.24 Interrupt Collector Interrupt Register 14 (HW_ICOLL_INTERRUPT14) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT14: 0x200 HW_ICOLL_INTERRUPT14_SET: 0x204 HW_ICOLL_INTERRUPT14_CLR: 0x208 HW_ICOLL_INTERRUPT14_TOG: 0x20C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT14_SET(0,0x00000001); Address: 8000_0000h base + 200h offset = 8000_0200h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 188 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT14 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.25 Interrupt Collector Interrupt Register 15 (HW_ICOLL_INTERRUPT15) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT15: 0x210 HW_ICOLL_INTERRUPT15_SET: 0x214 HW_ICOLL_INTERRUPT15_CLR: 0x218 HW_ICOLL_INTERRUPT15_TOG: 0x21C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT15_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 189 Programmable Registers Address: 8000_0000h base + 210h offset = 8000_0210h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT15 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 190 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.26 Interrupt Collector Interrupt Register 16 (HW_ICOLL_INTERRUPT16) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT16: 0x220 HW_ICOLL_INTERRUPT16_SET: 0x224 HW_ICOLL_INTERRUPT16_CLR: 0x228 HW_ICOLL_INTERRUPT16_TOG: 0x22C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT16_SET(0,0x00000001); Address: 8000_0000h base + 220h offset = 8000_0220h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 191 Programmable Registers HW_ICOLL_INTERRUPT16 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.27 Interrupt Collector Interrupt Register 17 (HW_ICOLL_INTERRUPT17) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT17: 0x230 HW_ICOLL_INTERRUPT17_SET: 0x234 HW_ICOLL_INTERRUPT17_CLR: 0x238 HW_ICOLL_INTERRUPT17_TOG: 0x23C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT17_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 192 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 230h offset = 8000_0230h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT17 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 193 Programmable Registers 5.4.28 Interrupt Collector Interrupt Register 18 (HW_ICOLL_INTERRUPT18) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT18: 0x240 HW_ICOLL_INTERRUPT18_SET: 0x244 HW_ICOLL_INTERRUPT18_CLR: 0x248 HW_ICOLL_INTERRUPT18_TOG: 0x24C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT18_SET(0,0x00000001); Address: 8000_0000h base + 240h offset = 8000_0240h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 194 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT18 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.29 Interrupt Collector Interrupt Register 19 (HW_ICOLL_INTERRUPT19) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT19: 0x250 HW_ICOLL_INTERRUPT19_SET: 0x254 HW_ICOLL_INTERRUPT19_CLR: 0x258 HW_ICOLL_INTERRUPT19_TOG: 0x25C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT19_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 195 Programmable Registers Address: 8000_0000h base + 250h offset = 8000_0250h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT19 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 196 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.30 Interrupt Collector Interrupt Register 20 (HW_ICOLL_INTERRUPT20) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT20: 0x260 HW_ICOLL_INTERRUPT20_SET: 0x264 HW_ICOLL_INTERRUPT20_CLR: 0x268 HW_ICOLL_INTERRUPT20_TOG: 0x26C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT20_SET(0,0x00000001); Address: 8000_0000h base + 260h offset = 8000_0260h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 197 Programmable Registers HW_ICOLL_INTERRUPT20 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.31 Interrupt Collector Interrupt Register 21 (HW_ICOLL_INTERRUPT21) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT21: 0x270 HW_ICOLL_INTERRUPT21_SET: 0x274 HW_ICOLL_INTERRUPT21_CLR: 0x278 HW_ICOLL_INTERRUPT21_TOG: 0x27C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT21_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 198 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 270h offset = 8000_0270h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT21 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 199 Programmable Registers 5.4.32 Interrupt Collector Interrupt Register 22 (HW_ICOLL_INTERRUPT22) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT22: 0x280 HW_ICOLL_INTERRUPT22_SET: 0x284 HW_ICOLL_INTERRUPT22_CLR: 0x288 HW_ICOLL_INTERRUPT22_TOG: 0x28C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT22_SET(0,0x00000001); Address: 8000_0000h base + 280h offset = 8000_0280h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 200 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT22 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.33 Interrupt Collector Interrupt Register 23 (HW_ICOLL_INTERRUPT23) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT23: 0x290 HW_ICOLL_INTERRUPT23_SET: 0x294 HW_ICOLL_INTERRUPT23_CLR: 0x298 HW_ICOLL_INTERRUPT23_TOG: 0x29C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT23_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 201 Programmable Registers Address: 8000_0000h base + 290h offset = 8000_0290h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT23 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 202 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.34 Interrupt Collector Interrupt Register 24 (HW_ICOLL_INTERRUPT24) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT24: 0x2A0 HW_ICOLL_INTERRUPT24_SET: 0x2A4 HW_ICOLL_INTERRUPT24_CLR: 0x2A8 HW_ICOLL_INTERRUPT24_TOG: 0x2AC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT24_SET(0,0x00000001); Address: 8000_0000h base + 2A0h offset = 8000_02A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 203 Programmable Registers HW_ICOLL_INTERRUPT24 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.35 Interrupt Collector Interrupt Register 25 (HW_ICOLL_INTERRUPT25) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT25: 0x2B0 HW_ICOLL_INTERRUPT25_SET: 0x2B4 HW_ICOLL_INTERRUPT25_CLR: 0x2B8 HW_ICOLL_INTERRUPT25_TOG: 0x2BC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT25_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 204 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 2B0h offset = 8000_02B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT25 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 205 Programmable Registers 5.4.36 Interrupt Collector Interrupt Register 26 (HW_ICOLL_INTERRUPT26) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT26: 0x2C0 HW_ICOLL_INTERRUPT26_SET: 0x2C4 HW_ICOLL_INTERRUPT26_CLR: 0x2C8 HW_ICOLL_INTERRUPT26_TOG: 0x2CC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT26_SET(0,0x00000001); Address: 8000_0000h base + 2C0h offset = 8000_02C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 206 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT26 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.37 Interrupt Collector Interrupt Register 27 (HW_ICOLL_INTERRUPT27) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT27: 0x2D0 HW_ICOLL_INTERRUPT27_SET: 0x2D4 HW_ICOLL_INTERRUPT27_CLR: 0x2D8 HW_ICOLL_INTERRUPT27_TOG: 0x2DC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT27_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 207 Programmable Registers Address: 8000_0000h base + 2D0h offset = 8000_02D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT27 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 208 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.38 Interrupt Collector Interrupt Register 28 (HW_ICOLL_INTERRUPT28) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT28: 0x2E0 HW_ICOLL_INTERRUPT28_SET: 0x2E4 HW_ICOLL_INTERRUPT28_CLR: 0x2E8 HW_ICOLL_INTERRUPT28_TOG: 0x2EC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT28_SET(0,0x00000001); Address: 8000_0000h base + 2E0h offset = 8000_02E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 209 Programmable Registers HW_ICOLL_INTERRUPT28 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.39 Interrupt Collector Interrupt Register 29 (HW_ICOLL_INTERRUPT29) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT29: 0x2F0 HW_ICOLL_INTERRUPT29_SET: 0x2F4 HW_ICOLL_INTERRUPT29_CLR: 0x2F8 HW_ICOLL_INTERRUPT29_TOG: 0x2FC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT29_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 210 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 2F0h offset = 8000_02F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT29 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 211 Programmable Registers 5.4.40 Interrupt Collector Interrupt Register 30 (HW_ICOLL_INTERRUPT30) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT30: 0x300 HW_ICOLL_INTERRUPT30_SET: 0x304 HW_ICOLL_INTERRUPT30_CLR: 0x308 HW_ICOLL_INTERRUPT30_TOG: 0x30C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT30_SET(0,0x00000001); Address: 8000_0000h base + 300h offset = 8000_0300h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 212 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT30 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.41 Interrupt Collector Interrupt Register 31 (HW_ICOLL_INTERRUPT31) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT31: 0x310 HW_ICOLL_INTERRUPT31_SET: 0x314 HW_ICOLL_INTERRUPT31_CLR: 0x318 HW_ICOLL_INTERRUPT31_TOG: 0x31C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT31_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 213 Programmable Registers Address: 8000_0000h base + 310h offset = 8000_0310h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT31 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 214 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.42 Interrupt Collector Interrupt Register 32 (HW_ICOLL_INTERRUPT32) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT32: 0x320 HW_ICOLL_INTERRUPT32_SET: 0x324 HW_ICOLL_INTERRUPT32_CLR: 0x328 HW_ICOLL_INTERRUPT32_TOG: 0x32C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT32_SET(0,0x00000001); Address: 8000_0000h base + 320h offset = 8000_0320h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 215 Programmable Registers HW_ICOLL_INTERRUPT32 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.43 Interrupt Collector Interrupt Register 33 (HW_ICOLL_INTERRUPT33) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT33: 0x330 HW_ICOLL_INTERRUPT33_SET: 0x334 HW_ICOLL_INTERRUPT33_CLR: 0x338 HW_ICOLL_INTERRUPT33_TOG: 0x33C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT33_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 216 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 330h offset = 8000_0330h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT33 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 217 Programmable Registers 5.4.44 Interrupt Collector Interrupt Register 34 (HW_ICOLL_INTERRUPT34) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT34: 0x340 HW_ICOLL_INTERRUPT34_SET: 0x344 HW_ICOLL_INTERRUPT34_CLR: 0x348 HW_ICOLL_INTERRUPT34_TOG: 0x34C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT34_SET(0,0x00000001); Address: 8000_0000h base + 340h offset = 8000_0340h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 218 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT34 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.45 Interrupt Collector Interrupt Register 35 (HW_ICOLL_INTERRUPT35) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT35: 0x350 HW_ICOLL_INTERRUPT35_SET: 0x354 HW_ICOLL_INTERRUPT35_CLR: 0x358 HW_ICOLL_INTERRUPT35_TOG: 0x35C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT35_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 219 Programmable Registers Address: 8000_0000h base + 350h offset = 8000_0350h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT35 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 220 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.46 Interrupt Collector Interrupt Register 36 (HW_ICOLL_INTERRUPT36) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT36: 0x360 HW_ICOLL_INTERRUPT36_SET: 0x364 HW_ICOLL_INTERRUPT36_CLR: 0x368 HW_ICOLL_INTERRUPT36_TOG: 0x36C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT36_SET(0,0x00000001); Address: 8000_0000h base + 360h offset = 8000_0360h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 221 Programmable Registers HW_ICOLL_INTERRUPT36 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.47 Interrupt Collector Interrupt Register 37 (HW_ICOLL_INTERRUPT37) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT37: 0x370 HW_ICOLL_INTERRUPT37_SET: 0x374 HW_ICOLL_INTERRUPT37_CLR: 0x378 HW_ICOLL_INTERRUPT37_TOG: 0x37C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT37_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 222 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 370h offset = 8000_0370h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT37 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 223 Programmable Registers 5.4.48 Interrupt Collector Interrupt Register 38 (HW_ICOLL_INTERRUPT38) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT38: 0x380 HW_ICOLL_INTERRUPT38_SET: 0x384 HW_ICOLL_INTERRUPT38_CLR: 0x388 HW_ICOLL_INTERRUPT38_TOG: 0x38C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT38_SET(0,0x00000001); Address: 8000_0000h base + 380h offset = 8000_0380h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 224 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT38 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.49 Interrupt Collector Interrupt Register 39 (HW_ICOLL_INTERRUPT39) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT39: 0x390 HW_ICOLL_INTERRUPT39_SET: 0x394 HW_ICOLL_INTERRUPT39_CLR: 0x398 HW_ICOLL_INTERRUPT39_TOG: 0x39C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT39_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 225 Programmable Registers Address: 8000_0000h base + 390h offset = 8000_0390h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT39 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 226 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.50 Interrupt Collector Interrupt Register 40 (HW_ICOLL_INTERRUPT40) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT40: 0x3A0 HW_ICOLL_INTERRUPT40_SET: 0x3A4 HW_ICOLL_INTERRUPT40_CLR: 0x3A8 HW_ICOLL_INTERRUPT40_TOG: 0x3AC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT40_SET(0,0x00000001); Address: 8000_0000h base + 3A0h offset = 8000_03A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 227 Programmable Registers HW_ICOLL_INTERRUPT40 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.51 Interrupt Collector Interrupt Register 41 (HW_ICOLL_INTERRUPT41) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT41: 0x3B0 HW_ICOLL_INTERRUPT41_SET: 0x3B4 HW_ICOLL_INTERRUPT41_CLR: 0x3B8 HW_ICOLL_INTERRUPT41_TOG: 0x3BC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT41_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 228 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 3B0h offset = 8000_03B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT41 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 229 Programmable Registers 5.4.52 Interrupt Collector Interrupt Register 42 (HW_ICOLL_INTERRUPT42) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT42: 0x3C0 HW_ICOLL_INTERRUPT42_SET: 0x3C4 HW_ICOLL_INTERRUPT42_CLR: 0x3C8 HW_ICOLL_INTERRUPT42_TOG: 0x3CC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT42_SET(0,0x00000001); Address: 8000_0000h base + 3C0h offset = 8000_03C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 230 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT42 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.53 Interrupt Collector Interrupt Register 43 (HW_ICOLL_INTERRUPT43) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT43: 0x3D0 HW_ICOLL_INTERRUPT43_SET: 0x3D4 HW_ICOLL_INTERRUPT43_CLR: 0x3D8 HW_ICOLL_INTERRUPT43_TOG: 0x3DC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT43_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 231 Programmable Registers Address: 8000_0000h base + 3D0h offset = 8000_03D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT43 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 232 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.54 Interrupt Collector Interrupt Register 44 (HW_ICOLL_INTERRUPT44) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT44: 0x3E0 HW_ICOLL_INTERRUPT44_SET: 0x3E4 HW_ICOLL_INTERRUPT44_CLR: 0x3E8 HW_ICOLL_INTERRUPT44_TOG: 0x3EC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT44_SET(0,0x00000001); Address: 8000_0000h base + 3E0h offset = 8000_03E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 233 Programmable Registers HW_ICOLL_INTERRUPT44 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.55 Interrupt Collector Interrupt Register 45 (HW_ICOLL_INTERRUPT45) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT45: 0x3F0 HW_ICOLL_INTERRUPT45_SET: 0x3F4 HW_ICOLL_INTERRUPT45_CLR: 0x3F8 HW_ICOLL_INTERRUPT45_TOG: 0x3FC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT45_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 234 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 3F0h offset = 8000_03F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT45 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 235 Programmable Registers 5.4.56 Interrupt Collector Interrupt Register 46 (HW_ICOLL_INTERRUPT46) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT46: 0x400 HW_ICOLL_INTERRUPT46_SET: 0x404 HW_ICOLL_INTERRUPT46_CLR: 0x408 HW_ICOLL_INTERRUPT46_TOG: 0x40C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT46_SET(0,0x00000001); Address: 8000_0000h base + 400h offset = 8000_0400h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 236 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT46 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.57 Interrupt Collector Interrupt Register 47 (HW_ICOLL_INTERRUPT47) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT47: 0x410 HW_ICOLL_INTERRUPT47_SET: 0x414 HW_ICOLL_INTERRUPT47_CLR: 0x418 HW_ICOLL_INTERRUPT47_TOG: 0x41C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT47_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 237 Programmable Registers Address: 8000_0000h base + 410h offset = 8000_0410h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT47 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 238 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.58 Interrupt Collector Interrupt Register 48 (HW_ICOLL_INTERRUPT48) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT48: 0x420 HW_ICOLL_INTERRUPT48_SET: 0x424 HW_ICOLL_INTERRUPT48_CLR: 0x428 HW_ICOLL_INTERRUPT48_TOG: 0x42C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT48_SET(0,0x00000001); Address: 8000_0000h base + 420h offset = 8000_0420h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 239 Programmable Registers HW_ICOLL_INTERRUPT48 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.59 Interrupt Collector Interrupt Register 49 (HW_ICOLL_INTERRUPT49) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT49: 0x430 HW_ICOLL_INTERRUPT49_SET: 0x434 HW_ICOLL_INTERRUPT49_CLR: 0x438 HW_ICOLL_INTERRUPT49_TOG: 0x43C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT49_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 240 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 430h offset = 8000_0430h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT49 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 241 Programmable Registers 5.4.60 Interrupt Collector Interrupt Register 50 (HW_ICOLL_INTERRUPT50) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT50: 0x440 HW_ICOLL_INTERRUPT50_SET: 0x444 HW_ICOLL_INTERRUPT50_CLR: 0x448 HW_ICOLL_INTERRUPT50_TOG: 0x44C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT50_SET(0,0x00000001); Address: 8000_0000h base + 440h offset = 8000_0440h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 242 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT50 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.61 Interrupt Collector Interrupt Register 51 (HW_ICOLL_INTERRUPT51) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT51: 0x450 HW_ICOLL_INTERRUPT51_SET: 0x454 HW_ICOLL_INTERRUPT51_CLR: 0x458 HW_ICOLL_INTERRUPT51_TOG: 0x45C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT51_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 243 Programmable Registers Address: 8000_0000h base + 450h offset = 8000_0450h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT51 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 244 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.62 Interrupt Collector Interrupt Register 52 (HW_ICOLL_INTERRUPT52) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT52: 0x460 HW_ICOLL_INTERRUPT52_SET: 0x464 HW_ICOLL_INTERRUPT52_CLR: 0x468 HW_ICOLL_INTERRUPT52_TOG: 0x46C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT52_SET(0,0x00000001); Address: 8000_0000h base + 460h offset = 8000_0460h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 245 Programmable Registers HW_ICOLL_INTERRUPT52 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.63 Interrupt Collector Interrupt Register 53 (HW_ICOLL_INTERRUPT53) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT53: 0x470 HW_ICOLL_INTERRUPT53_SET: 0x474 HW_ICOLL_INTERRUPT53_CLR: 0x478 HW_ICOLL_INTERRUPT53_TOG: 0x47C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT53_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 246 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 470h offset = 8000_0470h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT53 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 247 Programmable Registers 5.4.64 Interrupt Collector Interrupt Register 54 (HW_ICOLL_INTERRUPT54) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT54: 0x480 HW_ICOLL_INTERRUPT54_SET: 0x484 HW_ICOLL_INTERRUPT54_CLR: 0x488 HW_ICOLL_INTERRUPT54_TOG: 0x48C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT54_SET(0,0x00000001); Address: 8000_0000h base + 480h offset = 8000_0480h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 248 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT54 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.65 Interrupt Collector Interrupt Register 55 (HW_ICOLL_INTERRUPT55) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT55: 0x490 HW_ICOLL_INTERRUPT55_SET: 0x494 HW_ICOLL_INTERRUPT55_CLR: 0x498 HW_ICOLL_INTERRUPT55_TOG: 0x49C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT55_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 249 Programmable Registers Address: 8000_0000h base + 490h offset = 8000_0490h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT55 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 250 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.66 Interrupt Collector Interrupt Register 56 (HW_ICOLL_INTERRUPT56) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT56: 0x4A0 HW_ICOLL_INTERRUPT56_SET: 0x4A4 HW_ICOLL_INTERRUPT56_CLR: 0x4A8 HW_ICOLL_INTERRUPT56_TOG: 0x4AC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT56_SET(0,0x00000001); Address: 8000_0000h base + 4A0h offset = 8000_04A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 251 Programmable Registers HW_ICOLL_INTERRUPT56 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.67 Interrupt Collector Interrupt Register 57 (HW_ICOLL_INTERRUPT57) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT57: 0x4B0 HW_ICOLL_INTERRUPT57_SET: 0x4B4 HW_ICOLL_INTERRUPT57_CLR: 0x4B8 HW_ICOLL_INTERRUPT57_TOG: 0x4BC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT57_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 252 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 4B0h offset = 8000_04B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT57 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 253 Programmable Registers 5.4.68 Interrupt Collector Interrupt Register 58 (HW_ICOLL_INTERRUPT58) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT58: 0x4C0 HW_ICOLL_INTERRUPT58_SET: 0x4C4 HW_ICOLL_INTERRUPT58_CLR: 0x4C8 HW_ICOLL_INTERRUPT58_TOG: 0x4CC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT58_SET(0,0x00000001); Address: 8000_0000h base + 4C0h offset = 8000_04C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 254 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT58 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.69 Interrupt Collector Interrupt Register 59 (HW_ICOLL_INTERRUPT59) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT59: 0x4D0 HW_ICOLL_INTERRUPT59_SET: 0x4D4 HW_ICOLL_INTERRUPT59_CLR: 0x4D8 HW_ICOLL_INTERRUPT59_TOG: 0x4DC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT59_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 255 Programmable Registers Address: 8000_0000h base + 4D0h offset = 8000_04D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT59 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 256 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.70 Interrupt Collector Interrupt Register 60 (HW_ICOLL_INTERRUPT60) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT60: 0x4E0 HW_ICOLL_INTERRUPT60_SET: 0x4E4 HW_ICOLL_INTERRUPT60_CLR: 0x4E8 HW_ICOLL_INTERRUPT60_TOG: 0x4EC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT60_SET(0,0x00000001); Address: 8000_0000h base + 4E0h offset = 8000_04E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 257 Programmable Registers HW_ICOLL_INTERRUPT60 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.71 Interrupt Collector Interrupt Register 61 (HW_ICOLL_INTERRUPT61) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT61: 0x4F0 HW_ICOLL_INTERRUPT61_SET: 0x4F4 HW_ICOLL_INTERRUPT61_CLR: 0x4F8 HW_ICOLL_INTERRUPT61_TOG: 0x4FC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT61_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 258 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 4F0h offset = 8000_04F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT61 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 259 Programmable Registers 5.4.72 Interrupt Collector Interrupt Register 62 (HW_ICOLL_INTERRUPT62) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT62: 0x500 HW_ICOLL_INTERRUPT62_SET: 0x504 HW_ICOLL_INTERRUPT62_CLR: 0x508 HW_ICOLL_INTERRUPT62_TOG: 0x50C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT62_SET(0,0x00000001); Address: 8000_0000h base + 500h offset = 8000_0500h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 260 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT62 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.73 Interrupt Collector Interrupt Register 63 (HW_ICOLL_INTERRUPT63) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT63: 0x510 HW_ICOLL_INTERRUPT63_SET: 0x514 HW_ICOLL_INTERRUPT63_CLR: 0x518 HW_ICOLL_INTERRUPT63_TOG: 0x51C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT63_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 261 Programmable Registers Address: 8000_0000h base + 510h offset = 8000_0510h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT63 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 262 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.74 Interrupt Collector Interrupt Register 64 (HW_ICOLL_INTERRUPT64) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT64: 0x520 HW_ICOLL_INTERRUPT64_SET: 0x524 HW_ICOLL_INTERRUPT64_CLR: 0x528 HW_ICOLL_INTERRUPT64_TOG: 0x52C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT64_SET(0,0x00000001); Address: 8000_0000h base + 520h offset = 8000_0520h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 263 Programmable Registers HW_ICOLL_INTERRUPT64 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.75 Interrupt Collector Interrupt Register 65 (HW_ICOLL_INTERRUPT65) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT65: 0x530 HW_ICOLL_INTERRUPT65_SET: 0x534 HW_ICOLL_INTERRUPT65_CLR: 0x538 HW_ICOLL_INTERRUPT65_TOG: 0x53C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT65_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 264 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 530h offset = 8000_0530h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT65 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 265 Programmable Registers 5.4.76 Interrupt Collector Interrupt Register 66 (HW_ICOLL_INTERRUPT66) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT66: 0x540 HW_ICOLL_INTERRUPT66_SET: 0x544 HW_ICOLL_INTERRUPT66_CLR: 0x548 HW_ICOLL_INTERRUPT66_TOG: 0x54C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT66_SET(0,0x00000001); Address: 8000_0000h base + 540h offset = 8000_0540h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 266 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT66 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.77 Interrupt Collector Interrupt Register 67 (HW_ICOLL_INTERRUPT67) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT67: 0x550 HW_ICOLL_INTERRUPT67_SET: 0x554 HW_ICOLL_INTERRUPT67_CLR: 0x558 HW_ICOLL_INTERRUPT67_TOG: 0x55C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT67_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 267 Programmable Registers Address: 8000_0000h base + 550h offset = 8000_0550h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT67 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 268 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.78 Interrupt Collector Interrupt Register 68 (HW_ICOLL_INTERRUPT68) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT68: 0x560 HW_ICOLL_INTERRUPT68_SET: 0x564 HW_ICOLL_INTERRUPT68_CLR: 0x568 HW_ICOLL_INTERRUPT68_TOG: 0x56C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT68_SET(0,0x00000001); Address: 8000_0000h base + 560h offset = 8000_0560h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 269 Programmable Registers HW_ICOLL_INTERRUPT68 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.79 Interrupt Collector Interrupt Register 69 (HW_ICOLL_INTERRUPT69) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT69: 0x570 HW_ICOLL_INTERRUPT69_SET: 0x574 HW_ICOLL_INTERRUPT69_CLR: 0x578 HW_ICOLL_INTERRUPT69_TOG: 0x57C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT69_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 270 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 570h offset = 8000_0570h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT69 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 271 Programmable Registers 5.4.80 Interrupt Collector Interrupt Register 70 (HW_ICOLL_INTERRUPT70) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT70: 0x580 HW_ICOLL_INTERRUPT70_SET: 0x584 HW_ICOLL_INTERRUPT70_CLR: 0x588 HW_ICOLL_INTERRUPT70_TOG: 0x58C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT70_SET(0,0x00000001); Address: 8000_0000h base + 580h offset = 8000_0580h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 272 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT70 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.81 Interrupt Collector Interrupt Register 71 (HW_ICOLL_INTERRUPT71) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT71: 0x590 HW_ICOLL_INTERRUPT71_SET: 0x594 HW_ICOLL_INTERRUPT71_CLR: 0x598 HW_ICOLL_INTERRUPT71_TOG: 0x59C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT71_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 273 Programmable Registers Address: 8000_0000h base + 590h offset = 8000_0590h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT71 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 274 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.82 Interrupt Collector Interrupt Register 72 (HW_ICOLL_INTERRUPT72) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT72: 0x5A0 HW_ICOLL_INTERRUPT72_SET: 0x5A4 HW_ICOLL_INTERRUPT72_CLR: 0x5A8 HW_ICOLL_INTERRUPT72_TOG: 0x5AC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT72_SET(0,0x00000001); Address: 8000_0000h base + 5A0h offset = 8000_05A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 275 Programmable Registers HW_ICOLL_INTERRUPT72 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.83 Interrupt Collector Interrupt Register 73 (HW_ICOLL_INTERRUPT73) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT73: 0x5B0 HW_ICOLL_INTERRUPT73_SET: 0x5B4 HW_ICOLL_INTERRUPT73_CLR: 0x5B8 HW_ICOLL_INTERRUPT73_TOG: 0x5BC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT73_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 276 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 5B0h offset = 8000_05B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT73 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 277 Programmable Registers 5.4.84 Interrupt Collector Interrupt Register 74 (HW_ICOLL_INTERRUPT74) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT74: 0x5C0 HW_ICOLL_INTERRUPT74_SET: 0x5C4 HW_ICOLL_INTERRUPT74_CLR: 0x5C8 HW_ICOLL_INTERRUPT74_TOG: 0x5CC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT74_SET(0,0x00000001); Address: 8000_0000h base + 5C0h offset = 8000_05C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 278 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT74 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.85 Interrupt Collector Interrupt Register 75 (HW_ICOLL_INTERRUPT75) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT75: 0x5D0 HW_ICOLL_INTERRUPT75_SET: 0x5D4 HW_ICOLL_INTERRUPT75_CLR: 0x5D8 HW_ICOLL_INTERRUPT75_TOG: 0x5DC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT75_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 279 Programmable Registers Address: 8000_0000h base + 5D0h offset = 8000_05D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT75 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 280 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.86 Interrupt Collector Interrupt Register 76 (HW_ICOLL_INTERRUPT76) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT76: 0x5E0 HW_ICOLL_INTERRUPT76_SET: 0x5E4 HW_ICOLL_INTERRUPT76_CLR: 0x5E8 HW_ICOLL_INTERRUPT76_TOG: 0x5EC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT76_SET(0,0x00000001); Address: 8000_0000h base + 5E0h offset = 8000_05E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 281 Programmable Registers HW_ICOLL_INTERRUPT76 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.87 Interrupt Collector Interrupt Register 77 (HW_ICOLL_INTERRUPT77) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT77: 0x5F0 HW_ICOLL_INTERRUPT77_SET: 0x5F4 HW_ICOLL_INTERRUPT77_CLR: 0x5F8 HW_ICOLL_INTERRUPT77_TOG: 0x5FC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT77_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 282 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 5F0h offset = 8000_05F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT77 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 283 Programmable Registers 5.4.88 Interrupt Collector Interrupt Register 78 (HW_ICOLL_INTERRUPT78) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT78: 0x600 HW_ICOLL_INTERRUPT78_SET: 0x604 HW_ICOLL_INTERRUPT78_CLR: 0x608 HW_ICOLL_INTERRUPT78_TOG: 0x60C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT78_SET(0,0x00000001); Address: 8000_0000h base + 600h offset = 8000_0600h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 284 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT78 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.89 Interrupt Collector Interrupt Register 79 (HW_ICOLL_INTERRUPT79) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT79: 0x610 HW_ICOLL_INTERRUPT79_SET: 0x614 HW_ICOLL_INTERRUPT79_CLR: 0x618 HW_ICOLL_INTERRUPT79_TOG: 0x61C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT79_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 285 Programmable Registers Address: 8000_0000h base + 610h offset = 8000_0610h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT79 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 286 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.90 Interrupt Collector Interrupt Register 80 (HW_ICOLL_INTERRUPT80) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT80: 0x620 HW_ICOLL_INTERRUPT80_SET: 0x624 HW_ICOLL_INTERRUPT80_CLR: 0x628 HW_ICOLL_INTERRUPT80_TOG: 0x62C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT80_SET(0,0x00000001); Address: 8000_0000h base + 620h offset = 8000_0620h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 287 Programmable Registers HW_ICOLL_INTERRUPT80 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.91 Interrupt Collector Interrupt Register 81 (HW_ICOLL_INTERRUPT81) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT81: 0x630 HW_ICOLL_INTERRUPT81_SET: 0x634 HW_ICOLL_INTERRUPT81_CLR: 0x638 HW_ICOLL_INTERRUPT81_TOG: 0x63C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT81_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 288 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 630h offset = 8000_0630h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT81 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 289 Programmable Registers 5.4.92 Interrupt Collector Interrupt Register 82 (HW_ICOLL_INTERRUPT82) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT82: 0x640 HW_ICOLL_INTERRUPT82_SET: 0x644 HW_ICOLL_INTERRUPT82_CLR: 0x648 HW_ICOLL_INTERRUPT82_TOG: 0x64C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT82_SET(0,0x00000001); Address: 8000_0000h base + 640h offset = 8000_0640h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 290 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT82 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.93 Interrupt Collector Interrupt Register 83 (HW_ICOLL_INTERRUPT83) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT83: 0x650 HW_ICOLL_INTERRUPT83_SET: 0x654 HW_ICOLL_INTERRUPT83_CLR: 0x658 HW_ICOLL_INTERRUPT83_TOG: 0x65C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT83_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 291 Programmable Registers Address: 8000_0000h base + 650h offset = 8000_0650h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT83 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 292 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.94 Interrupt Collector Interrupt Register 84 (HW_ICOLL_INTERRUPT84) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT84: 0x660 HW_ICOLL_INTERRUPT84_SET: 0x664 HW_ICOLL_INTERRUPT84_CLR: 0x668 HW_ICOLL_INTERRUPT84_TOG: 0x66C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT84_SET(0,0x00000001); Address: 8000_0000h base + 660h offset = 8000_0660h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 293 Programmable Registers HW_ICOLL_INTERRUPT84 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.95 Interrupt Collector Interrupt Register 85 (HW_ICOLL_INTERRUPT85) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT85: 0x670 HW_ICOLL_INTERRUPT85_SET: 0x674 HW_ICOLL_INTERRUPT85_CLR: 0x678 HW_ICOLL_INTERRUPT85_TOG: 0x67C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT85_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 294 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 670h offset = 8000_0670h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT85 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 295 Programmable Registers 5.4.96 Interrupt Collector Interrupt Register 86 (HW_ICOLL_INTERRUPT86) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT86: 0x680 HW_ICOLL_INTERRUPT86_SET: 0x684 HW_ICOLL_INTERRUPT86_CLR: 0x688 HW_ICOLL_INTERRUPT86_TOG: 0x68C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT86_SET(0,0x00000001); Address: 8000_0000h base + 680h offset = 8000_0680h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 296 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT86 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.97 Interrupt Collector Interrupt Register 87 (HW_ICOLL_INTERRUPT87) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT87: 0x690 HW_ICOLL_INTERRUPT87_SET: 0x694 HW_ICOLL_INTERRUPT87_CLR: 0x698 HW_ICOLL_INTERRUPT87_TOG: 0x69C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT87_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 297 Programmable Registers Address: 8000_0000h base + 690h offset = 8000_0690h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT87 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 298 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.98 Interrupt Collector Interrupt Register 88 (HW_ICOLL_INTERRUPT88) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT88: 0x6A0 HW_ICOLL_INTERRUPT88_SET: 0x6A4 HW_ICOLL_INTERRUPT88_CLR: 0x6A8 HW_ICOLL_INTERRUPT88_TOG: 0x6AC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT88_SET(0,0x00000001); Address: 8000_0000h base + 6A0h offset = 8000_06A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 299 Programmable Registers HW_ICOLL_INTERRUPT88 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.99 Interrupt Collector Interrupt Register 89 (HW_ICOLL_INTERRUPT89) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT89: 0x6B0 HW_ICOLL_INTERRUPT89_SET: 0x6B4 HW_ICOLL_INTERRUPT89_CLR: 0x6B8 HW_ICOLL_INTERRUPT89_TOG: 0x6BC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT89_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 300 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 6B0h offset = 8000_06B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT89 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 301 Programmable Registers 5.4.100 Interrupt Collector Interrupt Register 90 (HW_ICOLL_INTERRUPT90) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT90: 0x6C0 HW_ICOLL_INTERRUPT90_SET: 0x6C4 HW_ICOLL_INTERRUPT90_CLR: 0x6C8 HW_ICOLL_INTERRUPT90_TOG: 0x6CC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT90_SET(0,0x00000001); Address: 8000_0000h base + 6C0h offset = 8000_06C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 302 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT90 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.101 Interrupt Collector Interrupt Register 91 (HW_ICOLL_INTERRUPT91) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT91: 0x6D0 HW_ICOLL_INTERRUPT91_SET: 0x6D4 HW_ICOLL_INTERRUPT91_CLR: 0x6D8 HW_ICOLL_INTERRUPT91_TOG: 0x6DC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT91_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 303 Programmable Registers Address: 8000_0000h base + 6D0h offset = 8000_06D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT91 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 304 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.102 Interrupt Collector Interrupt Register 92 (HW_ICOLL_INTERRUPT92) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT92: 0x6E0 HW_ICOLL_INTERRUPT92_SET: 0x6E4 HW_ICOLL_INTERRUPT92_CLR: 0x6E8 HW_ICOLL_INTERRUPT92_TOG: 0x6EC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT92_SET(0,0x00000001); Address: 8000_0000h base + 6E0h offset = 8000_06E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 305 Programmable Registers HW_ICOLL_INTERRUPT92 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.103 Interrupt Collector Interrupt Register 93 (HW_ICOLL_INTERRUPT93) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT93: 0x6F0 HW_ICOLL_INTERRUPT93_SET: 0x6F4 HW_ICOLL_INTERRUPT93_CLR: 0x6F8 HW_ICOLL_INTERRUPT93_TOG: 0x6FC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT93_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 306 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 6F0h offset = 8000_06F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT93 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 307 Programmable Registers 5.4.104 Interrupt Collector Interrupt Register 94 (HW_ICOLL_INTERRUPT94) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT94: 0x700 HW_ICOLL_INTERRUPT94_SET: 0x704 HW_ICOLL_INTERRUPT94_CLR: 0x708 HW_ICOLL_INTERRUPT94_TOG: 0x70C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT94_SET(0,0x00000001); Address: 8000_0000h base + 700h offset = 8000_0700h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 308 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT94 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.105 Interrupt Collector Interrupt Register 95 (HW_ICOLL_INTERRUPT95) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT95: 0x710 HW_ICOLL_INTERRUPT95_SET: 0x714 HW_ICOLL_INTERRUPT95_CLR: 0x718 HW_ICOLL_INTERRUPT95_TOG: 0x71C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT95_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 309 Programmable Registers Address: 8000_0000h base + 710h offset = 8000_0710h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT95 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 310 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.106 Interrupt Collector Interrupt Register 96 (HW_ICOLL_INTERRUPT96) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT96: 0x720 HW_ICOLL_INTERRUPT96_SET: 0x724 HW_ICOLL_INTERRUPT96_CLR: 0x728 HW_ICOLL_INTERRUPT96_TOG: 0x72C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT96_SET(0,0x00000001); Address: 8000_0000h base + 720h offset = 8000_0720h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 311 Programmable Registers HW_ICOLL_INTERRUPT96 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.107 Interrupt Collector Interrupt Register 97 (HW_ICOLL_INTERRUPT97) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT97: 0x730 HW_ICOLL_INTERRUPT97_SET: 0x734 HW_ICOLL_INTERRUPT97_CLR: 0x738 HW_ICOLL_INTERRUPT97_TOG: 0x73C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT97_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 312 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 730h offset = 8000_0730h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT97 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 313 Programmable Registers 5.4.108 Interrupt Collector Interrupt Register 98 (HW_ICOLL_INTERRUPT98) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT98: 0x740 HW_ICOLL_INTERRUPT98_SET: 0x744 HW_ICOLL_INTERRUPT98_CLR: 0x748 HW_ICOLL_INTERRUPT98_TOG: 0x74C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT98_SET(0,0x00000001); Address: 8000_0000h base + 740h offset = 8000_0740h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 314 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT98 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.109 Interrupt Collector Interrupt Register 99 (HW_ICOLL_INTERRUPT99) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT99: 0x750 HW_ICOLL_INTERRUPT99_SET: 0x754 HW_ICOLL_INTERRUPT99_CLR: 0x758 HW_ICOLL_INTERRUPT99_TOG: 0x75C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT99_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 315 Programmable Registers Address: 8000_0000h base + 750h offset = 8000_0750h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT99 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 316 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.110 Interrupt Collector Interrupt Register 100 (HW_ICOLL_INTERRUPT100) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT100: 0x760 HW_ICOLL_INTERRUPT100_SET: 0x764 HW_ICOLL_INTERRUPT100_CLR: 0x768 HW_ICOLL_INTERRUPT100_TOG: 0x76C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT100_SET(0,0x00000001); Address: 8000_0000h base + 760h offset = 8000_0760h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 317 Programmable Registers HW_ICOLL_INTERRUPT100 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.111 Interrupt Collector Interrupt Register 101 (HW_ICOLL_INTERRUPT101) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT101: 0x770 HW_ICOLL_INTERRUPT101_SET: 0x774 HW_ICOLL_INTERRUPT101_CLR: 0x778 HW_ICOLL_INTERRUPT101_TOG: 0x77C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT101_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 318 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 770h offset = 8000_0770h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT101 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 319 Programmable Registers 5.4.112 Interrupt Collector Interrupt Register 102 (HW_ICOLL_INTERRUPT102) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT102: 0x780 HW_ICOLL_INTERRUPT102_SET: 0x784 HW_ICOLL_INTERRUPT102_CLR: 0x788 HW_ICOLL_INTERRUPT102_TOG: 0x78C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT102_SET(0,0x00000001); Address: 8000_0000h base + 780h offset = 8000_0780h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 320 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT102 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.113 Interrupt Collector Interrupt Register 103 (HW_ICOLL_INTERRUPT103) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT103: 0x790 HW_ICOLL_INTERRUPT103_SET: 0x794 HW_ICOLL_INTERRUPT103_CLR: 0x798 HW_ICOLL_INTERRUPT103_TOG: 0x79C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT103_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 321 Programmable Registers Address: 8000_0000h base + 790h offset = 8000_0790h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT103 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 322 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.114 Interrupt Collector Interrupt Register 104 (HW_ICOLL_INTERRUPT104) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT104: 0x7A0 HW_ICOLL_INTERRUPT104_SET: 0x7A4 HW_ICOLL_INTERRUPT104_CLR: 0x7A8 HW_ICOLL_INTERRUPT104_TOG: 0x7AC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT104_SET(0,0x00000001); Address: 8000_0000h base + 7A0h offset = 8000_07A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 323 Programmable Registers HW_ICOLL_INTERRUPT104 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.115 Interrupt Collector Interrupt Register 105 (HW_ICOLL_INTERRUPT105) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT105: 0x7B0 HW_ICOLL_INTERRUPT105_SET: 0x7B4 HW_ICOLL_INTERRUPT105_CLR: 0x7B8 HW_ICOLL_INTERRUPT105_TOG: 0x7BC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT105_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 324 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 7B0h offset = 8000_07B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT105 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 325 Programmable Registers 5.4.116 Interrupt Collector Interrupt Register 106 (HW_ICOLL_INTERRUPT106) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT106: 0x7C0 HW_ICOLL_INTERRUPT106_SET: 0x7C4 HW_ICOLL_INTERRUPT106_CLR: 0x7C8 HW_ICOLL_INTERRUPT106_TOG: 0x7CC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT106_SET(0,0x00000001); Address: 8000_0000h base + 7C0h offset = 8000_07C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 326 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT106 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.117 Interrupt Collector Interrupt Register 107 (HW_ICOLL_INTERRUPT107) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT107: 0x7D0 HW_ICOLL_INTERRUPT107_SET: 0x7D4 HW_ICOLL_INTERRUPT107_CLR: 0x7D8 HW_ICOLL_INTERRUPT107_TOG: 0x7DC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT107_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 327 Programmable Registers Address: 8000_0000h base + 7D0h offset = 8000_07D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT107 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 328 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.118 Interrupt Collector Interrupt Register 108 (HW_ICOLL_INTERRUPT108) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT108: 0x7E0 HW_ICOLL_INTERRUPT108_SET: 0x7E4 HW_ICOLL_INTERRUPT108_CLR: 0x7E8 HW_ICOLL_INTERRUPT108_TOG: 0x7EC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT108_SET(0,0x00000001); Address: 8000_0000h base + 7E0h offset = 8000_07E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 329 Programmable Registers HW_ICOLL_INTERRUPT108 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.119 Interrupt Collector Interrupt Register 109 (HW_ICOLL_INTERRUPT109) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT109: 0x7F0 HW_ICOLL_INTERRUPT109_SET: 0x7F4 HW_ICOLL_INTERRUPT109_CLR: 0x7F8 HW_ICOLL_INTERRUPT109_TOG: 0x7FC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT109_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 330 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 7F0h offset = 8000_07F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT109 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 331 Programmable Registers 5.4.120 Interrupt Collector Interrupt Register 110 (HW_ICOLL_INTERRUPT110) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT110: 0x800 HW_ICOLL_INTERRUPT110_SET: 0x804 HW_ICOLL_INTERRUPT110_CLR: 0x808 HW_ICOLL_INTERRUPT110_TOG: 0x80C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT110_SET(0,0x00000001); Address: 8000_0000h base + 800h offset = 8000_0800h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 332 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT110 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.121 Interrupt Collector Interrupt Register 111 (HW_ICOLL_INTERRUPT111) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT111: 0x810 HW_ICOLL_INTERRUPT111_SET: 0x814 HW_ICOLL_INTERRUPT111_CLR: 0x818 HW_ICOLL_INTERRUPT111_TOG: 0x81C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT111_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 333 Programmable Registers Address: 8000_0000h base + 810h offset = 8000_0810h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT111 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 334 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.122 Interrupt Collector Interrupt Register 112 (HW_ICOLL_INTERRUPT112) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT112: 0x820 HW_ICOLL_INTERRUPT112_SET: 0x824 HW_ICOLL_INTERRUPT112_CLR: 0x828 HW_ICOLL_INTERRUPT112_TOG: 0x82C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT112_SET(0,0x00000001); Address: 8000_0000h base + 820h offset = 8000_0820h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 335 Programmable Registers HW_ICOLL_INTERRUPT112 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.123 Interrupt Collector Interrupt Register 113 (HW_ICOLL_INTERRUPT113) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT113: 0x830 HW_ICOLL_INTERRUPT113_SET: 0x834 HW_ICOLL_INTERRUPT113_CLR: 0x838 HW_ICOLL_INTERRUPT113_TOG: 0x83C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT113_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 336 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 830h offset = 8000_0830h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT113 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 337 Programmable Registers 5.4.124 Interrupt Collector Interrupt Register 114 (HW_ICOLL_INTERRUPT114) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT114: 0x840 HW_ICOLL_INTERRUPT114_SET: 0x844 HW_ICOLL_INTERRUPT114_CLR: 0x848 HW_ICOLL_INTERRUPT114_TOG: 0x84C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT114_SET(0,0x00000001); Address: 8000_0000h base + 840h offset = 8000_0840h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 338 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT114 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.125 Interrupt Collector Interrupt Register 115 (HW_ICOLL_INTERRUPT115) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT115: 0x850 HW_ICOLL_INTERRUPT115_SET: 0x854 HW_ICOLL_INTERRUPT115_CLR: 0x858 HW_ICOLL_INTERRUPT115_TOG: 0x85C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT115_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 339 Programmable Registers Address: 8000_0000h base + 850h offset = 8000_0850h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT115 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 340 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.126 Interrupt Collector Interrupt Register 116 (HW_ICOLL_INTERRUPT116) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT116: 0x860 HW_ICOLL_INTERRUPT116_SET: 0x864 HW_ICOLL_INTERRUPT116_CLR: 0x868 HW_ICOLL_INTERRUPT116_TOG: 0x86C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT116_SET(0,0x00000001); Address: 8000_0000h base + 860h offset = 8000_0860h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 341 Programmable Registers HW_ICOLL_INTERRUPT116 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.127 Interrupt Collector Interrupt Register 117 (HW_ICOLL_INTERRUPT117) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT117: 0x870 HW_ICOLL_INTERRUPT117_SET: 0x874 HW_ICOLL_INTERRUPT117_CLR: 0x878 HW_ICOLL_INTERRUPT117_TOG: 0x87C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT117_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 342 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 870h offset = 8000_0870h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT117 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 343 Programmable Registers 5.4.128 Interrupt Collector Interrupt Register 118 (HW_ICOLL_INTERRUPT118) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT118: 0x880 HW_ICOLL_INTERRUPT118_SET: 0x884 HW_ICOLL_INTERRUPT118_CLR: 0x888 HW_ICOLL_INTERRUPT118_TOG: 0x88C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT118_SET(0,0x00000001); Address: 8000_0000h base + 880h offset = 8000_0880h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 344 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT118 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.129 Interrupt Collector Interrupt Register 119 (HW_ICOLL_INTERRUPT119) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT119: 0x890 HW_ICOLL_INTERRUPT119_SET: 0x894 HW_ICOLL_INTERRUPT119_CLR: 0x898 HW_ICOLL_INTERRUPT119_TOG: 0x89C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT119_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 345 Programmable Registers Address: 8000_0000h base + 890h offset = 8000_0890h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT119 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 346 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.130 Interrupt Collector Interrupt Register 120 (HW_ICOLL_INTERRUPT120) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT120: 0x8A0 HW_ICOLL_INTERRUPT120_SET: 0x8A4 HW_ICOLL_INTERRUPT120_CLR: 0x8A8 HW_ICOLL_INTERRUPT120_TOG: 0x8AC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT120_SET(0,0x00000001); Address: 8000_0000h base + 8A0h offset = 8000_08A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 347 Programmable Registers HW_ICOLL_INTERRUPT120 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.131 Interrupt Collector Interrupt Register 121 (HW_ICOLL_INTERRUPT121) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT121: 0x8B0 HW_ICOLL_INTERRUPT121_SET: 0x8B4 HW_ICOLL_INTERRUPT121_CLR: 0x8B8 HW_ICOLL_INTERRUPT121_TOG: 0x8BC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT121_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 348 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 8B0h offset = 8000_08B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT121 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 349 Programmable Registers 5.4.132 Interrupt Collector Interrupt Register 122 (HW_ICOLL_INTERRUPT122) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT122: 0x8C0 HW_ICOLL_INTERRUPT122_SET: 0x8C4 HW_ICOLL_INTERRUPT122_CLR: 0x8C8 HW_ICOLL_INTERRUPT122_TOG: 0x8CC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT122_SET(0,0x00000001); Address: 8000_0000h base + 8C0h offset = 8000_08C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 350 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT122 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.133 Interrupt Collector Interrupt Register 123 (HW_ICOLL_INTERRUPT123) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT123: 0x8D0 HW_ICOLL_INTERRUPT123_SET: 0x8D4 HW_ICOLL_INTERRUPT123_CLR: 0x8D8 HW_ICOLL_INTERRUPT123_TOG: 0x8DC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT123_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 351 Programmable Registers Address: 8000_0000h base + 8D0h offset = 8000_08D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT123 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 352 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.134 Interrupt Collector Interrupt Register 124 (HW_ICOLL_INTERRUPT124) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT124: 0x8E0 HW_ICOLL_INTERRUPT124_SET: 0x8E4 HW_ICOLL_INTERRUPT124_CLR: 0x8E8 HW_ICOLL_INTERRUPT124_TOG: 0x8EC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT124_SET(0,0x00000001); Address: 8000_0000h base + 8E0h offset = 8000_08E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 353 Programmable Registers HW_ICOLL_INTERRUPT124 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.135 Interrupt Collector Interrupt Register 125 (HW_ICOLL_INTERRUPT125) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT125: 0x8F0 HW_ICOLL_INTERRUPT125_SET: 0x8F4 HW_ICOLL_INTERRUPT125_CLR: 0x8F8 HW_ICOLL_INTERRUPT125_TOG: 0x8FC This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT125_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 354 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) Address: 8000_0000h base + 8F0h offset = 8000_08F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT125 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 355 Programmable Registers 5.4.136 Interrupt Collector Interrupt Register 126 (HW_ICOLL_INTERRUPT126) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT126: 0x900 HW_ICOLL_INTERRUPT126_SET: 0x904 HW_ICOLL_INTERRUPT126_CLR: 0x908 HW_ICOLL_INTERRUPT126_TOG: 0x90C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT126_SET(0,0x00000001); Address: 8000_0000h base + 900h offset = 8000_0900h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 356 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_INTERRUPT126 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority 5.4.137 Interrupt Collector Interrupt Register 127 (HW_ICOLL_INTERRUPT127) This register provides a mechanism to specify the priority level for an interrupt source. It also provides an enable and software interrupt for each one, as well as security designation. HW_ICOLL_INTERRUPT127: 0x910 HW_ICOLL_INTERRUPT127_SET: 0x914 HW_ICOLL_INTERRUPT127_CLR: 0x918 HW_ICOLL_INTERRUPT127_TOG: 0x91C This register provides a mechanism to specify the priority associated with an interrupt bit. In addition, this register controls the enable and software generated interrupt. WARNING: Modifying the priority of an enabled interrupt may result in undefined behavior. You should always disable an interrupt prior to changing its priority. EXAMPLE HW_ICOLL_INTERRUPT127_SET(0,0x00000001); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 357 Programmable Registers Address: 8000_0000h base + 910h offset = 8000_0910h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 SOFTIRQ Reset ENFIQ W 0 0 0 RSRVD1 R PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_INTERRUPT127 field descriptions Field 31-5 RSRVD1 4 ENFIQ Description Always write zeroes to this bitfield. Set this to 1 to steer this interrupt to the non-vectored FIQ line. When set to 0 the interrupt will pass through the main IRQ FSM and priority logic. 0x0 0x1 DISABLE -- Disable ENABLE -- Enable 3 SOFTIRQ Set this bit to one to force a software interrupt. 2 ENABLE Enable the interrupt bit through the collector. PRIORITY 0x0 0x1 0x0 0x1 NO_INTERRUPT -- turn off the software interrupt request. FORCE_INTERRUPT -- force a software interrupt DISABLE -- Disable ENABLE -- Enable Set the priority level for this interrupt, 0x3 is highest, 0x0 is lowest (weakest). 0x0 0x1 0x2 0x3 LEVEL0 -- level 0, lowest or weakest priority LEVEL1 -- level 1 LEVEL2 -- level 2 LEVEL3 -- level 3, highest or strongest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 358 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.138 Interrupt Collector Debug Register 0 (HW_ICOLL_DEBUG) The contents of this register will be defined as the hardware is developed. HW_ICOLL_DEBUG: 0x1120 HW_ICOLL_DEBUG_SET: 0x1124 HW_ICOLL_DEBUG_CLR: 0x1128 HW_ICOLL_DEBUG_TOG: 0x112C This register provides diagnostic visibility into the IRQ request state machine and its various inputs. EXAMPLE if (BF_RD(ICOLL_DEBUG, LEVEL_REQUESTS) != HW_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3) Error(); TPRINTF(TP_MED, ("ICOLL INSERVICE = 0x%x\n", BF_RD(ICOLL_DEBUG, INSERVICE))); TPRINTF(TP_MED, ("ICOLL STATE = 0x%x\n", BF_RD(ICOLL_DEBUG, VECTOR_FSM))); Address: 8000_0000h base + 1120h offset = 8000_1120h Bit 31 30 29 28 27 INSERVICE R 26 25 24 LEVEL_REQUESTS 23 22 21 20 REQUESTS_BY_LEVEL 19 18 RSRVD2 17 16 FIQ IRQ W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 RSRVD1 R VECTOR_FSM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_DEBUG field descriptions Field Description 31-28 INSERVICE read-only view of the Inservice bits used for nesting IRQs. 27-24 LEVEL_ REQUESTS read-only view of the requsts by priority level for the current IRQ. 0x1 0x2 0x4 0x8 0x1 0x2 LEVEL0 -- LEVEL0 LEVEL1 -- LEVEL1 LEVEL2 -- LEVEL2 LEVEL3 -- LEVEL3 LEVEL0 -- LEVEL0 LEVEL1 -- LEVEL1 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 359 Programmable Registers HW_ICOLL_DEBUG field descriptions (continued) Field Description LEVEL2 -- LEVEL2 LEVEL3 -- LEVEL3 0x4 0x8 23-20 REQUESTS_ BY_LEVEL 19-18 RSRVD2 read-only view of the requsts by priority level for the current IRQ. LEVEL0 -- LEVEL0 LEVEL1 -- LEVEL1 LEVEL2 -- LEVEL2 LEVEL3 -- LEVEL3 0x1 0x2 0x4 0x8 Always write zeroes to this bitfield. 17 FIQ Read-Only View of the FIQ output to the CPU. 16 IRQ Read-Only View of the FIQ output to the CPU. 15-10 RSRVD1 VECTOR_FSM NO_FIQ_REQUESTED -- No FIQ Requested FIQ_REQUESTED -- FIQ Requested 0x0 0x1 NO_IRQ_REQUESTED -- No IRQ Requested IRQ_REQUESTED -- IRQ Requested 0x0 0x1 Always write zeroes to this bitfield. Empty description. 0x000 0x001 0x002 0x004 0x008 0x010 0x020 0x040 0x080 0x100 0x200 FSM_IDLE -- FSM_IDLE FSM_MULTICYCLE1 -- FSM_MULTICYCLE1 FSM_MULTICYCLE2 -- FSM_MULTICYCLE2 FSM_PENDING -- FSM_PENDING FSM_MULTICYCLE3 -- FSM_MULTICYCLE3 FSM_MULTICYCLE4 -- FSM_MULTICYCLE4 FSM_ISR_RUNNING1 -- FSM_ISR_RUNNING1 FSM_ISR_RUNNING2 -- FSM_ISR_RUNNING2 FSM_ISR_RUNNING3 -- FSM_ISR_RUNNING3 FSM_MULTICYCLE5 -- FSM_MULTICYCLE5 FSM_MULTICYCLE6 -- FSM_MULTICYCLE6 5.4.139 Interrupt Collector Debug Read Register 0 (HW_ICOLL_DBGREAD0) This register always returns a known read value for debug purposes. HW_ICOLL_DBGREAD0: 0x1130 HW_ICOLL_DBGREAD0_SET: 0x1134 HW_ICOLL_DBGREAD0_CLR: 0x1138 HW_ICOLL_DBGREAD0_TOG: 0x113C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 360 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) This register is used to test the read mux paths on the APBH. EXAMPLE if (HW_ICOLL_DBGREAD0_RD != 0xECA94567) Error(); Address: 8000_0000h base + 1130h offset = 8000_1130h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 VALUE R W Reset 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 0 HW_ICOLL_DBGREAD0 field descriptions Field Description VALUE Fixed read-only value. 5.4.140 Interrupt Collector Debug Read Register 1 (HW_ICOLL_DBGREAD1) This register always returns a known read value for debug purposes. HW_ICOLL_DBGREAD1: 0x1140 HW_ICOLL_DBGREAD1_SET: 0x1144 HW_ICOLL_DBGREAD1_CLR: 0x1148 HW_ICOLL_DBGREAD1_TOG: 0x114C This register is used to test the read mux paths on the APBH. EXAMPLE if (HW_ICOLL_DBGREAD1_RD != 0x1356DA98) Error(); Address: 8000_0000h base + 1140h offset = 8000_1140h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 0 VALUE R W Reset 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 361 Programmable Registers HW_ICOLL_DBGREAD1 field descriptions Field Description VALUE Fixed read-only value. 5.4.141 Interrupt Collector Debug Flag Register (HW_ICOLL_DBGFLAG) The Interrupt Collector debug flag register is used to post diagnostic state into simulation. HW_ICOLL_DBGFLAG: 0x1150 HW_ICOLL_DBGFLAG_SET: 0x1154 HW_ICOLL_DBGFLAG_CLR: 0x1158 HW_ICOLL_DBGFLAG_TOG: 0x115C This register provides a posting register to synchronize C program execution and the internal simulation environment. EXAMPLE BF_WR(ICOLL_DBGFLAG, FLAG, 3); // ... do some diagnostic action BF_WR(ICOLL_DBGFLAG, FLAG, 4); // ... do some more diagnostic actions BF_WR(ICOLL_DBGFLAG, FLAG, 5); Address: 8000_0000h base + 1150h offset = 8000_1150h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RSRVD1 R 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FLAG W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_DBGFLAG field descriptions Field 31-16 RSRVD1 FLAG Description Always write zeroes to this bitfield. This debug facility is probably temporary. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 362 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) 5.4.142 Interrupt Collector Debug Read Request Register 0 (HW_ICOLL_DBGREQUEST0) read-only view into the low 32 bits of the request holding register. HW_ICOLL_DBGREQUEST0: 0x1160 HW_ICOLL_DBGREQUEST0_SET: 0x1164 HW_ICOLL_DBGREQUEST0_CLR: 0x1168 HW_ICOLL_DBGREQUEST0_TOG: 0x116C This register is used to test interrupt collector state machine and its associated request holding register. EXAMPLE if (HW_ICOLL_DBGREQUESTn_RD(0) != 0x00000000) Error(); Address: 8000_0000h base + 1160h offset = 8000_1160h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_DBGREQUEST0 field descriptions Field BITS Description Low 32 bits of the request holding register. 5.4.143 Interrupt Collector Debug Read Request Register 1 (HW_ICOLL_DBGREQUEST1) read-only view into bits 32-63 of the request holding register. HW_ICOLL_DBGREQUEST1: 0x1170 HW_ICOLL_DBGREQUEST1_SET: 0x1174 HW_ICOLL_DBGREQUEST1_CLR: 0x1178 HW_ICOLL_DBGREQUEST1_TOG: 0x117C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 363 Programmable Registers This register is used to test interrupt collector state machine and its associated request holding register. EXAMPLE if (HW_ICOLL_DBGREQUESTn_RD(n) != 0x00000000) Error(); Address: 8000_0000h base + 1170h offset = 8000_1170h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_DBGREQUEST1 field descriptions Field Description BITS Bits 32-63 of the request holding register. 5.4.144 Interrupt Collector Debug Read Request Register 2 (HW_ICOLL_DBGREQUEST2) read-only view into bits 64-95 of the request holding register. HW_ICOLL_DBGREQUEST2: 0x1180 HW_ICOLL_DBGREQUEST2_SET: 0x1184 HW_ICOLL_DBGREQUEST2_CLR: 0x1188 HW_ICOLL_DBGREQUEST2_TOG: 0x118C This register is used to test interrupt collector state machine and its associated request holding register. EXAMPLE if (HW_ICOLL_DBGREQUESTn_RD(n) != 0x00000000) Error(); Address: 8000_0000h base + 1180h offset = 8000_1180h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 364 Freescale Semiconductor, Inc. Chapter 5 Interrupt Collector (ICOLL) HW_ICOLL_DBGREQUEST2 field descriptions Field Description BITS Bits 64-95 of the request holding register. 5.4.145 Interrupt Collector Debug Read Request Register 3 (HW_ICOLL_DBGREQUEST3) read-only view into bits 96-127 of the request holding register. HW_ICOLL_DBGREQUEST3: 0x1190 HW_ICOLL_DBGREQUEST3_SET: 0x1194 HW_ICOLL_DBGREQUEST3_CLR: 0x1198 HW_ICOLL_DBGREQUEST3_TOG: 0x119C This register is used to test interrupt collector state machine and its associated request holding register. EXAMPLE if (HW_ICOLL_DBGREQUESTn_RD(n) != 0x00000000) Error(); Address: 8000_0000h base + 1190h offset = 8000_1190h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ICOLL_DBGREQUEST3 field descriptions Field BITS Description Bits 96-127 of the request holding register. 5.4.146 Interrupt Collector Version Register (HW_ICOLL_VERSION) This register always returns a known read value for debug purposes it indicates the version of the block. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 365 Programmable Registers if (HW_ICOLL_VERSION.B.MAJOR != 3) Error(); Address: 8000_0000h base + 11E0h offset = 8000_11E0h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 HW_ICOLL_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 366 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.1 Overview The AHB-to-APBH bridge provides the i.MX28 with an inexpensive peripheral attachment bus running on the AHB's HCLK. (The H in APBH denotes that the APBH is synchronous to HCLK, as compared to APBX, which runs on the crystal-derived XCLK.) As shown in the figure below, the AHB-to-APBH bridge includes the AHB-to-APB PIO bridge for a memory-mapped I/O to the APB devices, as well as a central DMA facility for devices on this bus and a vectored interrupt controller for the ARM Cortex-A8 core. Each one of the APB peripherals, including the vectored interrupt controller, is documented in their respective chapters. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 367 Overview AHB AHB Slave AHB Master AHB-to-APBH DMA APBH Master AHB-to-APBH Bridge SSP0 ATA_NAND0 SSP1 ATA_NAND1 ATA_NAND2 SSP3 APBH SSP2 ATA_NAND3 ATA_NAND0 LCDIF ATA_NAND1 HSADC ATA_NAND2 ATA_NAND3 Figure 6-1. AHB-to-APBH Bridge DMA Block Diagram The DMA controller uses the APBH bus to transfer read and write data to and from each peripheral. There is no separate DMA bus for these devices. Contention between the DMA's use of the APBH bus and the AHB-to-APB bridge functions' use of the APBH is i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 368 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) mediated by an internal arbitration logic. For contention between these two units, the DMA is favored and the AHB slave will report "not ready" through its HREADY output until the bridge transfer can complete. The arbiter tracks repeated lockouts and inverts the priority, guaranteeing the ARM platform every fourth transfer on the APB. 6.2 APBH DMA The DMA supports sixteen channels of DMA services, as shown in the following table. The shared DMA resource allows each independent channel to follow a simple chained command list. Command chains are built up using the general structure, as shown in Figure 6-2. Table 6-1. APBH DMA channel assignments APBH DMA Channel # Usage 0 SSP0 1 SSP1 2 SSP2 3 SSP3 4 GPMI0 5 GPMI1 6 GPMI2 7 GPMI3 8 GPMI4 9 GPMI5 10 GPMI6 11 GPMI7 12 HSADC 13 LCDIF 14 Empty 15 Empty A single command structure or channel command word specifies a number of operations to be performed by the DMA in support of a given device. Thus, the ARM platform can set up large units of work, chaining together many DMA channel command words, pass them off to the DMA, and have no further concern for the device until the DMA completion interrupt occurs. The goal is to have enough intelligence in the DMA and the devices to keep the interrupt frequency from any device below 1 KHz (arrival intervals longer than 1 ms). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 369 APBH DMA A single command structure can issue 32-bit PIO write operations to key registers in the associated device using the same APB bus and controls that it uses to write DMA data bytes to the device. For example, this allows a chain of operations to be issued to the GPMI controller to send NAND command bytes, address bytes, and data transfers where the command and the address structure is completely under software control, but the administration of that transfer is handled autonomously by the DMA. Each DMA structure can have 0-15 PIO words appended to it. The CMDPIOWORDS field, if nonzero, instructs the DMA engine to copy these words to the APB, beginning at the first register address offset for the peripheral and and incrementing the register offset each cycle. The DMA master generates only normal read/write transfers to the APBH. It does not generate set, clear, or toggle (SCT) transfers. After any requested PIO words have been transferred to the peripheral, the DMA examines the two-bit command field in the channel command structure. Table 6-2 shows the four commands implemented by the DMA. word 0 word 2 COMMAND NANDLOCK IRQONCMPLT CHAIN NANDWAIT4READY WAIT4ENDCMD SEMAPHORE HALTONTERMINATE XFER_COUNT word 1 CMDPIOWORDS NEXTCMDADDR BUFFER ADDRESS word 3-n PIOWORD Figure 6-2. AHB-to-APBH Bridge DMA channel command structure Table 6-2. APBH DMA commands DMA Command Usage 00 NO_DMA_XFER. Perform any requested PIO word transfers, but terminate the command before any DMA transfer. 01 DMA_WRITE. Perform any requested PIO word transfers, then perform a DMA transfer from the peripheral for the specified number of bytes. 10 DMA_READ. Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 370 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Table 6-2. APBH DMA commands (continued) DMA Command Usage 11 DMA_SENSE. Perform any requested PIO word transfers, then perform a conditional branch to the next chained device. Follow the NEXTCMD_ADDR pointer if the peripheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. This command becomes a nooperation for any channel other than a GPMI channel. DMA_WRITE operations copy data bytes to the system memory (on-chip RAM or SDRAM) from the associated peripheral. The DMA_WRITE transfer uses the BUFFER_ADDRESS word in the command structure to point to the beginning byte to write data from the peripheral. DMA_READ operations copy data bytes to the APB peripheral from the system memory. The DMA engine contains a shared byte aligner that aligns bytes from system memory to or from the peripherals. Peripherals always assume little-endian-aligned data arrives or departs on their 32-bit APB. The DMA_READ transfer uses the BUFFER_ADDRESS word in the command structure to point to the DMA data buffer to be read by the DMA_READ command. The NO_DMA_XFER command is used to write PIO words to a device without performing any DMA data byte transfers. This command is useful in such applications as activating the NAND devices CHECKSTATUS operation. The check status command reads a status byte from the NAND device, performs an XOR and MASK against an expected value supplied as part of the PIO transfer. Once the read check completes (see NAND Read Status Polling Example), the NO_DMA_XFER command completes. The result in the peripheral is that its sense line is driven by the results of the comparison. The sense flip-flop is only updated by CHECKSTATUS for the device that is executed. At some future point, the chain contains a DMA command structure with the fourth and final command value, that is, the DMA_SENSE command. As each DMA command completes, it triggers the DMA to load the next DMA command structure in the chain. The normal flow list of DMA commands is found by following the NEXTCMD_ADDR pointer in the DMA command structure. The DMA_SENSE command uses the DMA buffer pointer word of the command structure to point to an alternate DMA command structure chain or list. The DMA_SENSE command examines the sense line of the associated peripheral. If the sense line is false, then the DMA follows the standard list found whose next command is found from the pointer in the NEXTCMD_ADDR word of the command structure. If the sense line is true, then the DMA follows the alternate list whose next command is found from the pointer in the DMA Buffer Pointer word of the DMA_SENSE command structure (see Figure 6-2). The sense command ignores the CHAIN bit, so that both pointers must be valid when the DMA comes to a sense command. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 371 APBH DMA If the wait-for-end-command bit (WAIT4ENDCMD) is set in a command structure, the DMA channel waits for the device to signal completion of a command by toggling the endcmd signal before proceeding to load and execute the next command structure. Then, if DECREMENT_SEMAPHORE is set, the semaphore is decremented after the end command is seen. A detailed bit-field view of the DMA command structure is shown in the following table, which shows a field that specifies the number of bytes to be transferred by this DMA command. The transfer-count mechanism is duplicated in the associated peripheral, either as an implied or as a specified count in the peripheral. Table 6-3. DMA channel command word in system memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 COMMAND CHAIN IRQ_COMPLETE NANDLOCK NANDwAIT4READY DECREMENT SEMAPHORE Number PIO Words to Write WAIT4ENDCMD Number DMA Bytes to Transfer HALTONTERMINATE NEXT_COMMAND_ADDRESS DMA Buffer or Alternate CCW Zero or More PIO Words to Write to the Associated Peripheral Starting at its Base Address on the APBH Bus Figure 6-2 also shows the CHAIN bit in bit 2 of the second word of the command structure. This bit is set to 1, if the NEXT_COMMAND_ADDRESS contains a pointer to another DMA command structure. If a null pointer (0) is loaded into the NEXT_COMMAND_ADDRESS, it is not detected by the DMA hardware. Only the CHAIN bit indicates whether a valid list exists beyond the current structure. If the IRQ_COMPLETE bit is set in the command structure, then the last act of the DMA before loading the next command is to set the interrupt-status bit corresponding to the current channel. The sticky interrupt request bit in the DMA CSR remains set until cleared by the software. It can be used to interrupt the ARM platform. The NAND_LOCK bit is monitored by the DMA channel arbiter. After a NAND channel (from channel 4 to channel 11) succeeds in the arbiter with its NAND_LOCK bit set, then the arbiter ignores the other NAND channels until a command is completed in which the NAND_LOCK is not set. Notice that the semantic here is that the NAND_LOCK state is to limit scheduling of a non-locked DMA. A DMA channel can go from unlocked to locked in the arbiter at the beginning of a command when the NAND_LOCK bit is set. When the last DMA command of an atomic sequence is completed, the lock should be i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 372 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) removed. To accomplish this, the last command does not have the NAND_LOCK bit. It is still locked in the atomic state within the arbiter when the command starts, so that it is the only NAND command that can be executed. At the end, it drops from the atomic state within the arbiter. The NAND_WAIT4READY bit also has a special use for GPMI channels (from channel 4 to channel 11), i.e., the NAND device channels. The GPMI peripheral supplies a sample of the ready line from the NAND device. This ready value is used to hold off of a command with this bit set until the ready line is asserted to 1. Once the arbiter sees a command with a wait-for-ready set, it holds off that channel until ready is asserted. Receiving an IRQ for HALTONTERMINATE (HOT) is a feature in the APBH DMA descriptor that allows GPMI (as well as SSP and I2C) to signal to the DMA engine that an error has occurred. If a commmand is stalled due to an error, a HOT signal is sent from the peripheral to the DMA engine and causes an IRQ after terminating the DMA descriptor being executed. Therefore, it is recommended that software use this signal as follows: * Always set HALTONTERMINATE to 1 in a DMA descriptor. That way, if a peripheral signals HOT, the transfer will end, leaving the peripheral block and the DMA engine synchronized (but at the end of a command). * When an IRQ from an APBH channel is received, and the IRQ is determined to be due to an error (as opposed to an IRQONCOMPLETE interrupt) the software should: * Reset the channel. * Determine the error from error reporting in the peripheral block, then manage the error in the peripheral that is attached to that channel in whatever appropriate way exists for that device (software recovery, device reset, block reset, etc). Each channel has an eight-bit counting semaphore that controls whether it is in the idle state. When the semaphore is non-zero, the channel is ready to run, process commands and perform DMA transfers. Whenever a command finishes its DMA transfer, it checks the DECREMENT_SEMAPHORE bit. If set, it decrements the counting semaphore. If the semaphore goes to 0 as a result, then the channel enters the idle state and remains there until the semaphore is incremented by the software. When the semaphore goes to non-zero and the channel is in its idle state, then it uses the value in the APBH_CHn_NXTCMDAR register (next command address register) to fetch a pointer to the next command to process. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 373 Implementation Examples NOTE This is a double indirect case. This method allows the software to append to a running command list under the protection of the counting semaphore. To start processing the first time, software creates the command list to be processed. It writes the address of the first command into the APBH_CHn_NXTCMDAR register, and then writes 1 to the counting semaphore in APBH_CHn_SEMA. The DMA channel loads APBH_CHn_CURCMDAR register and then enters the normal state machine processing for the next command. When the software writes a value to the counting semaphore, it is added to the semaphore count by hardware, protecting the case where both hardware and software are trying to change the semaphore on the same clock edge. Software can examine the value of APBH_CHn_CURCMDAR at any time to determine the location of the command structure currently being processed. 6.3 Implementation Examples 6.3.1 NAND Read Status Polling Example The following figure shows a more complicated scenario. This subset of a NAND device workload shows that the first two command structures are used during the data-write phase of an NAND device write operation (CLE and ALE transfers omitted for clarity). * After writing the data, one must wait until the NAND device status register indicates that the write charge has been transferred. This is built into the workload using a check status command in the NAND in a loop created from the next two DMA command structures. * The NO_DMA_TRANSFER command is shown here performing the read check, followed by a DMA_SENSE command to branch the DMA command structure list, based on the status of a bit in the external NAND device. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 374 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 1 PIO, chaining, no DMA, Check NAND status & set sense line NEXTCMD_ADDR 1 PIO, chaining, DMA read NEXTCMD_ADDR 512 1 0 0 0 1 10 NAND0= check status NAND0=write mode No PIO, chaining, no DMA, conditional branch based on sense line No PIO, chaining DMA read NEXTCMD_ADDR 16 0 NEXTCMD_ADDR 0 0 0 1 10 0 0 0 1 11 BUFFER ADDRESS BUFFER ADDRESS 16-Byte Spare Area 0 0 1 00 BUFFER ADDRESS BUFFER ADDRESS 512-Byte Data Block 1 1 PIO, chaining, DMA read NEXTCMD_ADDR 512 1 0 0 1 10 BUFFER ADDRESS NAND0=write mode 512-Byte Data Block No PIO,IRQ, no chaining, DMA read NEXTCMD_ADDR=0 16 0 0 1 0 10 BUFFER ADDRESS 16-Byte Spare Area Figure 6-3. AHB-to-APBH Bridge DMA NAND Read Status Polling with DMA Sense Command The example in the above figure shows the workload continuing immediately to the next NAND page transfer. However, one could perform a second sense operation to see if an error has occurred after the write. One could then point the sense command alternate branch at a NO_DMA_XFER command with the interrupt bit set. If the CHAIN bit is not i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 375 Behavior During Reset set on this failure branch, then the ARM platform is interrupted immediately, and the channel process is also immediately terminated in the presence of a workload-detected NAND error bit. Note that each word of the three-word DMA command structure corresponds to a PIO register of the DMA that is accessible on the APBH bus. Normally, the DMA copies the next command structure onto these registers for processing at the start of each command by following the value of the pointer previously loaded into the NEXTCMD_ADDR register. To start DMA processing for the first command, initialize the PIO registers of the desired channel, as follows: * First, load the next command address register with a pointer to the first command to be loaded. * Then, write 1 to the counting semaphore register. This causes the DMA to schedule the targeted channel for the DMA command structure load, just as if it had finished its previous command. 6.4 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. 6.5 Programmable Registers APBH Hardware Register Format Summary HW_APBH memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_4000 AHB to APBH Bridge Control and Status Register 0 (HW_APBH_CTRL0) 32 R/W E000_0000h 6.5.1/382 8000_4010 AHB to APBH Bridge Control and Status Register 1 (HW_APBH_CTRL1) 32 R/W 0000_0000h 6.5.2/384 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 376 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_4020 AHB to APBH Bridge Control and Status Register 2 (HW_APBH_CTRL2) 32 R/W 0000_0000h 6.5.3/387 8000_4030 AHB to APBH Bridge Channel Register (HW_APBH_CHANNEL_CTRL) 32 R/W 0000_0000h 6.5.4/392 8000_4040 AHB to APBH DMA Device Assignment Register (HW_APBH_DEVSEL) 32 R 0000_0000h 6.5.5/394 8000_4050 AHB to APBH DMA burst size (HW_APBH_DMA_BURST_SIZE) 32 R/W 0055_5555h 6.5.6/395 8000_4060 AHB to APBH DMA Debug Register (HW_APBH_DEBUG) 32 R/W 0000_0000h 6.5.7/396 8000_4100 APBH DMA Channel 0 Current Command Address Register (HW_APBH_CH0_CURCMDAR) 32 R 0000_0000h 6.5.8/397 8000_4110 APBH DMA Channel 0 Next Command Address Register (HW_APBH_CH0_NXTCMDAR) 32 R/W 0000_0000h 6.5.9/398 8000_4120 APBH DMA Channel 0 Command Register (HW_APBH_CH0_CMD) 32 R 0000_0000h 6.5.10/399 8000_4130 APBH DMA Channel 0 Buffer Address Register (HW_APBH_CH0_BAR) 32 R 0000_0000h 6.5.11/401 8000_4140 APBH DMA Channel 0 Semaphore Register (HW_APBH_CH0_SEMA) 32 R/W 0000_0000h 6.5.12/402 8000_4150 AHB to APBH DMA Channel 0 Debug Information (HW_APBH_CH0_DEBUG1) 32 R 00A0_0000h 6.5.13/403 8000_4160 AHB to APBH DMA Channel 0 Debug Information (HW_APBH_CH0_DEBUG2) 32 R 0000_0000h 6.5.14/405 8000_4170 APBH DMA Channel 1 Current Command Address Register (HW_APBH_CH1_CURCMDAR) 32 R/W 0000_0000h 6.5.15/406 8000_4180 APBH DMA Channel 1 Next Command Address Register (HW_APBH_CH1_NXTCMDAR) 32 R/W 0000_0000h 6.5.16/407 8000_4190 APBH DMA Channel 1 Command Register (HW_APBH_CH1_CMD) 32 R 0000_0000h 6.5.17/407 8000_41A0 APBH DMA Channel 1 Buffer Address Register (HW_APBH_CH1_BAR) 32 R 0000_0000h 6.5.18/409 8000_41B0 APBH DMA Channel 1 Semaphore Register (HW_APBH_CH1_SEMA) 32 R/W 0000_0000h 6.5.19/410 8000_41C0 AHB to APBH DMA Channel 1 Debug Information (HW_APBH_CH1_DEBUG1) 32 R 00A0_0000h 6.5.20/411 8000_41D0 AHB to APBH DMA Channel 1 Debug Information (HW_APBH_CH1_DEBUG2) 32 R 0000_0000h 6.5.21/413 8000_41E0 APBH DMA Channel 2 Current Command Address Register (HW_APBH_CH2_CURCMDAR) 32 R 0000_0000h 6.5.22/414 8000_41F0 APBH DMA Channel 2 Next Command Address Register (HW_APBH_CH2_NXTCMDAR) 32 R/W 0000_0000h 6.5.23/414 8000_4200 APBH DMA Channel 2 Command Register (HW_APBH_CH2_CMD) 32 R 0000_0000h 6.5.24/415 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 377 Programmable Registers HW_APBH memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_4210 APBH DMA Channel 2 Buffer Address Register (HW_APBH_CH2_BAR) 32 R 0000_0000h 6.5.25/417 8000_4220 APBH DMA Channel 2 Semaphore Register (HW_APBH_CH2_SEMA) 32 R/W 0000_0000h 6.5.26/418 8000_4230 AHB to APBH DMA Channel 2 Debug Information (HW_APBH_CH2_DEBUG1) 32 R 00A0_0000h 6.5.27/418 8000_4240 AHB to APBH DMA Channel 2 Debug Information (HW_APBH_CH2_DEBUG2) 32 R 0000_0000h 6.5.28/421 8000_4250 APBH DMA Channel 3 Current Command Address Register (HW_APBH_CH3_CURCMDAR) 32 R 0000_0000h 6.5.29/422 8000_4260 APBH DMA Channel 3 Next Command Address Register (HW_APBH_CH3_NXTCMDAR) 32 R/W 0000_0000h 6.5.30/422 8000_4270 APBH DMA Channel 3 Command Register (HW_APBH_CH3_CMD) 32 R 0000_0000h 6.5.31/423 8000_4280 APBH DMA Channel 3 Buffer Address Register (HW_APBH_CH3_BAR) 32 R 0000_0000h 6.5.32/425 8000_4290 APBH DMA Channel 3 Semaphore Register (HW_APBH_CH3_SEMA) 32 R/W 0000_0000h 6.5.33/426 8000_42A0 AHB to APBH DMA Channel 3 Debug Information (HW_APBH_CH3_DEBUG1) 32 R 00A0_0000h 6.5.34/426 8000_42B0 AHB to APBH DMA Channel 3 Debug Information (HW_APBH_CH3_DEBUG2) 32 R 0000_0000h 6.5.35/429 8000_42C0 APBH DMA Channel 4 Current Command Address Register (HW_APBH_CH4_CURCMDAR) 32 R 0000_0000h 6.5.36/430 8000_42D0 APBH DMA Channel 4 Next Command Address Register (HW_APBH_CH4_NXTCMDAR) 32 R/W 0000_0000h 6.5.37/430 8000_42E0 APBH DMA Channel 4 Command Register (HW_APBH_CH4_CMD) 32 R 0000_0000h 6.5.38/431 8000_42F0 APBH DMA Channel 4 Buffer Address Register (HW_APBH_CH4_BAR) 32 R 0000_0000h 6.5.39/433 8000_4300 APBH DMA Channel 4 Semaphore Register (HW_APBH_CH4_SEMA) 32 R/W 0000_0000h 6.5.40/434 8000_4310 AHB to APBH DMA Channel 4 Debug Information (HW_APBH_CH4_DEBUG1) 32 R 00A0_0000h 6.5.41/434 8000_4320 AHB to APBH DMA Channel 4 Debug Information (HW_APBH_CH4_DEBUG2) 32 R 0000_0000h 6.5.42/437 8000_4330 APBH DMA Channel 5 Current Command Address Register (HW_APBH_CH5_CURCMDAR) 32 R 0000_0000h 6.5.43/438 8000_4340 APBH DMA Channel 5 Next Command Address Register (HW_APBH_CH5_NXTCMDAR) 32 R/W 0000_0000h 6.5.44/438 8000_4350 APBH DMA Channel 5 Command Register (HW_APBH_CH5_CMD) 32 R 0000_0000h 6.5.45/439 8000_4360 APBH DMA Channel 5 Buffer Address Register (HW_APBH_CH5_BAR) 32 R 0000_0000h 6.5.46/441 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 378 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_4370 APBH DMA Channel 5 Semaphore Register (HW_APBH_CH5_SEMA) 32 R/W 0000_0000h 6.5.47/442 8000_4380 AHB to APBH DMA Channel 5 Debug Information (HW_APBH_CH5_DEBUG1) 32 R 00A0_0000h 6.5.48/442 8000_4390 AHB to APBH DMA Channel 5 Debug Information (HW_APBH_CH5_DEBUG2) 32 R 0000_0000h 6.5.49/445 8000_43A0 APBH DMA Channel 6 Current Command Address Register (HW_APBH_CH6_CURCMDAR) 32 R 0000_0000h 6.5.50/446 8000_43B0 APBH DMA Channel 6 Next Command Address Register (HW_APBH_CH6_NXTCMDAR) 32 R/W 0000_0000h 6.5.51/446 8000_43C0 APBH DMA Channel 6 Command Register (HW_APBH_CH6_CMD) 32 R 0000_0000h 6.5.52/447 8000_43D0 APBH DMA Channel 6 Buffer Address Register (HW_APBH_CH6_BAR) 32 R 0000_0000h 6.5.53/449 8000_43E0 APBH DMA Channel 6 Semaphore Register (HW_APBH_CH6_SEMA) 32 R/W 0000_0000h 6.5.54/450 8000_43F0 AHB to APBH DMA Channel 6 Debug Information (HW_APBH_CH6_DEBUG1) 32 R 00A0_0000h 6.5.55/450 8000_4400 AHB to APBH DMA Channel 6 Debug Information (HW_APBH_CH6_DEBUG2) 32 R 0000_0000h 6.5.56/453 8000_4410 APBH DMA Channel 7 Current Command Address Register (HW_APBH_CH7_CURCMDAR) 32 R 0000_0000h 6.5.57/454 8000_4420 APBH DMA Channel 7 Next Command Address Register (HW_APBH_CH7_NXTCMDAR) 32 R/W 0000_0000h 6.5.58/454 8000_4430 APBH DMA Channel 7 Command Register (HW_APBH_CH7_CMD) 32 R 0000_0000h 6.5.59/455 8000_4440 APBH DMA Channel 7 Buffer Address Register (HW_APBH_CH7_BAR) 32 R 0000_0000h 6.5.60/457 8000_4450 APBH DMA Channel 7 Semaphore Register (HW_APBH_CH7_SEMA) 32 R/W 0000_0000h 6.5.61/458 8000_4460 AHB to APBH DMA Channel 7 Debug Information (HW_APBH_CH7_DEBUG1) 32 R 00A0_0000h 6.5.62/458 8000_4470 AHB to APBH DMA Channel 7 Debug Information (HW_APBH_CH7_DEBUG2) 32 R 0000_0000h 6.5.63/461 8000_4480 APBH DMA Channel 8 Current Command Address Register (HW_APBH_CH8_CURCMDAR) 32 R 0000_0000h 6.5.64/462 8000_4490 APBH DMA Channel 8 Next Command Address Register (HW_APBH_CH8_NXTCMDAR) 32 R/W 0000_0000h 6.5.65/462 8000_44A0 APBH DMA Channel 8 Command Register (HW_APBH_CH8_CMD) 32 R 0000_0000h 6.5.66/463 8000_44B0 APBH DMA Channel 8 Buffer Address Register (HW_APBH_CH8_BAR) 32 R 0000_0000h 6.5.67/465 8000_44C0 APBH DMA Channel 8 Semaphore Register (HW_APBH_CH8_SEMA) 32 R/W 0000_0000h 6.5.68/466 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 379 Programmable Registers HW_APBH memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_44D0 AHB to APBH DMA Channel 8 Debug Information (HW_APBH_CH8_DEBUG1) 32 R 00A0_0000h 6.5.69/466 8000_44E0 AHB to APBH DMA Channel 8 Debug Information (HW_APBH_CH8_DEBUG2) 32 R 0000_0000h 6.5.70/469 8000_44F0 APBH DMA Channel 9 Current Command Address Register (HW_APBH_CH9_CURCMDAR) 32 R 0000_0000h 6.5.71/470 8000_4500 APBH DMA Channel 9 Next Command Address Register (HW_APBH_CH9_NXTCMDAR) 32 R/W 0000_0000h 6.5.72/470 8000_4510 APBH DMA Channel 9 Command Register (HW_APBH_CH9_CMD) 32 R 0000_0000h 6.5.73/471 8000_4520 APBH DMA Channel 9 Buffer Address Register (HW_APBH_CH9_BAR) 32 R 0000_0000h 6.5.74/473 8000_4530 APBH DMA Channel 9 Semaphore Register (HW_APBH_CH9_SEMA) 32 R/W 0000_0000h 6.5.75/474 8000_4540 AHB to APBH DMA Channel 9 Debug Information (HW_APBH_CH9_DEBUG1) 32 R 00A0_0000h 6.5.76/474 8000_4550 AHB to APBH DMA Channel 9 Debug Information (HW_APBH_CH9_DEBUG2) 32 R 0000_0000h 6.5.77/477 8000_4560 APBH DMA channel 10 Current Command Address Register (HW_APBH_CH10_CURCMDAR) 32 R 0000_0000h 6.5.78/478 8000_4570 APBH DMA channel 10 Next Command Address Register (HW_APBH_CH10_NXTCMDAR) 32 R/W 0000_0000h 6.5.79/478 8000_4580 APBH DMA channel 10 Command Register (HW_APBH_CH10_CMD) 32 R 0000_0000h 6.5.80/479 8000_4590 APBH DMA channel 10 Buffer Address Register (HW_APBH_CH10_BAR) 32 R 0000_0000h 6.5.81/481 8000_45A0 APBH DMA channel 10 Semaphore Register (HW_APBH_CH10_SEMA) 32 R/W 0000_0000h 6.5.82/482 8000_45B0 AHB to APBH DMA channel 10 Debug Information (HW_APBH_CH10_DEBUG1) 32 R 00A0_0000h 6.5.83/482 8000_45C0 AHB to APBH DMA channel 10 Debug Information (HW_APBH_CH10_DEBUG2) 32 R 0000_0000h 6.5.84/485 8000_45D0 APBH DMA Channel 11 Current Command Address Register (HW_APBH_CH11_CURCMDAR) 32 R 0000_0000h 6.5.85/486 8000_45E0 APBH DMA Channel 11 Next Command Address Register (HW_APBH_CH11_NXTCMDAR) 32 R/W 0000_0000h 6.5.86/486 8000_45F0 APBH DMA Channel 11 Command Register (HW_APBH_CH11_CMD) 32 R 0000_0000h 6.5.87/487 8000_4600 APBH DMA Channel 11 Buffer Address Register (HW_APBH_CH11_BAR) 32 R 0000_0000h 6.5.88/489 8000_4610 APBH DMA Channel 11 Semaphore Register (HW_APBH_CH11_SEMA) 32 R/W 0000_0000h 6.5.89/490 8000_4620 AHB to APBH DMA Channel 11 Debug Information (HW_APBH_CH11_DEBUG1) 32 R 00A0_0000h 6.5.90/490 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 380 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_4630 AHB to APBH DMA Channel 11 Debug Information (HW_APBH_CH11_DEBUG2) 32 R 0000_0000h 6.5.91/493 8000_4640 APBH DMA channel 12 Current Command Address Register (HW_APBH_CH12_CURCMDAR) 32 R 0000_0000h 6.5.92/494 8000_4650 APBH DMA channel 12 Next Command Address Register (HW_APBH_CH12_NXTCMDAR) 32 R/W 0000_0000h 6.5.93/494 8000_4660 APBH DMA channel 12 Command Register (HW_APBH_CH12_CMD) 32 R 0000_0000h 6.5.94/495 8000_4670 APBH DMA channel 12 Buffer Address Register (HW_APBH_CH12_BAR) 32 R 0000_0000h 6.5.95/497 8000_4680 APBH DMA channel 12 Semaphore Register (HW_APBH_CH12_SEMA) 32 R/W 0000_0000h 6.5.96/498 8000_4690 AHB to APBH DMA channel 12 Debug Information (HW_APBH_CH12_DEBUG1) 32 R 00A0_0000h 6.5.97/498 8000_46A0 AHB to APBH DMA channel 12 Debug Information (HW_APBH_CH12_DEBUG2) 32 R 0000_0000h 6.5.98/501 8000_46B0 APBH DMA Channel 13 Current Command Address Register (HW_APBH_CH13_CURCMDAR) 32 R 0000_0000h 6.5.99/502 8000_46C0 APBH DMA Channel 13 Next Command Address Register (HW_APBH_CH13_NXTCMDAR) 32 R/W 0000_0000h 6.5.100/502 8000_46D0 APBH DMA Channel 13 Command Register (HW_APBH_CH13_CMD) 32 R 0000_0000h 6.5.101/503 8000_46E0 APBH DMA Channel 13 Buffer Address Register (HW_APBH_CH13_BAR) 32 R 0000_0000h 6.5.102/505 8000_46F0 APBH DMA Channel 13 Semaphore Register (HW_APBH_CH13_SEMA) 32 R/W 0000_0000h 6.5.103/506 8000_4700 AHB to APBH DMA Channel 13 Debug Information (HW_APBH_CH13_DEBUG1) 32 R 00A0_0000h 6.5.104/506 8000_4710 AHB to APBH DMA Channel 13 Debug Information (HW_APBH_CH13_DEBUG2) 32 R 0000_0000h 6.5.105/509 8000_4720 APBH DMA channel 14 Current Command Address Register (HW_APBH_CH14_CURCMDAR) 32 R 0000_0000h 6.5.106/510 8000_4730 APBH DMA channel 14 Next Command Address Register (HW_APBH_CH14_NXTCMDAR) 32 R/W 0000_0000h 6.5.107/510 8000_4740 APBH DMA channel 14 Command Register (HW_APBH_CH14_CMD) 32 R 0000_0000h 6.5.108/511 8000_4750 APBH DMA channel 14 Buffer Address Register (HW_APBH_CH14_BAR) 32 R 0000_0000h 6.5.109/513 8000_4760 APBH DMA channel 14 Semaphore Register (HW_APBH_CH14_SEMA) 32 R/W 0000_0000h 6.5.110/514 8000_4770 AHB to APBH DMA channel 14 Debug Information (HW_APBH_CH14_DEBUG1) 32 R 0000_0000h 6.5.111/514 8000_4780 AHB to APBH DMA channel 14 Debug Information (HW_APBH_CH14_DEBUG2) 32 R 0000_0000h 6.5.112/517 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 381 Programmable Registers HW_APBH memory map (continued) Absolute address (hex) Register name 8000_4790 APBH DMA channel 15 Current Command Address Register (HW_APBH_CH15_CURCMDAR) 32 8000_47A0 APBH DMA channel 15 Next Command Address Register (HW_APBH_CH15_NXTCMDAR) 8000_47B0 Width Access (in bits) Reset value Section/ page R 0000_0000h 6.5.113/518 32 R/W 0000_0000h 6.5.114/518 APBH DMA channel 15 Command Register (HW_APBH_CH15_CMD) 32 R 0000_0000h 6.5.115/519 8000_47C0 APBH DMA channel 15 Buffer Address Register (HW_APBH_CH15_BAR) 32 R 0000_0000h 6.5.116/521 8000_47D0 APBH DMA channel 15 Semaphore Register (HW_APBH_CH15_SEMA) 32 R/W 0000_0000h 6.5.117/522 8000_47E0 AHB to APBH DMA channel 15 Debug Information (HW_APBH_CH15_DEBUG1) 32 R 0000_0000h 6.5.118/522 8000_47F0 AHB to APBH DMA channel 15 Debug Information (HW_APBH_CH15_DEBUG2) 32 R 0000_0000h 6.5.119/525 8000_4800 APBH Bridge Version Register (HW_APBH_VERSION) 32 R 0301_0000h 6.5.120/525 6.5.1 AHB to APBH Bridge Control and Status Register 0 (HW_APBH_CTRL0) The APBH CTRL 0 provides overall control of the AHB to APBH bridge and DMA. HW_APBH_CTRL0: 0x000 HW_APBH_CTRL0_SET: 0x004 HW_APBH_CTRL0_CLR: 0x008 HW_APBH_CTRL0_TOG: 0x00C This register contains module softreset, clock gating, channel clock gating/freeze bits. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 382 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 0h offset = 8000_4000h Bit 31 30 26 25 24 23 22 21 20 19 18 17 16 AHB_BURST8_EN APB_BURST_EN RSVD0 CLKGATE Bit 27 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 W Reset 28 SFTRST R 29 R CLKGATE_CHANNEL W Reset 0 0 0 0 0 0 0 0 0 0 HW_APBH_CTRL0 field descriptions Field 31 SFTRST 30 CLKGATE Description Set this bit to zero to enable normal APBH DMA operation. Set this bit to one (default) to disable clocking with the APBH DMA and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the APBH DMA block to its default state. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. 29 Set this bit to one (default) to enable AHB 8-beat burst. Set to zero to disable 8-beat burst on AHB AHB_BURST8_ interface. EN 28 Set this bit to one to enable apb master do a continous transfers when a device request a burst dma. Set APB_BURST_EN to zero will treat a burst dma request as 4/8 individual requests. 27-16 RSVD0 CLKGATE_ CHANNEL Reserved, always set to zero. These bits must be set to zero for normal operation of each channel. When set to one they gate off the individual clocks to the channels. 0x0001 0x0002 0x0004 SSP0 -- SSP1 -- SSP2 -- Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 383 Programmable Registers HW_APBH_CTRL0 field descriptions (continued) Field Description 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 SSP3 -- NAND0 -- NAND1 -- NAND2 -- NAND3 -- NAND4 -- NAND5 -- NAND6 -- NAND7 -- HSADC -- LCDIF -- 6.5.2 AHB to APBH Bridge Control and Status Register 1 (HW_APBH_CTRL1) The APBH CTRL one provides overall control of the interrupts generated by the AHB to APBH DMA. HW_APBH_CTRL1: 0x010 HW_APBH_CTRL1_SET: 0x014 HW_APBH_CTRL1_CLR: 0x018 HW_APBH_CTRL1_TOG: 0x01C This register contains the per channel interrupt status bits and the per channel interrupt enable bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller. EXAMPLE BF_WR(APBH_CTRL1, CH5_CMDCMPLT_IRQ, 0); BF_APBH_CTRL1.CH5_CMDCMPLT_IRQ = 0; // use bitfield write macro // or, assign to register struct's bitfield 0 0 0 0 0 0 23 22 21 20 19 18 17 16 CH0_CMDCMPLT_ IRQ_EN 0 24 CH1_CMDCMPLT_ IRQ_EN 25 CH2_CMDCMPLT_ IRQ_EN 26 CH3_CMDCMPLT_ IRQ_EN 27 CH4_CMDCMPLT_ IRQ_EN Reset 28 CH5_CMDCMPLT_ IRQ_EN W 29 CH6_CMDCMPLT_ IRQ_EN R 30 CH7_CMDCMPLT_ IRQ_EN 31 CH15_ CMDCMPLT_IRQ_ EN CH14_ CMDCMPLT_IRQ_ EN CH13_ CMDCMPLT_IRQ_ EN CH12_ CMDCMPLT_IRQ_ EN CH11_ CMDCMPLT_IRQ_ EN CH10_ CMDCMPLT_IRQ_ EN CH9_CMDCMPLT_ IRQ_EN Bit CH8_CMDCMPLT_ IRQ_EN Address: 8000_4000h base + 10h offset = 8000_4010h 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 384 Freescale Semiconductor, Inc. 12 11 10 9 8 7 6 5 4 3 2 1 0 CH11_ CMDCMPLT_IRQ CH10_ CMDCMPLT_IRQ CH9_CMDCMPLT_ IRQ CH8_CMDCMPLT_ IRQ CH7_CMDCMPLT_ IRQ CH6_CMDCMPLT_ IRQ CH5_CMDCMPLT_ IRQ CH4_CMDCMPLT_ IRQ CH3_CMDCMPLT_ IRQ CH2_CMDCMPLT_ IRQ CH1_CMDCMPLT_ IRQ CH0_CMDCMPLT_ IRQ Reset 13 CH12_ CMDCMPLT_IRQ W 14 CH13_ CMDCMPLT_IRQ R 15 CH14_ CMDCMPLT_IRQ Bit CH15_ CMDCMPLT_IRQ Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CTRL1 field descriptions Field Description 31 CH15_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 15. 30 CH14_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 14. 29 CH13_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 13. 28 CH12_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 12. 27 CH11_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 11. 26 CH10_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 10. 25 CH9_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 9. 24 CH8_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 8. 23 CH7_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 7. 22 CH6_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 6. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 385 Programmable Registers HW_APBH_CTRL1 field descriptions (continued) Field Description 21 CH5_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 5. 20 CH4_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 4. 19 CH3_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 3. 18 CH2_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 2. 17 CH1_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 1. 16 CH0_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBH DMA channel 0. 15 CH15_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA Channel 15. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 14 CH14_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA Channel 14. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 13 CH13_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA Channel 13. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 12 CH12_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA Channel 12. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 11 CH11_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA Channel 11. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 10 CH10_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA Channel 10. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 386 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CTRL1 field descriptions (continued) Field Description 9 CH9_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA Channel 9. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 8 CH8_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA Channel 8. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 7 CH7_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA channel 7. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 6 CH6_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA channel 6. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 5 CH5_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA channel 5. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 4 CH4_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA channel 4. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 3 CH3_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA channel 3. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 2 CH2_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA channel 2. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 1 CH1_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA channel 1. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 0 CH0_ CMDCMPLT_ IRQ Interrupt request status bit for APBH DMA channel 0. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 6.5.3 AHB to APBH Bridge Control and Status Register 2 (HW_APBH_CTRL2) The APBH CTRL 2 provides channel error interrupts generated by the AHB to APBH DMA. HW_APBH_CTRL2: 0x020 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 387 Programmable Registers HW_APBH_CTRL2_SET: 0x024 HW_APBH_CTRL2_CLR: 0x028 HW_APBH_CTRL2_TOG: 0x02C This register contains the per channel interrupt status bits and the per channel interrupt enable bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller. EXAMPLE BF_WR(APBH_CTRL1, CH5_CMDCMPLT_IRQ, 0); BF_APBH_CTRL1.CH5_CMDCMPLT_IRQ = 0; // use bitfield write macro // or, assign to register struct's bitfield 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CH13_ERROR_STATUS CH12_ERROR_STATUS CH11_ERROR_STATUS CH10_ERROR_STATUS CH9_ERROR_STATUS CH8_ERROR_STATUS CH7_ERROR_STATUS CH6_ERROR_STATUS CH5_ERROR_STATUS CH4_ERROR_STATUS CH3_ERROR_STATUS CH2_ERROR_STATUS CH1_ERROR_STATUS CH0_ERROR_STATUS R 31 CH14_ERROR_STATUS Bit CH15_ERROR_STATUS Address: 8000_4000h base + 20h offset = 8000_4020h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 388 Freescale Semiconductor, Inc. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH14_ERROR_IRQ CH13_ERROR_IRQ CH12_ERROR_IRQ CH11_ERROR_IRQ CH10_ERROR_IRQ CH9_ERROR_IRQ CH8_ERROR_IRQ CH7_ERROR_IRQ CH6_ERROR_IRQ CH5_ERROR_IRQ CH4_ERROR_IRQ CH3_ERROR_IRQ CH2_ERROR_IRQ CH1_ERROR_IRQ CH0_ERROR_IRQ Bit CH15_ERROR_IRQ Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W Reset HW_APBH_CTRL2 field descriptions Field Description 31 Error status bit for APBH DMA Channel 15. Valid when corresponding Error IRQ is set. CH15_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 30 Error status bit for APBH DMA Channel 14. Valid when corresponding Error IRQ is set. CH14_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 29 Error status bit for APBH DMA Channel 13. Valid when corresponding Error IRQ is set. CH13_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 28 Error status bit for APBH DMA Channel 12. Valid when corresponding Error IRQ is set. CH12_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 27 Error status bit for APBH DMA Channel 11. Valid when corresponding Error IRQ is set. CH11_ERROR_ 1 - AHB bus error STATUS Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 389 Programmable Registers HW_APBH_CTRL2 field descriptions (continued) Field Description 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 26 Error status bit for APBH DMA Channel 10. Valid when corresponding Error IRQ is set. CH10_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 25 CH9_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBH DMA Channel 9. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 24 CH8_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBH DMA Channel 8. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 23 CH7_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 7. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 22 CH6_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 6. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 21 CH5_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 5. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 20 CH4_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 4. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 390 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CTRL2 field descriptions (continued) Field Description 0x0 0x1 19 CH3_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 3. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 18 CH2_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 2. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 17 CH1_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 1. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 16 CH0_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 0. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 15 Error interrupt status bit for APBH DMA Channel 15. This sticky bit is set by DMA hardware and reset by CH15_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 14 Error interrupt status bit for APBH DMA Channel 14. This sticky bit is set by DMA hardware and reset by CH14_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 13 Error interrupt status bit for APBH DMA Channel 13. This sticky bit is set by DMA hardware and reset by CH13_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 12 Error interrupt status bit for APBH DMA Channel 12. This sticky bit is set by DMA hardware and reset by CH12_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 11 Error interrupt status bit for APBH DMA Channel 11. This sticky bit is set by DMA hardware and reset by CH11_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 10 Error interrupt status bit for APBH DMA Channel 10. This sticky bit is set by DMA hardware and reset by CH10_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 391 Programmable Registers HW_APBH_CTRL2 field descriptions (continued) Field Description 9 CH9_ERROR_ IRQ Error interrupt status bit for APBH DMA Channel 9. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 8 CH8_ERROR_ IRQ Error interrupt status bit for APBH DMA Channel 8. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 7 CH7_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 7. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 6 CH6_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 6. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 5 CH5_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 5. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 4 CH4_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 4. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 3 CH3_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 3. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 2 CH2_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 2. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 1 CH1_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 1. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 0 CH0_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 0. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 6.5.4 AHB to APBH Bridge Channel Register (HW_APBH_CHANNEL_CTRL) The APBH CHANNEL CTRL provides reset/freeze control of each DMA channel. HW_APBH_CHANNEL_CTRL: 0x030 HW_APBH_CHANNEL_CTRL_SET: 0x034 HW_APBH_CHANNEL_CTRL_CLR: 0x038 HW_APBH_CHANNEL_CTRL_TOG: 0x03C This register contains individual channel reset/freeze bits. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 392 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 30h offset = 8000_4030h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RESET_CHANNEL 0 0 0 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 FREEZE_CHANNEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CHANNEL_CTRL field descriptions Field Description 31-16 RESET_ CHANNEL Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state. The bit is reset after the channel resources are cleared. FREEZE_ CHANNEL Setting a bit in this field will freeze the DMA channel associated with it. This field is a direct input to the DMA channel arbiter. When frozen, the channel is denied access to the central DMA resources. Note: 1. DMA PIO write to associated peripheral is not supported when Freeze bit is set, and use ARM instead to configure peripheral. 2. After FREEZE bit is set, no more access, neither AHB access to memory nor APB access to peripherals, will be allowed by arbiter. But, there might be on-going channel access exactly when FREEZE bit is set, either INCR8/INCR4/SINGLE AHB access or APB peripheral access, this ongoing access will not be affected by FREEZE bit and will finish as normal. That is to say, setting FREEZE bit might not freeze channel access immediately, it only freezes further channel access, and you have to wait a while to freeze channel access completely. To make sure that there is no more access from freezed channel, channel state machine should be checked by reading channel DEBUG1 register, wait till state stunk at any of IDLE, READ_REQ, WRITE, or CHAIN_WAIT. 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 0x0001 0x0002 0x0004 0x0008 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 SSP0 -- SSP1 -- SSP2 -- SSP3 -- NAND0 -- NAND1 -- NAND2 -- NAND3 -- NAND4 -- NAND5 -- NAND6 -- NAND7 -- HSADC -- LCDIF -- SSP0 -- SSP1 -- SSP2 -- SSP3 -- NAND0 -- NAND1 -- NAND2 -- NAND3 -- NAND4 -- NAND5 -- NAND6 -- NAND7 -- HSADC -- LCDIF -- i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 393 Programmable Registers 6.5.5 AHB to APBH DMA Device Assignment Register (HW_APBH_DEVSEL) This register allows reassignment of the APBH device connected to the DMA Channels. In this chip, apbhdma channel resource is enough for high speed peripherals, so this register is of no use and reserved. Address: 8000_4000h base + 40h offset = 8000_4040h Bit 31 30 29 CH15 R 28 27 CH14 26 25 CH13 24 23 CH12 22 21 CH11 20 19 CH10 18 17 CH9 16 CH8 W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH7 R CH6 CH5 CH4 CH3 CH2 CH1 CH0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_DEVSEL field descriptions Field Description 31-30 CH15 Reserved. 29-28 CH14 Reserved. 27-26 CH13 Reserved. 25-24 CH12 Reserved. 23-22 CH11 Reserved. 21-20 CH10 Reserved. 19-18 CH9 Reserved. 17-16 CH8 Reserved. 15-14 CH7 Reserved. 13-12 CH6 Reserved. 11-10 CH5 Reserved. 9-8 CH4 Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 394 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_DEVSEL field descriptions (continued) Field Description 7-6 CH3 Reserved. 5-4 CH2 Reserved. 3-2 CH1 Reserved. CH0 Reserved. 6.5.6 AHB to APBH DMA burst size (HW_APBH_DMA_BURST_SIZE) This register programs the apbh burst size of the APBH DMA devices when a DMA burst request is issued. It provides a mechanism for improving bandwidth between DMA and device if device's FIFO is large enough. Address: 8000_4000h base + 50h offset = 8000_4050h Bit 31 30 29 CH15 R 28 27 CH14 26 25 CH13 24 23 CH12 Bit 20 19 CH10 18 17 CH9 16 CH8 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CH7 W Reset 21 CH11 W Reset 22 0 CH6 1 0 CH5 1 0 CH4 1 0 CH3 1 0 CH2 1 0 CH1 1 0 CH0 1 0 1 HW_APBH_DMA_BURST_SIZE field descriptions Field Description 31-30 CH15 Reserved. 29-28 CH14 Reserved. 27-26 CH13 Reserved. HSADC not support DMA burst request. 25-24 CH12 Reserved.LCDIF not support DMA burst request. 23-22 CH11 DMA burst size for GPMI channel 7. Do not change. GPMI only support burst size 4. 21-20 CH10 DMA burst size for GPMI channel 6. Do not change. GPMI only support burst size 4. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 395 Programmable Registers HW_APBH_DMA_BURST_SIZE field descriptions (continued) Field Description 19-18 CH9 DMA burst size for GPMI channel 5. Do not change. GPMI only support burst size 4. 17-16 CH8 DMA burst size for GPMI channel 4. Do not change. GPMI only support burst size 4. 15-14 CH7 DMA burst size for GPMI channel 3. Do not change. GPMI only support burst size 4. 13-12 CH6 DMA burst size for GPMI channel 2. Do not change. GPMI only support burst size 4. 11-10 CH5 DMA burst size for GPMI channel 1. Do not change. GPMI only support burst size 4. 9-8 CH4 DMA burst size for GPMI channel 0. Do not change. GPMI only support burst size 4. 7-6 CH3 DMA burst size for SSP3. 5-4 CH2 DMA burst size for SSP2. 3-2 CH1 DMA burst size for SSP1. CH0 DMA burst size for SSP0. 0x0 0x1 0x2 0x0 0x1 0x2 0x0 0x1 0x2 0x0 0x1 0x2 BURST0 -- BURST4 -- BURST8 -- BURST0 -- BURST4 -- BURST8 -- BURST0 -- BURST4 -- BURST8 -- BURST0 -- BURST4 -- BURST8 -- 6.5.7 AHB to APBH DMA Debug Register (HW_APBH_DEBUG) This register is for debug purpose. It is for internal use only. Not recommend for customer usage. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 396 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 60h offset = 8000_4060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSVD R GPMI_ONE_FIFO Reset W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_DEBUG field descriptions Field 31-1 RSVD 0 GPMI_ONE_ FIFO Description Reserved, always set to zero. Set to one and the eight GPMI channels will share the DMA FIFO, and when set to zero, the eight GPMI channels will use its own DMA FIFO. 6.5.8 APBH DMA Channel 0 Current Command Address Register (HW_APBH_CH0_CURCMDAR) The APBH DMA channel 0 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 0 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 397 Programmable Registers EXAMPLE pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR_RD(0); register, since there is only one field pCurCmd = (hw_apbh_chn_cmd_t *) BF_RDn(APBH_CHn_CURCMDAR, 0, CMD_ADDR); register bitfield read macro pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR(0).CMD_ADDR; bitfield of indexed register's struct // read the whole // or, use multi// or, assign from Address: 8000_4000h base + 100h offset = 8000_4100h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH0_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 0. 6.5.9 APBH DMA Channel 0 Next Command Address Register (HW_APBH_CH0_NXTCMDAR) The APBH DMA Channel 0 Next Command Address register contains the address of the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to 1 in the DMA command word to process command lists. APBH DMA Channel 0 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 0 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE HW_APBH_CHn_NXTCMDAR_WR(0, (reg32_t) pCommandTwoStructure); register, since there is only one field BF_WRn(APBH_CHn_NXTCMDAR, 0, (reg32_t) pCommandTwoStructure); register bitfield write macro HW_APBH_CHn_NXTCMDAR(0).CMD_ADDR = (reg32_t) pCommandTwoStructure; bitfield of indexed register's struct // write the entire // or, use multi// or, assign to Address: 8000_4000h base + 110h offset = 8000_4110h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 398 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH0_NXTCMDAR field descriptions Field Description CMD_ADDR Pointer to next command structure for channel 0. 6.5.10 APBH DMA Channel 0 Command Register (HW_APBH_CH0_CMD) The APBH DMA Channel 0 command register specifies the DMA transaction to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE hw_apbh_chn_cmd_t dma_cmd; dma_cmd.XFER_COUNT = 512; dma_cmd.COMMAND = BV_APBH_CHn_CMD_COMMAND__DMA_WRITE; peripheral device dma_cmd.CHAIN = 1; structure on to the list dma_cmd.IRQONCMPLT = 1; completion of this command structure // transfer 512 bytes // transfer to system memory from // chain an additional command // generate an interrupt on Address: 8000_4000h base + 120h offset = 8000_4120h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 399 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH0_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SSP0 device. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the SSP0, starting with the base PIO address of the SSP0 control register and incrementing from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 400 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH0_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH0_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from the SSP0 (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.11 APBH DMA Channel 0 Buffer Address Register (HW_APBH_CH0_BAR) The APBH DMA Channel 0 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE hw_apbh_chn_bar_t dma_data; dma_data.ADDRESS = (reg32_t) pDataBuffer; Address: 8000_4000h base + 130h offset = 8000_4130h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 401 Programmable Registers HW_APBH_CH0_BAR field descriptions Field Description ADDRESS Address of system memory buffer to be read or written over the AHB bus. 6.5.12 APBH DMA Channel 0 Semaphore Register (HW_APBH_CH0_SEMA) The APBH DMA Channel 0 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE BF_WR(APBH_CHn_SEMA, 0, INCREMENT_SEMA, 2); current_sema = BF_RD(APBH_CHn_SEMA, 0, PHORE); // increment semaphore by two // get instantaneous value Address: 8000_4000h base + 140h offset = 8000_4140h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH0_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 402 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.13 AHB to APBH DMA Channel 0 Debug Information (HW_APBH_CH0_DEBUG1) This register gives debug visibility into the APBH DMA Channel 0 state machine and controls. This register allows debug visibility of the APBH DMA Channel 0. 30 29 28 27 26 25 24 23 22 21 20 KICK END SENSE READY LOCK NEXTCMDADDRVALID RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL R 31 BURST Bit REQ Address: 8000_4000h base + 150h offset = 8000_4150h 0 0 0 0 0 0 0 0 1 0 1 0 19 18 17 16 RSVD1 W Reset 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 403 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 RSVD1 R 3 2 1 0 STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH0_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit is reserved for this DMA Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit is reserved for this DMA Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit is reserved for this Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID This bit reflects the internal bit which indicates whether the channel's next command address is valid. 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 0 state machine state. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 404 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH0_DEBUG1 field descriptions (continued) Field Description 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x14 0x15 0x1C 0x1D 0x1E 0x1F IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.14 AHB to APBH DMA Channel 0 Debug Information (HW_APBH_CH0_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 0. This register allows debug visibility of the APBH DMA Channel 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 405 Programmable Registers Address: 8000_4000h base + 160h offset = 8000_4160h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH0_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 6.5.15 APBH DMA Channel 1 Current Command Address Register (HW_APBH_CH1_CURCMDAR) The APBH DMA Channel 1 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 1 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR_RD(1); register, since there is only one field pCurCmd = (hw_apbh_chn_cmd_t *) BF_RDn(APBH_CHn_CURCMDAR, 1, CMD_ADDR); register bitfield read macro pCurCmd = (hw_apbh_chn_cmd_t *) HW_APBH_CHn_CURCMDAR(1).CMD_ADDR; bitfield of indexed register's struct // read the whole // or, use multi// or, assign from Address: 8000_4000h base + 170h offset = 8000_4170h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH1_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for channel 1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 406 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.16 APBH DMA Channel 1 Next Command Address Register (HW_APBH_CH1_NXTCMDAR) The APBH DMA Channel 1 Next Command Address register contains the address of the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to 1 in the DMA command word to process command lists. APBH DMA Channel 1 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 1 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE HW_APBH_CHn_NXTCMDAR_WR(1, (reg32_t) pCommandTwoStructure); register, since there is only one field BF_WRn(APBH_CHn_NXTCMDAR, 1, (reg32_t) pCommandTwoStructure); register bitfield write macro HW_APBH_CHn_NXTCMDAR(1).CMD_ADDR = (reg32_t) pCommandTwoStructure; bitfield of indexed register's struct // write the entire // or, use multi// or, assign to Address: 8000_4000h base + 180h offset = 8000_4180h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH1_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 1. 6.5.17 APBH DMA Channel 1 Command Register (HW_APBH_CH1_CMD) The APBH DMA Channel 1 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 407 Programmable Registers Address: 8000_4000h base + 190h offset = 8000_4190h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XFER_COUNT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEMAPHORE NANDWAIT4READY NANDLOCK IRQONCMPLT CHAIN Bit 0 WAIT4ENDCMD Reset HALTONTERMINATE W 0 0 0 0 0 0 0 CMDWORDS R RSVD1 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH1_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SSP1 device. A value of 0 indicates a 64 KBytes trasnfer size. This field indicates the number of command words to send to the SSP1, starting with the base PIO address of the SSP1 control register and incrementing from there. Zero means transfer NO command words Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 408 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH1_CMD field descriptions (continued) Field 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH1_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from the SSP1 (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.18 APBH DMA Channel 1 Buffer Address Register (HW_APBH_CH1_BAR) The APBH DMA Channel 1 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 409 Programmable Registers This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE hw_apbh_chn_bar_t dma_data; dma_data.ADDRESS = (reg32_t) pDataBuffer; Address: 8000_4000h base + 1A0h offset = 8000_41A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH1_BAR field descriptions Field Description ADDRESS Address of system memory buffer to be read or written over the AHB bus. 6.5.19 APBH DMA Channel 1 Semaphore Register (HW_APBH_CH1_SEMA) The APBH DMA Channel 1 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE BF_WR(APBH_CHn_SEMA, 1, INCREMENT_SEMA, 2); current_sema = BF_RD(APBH_CHn_SEMA, 1, PHORE); // increment semaphore by two // get instantaneous value Address: 8000_4000h base + 1B0h offset = 8000_41B0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 410 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH1_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.20 AHB to APBH DMA Channel 1 Debug Information (HW_APBH_CH1_DEBUG1) This register gives debug visibility into the APBH DMA Channel 1 state machine and controls. This register allows debug visibility of the APBH DMA Channel 1. 30 29 28 27 26 25 24 23 22 21 20 KICK END SENSE READY LOCK NEXTCMDADDRVALID RD_FIFO_EMPTY RD_FIFO_FULL WR_FIFO_EMPTY WR_FIFO_FULL R 31 BURST Bit REQ Address: 8000_4000h base + 1C0h offset = 8000_41C0h 0 0 0 0 0 0 0 0 1 0 1 0 19 18 17 16 RSVD1 W Reset 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 411 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 RSVD1 R 3 2 1 0 STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH1_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit is reserved for this DMA Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit is reserved for this DMA Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit is reserved for this Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID This bit reflect the internal bit which indicates whether the channel's next command address is valid. 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflect the current state of the DMA Channel's Read FIFO Empty signal. This bit reflect the current state of the DMA Channel's Read FIFO Full signal. This bit reflect the current state of the DMA Channel's Write FIFO Empty signal. This bit reflect the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 1 state machine state. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 412 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH1_DEBUG1 field descriptions (continued) Field Description 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x14 0x15 0x1C 0x1D 0x1E 0x1F IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.21 AHB to APBH DMA Channel 1 Debug Information (HW_APBH_CH1_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 1. This register allows debug visibility of the APBH DMA Channel 1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 413 Programmable Registers Address: 8000_4000h base + 1D0h offset = 8000_41D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH1_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 6.5.22 APBH DMA Channel 2 Current Command Address Register (HW_APBH_CH2_CURCMDAR) The APBH DMA Channel 2 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 2 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 1E0h offset = 8000_41E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH2_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for channel 2. 6.5.23 APBH DMA Channel 2 Next Command Address Register (HW_APBH_CH2_NXTCMDAR) The APBH DMA Channel 2 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 414 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) APBH DMA Channel 2 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 0 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 1F0h offset = 8000_41F0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH2_NXTCMDAR field descriptions Field Description CMD_ADDR Pointer to next command structure for channel 2. 6.5.24 APBH DMA Channel 2 Command Register (HW_APBH_CH2_CMD) The APBH DMA Channel 2 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 200h offset = 8000_4200h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 415 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH2_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SSP2 device. A value of 0 indicates a 64 KBytes trasnfer size. This field indicates the number of command words to send to the SSP2, starting with the base PIO address of the SSP2 control register and incrementing from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 416 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH2_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH1_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from the SSP2 (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.25 APBH DMA Channel 2 Buffer Address Register (HW_APBH_CH2_BAR) The APBH DMA Channel 2 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 210h offset = 8000_4210h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH2_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 417 Programmable Registers 6.5.26 APBH DMA Channel 2 Semaphore Register (HW_APBH_CH2_SEMA) The APBH DMA Channel 2 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 220h offset = 8000_4220h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH2_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.27 AHB to APBH DMA Channel 2 Debug Information (HW_APBH_CH2_DEBUG1) This register gives debug visibility into the APBH DMA Channel 2 state machine and controls. This register allows debug visibility of the APBH DMA Channel 2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 418 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 230h offset = 8000_4230h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH2_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 419 Programmable Registers HW_APBH_CH2_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit is reserved for this DMA Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit is reserved for this DMA Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit is reserved for this Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID This bit reflect the internal bit which indicates whether the channel's next command address is valid. 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflect the current state of the DMA Channel's Read FIFO Empty signal. This bit reflect the current state of the DMA Channel's Read FIFO Full signal. This bit reflect the current state of the DMA Channel's Write FIFO Empty signal. This bit reflect the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 2 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 420 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH2_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.28 AHB to APBH DMA Channel 2 Debug Information (HW_APBH_CH2_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 2. This register allows debug visibility of the APBH DMA Channel 2. Address: 8000_4000h base + 240h offset = 8000_4240h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH2_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 421 Programmable Registers 6.5.29 APBH DMA Channel 3 Current Command Address Register (HW_APBH_CH3_CURCMDAR) The APBH DMA Channel 3 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 3 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 250h offset = 8000_4250h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH3_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 3. 6.5.30 APBH DMA Channel 3 Next Command Address Register (HW_APBH_CH3_NXTCMDAR) The APBH DMA Channel 3 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA Channel 3 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 3 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 260h offset = 8000_4260h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH3_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 3. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 422 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.31 APBH DMA Channel 3 Command Register (HW_APBH_CH3_CMD) The APBH DMA Channel 3 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 270h offset = 8000_4270h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 423 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH3_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SSP3 device. A value of 0 indicates a 64 KBytes trasnfer size. This field indicates the number of command words to send to the SSP3, starting with the base PIO address of the SSP3 control register and incrementing from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 424 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH3_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH1_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from the SSP3 (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.32 APBH DMA Channel 3 Buffer Address Register (HW_APBH_CH3_BAR) The APBH DMA Channel 3 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 280h offset = 8000_4280h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH3_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 425 Programmable Registers 6.5.33 APBH DMA Channel 3 Semaphore Register (HW_APBH_CH3_SEMA) The APBH DMA Channel 3 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 290h offset = 8000_4290h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH3_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.34 AHB to APBH DMA Channel 3 Debug Information (HW_APBH_CH3_DEBUG1) This register gives debug visibility into the APBH DMA Channel 3 state machine and controls. This register allows debug visibility of the APBH DMA Channel 3. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 426 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 2A0h offset = 8000_42A0h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH3_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 427 Programmable Registers HW_APBH_CH3_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit is reserved for this DMA Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit is reserved for this DMA Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit is reserved for this Channel and always reads 0. For Channels 4-11, this bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID This bit reflect the internal bit which indicates whether the channel's next command address is valid. 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflect the current state of the DMA Channel's Read FIFO Empty signal. This bit reflect the current state of the DMA Channel's Read FIFO Full signal. This bit reflect the current state of the DMA Channel's Write FIFO Empty signal. This bit reflect the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 3 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 428 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH3_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.35 AHB to APBH DMA Channel 3 Debug Information (HW_APBH_CH3_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 3. This register allows debug visibility of the APBH DMA Channel 3. Address: 8000_4000h base + 2B0h offset = 8000_42B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH3_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 429 Programmable Registers 6.5.36 APBH DMA Channel 4 Current Command Address Register (HW_APBH_CH4_CURCMDAR) The APBH DMA Channel 4 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 4 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 2C0h offset = 8000_42C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH4_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 4. 6.5.37 APBH DMA Channel 4 Next Command Address Register (HW_APBH_CH4_NXTCMDAR) The APBH DMA Channel 4 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA Channel 4 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 4 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 2D0h offset = 8000_42D0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH4_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 4. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 430 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.38 APBH DMA Channel 4 Command Register (HW_APBH_CH4_CMD) The APBH DMA Channel 4 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 2E0h offset = 8000_42E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 431 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH4_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI0 device. A value of 0 indicates a 64 KBytes trasnfer size. This field indicates the number of command words to send to the GPMI0, starting with the base PIO address of the GPMI0 control register and incrementing from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 432 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH4_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH1_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from the NAND0(APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.39 APBH DMA Channel 4 Buffer Address Register (HW_APBH_CH4_BAR) The APBH DMA Channel 1 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 2F0h offset = 8000_42F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH4_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 433 Programmable Registers 6.5.40 APBH DMA Channel 4 Semaphore Register (HW_APBH_CH4_SEMA) The APBH DMA Channel 4 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE BF_WR(APBH_CHn_SEMA, 0, INCREMENT_SEMA, 2); current_sema = BF_RD(APBH_CHn_SEMA, 0, PHORE); // increment semaphore by two // get instantaneous value Address: 8000_4000h base + 300h offset = 8000_4300h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH4_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.41 AHB to APBH DMA Channel 4 Debug Information (HW_APBH_CH4_DEBUG1) This register gives debug visibility into the APBH DMA Channel 4 state machine and controls. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 434 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) This register allows debug visibility of the APBH DMA Channel 4. Address: 8000_4000h base + 310h offset = 8000_4310h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 435 Programmable Registers HW_APBH_CH4_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 4 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 436 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH4_DEBUG1 field descriptions (continued) Field Description 0x0E CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.42 AHB to APBH DMA Channel 4 Debug Information (HW_APBH_CH4_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 4. This register allows debug visibility of the APBH DMA Channel 4. Address: 8000_4000h base + 320h offset = 8000_4320h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH4_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 437 Programmable Registers 6.5.43 APBH DMA Channel 5 Current Command Address Register (HW_APBH_CH5_CURCMDAR) The APBH DMA Channel 5 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 5 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 330h offset = 8000_4330h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH5_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 5. 6.5.44 APBH DMA Channel 5 Next Command Address Register (HW_APBH_CH5_NXTCMDAR) The APBH DMA Channel 5 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA Channel 5 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 5 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 340h offset = 8000_4340h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH5_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 5. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 438 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.45 APBH DMA Channel 5 Command Register (HW_APBH_CH5_CMD) The APBH DMA Channel 5 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 350h offset = 8000_4350h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 439 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH5_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI1 device. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the GPMI1, starting with the base PIO address of the GPMI1 control register and incrementing from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 440 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH5_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH0_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from the NAND1 (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.46 APBH DMA Channel 5 Buffer Address Register (HW_APBH_CH5_BAR) The APBH DMA Channel 5 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 360h offset = 8000_4360h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH5_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 441 Programmable Registers 6.5.47 APBH DMA Channel 5 Semaphore Register (HW_APBH_CH5_SEMA) The APBH DMA Channel 5 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 370h offset = 8000_4370h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH5_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.48 AHB to APBH DMA Channel 5 Debug Information (HW_APBH_CH5_DEBUG1) This register gives debug visibility into the APBH DMA Channel 5 state machine and controls. This register allows debug visibility of the APBH DMA Channel 5. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 442 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 380h offset = 8000_4380h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH5_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 443 Programmable Registers HW_APBH_CH5_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 5 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 444 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH5_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.49 AHB to APBH DMA Channel 5 Debug Information (HW_APBH_CH5_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 5. This register allows debug visibility of the APBH DMA Channel 5. Address: 8000_4000h base + 390h offset = 8000_4390h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH5_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 445 Programmable Registers 6.5.50 APBH DMA Channel 6 Current Command Address Register (HW_APBH_CH6_CURCMDAR) The APBH DMA Channel 6 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 6 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 3A0h offset = 8000_43A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH6_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 6. 6.5.51 APBH DMA Channel 6 Next Command Address Register (HW_APBH_CH6_NXTCMDAR) The APBH DMA Channel 6 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA Channel 6 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 6 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 3B0h offset = 8000_43B0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH6_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 6. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 446 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.52 APBH DMA Channel 6 Command Register (HW_APBH_CH6_CMD) The APBH DMA Channel 6 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 3C0h offset = 8000_43C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 447 11 CMDWORDS R 10 9 RSVD1 8 7 6 0 0 0 5 4 RSVD0 3 2 CHAIN 12 IRQONCMPLT 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH6_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI2 device. A value of 0 indicates a 64 Kbytes transfer. This field indicates the number of command words to send to the GPMI2 starting with the base PIO address of the GPMI2 and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, that is, after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH3_CMDAR to find the next command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 448 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH6_CMD field descriptions (continued) Field Description COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, that is, data sent from NAND2(APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.53 APBH DMA Channel 6 Buffer Address Register (HW_APBH_CH6_BAR) The APBH DMA Channel 6 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 3D0h offset = 8000_43D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH6_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 449 Programmable Registers 6.5.54 APBH DMA Channel 6 Semaphore Register (HW_APBH_CH6_SEMA) The APBH DMA Channel 6 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 3E0h offset = 8000_43E0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH6_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.55 AHB to APBH DMA Channel 6 Debug Information (HW_APBH_CH6_DEBUG1) This register gives debug visibility into the APBH DMA Channel 6 state machine and controls. This register allows debug visibility of the APBH DMA Channel 6. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 450 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 3F0h offset = 8000_43F0h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH6_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 451 Programmable Registers HW_APBH_CH6_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 6 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 452 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH6_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.56 AHB to APBH DMA Channel 6 Debug Information (HW_APBH_CH6_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 6. This register allows debug visibility of the APBH DMA Channel 6. Address: 8000_4000h base + 400h offset = 8000_4400h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH6_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 453 Programmable Registers 6.5.57 APBH DMA Channel 7 Current Command Address Register (HW_APBH_CH7_CURCMDAR) The APBH DMA Channel 7 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 7 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 410h offset = 8000_4410h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH7_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 7. 6.5.58 APBH DMA Channel 7 Next Command Address Register (HW_APBH_CH7_NXTCMDAR) The APBH DMA Channel 7 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA Channel 7 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 7 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 420h offset = 8000_4420h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH7_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 7. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 454 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.59 APBH DMA Channel 7 Command Register (HW_APBH_CH7_CMD) The APBH DMA Channel 7 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 430h offset = 8000_4430h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 455 11 CMDWORDS R 10 9 RSVD1 8 7 6 0 0 0 5 4 RSVD0 3 2 CHAIN 12 IRQONCMPLT 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH7_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI3 device. A value of 0 indicates a 64 Kbytes transfer. This field indicates the number of command words to send to the GPMI3, starting with the base PIO address of the GPMI3 and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH3_CMDAR to find the next command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 456 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH7_CMD field descriptions (continued) Field Description COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, that is, data sent from NAND3 (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.60 APBH DMA Channel 7 Buffer Address Register (HW_APBH_CH7_BAR) The APBH DMA Channel 7 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 440h offset = 8000_4440h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH7_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 457 Programmable Registers 6.5.61 APBH DMA Channel 7 Semaphore Register (HW_APBH_CH7_SEMA) The APBH DMA Channel 7 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 450h offset = 8000_4450h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH7_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.62 AHB to APBH DMA Channel 7 Debug Information (HW_APBH_CH7_DEBUG1) This register gives debug visibility into the APBH DMA Channel 7 state machine and controls. This register allows debug visibility of the APBH DMA Channel 7. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 458 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 460h offset = 8000_4460h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH7_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 459 Programmable Registers HW_APBH_CH7_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 7 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 460 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH7_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.63 AHB to APBH DMA Channel 7 Debug Information (HW_APBH_CH7_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 7. This register allows debug visibility of the APBH DMA Channel 7. Address: 8000_4000h base + 470h offset = 8000_4470h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH7_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 461 Programmable Registers 6.5.64 APBH DMA Channel 8 Current Command Address Register (HW_APBH_CH8_CURCMDAR) The APBH DMA Channel 8 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 8 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 480h offset = 8000_4480h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH8_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 8. 6.5.65 APBH DMA Channel 8 Next Command Address Register (HW_APBH_CH8_NXTCMDAR) The APBH DMA Channel 8 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA Channel 8 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 8 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 490h offset = 8000_4490h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH8_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 8. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 462 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.66 APBH DMA Channel 8 Command Register (HW_APBH_CH8_CMD) The APBH DMA Channel 8 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 4A0h offset = 8000_44A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 463 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH8_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI4 device HW_GPMI_DATA register. A value of 0 indicates a 64 Kbytes transfer. This field indicates the number of command words to send to the GPMI4, starting with the base PIO address of the GPMI4 (HW_GPMI_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 464 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH8_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH7_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from NAND4 (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.67 APBH DMA Channel 8 Buffer Address Register (HW_APBH_CH8_BAR) The APBH DMA Channel 8 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 4B0h offset = 8000_44B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH8_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 465 Programmable Registers 6.5.68 APBH DMA Channel 8 Semaphore Register (HW_APBH_CH8_SEMA) The APBH DMA Channel 8 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 4C0h offset = 8000_44C0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH8_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.69 AHB to APBH DMA Channel 8 Debug Information (HW_APBH_CH8_DEBUG1) This register gives debug visibility into the APBH DMA Channel 8 state machine and controls. This register allows debug visibility of the APBH DMA Channel 7. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 466 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 4D0h offset = 8000_44D0h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH8_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 467 Programmable Registers HW_APBH_CH8_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 7 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 468 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH8_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.70 AHB to APBH DMA Channel 8 Debug Information (HW_APBH_CH8_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 8. This register allows debug visibility of the APBH DMA Channel 8. Address: 8000_4000h base + 4E0h offset = 8000_44E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH8_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 469 Programmable Registers 6.5.71 APBH DMA Channel 9 Current Command Address Register (HW_APBH_CH9_CURCMDAR) The APBH DMA Channel 9 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 9 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 4F0h offset = 8000_44F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH9_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for Channel 9. 6.5.72 APBH DMA Channel 9 Next Command Address Register (HW_APBH_CH9_NXTCMDAR) The APBH DMA Channel 9 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA Channel 9 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 9 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 500h offset = 8000_4500h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH9_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for Channel 9. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 470 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.73 APBH DMA Channel 9 Command Register (HW_APBH_CH9_CMD) The APBH DMA Channel 9 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 510h offset = 8000_4510h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 471 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH9_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI5 device HW_GPMI_DATA register. A value of 0 indicates a 64 Kbytes transfer. This field indicates the number of command words to send to the GPMI5, starting with the base PIO address of the GPMI5 (HW_GPMI_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 472 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH9_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH9_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from NAND5 (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.74 APBH DMA Channel 9 Buffer Address Register (HW_APBH_CH9_BAR) The APBH DMA Channel 9 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 520h offset = 8000_4520h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH9_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 473 Programmable Registers 6.5.75 APBH DMA Channel 9 Semaphore Register (HW_APBH_CH9_SEMA) The APBH DMA Channel 9 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 530h offset = 8000_4530h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH9_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.76 AHB to APBH DMA Channel 9 Debug Information (HW_APBH_CH9_DEBUG1) This register gives debug visibility into the APBH DMA Channel 9 state machine and controls. This register allows debug visibility of the APBH DMA Channel 9. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 474 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 540h offset = 8000_4540h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH9_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 475 Programmable Registers HW_APBH_CH9_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 9 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 476 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH9_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.77 AHB to APBH DMA Channel 9 Debug Information (HW_APBH_CH9_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 9. This register allows debug visibility of the APBH DMA Channel 9. Address: 8000_4000h base + 550h offset = 8000_4550h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH9_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 477 Programmable Registers 6.5.78 APBH DMA channel 10 Current Command Address Register (HW_APBH_CH10_CURCMDAR) The APBH DMA channel 10 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA channel 10 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 560h offset = 8000_4560h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH10_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 10. 6.5.79 APBH DMA channel 10 Next Command Address Register (HW_APBH_CH10_NXTCMDAR) The APBH DMA channel 10 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA channel 10 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the channel 10 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 570h offset = 8000_4570h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH10_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 10. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 478 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.80 APBH DMA channel 10 Command Register (HW_APBH_CH10_CMD) The APBH DMA channel 10 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 580h offset = 8000_4580h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 479 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH10_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI6 device HW_GPMI_DATA register. A value of 0 indicates a 64 Kbytes transfer. This field indicates the number of command words to send to the GPMI6, starting with the base PIO address of the GPMI6 (HW_GPMI_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 480 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH10_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH10_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from NAND6 (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.81 APBH DMA channel 10 Buffer Address Register (HW_APBH_CH10_BAR) The APBH DMA channel 10 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 590h offset = 8000_4590h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH10_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 481 Programmable Registers 6.5.82 APBH DMA channel 10 Semaphore Register (HW_APBH_CH10_SEMA) The APBH DMA channel 10 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 5A0h offset = 8000_45A0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH10_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.83 AHB to APBH DMA channel 10 Debug Information (HW_APBH_CH10_DEBUG1) This register gives debug visibility into the APBH DMA channel 10 state machine and controls. This register allows debug visibility of the APBH DMA channel 10. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 482 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 5B0h offset = 8000_45B0h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH10_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 483 Programmable Registers HW_APBH_CH10_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA channel 10 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 484 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH10_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.84 AHB to APBH DMA channel 10 Debug Information (HW_APBH_CH10_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA channel 10. This register allows debug visibility of the APBH DMA channel 10. Address: 8000_4000h base + 5C0h offset = 8000_45C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH10_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 485 Programmable Registers 6.5.85 APBH DMA Channel 11 Current Command Address Register (HW_APBH_CH11_CURCMDAR) The APBH DMA Channel 11 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 11 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 5D0h offset = 8000_45D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH11_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for Channel 11. 6.5.86 APBH DMA Channel 11 Next Command Address Register (HW_APBH_CH11_NXTCMDAR) The APBH DMA Channel 11 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA Channel 11 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 11 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 5E0h offset = 8000_45E0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH11_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for Channel 11. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 486 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.87 APBH DMA Channel 11 Command Register (HW_APBH_CH11_CMD) The APBH DMA Channel 11 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 5F0h offset = 8000_45F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 487 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH11_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the GPMI7 device HW_GPMI_DATA register. A value of 0 indicates a 64 Kbytes transfer. This field indicates the number of command words to send to the GPMI7, starting with the base PIO address of the GPMI7 (HW_GPMI_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 488 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH11_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH11_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from NAND7 (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.88 APBH DMA Channel 11 Buffer Address Register (HW_APBH_CH11_BAR) The APBH DMA Channel 11 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 600h offset = 8000_4600h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH11_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 489 Programmable Registers 6.5.89 APBH DMA Channel 11 Semaphore Register (HW_APBH_CH11_SEMA) The APBH DMA Channel 11 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 610h offset = 8000_4610h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH11_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.90 AHB to APBH DMA Channel 11 Debug Information (HW_APBH_CH11_DEBUG1) This register gives debug visibility into the APBH DMA Channel 11 state machine and controls. This register allows debug visibility of the APBH DMA Channel 11. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 490 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 620h offset = 8000_4620h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH11_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 491 Programmable Registers HW_APBH_CH11_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 11 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 492 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH11_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.91 AHB to APBH DMA Channel 11 Debug Information (HW_APBH_CH11_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 11. This register allows debug visibility of the APBH DMA Channel 11. Address: 8000_4000h base + 630h offset = 8000_4630h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH11_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 493 Programmable Registers 6.5.92 APBH DMA channel 12 Current Command Address Register (HW_APBH_CH12_CURCMDAR) The APBH DMA channel 12 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA channel 12 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 640h offset = 8000_4640h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH12_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 12. 6.5.93 APBH DMA channel 12 Next Command Address Register (HW_APBH_CH12_NXTCMDAR) The APBH DMA channel 12 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA channel 12 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the channel 12 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 650h offset = 8000_4650h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH12_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 12. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 494 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.94 APBH DMA channel 12 Command Register (HW_APBH_CH12_CMD) The APBH DMA channel 12 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 660h offset = 8000_4660h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 495 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH12_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the HSADC device HW_HSADC_FIFO_DATA register. A value of 0 indicates a 64 Kbytes transfer. This field indicates the number of command words to send to the HSADC, starting with the base PIO address of the HSADC (HW_HSADC_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels.. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 496 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH12_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH12_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from HSADC (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.95 APBH DMA channel 12 Buffer Address Register (HW_APBH_CH12_BAR) The APBH DMA channel 12 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 670h offset = 8000_4670h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH12_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 497 Programmable Registers 6.5.96 APBH DMA channel 12 Semaphore Register (HW_APBH_CH12_SEMA) The APBH DMA channel 12 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 680h offset = 8000_4680h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH12_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.97 AHB to APBH DMA channel 12 Debug Information (HW_APBH_CH12_DEBUG1) This register gives debug visibility into the APBH DMA channel 12 state machine and controls. This register allows debug visibility of the APBH DMA channel 12. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 498 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 690h offset = 8000_4690h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH12_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 499 Programmable Registers HW_APBH_CH12_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA channel 12 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 500 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH12_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.98 AHB to APBH DMA channel 12 Debug Information (HW_APBH_CH12_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA channel 12. This register allows debug visibility of the APBH DMA channel 12. Address: 8000_4000h base + 6A0h offset = 8000_46A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH12_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 501 Programmable Registers 6.5.99 APBH DMA Channel 13 Current Command Address Register (HW_APBH_CH13_CURCMDAR) The APBH DMA Channel 13 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBH DMA Channel 13 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8000_4000h base + 6B0h offset = 8000_46B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH13_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for Channel 13. 6.5.100 APBH DMA Channel 13 Next Command Address Register (HW_APBH_CH13_NXTCMDAR) The APBH DMA Channel 13 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBH DMA Channel 13 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 13 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8000_4000h base + 6C0h offset = 8000_46C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH13_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for Channel 13. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 502 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.101 APBH DMA Channel 13 Command Register (HW_APBH_CH13_CMD) The APBH DMA Channel 13 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8000_4000h base + 6D0h offset = 8000_46D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 503 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH13_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the LCDIF device HW_LCDIF_DATA register. A value of 0 indicates a 64 Kbytes transfer. This field indicates the number of command words to send to the LCDIF, starting with the base PIO address of the LCDIF (HW_LCDIF_CTRL) and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 504 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH13_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH13_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from LCDIF (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.102 APBH DMA Channel 13 Buffer Address Register (HW_APBH_CH13_BAR) The APBH DMA Channel 13 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8000_4000h base + 6E0h offset = 8000_46E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH13_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 505 Programmable Registers 6.5.103 APBH DMA Channel 13 Semaphore Register (HW_APBH_CH13_SEMA) The APBH DMA Channel 13 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8000_4000h base + 6F0h offset = 8000_46F0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH13_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.104 AHB to APBH DMA Channel 13 Debug Information (HW_APBH_CH13_DEBUG1) This register gives debug visibility into the APBH DMA Channel 13 state machine and controls. This register allows debug visibility of the APBH DMA Channel 13. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 506 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 700h offset = 8000_4700h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH13_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 507 Programmable Registers HW_APBH_CH13_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the GPMI Sense Signal sent from the APB GPMI Device 26 READY This bit reflects the current state of the GPMI Ready Signal sent from the APB GPMI Device 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 13 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 508 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH13_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.105 AHB to APBH DMA Channel 13 Debug Information (HW_APBH_CH13_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 13. This register allows debug visibility of the APBH DMA Channel 13. Address: 8000_4000h base + 710h offset = 8000_4710h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH13_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 509 Programmable Registers 6.5.106 APBH DMA channel 14 Current Command Address Register (HW_APBH_CH14_CURCMDAR) The APBH DMA channel 14 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. Because channel 14 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 720h offset = 8000_4720h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH14_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 14. 6.5.107 APBH DMA channel 14 Next Command Address Register (HW_APBH_CH14_NXTCMDAR) The APBH DMA channel 14 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. Because channel 14 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 730h offset = 8000_4730h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH14_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 14. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 510 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.108 APBH DMA channel 14 Command Register (HW_APBH_CH14_CMD) The APBH DMA channel 14 command register specifies the cycle to perform for the current command chain item. Because channel 14 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 740h offset = 8000_4740h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 511 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH14_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in assigned peripheral. A value of 0 indicates a 64 Kbytes transfer. This field indicates the number of command words to send to assigned peripheral, starting with the base PIO address of assigned peripheral and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 512 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH14_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH14_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, that is, data sent from assigned peripheral (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.109 APBH DMA channel 14 Buffer Address Register (HW_APBH_CH14_BAR) The APBH DMA channel 14 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. Because channel 14 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 750h offset = 8000_4750h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH14_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 513 Programmable Registers 6.5.110 APBH DMA channel 14 Semaphore Register (HW_APBH_CH14_SEMA) The APBH DMA channel 14 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Because channel 14 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 760h offset = 8000_4760h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH14_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.111 AHB to APBH DMA channel 14 Debug Information (HW_APBH_CH14_DEBUG1) This register gives debug visibility into the APBH DMA channel 14 state machine and controls. Because channel 14 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 514 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 770h offset = 8000_4770h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH14_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 515 Programmable Registers HW_APBH_CH14_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of the Sense Signal sent from assigned peripheral 26 READY This bit reflects the current state of the Ready Signal sent from assigned peripheral 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA channel 14 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 516 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH14_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.112 AHB to APBH DMA channel 14 Debug Information (HW_APBH_CH14_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA channel 14. Because channel 14 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 780h offset = 8000_4780h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH14_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 517 Programmable Registers 6.5.113 APBH DMA channel 15 Current Command Address Register (HW_APBH_CH15_CURCMDAR) The APBH DMA channel 15 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. Because channel 15 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 790h offset = 8000_4790h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH15_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 15. 6.5.114 APBH DMA channel 15 Next Command Address Register (HW_APBH_CH15_NXTCMDAR) The APBH DMA channel 15 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. Because channel 15 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 7A0h offset = 8000_47A0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH15_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 15. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 518 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) 6.5.115 APBH DMA channel 15 Command Register (HW_APBH_CH15_CMD) The APBH DMA channel 15 command register specifies the cycle to perform for the current command chain item. Because channel 15 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 7B0h offset = 8000_47B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 519 9 RSVD1 8 7 6 5 4 3 2 CHAIN CMDWORDS R 10 IRQONCMPLT 11 NANDLOCK 12 NANDWAIT4READY 13 SEMAPHORE 14 WAIT4ENDCMD 15 Bit HALTONTERMINATE Programmable Registers 0 0 0 0 0 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 HW_APBH_CH15_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-9 RSVD1 8 HALTONTERMINATE 7 WAIT4ENDCMD 6 SEMAPHORE Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in assigned peripheral. A value of 0 indicates a 64 Kbytes transfer. This field indicates the number of command words to send to assigned peripheral, starting with the base PIO address of assigned peripheral and increment from there. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel immediately terminates the current descriptor and halts the DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the channel if the terminate signal is set, but the channel continues as if the count had been exhausted, meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. A value of one indicates that the channel waits for the end of command signal to be sent from the APBH device to the DMA before starting the next DMA command. A value of one indicates that the channel decrements its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. 5 NANDWAIT4READY A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\' before executing the command. It is ignored for non-NAND DMA channels. 4 NANDLOCK A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of other NAND DMA channels. It is ignored for non-NAND DMA channels. 3 IRQONCMPLT A value of one indicates that the channel will cause the interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 520 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH15_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBH_CH15_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- Write transfers, i.e. data sent from assigned peripheral (APB PIO Read) to the system memory (AHB master write). 10- Read transfer 11- SENSE 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x3 DMA_SENSE -- Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is false. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is true. 6.5.116 APBH DMA channel 15 Buffer Address Register (HW_APBH_CH15_BAR) The APBH DMA channel 15 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. Because channel 15 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 7C0h offset = 8000_47C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH15_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 521 Programmable Registers 6.5.117 APBH DMA channel 15 Semaphore Register (HW_APBH_CH15_SEMA) The APBH DMA channel 15 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Because channel 15 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 7D0h offset = 8000_47D0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH15_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 6.5.118 AHB to APBH DMA channel 15 Debug Information (HW_APBH_CH15_DEBUG1) This register gives debug visibility into the APBH DMA channel 15 state machine and controls. Because channel 15 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 522 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) Address: 8000_4000h base + 7E0h offset = 8000_47E0h 20 19 18 17 16 WR_FIFO_FULL 21 WR_FIFO_EMPTY 22 RD_FIFO_FULL 23 RD_FIFO_EMPTY 24 NEXTCMDADDRVALID 25 LOCK 26 READY 27 SENSE 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH15_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 523 Programmable Registers HW_APBH_CH15_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27 SENSE This bit reflects the current state of Sense Signal sent from assigned peripheral 26 READY This bit reflects the current state of Ready Signal sent from assigned peripheral 25 LOCK This bit reflects the current state of the DMA Channel Lock for a GPMI Channel. 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA channel 15 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 524 Freescale Semiconductor, Inc. Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA) HW_APBH_CH15_DEBUG1 field descriptions (continued) Field Description 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x14 TERMINATE -- When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1D HALT_AFTER_TERM -- If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 0x1F WAIT_READY -- When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready. 6.5.119 AHB to APBH DMA channel 15 Debug Information (HW_APBH_CH15_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA channel 15. Because channel 15 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8000_4000h base + 7F0h offset = 8000_47F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBH_CH15_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 6.5.120 APBH Bridge Version Register (HW_APBH_VERSION) This register always returns a known read value for debug purposes it indicates the version of the block. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 525 Programmable Registers EXAMPLE if (HW_APBH_VERSION.B.MAJOR != 3) Error(); Address: 8000_4000h base + 800h offset = 8000_4800h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 HW_APBH_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 526 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 7.1 AHB-to-APBX Bridge Overview The AHB-to-APBX bridge provides the device with an inexpensive peripheral attachment bus running on the AHB's XCLK. (The X in APBX denotes that the APBX runs on a crystal-derived clock, as compared to APBH, which is synchronous to HCLK.) As shown in the following figure, the AHB-to-APBX bridge includes the AHB-to-APB PIO bridge for a memory-mapped I/O to the APB devices, as well a central DMA facility for devices on this bus. Each one of the APB peripherals is documented in their own chapters elsewhere in this document. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 527 AHB-to-APBX Bridge Overview AHB AHB Slave AHB Master AHB-to-APBX DMA APBX MASTER AHB-to-APBX Bridge AUART3 RX I2C0 AUART3 TX I2C1 SPDIF Transmit SAIF1 APBX AUART0 RX AUART0 TX AUART1 RX SAIF2 AUART1 TX SAIF1 AUART2 RX SAIF2 AUART2 TX Figure 7-1. AHB-to-APBX Bridge DMA Block Diagram The DMA controller uses the APBX bus to transfer read and write data to and from each peripheral. There is no separate DMA bus for these devices. Contention between the DMA's use of the APBX bus and AHB-to-APB bridge functions' use of the APBX is i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 528 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) mediated by an internal arbitration logic. For contention between these two units, the DMA is favored and the AHB slave will report not ready through its HREADY output until the bridge transfer completes. The arbiter tracks repeated lockouts and inverts the priority, so that the CPU is guaranteed every fourth transfer on the APB. 7.2 APBX DMA The DMA supports sixteen channels of DMA services, as shown in the following table. The shared DMA resource allows each independent channel to follow a simple chained command list. Command chains are built up using the DMA command structure, as shown in Figure 7-2. Table 7-1. APBX DMA Channel Assignments APBX DMA Channel # USAGE 0 AUART4 RX 1 AUART4 TX 2 SPDIF TX 3 EMPTY 4 SAIF0 5 SAIF1 6 I2C0 7 I2C1 8 AUART0 RX 9 AUART0 TX 10 AUART1 RX 11 AUART1 TX 12 AUART2 RX 13 AUART2 TX 14 AUART3 RX 15 AUART3 TX A single command structure or channel command word specifies a number of operations to be performed by the DMA in support of a given device. Thus, the CPU can set up large units of work, chaining together many DMA channel command words, pass them off to the DMA and have no further concern for the device until the DMA completion interrupt occurs. The i.MX28 is designed to have enough intelligence in the DMA and the devices to keep the interrupt frequency from any device below 1 KHz (arrival intervals longer than 1 ms). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 529 APBX DMA Thus, a single command structure can issue 32-bit PIO write operations to key registers in the associated device using the same APB bus and the controls, it uses to write DMA data bytes to the device. For example, this allows a chain of operations to be issued to the serial audio interface to send command bytes, address bytes, and data transfers, where the command and the address structure is completely under software control, but the administration of that transfer is handled autonomously by the DMA. Each DMA structure can have from 0 to 15 PIO words appended to it. The #PIOWORDs field, if non-zero, instructs the DMA engine to copy these words to the APB, beginning at PADDR = 0x0000 and incrementing its PADDR for each cycle. (Note that for APBX DMA Channel 8, which is the UART RX channel, the first PIO word in the DMA command is CTRL0. However, for APBX DMA Channel 9, which is the UART TX, the first PIO word in a DMA command is CTRL1.) The DMA master generates only normal read/write transfers to the APBX. It does not generate set, clear, or toggle SCT transfers. word 2 word 3-n COMMAND IRQONCMPLT CHAIN WAIT4ENDCMD SEMAPHORE XFER_COUNT TERMINATEFLUSH HALTONTERMINATE word 1 NEXTCMDADDR CMDWORDS word 0 BUFFER ADDRESS PIOWORD Value Figure 7-2. AHB-to-APBX Bridge DMA Channel Command Structure After any requested PIO words have been transferred to the peripheral, the DMA examines the two-bit command field in the channel command structure. The following table shows the four commands implemented by the DMA. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 530 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Table 7-2. APBX DMA Commands DMA COMMAND Usage 00 NO_DMA_XFER. Perform any requested PIO word transfers, but terminate the command before any DMA transfer. 01 DMA_WRITE. Perform any requested PIO word transfers, and then perform a DMA transfer from the peripheral for the specified number of bytes. 10 DMA_READ. Perform any requested PIO word transfers, and then perform a DMA transfer to the peripheral for the specified number of bytes. 11 Reserved DMA_WRITE operations copy data bytes to the system memory (on-chip RAM or SDRAM) from the associated peripheral. Each peripheral has a target PADDR value that it expects to receive DMA bytes. This association is synthesized in the DMA. The DMA_WRITE transfer uses the BUFFER_ADDRESS word in the command structure to point to the beginning byte to write data from the peripheral. DMA_READ operations copy data bytes to the APB peripheral from the system memory. The DMA engine contains a shared byte aligner that aligns bytes from system memory to or from the peripherals. Peripherals always assume little-endian-aligned data arrives or departs on their 32-bit APB. The DMA_READ transfer uses the BUFFER_ADDRESS word in the command structure to point to the DMA data buffer to be read by the DMA_READ command. The NO_DMA_XFER command is used to write PIO words to a device without performing any DMA data byte transfers. As each DMA command completes, it triggers the DMA to load the next DMA command structure in the chain. The normal flow list of DMA commands is found by following the NEXTCMD_ADDR pointer in the DMA command structure. If the wait-for-endcommand bit (WAIT4ENDCMD) is set in a command structure, then the DMA channel waits for the device to signal completion of a command by toggling the apx_endcmcd signal before proceeding to load and execute the next command structure. Then, if DECREMENT_SEMAPHORE is set, the semaphore is decremented after the end command is seen. A detailed bit-field view of the DMA command structure is shown in the following table, which shows a field that specifies the number of bytes to be transferred by this DMA command. The transfer count mechanism is duplicated in the associated peripheral, either as an implied or as a specified count in the peripheral. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 531 APBX DMA 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 CHAIN 2 7 IRQ_FINISH 2 8 DECREMENT SEMAPHORE 2 9 WAIT4ENDCMD 3 0 HALTONTERMINATE 3 1 TERMINATEFLUSH Table 7-3. DMA Channel Command Word in System Memory 0 1 0 0 Number PIO Words to Write COMMAND Number DMA Bytes to Transfer Reserved NEXT_COMMAND_ADDRESS DMA Buffer or Alternate CCW Zero or More PIO Words to Write to the Associated Peripheral Starting at its Base Address on the APBX Bus Figure 7-3 shows the CHAIN bit in bit 2 of the second word of the command structure. This bit is set to 1, if the NEXT_COMMAND_ADDRESS contains a pointer to another DMA command structure. If a null pointer (0) is loaded into the NEXT_COMMAND_ADDRESS, it will not be detected by the DMA hardware. Only the CHAIN bit indicates whether a valid list exists beyond the current structure. If the IRQ_COMPLETE bit is set in the command structure, then the last act of the DMA before loading the next command is to set the interrupt status bit corresponding to the current channel. The sticky interrupt request bit in the DMA CSR remains set until cleared by the software. It can be used to interrupt the CPU. Each channel has an eight-bit counting semaphore that controls whether it is in the run or idle state. When the semaphore is non-zero, the channel is ready to run and process commands and DMA transfers. Whenever a command finishes its DMA transfer, it checks the DECREMENT_SEMAPHORE bit. If set, it decrements the counting semaphore. If the semaphore goes to 0 as a result, then the channel enters the IDLE state and remains there until the semaphore is incremented by software. When the semaphore goes to non-zero and the channel is in its IDLE state, then it uses the value in the HW_APBX_CHn_NXTCMDAR (next command address register) to fetch a pointer to the next command to process. NOTE: this is a double indirect case. This method allows software to append to a running command list under the protection of the counting semaphore. Receiving an IRQ for HALTONTERMINATE (HOT) is a new feature in the APBH/X DMA descriptor that allows certain peripheral block (for example, GPMI, SSP, I2C) to signal to the DMA engine that an error has occurred. In prior chips, if a block stalled due to an error, the only practical way to discover this in software was through a timer of i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 532 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) some sort, or to poll the block. Now, an HOT signal is sent from the peripheral to the DMA engine and causes an IRQ after terminating the DMA descriptor being executed. Note not all peripheral block support this termination feature. Under a normal operation mode, when termination occurs, DMA would stop the current descriptor and discard any data remaining in the FIFO. By setting TERMINATEFLUSH bit in the descriptor command word, DMA will flush out all the remainder data in the FIFO to system memory for write DMA operation before issue HOT IRQ. Therefore, it is recommended that software use this signal as follows: * Always set HALTONTERMINATE to 1 in a DMA descriptor. That way, if a peripheral signals HOT, the transfer will end, leaving the peripheral block and the DMA engine synchronized (but at the end of a command). * When an IRQ from an APBH/X channel is received, and the IRQ is determined to be due to an error (as opposed to an IRQONCOMPLETE interrupt) the software should: 1. Reset the channel. 2. Determine the error from error reporting in the peripheral block, then manage the error in the peripheral that is attached to that channel in whatever appropriate way exists for that device (software recovery, device reset, block reset, and so on). To start processing the first time, software creates the command list to be processed. It writes the address of the first command into the HW_APBX_CHn_NXTCMDAR register, and then writes a 1 to the counting semaphore in HW_APBX_CHn_SEMA. The DMA channel loads HW_APBX_CHn_CURCMDAR register and then enters the normal state machine processing for the next command. When the software writes a value to the counting semaphore, it is added to the semaphore count by hardware, protecting the case where both hardware and software are trying to change the semaphore on the same clock edge. Software can examine the value of HW_APBX_CHn_CURCMDAR at any time to determine the location of the command structure that is currently being processed. 7.3 DMA Chain Example The example in the following figure shows how to bring the basic items together to make a simple DMA chain to read PCM samples and send them out the Audio Output (DAC) using one DMA channel. This example shows three command structures linked together using their normal command list pointers. The first command writes a single PIO word to the HW_AUDIOOUT_CTRL0 register with a new word count for the DAC. This first i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 533 DMA Chain Example command also performs a 512 byte DMA_READ operation to read the data block bytes into the DAC. A second and a third DMA command structure also performs a DMA_READ operation to handle circular buffer style outputs. The completion of each command structure generates an interrupt request. In addition, each command structure decrements the semaphore. If the decompression software has not provided a buffer in a timely fashion, then the DMA will stall. Without the decrement semaphore interlocking, then the DMA will continue to output a stream of samples. In this mode, it is up to software to use the interrupts to synchronize outputs so that underruns do not occur. 1 PIO, IRQ, DecSema chaining, DMA read 1 PIO,IRQ, DecSema, chaining, DMA read NEXTCMD_ADDR NEXTCMD_ADDR 512=0x200 512=0x200 0x104E BUFFER ADDRESS BUFFER ADDRESS HW_AUDIOOUT_CTRL0 0x104E 1 PIO, IRQ, DecSema, chaining, DMA read HW_AUDIOOUT_CTRL0 NEXTCMD_ADDR 512=0x200 512-Byte Data Block (64 PCM stereo samples) (1.33 ms @ 48 kHz) 0x104E BUFFER ADDRESS HW_AUDIOOUT_CTRL0 512-Byte Data Block (64 PCM stereo samples) (1.33 ms @ 48 kHz) 512-Byte Data Block (64 PCM stereo samples) (1.33 ms @ 48 kHz) Pointer to next ccw Pointer to DMA buffer Figure 7-3. AHB-to-APBX Bridge DMA AUDIOOUT (DAC) Example Command Chain Note that each word of the three-word DMA command structure corresponds to a PIO register of the DMA that is accessible on the APBX bus. Normally, the DMA copies the next command structure onto these registers for processing at the start of each command by following the value of the pointer previously loaded into the NEXTCMD_ADDR i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 534 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) register. To start DMA processing, for the first command, one must initialize the PIO registers of the desired channel. First load the next command address register with a pointer to the first command to be loaded. Then, write a one to the counting semaphore register. This causes the DMA to schedule the targeted channel for DMA command structure load, as if it just finished its previous command. 7.4 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. 7.5 Programmable Registers APBX Hardware Register Format Summary HW_APBX memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8002_4000 AHB to APBX Bridge Control Register 0 (HW_APBX_CTRL0) 32 R/W C000_0000h 7.5.1/541 8002_4010 AHB to APBX Bridge Control Register 1 (HW_APBX_CTRL1) 32 R/W 0000_0000h 7.5.2/542 8002_4020 AHB to APBX Bridge Control and Status Register 2 (HW_APBX_CTRL2) 32 R/W 0000_0000h 7.5.3/545 8002_4030 AHB to APBX Bridge Channel Register (HW_APBX_CHANNEL_CTRL) 32 R/W 0000_0000h 7.5.4/550 8002_4040 AHB to APBX DMA Device Assignment Register (HW_APBX_DEVSEL) 32 R 0000_0000h 7.5.5/551 8002_4100 APBX DMA Channel 0 Current Command Address Register (HW_APBX_CH0_CURCMDAR) 32 R 0000_0000h 7.5.6/553 8002_4110 APBX DMA Channel 0 Next Command Address Register (HW_APBX_CH0_NXTCMDAR) 32 R/W 0000_0000h 7.5.7/553 8002_4120 APBX DMA Channel 0 Command Register (HW_APBX_CH0_CMD) 32 R 0000_0000h 7.5.8/554 8002_4130 APBX DMA Channel 0 Buffer Address Register (HW_APBX_CH0_BAR) 32 R 0000_0000h 7.5.9/556 8002_4140 APBX DMA Channel 0 Semaphore Register (HW_APBX_CH0_SEMA) 32 R/W 0000_0000h 7.5.10/557 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 535 Programmable Registers HW_APBX memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8002_4150 AHB to APBX DMA Channel 0 Debug Information (HW_APBX_CH0_DEBUG1) 32 R 00A0_0000h 7.5.11/558 8002_4160 AHB to APBX DMA Channel 0 Debug Information (HW_APBX_CH0_DEBUG2) 32 R 0000_0000h 7.5.12/560 8002_4170 APBX DMA Channel 1 Current Command Address Register (HW_APBX_CH1_CURCMDAR) 32 R 0000_0000h 7.5.13/561 8002_4180 APBX DMA Channel 1 Next Command Address Register (HW_APBX_CH1_NXTCMDAR) 32 R/W 0000_0000h 7.5.14/561 8002_4190 APBX DMA Channel 1 Command Register (HW_APBX_CH1_CMD) 32 R 0000_0000h 7.5.15/562 8002_41A0 APBX DMA Channel 1 Buffer Address Register (HW_APBX_CH1_BAR) 32 R 0000_0000h 7.5.16/564 8002_41B0 APBX DMA Channel 1 Semaphore Register (HW_APBX_CH1_SEMA) 32 R/W 0000_0000h 7.5.17/565 8002_41C0 AHB to APBX DMA Channel 1 Debug Information (HW_APBX_CH1_DEBUG1) 32 R 00A0_0000h 7.5.18/566 8002_41D0 AHB to APBX DMA Channel 1 Debug Information (HW_APBX_CH1_DEBUG2) 32 R 0000_0000h 7.5.19/568 8002_41E0 APBX DMA Channel 2 Current Command Address Register (HW_APBX_CH2_CURCMDAR) 32 R 0000_0000h 7.5.20/569 8002_41F0 APBX DMA Channel 2 Next Command Address Register (HW_APBX_CH2_NXTCMDAR) 32 R/W 0000_0000h 7.5.21/569 8002_4200 APBX DMA Channel 2 Command Register (HW_APBX_CH2_CMD) 32 R 0000_0000h 7.5.22/570 8002_4210 APBX DMA Channel 2 Buffer Address Register (HW_APBX_CH2_BAR) 32 R 0000_0000h 7.5.23/572 8002_4220 APBX DMA Channel 2 Semaphore Register (HW_APBX_CH2_SEMA) 32 R/W 0000_0000h 7.5.24/572 8002_4230 AHB to APBX DMA Channel 2 Debug Information (HW_APBX_CH2_DEBUG1) 32 R 00A0_0000h 7.5.25/573 8002_4240 AHB to APBX DMA Channel 2 Debug Information (HW_APBX_CH2_DEBUG2) 32 R 0000_0000h 7.5.26/576 8002_4250 APBX DMA Channel 3 Current Command Address Register (HW_APBX_CH3_CURCMDAR) 32 R 0000_0000h 7.5.27/576 8002_4260 APBX DMA Channel 3 Next Command Address Register (HW_APBX_CH3_NXTCMDAR) 32 R/W 0000_0000h 7.5.28/577 8002_4270 APBX DMA Channel 3 Command Register (HW_APBX_CH3_CMD) 32 R 0000_0000h 7.5.29/577 8002_4280 APBX DMA Channel 3 Buffer Address Register (HW_APBX_CH3_BAR) 32 R 0000_0000h 7.5.30/579 8002_4290 APBX DMA Channel 3 Semaphore Register (HW_APBX_CH3_SEMA) 32 R/W 0000_0000h 7.5.31/580 8002_42A0 AHB to APBX DMA Channel 3 Debug Information (HW_APBX_CH3_DEBUG1) 32 R 0000_0000h 7.5.32/580 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 536 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8002_42B0 AHB to APBX DMA Channel 3 Debug Information (HW_APBX_CH3_DEBUG2) 32 R 0000_0000h 7.5.33/583 8002_42C0 APBX DMA Channel 4 Current Command Address Register (HW_APBX_CH4_CURCMDAR) 32 R 0000_0000h 7.5.34/583 8002_42D0 APBX DMA Channel 4 Next Command Address Register (HW_APBX_CH4_NXTCMDAR) 32 R/W 0000_0000h 7.5.35/584 8002_42E0 APBX DMA Channel 4 Command Register (HW_APBX_CH4_CMD) 32 R 0000_0000h 7.5.36/584 8002_42F0 APBX DMA Channel 4 Buffer Address Register (HW_APBX_CH4_BAR) 32 R 0000_0000h 7.5.37/586 8002_4300 APBX DMA Channel 4 Semaphore Register (HW_APBX_CH4_SEMA) 32 R/W 0000_0000h 7.5.38/587 8002_4310 AHB to APBX DMA Channel 4 Debug Information (HW_APBX_CH4_DEBUG1) 32 R 00A0_0000h 7.5.39/588 8002_4320 AHB to APBX DMA Channel 4 Debug Information (HW_APBX_CH4_DEBUG2) 32 R 0000_0000h 7.5.40/590 8002_4330 APBX DMA Channel 5 Current Command Address Register (HW_APBX_CH5_CURCMDAR) 32 R 0000_0000h 7.5.41/591 8002_4340 APBX DMA Channel 5 Next Command Address Register (HW_APBX_CH5_NXTCMDAR) 32 R/W 0000_0000h 7.5.42/591 8002_4350 APBX DMA Channel 5 Command Register (HW_APBX_CH5_CMD) 32 R 0000_0000h 7.5.43/592 8002_4360 APBX DMA Channel 5 Buffer Address Register (HW_APBX_CH5_BAR) 32 R 0000_0000h 7.5.44/594 8002_4370 APBX DMA Channel 5 Semaphore Register (HW_APBX_CH5_SEMA) 32 R/W 0000_0000h 7.5.45/594 8002_4380 AHB to APBX DMA Channel 5 Debug Information (HW_APBX_CH5_DEBUG1) 32 R 00A0_0000h 7.5.46/595 8002_4390 AHB to APBX DMA Channel 5 Debug Information (HW_APBX_CH5_DEBUG2) 32 R 0000_0000h 7.5.47/598 8002_43A0 APBX DMA Channel 6 Current Command Address Register (HW_APBX_CH6_CURCMDAR) 32 R 0000_0000h 7.5.48/598 8002_43B0 APBX DMA Channel 6 Next Command Address Register (HW_APBX_CH6_NXTCMDAR) 32 R/W 0000_0000h 7.5.49/599 8002_43C0 APBX DMA Channel 6 Command Register (HW_APBX_CH6_CMD) 32 R 0000_0000h 7.5.50/599 8002_43D0 APBX DMA Channel 6 Buffer Address Register (HW_APBX_CH6_BAR) 32 R 0000_0000h 7.5.51/601 8002_43E0 APBX DMA Channel 6 Semaphore Register (HW_APBX_CH6_SEMA) 32 R/W 0000_0000h 7.5.52/602 8002_43F0 AHB to APBX DMA Channel 6 Debug Information (HW_APBX_CH6_DEBUG1) 32 R 00A0_0000h 7.5.53/603 8002_4400 AHB to APBX DMA Channel 6 Debug Information (HW_APBX_CH6_DEBUG2) 32 R 0000_0000h 7.5.54/605 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 537 Programmable Registers HW_APBX memory map (continued) Absolute address (hex) Register name 8002_4410 APBX DMA Channel 7 Current Command Address Register (HW_APBX_CH7_CURCMDAR) 32 8002_4420 APBX DMA Channel 7 Next Command Address Register (HW_APBX_CH7_NXTCMDAR) 8002_4430 Width Access (in bits) Reset value Section/ page R 0000_0000h 7.5.55/606 32 R/W 0000_0000h 7.5.56/606 APBX DMA Channel 7 Command Register (HW_APBX_CH7_CMD) 32 R 0000_0000h 7.5.57/607 8002_4440 APBX DMA Channel 7 Buffer Address Register (HW_APBX_CH7_BAR) 32 R 0000_0000h 7.5.58/609 8002_4450 APBX DMA Channel 7 Semaphore Register (HW_APBX_CH7_SEMA) 32 R/W 0000_0000h 7.5.59/610 8002_4460 AHB to APBX DMA Channel 7 Debug Information (HW_APBX_CH7_DEBUG1) 32 R 00A0_0000h 7.5.60/610 8002_4470 AHB to APBX DMA Channel 7 Debug Information (HW_APBX_CH7_DEBUG2) 32 R 0000_0000h 7.5.61/613 8002_4480 APBX DMA Channel 8 Current Command Address Register (HW_APBX_CH8_CURCMDAR) 32 R 0000_0000h 7.5.62/613 8002_4490 APBX DMA Channel 8 Next Command Address Register (HW_APBX_CH8_NXTCMDAR) 32 R/W 0000_0000h 7.5.63/614 8002_44A0 APBX DMA Channel 8 Command Register (HW_APBX_CH8_CMD) 32 R 0000_0000h 7.5.64/614 8002_44B0 APBX DMA Channel 8 Buffer Address Register (HW_APBX_CH8_BAR) 32 R 0000_0000h 7.5.65/616 8002_44C0 APBX DMA Channel 8 Semaphore Register (HW_APBX_CH8_SEMA) 32 R/W 0000_0000h 7.5.66/617 8002_44D0 AHB to APBX DMA Channel 8 Debug Information (HW_APBX_CH8_DEBUG1) 32 R 00A0_0000h 7.5.67/618 8002_44E0 AHB to APBX DMA Channel 8 Debug Information (HW_APBX_CH8_DEBUG2) 32 R 0000_0000h 7.5.68/620 8002_44F0 APBX DMA Channel 9 Current Command Address Register (HW_APBX_CH9_CURCMDAR) 32 R 0000_0000h 7.5.69/621 8002_4500 APBX DMA Channel 9 Next Command Address Register (HW_APBX_CH9_NXTCMDAR) 32 R/W 0000_0000h 7.5.70/621 8002_4510 APBX DMA Channel 9 Command Register (HW_APBX_CH9_CMD) 32 R 0000_0000h 7.5.71/622 8002_4520 APBX DMA Channel 9 Buffer Address Register (HW_APBX_CH9_BAR) 32 R 0000_0000h 7.5.72/624 8002_4530 APBX DMA Channel 9 Semaphore Register (HW_APBX_CH9_SEMA) 32 R/W 0000_0000h 7.5.73/625 8002_4540 AHB to APBX DMA Channel 9 Debug Information (HW_APBX_CH9_DEBUG1) 32 R 00A0_0000h 7.5.74/625 8002_4550 AHB to APBX DMA Channel 9 Debug Information (HW_APBX_CH9_DEBUG2) 32 R 0000_0000h 7.5.75/628 8002_4560 APBX DMA Channel 10 Current Command Address Register (HW_APBX_CH10_CURCMDAR) 32 R 0000_0000h 7.5.76/628 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 538 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8002_4570 APBX DMA Channel 10 Next Command Address Register (HW_APBX_CH10_NXTCMDAR) 32 R/W 0000_0000h 7.5.77/629 8002_4580 APBX DMA Channel 10 Command Register (HW_APBX_CH10_CMD) 32 R 0000_0000h 7.5.78/629 8002_4590 APBX DMA Channel 10 Buffer Address Register (HW_APBX_CH10_BAR) 32 R 0000_0000h 7.5.79/631 8002_45A0 APBX DMA Channel 10 Semaphore Register (HW_APBX_CH10_SEMA) 32 R/W 0000_0000h 7.5.80/632 8002_45B0 AHB to APBX DMA Channel 10 Debug Information (HW_APBX_CH10_DEBUG1) 32 R 00A0_0000h 7.5.81/633 8002_45C0 AHB to APBX DMA Channel 10 Debug Information (HW_APBX_CH10_DEBUG2) 32 R 0000_0000h 7.5.82/635 8002_45D0 APBX DMA Channel 11 Current Command Address Register (HW_APBX_CH11_CURCMDAR) 32 R 0000_0000h 7.5.83/636 8002_45E0 APBX DMA Channel 11 Next Command Address Register (HW_APBX_CH11_NXTCMDAR) 32 R/W 0000_0000h 7.5.84/636 8002_45F0 APBX DMA Channel 11 Command Register (HW_APBX_CH11_CMD) 32 R 0000_0000h 7.5.85/637 8002_4600 APBX DMA Channel 11 Buffer Address Register (HW_APBX_CH11_BAR) 32 R 0000_0000h 7.5.86/639 8002_4610 APBX DMA Channel 11 Semaphore Register (HW_APBX_CH11_SEMA) 32 R/W 0000_0000h 7.5.87/639 8002_4620 AHB to APBX DMA Channel 11 Debug Information (HW_APBX_CH11_DEBUG1) 32 R 00A0_0000h 7.5.88/640 8002_4630 AHB to APBX DMA Channel 11 Debug Information (HW_APBX_CH11_DEBUG2) 32 R 0000_0000h 7.5.89/643 8002_4640 APBX DMA Channel 12 Current Command Address Register (HW_APBX_CH12_CURCMDAR) 32 R 0000_0000h 7.5.90/643 8002_4650 APBX DMA Channel 12 Next Command Address Register (HW_APBX_CH12_NXTCMDAR) 32 R/W 0000_0000h 7.5.91/644 8002_4660 APBX DMA Channel 12 Command Register (HW_APBX_CH12_CMD) 32 R 0000_0000h 7.5.92/644 8002_4670 APBX DMA Channel 12 Buffer Address Register (HW_APBX_CH12_BAR) 32 R 0000_0000h 7.5.93/646 8002_4680 APBX DMA Channel 12 Semaphore Register (HW_APBX_CH12_SEMA) 32 R/W 0000_0000h 7.5.94/647 8002_4690 AHB to APBX DMA Channel 12 Debug Information (HW_APBX_CH12_DEBUG1) 32 R 00A0_0000h 7.5.95/648 8002_46A0 AHB to APBX DMA Channel 12 Debug Information (HW_APBX_CH12_DEBUG2) 32 R 0000_0000h 7.5.96/650 8002_46B0 APBX DMA Channel 13 Current Command Address Register (HW_APBX_CH13_CURCMDAR) 32 R 0000_0000h 7.5.97/651 8002_46C0 APBX DMA Channel 13 Next Command Address Register (HW_APBX_CH13_NXTCMDAR) 32 R/W 0000_0000h 7.5.98/651 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 539 Programmable Registers HW_APBX memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8002_46D0 APBX DMA Channel 13 Command Register (HW_APBX_CH13_CMD) 32 R 0000_0000h 7.5.99/652 8002_46E0 APBX DMA Channel 13 Buffer Address Register (HW_APBX_CH13_BAR) 32 R 0000_0000h 7.5.100/ 654 8002_46F0 APBX DMA Channel 13 Semaphore Register (HW_APBX_CH13_SEMA) 32 R/W 0000_0000h 7.5.101/ 654 8002_4700 AHB to APBX DMA Channel 13 Debug Information (HW_APBX_CH13_DEBUG1) 32 R 00A0_0000h 7.5.102/ 655 8002_4710 AHB to APBX DMA Channel 13 Debug Information (HW_APBX_CH13_DEBUG2) 32 R 0000_0000h 7.5.103/ 658 8002_4720 APBX DMA Channel 14 Current Command Address Register (HW_APBX_CH14_CURCMDAR) 32 R 0000_0000h 7.5.104/ 658 8002_4730 APBX DMA Channel 14 Next Command Address Register (HW_APBX_CH14_NXTCMDAR) 32 R/W 0000_0000h 7.5.105/ 659 8002_4740 APBX DMA Channel 14 Command Register (HW_APBX_CH14_CMD) 32 R 0000_0000h 7.5.106/ 659 8002_4750 APBX DMA Channel 14 Buffer Address Register (HW_APBX_CH14_BAR) 32 R 0000_0000h 7.5.107/ 661 8002_4760 APBX DMA Channel 14 Semaphore Register (HW_APBX_CH14_SEMA) 32 R/W 0000_0000h 7.5.108/ 662 8002_4770 AHB to APBX DMA Channel 14 Debug Information (HW_APBX_CH14_DEBUG1) 32 R 00A0_0000h 7.5.109/ 663 8002_4780 AHB to APBX DMA Channel 14 Debug Information (HW_APBX_CH14_DEBUG2) 32 R 0000_0000h 7.5.110/ 665 8002_4790 APBX DMA Channel 15 Current Command Address Register (HW_APBX_CH15_CURCMDAR) 32 R 0000_0000h 7.5.111/ 666 8002_47A0 APBX DMA Channel 15 Next Command Address Register (HW_APBX_CH15_NXTCMDAR) 32 R/W 0000_0000h 7.5.112/ 666 8002_47B0 APBX DMA Channel 15 Command Register (HW_APBX_CH15_CMD) 32 R 0000_0000h 7.5.113/ 667 8002_47C0 APBX DMA Channel 15 Buffer Address Register (HW_APBX_CH15_BAR) 32 R 0000_0000h 7.5.114/ 669 8002_47D0 APBX DMA Channel 15 Semaphore Register (HW_APBX_CH15_SEMA) 32 R/W 0000_0000h 7.5.115/ 669 8002_47E0 AHB to APBX DMA Channel 15 Debug Information (HW_APBX_CH15_DEBUG1) 32 R 00A0_0000h 7.5.116/ 670 8002_47F0 AHB to APBX DMA Channel 15 Debug Information (HW_APBX_CH15_DEBUG2) 32 R 0000_0000h 7.5.117/ 673 8002_4800 APBX Bridge Version Register (HW_APBX_VERSION) 32 R 0202_0000h 7.5.118/ 673 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 540 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 7.5.1 AHB to APBX Bridge Control Register 0 (HW_APBX_CTRL0) The APBX CTRL 0 provides overall control and IRQ status of the AHB to APBX bridge and DMA. HW_APBX_CTRL0: 0x000 HW_APBX_CTRL0_SET: 0x004 HW_APBX_CTRL0_CLR: 0x008 HW_APBX_CTRL0_TOG: 0x00C This register contains softreset, clock gating bits. Address: 8002_4000h base + 0h offset = 8002_4000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD0 SFTRST CLKGATE R 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset Bit RSVD0 R W Reset 0 0 0 0 0 0 0 0 0 HW_APBX_CTRL0 field descriptions Field 31 SFTRST 30 CLKGATE RSVD0 Description Set this bit to zero to enable normal APBX DMA operation. Set this bit to one (default) to disable clocking with the APBX DMA and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the APBX DMA block to its default state. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. Reserved, always set to zero. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 541 Programmable Registers 7.5.2 AHB to APBX Bridge Control Register 1 (HW_APBX_CTRL1) The APBX CTRL 1 provides channel complete IRQ status of the AHB to APBX bridge and DMA. HW_APBX_CTRL1: 0x010 HW_APBX_CTRL1_SET: 0x014 HW_APBX_CTRL1_CLR: 0x018 HW_APBX_CTRL1_TOG: 0x01C This register contains the per channel interrupt status bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller. EXAMPLE BF_WR(APBX_CTRL1, CH5_CMDCMPLT_IRQ, 0); BF_APBX_CTRL1.CH5_CMDCMPLT_IRQ = 0; // use bitfield write macro // or, assign to register struct's bitfield Address: 8002_4000h base + 10h offset = 8002_4010h CH4_CMDCMPLT_ IRQ_EN CH3_CMDCMPLT_ IRQ_EN CH2_CMDCMPLT_ IRQ_EN CH1_CMDCMPLT_ IRQ_EN CH0_CMDCMPLT_ IRQ_EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH4_CMDCMPLT_ IRQ CH3_CMDCMPLT_ IRQ CH2_CMDCMPLT_ IRQ CH1_CMDCMPLT_ IRQ CH0_CMDCMPLT_ IRQ 16 CH5_CMDCMPLT_ IRQ_EN 17 CH5_CMDCMPLT_ IRQ 18 CH6_CMDCMPLT_ IRQ_EN 19 CH6_CMDCMPLT_ IRQ 20 CH7_CMDCMPLT_ IRQ_EN 21 CH7_CMDCMPLT_ IRQ 22 CH8_CMDCMPLT_ IRQ_EN 23 CH8_CMDCMPLT_ IRQ Reset 24 CH9_CMDCMPLT_ IRQ W 25 CH10_ CMDCMPLT_IRQ R 26 CH11_ CMDCMPLT_IRQ Bit 27 CH12_ CMDCMPLT_IRQ Reset 28 CH13_ CMDCMPLT_IRQ W 29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH15_ CMDCMPLT_IRQ_ EN CH14_ CMDCMPLT_IRQ_ EN CH13_ CMDCMPLT_IRQ_ EN CH12_ CMDCMPLT_IRQ_ EN CH11_ CMDCMPLT_IRQ_ EN CH10_ CMDCMPLT_IRQ_ EN CH9_CMDCMPLT_ IRQ_EN R 30 CH14_ CMDCMPLT_IRQ 31 CH15_ CMDCMPLT_IRQ Bit HW_APBX_CTRL1 field descriptions Field 31 CH15_ CMDCMPLT_ IRQ_EN Description Setting this bit enables the generation of an interrupt request for APBX DMA Channel 15. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 542 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CTRL1 field descriptions (continued) Field Description 30 CH14_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 14. 29 CH13_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 13. 28 CH12_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 12. 27 CH11_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 11. 26 CH10_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 10. 25 CH9_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 9. 24 CH8_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 8. 23 CH7_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 7. 22 CH6_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 6. 21 CH5_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 5. 20 CH4_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 4. 19 CH3_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 3. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 543 Programmable Registers HW_APBX_CTRL1 field descriptions (continued) Field Description 18 CH2_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 2. 17 CH1_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1. 16 CH0_ CMDCMPLT_ IRQ_EN Setting this bit enables the generation of an interrupt request for APBX DMA Channel 0. 15 CH15_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 15. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 14 CH14_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 14. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 13 CH13_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 13. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 12 CH12_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 12. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 11 CH11_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 11. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 10 CH10_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 10. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 9 CH9_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 9. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 8 CH8_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 8. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 7 CH7_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 7. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 544 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CTRL1 field descriptions (continued) Field Description 6 CH6_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 6. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 5 CH5_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 5. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 4 CH4_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 4. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 3 CH3_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 3. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 2 CH2_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 2. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 1 CH1_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 1. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 0 CH0_ CMDCMPLT_ IRQ Interrupt request status bit for APBX DMA Channel 0. This sticky bit is set by DMA hardware and reset by software. It is ANDed with its corresponding enable bit to generate an interrupt. 7.5.3 AHB to APBX Bridge Control and Status Register 2 (HW_APBX_CTRL2) The APBX CTRL 2 provides channel error interrupts generated by the AHB to APBX DMA. HW_APBX_CTRL2: 0x020 HW_APBX_CTRL2_SET: 0x024 HW_APBX_CTRL2_CLR: 0x028 HW_APBX_CTRL2_TOG: 0x02C This register contains the per channel bus error interrupt status bits and the per channel completion interrupt enable bits. Each channel has a dedicated interrupt vector in the vectored interrupt controller. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 545 546 CH11_ERROR_STATUS CH10_ERROR_STATUS CH9_ERROR_STATUS CH8_ERROR_STATUS CH7_ERROR_STATUS CH6_ERROR_STATUS CH5_ERROR_STATUS CH4_ERROR_STATUS CH3_ERROR_STATUS CH2_ERROR_STATUS CH1_ERROR_STATUS CH0_ERROR_STATUS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH11_ERROR_IRQ CH10_ERROR_IRQ CH9_ERROR_IRQ CH8_ERROR_IRQ CH7_ERROR_IRQ CH6_ERROR_IRQ CH5_ERROR_IRQ CH4_ERROR_IRQ CH3_ERROR_IRQ CH2_ERROR_IRQ CH1_ERROR_IRQ CH0_ERROR_IRQ Reset CH12_ERROR_STATUS W 0 CH12_ERROR_IRQ R CH13_ERROR_STATUS Bit 0 CH13_ERROR_IRQ Reset CH14_ERROR_STATUS W CH14_ERROR_IRQ R CH15_ERROR_STATUS Bit CH15_ERROR_IRQ Programmable Registers Address: 8002_4000h base + 20h offset = 8002_4020h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CTRL2 field descriptions Field Description 31 Error status bit for APBX DMA Channel 15. Valid when corresponding Error IRQ is set. CH15_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 30 Error status bit for APBX DMA Channel 14. Valid when corresponding Error IRQ is set. CH14_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 29 Error status bit for APBX DMA Channel 13. Valid when corresponding Error IRQ is set. CH13_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 28 Error status bit for APBX DMA Channel 12. Valid when corresponding Error IRQ is set. CH12_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 27 Error status bit for APBX DMA Channel 11. Valid when corresponding Error IRQ is set. CH11_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 26 Error status bit for APBX DMA Channel 10. Valid when corresponding Error IRQ is set. CH10_ERROR_ 1 - AHB bus error STATUS 0 - channel early termination. 0x0 0x1 25 CH9_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 9. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 24 CH8_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 8. Valid when corresponding Error IRQ is set. 1 - AHB bus error Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 547 Programmable Registers HW_APBX_CTRL2 field descriptions (continued) Field Description 0 - channel early termination. 0x0 0x1 23 CH7_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 7. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 22 CH6_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 6. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 21 CH5_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 5. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 20 CH4_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 4. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 19 CH3_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 3. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 18 CH2_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 2. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 17 CH1_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 1. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 548 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CTRL2 field descriptions (continued) Field Description 0x0 0x1 16 CH0_ERROR_ STATUS TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. Error status bit for APBX DMA Channel 0. Valid when corresponding Error IRQ is set. 1 - AHB bus error 0 - channel early termination. 0x0 0x1 TERMINATION -- An early termination from the device causes error IRQ. BUS_ERROR -- An AHB bus error causes error IRQ. 15 Error interrupt status bit for APBX DMA Channel 15. This sticky bit is set by DMA hardware and reset by CH15_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 14 Error interrupt status bit for APBX DMA Channel 14. This sticky bit is set by DMA hardware and reset by CH14_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 13 Error interrupt status bit for APBX DMA Channel 13. This sticky bit is set by DMA hardware and reset by CH13_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 12 Error interrupt status bit for APBX DMA Channel 12. This sticky bit is set by DMA hardware and reset by CH12_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 11 Error interrupt status bit for APBX DMA Channel 11. This sticky bit is set by DMA hardware and reset by CH11_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 10 Error interrupt status bit for APBX DMA Channel 10. This sticky bit is set by DMA hardware and reset by CH10_ERROR_ software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. IRQ 9 CH9_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 9. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 8 CH8_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 8. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 7 CH7_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 7. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 6 CH6_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 6. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 5 CH5_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 5. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 4 CH4_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 4. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 3 CH3_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 3. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 549 Programmable Registers HW_APBX_CTRL2 field descriptions (continued) Field Description 2 CH2_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 2. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 1 CH1_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 1. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 0 CH0_ERROR_ IRQ Error interrupt status bit for APBX DMA Channel 0. This sticky bit is set by DMA hardware and reset by software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM. 7.5.4 AHB to APBX Bridge Channel Register (HW_APBX_CHANNEL_CTRL) The APBX CHANNEL CTRL provides reset/freeze control of each DMA channel. HW_APBX_CHANNEL_CTRL: 0x030 HW_APBX_CHANNEL_CTRL_SET: 0x034 HW_APBX_CHANNEL_CTRL_CLR: 0x038 HW_APBX_CHANNEL_CTRL_TOG: 0x03C This register contains individual channel reset/freeze bits. Address: 8002_4000h base + 30h offset = 8002_4030h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RESET_CHANNEL 0 0 0 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 FREEZE_CHANNEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CHANNEL_CTRL field descriptions Field 31-16 RESET_ CHANNEL Description Setting a bit in this field causes the DMA controller to take the corresponding channel through its reset state. The bit is reset after the channel resources are cleared. 0x0001 0x0002 0x0004 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 UART4_RX -- UART4_TX -- SPDIF_TX -- SAIF0 -- SAIF1 -- I2C0 -- I2C1 -- UART0_RX -- UART0_TX -- UART1_RX -- Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 550 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CHANNEL_CTRL field descriptions (continued) Field Description 0x0800 0x1000 0x2000 0x4000 0x8000 FREEZE_ CHANNEL UART1_TX -- UART2_RX -- UART2_TX -- UART3_RX -- UART3_TX -- Setting a bit in this field will freeze the DMA channel associated with it. This field is a direct input to the DMA channel arbiter. When frozen, the channel is deined access to the central DMA resources. Note: 1. DMA PIO write to associated peripheral is not supported when Freeze bit is to set, and use ARM instead to configure peripheral. 2. After FREEZE bit is set, no more access, neither AHB access to memory nor APB access to peripherals, will be allowed by arbiter. But, there might be on-going channel access exactly when FREEZE bit is set, either INCR8/INCR4/SINGLE AHB access or APB peripheral access, this ongoing access will not be affected by FREEZE bit and will finish as normal. That is to say, setting FREEZE bit might not freeze channel access immediately, it only freezes further channel access, and you have to wait a while to freeze channel access completely. To make sure that there is no more access from freezed channel, channel state machine should be checked by reading channel DEBUG1 register, wait till state stunk at any of IDLE, READ_REQ, WRITE, or CHAIN_WAIT. 0x0001 0x0002 0x0004 0x0010 0x0020 0x0040 0x0080 0x0100 0x0200 0x0400 0x0800 0x1000 0x2000 0x4000 0x8000 UART4_RX -- UART4_TX -- SPDIF_TX -- SAIF0 -- SAIF1 -- I2C0 -- I2C1 -- UART0_RX -- UART0_TX -- UART1_RX -- UART1_TX -- UART2_RX -- UART2_TX -- UART3_RX -- UART3_TX -- 7.5.5 AHB to APBX DMA Device Assignment Register (HW_APBX_DEVSEL) This register allows reassignment of the APBX device connected to the DMA Channels. HW_APBX_DEVSEL: 0x040 HW_APBX_DEVSEL_SET: 0x044 HW_APBX_DEVSEL_CLR: 0x048 HW_APBX_DEVSEL_TOG: 0x04C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 551 Programmable Registers In this chip, apbxdma channel resource is enough for peripherals, so this register is of no use and reserved. Address: 8002_4000h base + 40h offset = 8002_4040h Bit 31 30 29 CH15 R 28 27 CH14 26 25 CH13 24 23 CH12 22 21 CH11 20 19 CH10 18 17 CH9 16 CH8 W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH7 R CH6 CH5 CH4 CH3 CH2 CH1 CH0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_DEVSEL field descriptions Field Description 31-30 CH15 Reserved. 29-28 CH14 Reserved. 27-26 CH13 Reserved. 25-24 CH12 Reserved. 23-22 CH11 Reserved. 21-20 CH10 Reserved. 19-18 CH9 Reserved. 17-16 CH8 Reserved. 15-14 CH7 Reserved. 13-12 CH6 Reserved. 11-10 CH5 Reserved. 9-8 CH4 Reserved. 7-6 CH3 Reserved. 5-4 CH2 Reserved. 3-2 CH1 Reserved. CH0 Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 552 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 7.5.6 APBX DMA Channel 0 Current Command Address Register (HW_APBX_CH0_CURCMDAR) The APBX DMA Channel 0 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 0 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE pCurCmd = (hw_apbx_chn_cmd_t *) HW_APBX_CHn_CURCMDAR_RD(0); register, since there is only one field pCurCmd = (hw_apbx_chn_cmd_t *) BF_RDn(APBX_CHn_CURCMDAR, 0, CMD_ADDR); register bitfield read macro pCurCmd = (hw_apbx_chn_cmd_t *) HW_APBX_CHn_CURCMDAR(0).CMD_ADDR; bitfield of indexed register's struct // read the whole // or, use multi// or, assign from Address: 8002_4000h base + 100h offset = 8002_4100h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH0_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for channel 0. 7.5.7 APBX DMA Channel 0 Next Command Address Register (HW_APBX_CH0_NXTCMDAR) The APBX DMA Channel 0 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 0 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 0 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 553 Programmable Registers HW_APBX_CHn_NXTCMDAR_WR(0, (reg32_t) pCommandTwoStructure); register, since there is only one field BF_WRn(APBX_CHn_NXTCMDAR, 0, (reg32_t) pCommandTwoStructure); register bitfield write macro HW_APBX_CHn_NXTCMDAR(0).CMD_ADDR = (reg32_t) pCommandTwoStructure; bitfield of indexed register's struct // write the entire // or, use multi// or, assign to Address: 8002_4000h base + 110h offset = 8002_4110h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH0_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 0. 7.5.8 APBX DMA Channel 0 Command Register (HW_APBX_CH0_CMD) The APBX DMA Channel 0 command register specifies the DMA transaction to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. EXAMPLE hw_apbx_chn_cmd_t dma_cmd; dma_cmd.XFER_COUNT = 512; dma_cmd.COMMAND = BV_APBX_CHn_CMD_COMMAND__DMA_WRITE; peripheral device dma_cmd.CHAIN = 1; structure on to the list dma_cmd.IRQONCMPLT = 1; completion of this command structure // transfer 512 bytes // transfer to system memory from // chain an additional command // generate an interrupt on i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 554 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 120h offset = 8002_4120h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XFER_COUNT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQONCMPLT CHAIN Bit 0 SEMAPHORE Reset WAIT4ENDCMD W 0 0 0 0 CMDWORDS R RSVD1 RSVD0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH0_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-8 RSVD1 Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART4 device HW_UARTAPP_DATA. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART, starting with the base PIO address of the UART4 (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words Reserved, always set to zero. 7 A value of one indicates that the channel will wait for the end of command signal to be sent from the WAIT4ENDCMD ABPX device to the DMA before starting the next DMA command. 6 SEMAPHORE A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 555 Programmable Registers HW_APBX_CH0_CMD field descriptions (continued) Field Description 5-4 RSVD0 Reserved, always set to zero. 3 IRQONCMPLT 2 CHAIN A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH0_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x0 0x1 0x2 7.5.9 APBX DMA Channel 0 Buffer Address Register (HW_APBX_CH0_BAR) The APBX DMA Channel 0 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE hw_apbx_chn_bar_t dma_data; dma_data.ADDRESS = (reg32_t) pDataBuffer; Address: 8002_4000h base + 130h offset = 8002_4130h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 556 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH0_BAR field descriptions Field Description ADDRESS Address of system memory buffer to be read or written over the AHB bus. 7.5.10 APBX DMA Channel 0 Semaphore Register (HW_APBX_CH0_SEMA) The APBX DMA Channel 0 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE BF_WR(APBX_CHn_SEMA, 0, INCREMENT_SEMA, 2); current_sema = BF_RD(APBX_CHn_SEMA, 0, PHORE); // increment semaphore by two // get instantaneous value Address: 8002_4000h base + 140h offset = 8002_4140h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH0_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 557 Programmable Registers 7.5.11 AHB to APBX DMA Channel 0 Debug Information (HW_APBX_CH0_DEBUG1) This register gives debug visibility into the APBX DMA Channel 0 state machine and controls. This register allows debug visibility of the APBX DMA Channel 0. 0 0 25 RSVD2 24 23 22 21 20 WR_FIFO_FULL 0 26 WR_FIFO_EMPTY END 0 27 RD_FIFO_FULL 28 RD_FIFO_EMPTY 29 NEXTCMDADDRVALID 30 KICK R 31 BURST Bit REQ Address: 8002_4000h base + 150h offset = 8002_4150h 0 1 0 1 0 19 18 17 16 RSVD1 W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 558 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 RSVD1 R 3 2 1 0 STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH0_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 0 state machine state. 0x00 IDLE -- This is the idle state of the DMA state machine. 0x01 REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. 0x02 REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 559 Programmable Registers HW_APBX_CH0_DEBUG1 field descriptions (continued) Field Description 0x03 REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. 0x04 XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. 0x05 REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. 0x06 REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. 0x07 PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. 0x08 READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. 0x09 READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. 0x0C WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0D READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0E CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.12 AHB to APBX DMA Channel 0 Debug Information (HW_APBX_CH0_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 0. This register allows debug visibility of the APBX DMA Channel 0. Address: 8002_4000h base + 160h offset = 8002_4160h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 560 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH0_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.13 APBX DMA Channel 1 Current Command Address Register (HW_APBX_CH1_CURCMDAR) The APBX DMA Channel 1 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 1 is controlled by a variable sized command structure. This register points to the command structure currently being executed. EXAMPLE pCurCmd = (hw_apbx_chn_cmd_t *) HW_APBX_CHn_CURCMDAR_RD(1); register, since there is only one field pCurCmd = (hw_apbx_chn_cmd_t *) BF_RDn(APBX_CHn_CURCMDAR, 1, CMD_ADDR); register bitfield read macro pCurCmd = (hw_apbx_chn_cmd_t *) HW_APBX_CHn_CURCMDAR(1).CMD_ADDR; bitfield of indexed register's struct // read the whole // or, use multi// or, assign from Address: 8002_4000h base + 170h offset = 8002_4170h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH1_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for channel 1. 7.5.14 APBX DMA Channel 1 Next Command Address Register (HW_APBX_CH1_NXTCMDAR) The APBX DMA Channel 1 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 561 Programmable Registers APBX DMA Channel 1 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 1 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. EXAMPLE HW_APBX_CHn_NXTCMDAR_WR(1, (reg32_t) pCommandTwoStructure); register, since there is only one field BF_WRn(APBX_CHn_NXTCMDAR, 1, (reg32_t) pCommandTwoStructure); register bitfield write macro HW_APBX_CHn_NXTCMDAR(1).CMD_ADDR = (reg32_t) pCommandTwoStructure; bitfield of indexed register's struct // write the entire // or, use multi// or, assign to Address: 8002_4000h base + 180h offset = 8002_4180h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH1_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 1. 7.5.15 APBX DMA Channel 1 Command Register (HW_APBX_CH1_CMD) The APBX DMA Channel 1 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 562 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 190h offset = 8002_4190h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XFER_COUNT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQONCMPLT CHAIN Bit 0 SEMAPHORE Reset WAIT4ENDCMD W 0 0 0 0 CMDWORDS R RSVD1 RSVD0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH1_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-8 RSVD1 Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART4 device HW_UARTAPP_DATA. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the DAC, starting with the base PIO address of the UART4 (HW_UARTAPP_CTRL1) and increment from there. Zero means transfer NO command words Reserved, always set to zero. 7 A value of one indicates that the channel will wait for the end of command signal to be sent from the WAIT4ENDCMD APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 563 Programmable Registers HW_APBX_CH1_CMD field descriptions (continued) Field Description 5-4 RSVD0 Reserved, always set to zero. 3 IRQONCMPLT 2 CHAIN A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH1_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x0 0x1 0x2 7.5.16 APBX DMA Channel 1 Buffer Address Register (HW_APBX_CH1_BAR) The APBX DMA Channel 1 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. EXAMPLE hw_apbx_chn_bar_t dma_data; dma_data.ADDRESS = (reg32_t) pDataBuffer; Address: 8002_4000h base + 1A0h offset = 8002_41A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 564 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH1_BAR field descriptions Field Description ADDRESS Address of system memory buffer to be read or written over the AHB bus. 7.5.17 APBX DMA Channel 1 Semaphore Register (HW_APBX_CH1_SEMA) The APBX DMA Channel 1 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. EXAMPLE BF_WR(APBX_CHn_SEMA, 1, INCREMENT_SEMA, 2); current_sema = BF_RD(APBX_CHn_SEMA, 1, PHORE); // increment semaphore by two // get instantaneous value Address: 8002_4000h base + 1B0h offset = 8002_41B0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH1_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 565 Programmable Registers 7.5.18 AHB to APBX DMA Channel 1 Debug Information (HW_APBX_CH1_DEBUG1) This register gives debug visibility into the APBX DMA Channel 1 state machine and controls. This register allows debug visibility of the APBX DMA Channel 1. 0 0 25 RSVD2 24 23 22 21 20 WR_FIFO_FULL 0 26 WR_FIFO_EMPTY END 0 27 RD_FIFO_FULL 28 RD_FIFO_EMPTY 29 NEXTCMDADDRVALID 30 KICK R 31 BURST Bit REQ Address: 8002_4000h base + 1C0h offset = 8002_41C0h 0 1 0 1 0 19 18 17 16 RSVD1 W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 566 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 RSVD1 R 3 2 1 0 STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH1_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 1 state machine state. 0x00 IDLE -- This is the idle state of the DMA state machine. 0x01 REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. 0x02 REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 567 Programmable Registers HW_APBX_CH1_DEBUG1 field descriptions (continued) Field Description 0x03 REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. 0x04 XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. 0x05 REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. 0x06 REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. 0x07 PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. 0x08 READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. 0x09 READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. 0x0C WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0D READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0E CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.19 AHB to APBX DMA Channel 1 Debug Information (HW_APBX_CH1_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 1. This register allows debug visibility of the APBX DMA Channel 1. Address: 8002_4000h base + 1D0h offset = 8002_41D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 568 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH1_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.20 APBX DMA Channel 2 Current Command Address Register (HW_APBX_CH2_CURCMDAR) The APBX DMA Channel 2 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 2 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8002_4000h base + 1E0h offset = 8002_41E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH2_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for channel 2. 7.5.21 APBX DMA Channel 2 Next Command Address Register (HW_APBX_CH2_NXTCMDAR) The APBX DMA Channel 2 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 2 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 0 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 569 Programmable Registers Address: 8002_4000h base + 1F0h offset = 8002_41F0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH2_NXTCMDAR field descriptions Field Description CMD_ADDR Pointer to next command structure for channel 2. 7.5.22 APBX DMA Channel 2 Command Register (HW_APBX_CH2_CMD) The APBX DMA Channel 2 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 200h offset = 8002_4200h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 570 Freescale Semiconductor, Inc. 12 11 10 CMDWORDS R 9 8 RSVD1 7 6 0 0 5 4 RSVD0 3 2 CHAIN 13 IRQONCMPLT 14 SEMAPHORE 15 Bit WAIT4ENDCMD Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH2_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-8 RSVD1 Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SPDIF device. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the SPDIF, starting with the base PIO address of the SPDIF and incrementing from there. Zero means transfer NO command words Reserved, always set to zero. 7 A value of one indicates that the channel will wait for the end of command signal to be sent from the WAIT4ENDCMD APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH2_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 571 Programmable Registers HW_APBX_CH2_CMD field descriptions (continued) Field Description NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x0 0x1 0x2 7.5.23 APBX DMA Channel 2 Buffer Address Register (HW_APBX_CH2_BAR) The APBX DMA Channel 2 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 210h offset = 8002_4210h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH2_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. 7.5.24 APBX DMA Channel 2 Semaphore Register (HW_APBX_CH2_SEMA) The APBX DMA Channel 2 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 572 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 220h offset = 8002_4220h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH2_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.25 AHB to APBX DMA Channel 2 Debug Information (HW_APBX_CH2_DEBUG1) This register gives debug visibility into the APBX DMA Channel 2 state machine and controls. This register allows debug visibility of the APBX DMA Channel 2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 573 Programmable Registers Address: 8002_4000h base + 230h offset = 8002_4230h 23 22 21 20 19 18 17 16 WR_FIFO_FULL 24 WR_FIFO_EMPTY 25 RD_FIFO_FULL 26 RD_FIFO_EMPTY 27 NEXTCMDADDRVALID 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH2_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 574 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH2_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 2 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x15 IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 575 Programmable Registers HW_APBX_CH2_DEBUG1 field descriptions (continued) Field Description 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.26 AHB to APBX DMA Channel 2 Debug Information (HW_APBX_CH2_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 2. This register allows debug visibility of the APBX DMA Channel 2. Address: 8002_4000h base + 240h offset = 8002_4240h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH2_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.27 APBX DMA Channel 3 Current Command Address Register (HW_APBX_CH3_CURCMDAR) The APBX DMA Channel 3 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. Because channel 3 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 576 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 250h offset = 8002_4250h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH3_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 3. 7.5.28 APBX DMA Channel 3 Next Command Address Register (HW_APBX_CH3_NXTCMDAR) The APBX DMA Channel 3 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. Because channel 3 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8002_4000h base + 260h offset = 8002_4260h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH3_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 3. 7.5.29 APBX DMA Channel 3 Command Register (HW_APBX_CH3_CMD) The APBX DMA Channel 3 command register specifies the cycle to perform for the current command chain item. Because channel 3 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 577 Programmable Registers Address: 8002_4000h base + 270h offset = 8002_4270h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XFER_COUNT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQONCMPLT CHAIN Bit 0 SEMAPHORE Reset WAIT4ENDCMD W 0 0 0 0 CMDWORDS R RSVD1 RSVD0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH3_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-8 RSVD1 Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in assigned peripheral. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to assigned peripheral, starting with the base PIO address of the assigned peripheral and increment from there. Zero means transfer NO command words Reserved, always set to zero. 7 A value of one indicates that the channel will wait for the end of command signal to be sent from the WAIT4ENDCMD APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 578 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH3_CMD field descriptions (continued) Field Description 5-4 RSVD0 Reserved, always set to zero. 3 IRQONCMPLT 2 CHAIN A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH3_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x0 0x1 0x2 7.5.30 APBX DMA Channel 3 Buffer Address Register (HW_APBX_CH3_BAR) The APBX DMA Channel 3 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. Because channel 3 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8002_4000h base + 280h offset = 8002_4280h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH3_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 579 Programmable Registers 7.5.31 APBX DMA Channel 3 Semaphore Register (HW_APBX_CH3_SEMA) The APBX DMA Channel 3 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8002_4000h base + 290h offset = 8002_4290h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH3_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.32 AHB to APBX DMA Channel 3 Debug Information (HW_APBX_CH3_DEBUG1) This register gives debug visibility into the APBX DMA Channel 3 state machine and controls. Because channel 3 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Because channel 3 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 580 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 2A0h offset = 8002_42A0h 23 22 21 20 19 18 17 16 WR_FIFO_FULL 24 WR_FIFO_EMPTY 25 RD_FIFO_FULL 26 RD_FIFO_EMPTY 27 NEXTCMDADDRVALID 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH3_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 581 Programmable Registers HW_APBX_CH3_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 3 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x15 IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 582 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH3_DEBUG1 field descriptions (continued) Field Description 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.33 AHB to APBX DMA Channel 3 Debug Information (HW_APBX_CH3_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 3. Because channel 3 is not assigned to any peripheral, this register is of no practical usage and just reserved for compatibility. Address: 8002_4000h base + 2B0h offset = 8002_42B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH3_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.34 APBX DMA Channel 4 Current Command Address Register (HW_APBX_CH4_CURCMDAR) The APBX DMA Channel 4 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 4 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 583 Programmable Registers Address: 8002_4000h base + 2C0h offset = 8002_42C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH4_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 4. 7.5.35 APBX DMA Channel 4 Next Command Address Register (HW_APBX_CH4_NXTCMDAR) The APBX DMA Channel 4 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 4 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 4 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8002_4000h base + 2D0h offset = 8002_42D0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH4_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 4. 7.5.36 APBX DMA Channel 4 Command Register (HW_APBX_CH4_CMD) The APBX DMA Channel 4 command register specifies the cycle to perform for the current command chain item. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 584 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 2E0h offset = 8002_42E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XFER_COUNT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQONCMPLT CHAIN Bit 0 SEMAPHORE Reset WAIT4ENDCMD W 0 0 0 0 CMDWORDS R RSVD1 RSVD0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH4_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS Description This field indicates the number of bytes to transfer to or from the SAIF0 device. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the SAIF0. Zero means transfer NO command words Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 585 Programmable Registers HW_APBX_CH4_CMD field descriptions (continued) Field 11-8 RSVD1 Description Reserved, always set to zero. 7 A value of one indicates that the channel will wait for the end of command signal to be sent from the WAIT4ENDCMD APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH4_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved 0x0 0x1 0x2 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 7.5.37 APBX DMA Channel 4 Buffer Address Register (HW_APBX_CH4_BAR) The APBX DMA Channel 4 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device associate with this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 586 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 2F0h offset = 8002_42F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH4_BAR field descriptions Field Description ADDRESS Address of system memory buffer to be read or written over the AHB bus. 7.5.38 APBX DMA Channel 4 Semaphore Register (HW_APBX_CH4_SEMA) The APBX DMA Channel 4 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8002_4000h base + 300h offset = 8002_4300h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH4_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 587 Programmable Registers 7.5.39 AHB to APBX DMA Channel 4 Debug Information (HW_APBX_CH4_DEBUG1) This register gives debug visibility into the APBX DMA Channel 4 state machine and controls. This register allows debug visibility of the APBX DMA Channel 4. 0 0 25 RSVD2 24 23 22 21 20 WR_FIFO_FULL 0 26 WR_FIFO_EMPTY END 0 27 RD_FIFO_FULL 28 RD_FIFO_EMPTY 29 NEXTCMDADDRVALID 30 KICK R 31 BURST Bit REQ Address: 8002_4000h base + 310h offset = 8002_4310h 0 1 0 1 0 19 18 17 16 RSVD1 W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 588 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 RSVD1 R 3 2 1 0 STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH4_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 4 state machine state. 0x00 IDLE -- This is the idle state of the DMA state machine. 0x01 REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. 0x02 REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 589 Programmable Registers HW_APBX_CH4_DEBUG1 field descriptions (continued) Field Description 0x03 REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. 0x04 XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. 0x05 REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. 0x06 REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. 0x07 PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. 0x08 READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. 0x09 READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. 0x0C WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0D READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0E CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.40 AHB to APBX DMA Channel 4 Debug Information (HW_APBX_CH4_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 4. This register allows debug visibility of the APBX DMA Channel 4. Address: 8002_4000h base + 320h offset = 8002_4320h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 590 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH4_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.41 APBX DMA Channel 5 Current Command Address Register (HW_APBX_CH5_CURCMDAR) The APBX DMA Channel 5 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 5 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8002_4000h base + 330h offset = 8002_4330h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH5_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for channel 5. 7.5.42 APBX DMA Channel 5 Next Command Address Register (HW_APBX_CH5_NXTCMDAR) The APBX DMA Channel 5 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 5 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 5 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 591 Programmable Registers Address: 8002_4000h base + 340h offset = 8002_4340h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH5_NXTCMDAR field descriptions Field Description CMD_ADDR Pointer to next command structure for channel 5. 7.5.43 APBX DMA Channel 5 Command Register (HW_APBX_CH5_CMD) The APBX DMA Channel 5 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 350h offset = 8002_4350h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 592 Freescale Semiconductor, Inc. 12 11 10 CMDWORDS R 9 8 RSVD1 7 6 0 0 5 4 RSVD0 3 2 CHAIN 13 IRQONCMPLT 14 SEMAPHORE 15 Bit WAIT4ENDCMD Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH5_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-8 RSVD1 Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the SAIF1 register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the SAIF1. Zero means transfer NO command words Reserved, always set to zero. 7 A value of one indicates that the channel will wait for the end of command signal to be sent from the WAIT4ENDCMD APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH5_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 593 Programmable Registers HW_APBX_CH5_CMD field descriptions (continued) Field Description NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x0 0x1 0x2 7.5.44 APBX DMA Channel 5 Buffer Address Register (HW_APBX_CH5_BAR) The APBX DMA Channel 5 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 360h offset = 8002_4360h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH5_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. 7.5.45 APBX DMA Channel 5 Semaphore Register (HW_APBX_CH5_SEMA) The APBX DMA Channel 5 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 594 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 370h offset = 8002_4370h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH5_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.46 AHB to APBX DMA Channel 5 Debug Information (HW_APBX_CH5_DEBUG1) This register gives debug visibility into the APBX DMA Channel 5 state machine and controls. This register allows debug visibility of the APBX DMA Channel 5. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 595 Programmable Registers Address: 8002_4000h base + 380h offset = 8002_4380h 23 22 21 20 19 18 17 16 WR_FIFO_FULL 24 WR_FIFO_EMPTY 25 RD_FIFO_FULL 26 RD_FIFO_EMPTY 27 NEXTCMDADDRVALID 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH5_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 596 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH5_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 5 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x15 IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 597 Programmable Registers HW_APBX_CH5_DEBUG1 field descriptions (continued) Field Description 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.47 AHB to APBX DMA Channel 5 Debug Information (HW_APBX_CH5_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 5. This register allows debug visibility of the APBX DMA Channel 5. Address: 8002_4000h base + 390h offset = 8002_4390h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH5_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.48 APBX DMA Channel 6 Current Command Address Register (HW_APBX_CH6_CURCMDAR) The APBX DMA Channel 6 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 6 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 598 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 3A0h offset = 8002_43A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH6_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for channel 6. 7.5.49 APBX DMA Channel 6 Next Command Address Register (HW_APBX_CH6_NXTCMDAR) The APBX DMA Channel 6 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 6 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 6 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8002_4000h base + 3B0h offset = 8002_43B0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH6_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for channel 6. 7.5.50 APBX DMA Channel 6 Command Register (HW_APBX_CH6_CMD) The APBX DMA Channel 6 command register specifies the cycle to perform for the current command chain item. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 599 Programmable Registers The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 3C0h offset = 8002_43C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XFER_COUNT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAIT4ENDCMD SEMAPHORE IRQONCMPLT CHAIN Bit 0 HALTONTERMINATE Reset TERMINATEFLUSH W 0 0 0 0 0 0 CMDWORDS R RSVD1 RSVD0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 600 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH6_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-10 RSVD1 9 TERMINATEFLUSH Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the I2C0 device. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the I2C0 device. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will flush out any remainder data in DMA FIFO when termination occurs. Only appliese for write DMA operation. 8 HALTONTERMINATE A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. 7 WAIT4ENDCMD A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH6_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 7.5.51 APBX DMA Channel 6 Buffer Address Register (HW_APBX_CH6_BAR) The APBX DMA Channel 6 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 601 Programmable Registers This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 3D0h offset = 8002_43D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH6_BAR field descriptions Field Description ADDRESS Address of system memory buffer to be read or written over the AHB bus. 7.5.52 APBX DMA Channel 6 Semaphore Register (HW_APBX_CH6_SEMA) The APBX DMA Channel 6 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8002_4000h base + 3E0h offset = 8002_43E0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH6_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 602 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH6_SEMA field descriptions (continued) Field Description reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.53 AHB to APBX DMA Channel 6 Debug Information (HW_APBX_CH6_DEBUG1) This register gives debug visibility into the APBX DMA Channel 6 state machine and controls. This register allows debug visibility of the APBX DMA Channel 6. 0 0 25 RSVD2 24 23 22 21 20 WR_FIFO_FULL 0 26 WR_FIFO_EMPTY END 0 27 RD_FIFO_FULL 28 RD_FIFO_EMPTY 29 NEXTCMDADDRVALID 30 KICK R 31 BURST Bit REQ Address: 8002_4000h base + 3F0h offset = 8002_43F0h 0 1 0 1 0 19 18 17 16 RSVD1 W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 603 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 RSVD1 R 3 2 1 0 STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH6_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 6 state machine state. 0x00 IDLE -- This is the idle state of the DMA state machine. 0x01 REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. 0x02 REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 604 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH6_DEBUG1 field descriptions (continued) Field Description 0x03 REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. 0x04 XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. 0x05 REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. 0x06 REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. 0x07 PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. 0x08 READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. 0x09 READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. 0x0C WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0D READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0E CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.54 AHB to APBX DMA Channel 6 Debug Information (HW_APBX_CH6_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 6. This register allows debug visibility of the APBX DMA Channel 6. Address: 8002_4000h base + 400h offset = 8002_4400h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 605 Programmable Registers HW_APBX_CH6_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.55 APBX DMA Channel 7 Current Command Address Register (HW_APBX_CH7_CURCMDAR) The APBX DMA Channel 7 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 7 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8002_4000h base + 410h offset = 8002_4410h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH7_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for channel 7. 7.5.56 APBX DMA Channel 7 Next Command Address Register (HW_APBX_CH7_NXTCMDAR) The APBX DMA Channel 7 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 7 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 7 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 606 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 420h offset = 8002_4420h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH7_NXTCMDAR field descriptions Field Description CMD_ADDR Pointer to next command structure for channel 7. 7.5.57 APBX DMA Channel 7 Command Register (HW_APBX_CH7_CMD) The APBX DMA Channel 7 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 430h offset = 8002_4430h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 607 10 RSVD1 9 8 7 6 0 0 0 0 5 4 RSVD0 3 2 CHAIN CMDWORDS R 11 IRQONCMPLT 12 SEMAPHORE 13 WAIT4ENDCMD 14 HALTONTERMINATE 15 Bit TERMINATEFLUSH Programmable Registers 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH7_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-10 RSVD1 9 TERMINATEFLUSH Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in I2C1 device. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the I2C1 device. Zero means transfer NO command words Reserved, always set to zero. A value of one indicates that the channel will flush out any remainder data in DMA FIFO when termination occurs. Only appliese for write DMA operation. 8 HALTONTERMINATE A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. 7 WAIT4ENDCMD A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 608 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH7_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH7_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 7.5.58 APBX DMA Channel 7 Buffer Address Register (HW_APBX_CH7_BAR) The APBX DMA Channel 7 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 440h offset = 8002_4440h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH7_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 609 Programmable Registers 7.5.59 APBX DMA Channel 7 Semaphore Register (HW_APBX_CH7_SEMA) The APBX DMA Channel 7 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8002_4000h base + 450h offset = 8002_4450h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH7_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.60 AHB to APBX DMA Channel 7 Debug Information (HW_APBX_CH7_DEBUG1) This register gives debug visibility into the APBX DMA Channel 7 state machine and controls. This register allows debug visibility of the APBX DMA Channel 7. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 610 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 460h offset = 8002_4460h 23 22 21 20 19 18 17 16 WR_FIFO_FULL 24 WR_FIFO_EMPTY 25 RD_FIFO_FULL 26 RD_FIFO_EMPTY 27 NEXTCMDADDRVALID 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH7_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 611 Programmable Registers HW_APBX_CH7_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 7 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x15 IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 612 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH7_DEBUG1 field descriptions (continued) Field Description 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.61 AHB to APBX DMA Channel 7 Debug Information (HW_APBX_CH7_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 7. This register allows debug visibility of the APBX DMA Channel 7. Address: 8002_4000h base + 470h offset = 8002_4470h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH7_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.62 APBX DMA Channel 8 Current Command Address Register (HW_APBX_CH8_CURCMDAR) The APBX DMA Channel 8 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 8 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 613 Programmable Registers Address: 8002_4000h base + 480h offset = 8002_4480h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH8_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for Channel 8. 7.5.63 APBX DMA Channel 8 Next Command Address Register (HW_APBX_CH8_NXTCMDAR) The APBX DMA Channel 8 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 8 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 8 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8002_4000h base + 490h offset = 8002_4490h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH8_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for Channel 8. 7.5.64 APBX DMA Channel 8 Command Register (HW_APBX_CH8_CMD) The APBX DMA Channel 8 command register specifies the cycle to perform for the current command chain item. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 614 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 4A0h offset = 8002_44A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XFER_COUNT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAIT4ENDCMD SEMAPHORE IRQONCMPLT CHAIN Bit 0 HALTONTERMINATE Reset TERMINATEFLUSH W 0 0 0 0 0 0 CMDWORDS R RSVD1 RSVD0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 615 Programmable Registers HW_APBX_CH8_CMD field descriptions Field Description 31-16 XFER_COUNT This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART4 device HW_UARTAPP_DATA. A value of 0 indicates a 64 KBytes transfer. 15-12 CMDWORDS This field indicates the number of command words to send to the UART0, starting with the base PIO address of the UART0 (HW_UARTAPP_CTRL0). Zero means transfer NO command words 11-10 RSVD1 9 TERMINATEFLUSH Reserved, always set to zero. A value of one indicates that the channel will flush out any remainder data in DMA FIFO when termination occurs. Only appliese for write DMA operation. 8 HALTONTERMINATE A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. 7 WAIT4ENDCMD A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH8_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 7.5.65 APBX DMA Channel 8 Buffer Address Register (HW_APBX_CH8_BAR) The APBX DMA Channel 8 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 616 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 4B0h offset = 8002_44B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH8_BAR field descriptions Field Description ADDRESS Address of system memory buffer to be read or written over the AHB bus. 7.5.66 APBX DMA Channel 8 Semaphore Register (HW_APBX_CH8_SEMA) The APBX DMA Channel 8 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8002_4000h base + 4C0h offset = 8002_44C0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH8_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 617 Programmable Registers HW_APBX_CH8_SEMA field descriptions (continued) Field Description reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.67 AHB to APBX DMA Channel 8 Debug Information (HW_APBX_CH8_DEBUG1) This register gives debug visibility into the APBX DMA Channel 8 state machine and controls. This register allows debug visibility of the APBX DMA Channel 8. 0 0 25 RSVD2 24 23 22 21 20 WR_FIFO_FULL 0 26 WR_FIFO_EMPTY END 0 27 RD_FIFO_FULL 28 RD_FIFO_EMPTY 29 NEXTCMDADDRVALID 30 KICK R 31 BURST Bit REQ Address: 8002_4000h base + 4D0h offset = 8002_44D0h 0 1 0 1 0 19 18 17 16 RSVD1 W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 618 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 RSVD1 R 3 2 1 0 STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH8_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 8 state machine state. 0x00 IDLE -- This is the idle state of the DMA state machine. 0x01 REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. 0x02 REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 619 Programmable Registers HW_APBX_CH8_DEBUG1 field descriptions (continued) Field Description 0x03 REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. 0x04 XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. 0x05 REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. 0x06 REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. 0x07 PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. 0x08 READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. 0x09 READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. 0x0C WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0D READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0E CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.68 AHB to APBX DMA Channel 8 Debug Information (HW_APBX_CH8_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 8. This register allows debug visibility of the APBX DMA Channel 8. Address: 8002_4000h base + 4E0h offset = 8002_44E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 620 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH8_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.69 APBX DMA Channel 9 Current Command Address Register (HW_APBX_CH9_CURCMDAR) The APBX DMA Channel 9 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 9 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8002_4000h base + 4F0h offset = 8002_44F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH9_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for Channel 9. 7.5.70 APBX DMA Channel 9 Next Command Address Register (HW_APBX_CH9_NXTCMDAR) The APBX DMA Channel 9 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 9 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 9 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 621 Programmable Registers Address: 8002_4000h base + 500h offset = 8002_4500h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH9_NXTCMDAR field descriptions Field Description CMD_ADDR Pointer to next command structure for Channel 9. 7.5.71 APBX DMA Channel 9 Command Register (HW_APBX_CH9_CMD) The APBX DMA Channel 9 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 510h offset = 8002_4510h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 622 Freescale Semiconductor, Inc. 10 RSVD1 9 8 7 6 0 0 0 0 5 4 RSVD0 3 2 CHAIN CMDWORDS R 11 IRQONCMPLT 12 SEMAPHORE 13 WAIT4ENDCMD 14 HALTONTERMINATE 15 Bit TERMINATEFLUSH Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH9_CMD field descriptions Field Description 31-16 XFER_COUNT This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART0 device HW_UARTAPP_DATA. A value of 0 indicates a 64 KBytes transfer. 15-12 CMDWORDS This field indicates the number of command words to send to the UART0, starting with the base PIO address of the UART0 (HW_UARTAPP_CTRL1). Zero means transfer NO command words 11-10 RSVD1 9 TERMINATEFLUSH Reserved, always set to zero. A value of one indicates that the channel will flush out any remainder data in DMA FIFO when termination occurs. Only appliese for write DMA operation. 8 HALTONTERMINATE A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. 7 WAIT4ENDCMD A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 623 Programmable Registers HW_APBX_CH9_CMD field descriptions (continued) Field Description 2 CHAIN A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH9_CMDAR to find the next command. COMMAND This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 7.5.72 APBX DMA Channel 9 Buffer Address Register (HW_APBX_CH9_BAR) The APBX DMA Channel 9 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 520h offset = 8002_4520h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH9_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 624 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 7.5.73 APBX DMA Channel 9 Semaphore Register (HW_APBX_CH9_SEMA) The APBX DMA Channel 9 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8002_4000h base + 530h offset = 8002_4530h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH9_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.74 AHB to APBX DMA Channel 9 Debug Information (HW_APBX_CH9_DEBUG1) This register gives debug visibility into the APBX DMA Channel 9 state machine and controls. This register allows debug visibility of the APBX DMA Channel 9. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 625 Programmable Registers Address: 8002_4000h base + 540h offset = 8002_4540h 23 22 21 20 19 18 17 16 WR_FIFO_FULL 24 WR_FIFO_EMPTY 25 RD_FIFO_FULL 26 RD_FIFO_EMPTY 27 NEXTCMDADDRVALID 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH9_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 626 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH9_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 9 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x15 IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 627 Programmable Registers HW_APBX_CH9_DEBUG1 field descriptions (continued) Field Description 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.75 AHB to APBX DMA Channel 9 Debug Information (HW_APBX_CH9_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 9. This register allows debug visibility of the APBX DMA Channel 9. Address: 8002_4000h base + 550h offset = 8002_4550h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH9_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.76 APBX DMA Channel 10 Current Command Address Register (HW_APBX_CH10_CURCMDAR) The APBX DMA Channel 10 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 10 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 628 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 560h offset = 8002_4560h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH10_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for Channel 10. 7.5.77 APBX DMA Channel 10 Next Command Address Register (HW_APBX_CH10_NXTCMDAR) The APBX DMA Channel 10 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 10 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 10 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8002_4000h base + 570h offset = 8002_4570h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH10_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for Channel 10. 7.5.78 APBX DMA Channel 10 Command Register (HW_APBX_CH10_CMD) The APBX DMA Channel 10 command register specifies the cycle to perform for the current command chain item. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 629 Programmable Registers The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 580h offset = 8002_4580h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XFER_COUNT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAIT4ENDCMD SEMAPHORE IRQONCMPLT CHAIN Bit 0 HALTONTERMINATE Reset TERMINATEFLUSH W 0 0 0 0 0 0 CMDWORDS R RSVD1 RSVD0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 630 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH10_CMD field descriptions Field Description 31-16 XFER_COUNT This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART1 device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. 15-12 CMDWORDS This field indicates the number of command words to send to the UART1, starting with the base PIO address of the UART1 (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words 11-10 RSVD1 9 TERMINATEFLUSH Reserved, always set to zero. A value of one indicates that the channel will flush out any remainder data in DMA FIFO when termination occurs. Only appliese for write DMA operation. 8 HALTONTERMINATE A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. 7 WAIT4ENDCMD A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH10_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 7.5.79 APBX DMA Channel 10 Buffer Address Register (HW_APBX_CH10_BAR) The APBX DMA Channel 10 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 631 Programmable Registers This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 590h offset = 8002_4590h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH10_BAR field descriptions Field Description ADDRESS Address of system memory buffer to be read or written over the AHB bus. 7.5.80 APBX DMA Channel 10 Semaphore Register (HW_APBX_CH10_SEMA) The APBX DMA Channel 10 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8002_4000h base + 5A0h offset = 8002_45A0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH10_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 632 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH10_SEMA field descriptions (continued) Field Description reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.81 AHB to APBX DMA Channel 10 Debug Information (HW_APBX_CH10_DEBUG1) This register gives debug visibility into the APBX DMA Channel 10 state machine and controls. This register allows debug visibility of the APBX DMA Channel 10. 0 0 25 RSVD2 24 23 22 21 20 WR_FIFO_FULL 0 26 WR_FIFO_EMPTY END 0 27 RD_FIFO_FULL 28 RD_FIFO_EMPTY 29 NEXTCMDADDRVALID 30 KICK R 31 BURST Bit REQ Address: 8002_4000h base + 5B0h offset = 8002_45B0h 0 1 0 1 0 19 18 17 16 RSVD1 W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 633 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 RSVD1 R 3 2 1 0 STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH10_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 10 state machine state. 0x00 IDLE -- This is the idle state of the DMA state machine. 0x01 REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. 0x02 REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 634 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH10_DEBUG1 field descriptions (continued) Field Description 0x03 REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. 0x04 XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. 0x05 REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. 0x06 REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. 0x07 PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. 0x08 READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. 0x09 READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. 0x0C WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0D READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0E CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.82 AHB to APBX DMA Channel 10 Debug Information (HW_APBX_CH10_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 10. This register allows debug visibility of the APBX DMA Channel 10. Address: 8002_4000h base + 5C0h offset = 8002_45C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 635 Programmable Registers HW_APBX_CH10_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.83 APBX DMA Channel 11 Current Command Address Register (HW_APBX_CH11_CURCMDAR) The APBX DMA Channel 11 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 11 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8002_4000h base + 5D0h offset = 8002_45D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH11_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for Channel 11. 7.5.84 APBX DMA Channel 11 Next Command Address Register (HW_APBX_CH11_NXTCMDAR) The APBX DMA Channel 11 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 11 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 11 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 636 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 5E0h offset = 8002_45E0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH11_NXTCMDAR field descriptions Field Description CMD_ADDR Pointer to next command structure for Channel 11. 7.5.85 APBX DMA Channel 11 Command Register (HW_APBX_CH11_CMD) The APBX DMA Channel 11 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 5F0h offset = 8002_45F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 637 12 11 10 CMDWORDS R 9 8 RSVD1 7 6 0 0 5 4 RSVD0 3 2 CHAIN 13 IRQONCMPLT 14 SEMAPHORE 15 Bit WAIT4ENDCMD Programmable Registers 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH11_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-8 RSVD1 Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART1 device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART1, starting with the base PIO address of the UART1 (HW_UARTAPP_CTRL1) and increment from there. Zero means transfer NO command words Reserved, always set to zero. 7 A value of one indicates that the channel will wait for the end of command signal to be sent from the WAIT4ENDCMD APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH11_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 638 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH11_CMD field descriptions (continued) Field Description NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x0 0x1 0x2 7.5.86 APBX DMA Channel 11 Buffer Address Register (HW_APBX_CH11_BAR) The APBX DMA Channel 11 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 600h offset = 8002_4600h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH11_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. 7.5.87 APBX DMA Channel 11 Semaphore Register (HW_APBX_CH11_SEMA) The APBX DMA Channel 11 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 639 Programmable Registers Address: 8002_4000h base + 610h offset = 8002_4610h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH11_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.88 AHB to APBX DMA Channel 11 Debug Information (HW_APBX_CH11_DEBUG1) This register gives debug visibility into the APBX DMA Channel 11 state machine and controls. This register allows debug visibility of the APBX DMA Channel 11. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 640 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 620h offset = 8002_4620h 23 22 21 20 19 18 17 16 WR_FIFO_FULL 24 WR_FIFO_EMPTY 25 RD_FIFO_FULL 26 RD_FIFO_EMPTY 27 NEXTCMDADDRVALID 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH11_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 641 Programmable Registers HW_APBX_CH11_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 11 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x15 IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 642 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH11_DEBUG1 field descriptions (continued) Field Description 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.89 AHB to APBX DMA Channel 11 Debug Information (HW_APBX_CH11_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 11. This register allows debug visibility of the APBX DMA Channel 11. Address: 8002_4000h base + 630h offset = 8002_4630h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH11_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.90 APBX DMA Channel 12 Current Command Address Register (HW_APBX_CH12_CURCMDAR) The APBX DMA Channel 12 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 12 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 643 Programmable Registers Address: 8002_4000h base + 640h offset = 8002_4640h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH12_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for Channel 12. 7.5.91 APBX DMA Channel 12 Next Command Address Register (HW_APBX_CH12_NXTCMDAR) The APBX DMA Channel 12 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 12 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 12 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8002_4000h base + 650h offset = 8002_4650h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH12_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for Channel 12. 7.5.92 APBX DMA Channel 12 Command Register (HW_APBX_CH12_CMD) The APBX DMA Channel 12 command register specifies the cycle to perform for the current command chain item. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 644 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 660h offset = 8002_4660h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XFER_COUNT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAIT4ENDCMD SEMAPHORE IRQONCMPLT CHAIN Bit 0 HALTONTERMINATE Reset TERMINATEFLUSH W 0 0 0 0 0 0 CMDWORDS R RSVD1 RSVD0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 645 Programmable Registers HW_APBX_CH12_CMD field descriptions Field Description 31-16 XFER_COUNT This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART2 device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. 15-12 CMDWORDS This field indicates the number of command words to send to the UART2, starting with the base PIO address of the UART2 (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words 11-10 RSVD1 9 TERMINATEFLUSH Reserved, always set to zero. A value of one indicates that the channel will flush out any remainder data in DMA FIFO when termination occurs. Only appliese for write DMA operation. 8 HALTONTERMINATE A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. 7 WAIT4ENDCMD A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH12_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 7.5.93 APBX DMA Channel 12 Buffer Address Register (HW_APBX_CH12_BAR) The APBX DMA Channel 12 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 646 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 670h offset = 8002_4670h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH12_BAR field descriptions Field Description ADDRESS Address of system memory buffer to be read or written over the AHB bus. 7.5.94 APBX DMA Channel 12 Semaphore Register (HW_APBX_CH12_SEMA) The APBX DMA Channel 12 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8002_4000h base + 680h offset = 8002_4680h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH12_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 647 Programmable Registers HW_APBX_CH12_SEMA field descriptions (continued) Field Description reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.95 AHB to APBX DMA Channel 12 Debug Information (HW_APBX_CH12_DEBUG1) This register gives debug visibility into the APBX DMA Channel 12 state machine and controls. This register allows debug visibility of the APBX DMA Channel 12. 0 0 25 RSVD2 24 23 22 21 20 WR_FIFO_FULL 0 26 WR_FIFO_EMPTY END 0 27 RD_FIFO_FULL 28 RD_FIFO_EMPTY 29 NEXTCMDADDRVALID 30 KICK R 31 BURST Bit REQ Address: 8002_4000h base + 690h offset = 8002_4690h 0 1 0 1 0 19 18 17 16 RSVD1 W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 648 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 RSVD1 R 3 2 1 0 STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH12_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 12 state machine state. 0x00 IDLE -- This is the idle state of the DMA state machine. 0x01 REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. 0x02 REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 649 Programmable Registers HW_APBX_CH12_DEBUG1 field descriptions (continued) Field Description 0x03 REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. 0x04 XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. 0x05 REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. 0x06 REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. 0x07 PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. 0x08 READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. 0x09 READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. 0x0C WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0D READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0E CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.96 AHB to APBX DMA Channel 12 Debug Information (HW_APBX_CH12_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 12. This register allows debug visibility of the APBX DMA Channel 12. Address: 8002_4000h base + 6A0h offset = 8002_46A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 650 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH12_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.97 APBX DMA Channel 13 Current Command Address Register (HW_APBX_CH13_CURCMDAR) The APBX DMA Channel 13 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 13 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8002_4000h base + 6B0h offset = 8002_46B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH13_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for Channel 13. 7.5.98 APBX DMA Channel 13 Next Command Address Register (HW_APBX_CH13_NXTCMDAR) The APBX DMA Channel 13 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 13 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 13 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 651 Programmable Registers Address: 8002_4000h base + 6C0h offset = 8002_46C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH13_NXTCMDAR field descriptions Field Description CMD_ADDR Pointer to next command structure for Channel 13. 7.5.99 APBX DMA Channel 13 Command Register (HW_APBX_CH13_CMD) The APBX DMA Channel 13 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 6D0h offset = 8002_46D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 652 Freescale Semiconductor, Inc. 12 11 10 CMDWORDS R 9 8 RSVD1 7 6 0 0 5 4 RSVD0 3 2 CHAIN 13 IRQONCMPLT 14 SEMAPHORE 15 Bit WAIT4ENDCMD Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH13_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-8 RSVD1 Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART1 device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART2, starting with the base PIO address of the UART2 (HW_UARTAPP_CTRL1) and increment from there. Zero means transfer NO command words Reserved, always set to zero. 7 A value of one indicates that the channel will wait for the end of command signal to be sent from the WAIT4ENDCMD APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH13_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 653 Programmable Registers HW_APBX_CH13_CMD field descriptions (continued) Field Description NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x0 0x1 0x2 7.5.100 APBX DMA Channel 13 Buffer Address Register (HW_APBX_CH13_BAR) The APBX DMA Channel 13 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 6E0h offset = 8002_46E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH13_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. 7.5.101 APBX DMA Channel 13 Semaphore Register (HW_APBX_CH13_SEMA) The APBX DMA Channel 13 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 654 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 6F0h offset = 8002_46F0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH13_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.102 AHB to APBX DMA Channel 13 Debug Information (HW_APBX_CH13_DEBUG1) This register gives debug visibility into the APBX DMA Channel 13 state machine and controls. This register allows debug visibility of the APBX DMA Channel 13. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 655 Programmable Registers Address: 8002_4000h base + 700h offset = 8002_4700h 23 22 21 20 19 18 17 16 WR_FIFO_FULL 24 WR_FIFO_EMPTY 25 RD_FIFO_FULL 26 RD_FIFO_EMPTY 27 NEXTCMDADDRVALID 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH13_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 656 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH13_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 13 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x15 IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 657 Programmable Registers HW_APBX_CH13_DEBUG1 field descriptions (continued) Field Description 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.103 AHB to APBX DMA Channel 13 Debug Information (HW_APBX_CH13_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 13. This register allows debug visibility of the APBX DMA Channel 13. Address: 8002_4000h base + 710h offset = 8002_4710h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH13_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.104 APBX DMA Channel 14 Current Command Address Register (HW_APBX_CH14_CURCMDAR) The APBX DMA Channel 14 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 14 is controlled by a variable sized command structure. This register points to the command structure currently being executed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 658 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 720h offset = 8002_4720h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH14_CURCMDAR field descriptions Field Description CMD_ADDR Pointer to command structure currently being processed for Channel 14. 7.5.105 APBX DMA Channel 14 Next Command Address Register (HW_APBX_CH14_NXTCMDAR) The APBX DMA Channel 14 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 14 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 14 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. Address: 8002_4000h base + 730h offset = 8002_4730h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH14_NXTCMDAR field descriptions Field CMD_ADDR Description Pointer to next command structure for Channel 14. 7.5.106 APBX DMA Channel 14 Command Register (HW_APBX_CH14_CMD) The APBX DMA Channel 14 command register specifies the cycle to perform for the current command chain item. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 659 Programmable Registers The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 740h offset = 8002_4740h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XFER_COUNT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAIT4ENDCMD SEMAPHORE IRQONCMPLT CHAIN Bit 0 HALTONTERMINATE Reset TERMINATEFLUSH W 0 0 0 0 0 0 CMDWORDS R RSVD1 RSVD0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 660 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH14_CMD field descriptions Field Description 31-16 XFER_COUNT This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART3 device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. 15-12 CMDWORDS This field indicates the number of command words to send to the UART3, starting with the base PIO address of the UART3 (HW_UARTAPP_CTRL0) and increment from there. Zero means transfer NO command words 11-10 RSVD1 9 TERMINATEFLUSH Reserved, always set to zero. A value of one indicates that the channel will flush out any remainder data in DMA FIFO when termination occurs. Only appliese for write DMA operation. 8 HALTONTERMINATE A value of one indicates that the channel will immeditately terminate the current descriptor and halt the DMA channel if a terminate signal is set. A value of 0 will still cause an immediate terminate of the channel if the terminate signal is set, but the channel will continue as if the count had been exhausted, meaning it will honor IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD. 7 WAIT4ENDCMD A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH14_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved 0x0 NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. 0x1 DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. 0x2 DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 7.5.107 APBX DMA Channel 14 Buffer Address Register (HW_APBX_CH14_BAR) The APBX DMA Channel 14 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 661 Programmable Registers This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 750h offset = 8002_4750h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH14_BAR field descriptions Field Description ADDRESS Address of system memory buffer to be read or written over the AHB bus. 7.5.108 APBX DMA Channel 14 Semaphore Register (HW_APBX_CH14_SEMA) The APBX DMA Channel 14 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. Address: 8002_4000h base + 760h offset = 8002_4760h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH14_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 662 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH14_SEMA field descriptions (continued) Field Description reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.109 AHB to APBX DMA Channel 14 Debug Information (HW_APBX_CH14_DEBUG1) This register gives debug visibility into the APBX DMA Channel 14 state machine and controls. This register allows debug visibility of the APBX DMA Channel 14. 0 0 25 RSVD2 24 23 22 21 20 WR_FIFO_FULL 0 26 WR_FIFO_EMPTY END 0 27 RD_FIFO_FULL 28 RD_FIFO_EMPTY 29 NEXTCMDADDRVALID 30 KICK R 31 BURST Bit REQ Address: 8002_4000h base + 770h offset = 8002_4770h 0 1 0 1 0 19 18 17 16 RSVD1 W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 663 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 RSVD1 R 3 2 1 0 STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH14_DEBUG1 field descriptions Field Description 31 REQ This bit reflects the current state of the DMA Request Signal from the APB device 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 14 state machine state. 0x00 IDLE -- This is the idle state of the DMA state machine. 0x01 REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. 0x02 REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 664 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH14_DEBUG1 field descriptions (continued) Field Description 0x03 REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. 0x04 XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. 0x05 REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. 0x06 REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. 0x07 PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. 0x08 READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. 0x09 READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. 0x0C WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0D READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. 0x0E CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. 0x0F XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. 0x15 WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.110 AHB to APBX DMA Channel 14 Debug Information (HW_APBX_CH14_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 14. This register allows debug visibility of the APBX DMA Channel 14. Address: 8002_4000h base + 780h offset = 8002_4780h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 665 Programmable Registers HW_APBX_CH14_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.111 APBX DMA Channel 15 Current Command Address Register (HW_APBX_CH15_CURCMDAR) The APBX DMA Channel 15 current command address register points to the multiword command that is currently being executed. Commands are threaded on the command address. APBX DMA Channel 15 is controlled by a variable sized command structure. This register points to the command structure currently being executed. Address: 8002_4000h base + 790h offset = 8002_4790h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH15_CURCMDAR field descriptions Field CMD_ADDR Description Pointer to command structure currently being processed for Channel 15. 7.5.112 APBX DMA Channel 15 Next Command Address Register (HW_APBX_CH15_NXTCMDAR) The APBX DMA Channel 15 next command address register points to the next multiword command to be executed. Commands are threaded on the command address. Set CHAIN to one to process command lists. APBX DMA Channel 15 is controlled by a variable sized command structure. Software loads this register with the address of the first command structure to process and increments the Channel 15 semaphore to start processing. This register points to the next command structure to be executed when the current command is completed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 666 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 7A0h offset = 8002_47A0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH15_NXTCMDAR field descriptions Field Description CMD_ADDR Pointer to next command structure for Channel 15. 7.5.113 APBX DMA Channel 15 Command Register (HW_APBX_CH15_CMD) The APBX DMA Channel 15 command register specifies the cycle to perform for the current command chain item. The command register controls the overall operation of each DMA command for this channel. It includes the number of bytes to transfer to or from the device, the number of APB PIO command words included with this command structure, whether to interrupt at command completion, whether to chain an additional command to the end of this one and whether this transfer is a read or write DMA transfer. Address: 8002_4000h base + 7B0h offset = 8002_47B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 XFER_COUNT R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 667 12 11 10 CMDWORDS R 9 8 RSVD1 7 6 0 0 5 4 RSVD0 3 2 CHAIN 13 IRQONCMPLT 14 SEMAPHORE 15 Bit WAIT4ENDCMD Programmable Registers 0 0 1 0 COMMAND W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH15_CMD field descriptions Field 31-16 XFER_COUNT 15-12 CMDWORDS 11-8 RSVD1 Description This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART3 device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer. This field indicates the number of command words to send to the UART3, starting with the base PIO address of the UART3 (HW_UARTAPP_CTRL1) and increment from there. Zero means transfer NO command words Reserved, always set to zero. 7 A value of one indicates that the channel will wait for the end of command signal to be sent from the WAIT4ENDCMD APBX device to the DMA before starting the next DMA command. 6 SEMAPHORE 5-4 RSVD0 3 IRQONCMPLT 2 CHAIN COMMAND A value of one indicates that the channel will decrement its semaphore at the completion of the current command structure. If the semaphore decrements to zero, then this channel stalls until software increments it again. Reserved, always set to zero. A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the current command, i.e. after the DMA transfer is complete. A value of one indicates that another command is chained onto the end of the current command structure. At the completion of the current command, this channel will follow the pointer in HW_APBX_CH15_CMDAR to find the next command. This bitfield indicates the type of current command: 00- NO DMA TRANSFER 01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master write). 10- read transfer 11- reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 668 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH15_CMD field descriptions (continued) Field Description NO_DMA_XFER -- Perform any requested PIO word transfers but terminate command before any DMA transfer. DMA_WRITE -- Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes. DMA_READ -- Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes. 0x0 0x1 0x2 7.5.114 APBX DMA Channel 15 Buffer Address Register (HW_APBX_CH15_BAR) The APBX DMA Channel 15 buffer address register contains a pointer to the data buffer for the transfer. For immediate forms, the data is taken from this register. This is a byte address which means transfers can start on any byte boundary. This register holds a pointer to the data buffer in system memory. After the command values have been read into the DMA controller and the device controlled by this channel, then the DMA transfer will begin, to or from the buffer pointed to by this register. Address: 8002_4000h base + 7C0h offset = 8002_47C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH15_BAR field descriptions Field ADDRESS Description Address of system memory buffer to be read or written over the AHB bus. 7.5.115 APBX DMA Channel 15 Semaphore Register (HW_APBX_CH15_SEMA) The APBX DMA Channel 15 semaphore register is used to synchronize between the CPU instruction stream and the DMA chain processing state. Each DMA channel has an 8 bit counting semaphore used to synchronize between the program stream and the DMA chain processing. DMA processing continues until the DMA attempts to decrement a semaphore which has already reached a value of zero. When the attempt is made, the DMA channel is stalled until software increments the semaphore count. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 669 Programmable Registers Address: 8002_4000h base + 7D0h offset = 8002_47D0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 PHORE 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INCREMENT_SEMA W Reset 6 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH15_SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 PHORE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT_ SEMA The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DMA hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DMA channel decrements the count on the same clock, then the count is incremented by a net one. 7.5.116 AHB to APBX DMA Channel 15 Debug Information (HW_APBX_CH15_DEBUG1) This register gives debug visibility into the APBX DMA Channel 15 state machine and controls. This register allows debug visibility of the APBX DMA Channel 15. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 670 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) Address: 8002_4000h base + 7E0h offset = 8002_47E0h 23 22 21 20 19 18 17 16 WR_FIFO_FULL 24 WR_FIFO_EMPTY 25 RD_FIFO_FULL 26 RD_FIFO_EMPTY 27 NEXTCMDADDRVALID 28 END 29 KICK 30 BURST R 31 REQ Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 RSVD1 W Reset Bit RSVD1 R STATEMACHINE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH15_DEBUG1 field descriptions Field 31 REQ Description This bit reflects the current state of the DMA Request Signal from the APB device Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 671 Programmable Registers HW_APBX_CH15_DEBUG1 field descriptions (continued) Field Description 30 BURST This bit reflects the current state of the DMA Burst Signal from the APB device 29 KICK This bit reflects the current state of the DMA Kick Signal sent to the APB Device 28 END This bit reflects the current state of the DMA End Command Signal sent from the APB Device 27-25 RSVD2 Reserved 24 NEXTCMDADDRVALID 23 RD_FIFO_EMPTY 22 RD_FIFO_FULL 21 WR_FIFO_EMPTY 20 WR_FIFO_FULL 19-5 RSVD1 STATEMACHINE This bit reflects the internal bit which indicates whether the channel's next command address is valid. This bit reflects the current state of the DMA Channel's Read FIFO Empty signal. This bit reflects the current state of the DMA Channel's Read FIFO Full signal. This bit reflects the current state of the DMA Channel's Write FIFO Empty signal. This bit reflects the current state of the DMA Channel's Write FIFO Full signal. Reserved PIO Display of the DMA Channel 15 state machine state. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0C 0x0D 0x0E 0x0F 0x15 IDLE -- This is the idle state of the DMA state machine. REQ_CMD1 -- State in which the DMA is waiting to receive the first word of a command. REQ_CMD3 -- State in which the DMA is waiting to receive the third word of a command. REQ_CMD2 -- State in which the DMA is waiting to receive the second word of a command. XFER_DECODE -- The state machine processes the descriptor command field in this state and branches accordingly. REQ_WAIT -- The state machine waits in this state for the PIO APB cycles to complete. REQ_CMD4 -- State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1. PIO_REQ -- This state determines whether another PIO cycle needs to occur before starting DMA transfers. READ_FLUSH -- During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB. READ_WAIT -- When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete. WRITE -- During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. READ_REQ -- During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel. CHECK_CHAIN -- Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly. XFER_COMPLETE -- The state machine goes to this state after the DMA transfers are complete, and determines what step to take next. WAIT_END -- When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 672 Freescale Semiconductor, Inc. Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA) HW_APBX_CH15_DEBUG1 field descriptions (continued) Field Description 0x1C WRITE_WAIT -- During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space. 0x1E CHECK_WAIT -- If the Chain bit is a 0, the state machine enters this state and effectively halts. 7.5.117 AHB to APBX DMA Channel 15 Debug Information (HW_APBX_CH15_DEBUG2) This register gives debug visibility for the APB and AHB byte counts for DMA Channel 15. This register allows debug visibility of the APBX DMA Channel 15. Address: 8002_4000h base + 7F0h offset = 8002_47F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 APB_BYTES R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 AHB_BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_APBX_CH15_DEBUG2 field descriptions Field Description 31-16 APB_BYTES This value reflects the current number of APB bytes remaining to be transfered in the current transfer. AHB_BYTES This value reflects the current number of AHB bytes remaining to be transfered in the current transfer. 7.5.118 APBX Bridge Version Register (HW_APBX_VERSION) This register always returns a known read value for debug purposes it indicates the version of the block. This register indicates the RTL version in use. EXAMPLE if (HW_APBX_VERSION.B.MAJOR != 1) Error(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 673 Programmable Registers Address: 8002_4000h base + 800h offset = 8002_4800h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 HW_APBX_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 674 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions 8.1 Pin Descriptions Overview This chapter provides various views of the pinout for the i.MX28. * Pin definitions for the 289-pin BGA are in Pin Definitions for 289-pin BGA * Pin sorted by functional groups are in Functional Pin Groups The pin tables in this chapter include columns with the headings MUX0, MUX1, and MUX2. These columns refer to the different functions that can be enabled for each individual pin by programming the pin control registers (HW_PINCTRL_MUXSELx). For example: * Enable the function listed in the "MUX0" column by programming the BANKx_PINx bit field to 00. * Enable the function listed in the "MUX1" column by programming the BANKx_PINx bit field to 01. * Enable the function listed in the "MUX2" column by programming the BANKx_PINx bit field to 10. See Pin Control and GPIO Overview for more information. Table 8-1 lists the abbreviations used in the pin tables in this chapter. Table 8-1. Nomenclature for Pin Tables TYPE DESCRIPTION MODULE DESCRIPTION A Analog pin ADC ADC analog pins D Digital pin CLOCK Clock pins Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 675 Pin Definitions for 289-pin BGA Table 8-1. Nomenclature for Pin Tables (continued) TYPE DESCRIPTION MODULE DESCRIPTION E EMI pin DCDC DC-DC Converter pins P Power pin EMI External Memory Interface pins I Input pin ETM Embedded Trace Macrocell O Output pin GPIO General-Purpose Input/Output pins I/O Input/output pin GPMI General-Purpose Media Interface (NAND/ATA/ CMOS) pins HP Headphone pins I2C I2C pins LCDIF LCD Interface pins LRADC Low-Resolution ADC/Touch-Screen pins POWER Power pins PWM Pulse Width Modulator pins RTC Real-Time Clock pins SSP Synchronous Serial Port pins SYSTEM System pins TIMER Timer/Rotary Encoder pins UART Either debug or application UART pins USB USB pins Note Almost all digital pins are powered down (that is, highimpedance) or configured as GPIO input at reset, until reprogrammed. The only exceptions are TEST PINS(TESTMODE, DEBUG, JTAG pins). These pins are always active. 8.2 Pin Definitions for 289-pin BGA This section includes the following pin information for the 289-pin BGA package: * Table 8-2 * Figure 8-1 Table 8-2. Pin Definitions PIN NAME PIN GROUP AUART0_CTS J6 AUART TYP MUX0 E D AUART0_CTS MUX1 MUX2 AUART4_RX DUART_RX Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 676 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-2. Pin Definitions (continued) TYP MUX0 E PIN NAME PIN GROUP MUX1 MUX2 AUART0_RTS J7 AUART D AUART0_RTS AUART4_TX DUART_TX AUART0_RX G5 AUART D AUART0_RX I2C0_SCL DUART_CTS AUART0_TX H5 AUART D AUART0_TX I2C0_SDA DUART_RTS AUART1_CTS K5 AUART D AUART1_CTS USB0_OVERCURRENT TIMROT_ROTARYA AUART1_RTS J5 AUART D AUART1_RTS USB0_ID AUART1_RX L4 AUART D AUART1_RX SSP2_CARD_DETECT PWM_0 AUART1_TX K4 AUART D AUART1_TX SSP3_CARD_DETECT PWM_1 AUART2_CTS H6 AUART D AUART2_CTS I2C1_SCL SAIF1_BITCLK AUART2_RTS H7 AUART D AUART2_RTS I2C1_SDA SAIF1_LRCLK AUART2_RX F6 AUART D AUART2_RX SSP3_D1 SSP3_D4 AUART2_TX F5 AUART D AUART2_TX SSP3_D2 SSP3_D5 AUART3_CTS L6 AUART D AUART3_CTS CAN1_TX ENET0_1588_EVENT1 _OUT AUART3_RTS K6 AUART D AUART3_RTS CAN1_RX ENET0_1588_EVENT1 _IN AUART3_RX M5 AUART D AUART3_RX CAN0_TX ENET0_1588_EVENT0 _OUT AUART3_TX L5 AUART D AUART3_TX CAN0_RX ENET0_1588_EVENT0 _IN BATTERY A15 DCDC A DCDC_BATT B15 DCDC A DCDC_GND A17 DCDC A DCDC_LN1 B17 DCDC A DCDC_LP A16 DCDC A DCDC_VDDA B16 DCDC A DCDC_VDDD D17 DCDC A DCDC_VDDIO C17 DCDC A DEBUG B9 SYSTE M D EMI_A00 U15 EMI E EMI_ADDR0 EMI_A01 U12 EMI E EMI_ADDR1 EMI_A02 U14 EMI E EMI_ADDR2 EMI_A03 T11 EMI E EMI_ADDR3 EMI_A04 U10 EMI E EMI_ADDR4 EMI_A05 R11 EMI E EMI_ADDR5 EMI_A06 R9 EMI E EMI_ADDR6 EMI_A07 N11 EMI E EMI_ADDR7 EMI_A08 U9 EMI E EMI_ADDR8 EMI_A09 P10 EMI E EMI_ADDR9 EMI_A10 U13 EMI E EMI_ADDR10 TIMROT_ROTARYB Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 677 Pin Definitions for 289-pin BGA Table 8-2. Pin Definitions (continued) TYP MUX0 E PIN NAME PIN GROUP EMI_A11 T10 EMI E EMI_ADDR11 EMI_A12 U11 EMI E EMI_ADDR12 EMI_A13 T9 EMI E EMI_ADDR13 EMI_A14 N10 EMI E EMI_ADDR14 EMI_BA0 T16 EMI E EMI_BA0 EMI_BA1 T12 EMI E EMI_BA1 EMI_BA2 N12 EMI E EMI_BA2 EMI_CASN U16 EMI E EMI_CASN EMI_CE0N P12 EMI E EMI_CE0N EMI_CE1N P9 EMI E EMI_CE1N EMI_CKE T13 EMI E EMI_CKE EMI_CLK L17 EMI E EMI_CLK EMI_CLKN L16 EMI E EMI_D00 N16 EMI E EMI_DATA0 EMI_D01 M13 EMI E EMI_DATA1 EMI_D02 P15 EMI E EMI_DATA2 EMI_D03 N14 EMI E EMI_DATA3 EMI_D04 P13 EMI E EMI_DATA4 EMI_D05 P17 EMI E EMI_DATA5 EMI_D06 L14 EMI E EMI_DATA6 EMI_D07 M17 EMI E EMI_DATA7 EMI_D08 G16 EMI E EMI_DATA8 EMI_D09 H15 EMI E EMI_DATA9 EMI_D10 G14 EMI E EMI_DATA10 EMI_D11 J14 EMI E EMI_DATA11 EMI_D12 H13 EMI E EMI_DATA12 EMI_D13 H17 EMI E EMI_DATA13 EMI_D14 F13 EMI E EMI_DATA14 EMI_D15 F17 EMI E EMI_DATA15 EMI_DDR_OPEN K14 EMI E EMI_DDR_OPEN EMI_DDR_OPEN L15 _FB EMI E EMI_DDR_OPEN_FE EDBACK EMI_DQM0 M15 EMI E EMI_DQM0 EMI_DQM1 F15 EMI E EMI_DQM1 EMI_DQS0 K17 EMI E EMI_DQS0 EMI_DQS0N K16 EMI E EMI_DQS1 J17 EMI E EMI_DQS1N J16 EMI E EMI_ODT0 R17 EMI E MUX1 MUX2 EMI_DQS1 EMI_ODT0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 678 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-2. Pin Definitions (continued) TYP MUX0 E PIN NAME PIN GROUP MUX1 MUX2 EMI_ODT1 T17 EMI E EMI_ODT1 EMI_RASN R16 EMI E EMI_RASN EMI_VREF0 R14 EMI E EMI_VREF1 K13 EMI E EMI_WEN T15 EMI E EMI_WEN ENET0_COL J4 ENET D ENET0_COL ENET1_TX_EN ENET0_1588_EVENT3 _OUT ENET0_CRS J3 ENET D ENET0_CRS ENET1_RX_EN ENET0_1588_EVENT3 _IN ENET0_MDC G4 ENET D ENET0_MDC GPMI_CE4N SAIF0_SDATA1 ENET0_MDIO ENET0_RXD0 H4 ENET D ENET0_MDIO GPMI_CE5N SAIF0_SDATA2 H1 ENET D ENET0_RXD0 GPMI_CE7N SAIF1_SDATA2 ENET0_RXD1 H2 ENET D ENET0_RXD1 GPMI_READY4 ENET0_RXD2 J1 ENET D ENET0_RXD2 ENET1_RXD0 ENET0_1588_EVENT0 _OUT ENET0_RXD3 J2 ENET D ENET0_RXD3 ENET1_RXD1 ENET0_1588_EVENT0 _IN ENET0_RX_CLK F3 ENET D ENET0_RX_CLK ENET0_RX_ER ENET0_1588_EVENT2 _IN ENET0_RX_EN E4 ENET D ENET0_RX_EN GPMI_CE6N SAIF1_SDATA1 ENET0_TXD0 F1 ENET D ENET0_TXD0 GPMI_READY6 ENET0_TXD1 F2 ENET D ENET0_TXD1 GPMI_READY7 ENET0_TXD2 G1 ENET D ENET0_TXD2 ENET1_TXD0 ENET0_1588_EVENT1 _OUT ENET0_TXD3 G2 ENET D ENET0_TXD3 ENET1_TXD1 ENET0_1588_EVENT1 _IN ENET0_TX_CLK E3 ENET D ENET0_TX_CLK HSADC_TRIGGER ENET0_1588_EVENT2 _OUT ENET0_TX_EN F4 ENET D ENET0_TX_EN GPMI_READY5 ENET_CLK E2 ENET D CLKCTRL_ENET GPMI_ALE P6 GPMI D GPMI_ALE SSP3_D1 GPMI_CE0N N7 GPMI D GPMI_CE0N SSP3_D0 GPMI_CE1N N9 GPMI D GPMI_CE1N SSP3_D3 GPMI_CE2N M7 GPMI D GPMI_CE2N CAN1_TX ENET0_RX_ER GPMI_CE3N M9 GPMI D GPMI_CE3N CAN1_RX SAIF1_MCLK GPMI_CLE P7 GPMI D GPMI_CLE SSP3_D2 SSP3_D5 GPMI_D00 U8 GPMI D GPMI_D0 SSP1_D0 GPMI_D01 T8 GPMI D GPMI_D1 SSP1_D1 GPMI_D02 R8 GPMI D GPMI_D2 SSP1_D2 GPMI_D03 U7 GPMI D GPMI_D3 SSP1_D3 GPMI_D04 T7 GPMI D GPMI_D4 SSP1_D4 SSP3_D4 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 679 Pin Definitions for 289-pin BGA Table 8-2. Pin Definitions (continued) GROUP TYP MUX0 E PIN NAME PIN MUX1 MUX2 GPMI_D05 R7 GPMI D GPMI_D5 SSP1_D5 GPMI_D06 U6 GPMI D GPMI_D6 SSP1_D6 GPMI_D07 T6 GPMI D GPMI_D7 SSP1_D7 GPMI_RDN R6 GPMI D GPMI_RDN SSP3_SCK GPMI_RDY0 N6 GPMI D GPMI_READY0 SSP1_CARD_DETECT USB0_ID GPMI_RDY1 N8 GPMI D GPMI_READY1 SSP1_CMD GPMI_RDY2 M8 GPMI D GPMI_READY2 CAN0_TX ENET0_TX_ER GPMI_RDY3 L8 GPMI D GPMI_READY3 CAN0_RX HSADC_TRIGGER GPMI_RESETN L9 GPMI D GPMI_RESETN SSP3_CMD GPMI_WRN P8 GPMI D GPMI_WRN SSP1_SCK HSADC0 B14 HSADC A I2C0_SCL C7 I2C D I2C0_SCL TIMROT_ROTARYA DUART_RX I2C0_SDA D8 I2C D I2C0_SDA TIMROT_ROTARYB DUART_TX JTAG_RTCK E14 SYSTE M D JTAG_RTCK JTAG_TCK E11 SYSTE M D JTAG_TDI E12 SYSTE M D JTAG_TDO E13 SYSTE M D JTAG_TMS D12 SYSTE M D JTAG_TRST D14 SYSTE M D LCD_CS P5 LCD D LCD_CS LCD_D00 K2 LCD D LCD_D0 ETM_DA0 LCD_D01 K3 LCD D LCD_D1 ETM_DA1 LCD_D02 L2 LCD D LCD_D2 ETM_DA2 LCD_D03 L3 LCD D LCD_D3 ETM_DA8 ETM_DA3 LCD_D04 M2 LCD D LCD_D4 ETM_DA9 ETM_DA4 LCD_D05 M3 LCD D LCD_D5 ETM_DA5 LCD_D06 N2 LCD D LCD_D6 ETM_DA6 LCD_D07 P1 LCD D LCD_D7 ETM_DA7 LCD_D08 P2 LCD D LCD_D8 ETM_DA3 ETM_DA8 LCD_D09 P3 LCD D LCD_D9 ETM_DA4 ETM_DA9 LCD_D10 R1 LCD D LCD_D10 ETM_DA10 LCD_D11 R2 LCD D LCD_D11 ETM_DA11 LCD_D12 T1 LCD D LCD_D12 ETM_DA12 LCD_D13 T2 LCD D LCD_D13 ETM_DA13 LCD_ENABLE Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 680 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-2. Pin Definitions (continued) GROUP TYP MUX0 E PIN NAME PIN MUX1 MUX2 LCD_D14 U2 LCD D LCD_D14 ETM_DA14 LCD_D15 U3 LCD D LCD_D15 ETM_DA15 LCD_D16 T3 LCD D LCD_D16 ETM_DA7 LCD_D17 R3 LCD D LCD_D17 ETM_DA6 LCD_D18 U4 LCD D LCD_D18 ETM_DA5 LCD_D19 T4 LCD D LCD_D19 ETM_DA4 LCD_D20 R4 LCD D LCD_D20 ENET1_1588_EVENT2 ETM_DA3 _OUT LCD_D21 U5 LCD D LCD_D21 ENET1_1588_EVENT2 ETM_DA2 _IN LCD_D22 T5 LCD D LCD_D22 ENET1_1588_EVENT3 ETM_DA1 _OUT LCD_D23 R5 LCD D LCD_D23 ENET1_1588_EVENT3 ETM_DA0 _IN LCD_DOTCLK N1 LCD D LCD_DOTCLK SAIF1_MCLK ETM_TCLK LCD_ENABLE N5 LCD D LCD_ENABLE LCD_HSYNC M1 LCD D LCD_HSYNC SAIF1_SDATA1 ETM_TCTL LCD_RD_E P4 LCD D LCD_RD_E LCD_VSYNC ETM_TCTL LCD_RESET M6 LCD D LCD_RESET LCD_VSYNC LCD_RS M4 LCD D LCD_RS LCD_DOTCLK LCD_VSYNC L1 LCD D LCD_VSYNC SAIF1_SDATA0 LCD_WR_RWN K1 LCD D LCD_WR_RWN LCD_HSYNC ETM_TCLK LRADC0 C15 LRADC A LRADC1 C9 LRADC A LRADC2 C8 LRADC A LRADC3 D9 LRADC A LRADC4 D13 LRADC A LRADC5 D15 LRADC A LRADC6 C14 LRADC A PSWITCH A11 DCDC A PWM0 K7 PWM D PWM_0 I2C1_SCL DUART_RX PWM1 L7 PWM D PWM_1 I2C1_SDA DUART_TX PWM2 K8 PWM D PWM_2 USB0_ID USB1_OVERCURRENT PWM3 E9 PWM D PWM_3 PWM4 E10 PWM D PWM_4 RESETN A14 DCDC A RTC_XTALI D11 XTAL A RTC_XTALO C11 XTAL A SAIF0_BITCLK F7 SAIF D SAIF0_BITCLK PWM_5 AUART4_RX SAIF0_LRCLK G6 SAIF D SAIF0_LRCLK PWM_4 AUART4_RTS Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 681 Pin Definitions for 289-pin BGA Table 8-2. Pin Definitions (continued) GROUP TYP MUX0 E PIN NAME PIN MUX1 MUX2 SAIF0_MCLK G7 SAIF D SAIF0_MCLK PWM_3 AUART4_CTS SAIF0_SDATA0 E7 SAIF D SAIF0_SDATA0 PWM_6 AUART4_TX SAIF1_SDATA0 E8 SAIF D SAIF1_SDATA0 PWM_7 SAIF0_SDATA1 SPDIF D7 SPDIF D SPDIF_TX SSP0_CMD A4 SSP D SSP0_CMD SSP0_DATA0 B6 SSP D SSP0_D0 SSP0_DATA1 C6 SSP D SSP0_D1 SSP0_DATA2 D6 SSP D SSP0_D2 SSP0_DATA3 A5 SSP D SSP0_D3 SSP0_DATA4 B5 SSP D SSP0_D4 SSP2_D0 SSP0_DATA5 C5 SSP D SSP0_D5 SSP2_D3 SSP0_DATA6 D5 SSP D SSP0_D6 SSP2_CMD SSP0_DATA7 B4 SSP D SSP0_D7 SSP2_SCK ENET1_RX_ER SSP0_DETECT D10 SSP D SSP0_CARD_DETE CT SSP0_SCK A6 SSP D SSP0_SCK SSP1_CMD C1 SSP D SSP1_CMD SSP2_D2 ENET0_1588_EVENT2 _IN SSP1_DATA0 D1 SSP D SSP1_D0 SSP2_D6 ENET0_1588_EVENT3 _OUT SSP1_DATA3 E1 SSP D SSP1_D3 SSP2_D7 ENET0_1588_EVENT3 _IN SSP1_SCK B1 SSP D SSP1_SCK SSP2_D1 ENET0_1588_EVENT2 _OUT SSP2_MISO B3 SSP D SSP2_D0 AUART3_RX SAIF1_SDATA1 SSP2_MOSI C3 SSP D SSP2_CMD AUART2_TX SAIF0_SDATA2 SSP2_SCK A3 SSP D SSP2_SCK AUART2_RX SAIF0_SDATA1 SSP2_SS0 C4 SSP D SSP2_D3 AUART3_TX SAIF1_SDATA2 SSP2_SS1 D3 SSP D SSP2_D4 SSP2_D1 USB1_OVERCURRENT SSP2_SS2 D4 SSP D SSP2_D5 SSP2_D2 USB0_OVERCURRENT SSP3_MISO B2 SSP D SSP3_D0 AUART4_RTS ENET1_1588_EVENT1 _OUT SSP3_MOSI C2 SSP D SSP3_CMD AUART4_RX ENET1_1588_EVENT0 _IN SSP3_SCK A2 SSP D SSP3_SCK AUART4_TX ENET1_1588_EVENT0 _OUT SSP3_SS0 D2 SSP D SSP3_D3 AUART4_CTS ENET1_1588_EVENT1 _IN TESTMODE C10 SYSTE M D USB0DM A10 USB A USB0DP B10 USB A Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 682 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-2. Pin Definitions (continued) GROUP TYP MUX0 E PIN NAME PIN USB1DM B8 USB A USB1DP A8 USB A VDD1P5 D16 DCDC A VDD4P2 A13 DCDC A VDD5V E17 DCDC A VDDA1 C13 POWER A VDDD G12, G11, F10, F11, K12, F12, G10 POWER P VDDIO18 G8, F9, F8, G9 POWER P VDDIO33 H8, J8, N3, G3, E6, J9, J10, A7, E16 POWER P VDDIO33_EMI N17 POWER P VDDIO_EMI P11, R13, N13, N15, G17, M12, M10, G13, M11, L13, G15 POWER P VDDIO_EMIQ K15, J13, R15 POWER P VDDXTAL C12 POWER A VSS E15, L11, A1, K10, K11, J11, M14, H11, U1, H9, H12, H3, K9, POWER C16, L10, H16, J12, H10, B7, E5, J15, A9, N4 P VSSA1 B13 POWER A VSSA2 B11 POWER A VSSIO_EMI F16, R10, H14, M16, F14, L12, P16, U17, T14, P14, R12 POWER P XTALI A12 XTAL A XTALO B12 XTAL A MUX1 MUX2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 683 Functional Pin Groups 1 A B C D E F G H J K L M VSS 2 3 4 5 SSP1_SC SSP3_MI SSP2_MI SSP0_DA SSP0_DA SSP0_DA K SO SO TA7 TA4 TA0 SSP1_CM SSP3_M SSP2_M SSP2_SS SSP0_DA SSP0_DA D OSI OSI 0 TA5 TA1 SSP1_DA SSP3_SS SSP2_SS SSP2_SS SSP0_DA SSP0_DA TA0 0 1 2 SSP1_DA ENET_CL ENET0_T ENET0_R TA3 7 K X_CLK X_EN TA6 TA2 VSS VDDIO33 VSS XD1 ENET0_T ENET0_T XD2 XD3 ENET0_R ENET0_R XD0 XD1 X_CLK VDDIO33 VSS X_EN TX RX SPDIF RX RCLK DATA0 TCLK CLK ENET0_M AUART0_ AUART2_ AUART2_ DIO TX CTS RTS ENET0_R ENET0_R ENET0_C ENET0_C AUART1_ AUART0_ AUART0_ XD2 LCD_WR _RWN LCD_VSY NC LCD_HSY NC XD3 RS LCD_D00 LCD_D01 LCD_D02 LCD_D03 OL RTS AUART1_ AUART1_ AUART3_ TX CTS RX TX PWM0 PWM1 PWM3 12 USB0DM PSWITCH XTALI USB0DP XTALO VSSA2 TESTMO RTC_XTA DE LO PWM4 LI JTAG_TC K S JTAG_TDI VDDIO18 VDDIO18 VDDD VDDD VDDD VDDIO18 VDDIO18 VDDD VDDD VDDD VSS VSS VSS VSS VSS VSS VSS VDDD VSS VSS VDDIO33 VSS VDDIO33 VDDIO33 VDDIO33 PWM2 VSS GPMI_RD GPMI_RE Y3 SETN VSSA1 LRADC4 HSADC0 15 16 JTAG_TR ST O EMI_D14 VDDIO_E MI EMI_D12 VDDIO_E MIQ CK ATT DDA VSS LRADC5 VDD1P5 VSS VDDIO33 VSSIO_E EMI_DQM VSSIO_E MI EMI_D10 VSSIO_E MI EMI_D11 17 DCDC_G ND DCDC_B DCDC_V DCDC_L LRADC6 LRADC0 JTAG_TD JTAG_RT 1 VDDIO_E MI EMI_D09 VSS MI EMI_D08 VSS N1 DCDC_V DDIO DCDC_V F1 MI _OPEN MIQ 0N C VDD5V E EMI_D15 F VDDIO_E MI EMI_D13 1 0 EMI_DDR EMI_CLK EMI_D06 _OPEN_F EMI_CLK N B EMI_DQM VSSIO_E B D EMI_DQS EMI_DQS 1N A DDD EMI_VRE EMI_DDR VDDIO_E EMI_DQS EMI_DQS VSSIO_E VDDIO_E MI 14 VDD4P2 RESETN BATTERY DCDC_LP VDDXTAL VDDA1 SSP0_DE RTC_XTA JTAG_TM TECT 13 G H J K L M LCD_EN GPMI_RD GPMI_CE GPMI_RD GPMI_CE VDDIO_E VDDIO_E VDDIO33 EMI_A14 EMI_A07 EMI_BA2 EMI_D03 EMI_D00 ABLE Y0 0N Y1 1N MI MI _EMI N LCD_RD_ GPMI_AL GPMI_CL GPMI_W EMI_CE1 VDDIO_E EMI_CE0 VSSIO_E VSSIO_E LCD_CS EMI_A09 EMI_D04 EMI_D02 EMI_D05 E E E RN N MI N MI MI P GPMI_RD GPMI_D0 GPMI_D0 VSSIO_E VSSIO_E VDDIO_E EMI_VRE VDDIO_E EMI_RAS EMI_ODT EMI_A06 EMI_A05 N 5 2 MI MI MI F0 MIQ N 0 R RX R LCD_D10 LCD_D11 LCD_D17 LCD_D20 LCD_D23 T LCD_D12 LCD_D13 LCD_D16 LCD_D19 LCD_D22 VSS LCD_D14 LCD_D15 LCD_D18 LCD_D21 3 RTS DATA0 11 AUART3_ LCD_RES GPMI_CE GPMI_RD GPMI_CE VDDIO_E VDDIO_E VDDIO_E LCD_D07 LCD_D08 LCD_D09 2 CTS I2C0_SDA LRADC3 10 EMI_D07 LCD_D04 LCD_D05 LCD_RS P 1 RTS AUART1_ AUART3_ AUART3_ LCD_DO LCD_D06 VDDIO33 TCLK VSS CTS VSS USB1DM DEBUG SAIF0_S SAIF1_S ENET0_M AUART0_ SAIF0_L SAIF0_M DC 9 I2C0_SCL LRADC2 LRADC1 ENET0_T ENET0_T ENET0_R ENET0_T AUART2_ AUART2_ SAIF0_BI XD0 8 SSP3_SC SSP2_SC SSP0_CM SSP0_DA SSP0_SC VDDIO33 USB1DP K K D TA3 K N U 6 4 5 ET 2N Y2 GPMI_D0 GPMI_D0 GPMI_D0 7 4 1 GPMI_D0 GPMI_D0 GPMI_D0 6 3 0 6 7 8 3N MI MI MI EMI_D01 EMI_A13 EMI_A11 EMI_A03 EMI_BA1 EMI_CKE VSS VSSIO_E MI 0 EMI_WEN EMI_BA0 EMI_A08 EMI_A04 EMI_A12 EMI_A01 EMI_A10 EMI_A02 EMI_A00 9 10 11 12 13 14 MI 15 EMI_ODT 1 EMI_CAS VSSIO_E N MI 16 17 T U Figure 8-1. Ball Map 8.3 Functional Pin Groups This section includes the i.MX28 pins listed in tables by function. Refer to the pin name tables in the previous sections for appropriate package pin numbers. 1. Table 8-3 2. Table 8-4 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 684 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions 3. Table 8-5 4. Table 8-6 5. Table 8-7 6. Table 8-8 7. Table 8-9 8. Table 8-10 9. Table 8-11 10. Table 8-12 11. Table 8-13 12. Table 8-14 13. Table 8-15 14. Table 8-16 15. Table 8-17 16. Table 8-18 17. Table 8-19 18. Table 8-20 19. Table 8-21 Table 8-3. DCDC PIN NAME GROUP TYPE DESCRIPTION VDD1P5 DCDC A 1.5V regulator output for LVDDR2 power supply DCDC_VDDD DCDC A DCDC output for Digital Core Power w/ typical value of 1.2V DCDC_LN2 DCDC A DCDC Inductor N 2 DCDC_VDDIO DCDC A DCDC output for I/O Power w/ typical value of 3.3V DCDC_VDDA DCDC A DCDC output for analog/DDR2/1.8V IO power w/ typical value of 1.8V DCDC_LN1 DCDC A DCDC Inductor N 1 DCDC_GND DCDC A DCDC Ground DCDC_LP DCDC A DCDC Inductor P DCDC_BATT DCDC A DCDC Battery VDD4P2_DCDC DCDC A DCDC 4.2V Input VDD4P2 DCDC A DCDC 4.2V Regulated Output Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 685 Functional Pin Groups Table 8-3. DCDC (continued) PIN NAME GROUP TYPE DESCRIPTION VDD5V DCDC A 5V Power Input BATTERY DCDC A Battery Input RESETN DCDC A Chip-wide Reset In PSWITCH DCDC A Power On / Recovery / Software Visible Table 8-4. POWER PIN NAME GROUP TYPE DESCRIPTION VDDA1 POWER A Analog Power 1 VDDD POWER P VDDIO18 POWER P VDDIO33 POWER P VDDIO33_EMI POWER P VDDIO_EMI POWER P VDDIO_EMIQ POWER P Digital I/O Quiet Power 0 / EMI VDDXTAL POWER A Crystal Power Filter Capacitor VSSA1 POWER A Analog Ground 1 VSSA2 POWER A Analog Ground 2 VSSA3 POWER A Analog Ground 3 VSSD POWER P VSSIO18 POWER P VSSIO33 POWER P VSSIO_EMI POWER P VSSIO_EMIQ POWER P Digital I/O Quiet Power 0 / EMI Table 8-5. Analog application pins PIN NAME GROUP TYPE DESCRIPTION HSADC0 HSADC A HSADC LRADC6 LRADC A LRADC6 LRADC5 LRADC A LRADC5 LRADC4 LRADC A LRADC4 LRADC3 LRADC A LRADC3 LRADC2 LRADC A LRADC2 LRADC1 LRADC A LRADC1 LRADC0 LRADC A LRADC0 USB0DP USB A USB0 Positive Data Line USB0DM USB A USB0 Negative Data Line USB1DP USB A USB1 Positive Data Line Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 686 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-5. Analog application pins (continued) PIN NAME GROUP TYPE DESCRIPTION USB1DM USB A USB1 Negative Data Line RTC_XTALI XTAL A 32.768 or 32.0 KHz Xtal In RTC_XTALO XTAL A 32.768 or 32.0 KHz Xtal Out XTALO XTAL A 24MHz Crystal Out XTALI XTAL A 24MHz Crystal In Table 8-6. AUART PIN NAME GROU P TYPE SAIF0_SD ATA0 SAIF D SAIF0 Serial Data0 (stereo) SSP2_SC K SSP D SSP3_SC K SSP SSP2_MIS O DESCRIPTION MUX0 MUX1 MUX2 SAIF0_SDATA0 PWM_6 AUART4_TX SSP Serial Clock SSP2_SCK AUART2_RX SAIF0_SDATA1 D SSP Serial Clock SSP3_SCK AUART4_TX ENET1_1588_EVE NT0_OUT SSP D SD/MMC/Data0 / SPI MISO SSP2_D0 AUART3_RX SAIF1_SDATA1 SSP2_SS0 SSP D SD/MMC/Data3 / SPI Slave Select 0 SSP2_D3 AUART3_TX SAIF1_SDATA2 SAIF0_BIT CLK SAIF D SAIF0_BITCLK PWM_5 AUART4_RX SSP3_MIS O SSP D SD/MMC/Data0 / SPI MISO SSP3_D0 AUART4_RTS ENET1_1588_EVE NT1_OUT SSP2_MO SI SSP D SD/MMC CMD / SPI MOSI SSP2_CMD AUART2_TX SAIF0_SDATA2 AUART2_ RX AUART D Application UART2 RX AUART2_RX SSP3_D1 SSP3_D4 SSP3_MO SI SSP D SD/MMC CMD / SPI MOSI SSP3_CMD AUART4_RX ENET1_1588_EVE NT0_IN SSP3_SS0 SSP D SD/MMC/Data3 / SPI Slave Select 0 SSP3_D3 AUART4_CTS ENET1_1588_EVE NT1_IN SAIF0_MC LK SAIF D SAIF0_MCLK PWM_3 AUART4_CTS SAIF0_LR CLK SAIF D SAIF0 Left/Right Clock SAIF0_LRCLK PWM_4 AUART4_RTS AUART2_ TX AUART D Application UART2 TX AUART2_TX SSP3_D2 SSP3_D5 AUART2_ RTS AUART D Application UART2 RTS Flow Control AUART2_RTS I2C1_SDA SAIF1_LRCLK AUART2_ CTS AUART D Application UART2 CTS Flow Control AUART2_CTS I2C1_SCL SAIF1_BITCLK AUART0_ RX AUART D Application UART0 RX AUART0_RX I2C0_SCL DUART_CTS Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 687 Functional Pin Groups Table 8-6. AUART (continued) PIN NAME GROU P TYPE AUART0_ RTS AUART D Application UART0 RTS Flow Control AUART0_ TX AUART D Application UART0 TX AUART0_ CTS AUART D AUART1_ RTS AUART AUART3_ RTS DESCRIPTION MUX0 MUX1 MUX2 AUART0_RTS AUART4_TX DUART_TX AUART0_TX I2C0_SDA DUART_RTS Application UART0 CTS Flow Control AUART0_CTS AUART4_RX DUART_RX D Application UART1 RTS Flow Control AUART1_RTS USB0_ID TIMROT_ROTARY B AUART D Application UART2 RTS Flow Control AUART3_RTS CAN1_RX ENET0_1588_EVE NT1_IN AUART1_ CTS AUART D Application UART1 CTS Flow Control AUART1_CTS AUART1_ TX AUART D Application UART1 TX AUART1_TX SSP3_CARD_DET ECT PWM_1 AUART3_ TX AUART D Application UART2 TX AUART3_TX CAN0_RX ENET0_1588_EVE NT0_IN AUART1_ RX AUART D Application UART1 RX AUART1_RX SSP2_CARD_DET ECT PWM_0 AUART3_ CTS AUART D Application UART2 CTS Flow Control AUART3_CTS CAN1_TX ENET0_1588_EVE NT1_OUT AUART3_ RX AUART D Application UART2 RX AUART3_RX CAN0_TX ENET0_1588_EVE NT0_OUT MUX0 MUX1 MUX2 AUART3_RTS CAN1_RX ENET0_1588_EVE NT1_IN AUART3_TX CAN0_RX ENET0_1588_EVE NT0_IN AUART3_CTS CAN1_TX ENET0_1588_EVE NT1_OUT USB0_OVERCURR TIMROT_ROTARY ENT A Table 8-7. CAN PIN NAME GROU P TYPE AUART3_ RTS AUART D Application UART2 RTS Flow Control AUART3_ TX AUART D Application UART2 TX AUART3_ CTS AUART D Application UART2 CTS Flow Control AUART3_ RX AUART D Application UART2 RX AUART3_RX CAN0_TX ENET0_1588_EVE NT0_OUT GPMI_CE2 GPMI N D NAND Chip Enable 2 GPMI_CE2N CAN1_TX ENET0_RX_ER GPMI_RD Y2 GPMI D NAND2 Ready/Busy# GPMI_READY2 CAN0_TX ENET0_TX_ER GPMI_CE3 GPMI N D NAND Chip Enable 3 GPMI_CE3N CAN1_RX SAIF1_MCLK GPMI_RD Y3 D NAND3 Ready/Busy# GPMI_READY3 CAN0_RX HSADC_TRIGGER GPMI DESCRIPTION i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 688 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-8. DUART PIN NAME GROU P TYPE DESCRIPTION MUX0 MUX1 MUX2 I2C0_SDA I2C D I2C0 Serial Data I2C0_SDA TIMROT_ROTARY B DUART_TX I2C0_SCL I2C D I2C0 Serial Clock I2C0_SCL TIMROT_ROTARY A DUART_RX AUART0_ RX AUART D Application UART0 RX AUART0_RX I2C0_SCL DUART_CTS AUART0_ RTS AUART D Application UART0 RTS Flow Control AUART0_RTS AUART4_TX DUART_TX AUART0_ TX AUART D Application UART0 TX AUART0_TX I2C0_SDA DUART_RTS AUART0_ CTS AUART D Application UART0 CTS Flow Control AUART0_CTS AUART4_RX DUART_RX PWM0 PWM D PWM_0 I2C1_SCL DUART_RX PWM1 PWM D PWM_1 I2C1_SDA DUART_TX Table 8-9. EMI PIN NAME GROUP TYPE DESCRIPTION EMI_A13 EMI E EMI Address 13 EMI_A12 EMI E EMI Address 12 EMI_A08 EMI E EMI Address 8 EMI_A11 EMI E EMI Address 11 EMI_A09 EMI E EMI Address 9 EMI_A07 EMI E EMI Address 7 EMI_A04 EMI E EMI Address 4 EMI_A14 EMI E EMI Address 14 EMI_A06 EMI E EMI Address 6 EMI_A05 EMI E EMI Address 5 EMI_A03 EMI E EMI Address 3 EMI_CE0N EMI E EMI CE0n EMI_A00 EMI E EMI Address 0 EMI_A02 EMI E EMI Address 2 EMI_A01 EMI E EMI Address 1 EMI_CE1N EMI E EMI CE1n EMI_A10 EMI E EMI Address 10 EMI_BA1 EMI E EMI Bank Address 1 EMI_BA0 EMI E EMI Bank Address 0 EMI_ODT1 EMI E EMI DDR Byte1 ODT Enable EMI_ODT0 EMI E EMI DDR Byte0 ODT Enable EMI_RASN EMI E EMI RASn Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 689 Functional Pin Groups Table 8-9. EMI (continued) PIN NAME GROUP TYPE DESCRIPTION EMI_BA2 EMI E EMI Bank Address 2 EMI_CASN EMI E EMI CASn EMI_WEN EMI E EMI WEn EMI_CKE EMI E EMI Clock Enable EMI_D05 EMI E EMI Data 5 EMI_D02 EMI E EMI Data 2 EMI_D03 EMI E EMI Data 3 EMI_D04 EMI E EMI Data 4 EMI_D00 EMI E EMI Data 0 EMI_D01 EMI E EMI Data 1 EMI_DQM0 EMI E EMI DDR Data Mask 0 (Low Byte) EMI_D06 EMI E EMI Data 6 EMI_D07 EMI E EMI Data 7 EMI_CLK EMI E EMI Clock EMI_CLKN EMI E EMI Clock Invert EMI_DQS0 EMI E EMI DDR Data Strobe 0 (Low Byte) EMI_DQS0N EMI E EMI DDR Data Strobe 0 Invert (Low Byte) EMI_DQS1 EMI E EMI DDR Data Strobe 1 EMI_DQS1N EMI E EMI DDR Data Strobe 1 Invert EMI_DDR_OPEN_FB EMI E EMI DDR Echo Gating feedback EMI_DDR_OPEN EMI E EMI DDR DDR Echo Gating EMI_D13 EMI E EMI Data 13 EMI_D10 EMI E EMI Data 10 EMI_D11 EMI E EMI Data 11 EMI_D12 EMI E EMI Data 12 EMI_D08 EMI E EMI Data 8 EMI_D09 EMI E EMI Data 9 EMI_D15 EMI E EMI Data 15 EMI_DQM1 EMI E EMI DDR Data Mask 1 EMI_D14 EMI E EMI Data 14 Table 8-10. ENET PIN NAME GROU P TYPE DESCRIPTION MUX0 ENET_CL K ENET D reference clock CLK_ENET ENET1_RX_ER SPDIF SPDIF D SPDIF_TX ENET1_RX_ER SSP D SSP3_SC K SSP Serial Clock SSP3_SCK MUX1 AUART4_TX MUX2 ENET1_1588_EVE NT0_OUT Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 690 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-10. ENET (continued) PIN NAME GROU P TYPE SSP3_MIS O SSP D SD/MMC/Data0 / SPI MISO SSP1_SC K SSP D SSP3_MO SI SSP SSP1_CM D DESCRIPTION MUX0 MUX1 MUX2 SSP3_D0 AUART4_RTS ENET1_1588_EVE NT1_OUT SSP Serial Clock SSP1_SCK SSP2_D1 ENET0_1588_EVE NT2_OUT D SD/MMC CMD / SPI MOSI SSP3_CMD AUART4_RX ENET1_1588_EVE NT0_IN SSP D SD/MMC CMD / SPI MOSI SSP1_CMD SSP2_D2 ENET0_1588_EVE NT2_IN SSP3_SS0 SSP D SD/MMC/Data3 / SPI Slave Select 0 SSP3_D3 AUART4_CTS ENET1_1588_EVE NT1_IN SSP1_DA TA0 SSP D SD/MMC/ Data0 / SPI MISO SSP1_D0 SSP2_D6 ENET0_1588_EVE NT3_OUT SSP1_DA TA3 SSP D SD/MMC/ Data3 / SPI Slave Select 0 SSP1_D3 SSP2_D7 ENET0_1588_EVE NT3_IN ENET0_R X_EN ENET D DataValid/CRS_DV carrier sense ENET0_RX_EN GPMI_CE6N SAIF1_SDATA1 ENET0_TX ENET _CLK D transmit clock ENET0_TX_CLK HSADC_TRIGGER ENET0_1588_EVE NT2_OUT ENET0_TX ENET _EN D Transmit data valid ENET0_TX_EN GPMI_READY5 ENET0_R X_CLK ENET D receive clock ENET0_RX_CLK ENET0_RX_ER ENET0_TX ENET D1 D Transmit DATA1 ENET0_TXD1 GPMI_READY7 ENET0_TX ENET D0 D Transmit DATA0 ENET0_TXD0 GPMI_READY6 ENET0_M DC ENET D ENET0_MDC GPMI_CE4N SAIF0_SDATA1 ENET0_TX ENET D3 D Transmit DATA3 ENET0_TXD3 ENET1_TXD1 ENET0_1588_EVE NT1_IN ENET0_TX ENET D2 D Transmit DATA2 ENET0_TXD2 ENET1_TXD0 ENET0_1588_EVE NT1_OUT ENET0_M DIO ENET D Management data ENET0_MDIO GPMI_CE5N SAIF0_SDATA2 ENET0_R XD1 ENET D ENET0_RXD1 GPMI_READY4 ENET0_R XD0 ENET D Receive DATA0 ENET0_RXD0 GPMI_CE7N SAIF1_SDATA2 ENET0_C OL ENET D collision detect ENET0_COL ENET1_TX_EN ENET0_1588_EVE NT3_OUT ENET0_C RS ENET D carrier sense ENET0_CRS ENET1_RX_EN ENET0_1588_EVE NT3_IN ENET0_R XD3 ENET D Receive DATA3 ENET0_RXD3 ENET1_RXD1 ENET0_1588_EVE NT0_IN ENET0_1588_EVE NT2_IN Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 691 Functional Pin Groups Table 8-10. ENET (continued) PIN NAME GROU P TYPE ENET0_R XD2 ENET D AUART3_ RTS AUART AUART3_ TX MUX0 MUX1 MUX2 ENET0_RXD2 ENET0_RXD2 ENET1_RXD0 ENET0_1588_EVE NT0_OUT D Application UART2 RTS Flow Control AUART3_RTS CAN1_RX ENET0_1588_EVE NT1_IN AUART D Application UART2 TX AUART3_TX CAN0_RX ENET0_1588_EVE NT0_IN AUART3_ CTS AUART D Application UART2 CTS Flow Control AUART3_CTS CAN1_TX ENET0_1588_EVE NT1_OUT AUART3_ RX AUART D Application UART2 RX AUART3_RX CAN0_TX ENET0_1588_EVE NT0_OUT LCD_D20 LCD D LCD Interface Data 20 LCD_D20 ENET1_1588_EVE NT2_OUT ETM_DA3 LCD_D23 LCD D LCD Interface Data 23 LCD_D23 ENET1_1588_EVE NT3_IN ETM_DA0 LCD_D22 LCD D LCD Interface Data 22 LCD_D22 ENET1_1588_EVE NT3_OUT ETM_DA1 LCD_D21 LCD D LCD Interface Data 21 LCD_D21 ENET1_1588_EVE NT2_IN ETM_DA2 GPMI_CE2 GPMI N D NAND Chip Enable 2 GPMI_CE2N CAN1_TX ENET0_RX_ER GPMI_RD Y2 D NAND2 Ready/Busy# GPMI_READY2 CAN0_TX ENET0_TX_ER MUX1 MUX2 GPMI DESCRIPTION Table 8-11. ETM PIN NAME GROU P TYPE LCD_D01 LCD D LCD Interface Data 01 LCD_D1 ETM_DA1 LCD_D00 LCD D LCD Interface Data 00 LCD_D0 ETM_DA0 LCD_WR_ RWN LCD D LCD Interface 6800 R/W_ / 8080 W LCD_D03 LCD D LCD_D02 LCD LCD_D05 LCD_D04 DESCRIPTION MUX0 LCD_WR_RWN LCD_HSYNC ETM_TCLK LCD Interface Data 03 LCD_D3 ETM_DA8 ETM_DA3 D LCD Interface Data 02 LCD_D2 LCD D LCD Interface Data 05 LCD_D5 LCD D LCD Interface Data 04 LCD_D4 ETM_DA9 ETM_DA4 LCD_HSY NC LCD D LCD0 Horizontal Sync LCD_HSYNC SAIF1_SDATA1 ETM_TCTL LCD_D06 LCD D LCD Interface Data 06 LCD_D6 LCD_DOT CLK LCD D LCD Interface DOT clock LCD_RD_ E LCD D LCD Interface 6800 Enable / 8080 RD LCD_D09 LCD D LCD Interface Data 09 ETM_DA2 ETM_DA5 ETM_DA6 LCD_DOTCLK SAIF1_MCLK ETM_TCLK LCD_RD_E LCD_VSYNC ETM_TCTL LCD_D9 ETM_DA4 ETM_DA9 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 692 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-11. ETM (continued) PIN NAME GROU P TYPE LCD_D08 LCD D LCD_D07 LCD LCD_D17 DESCRIPTION MUX0 MUX1 MUX2 LCD Interface Data 08 LCD_D8 ETM_DA3 ETM_DA8 D LCD Interface Data 07 LCD_D7 ETM_DA7 LCD D LCD Interface Data 17 LCD_D17 ETM_DA6 LCD_D11 LCD D LCD Interface Data 11 LCD_D11 ETM_DA11 LCD_D10 LCD D LCD Interface Data 10 LCD_D10 ETM_DA10 LCD_D16 LCD D LCD Interface Data 16 LCD_D16 ETM_DA7 LCD_D13 LCD D LCD Interface Data 13 LCD_D13 ETM_DA13 LCD_D12 LCD D LCD Interface Data 12 LCD_D12 ETM_DA12 LCD_D14 LCD D LCD Interface Data 14 LCD_D14 ETM_DA14 LCD_D15 LCD D LCD Interface Data 15 LCD_D15 ETM_DA15 LCD_D20 LCD D LCD Interface Data 20 LCD_D20 LCD_D19 LCD D LCD Interface Data 19 LCD_D19 ETM_DA4 LCD_D18 LCD D LCD Interface Data 18 LCD_D18 ETM_DA5 LCD_D23 LCD D LCD Interface Data 23 LCD_D23 ENET1_1588_EVE NT3_IN ETM_DA0 LCD_D22 LCD D LCD Interface Data 22 LCD_D22 ENET1_1588_EVE NT3_OUT ETM_DA1 LCD_D21 LCD D LCD Interface Data 21 LCD_D21 ENET1_1588_EVE NT2_IN ETM_DA2 ENET1_1588_EVE NT2_OUT ETM_DA3 Table 8-12. GPMI PIN NAME GROUP TYPE DESCRIPTION MUX0 MUX1 MUX2 ENET0_RX_EN ENET D ENET0_RX_EN GPMI_CE6N SAIF1_SDATA1 ENET0_TX_EN ENET D ENET0_TX_EN GPMI_READY5 ENET0_TXD1 ENET ENET0_TXD0 ENET D ENET0_TXD1 GPMI_READY7 D ENET0_TXD0 GPMI_READY6 ENET0_MDC ENET D ENET0_MDC GPMI_CE4N SAIF0_SDATA1 ENET0_MDIO ENET D ENET0_MDIO GPMI_CE5N SAIF0_SDATA2 ENET0_RXD1 ENET D ENET0_RXD1 GPMI_READY4 ENET0_RXD0 ENET D ENET0_RXD0 GPMI_CE7N SAIF1_SDATA2 GPMI_RDY0 GPMI D NAND0 Ready/Busy# GPMI_READY0 SSP1_CARD_DE TECT USB0_ID GPMI_ALE GPMI D NAND ALE GPMI_ALE SSP3_D1 SSP3_D4 GPMI_RDN GPMI D NAND Read Strobe GPMI_RDN SSP3_SCK GPMI_D07 GPMI D NAND Data 7 GPMI_D7 SSP1_D7 GPMI_D06 GPMI D NAND Data 6 GPMI_D6 SSP1_D6 GPMI_CE2N GPMI D NAND Chip Enable 2 GPMI_CE2N CAN1_TX GPMI_CE0N GPMI D NAND Chip Enable 0 GPMI_CE0N SSP3_D0 RMII ENET0_MDC Receive DATA1 ENET0_RX_ER Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 693 Functional Pin Groups Table 8-12. GPMI (continued) PIN NAME GROUP TYPE DESCRIPTION MUX0 MUX1 MUX2 GPMI_CLE GPMI D NAND CLE GPMI_CLE SSP3_D2 SSP3_D5 GPMI_D05 GPMI D NAND Data 5 GPMI_D5 SSP1_D5 GPMI_D04 GPMI D NAND Data 4 GPMI_D4 SSP1_D4 GPMI_D03 GPMI D NAND Data 3 GPMI_D3 SSP1_D3 GPMI_RDY2 GPMI D NAND2 Ready/Busy# GPMI_READY2 CAN0_TX GPMI_RDY1 GPMI D NAND1 Ready/Busy# GPMI_READY1 SSP1_CMD GPMI_WRN GPMI D NAND Write Strobe GPMI_WRN SSP1_SCK GPMI_D02 GPMI D NAND Data 2 GPMI_D2 SSP1_D2 GPMI_D01 GPMI D NAND Data 1 GPMI_D1 SSP1_D1 GPMI_D00 GPMI D NAND Data 0 GPMI_D0 SSP1_D0 GPMI_RESETN GPMI D NAND Write Protect GPMI_RESETN SSP3_CMD GPMI_CE3N GPMI D NAND Chip Enable 3 GPMI_CE3N CAN1_RX GPMI_CE1N GPMI D NAND Chip Enable 1 GPMI_CE1N SSP3_D3 GPMI_RDY3 GPMI D NAND3 Ready/Busy# GPMI_READY3 CAN0_RX ENET0_TX_ER SAIF1_MCLK HSADC_TRIGGE R Table 8-13. HSADC PIN NAME GROUP TYPE ENET0_TX_CLK ENET D GPMI_RDY3 GPMI D DESCRIPTION MUX0 MUX1 ENET0_TX_CLK NAND3 Ready/ Busy# GPMI_READY3 MUX2 HSADC_TRIGGE ENET0_1588_EVENT2 R _OUT CAN0_RX HSADC_TRIGGER Table 8-14. I2C PIN NAME GROUP TYPE DESCRIPTION MUX0 MUX1 MUX2 I2C0_SDA I2C D I2C0 Serial Data I2C0_SDA TIMROT_ROT ARYB DUART_TX I2C0_SCL I2C D I2C0 Serial Clock I2C0_SCL TIMROT_ROT ARYA DUART_RX AUART2_RTS AUART D Application UART2 RTS Flow Control AUART2_RTS I2C1_SDA SAIF1_LRCLK AUART2_CTS AUART D Application UART2 CTS Flow Control AUART2_CTS I2C1_SCL SAIF1_BITCL K AUART0_RX AUART D Application UART0 RX AUART0_RX I2C0_SCL DUART_CTS AUART0_TX Application UART0 TX AUART D AUART0_TX I2C0_SDA DUART_RTS PWM0 PWM D PWM_0 I2C1_SCL DUART_RX PWM1 PWM D PWM_1 I2C1_SDA DUART_TX i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 694 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-15. JTAG PIN NAME GROUP TYPE DESCRIPTION DEBUG SYSTEM D ARM jtag chain/Boundary scan chain selection TESTMODE SYSTEM D Test Mode Pin JTAG_RTCK SYSTEM D JTAG feedback clock (only for ARM ICE) JTAG_TRST SYSTEM D JTAG Reset JTAG_TDO SYSTEM D JTAG Serial Data Out JTAG_TMS SYSTEM D JTAG Test Mode Select JTAG_TDI SYSTEM D JTAG Serial Data In JTAG_TCK SYSTEM D JTAG Clock Table 8-16. LCD GROU P TYPE LCD_D01 LCD D LCD Interface Data 01 LCD_D1 ETM_DA1 LCD_D00 LCD D LCD Interface Data 00 LCD_D0 ETM_DA0 LCD_WR_RWN LCD D LCD Interface 6800 R/W_ / 8080 W LCD_WR_RWN LCD_HSYNC ETM_TCLK LCD_D03 LCD D LCD Interface Data 03 LCD_D3 ETM_DA8 ETM_DA3 LCD_D02 LCD D LCD Interface Data 02 LCD_D2 LCD_VSYNC LCD D LCD Interface Vertical Sync LCD_RS LCD D LCD_D05 LCD LCD_D04 PIN NAME DESCRIPTION MUX0 MUX1 MUX2 ETM_DA2 LCD_VSYNC SAIF1_SDATA0 LCD Interface Register Select LCD_RS LCD_DOTCLK D LCD Interface Data 05 LCD_D5 LCD D LCD Interface Data 04 LCD_D4 ETM_DA9 ETM_DA4 LCD_HSYNC LCD D LCD0 Horizontal Sync LCD_HSYNC SAIF1_SDATA1 ETM_TCTL LCD_D06 LCD D LCD Interface Data 06 LCD_D6 LCD_DOTCLK LCD D LCD Interface DOT clock LCD_DOTCLK LCD_ENABLE LCD D LCD Interface Enable LCD_ENABLE LCD_RD_E LCD D LCD Interface 6800 Enable / 8080 RD LCD_D09 LCD D LCD_D08 LCD D ETM_DA5 ETM_DA6 SAIF1_MCLK ETM_TCLK LCD_RD_E LCD_VSYNC ETM_TCTL LCD Interface Data 09 LCD_D9 ETM_DA4 ETM_DA9 LCD Interface Data 08 LCD_D8 ETM_DA3 ETM_DA8 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 695 Functional Pin Groups Table 8-16. LCD (continued) GROU P TYPE LCD_D07 LCD D LCD Interface Data 07 LCD_D7 ETM_DA7 LCD_D17 LCD D LCD Interface Data 17 LCD_D17 ETM_DA6 LCD_D11 LCD D LCD Interface Data 11 LCD_D11 ETM_DA11 LCD_D10 LCD D LCD Interface Data 10 LCD_D10 ETM_DA10 LCD_D16 LCD D LCD Interface Data 16 LCD_D16 ETM_DA7 LCD_D13 LCD D LCD Interface Data 13 LCD_D13 ETM_DA13 LCD_D12 LCD D LCD Interface Data 12 LCD_D12 ETM_DA12 LCD_D14 LCD D LCD Interface Data 14 LCD_D14 ETM_DA14 LCD_D15 LCD D LCD Interface Data 15 LCD_D15 ETM_DA15 LCD_D20 LCD D LCD Interface Data 20 LCD_D20 LCD_D19 LCD D LCD Interface Data 19 LCD_D19 ETM_DA4 LCD_D18 LCD D LCD Interface Data 18 LCD_D18 ETM_DA5 LCD_CS LCD D LCD Interface Chip Select LCD_CS LCD_ENABLE LCD_D23 LCD D LCD Interface Data 23 LCD_D23 ENET1_1588_EVEN T3_IN ETM_DA0 LCD_D22 LCD D LCD Interface Data 22 LCD_D22 ENET1_1588_EVEN T3_OUT ETM_DA1 LCD_D21 LCD D LCD Interface Data 21 LCD_D21 ENET1_1588_EVEN T2_IN ETM_DA2 LCD_RESET LCD D LCD Interface Reset Out LCD_RESET LCD_VSYNC PIN NAME DESCRIPTION MUX0 MUX1 MUX2 ENET1_1588_EVEN T2_OUT ETM_DA3 Table 8-17. PWM PIN NAME GROUP TYPE DESCRIPTION SAIF1_SDATA0 SAIF D PWM3 PWM D PWM_3 PWM4 PWM D PWM_4 SAIF0_SDATA0 SAIF D SAIF0 Serial Data0 (stereo) SAIF0_BITCLK SAIF D SAIF0 BIT clock SAIF0_MCLK SAIF D SAIF0 Master Clock SAIF1 Serial Data0 (stereo) MUX0 MUX1 MUX2 SAIF1_SDATA0 PWM_7 SAIF0_SDATA1 SAIF0_SDATA0 PWM_6 AUART4_TX SAIF0_BITCLK PWM_5 AUART4_RX SAIF0_MCLK PWM_3 AUART4_CTS Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 696 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-17. PWM (continued) PIN NAME GROUP TYPE SAIF0_LRCLK SAIF D PWM0 PWM D AUART1_TX AUART D AUART1_RX AUART D PWM1 PWM PWM2 PWM DESCRIPTION MUX0 MUX1 MUX2 SAIF0_LRCLK PWM_4 AUART4_RTS PWM_0 I2C1_SCL DUART_RX Application UART1 TX AUART1_TX SSP3_CARD_DE TECT PWM_1 Application UART1 RX AUART1_RX SSP2_CARD_DE TECT PWM_0 D PWM_1 I2C1_SDA DUART_TX D PWM_2 USB0_ID USB1_OVERCU RRENT MUX0 MUX1 MUX2 PWM_7 SAIF0_SDATA1 SAIF0 Left/Right Clock Table 8-18. AUDIO(SAIF/SPDIF) PIN NAME GROUP TYPE DESCRIPTION SAIF1_SDATA0 SAIF D SAIF1 Serial Data0 (stereo) SAIF1_SDATA0 SAIF0_SDATA0 SAIF D SAIF0 Serial Data0 (stereo) SAIF0_SDATA0 PWM_6 AUART4_TX SSP2_SCK SSP D SSP Serial Clock SSP2_SCK AUART2_RX SAIF0_SDATA1 SSP2_MISO SSP D SD/MMC/Data0 / SPI MISO SSP2_D0 AUART3_RX SAIF1_SDATA1 SSP2_SS0 SSP D SD/MMC/Data3 / SPI Slave Select 0 SSP2_D3 AUART3_TX SAIF1_SDATA2 SAIF0_BITCLK SAIF D SAIF0_BITCLK PWM_5 AUART4_RX SSP2_MOSI SSP D SSP2_CMD AUART2_TX SAIF0_SDATA2 SAIF0_MCLK SAIF D SAIF0_MCLK PWM_3 AUART4_CTS SAIF0_LRCLK SAIF D SAIF0_LRCLK PWM_4 AUART4_RTS ENET0_RX_EN ENET D ENET0_RX_EN GPMI_CE6N SAIF1_SDATA1 AUART2_RTS AUART D Application UART2 RTS Flow Control AUART2_RTS I2C1_SDA SAIF1_LRCLK AUART2_CTS AUART D Application UART2 CTS Flow Control AUART2_CTS I2C1_SCL SAIF1_BITCLK ENET0_MDC ENET D ENET0_MDC GPMI_CE4N SAIF0_SDATA1 ENET0_MDIO ENET D ENET0_MDIO GPMI_CE5N SAIF0_SDATA2 ENET0_RXD0 ENET D ENET0_RXD0 GPMI_CE7N SAIF1_SDATA2 LCD_VSYNC LCD D LCD Interface Vertical Sync LCD_VSYNC SAIF1_SDATA0 LCD_HSYNC LCD D LCD0 Horizontal Sync LCD_HSYNC SAIF1_SDATA1 LCD_DOTCLK LCD D LCD Interface DOT clock LCD_DOTCLK SAIF1_MCLK ETM_TCLK GPMI_CE3N GPMI D NAND Chip Enable 3 GPMI_CE3N CAN1_RX SAIF1_MCLK SPDIF SPDIF D SD/MMC CMD / BS / SPI MOSI SAIF0 Left/Right Clock SPDIF_TX ETM_TCTL ENET1_RX_ER i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 697 Functional Pin Groups Table 8-19. SSP PIN NAME GROUP TYPE DESCRIPTION MUX0 MUX1 SSP0_DETE CT SSP D Removable Card Detect SSP0_SCK SSP D SSP Serial Clock SSP0_DATA 0 SSP D SD/MMC/Data0 / SPI MISO SSP0_D0 SSP0_DATA 3 SSP D SD/MMC/Data3 / SPI Slave Select 0 SSP0_D3 SSP0_DATA 4 SSP D SD/MMC/Data4 / SPI Slave Select 1 SSP0_D4 SSP0_DATA 1 SSP D SD/MMC/ Data1 / Winbond Write Protect_ SSP0_D1 SSP0_CMD SSP D SD/MMC CMD / SPI MOSI SSP0_CMD SSP2_SCK SSP D SSP Serial Clock SSP2_SCK AUART2_RX SSP0_DATA 7 SSP D SD/MMC/Data7 SSP0_D7 SSP2_SCK SSP0_DATA 5 SSP D SD/MMC/Data5 / SPI Slave Select 2 SSP0_D5 SSP2_D3 SSP0_DATA 2 SSP D SD/MMC/Data2 / Winbond Hold_ SSP0_D2 SSP3_SCK SSP D SSP Serial Clock SSP2_MISO SSP D MUX2 SSP0_CARD_DE TECT SSP0_SCK SSP2_D0 SAIF0_SDATA1 SSP3_SCK AUART4_TX ENET1_1588_EV ENT0_OUT SD/MMC/Data0 / SPI MISO SSP2_D0 AUART3_RX SAIF1_SDATA1 SSP2_D3 AUART3_TX SAIF1_SDATA2 SSP2_SS0 SSP D SD/MMC/Memstick Data3 / SPI Slave Select 0 SSP0_DATA 6 SSP D SD/MMC/Memstick Data6 SSP0_D6 SSP2_CMD SSP3_MISO SSP D SD/MMC/Memstick Data0 / SPI MISO SSP3_D0 AUART4_RTS ENET1_1588_EV ENT1_OUT SSP2_MOSI SSP D SD/MMC CMD / Memstick BS / SPI MOSI SSP2_CMD AUART2_TX SAIF0_SDATA2 SSP2_SS2 SSP D SD/MMC/Memstick Data0 / SPI MISO SSP2_D5 SSP2_D2 USB0_OVERCUR RENT AUART D AUART2_RX SSP3_D1 SSP3_D4 AUART2_RX SSP1_SCK SSP D SSP Serial Clock SSP1_SCK SSP2_D1 ENET0_1588_EV ENT2_OUT SSP3_MOSI SSP D SD/MMC CMD / SPI MOSI SSP3_CMD AUART4_RX ENET1_1588_EV ENT0_IN SSP2_SS1 SSP D SD/MMC/Data4 / SPI Slave Select 1 SSP2_D4 SSP2_D1 USB1_OVERCUR RENT SSP1_CMD SSP D SD/MMC CMD / SPI MOSI SSP1_CMD SSP2_D2 ENET0_1588_EV ENT2_IN SSP3_SS0 SSP D SD/MMC/Data3 / SPI Slave Select 0 SSP3_D3 AUART4_CTS ENET1_1588_EV ENT1_IN SSP1_DATA 0 SSP D SD/MMC/Data0 / SPI MISO SSP1_D0 SSP2_D6 ENET0_1588_EV ENT3_OUT Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 698 Freescale Semiconductor, Inc. Chapter 8 Pin Descriptions Table 8-19. SSP (continued) PIN NAME GROUP TYPE DESCRIPTION MUX0 MUX1 MUX2 SSP1_DATA 3 SSP D SD/MMC/Data3 / SPI Slave Select 0 SSP1_D3 SSP2_D7 ENET0_1588_EV ENT3_IN AUART2_TX AUART D Application UART2 TX AUART2_TX SSP3_D2 SSP3_D5 AUART1_TX AUART D Application UART1 TX AUART1_TX SSP3_CARD_DE TECT PWM_1 AUART1_RX AUART D Application UART1 RX AUART1_RX SSP2_CARD_DE TECT PWM_0 GPMI_RDY0 GPMI D NAND0 Ready/Busy# GPMI_READY0 SSP1_CARD_DE TECT USB0_ID GPMI_ALE GPMI D NAND ALE GPMI_ALE SSP3_D1 SSP3_D4 GPMI_RDN GPMI D NAND Read Strobe GPMI_RDN SSP3_SCK GPMI_D07 GPMI D NAND Data 7 GPMI_D7 SSP1_D7 GPMI_D06 GPMI D NAND Data 6 GPMI_D6 SSP1_D6 GPMI_CE0N GPMI D NAND Chip Enable 0 GPMI_CE0N SSP3_D0 GPMI_CLE GPMI D NAND CLE GPMI_CLE SSP3_D2 GPMI_D05 GPMI D NAND Data 5 GPMI_D5 SSP1_D5 GPMI_D04 GPMI D NAND Data 4 GPMI_D4 SSP1_D4 GPMI_D03 GPMI D NAND Data 3 GPMI_D3 SSP1_D3 GPMI_RDY1 GPMI D NAND1 Ready/Busy# GPMI_READY1 SSP1_CMD GPMI_WRN GPMI D NAND Write Strobe GPMI_WRN SSP1_SCK GPMI_D02 GPMI D NAND Data 2 GPMI_D2 SSP1_D2 GPMI_D01 GPMI D NAND Data 1 GPMI_D1 SSP1_D1 GPMI_D00 GPMI D NAND Data 0 GPMI_D0 SSP1_D0 GPMI_RESE TN GPMI D NAND Write Protect GPMI_RESETN SSP3_CMD GPMI_CE1N GPMI D NAND Chip Enable 1 GPMI_CE1N SSP3_D3 SSP3_D5 Table 8-20. TIMROT GROU P TYPE DESCRIPTION MUX0 MUX1 MUX2 I2C0_SDA I2C D I2C0 Serial Data I2C0_SDA TIMROT_ROTAR YB DUART_TX I2C0_SCL I2C D I2C0 Serial Clock I2C0_SCL TIMROT_ROTAR YA DUART_RX AUART1_RTS AUART D Application UART1 RTS Flow Control AUART1_RTS USB0_ID TIMROT_ROTAR YB AUART1_CTS AUART D Application UART1 CTS Flow Control AUART1_CTS PIN NAME USB0_OVERCUR TIMROT_ROTAR RENT YA i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 699 Functional Pin Groups Table 8-21. USB GROU P TYPE USB0DP USB A USB0 Positive Data Line USB0DM USB A USB0 Negative Data Line USB1DP USB A USB1 Positive Data Line USB1DM USB A USB1 Negative Data Line SSP2_SS2 SSP D SSP2_SS1 SSP PIN NAME DESCRIPTION MUX0 MUX1 MUX2 SD/MMC/Data3 / SPI Slave Select 0 SSP2_D5 SSP2_D2 USB0_OVERCUR RENT D SD/MMC/Data0 / SPI MISO SSP2_D4 SSP2_D1 USB1_OVERCUR RENT AUART1_RTS AUART D Application UART1 RTS Flow Control AUART1_RTS USB0_ID TIMROT_ROTAR YB AUART1_CTS AUART D Application UART1 CTS Flow Control AUART1_CTS PWM2 PWM D GPMI_RDY0 GPMI D NAND0 Ready/Busy# USB0_OVERCUR TIMROT_ROTAR RENT YA PWM_2 USB0_ID USB1_OVERCUR RENT GPMI_READY0 SSP1_CARD_DE TECT USB0_ID i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 700 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 9.1 Pin Control and GPIO Overview The i.MX28 digital interface pins have the following features: (In the context of this chapter, "digital pin" means the standard digital interface pins. This does not include test pins used for boundary scan control.) * The device has seven banks of pins, Banks 0~4 serve as GPIOs. Banks 5 and 6 contain the EMI sixteen data pins and EMI control/address signals, they are not multiplexed with other functions since all the use cases require at least sixteen bit external memory. * Each GPIO pin has separate control on voltage(1.8 V/3.3 V), Interrupt (trigger type/ polarity). * All non-EMI digital pins have selectable output drive strengths as described in Pin Drive Strength Selection. * Each group of EMI data[7:0], data[15:8], control pins and address pins, dual pads (clk/clkn/dqs#/dqs#n), have selectable output drive strengths. * All digital pins have weak internal keepers to minimize power loss due to undriven pins. * All EMI pins' internal keepers can be disabled to allow them to change to a highimpedance state (as required by some DRAM manufacturers). * The following pin interfaces have selectable pull up resistors: * SSP data - 47 k * SSP command/detect - 10 k i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 701 Operation * GPMI chip enable - 47 k * GPMI ready/busy - 10 k * The following pin interfaces are slow transitioning pins with internal Schmidt Triggers for noise immunity: * I2C SCL * I2C SDA 9.2 Operation Each individual digital pin supporting the GPIO operation may be dynamically programmed at any time to be in one of the following states: * High-impedance (for input, three-state, or open-drain applications) * Low * High * Controlled by one to three selectable on-chip peripheral module interfaces, on a pin by pin basis, as described in GPIO Interface. All non-EMI digital pins can be programmed for 1.8 or 3.3 V operation. All EMI pads run at 1.8 V/1.5 V. Selected pins have pullups that can be configured using register settings. When pullups are enabled, the pin's weak keeper devices are disabled. Additionally, the state of each pin may be read at any time (no matter how it is configured), and its drive strength may be configured as described in Pin Drive Strength Selection. Each GPIO pin may also be used as an interrupt input and the interrupt trigger type may be configured to be low level-sensitive, high level-sensitive, rising edge-sensitive, or falling edge-sensitive. The following sections show how to use all the features of each pin. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 702 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HARDWARE_FUNCTION_DOE0 HARDWARE_FUNCTION_DOE1 OE# HARDWARE_FUNCTION_DOE2 GPIO Output Enable Drive Strength HW_PINCTRL_DOEx HW_PINCTRL_DRIVEx HW_PINCTRL_MUXSELx OUTPUT HARDWARE_FUNCTION_DO0 HARDWARE_FUNCTION_DO1 GPIO Output 10 K or 47 K EN HARDWARE_FUNCTION_DO2 HW_PINCTRL_DOUTx Pad Power Integrated Pull-up (available only on certain pins). Enabling the internal pull-up disables the Gate Keeper. HW_PINCTRL_PULLx Pad Power PAD Gate Keeper. Note external 47K ( or stronger) pull-ups or pull-downs are needed to overdrive Gate Keepers HARDWARE_FUNCTION_DI0 HARDWARE_FUNCTION_DI1 EN HARDWARE_FUNCTION_DI2 HW_PINCTRL_MUXSELx INPUT GPIO Input HW_PINCTRL_DINx Figure 9-1. Pad Diagram 9.2.1 Reset Configuration Out of reset (hardware/software reset), all the pins (except JTAG related) are configured as GPIO inputs with gate keepers enabled. Here are some exceptions on general reset behavior: * Ethernet pins works differently, they will only reset when power is on. Software reset will not affect them. This is to make sure that the enet switch can still work during software reset. * EMI pins do not mux with GPIO function. So after reset, configure as GPIO means it is disabled. . 9.2.2 Pin Interface Multiplexing The device is designed for cost sensitive applications. It contains a rich set of specialized hardware interfaces (mDDR, NAND Flash, LCD panels, many types of insertable media, and so on), but does not have enough pins to allow use of all signals of all the interfaces i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 703 Operation simultaneously. Consequently, a pin multiplexing scheme is used to allow customers to choose which specialized interfaces to enable for their application. In addition to these specialized hardware interfaces, the device allows many digital pins to be used as GPIOs. This capability supports custom interfacing requirements, such as the ability to communicate with LEDs, digital buttons, and other devices that are not directly supported by any of the i.MX28 specialized hardware interfaces. Each pin is connected to one, two, or three specialized hardware interfaces, in addition to the GPIO function available on banks 0 through 4. The description of each pin in and contains full details of which specialized hardware interfaces are attached to that pin. For example, the package pin named PWM0 is shared between the PWM and debug UART hardware interfaces. Users define which of the available hardware interfaces controls each pin by writing a two-bit field for that pin into one of the HW_PINCTRL_MUXSELx registers. Table 9-1 - Table 9-2 illustrate the pin multiplexing on the device. Both 289 and 204 packages have same mux options, but some pins on 289 package are not available on 204 package and caused those related mux unavailable too. These unavailable pins for 204-pins package are marked gray on muxreg row in . * Table 9-1 shows the color mapping used in the tables. * Table 9-2 shows the multiplexing used in both the package. Table 9-1. Color Mapping for Pin Control Bank Tables EMI GPIO GPMI LCD SSP ENET USB ETM DUART AUART I2C PWM SAIF SPDIF JTAG Table 9-2. Pin Multiplexing for the 289-pin Package 12 11 10 9 8 7 6 5 4 gpmi_d4 gpmi_d5 gpmi_d6_gpmi_d7 sel ect = 00 gpmi_d7 Mu x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Re g0 3 8 7 2 6 5 1 4 3 0 2 1 0 gpmi_d0 13 gpmi_d1 14 gpmi_d2 15 gpmi_d3 Ba nk 0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 704 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) ssp1_d0 ssp1_d1 ssp1_d2 ssp1_d3 ssp1_d4 ssp1_d5 ssp1_d7 sel ect = 01 ssp1_d6 Table 9-2. Pin Multiplexing for the 289-pin Package (continued) sel ect = 10 sel ect = 11 31 30 29 28 27 26 25 24 23 22 21 20 sel ect = 11 Ba nk 1 gpmi_ce0n ssp3_d0 0 gpmi_ce1n 1 ssp3_d3 2 gpmi_ce2n 3 can1_tx 4 enet0_rx_er 5 can1_rx 6 16 saif1_mclk gpmi_ready0 7 17 ssp1_card_detect gpmi_ready1 ssp1_cmd 8 18 usb0_id gpmi_ready2 can0_tx enet0_tx_er gpmi_ready3 gpmi_rdn ssp3_sck can0_rx gpmi_wrn ssp1_sck hsadc_trigger gpmi_ale gpmi_cle ssp3_d1 sel ect = 10 ssp3_d4 ssp3_cmd sel ect = 01 ssp3_d2 gpmi_resetn sel ect = 00 ssp3_d5 Mu x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Re g1 19 gpmi_ce3n Ba nk 0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO 15 14 13 12 11 10 9 8 7 6 5 Mu x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Re g2 4 3 8 7 2 6 5 1 4 3 0 2 1 0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 705 Operation lcd_d15 lcd_d14 lcd_d13 lcd_d12 lcd_d11 lcd_d10 lcd_d9 lcd_d8 lcd_d7 lcd_d6 lcd_d5 lcd_d4 lcd_d3 lcd_d2 lcd_d1 lcd_d0 etm_da14 etm_da13 etm_da12 etm_da11 etm_da10 etm_da9 etm_da8 etm_da7 etm_da6 etm_da5 etm_da4 etm_da3 etm_da2 etm_da1 etm_da0 sel ect = 00 etm_da15 Table 9-2. Pin Multiplexing for the 289-pin Package (continued) sel ect = 01 sel ect = 10 sel ect GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO = 11 24 23 22 21 20 enet1_1588_event2_in etm_da3 lcd_d20 enet1_1588_event2_out etm_da2 lcd_d21 enet1_1588_event3_in etm_da1 lcd_d22 enet1_1588_event3_out lcd_d23 8 etm_da0 lcd_rd_e lcd_vsync etm_tctl lcd_wr_rwn lcd_hsync lcd_rs lcd_dotclk etm_tclk sel ect = 10 lcd_cs sel ect = 01 lcd_enable lcd_hsync etm_tclk lcd_vsync lcd_dotclk etm_tclk sel ect = 00 lcd_enable Mu x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Re g3 19 7 18 6 5 17 4 3 16 2 1 0 lcd_d16 25 etm_da7 26 lcd_d17 27 etm_da6 28 lcd_d18 29 etm_da5 30 lcd_d19 31 etm_da4 Ba nk 1 sel ect GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO = 11 Ba nk 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 706 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Table 9-2. Pin Multiplexing for the 289-pin Package (continued) sel ect GPIO GPIO GPIO GPIO = 11 Ba nk 2 31 30 29 28 2 1 0 ssp0_d0 ssp0_d4 ssp2_d0 3 ssp0_d1 ssp0_d5 ssp2_d3 4 ssp0_d2 ssp0_d6 ssp2_cmd 5 27 26 25 24 23 22 21 20 19 ssp2_d5 ssp2_d4 ssp2_d3 ssp2_d0 ssp2_cmd ssp2_sck ssp2_d1 auart3_tx auart3_rx auart2_tx auart2_rx 0 ssp2_d2 1 ssp3_sck 2 auart4_tx 3 ssp3_cmd 4 auart4_rx 5 ssp3_d0 6 16 auart4_rts 7 17 ssp3_d3 8 18 auart4_cts sel ect = 01 6 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Mu x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Re g5 sel ect = 00 7 ssp0_d3 ssp0_d7 8 ssp2_sck ssp0_cmd ssp0_card_detect ssp0_sck ssp1_sck ssp2_d1 enet0_1588_event2_out ssp1_cmd ssp2_d2 enet0_1588_event2_in ssp1_d0 ssp2_d6 enet0_1588_event3_out sel ect = 10 ssp2_d7 sel ect = 01 enet0_1588_event3_in sel ect = 00 ssp1_d3 Mu x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Re g4 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 707 Ba nk 3 708 31 30 29 28 i2c1_scl ssp3_d2 ssp3_d1 saif1_bitclk ssp3_d5 27 ssp3_d4 26 25 24 23 22 ssp2_card_detect auart4_tx auart4_rx i2c0_sda i2c0_scl pwm_0 21 duart_tx duart_rx duart_rts duart_cts 8 20 7 2 6 19 5 4 18 3 2 17 auart0_rx Mu x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Re g6 3 auart0_tx 4 auart0_cts 5 auart0_rts auart1_rx auart1_tx 6 ssp3_card_detect GPIO GPIO GPIO GPIO pwm_1 7 auart1_cts 8 auart1_rts 9 auart2_rx 10 auart2_tx 11 auart2_cts auart2_rts 12 usb0_overcurrent i2c1_sda saif1_lrclk auart3_rx 13 timrot_rotarya can0_tx enet0_1588_event0_out 14 auart3_tx sel ect = 11 usb0_id can0_rx enet0_1588_event0_in 15 auart3_cts saif0_sdata1 saif0_sdata2 saif1_sdata1 saif1_sdata2 usb1_overcurrent usb0_overcurrent enet1_1588_event0_out enet1_1588_event0_in enet1_1588_event1_out enet1_1588_event1_in sel ect = 10 timrot_rotaryb can1_tx sel ect = 10 enet0_1588_event1_out sel ect = 01 auart3_rts sel ect = 00 can1_rx Ba nk 3 enet0_1588_event1_in Operation Table 9-2. Pin Multiplexing for the 289-pin Package (continued) GPIO GPIO GPIO GPIO GPIO GPIO 1 0 1 0 sel ect GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO = 11 16 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. enet0_col enet0_rx_clk enet0_txd3 enet0_txd2 enet0_rxd3 enet0_rxd2 enet0_txd1 enet0_txd0 enet0_tx_en enet0_tx_clk enet0_rxd1 enet0_rxd0 enet0_rx_en enet0_mdio enet0_mdc enet0_rx_er enet1_txd1 enet1_txd0 enet1_rxd1 enet1_rxd0 gpmi_ready7 gpmi_ready6 gpmi_ready5 hsadc_trigger gpmi_ready4 gpmi_ce7n gpmi_ce6n gpmi_ce5n gpmi_ce4n sel ect = 01 enet1_tx_en sel ect = 00 enet0_crs Ba nk 4 enet1_rx_en sel ect = 01 lcd_reset sel ect = 00 sel ect = 11 15 14 GPIO 13 12 Freescale Semiconductor, Inc. 11 10 9 8 7 6 5 Mu x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Re g8 8 4 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO 7 6 i2c1_scl duart_rx 3 4 5 4 3 2 3 pwm_0 5 pwm_1 pwm_2 saif0_mclk 6 i2c1_sda pwm_3 auart4_cts saif0_lrclk 7 duart_tx pwm_4 auart4_rts saif0_bitclk 8 usb0_id pwm_5 auart4_rx saif0_sdata0 i2c0_scl i2c0_sda Mu x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Re g7 usb1_overcurrent pwm_6 timrot_rotarya duart_rx auart4_tx timrot_rotaryb duart_tx saif1_sdata0 saif0_sdata1 sel ect = 10 spdif_tx pwm_ 3 enet1_rx_er pwm_7 lcd_vsync Chapter 9 Pin Control and GPIO (PinCtrl) Table 9-2. Pin Multiplexing for the 289-pin Package (continued) 2 2 1 1 0 GPIO GPIO GPIO 0 1 0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 709 Operation saif0_sdata1 saif0_sdata2 saif1_sdata1 saif1_sdata2 enet0_1588_event2_out enet0_1588_event0_out enet0_1588_event0_in enet0_1588_event1_out enet0_1588_event1_in enet0_1588_event2_in enet0_1588_event3_out sel ect = 10 enet0_1588_event3_in Table 9-2. Pin Multiplexing for the 289-pin Package (continued) sel ect GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO = 11 31 30 29 28 27 26 25 24 23 22 21 20 Mu x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Re g9 8 7 18 6 5 17 4 3 16 2 jtag_rtck sel ect = 00 19 1 0 clkctrl_enet Ba nk 4 sel ect = 01 sel ect = 10 sel ect GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO = 11 12 11 10 9 8 7 6 5 4 emi_data4 emi_data5 emi_data6 emi_data7 emi_data8 emi_data9 emi_data10 emi_data11 emi_data12 emi_data13 emi_data14 sel ect = 00 emi_data15 Mu x Re 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 g 10 3 8 7 2 6 5 1 4 3 0 2 1 0 emi_data0 13 emi_data1 14 emi_data2 15 emi_data3 Ba nk 5 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 710 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Table 9-2. Pin Multiplexing for the 289-pin Package (continued) sel ect = 01 sel ect = 10 sel ect disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl = ed ed ed ed ed ed ed ed ed ed ed ed ed ed ed ed 11 28 27 26 25 24 23 22 21 20 8 emi_ddr_open_feedback emi_clk emi_dqs0 sel ect = 00 emi_dqs1 emi_ddr_open Mu x Re 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 g 11 19 7 18 6 5 17 4 3 16 2 1 0 emi_odt0 29 emi_dqm0 30 emi_odt1 31 emi_dqm1 Ba nk 5 sel ect = 01 sel ect = 10 sel ect = 11 Ba nk 6 disabl ed 15 14 13 12 11 10 disabl disabl disabl disabl disabl disabl disabl disabl ed ed ed ed ed ed ed ed 9 8 7 6 5 Mu x Re 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 g 12 4 3 8 7 2 6 5 1 4 3 0 2 1 0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 711 Operation emi_addr0 emi_addr1 emi_addr2 emi_addr3 emi_addr4 emi_addr5 emi_addr6 emi_addr7 emi_addr8 emi_addr9 emi_addr10 emi_addr11 emi_addr12 emi_addr14 sel ect = 00 emi_addr13 Table 9-2. Pin Multiplexing for the 289-pin Package (continued) sel ect = 01 sel ect = 10 sel ect = 11 28 26 25 24 23 22 21 20 emi_rasn emi_wen emi_ce0n emi_ce1n sel ect = 00 emi_cke Mu x Re 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 g 13 19 8 7 18 6 5 17 4 3 16 2 1 0 emi_ba0 29 emi_ba1 30 emi_ba2 31 emi_casn Ba nk 6 disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl disabl ed ed ed ed ed ed ed ed ed ed ed ed ed ed ed sel ect = 01 sel ect = 10 sel ect = 11 disabl disabl disabl disabl disabl disabl disabl disabl disabl ed ed ed ed ed ed ed ed ed Readback registers are never affected by the operation of the HW_PINCTRL_MUXSELx registers and always sense the actual value on the data pin. For example, if a pin is programmed to be a GPIO output and then driven high, then any specialized hardware interfaces that are actively monitoring that pin will read the high logic value. Conversely, if the pin mux is programmed to give a specialized hardware interface such as the GPMI block control of a particular pin, the current state of that pin i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 712 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) can be read through its GPIO read register at any time, even while active GPMI cycles are in progress. This is not true for the EMI pads that are GPIO capable due to the pad design. Because the pin mux configuration is independent for each individual pin, many pins which are not required for a given active interface can be reused as GPIO pins. For example, the LCD_RESET pin can be configured and controlled as a GPIO pin, while the other LCD interface pins are still controlled by the LCDIF. Banks 5 and 6 are for the EMI only and do not have GPIO capability. 9.2.2.1 Pin Drive Strength Selection The drive strength for each digital pin can be programmed by setting the bit corresponding to that pin in one of the HW_PINCTRL_DRIVEx registers. All digital pins have selectable output drive strengths of 4, 8, and 12 mA, with the following exceptions: * All clock pads have 8 and 16mA drive strength. * All EMI pads have 5, 10 and 20 mA drive strengths. Note The HW_PINCTRL_DRIVEx registers must be configured prior to the operation of the pins and cannot be changed mid-course during active operation. Drive-strength options are provided to optimize simultaneous switching output (SSO) noise. The majority of GPIO pins must be programmed in 4-mA mode. For EMI pins, the weakest mode should be used as long as the timing is met. Note It is recommended that the drive strength of GPMI_RDn and GPMI_WRn output pins be set to 8 mA. This will reduce the transition time under heavy loads. Low transition times will be important when NAND interface read and write cycle times are below 30 ns. The other GPMI pins may remain at 4 mA, since their frequency is only up to half that of GPMI_RDn and GPMI_WRn. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 713 Operation 9.2.2.2 Pin Voltage Selection Each GPIO (non-EMI) pin can be programmed to operate at either 1.8 V or 3.3 V by setting the bit corresponding to that pin in one of the HW_PINCTRL_DRIVEx registers. The EMI pins are capable of running at 1.5/1.8 V depending on the EMI_VDDIO voltage. Note The GPIO pad driver has two PMOS pullup drivers directly connected to the 1.8 or 3.3-V power supply. 9.2.2.3 Pullup Selection Several digital pins can be programmed to enable pullups by setting the appropriate bit in one of the HW_PINCTRL_PULLx registers. Note that enabling the pullup will also disable the internal gate keeper on that pin. The EMI pads do not have pullup selection, but do have keeper disable capability. The pullups are tied to the physical pin pad and not to the function. So, for example, if the AUART1_TX pullup is enabled, that pullup will be present on the AUART1_TX pin regardless of what function (AUART1_TX, IR_TX, or SSP1_DATA7) is pin multiplexed out of that pin. The table below lists which function (not which pin name), an internal pullup has been implemented, to assist in the hardware interfaces' operation. Table 9-3. i.MX28 Functions with Pullup Resistors FUNCTION Type Value Present on 289BGA Present on 204pins SSP0_DATA0 Pullup 47K Y Y SSP0_DATA1 Pullup 47K Y Y SSP0_DATA2 Pullup 47K Y Y SSP0_DATA3 Pullup 47K Y Y SSP0_DATA4 Pullup 47K Y Y SSP0_DATA5 Pullup 47K Y Y SSP0_DATA6 Pullup 47K Y Y SSP0_DATA7 Pullup 47K Y Y SSP0_CMD Pullup 10K Y Y SSP0_DETECT Pullup 10K Y Y SSP1_DATA0 Pullup 47K Y Y SSP1_DATA1 Pullup 47K Y Y SSP1_DATA2 Pullup 47K Y Y Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 714 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Table 9-3. i.MX28 Functions with Pullup Resistors (continued) FUNCTION Type Value Present on 289BGA Present on 204pins SSP1_DATA3 Pullup 47K Y Y SSP1_DATA4 Pullup 47K Y Y SSP1_DATA5 Pullup 47K Y Y SSP1_DATA6 Pullup 47K Y Y SSP1_DATA7 Pullup 47K Y Y SSP1_CMD Pullup 10K Y Y SSP1_DETECT Pullup 10K Y Y SSP2_DATA0 Pullup 47K Y Y SSP2_DATA1 Pullup 47K Y Y SSP2_DATA2 Pullup 47K Y Y SSP2_DATA3 Pullup 47K Y Y SSP2_DATA4 Pullup 47K Y Y SSP2_DATA5 Pullup 47K Y Y SSP2_DATA6 Pullup 47K Y N SSP2_DATA7 Pullup 47K Y N SSP2_CMD Pullup 10K Y Y SSP2_DETECT Pullup 10K Y Y SSP3_DATA0 Pullup 47K Y Y SSP3_DATA1 Pullup 47K Y Y SSP3_DATA2 Pullup 47K Y Y SSP3_DATA3 Pullup 47K Y Y SSP3_DATA4 Pullup 47K Y Y SSP3_DATA5 Pullup 47K Y Y SSP3_DATA6 Pullup 47K Y N SSP3_DATA7 Pullup 47K Y N SSP3_CMD Pullup 10K Y Y SSP3_DETECT Pullup 10K Y Y GPMI_CE0N Pullup 47K Y Y GPMI_CE1N Pullup 47K Y Y GPMI_CE2N Pullup 47K Y N GPMI_CE3N Pullup 47K Y N GPMI_RDY0 Pullup 10K Y Y GPMI_RDY1 Pullup 10K Y Y GPMI_RDY2 Pullup 10K Y N GPMI_RDY3 Pullup 10K Y N i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 715 Operation 9.2.3 GPIO Interface The registers discussed in the following sections exist within each of the three GPIO banks to configure the chip's digital pins. Some pins exist in the 289-pin package only. The registers that control those pins exist but do not perform any useful function when in a 204-pin package. 9.2.3.1 Output Operation Programming and controlling a digital pin as a GPIO output is accomplished by programming the appropriate bits in four registers, as shown in the figure below. * After setting the field in the HW_PINCTRL_MUXSELx to program for GPIO control, the HW_PINCTRL_DRIVEx register bit is set for the desired drive strength and pin voltage. Set bits in HW_PINCTRL_PULLx as required to enable pullups. * The HW_PINCTRL_DOUTx register bit is then loaded with the level that will initially be driven on the pin. * Finally, the HW_PINCTRL_DOEx register bit is set. * Once set, the logic value the HW_PINCTRL_DOUTx bit will be driven on the pin and the value can be toggled with repeated writes. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 716 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Begin Write to HW_PINCTRL_MUXSELx register bit to select pin as GPIO. Write to HW_PINCTRL_DRIVEx register bit to set current drive strength. Set bits in HW_PINCTRL_PULLx as required to enable pullups. Write to HW_PINCTRL_DOUTx register bit to set the output value to drive on the pin. Write to HW_PINCTRL_DOEx register bit to enable the data value to be driven on the pin. Re-write the HW_PINCTRL_DOUTx register bit to change the value driven on the pin. End Figure 9-2. GPIO Output Setup Flowchart 9.2.3.2 Input Operation Digital pins in Banks 0~4 may be used as a GPIO input by programming its HW_PINCTRL_MUXSELx field to 3 to enable GPIO mode, programming its HW_PINCTRL_DOEx field to 0 to disable output, and then reading from the HW_PINCTRL_DINx register, as shown in the figure below. Note that because of clock synchronization issues, the logic levels read from the HW_PINCTRL_DINx registers are delayed from the pins by several APBX clock cycles. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 717 Operation Begin Write to HW_PINCTRL_MUXSELx register bit to select pin as GPIO. Write zero to HW_PINCTRL_DOEx register bit to ensure pin is selected as an input. If applicable, set bits in HW_PINCTRL_PULLx to enable internal pull-up resistors. Read HW_PINCTRL_DINx register bit to get the value on the pin. End Figure 9-3. GPIO Input Setup Flowchart 9.2.3.3 Input Interrupt Operation Programming and controlling a digital pin as a GPIO interrupt input is accomplished by programming the appropriate bits in six registers, as shown in the figure below. * After setting the HW_PINCTRL_MUXSELx register for GPIO, the HW_PINCTRL_IRQLEVELx and HW_PINCTRL_IRQPOLx registers set the interrupt trigger mode. A GPIO interrupt pin can be programmed in one of four trigger detect modes: positive edge, negative edge, positive level, and negative level triggered. * The HW_PINCTRL_IRQSTATx register bit should then be cleared to ensure that there are no interrupts pending when enabled. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 718 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) * Setting the HW_PINCTRL_PIN2IRQx register bit will then set up the pin to be an interrupt pin. * At this point, if an interrupt event occurs on the pin, it will be sensed and recorded in the appropriate HW_PINCTRL_IRQSTATx bit. * However, the interrupt will not be communicated back to the interrupt collector until the HW_PINCTRL_IRQENx register bit is enabled. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 719 Operation Begin Write to HW_PINCTRL_MUXSELx register bit to select pin as GPIO. Write zero to HW_PINCTRL_DOEx register bit to ensure pin is selected as an input. If applicable, set bits in HW_PINCTRL_PULLx to enable internal pull-up resistors. Write to HW_PINCTRL_IRQLEVELx register bit to set level or edge assertion. Write to HW_PINCTRL_IRQPOLx register bit to set high or low logic assertion. Write zero to HW_PINCTRL_IRQSTATx register bit to clear interrupts. Write to HW_PINCTRL_PIN2IRQx register bit to enable as an interrupt pin. Write to HW_PINCTRL_IRQENx register bit to enable the interrupt signal back to the Interrupt collector. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 720 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) The figure below shows the logic diagram for the interrupt-generation circuit. 1 HW_PINCTRL_CTRL [hw_pinctrl_ctrl_irqoutb] HW_PINCTRL_IRQPOLxb Internal Register from other 31 bits FALL HW_PINCTRL_PIN2IRQxb HW_PINCTRL_IRQENxb edge level RISE LOW HW_PINCTRL_IRQLEVELxb HIGH HW_PINCTRL_DINxb sync pin GPxBb SCT Clear write to GPIOx & (apb_wdata[b]== 1) HW_PINCTRL_STATxb PINCTRL_IRQx to CPU Figure 9-5. GPIO Interrupt Generation 9.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. ENET pins will not be affected by SFTRST, it only resets when power is on. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 721 Pin Control Memory Map/Register Definition 9.4 Pin Control Memory Map/Register Definition PINCTRL Hardware Register Format Summary HW_PINCTRL memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8001_8000 PINCTRL Block Control Register (HW_PINCTRL_CTRL) 32 R/W C1F0_0000h 9.4.1/726 8001_8100 PINCTRL Pin Mux Select Register 0 (HW_PINCTRL_MUXSEL0) 32 R/W 0000_FFFFh 9.4.2/727 8001_8110 PINCTRL Pin Mux Select Register 1 (HW_PINCTRL_MUXSEL1) 32 R/W 03FF_FFFFh 9.4.3/729 8001_8120 PINCTRL Pin Mux Select Register 2 (HW_PINCTRL_MUXSEL2) 32 R/W FFFF_FFFFh 9.4.4/732 8001_8130 PINCTRL Pin Mux Select Register 3 (HW_PINCTRL_MUXSEL3) 32 R/W FFFF_FFFFh 9.4.5/734 8001_8140 PINCTRL Pin Mux Select Register 4 (HW_PINCTRL_MUXSEL4) 32 R/W FF3F_FFFFh 9.4.6/737 8001_8150 PINCTRL Pin Mux Select Register 5 (HW_PINCTRL_MUXSEL5) 32 R/W 00FF_0FFFh 9.4.7/740 8001_8160 PINCTRL Pin Mux Select Register 6 (HW_PINCTRL_MUXSEL6) 32 R/W FFFF_FFFFh 9.4.8/742 8001_8170 PINCTRL Pin Mux Select Register 7 (HW_PINCTRL_MUXSEL7) 32 R/W 3FFF_FF3Fh 9.4.9/745 8001_8180 PINCTRL Pin Mux Select Register 8 (HW_PINCTRL_MUXSEL8) 32 R/W FFFF_FFFFh 9.4.10/747 8001_8190 PINCTRL Pin Mux Select Register 9 (HW_PINCTRL_MUXSEL9) 32 R/W 0000_0003h 9.4.11/750 8001_81A0 PINCTRL Pin Mux Select Register 10 (HW_PINCTRL_MUXSEL10) 32 R/W FFFF_FFFFh 9.4.12/751 8001_81B0 PINCTRL Pin Mux Select Register 11 (HW_PINCTRL_MUXSEL11) 32 R/W 0030_FFFFh 9.4.13/754 8001_81C0 PINCTRL Pin Mux Select Register 12 (HW_PINCTRL_MUXSEL12) 32 R/W 3FFF_FFFFh 9.4.14/756 8001_81D0 PINCTRL Pin Mux Select Register 13 (HW_PINCTRL_MUXSEL13) 32 R/W 0003_FFFFh 9.4.15/759 8001_8300 PINCTRL Drive Strength and Voltage Register 0 (HW_PINCTRL_DRIVE0) 32 R/W 4444_4444h 9.4.16/761 8001_8310 PINCTRL Drive Strength and Voltage Register 1 (HW_PINCTRL_DRIVE1) 32 R/W 0000_0000h 9.4.17/764 8001_8320 PINCTRL Drive Strength and Voltage Register 2 (HW_PINCTRL_DRIVE2) 32 R/W 4444_4444h 9.4.18/765 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 722 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8001_8330 PINCTRL Drive Strength and Voltage Register 3 (HW_PINCTRL_DRIVE3) 32 R/W 0004_4444h 9.4.19/769 8001_8340 PINCTRL Drive Strength and Voltage Register 4 (HW_PINCTRL_DRIVE4) 32 R/W 4444_4444h 9.4.20/771 8001_8350 PINCTRL Drive Strength and Voltage Register 5 (HW_PINCTRL_DRIVE5) 32 R/W 4444_4444h 9.4.21/775 8001_8360 PINCTRL Drive Strength and Voltage Register 6 (HW_PINCTRL_DRIVE6) 32 R/W 4444_4444h 9.4.22/778 8001_8370 PINCTRL Drive Strength and Voltage Register 7 (HW_PINCTRL_DRIVE7) 32 R/W 4444_4444h 9.4.23/782 8001_8380 PINCTRL Drive Strength and Voltage Register 8 (HW_PINCTRL_DRIVE8) 32 R/W 4444_4444h 9.4.24/785 8001_8390 PINCTRL Drive Strength and Voltage Register 9 (HW_PINCTRL_DRIVE9) 32 R/W 4444_0444h 9.4.25/789 8001_83A0 PINCTRL Drive Strength and Voltage Register 10 (HW_PINCTRL_DRIVE10) 32 R/W 0044_4444h 9.4.26/792 8001_83B0 PINCTRL Drive Strength and Voltage Register 11 (HW_PINCTRL_DRIVE11) 32 R/W 0000_4444h 9.4.27/795 8001_83C0 PINCTRL Drive Strength and Voltage Register 12 (HW_PINCTRL_DRIVE12) 32 R/W 4444_4444h 9.4.28/797 8001_83D0 PINCTRL Drive Strength and Voltage Register 13 (HW_PINCTRL_DRIVE13) 32 R/W 4444_4444h 9.4.29/801 8001_83E0 PINCTRL Drive Strength and Voltage Register 14 (HW_PINCTRL_DRIVE14) 32 R/W 4444_0444h 9.4.30/805 8001_83F0 PINCTRL Drive Strength and Voltage Register 15 (HW_PINCTRL_DRIVE15) 32 R/W 0444_4444h 9.4.31/808 8001_8400 PINCTRL Drive Strength and Voltage Register 16 (HW_PINCTRL_DRIVE16) 32 R/W 4444_4444h 9.4.32/811 8001_8410 PINCTRL Drive Strength and Voltage Register 17 (HW_PINCTRL_DRIVE17) 32 R/W 4444_4444h 9.4.33/815 8001_8420 PINCTRL Drive Strength and Voltage Register 18 (HW_PINCTRL_DRIVE18) 32 R/W 0004_0004h 9.4.34/818 8001_8430 PINCTRL Drive Strength and Voltage Register 19 (HW_PINCTRL_DRIVE19) 32 R 0000_0000h 9.4.35/820 8001_8600 PINCTRL Bank 0 Pull Up Resistor Enable Register (HW_PINCTRL_PULL0) 32 R/W 0000_0000h 9.4.36/821 8001_8610 PINCTRL Bank 1 Pull Up Resistor Enable Register (HW_PINCTRL_PULL1) 32 R/W 0000_0000h 9.4.37/823 8001_8620 PINCTRL Bank 2 Pull Up Resistor Enable Register (HW_PINCTRL_PULL2) 32 R/W 0000_0000h 9.4.38/826 8001_8630 PINCTRL Bank 3 Pull Up Resistor Enable Register (HW_PINCTRL_PULL3) 32 R/W 0000_0000h 9.4.39/828 8001_8640 PINCTRL Bank 4 Pull Up Resistor Enable Register (HW_PINCTRL_PULL4) 32 R/W 0000_0000h 9.4.40/831 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 723 Pin Control Memory Map/Register Definition HW_PINCTRL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8001_8650 PINCTRL Bank 5 Pad Keeper Disable Register (HW_PINCTRL_PULL5) 32 R/W 0000_0000h 9.4.41/833 8001_8660 PINCTRL Bank 6 Pad Keeper Disable Register (HW_PINCTRL_PULL6) 32 R/W 0000_0000h 9.4.42/836 8001_8700 PINCTRL Bank 0 Data Output Register (HW_PINCTRL_DOUT0) 32 R/W 0000_0000h 9.4.43/838 8001_8710 PINCTRL Bank 1 Data Output Register (HW_PINCTRL_DOUT1) 32 R/W 0000_0000h 9.4.44/839 8001_8720 PINCTRL Bank 2 Data Output Register (HW_PINCTRL_DOUT2) 32 R/W 0000_0000h 9.4.45/840 8001_8730 PINCTRL Bank 3 Data Output Register (HW_PINCTRL_DOUT3) 32 R/W 0000_0000h 9.4.46/840 8001_8740 PINCTRL Bank 4 Data Output Register (HW_PINCTRL_DOUT4) 32 R/W 0000_0000h 9.4.47/842 8001_8900 PINCTRL Bank 0 Data Input Register (HW_PINCTRL_DIN0) 32 R 0000_0000h 9.4.48/842 8001_8910 PINCTRL Bank 1 Data Input Register (HW_PINCTRL_DIN1) 32 R 0000_0000h 9.4.49/843 8001_8920 PINCTRL Bank 2 Data Input Register (HW_PINCTRL_DIN2) 32 R 0000_0000h 9.4.50/844 8001_8930 PINCTRL Bank 3 Data Input Register (HW_PINCTRL_DIN3) 32 R 0000_0000h 9.4.51/845 8001_8940 PINCTRL Bank 4 Data Input Register (HW_PINCTRL_DIN4) 32 R 0000_0000h 9.4.52/846 8001_8B00 PINCTRL Bank 0 Data Output Enable Register (HW_PINCTRL_DOE0) 32 R/W 0000_0000h 9.4.53/847 8001_8B10 PINCTRL Bank 1 Data Output Enable Register (HW_PINCTRL_DOE1) 32 R/W 0000_0000h 9.4.54/847 8001_8B20 PINCTRL Bank 2 Data Output Enable Register (HW_PINCTRL_DOE2) 32 R/W 0000_0000h 9.4.55/848 8001_8B30 PINCTRL Bank 3 Data Output Enable Register (HW_PINCTRL_DOE3) 32 R/W 0000_0000h 9.4.56/849 8001_8B40 PINCTRL Bank 4 Data Output Enable Register (HW_PINCTRL_DOE4) 32 R/W 0000_0000h 9.4.57/850 8001_9000 PINCTRL Bank 0 Interrupt Select Register (HW_PINCTRL_PIN2IRQ0) 32 R/W 0000_0000h 9.4.58/851 8001_9010 PINCTRL Bank 1 Interrupt Select Register (HW_PINCTRL_PIN2IRQ1) 32 R/W 0000_0000h 9.4.59/852 8001_9020 PINCTRL Bank 2 Interrupt Select Register (HW_PINCTRL_PIN2IRQ2) 32 R/W 0000_0000h 9.4.60/852 8001_9030 PINCTRL Bank 3 Interrupt Select Register (HW_PINCTRL_PIN2IRQ3) 32 R/W 0000_0000h 9.4.61/853 8001_9040 PINCTRL Bank 4 Interrupt Select Register (HW_PINCTRL_PIN2IRQ4) 32 R/W 0000_0000h 9.4.62/855 8001_9100 PINCTRL Bank 0 Interrupt Mask Register (HW_PINCTRL_IRQEN0) 32 R/W 0000_0000h 9.4.63/856 8001_9110 PINCTRL Bank 1 Interrupt Mask Register (HW_PINCTRL_IRQEN1) 32 R/W 0000_0000h 9.4.64/856 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 724 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8001_9120 PINCTRL Bank 2 Interrupt Mask Register (HW_PINCTRL_IRQEN2) 32 R/W 0000_0000h 9.4.65/857 8001_9130 PINCTRL Bank 3 Interrupt Mask Register (HW_PINCTRL_IRQEN3) 32 R/W 0000_0000h 9.4.66/858 8001_9140 PINCTRL Bank 4 Interrupt Mask Register (HW_PINCTRL_IRQEN4) 32 R/W 0000_0000h 9.4.67/859 8001_9200 PINCTRL Bank 0 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL0) 32 R/W 0000_0000h 9.4.68/860 8001_9210 PINCTRL Bank 1 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL1) 32 R/W 0000_0000h 9.4.69/861 8001_9220 PINCTRL Bank 2 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL2) 32 R/W 0000_0000h 9.4.70/862 8001_9230 PINCTRL Bank 3 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL3) 32 R/W 0000_0000h 9.4.71/862 8001_9240 PINCTRL Bank 4 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL4) 32 R/W 0000_0000h 9.4.72/864 8001_9300 PINCTRL Bank 0 Interrupt Polarity Register (HW_PINCTRL_IRQPOL0) 32 R/W 0000_0000h 9.4.73/864 8001_9310 PINCTRL Bank 1 Interrupt Polarity Register (HW_PINCTRL_IRQPOL1) 32 R/W 0000_0000h 9.4.74/865 8001_9320 PINCTRL Bank 2 Interrupt Polarity Register (HW_PINCTRL_IRQPOL2) 32 R/W 0000_0000h 9.4.75/866 8001_9330 PINCTRL Bank 3 Interrupt Polarity Register (HW_PINCTRL_IRQPOL3) 32 R/W 0000_0000h 9.4.76/867 8001_9340 PINCTRL Bank 4 Interrupt Polarity Register (HW_PINCTRL_IRQPOL4) 32 R/W 0000_0000h 9.4.77/868 8001_9400 PINCTRL Bank 0 Interrupt Status Register (HW_PINCTRL_IRQSTAT0) 32 R/W 0000_0000h 9.4.78/869 8001_9410 PINCTRL Bank 1 Interrupt Status Register (HW_PINCTRL_IRQSTAT1) 32 R/W 0000_0000h 9.4.79/870 8001_9420 PINCTRL Bank 2 Interrupt Status Register (HW_PINCTRL_IRQSTAT2) 32 R/W 0000_0000h 9.4.80/870 8001_9430 PINCTRL Bank 3 Interrupt Status Register (HW_PINCTRL_IRQSTAT3) 32 R/W 0000_0000h 9.4.81/871 8001_9440 PINCTRL Bank 4 Interrupt Status Register (HW_PINCTRL_IRQSTAT4) 32 R/W 0000_0000h 9.4.82/873 8001_9A40 PINCTRL EMI Slice ODT Control (HW_PINCTRL_EMI_ODT_CTRL) 32 R/W 0888_8888h 9.4.83/874 8001_9B80 PINCTRL EMI Slice DS Control (HW_PINCTRL_EMI_DS_CTRL) 32 R/W 0003_0000h 9.4.84/878 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 725 Pin Control Memory Map/Register Definition 9.4.1 PINCTRL Block Control Register (HW_PINCTRL_CTRL) The PINCTRL Block Control Register contains the block control bits and combined interrupt output status for each PINCTRL bank. HW_PINCTRL_CTRL: 0x000 HW_PINCTRL_CTRL_SET: 0x004 HW_PINCTRL_CTRL_CLR: 0x008 HW_PINCTRL_CTRL_TOG: 0x00C This register contains block-wide control bits and combined bank interrupt status bits. For normal operation, write a 0x0 into this register. Address: 8001_8000h base + 0h offset = 8001_8000h 20 19 18 17 16 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQOUT0 21 IRQOUT1 22 IRQOUT2 23 IRQOUT3 24 PRESENT0 25 IRQOUT4 26 PRESENT1 27 PRESENT2 28 PRESENT3 29 PRESENT4 30 CLKGATE 31 SFTRST Bit 0 0 0 0 0 0 0 0 0 0 RSRVD2 R RSRVD1 W Reset Bit RSRVD1 R W Reset 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 726 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_CTRL field descriptions Field Description 31 SFTRST This bit must be set to zero to enable operation of any of the PINCTRL banks. When set to one, it forces a block-level reset. 30 CLKGATE 29-25 RSRVD2 This bit must be set to zero for normal operation. When set to one, it disables the block clock. Always write zeroes to this field. 24 PRESENT4 GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 4 is not present in this product. 1: GPIO functionality for Bank 4 is present. 23 PRESENT3 GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 3 is not present in this product. 1: GPIO functionality for Bank 3 is present. 22 PRESENT2 GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 2 is not present in this product. 1: GPIO functionality for Bank 2 is present. 21 PRESENT1 GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 1 is not present in this product. 1: GPIO functionality for Bank 1 is present. 20 PRESENT0 GPIO Functionality Present. 0: GPIO functionality for Pin Control Bank 0 is not present in this product. 1: GPIO functionality for Bank 0 is present. 19-5 RSRVD1 Always write zeroes to this field. 4 IRQOUT4 Read-only view of the interrupt collector GPIO4 signal, sourced from the combined IRQ outputs from bank 4. 3 IRQOUT3 Read-only view of the interrupt collector GPIO3 signal, sourced from the combined IRQ outputs from bank 3. 2 IRQOUT2 Read-only view of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 2. 1 IRQOUT1 Read-only view of the interrupt collector GPIO1 signal, sourced from the combined IRQ outputs from bank 1. 0 IRQOUT0 Read-only view of the interrupt collector GPIO0 signal, sourced from the combined IRQ outputs from bank 0. 9.4.2 PINCTRL Pin Mux Select Register 0 (HW_PINCTRL_MUXSEL0) The PINCTRL Pin Mux Select Register provides pin function selection for 8 pins in bank0. HW_PINCTRL_MUXSEL0: 0x100 HW_PINCTRL_MUXSEL0_SET: 0x104 HW_PINCTRL_MUXSEL0_CLR: 0x108 HW_PINCTRL_MUXSEL0_TOG: 0x10C This register allows the programmer to select which hardware interface blocks drive the 8 pins shown above. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 727 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 100h offset = 8001_8100h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R W Reset Bit R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK0_ PIN07 BANK0_ PIN06 BANK0_ PIN05 BANK0_ PIN04 BANK0_ PIN03 BANK0_ PIN02 BANK0_ PIN01 BANK0_ PIN00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_PINCTRL_MUXSEL0 field descriptions Field 31-16 RSRVD0 15-14 BANK0_PIN07 Description Always write zeroes to this field. Pin 124, GPMI_D07 pin function selection: 00= gpmi_d7; 01= ssp1_d7; 10= reserved; 11= GPIO. 13-12 BANK0_PIN06 Pin 130, GPMI_D06 pin function selection: 00= gpmi_d6; 01= ssp1_d6; 10= reserved; 11= GPIO. 11-10 BANK0_PIN05 Pin 116, GPMI_D05 pin function selection: 00= gpmi_d5; 01= ssp1_d5; 10= reserved; 11= GPIO. 9-8 BANK0_PIN04 Pin 128, GPMI_D04 pin function selection: 00= gpmi_d4; 01= ssp1_d4; 10= reserved; 11= GPIO. 7-6 BANK0_PIN03 Pin 132, GPMI_D03 pin function selection: 00= gpmi_d3; 01= ssp1_d3; 10= reserved; 11= GPIO. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 728 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL0 field descriptions (continued) Field Description 5-4 BANK0_PIN02 Pin 126, GPMI_D02 pin function selection: 00= gpmi_d2; 01= ssp1_d2; 10= reserved; 11= GPIO. 3-2 BANK0_PIN01 Pin 136, GPMI_D01 pin function selection: 00= gpmi_d1; 01= ssp1_d1; 10= reserved; 11= GPIO. BANK0_PIN00 Pin 134, GPMI_D00 pin function selection: 00= gpmi_d0; 01= ssp1_d0; 10= reserved; 11= GPIO. 9.4.3 PINCTRL Pin Mux Select Register 1 (HW_PINCTRL_MUXSEL1) The PINCTRL Pin Mux Select Register provides pin function selection for 13 pins in bank0. HW_PINCTRL_MUXSEL1: 0x110 HW_PINCTRL_MUXSEL1_SET: 0x114 HW_PINCTRL_MUXSEL1_CLR: 0x118 HW_PINCTRL_MUXSEL1_TOG: 0x11C This register allows the programmer to select which hardware interface blocks drive the 13 pins shown above. Address: 8001_8000h base + 110h offset = 8001_8110h Bit 31 30 29 28 27 26 RSRVD0 R W Reset 0 0 0 0 0 0 25 24 23 22 21 20 19 18 17 16 BANK0_ PIN28 BANK0_ PIN27 BANK0_ PIN26 BANK0_ PIN25 BANK0_ PIN24 1 1 1 1 1 1 1 1 1 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 729 Pin Control Memory Map/Register Definition 15 Bit R W Reset 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK0_ PIN23 BANK0_ PIN22 BANK0_ PIN21 BANK0_ PIN20 BANK0_ PIN19 BANK0_ PIN18 BANK0_ PIN17 BANK0_ PIN16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_PINCTRL_MUXSEL1 field descriptions Field 31-26 RSRVD0 25-24 BANK0_PIN28 Description Always write zeroes to this field. Pin 129, GPMI_RESETN pin function selection: 00= gpmi_resetn; 01= ssp3_cmd; 10= reserved; 11= GPIO. 23-22 BANK0_PIN27 Pin 123, GPMI_CLE pin function selection: 00= gpmi_cle; 01= ssp3_d2; 10= ssp3_d5; 11= GPIO. 21-20 BANK0_PIN26 Pin 117, GPMI_ALE pin function selection: 00= gpmi_ale; 01= ssp3_d1; 10= ssp3_d4; 11= GPIO. 19-18 BANK0_PIN25 Pin 127, GPMI_WRN pin function selection: 00= gpmi_wrn; 01= ssp1_sck; 10= reserved; 11= GPIO. 17-16 BANK0_PIN24 Pin 110, GPMI_RDN pin function selection: 00= gpmi_rdn; 01= ssp3_sck; 10= reserved; 11= GPIO. 15-14 BANK0_PIN23 Pin 80, GPMI_RDY3 pin function selection: 00= gpmi_ready3; 01= can0_rx; 10= hsadc_trigger; 11= GPIO. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 730 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL1 field descriptions (continued) Field 13-12 BANK0_PIN22 Description Pin 88, GPMI_RDY2 pin function selection: 00= gpmi_ready2; 01= can0_tx; 10= enet0_tx_er; 11= GPIO. 11-10 BANK0_PIN21 Pin 119, GPMI_RDY1 pin function selection: 00= gpmi_ready1; 01= ssp1_cmd; 10= reserved; 11= GPIO. 9-8 BANK0_PIN20 Pin 103, GPMI_RDY0 pin function selection: 00= gpmi_ready0; 01= ssp1_card_detect; 10= usb0_id; 11= GPIO. 7-6 BANK0_PIN19 Pin 135, GPMI_CE3N pin function selection: 00= gpmi_ce3n; 01= can1_rx; 10= saif1_mclk; 11= GPIO. 5-4 BANK0_PIN18 Pin 92, GPMI_CE2N pin function selection: 00= gpmi_ce2n; 01= can1_tx; 10= enet0_rx_er; 11= GPIO. 3-2 BANK0_PIN17 Pin 131, GPMI_CE1N pin function selection: 00= gpmi_ce1n; 01= ssp3_d3; 10= reserved; 11= GPIO. BANK0_PIN16 Pin 115, GPMI_CE0N pin function selection: 00= gpmi_ce0n; 01= ssp3_d0; 10= reserved; 11= GPIO. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 731 Pin Control Memory Map/Register Definition 9.4.4 PINCTRL Pin Mux Select Register 2 (HW_PINCTRL_MUXSEL2) The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank1. HW_PINCTRL_MUXSEL2: 0x120 HW_PINCTRL_MUXSEL2_SET: 0x124 HW_PINCTRL_MUXSEL2_CLR: 0x128 HW_PINCTRL_MUXSEL2_TOG: 0x12C This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. Address: 8001_8000h base + 120h offset = 8001_8120h Bit 31 R W Reset Bit R W Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BANK1_ PIN15 BANK1_ PIN14 BANK1_ PIN13 BANK1_ PIN12 BANK1_ PIN11 BANK1_ PIN10 BANK1_ PIN09 BANK1_ PIN08 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK1_ PIN07 BANK1_ PIN06 BANK1_ PIN05 BANK1_ PIN04 BANK1_ PIN03 BANK1_ PIN02 BANK1_ PIN01 BANK1_ PIN00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_PINCTRL_MUXSEL2 field descriptions Field 31-30 BANK1_PIN15 Description Pin 114, LCD_D15 pin function selection: 00= lcd_d15; 01= reserved; 10= etm_da15; 11= GPIO. 29-28 BANK1_PIN14 Pin 106, LCD_D14 pin function selection: 00= lcd_d14; 01= reserved; 10= etm_da14; 11= GPIO. 27-26 BANK1_PIN13 Pin 102, LCD_D13 pin function selection: 00= lcd_d13; 01= reserved; 10= etm_da13; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 732 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL2 field descriptions (continued) Field Description 11= GPIO. 25-24 BANK1_PIN12 Pin 87, LCD_D12 pin function selection: 00= lcd_d12; 01= reserved; 10= etm_da12; 11= GPIO. 23-22 BANK1_PIN11 Pin 95, LCD_D11 pin function selection: 00= lcd_d11; 01= reserved; 10= etm_da11; 11= GPIO. 21-20 BANK1_PIN10 Pin 85, LCD_D10 pin function selection: 00= lcd_d10; 01= reserved; 10= etm_da10; 11= GPIO. 19-18 BANK1_PIN09 Pin 99, LCD_D09 pin function selection: 00= lcd_d9; 01= etm_da4; 10= etm_da9; 11= GPIO. 17-16 BANK1_PIN08 Pin 93, LCD_D08 pin function selection: 00= lcd_d8; 01= etm_da3; 10= etm_da8; 11= GPIO. 15-14 BANK1_PIN07 Pin 75, LCD_D07 pin function selection: 00= lcd_d7; 01= reserved; 10= etm_da7; 11= GPIO. 13-12 BANK1_PIN06 Pin 91, LCD_D06 pin function selection: 00= lcd_d6; 01= reserved; 10= etm_da6; 11= GPIO. 11-10 BANK1_PIN05 Pin 89, LCD_D05 pin function selection: 00= lcd_d5; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 733 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL2 field descriptions (continued) Field Description 01= reserved; 10= etm_da5; 11= GPIO. 9-8 BANK1_PIN04 Pin 79, LCD_D04 pin function selection: 00= lcd_d4; 01= etm_da9; 10= etm_da4; 11= GPIO. 7-6 BANK1_PIN03 Pin 77, LCD_D03 pin function selection: 00= lcd_d3; 01= etm_da8; 10= etm_da3; 11= GPIO. 5-4 BANK1_PIN02 Pin 67, LCD_D02 pin function selection: 00= lcd_d2; 01= reserved; 10= etm_da2; 11= GPIO. 3-2 BANK1_PIN01 Pin 69, LCD_D01 pin function selection: 00= lcd_d1; 01= reserved; 10= etm_da1; 11= GPIO. BANK1_PIN00 Pin 63, LCD_D00 pin function selection: 00= lcd_d0; 01= reserved; 10= etm_da0; 11= GPIO. 9.4.5 PINCTRL Pin Mux Select Register 3 (HW_PINCTRL_MUXSEL3) The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank1. HW_PINCTRL_MUXSEL3: 0x130 HW_PINCTRL_MUXSEL3_SET: 0x134 HW_PINCTRL_MUXSEL3_CLR: 0x138 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 734 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL3_TOG: 0x13C This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. Address: 8001_8000h base + 130h offset = 8001_8130h Bit 31 R W Reset Bit R W Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BANK1_ PIN31 BANK1_ PIN30 BANK1_ PIN29 BANK1_ PIN28 BANK1_ PIN27 BANK1_ PIN26 BANK1_ PIN25 BANK1_ PIN24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK1_ PIN23 BANK1_ PIN22 BANK1_ PIN21 BANK1_ PIN20 BANK1_ PIN19 BANK1_ PIN18 BANK1_ PIN17 BANK1_ PIN16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_PINCTRL_MUXSEL3 field descriptions Field 31-30 BANK1_PIN31 Description Pin 111, LCD_ENABLE pin function selection: 00= lcd_enable; 01= reserved; 10= reserved; 11= GPIO. 29-28 BANK1_PIN30 Pin 73, LCD_DOTCLK pin function selection: 00= lcd_dotclk; 01= saif1_mclk; 10= etm_tclk; 11= GPIO. 27-26 BANK1_PIN29 Pin 71, LCD_HSYNC pin function selection: 00= lcd_hsync; 01= saif1_sdata1; 10= etm_tctl; 11= GPIO. 25-24 BANK1_PIN28 Pin 59, LCD_VSYNC pin function selection: 00= lcd_vsync; 01= saif1_sdata0; 10= reserved; 11= GPIO. 23-22 BANK1_PIN27 Pin 113, LCD_CS pin function selection: 00= lcd_cs; 01= lcd_enable; 10= reserved; 11= GPIO. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 735 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL3 field descriptions (continued) Field 21-20 BANK1_PIN26 Description Pin 94, LCD_RS pin function selection: 00= lcd_rs; 01= lcd_dotclk; 10= reserved; 11= GPIO. 19-18 BANK1_PIN25 Pin 55, LCD_WR_RWN pin function selection: 00= lcd_wr_rwn; 01= lcd_hsync; 10= etm_tclk; 11= GPIO. 17-16 BANK1_PIN24 Pin 96, LCD_RD_E pin function selection: 00= lcd_rd_e; 01= lcd_vsync; 10= etm_tctl; 11= GPIO. 15-14 BANK1_PIN23 Pin 108, LCD_D23 pin function selection: 00= lcd_d23; 01= enet1_1588_event3_in; 10= etm_da0; 11= GPIO. 13-12 BANK1_PIN22 Pin 120, LCD_D22 pin function selection: 00= lcd_d22; 01= enet1_1588_event3_out; 10= etm_da1; 11= GPIO. 11-10 BANK1_PIN21 Pin 122, LCD_D21 pin function selection: 00= lcd_d21; 01= enet1_1588_event2_in; 10= etm_da2; 11= GPIO. 9-8 BANK1_PIN20 Pin 107, LCD_D20 pin function selection: 00= lcd_d20; 01= enet1_1588_event2_out; 10= etm_da3; 11= GPIO. 7-6 BANK1_PIN19 Pin 112, LCD_D19 pin function selection: 00= lcd_d19; 01= reserved; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 736 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL3 field descriptions (continued) Field Description 10= etm_da4; 11= GPIO. 5-4 BANK1_PIN18 Pin 118, LCD_D18 pin function selection: 00= lcd_d18; 01= reserved; 10= etm_da5; 11= GPIO. 3-2 BANK1_PIN17 Pin 105, LCD_D17 pin function selection: 00= lcd_d17; 01= reserved; 10= etm_da6; 11= GPIO. BANK1_PIN16 Pin 104, LCD_D16 pin function selection: 00= lcd_d16; 01= reserved; 10= etm_da7; 11= GPIO. 9.4.6 PINCTRL Pin Mux Select Register 4 (HW_PINCTRL_MUXSEL4) The PINCTRL Pin Mux Select Register provides pin function selection for 15 pins in bank2. HW_PINCTRL_MUXSEL4: 0x140 HW_PINCTRL_MUXSEL4_SET: 0x144 HW_PINCTRL_MUXSEL4_CLR: 0x148 HW_PINCTRL_MUXSEL4_TOG: 0x14C This register allows the programmer to select which hardware interface blocks drive the 15 pins shown above. Address: 8001_8000h base + 140h offset = 8001_8140h Bit 31 R W Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BANK2_ PIN15 BANK2_ PIN14 BANK2_ PIN13 BANK2_ PIN12 RSRVD0 BANK2_ PIN10 BANK2_ PIN09 BANK2_ PIN08 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 737 Pin Control Memory Map/Register Definition 15 Bit R W Reset 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK2_ PIN07 BANK2_ PIN06 BANK2_ PIN05 BANK2_ PIN04 BANK2_ PIN03 BANK2_ PIN02 BANK2_ PIN01 BANK2_ PIN00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_PINCTRL_MUXSEL4 field descriptions Field 31-30 BANK2_PIN15 Description Pin 23, SSP1_DATA3 pin function selection: 00= ssp1_d3; 01= ssp2_d7; 10= enet0_1588_event3_in; 11= GPIO. 29-28 BANK2_PIN14 Pin 21, SSP1_DATA0 pin function selection: 00= ssp1_d0; 01= ssp2_d6; 10= enet0_1588_event3_out; 11= GPIO. 27-26 BANK2_PIN13 Pin 17, SSP1_CMD pin function selection: 00= ssp1_cmd; 01= ssp2_d2; 10= enet0_1588_event2_in; 11= GPIO. 25-24 BANK2_PIN12 Pin 11, SSP1_SCK pin function selection: 00= ssp1_sck; 01= ssp2_d1; 10= enet0_1588_event2_out; 11= GPIO. 23-22 RSRVD0 21-20 BANK2_PIN10 Always write zeroes to this field. Pin 268, SSP0_SCK pin function selection: 00= ssp0_sck; 01= reserved; 10= reserved; 11= GPIO. 19-18 BANK2_PIN09 Pin 275, SSP0_DETECT pin function selection: 00= ssp0_card_detect; 01= reserved; 10= reserved; 11= GPIO. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 738 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL4 field descriptions (continued) Field 17-16 BANK2_PIN08 Description Pin 276, SSP0_CMD pin function selection: 00= ssp0_cmd; 01= reserved; 10= reserved; 11= GPIO. 15-14 BANK2_PIN07 Pin 282, SSP0_DATA7 pin function selection: 00= ssp0_d7; 01= ssp2_sck; 10= reserved; 11= GPIO. 13-12 BANK2_PIN06 Pin 6, SSP0_DATA6 pin function selection: 00= ssp0_d6; 01= ssp2_cmd; 10= reserved; 11= GPIO. 11-10 BANK2_PIN05 Pin 284, SSP0_DATA5 pin function selection: 00= ssp0_d5; 01= ssp2_d3; 10= reserved; 11= GPIO. 9-8 BANK2_PIN04 Pin 278, SSP0_DATA4 pin function selection: 00= ssp0_d4; 01= ssp2_d0; 10= reserved; 11= GPIO. 7-6 BANK2_PIN03 Pin 274, SSP0_DATA3 pin function selection: 00= ssp0_d3; 01= reserved; 10= reserved; 11= GPIO. 5-4 BANK2_PIN02 Pin 2, SSP0_DATA2 pin function selection: 00= ssp0_d2; 01= reserved; 10= reserved; 11= GPIO. 3-2 BANK2_PIN01 Pin 289, SSP0_DATA1 pin function selection: 00= ssp0_d1; 01= reserved; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 739 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL4 field descriptions (continued) Field Description 10= reserved; 11= GPIO. BANK2_PIN00 Pin 270, SSP0_DATA0 pin function selection: 00= ssp0_d0; 01= reserved; 10= reserved; 11= GPIO. 9.4.7 PINCTRL Pin Mux Select Register 5 (HW_PINCTRL_MUXSEL5) The PINCTRL Pin Mux Select Register provides pin function selection for 10 pins in bank2. HW_PINCTRL_MUXSEL5: 0x150 HW_PINCTRL_MUXSEL5_SET: 0x154 HW_PINCTRL_MUXSEL5_CLR: 0x158 HW_PINCTRL_MUXSEL5_TOG: 0x15C This register allows the programmer to select which hardware interface blocks drive the 10 pins shown above. Address: 8001_8000h base + 150h offset = 8001_8150h Bit 31 30 29 28 27 26 25 24 RSRVD1 R W Reset Bit 22 21 20 19 18 17 16 BANK2_ PIN27 BANK2_ PIN26 BANK2_ PIN25 BANK2_ PIN24 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R W Reset 23 0 0 0 0 BANK2_ PIN21 BANK2_ PIN20 BANK2_ PIN19 BANK2_ PIN18 BANK2_ PIN17 BANK2_ PIN16 1 1 1 1 1 1 1 1 1 1 1 1 HW_PINCTRL_MUXSEL5 field descriptions Field 31-24 RSRVD1 23-22 BANK2_PIN27 Description Always write zeroes to this field. Pin 15, SSP3_SS0 pin function selection: Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 740 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL5 field descriptions (continued) Field Description 00= ssp3_d3; 01= auart4_cts; 10= enet1_1588_event1_in; 11= GPIO. 21-20 BANK2_PIN26 Pin 3, SSP3_MISO pin function selection: 00= ssp3_d0; 01= auart4_rts; 10= enet1_1588_event1_out; 11= GPIO. 19-18 BANK2_PIN25 Pin 9, SSP3_MOSI pin function selection: 00= ssp3_cmd; 01= auart4_rx; 10= enet1_1588_event0_in; 11= GPIO. 17-16 BANK2_PIN24 Pin 286, SSP3_SCK pin function selection: 00= ssp3_sck; 01= auart4_tx; 10= enet1_1588_event0_out; 11= GPIO. 15-12 RSRVD0 11-10 BANK2_PIN21 Always write zeroes to this field. Pin 18, SSP2_SS2 pin function selection: 00= ssp2_d5; 01= ssp2_d2; 10= usb0_overcurrent; 11= GPIO. 9-8 BANK2_PIN20 Pin 7, SSP2_SS1 pin function selection: 00= ssp2_d4; 01= ssp2_d1; 10= usb1_overcurrent; 11= GPIO. 7-6 BANK2_PIN19 Pin 4, SSP2_SS0 pin function selection: 00= ssp2_d3; 01= auart3_tx; 10= saif1_sdata2; 11= GPIO. 5-4 BANK2_PIN18 Pin 288, SSP2_MISO pin function selection: 00= ssp2_d0; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 741 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL5 field descriptions (continued) Field Description 01= auart3_rx; 10= saif1_sdata1; 11= GPIO. 3-2 BANK2_PIN17 Pin 1, SSP2_MOSI pin function selection: 00= ssp2_cmd; 01= auart2_tx; 10= saif0_sdata2; 11= GPIO. BANK2_PIN16 Pin 280, SSP2_SCK pin function selection: 00= ssp2_sck; 01= auart2_rx; 10= saif0_sdata1; 11= GPIO. 9.4.8 PINCTRL Pin Mux Select Register 6 (HW_PINCTRL_MUXSEL6) The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank3. HW_PINCTRL_MUXSEL6: 0x160 HW_PINCTRL_MUXSEL6_SET: 0x164 HW_PINCTRL_MUXSEL6_CLR: 0x168 HW_PINCTRL_MUXSEL6_TOG: 0x16C This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. Address: 8001_8000h base + 160h offset = 8001_8160h Bit 31 R W Reset Bit R W Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BANK3_ PIN15 BANK3_ PIN14 BANK3_ PIN13 BANK3_ PIN12 BANK3_ PIN11 BANK3_ PIN10 BANK3_ PIN09 BANK3_ PIN08 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK3_ PIN07 BANK3_ PIN06 BANK3_ PIN05 BANK3_ PIN04 BANK3_ PIN03 BANK3_ PIN02 BANK3_ PIN01 BANK3_ PIN00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 742 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL6 field descriptions Field 31-30 BANK3_PIN15 Description Pin 82, AUART3_RTS pin function selection: 00= auart3_rts; 01= can1_rx; 10= enet0_1588_event1_in; 11= GPIO. 29-28 BANK3_PIN14 Pin 90, AUART3_CTS pin function selection: 00= auart3_cts; 01= can1_tx; 10= enet0_1588_event1_out; 11= GPIO. 27-26 BANK3_PIN13 Pin 86, AUART3_TX pin function selection: 00= auart3_tx; 01= can0_rx; 10= enet0_1588_event0_in; 11= GPIO. 25-24 BANK3_PIN12 Pin 98, AUART3_RX pin function selection: 00= auart3_rx; 01= can0_tx; 10= enet0_1588_event0_out; 11= GPIO. 23-22 BANK3_PIN11 Pin 56, AUART2_RTS pin function selection: 00= auart2_rts; 01= i2c1_sda; 10= saif1_lrclk; 11= GPIO. 21-20 BANK3_PIN10 Pin 50, AUART2_CTS pin function selection: 00= auart2_cts; 01= i2c1_scl; 10= saif1_bitclk; 11= GPIO. 19-18 BANK3_PIN09 Pin 26, AUART2_TX pin function selection: 00= auart2_tx; 01= ssp3_d2; 10= ssp3_d5; 11= GPIO. 17-16 BANK3_PIN08 Pin 22, AUART2_RX pin function selection: 00= auart2_rx; 01= ssp3_d1; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 743 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL6 field descriptions (continued) Field Description 10= ssp3_d4; 11= GPIO. 15-14 BANK3_PIN07 Pin 74, AUART1_RTS pin function selection: 00= auart1_rts; 01= usb0_id; 10= timrot_rotaryb; 11= GPIO. 13-12 BANK3_PIN06 Pin 78, AUART1_CTS pin function selection: 00= auart1_cts; 01= usb0_overcurrent; 10= timrot_rotarya; 11= GPIO. 11-10 BANK3_PIN05 Pin 65, AUART1_TX pin function selection: 00= auart1_tx; 01= ssp3_card_detect; 10= pwm_1; 11= GPIO. 9-8 BANK3_PIN04 Pin 81, AUART1_RX pin function selection: 00= auart1_rx; 01= ssp2_card_detect; 10= pwm_0; 11= GPIO. 7-6 BANK3_PIN03 Pin 66, AUART0_RTS pin function selection: 00= auart0_rts; 01= auart4_tx; 10= duart_tx; 11= GPIO. 5-4 BANK3_PIN02 Pin 70, AUART0_CTS pin function selection: 00= auart0_cts; 01= auart4_rx; 10= duart_rx; 11= GPIO. 3-2 BANK3_PIN01 Pin 38, AUART0_TX pin function selection: 00= auart0_tx; 01= i2c0_sda; 10= duart_rts; 11= GPIO. BANK3_PIN00 Pin 30, AUART0_RX pin function selection: Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 744 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL6 field descriptions (continued) Field Description 00= auart0_rx; 01= i2c0_scl; 10= duart_cts; 11= GPIO. 9.4.9 PINCTRL Pin Mux Select Register 7 (HW_PINCTRL_MUXSEL7) The PINCTRL Pin Mux Select Register provides pin function selection for 14 pins in bank3. HW_PINCTRL_MUXSEL7: 0x170 HW_PINCTRL_MUXSEL7_SET: 0x174 HW_PINCTRL_MUXSEL7_CLR: 0x178 HW_PINCTRL_MUXSEL7_TOG: 0x17C This register allows the programmer to select which hardware interface blocks drive the 14 pins shown above. Address: 8001_8000h base + 170h offset = 8001_8170h Bit 31 R 30 Bit R W Reset 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 BANK3_ PIN30 BANK3_ PIN29 BANK3_ PIN28 BANK3_ PIN27 BANK3_ PIN26 BANK3_ PIN25 BANK3_ PIN24 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W Reset 29 BANK3_ PIN23 BANK3_ PIN22 BANK3_ PIN21 BANK3_ PIN20 RSRVD0 BANK3_ PIN18 BANK3_ PIN17 BANK3_ PIN16 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 HW_PINCTRL_MUXSEL7 field descriptions Field 31-30 RSRVD1 29-28 BANK3_PIN30 Description Always write zeroes to this field. Pin 101, LCD_RESET pin function selection: 00= lcd_reset; 01= lcd_vsync; 10= reserved; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 745 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL7 field descriptions (continued) Field Description 11= GPIO. 27-26 BANK3_PIN29 Pin 279, PWM4 pin function selection: 00= pwm_4; 01= reserved; 10= reserved; 11= GPIO. 25-24 BANK3_PIN28 Pin 287, PWM3 pin function selection: 00= pwm_3; 01= reserved; 10= reserved; 11= GPIO. 23-22 BANK3_PIN27 Pin 285, SPDIF pin function selection: 00= spdif_tx; 01= reserved; 10= enet1_rx_er; 11= GPIO. 21-20 BANK3_PIN26 Pin 8, SAIF1_SDATA0 pin function selection: 00= saif1_sdata0; 01= pwm_7; 10= saif0_sdata1; 11= GPIO. 19-18 BANK3_PIN25 Pin 281, I2C0_SDA pin function selection: 00= i2c0_sda; 01= timrot_rotaryb; 10= duart_tx; 11= GPIO. 17-16 BANK3_PIN24 Pin 272, I2C0_SCL pin function selection: 00= i2c0_scl; 01= timrot_rotarya; 10= duart_rx; 11= GPIO. 15-14 BANK3_PIN23 Pin 12, SAIF0_SDATA0 pin function selection: 00= saif0_sdata0; 01= pwm_6; 10= auart4_tx; 11= GPIO. 13-12 BANK3_PIN22 Pin 16, SAIF0_BITCLK pin function selection: 00= saif0_bitclk; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 746 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL7 field descriptions (continued) Field Description 01= pwm_5; 10= auart4_rx; 11= GPIO. 11-10 BANK3_PIN21 Pin 34, SAIF0_LRCLK pin function selection: 00= saif0_lrclk; 01= pwm_4; 10= auart4_rts; 11= GPIO. 9-8 BANK3_PIN20 Pin 28, SAIF0_MCLK pin function selection: 00= saif0_mclk; 01= pwm_3; 10= auart4_cts; 11= GPIO. 7-6 RSRVD0 5-4 BANK3_PIN18 Always write zeroes to this field. Pin 68, PWM2 pin function selection: 00= pwm_2; 01= usb0_id; 10= usb1_overcurrent; 11= GPIO. 3-2 BANK3_PIN17 Pin 84, PWM1 pin function selection: 00= pwm_1; 01= i2c1_sda; 10= duart_tx; 11= GPIO. BANK3_PIN16 Pin 72, PWM0 pin function selection: 00= pwm_0; 01= i2c1_scl; 10= duart_rx; 11= GPIO. 9.4.10 PINCTRL Pin Mux Select Register 8 (HW_PINCTRL_MUXSEL8) The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank4. HW_PINCTRL_MUXSEL8: 0x180 HW_PINCTRL_MUXSEL8_SET: 0x184 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 747 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL8_CLR: 0x188 HW_PINCTRL_MUXSEL8_TOG: 0x18C This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. Address: 8001_8000h base + 180h offset = 8001_8180h Bit 31 R W Reset Bit R W Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BANK4_ PIN15 BANK4_ PIN14 BANK4_ PIN13 BANK4_ PIN12 BANK4_ PIN11 BANK4_ PIN10 BANK4_ PIN09 BANK4_ PIN08 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK4_ PIN07 BANK4_ PIN06 BANK4_ PIN05 BANK4_ PIN04 BANK4_ PIN03 BANK4_ PIN02 BANK4_ PIN01 BANK4_ PIN00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_PINCTRL_MUXSEL8 field descriptions Field 31-30 BANK4_PIN15 Description Pin 61, ENET0_CRS pin function selection: 00= enet0_crs; 01= enet1_rx_en; 10= enet0_1588_event3_in; 11= GPIO. 29-28 BANK4_PIN14 Pin 57, ENET0_COL pin function selection: 00= enet0_col; 01= enet1_tx_en; 10= enet0_1588_event3_out; 11= GPIO. 27-26 BANK4_PIN13 Pin 31, ENET0_RX_CLK pin function selection: 00= enet0_rx_clk; 01= enet0_rx_er; 10= enet0_1588_event2_in; 11= GPIO. 25-24 BANK4_PIN12 Pin 41, ENET0_TXD3 pin function selection: 00= enet0_txd3; 01= enet1_txd1; 10= enet0_1588_event1_in; 11= GPIO. 23-22 BANK4_PIN11 Pin 43, ENET0_TXD2 pin function selection: 00= enet0_txd2; 01= enet1_txd0; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 748 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL8 field descriptions (continued) Field Description 10= enet0_1588_event1_out; 11= GPIO. 21-20 BANK4_PIN10 Pin 53, ENET0_RXD3 pin function selection: 00= enet0_rxd3; 01= enet1_rxd1; 10= enet0_1588_event0_in; 11= GPIO. 19-18 BANK4_PIN09 Pin 51, ENET0_RXD2 pin function selection: 00= enet0_rxd2; 01= enet1_rxd0; 10= enet0_1588_event0_out; 11= GPIO. 17-16 BANK4_PIN08 Pin 35, ENET0_TXD1 pin function selection: 00= enet0_txd1; 01= gpmi_ready7; 10= reserved; 11= GPIO. 15-14 BANK4_PIN07 Pin 37, ENET0_TXD0 pin function selection: 00= enet0_txd0; 01= gpmi_ready6; 10= reserved; 11= GPIO. 13-12 BANK4_PIN06 Pin 29, ENET0_TX_EN pin function selection: 00= enet0_tx_en; 01= gpmi_ready5; 10= reserved; 11= GPIO. 11-10 BANK4_PIN05 Pin 13, ENET0_TX_CLK pin function selection: 00= enet0_tx_clk; 01= hsadc_trigger; 10= enet0_1588_event2_out; 11= GPIO. 9-8 BANK4_PIN04 Pin 47, ENET0_RXD1 pin function selection: 00= enet0_rxd1; 01= gpmi_ready4; 10= reserved; 11= GPIO. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 749 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL8 field descriptions (continued) Field 7-6 BANK4_PIN03 Description Pin 45, ENET0_RXD0 pin function selection: 00= enet0_rxd0; 01= gpmi_ce7n; 10= saif1_sdata2; 11= GPIO. 5-4 BANK4_PIN02 Pin 27, ENET0_RX_EN pin function selection: 00= enet0_rx_en; 01= gpmi_ce6n; 10= saif1_sdata1; 11= GPIO. 3-2 BANK4_PIN01 Pin 39, ENET0_MDIO pin function selection: 00= enet0_mdio; 01= gpmi_ce5n; 10= saif0_sdata2; 11= GPIO. BANK4_PIN00 Pin 54, ENET0_MDC pin function selection: 00= enet0_mdc; 01= gpmi_ce4n; 10= saif0_sdata1; 11= GPIO. 9.4.11 PINCTRL Pin Mux Select Register 9 (HW_PINCTRL_MUXSEL9) The PINCTRL Pin Mux Select Register provides pin function selection for 2 pins in bank4. HW_PINCTRL_MUXSEL9: 0x190 HW_PINCTRL_MUXSEL9_SET: 0x194 HW_PINCTRL_MUXSEL9_CLR: 0x198 HW_PINCTRL_MUXSEL9_TOG: 0x19C This register allows the programmer to select which hardware interface blocks drive the 2 pins shown above. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 750 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Address: 8001_8000h base + 190h offset = 8001_8190h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD1 R W Reset 0 0 0 0 RSRVD0 BANK4_ PIN20 0 0 0 0 0 0 0 0 BANK4_ PIN16 0 0 1 1 HW_PINCTRL_MUXSEL9 field descriptions Field 31-10 RSRVD1 9-8 BANK4_PIN20 Description Always write zeroes to this field. Pin 230, JTAG_RTCK pin function selection: 00= jtag_rtck; 01= reserved; 10= reserved; 11= GPIO. 7-2 RSRVD0 BANK4_PIN16 Always write zeroes to this field. Pin 19, ENET_CLK pin function selection: 00= clkctrl_enet; 01= reserved; 10= reserved; 11= GPIO. 9.4.12 PINCTRL Pin Mux Select Register 10 (HW_PINCTRL_MUXSEL10) The PINCTRL Pin Mux Select Register provides pin function selection for 16 pins in bank5. HW_PINCTRL_MUXSEL10: 0x1a0 HW_PINCTRL_MUXSEL10_SET: 0x1a4 HW_PINCTRL_MUXSEL10_CLR: 0x1a8 HW_PINCTRL_MUXSEL10_TOG: 0x1aC This register allows the programmer to select which hardware interface blocks drive the 16 pins shown above. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 751 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 1A0h offset = 8001_81A0h Bit 31 R W Reset Bit R W Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BANK5_ PIN15 BANK5_ PIN14 BANK5_ PIN13 BANK5_ PIN12 BANK5_ PIN11 BANK5_ PIN10 BANK5_ PIN09 BANK5_ PIN08 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK5_ PIN07 BANK5_ PIN06 BANK5_ PIN05 BANK5_ PIN04 BANK5_ PIN03 BANK5_ PIN02 BANK5_ PIN01 BANK5_ PIN00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_PINCTRL_MUXSEL10 field descriptions Field 31-30 BANK5_PIN15 Description Pin 218, EMI_D15 pin function selection: 00= emi_data15; 01= reserved; 10= reserved; 11= disabled. 29-28 BANK5_PIN14 Pin 223, EMI_D14 pin function selection: 00= emi_data14; 01= reserved; 10= reserved; 11= disabled. 27-26 BANK5_PIN13 Pin 208, EMI_D13 pin function selection: 00= emi_data13; 01= reserved; 10= reserved; 11= disabled. 25-24 BANK5_PIN12 Pin 213, EMI_D12 pin function selection: 00= emi_data12; 01= reserved; 10= reserved; 11= disabled. 23-22 BANK5_PIN11 Pin 207, EMI_D11 pin function selection: 00= emi_data11; 01= reserved; 10= reserved; 11= disabled. 21-20 BANK5_PIN10 Pin 217, EMI_D10 pin function selection: 00= emi_data10; 01= reserved; 10= reserved; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 752 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL10 field descriptions (continued) Field Description 11= disabled. 19-18 BANK5_PIN09 Pin 212, EMI_D09 pin function selection: 00= emi_data9; 01= reserved; 10= reserved; 11= disabled. 17-16 BANK5_PIN08 Pin 216, EMI_D08 pin function selection: 00= emi_data8; 01= reserved; 10= reserved; 11= disabled. 15-14 BANK5_PIN07 Pin 193, EMI_D07 pin function selection: 00= emi_data7; 01= reserved; 10= reserved; 11= disabled. 13-12 BANK5_PIN06 Pin 189, EMI_D06 pin function selection: 00= emi_data6; 01= reserved; 10= reserved; 11= disabled. 11-10 BANK5_PIN05 Pin 182, EMI_D05 pin function selection: 00= emi_data5; 01= reserved; 10= reserved; 11= disabled. 9-8 BANK5_PIN04 Pin 180, EMI_D04 pin function selection: 00= emi_data4; 01= reserved; 10= reserved; 11= disabled. 7-6 BANK5_PIN03 Pin 184, EMI_D03 pin function selection: 00= emi_data3; 01= reserved; 10= reserved; 11= disabled. 5-4 BANK5_PIN02 Pin 177, EMI_D02 pin function selection: 00= emi_data2; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 753 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL10 field descriptions (continued) Field Description 01= reserved; 10= reserved; 11= disabled. 3-2 BANK5_PIN01 Pin 188, EMI_D01 pin function selection: 00= emi_data1; 01= reserved; 10= reserved; 11= disabled. BANK5_PIN00 Pin 185, EMI_D00 pin function selection: 00= emi_data0; 01= reserved; 10= reserved; 11= disabled. 9.4.13 PINCTRL Pin Mux Select Register 11 (HW_PINCTRL_MUXSEL11) The PINCTRL Pin Mux Select Register provides pin function selection for 9 pins in bank5. HW_PINCTRL_MUXSEL11: 0x1b0 HW_PINCTRL_MUXSEL11_SET: 0x1b4 HW_PINCTRL_MUXSEL11_CLR: 0x1b8 HW_PINCTRL_MUXSEL11_TOG: 0x1bC This register allows the programmer to select which hardware interface blocks drive the 9 pins shown above. Address: 8001_8000h base + 1B0h offset = 8001_81B0h Bit 31 30 29 28 27 26 25 24 23 22 RSRVD1 R Bit R W Reset 20 19 18 17 16 RSRVD0 BANK5_ PIN26 W Reset 21 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK5_ PIN23 BANK5_ PIN22 BANK5_ PIN21 BANK5_ PIN20 BANK5_ PIN19 BANK5_ PIN18 BANK5_ PIN17 BANK5_ PIN16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 754 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL11 field descriptions Field 31-22 RSRVD1 21-20 BANK5_PIN26 Description Always write zeroes to this field. Pin 196, EMI_DDR_OPEN pin function selection: 00= emi_ddr_open; 01= reserved; 10= reserved; 11= disabled. 19-16 RSRVD0 15-14 BANK5_PIN23 Always write zeroes to this field. Pin 204, EMI_DQS1 pin function selection: 00= emi_dqs1; 01= reserved; 10= reserved; 11= disabled. 13-12 BANK5_PIN22 Pin 202, EMI_DQS0 pin function selection: 00= emi_dqs0; 01= reserved; 10= reserved; 11= disabled. 11-10 BANK5_PIN21 Pin 200, EMI_CLK pin function selection: 00= emi_clk; 01= reserved; 10= reserved; 11= disabled. 9-8 BANK5_PIN20 Pin 195, EMI_DDR_OPEN_FB pin function selection: 00= emi_ddr_open_feedback; 01= reserved; 10= reserved; 11= disabled. 7-6 BANK5_PIN19 Pin 222, EMI_DQM1 pin function selection: 00= emi_dqm1; 01= reserved; 10= reserved; 11= disabled. 5-4 BANK5_PIN18 Pin 171, EMI_ODT1 pin function selection: 00= emi_odt1; 01= reserved; 10= reserved; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 755 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL11 field descriptions (continued) Field Description 11= disabled. 3-2 BANK5_PIN17 Pin 183, EMI_DQM0 pin function selection: 00= emi_dqm0; 01= reserved; 10= reserved; 11= disabled. BANK5_PIN16 Pin 173, EMI_ODT0 pin function selection: 00= emi_odt0; 01= reserved; 10= reserved; 11= disabled. 9.4.14 PINCTRL Pin Mux Select Register 12 (HW_PINCTRL_MUXSEL12) The PINCTRL Pin Mux Select Register provides pin function selection for 15 pins in bank6. HW_PINCTRL_MUXSEL12: 0x1c0 HW_PINCTRL_MUXSEL12_SET: 0x1c4 HW_PINCTRL_MUXSEL12_CLR: 0x1c8 HW_PINCTRL_MUXSEL12_TOG: 0x1cC This register allows the programmer to select which hardware interface blocks drive the 15 pins shown above. Address: 8001_8000h base + 1C0h offset = 8001_81C0h Bit 31 R 30 Bit R W Reset 28 27 26 25 24 23 22 21 20 19 18 17 16 BANK6_ PIN14 BANK6_ PIN13 BANK6_ PIN12 BANK6_ PIN11 BANK6_ PIN10 BANK6_ PIN09 BANK6_ PIN08 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W Reset 29 RSRVD0 BANK6_ PIN07 BANK6_ PIN06 BANK6_ PIN05 BANK6_ PIN04 BANK6_ PIN03 BANK6_ PIN02 BANK6_ PIN01 BANK6_ PIN00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 756 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL12 field descriptions Field 31-30 RSRVD0 29-28 BANK6_PIN14 Description Always write zeroes to this field. Pin 147, EMI_A14 pin function selection: 00= emi_addr14; 01= reserved; 10= reserved; 11= disabled. 27-26 BANK6_PIN13 Pin 142, EMI_A13 pin function selection: 00= emi_addr13; 01= reserved; 10= reserved; 11= disabled. 25-24 BANK6_PIN12 Pin 150, EMI_A12 pin function selection: 00= emi_addr12; 01= reserved; 10= reserved; 11= disabled. 23-22 BANK6_PIN11 Pin 146, EMI_A11 pin function selection: 00= emi_addr11; 01= reserved; 10= reserved; 11= disabled. 21-20 BANK6_PIN10 Pin 162, EMI_A10 pin function selection: 00= emi_addr10; 01= reserved; 10= reserved; 11= disabled. 19-18 BANK6_PIN09 Pin 143, EMI_A09 pin function selection: 00= emi_addr9; 01= reserved; 10= reserved; 11= disabled. 17-16 BANK6_PIN08 Pin 140, EMI_A08 pin function selection: 00= emi_addr8; 01= reserved; 10= reserved; 11= disabled. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 757 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL12 field descriptions (continued) Field 15-14 BANK6_PIN07 Description Pin 153, EMI_A07 pin function selection: 00= emi_addr7; 01= reserved; 10= reserved; 11= disabled. 13-12 BANK6_PIN06 Pin 138, EMI_A06 pin function selection: 00= emi_addr6; 01= reserved; 10= reserved; 11= disabled. 11-10 BANK6_PIN05 Pin 154, EMI_A05 pin function selection: 00= emi_addr5; 01= reserved; 10= reserved; 11= disabled. 9-8 BANK6_PIN04 Pin 144, EMI_A04 pin function selection: 00= emi_addr4; 01= reserved; 10= reserved; 11= disabled. 7-6 BANK6_PIN03 Pin 152, EMI_A03 pin function selection: 00= emi_addr3; 01= reserved; 10= reserved; 11= disabled. 5-4 BANK6_PIN02 Pin 164, EMI_A02 pin function selection: 00= emi_addr2; 01= reserved; 10= reserved; 11= disabled. 3-2 BANK6_PIN01 Pin 158, EMI_A01 pin function selection: 00= emi_addr1; 01= reserved; 10= reserved; 11= disabled. BANK6_PIN00 Pin 170, EMI_A00 pin function selection: 00= emi_addr0; 01= reserved; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 758 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL12 field descriptions (continued) Field Description 10= reserved; 11= disabled. 9.4.15 PINCTRL Pin Mux Select Register 13 (HW_PINCTRL_MUXSEL13) The PINCTRL Pin Mux Select Register provides pin function selection for 9 pins in bank6. HW_PINCTRL_MUXSEL13: 0x1d0 HW_PINCTRL_MUXSEL13_SET: 0x1d4 HW_PINCTRL_MUXSEL13_CLR: 0x1d8 HW_PINCTRL_MUXSEL13_TOG: 0x1dC This register allows the programmer to select which hardware interface blocks drive the 9 pins shown above. Address: 8001_8000h base + 1D0h offset = 8001_81D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RSRVD0 R Bit R W Reset 16 BANK6_ PIN24 W Reset 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK6_ PIN23 BANK6_ PIN22 BANK6_ PIN21 BANK6_ PIN20 BANK6_ PIN19 BANK6_ PIN18 BANK6_ PIN17 BANK6_ PIN16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_PINCTRL_MUXSEL13 field descriptions Field 31-18 RSRVD0 17-16 BANK6_PIN24 Description Always write zeroes to this field. Pin 166, EMI_CKE pin function selection: 00= emi_cke; 01= reserved; 10= reserved; 11= disabled. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 759 Pin Control Memory Map/Register Definition HW_PINCTRL_MUXSEL13 field descriptions (continued) Field 15-14 BANK6_PIN23 Description Pin 139, EMI_CE1N pin function selection: 00= emi_ce1n; 01= reserved; 10= reserved; 11= disabled. 13-12 BANK6_PIN22 Pin 151, EMI_CE0N pin function selection: 00= emi_ce0n; 01= reserved; 10= reserved; 11= disabled. 11-10 BANK6_PIN21 Pin 176, EMI_WEN pin function selection: 00= emi_wen; 01= reserved; 10= reserved; 11= disabled. 9-8 BANK6_PIN20 Pin 167, EMI_RASN pin function selection: 00= emi_rasn; 01= reserved; 10= reserved; 11= disabled. 7-6 BANK6_PIN19 Pin 172, EMI_CASN pin function selection: 00= emi_casn; 01= reserved; 10= reserved; 11= disabled. 5-4 BANK6_PIN18 Pin 165, EMI_BA2 pin function selection: 00= emi_ba2; 01= reserved; 10= reserved; 11= disabled. 3-2 BANK6_PIN17 Pin 160, EMI_BA1 pin function selection: 00= emi_ba1; 01= reserved; 10= reserved; 11= disabled. BANK6_PIN16 Pin 157, EMI_BA0 pin function selection: 00= emi_ba0; 01= reserved; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 760 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_MUXSEL13 field descriptions (continued) Field Description 10= reserved; 11= disabled. 9.4.16 PINCTRL Drive Strength and Voltage Register 0 (HW_PINCTRL_DRIVE0) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 0. HW_PINCTRL_DRIVE0: 0x300 HW_PINCTRL_DRIVE0_SET: 0x304 HW_PINCTRL_DRIVE0_CLR: 0x308 HW_PINCTRL_DRIVE0_TOG: 0x30C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK0_PINxx_V configure voltage for both input and output. Address: 8001_8000h base + 300h offset = 8001_8300h 24 23 BANK0_ PIN06_MA 22 21 20 19 RSRVD4 25 BANK0_ PIN05_MA 18 BANK0_PIN04_V BANK0_ PIN07_MA 26 BANK0_PIN05_V 27 RSRVD5 28 BANK0_PIN06_V 29 RSRVD6 R 30 BANK0_PIN07_V 31 RSRVD7 Bit 17 16 BANK0_ PIN04_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 761 Pin Control Memory Map/Register Definition 8 7 BANK0_ PIN02_MA 6 5 4 3 RSRVD0 9 BANK0_ PIN01_MA 2 BANK0_PIN00_V BANK0_ PIN03_MA 10 BANK0_PIN01_V 11 RSRVD1 12 BANK0_PIN02_V 13 RSRVD2 14 BANK0_PIN03_V R RSRVD3 15 Bit 1 0 BANK0_ PIN00_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE0 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 124, GPMI_D07 pin voltage selection: BANK0_PIN07_V 0= 1.8V; 1= 3.3V. 29-28 Pin 124, GPMI_D07 pin output drive strength selection: BANK0_PIN07_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 130, GPMI_D06 pin voltage selection: BANK0_PIN06_V 0= 1.8V; 1= 3.3V. 25-24 Pin 130, GPMI_D06 pin output drive strength selection: BANK0_PIN06_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 762 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE0 field descriptions (continued) Field Description 22 Pin 116, GPMI_D05 pin voltage selection: BANK0_PIN05_V 0= 1.8V; 1= 3.3V. 21-20 Pin 116, GPMI_D05 pin output drive strength selection: BANK0_PIN05_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 128, GPMI_D04 pin voltage selection: BANK0_PIN04_V 0= 1.8V; 1= 3.3V. 17-16 Pin 128, GPMI_D04 pin output drive strength selection: BANK0_PIN04_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 132, GPMI_D03 pin voltage selection: BANK0_PIN03_V 0= 1.8V; 1= 3.3V. 13-12 Pin 132, GPMI_D03 pin output drive strength selection: BANK0_PIN03_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 126, GPMI_D02 pin voltage selection: BANK0_PIN02_V 0= 1.8V; 1= 3.3V. 9-8 Pin 126, GPMI_D02 pin output drive strength selection: BANK0_PIN02_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 763 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE0 field descriptions (continued) Field 7 RSRVD1 Description Always write zeroes to this field. 6 Pin 136, GPMI_D01 pin voltage selection: BANK0_PIN01_V 0= 1.8V; 1= 3.3V. 5-4 Pin 136, GPMI_D01 pin output drive strength selection: BANK0_PIN01_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 134, GPMI_D00 pin voltage selection: BANK0_PIN00_V 0= 1.8V; 1= 3.3V. BANK0_PIN00_ Pin 134, GPMI_D00 pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved 9.4.17 PINCTRL Drive Strength and Voltage Register 1 (HW_PINCTRL_DRIVE1) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 0 pins of bank 0. HW_PINCTRL_DRIVE1: 0x310 HW_PINCTRL_DRIVE1_SET: 0x314 HW_PINCTRL_DRIVE1_CLR: 0x318 HW_PINCTRL_DRIVE1_TOG: 0x31C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 764 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Address: 8001_8000h base + 310h offset = 8001_8310h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DRIVE1 field descriptions Field RSRVD0 Description Always write zeroes to this field. 9.4.18 PINCTRL Drive Strength and Voltage Register 2 (HW_PINCTRL_DRIVE2) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 0. HW_PINCTRL_DRIVE2: 0x320 HW_PINCTRL_DRIVE2_SET: 0x324 HW_PINCTRL_DRIVE2_CLR: 0x328 HW_PINCTRL_DRIVE2_TOG: 0x32C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK0_PINxx_V configure voltage for both input and output. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 765 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 320h offset = 8001_8320h 24 23 BANK0_ PIN22_MA 22 21 20 19 RSRVD4 25 BANK0_ PIN21_MA 18 BANK0_PIN20_V BANK0_ PIN23_MA 26 BANK0_PIN21_V 27 RSRVD5 28 BANK0_PIN22_V 29 RSRVD6 R 30 BANK0_PIN23_V 31 RSRVD7 Bit 17 16 BANK0_ PIN20_MA W 0 0 1 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK0_ PIN19_MA BANK0_ PIN18_MA BANK0_ PIN17_MA BANK0_PIN16_V 0 RSRVD0 1 BANK0_PIN17_V 0 RSRVD1 0 BANK0_PIN18_V 0 RSRVD2 R 1 BANK0_PIN19_V Bit 0 RSRVD3 Reset BANK0_ PIN16_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE2 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 80, GPMI_RDY3 pin voltage selection: BANK0_PIN23_V 0= 1.8V; 1= 3.3V. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 766 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE2 field descriptions (continued) Field Description 29-28 Pin 80, GPMI_RDY3 pin output drive strength selection: BANK0_PIN23_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 88, GPMI_RDY2 pin voltage selection: BANK0_PIN22_V 0= 1.8V; 1= 3.3V. 25-24 Pin 88, GPMI_RDY2 pin output drive strength selection: BANK0_PIN22_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. 22 Pin 119, GPMI_RDY1 pin voltage selection: BANK0_PIN21_V 0= 1.8V; 1= 3.3V. 21-20 Pin 119, GPMI_RDY1 pin output drive strength selection: BANK0_PIN21_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 103, GPMI_RDY0 pin voltage selection: BANK0_PIN20_V 0= 1.8V; 1= 3.3V. 17-16 Pin 103, GPMI_RDY0 pin output drive strength selection: BANK0_PIN20_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 135, GPMI_CE3N pin voltage selection: BANK0_PIN19_V 0= 1.8V; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 767 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE2 field descriptions (continued) Field Description 1= 3.3V. 13-12 Pin 135, GPMI_CE3N pin output drive strength selection: BANK0_PIN19_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 92, GPMI_CE2N pin voltage selection: BANK0_PIN18_V 0= 1.8V; 1= 3.3V. 9-8 Pin 92, GPMI_CE2N pin output drive strength selection: BANK0_PIN18_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 131, GPMI_CE1N pin voltage selection: BANK0_PIN17_V 0= 1.8V; 1= 3.3V. 5-4 Pin 131, GPMI_CE1N pin output drive strength selection: BANK0_PIN17_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 115, GPMI_CE0N pin voltage selection: BANK0_PIN16_V 0= 1.8V; 1= 3.3V. BANK0_PIN16_ Pin 115, GPMI_CE0N pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 768 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 9.4.19 PINCTRL Drive Strength and Voltage Register 3 (HW_PINCTRL_DRIVE3) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 5 pins of bank 0. HW_PINCTRL_DRIVE3: 0x330 HW_PINCTRL_DRIVE3_SET: 0x334 HW_PINCTRL_DRIVE3_CLR: 0x338 HW_PINCTRL_DRIVE3_TOG: 0x33C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK0_PINxx_V configure voltage for both input and output. Address: 8001_8000h base + 330h offset = 8001_8330h 30 29 28 27 26 25 24 23 22 21 20 RSRVD5 R 19 18 BANK0_PIN28_V 31 RSRVD4 Bit 17 16 BANK0_ PIN28_MA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 769 Pin Control Memory Map/Register Definition 8 7 BANK0_ PIN26_MA 6 5 4 3 RSRVD0 9 BANK0_ PIN25_MA 2 BANK0_PIN24_V BANK0_ PIN27_MA 10 BANK0_PIN25_V 11 RSRVD1 12 BANK0_PIN26_V 13 RSRVD2 14 BANK0_PIN27_V R RSRVD3 15 Bit 1 0 BANK0_ PIN24_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE3 field descriptions Field Description 31-20 RSRVD5 Always write zeroes to this field. 19 RSRVD4 Always write zeroes to this field. 18 Pin 129, GPMI_RESETN pin voltage selection: BANK0_PIN28_V 0= 1.8V; 1= 3.3V. 17-16 Pin 129, GPMI_RESETN pin output drive strength selection: BANK0_PIN28_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 123, GPMI_CLE pin voltage selection: BANK0_PIN27_V 0= 1.8V; 1= 3.3V. 13-12 Pin 123, GPMI_CLE pin output drive strength selection: BANK0_PIN27_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 770 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE3 field descriptions (continued) Field 11 RSRVD2 Description Always write zeroes to this field. 10 Pin 117, GPMI_ALE pin voltage selection: BANK0_PIN26_V 0= 1.8V; 1= 3.3V. 9-8 Pin 117, GPMI_ALE pin output drive strength selection: BANK0_PIN26_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 127, GPMI_WRN pin voltage selection: BANK0_PIN25_V 0= 1.8V; 1= 3.3V. 5-4 Pin 127, GPMI_WRN pin output drive strength selection: BANK0_PIN25_ 00=medium drive strength MA 01=medium drive strength 10=very high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 110, GPMI_RDN pin voltage selection: BANK0_PIN24_V 0= 1.8V; 1= 3.3V. BANK0_PIN24_ Pin 110, GPMI_RDN pin output drive strength selection: MA 00=medium drive strength 01=medium drive strength 10=very high drive strength 11=reserved 9.4.20 PINCTRL Drive Strength and Voltage Register 4 (HW_PINCTRL_DRIVE4) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 1. HW_PINCTRL_DRIVE4: 0x340 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 771 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE4_SET: 0x344 HW_PINCTRL_DRIVE4_CLR: 0x348 HW_PINCTRL_DRIVE4_TOG: 0x34C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK1_PINxx_V configure voltage for both input and output. Address: 8001_8000h base + 340h offset = 8001_8340h 24 23 BANK1_ PIN06_MA 22 21 20 19 RSRVD4 25 BANK1_ PIN05_MA 18 BANK1_PIN04_V BANK1_ PIN07_MA 26 BANK1_PIN05_V 27 RSRVD5 28 BANK1_PIN06_V 29 RSRVD6 R 30 BANK1_PIN07_V 31 RSRVD7 Bit 17 16 BANK1_ PIN04_MA W 0 0 1 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK1_ PIN03_MA BANK1_ PIN02_MA BANK1_ PIN01_MA BANK1_PIN00_V 0 RSRVD0 1 BANK1_PIN01_V 0 RSRVD1 0 BANK1_PIN02_V 0 RSRVD2 R 1 BANK1_PIN03_V Bit 0 RSRVD3 Reset BANK1_ PIN00_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 772 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE4 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 75, LCD_D07 pin voltage selection: BANK1_PIN07_V 0= 1.8V; 1= 3.3V. 29-28 Pin 75, LCD_D07 pin output drive strength selection: BANK1_PIN07_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 91, LCD_D06 pin voltage selection: BANK1_PIN06_V 0= 1.8V; 1= 3.3V. 25-24 Pin 91, LCD_D06 pin output drive strength selection: BANK1_PIN06_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. 22 Pin 89, LCD_D05 pin voltage selection: BANK1_PIN05_V 0= 1.8V; 1= 3.3V. 21-20 Pin 89, LCD_D05 pin output drive strength selection: BANK1_PIN05_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 79, LCD_D04 pin voltage selection: BANK1_PIN04_V 0= 1.8V; 1= 3.3V. 17-16 Pin 79, LCD_D04 pin output drive strength selection: BANK1_PIN04_ 00=low drive strength MA 01=medium drive strength 10=high drive strength Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 773 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE4 field descriptions (continued) Field Description 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 77, LCD_D03 pin voltage selection: BANK1_PIN03_V 0= 1.8V; 1= 3.3V. 13-12 Pin 77, LCD_D03 pin output drive strength selection: BANK1_PIN03_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 67, LCD_D02 pin voltage selection: BANK1_PIN02_V 0= 1.8V; 1= 3.3V. 9-8 Pin 67, LCD_D02 pin output drive strength selection: BANK1_PIN02_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 69, LCD_D01 pin voltage selection: BANK1_PIN01_V 0= 1.8V; 1= 3.3V. 5-4 Pin 69, LCD_D01 pin output drive strength selection: BANK1_PIN01_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 63, LCD_D00 pin voltage selection: BANK1_PIN00_V 0= 1.8V; 1= 3.3V. BANK1_PIN00_ Pin 63, LCD_D00 pin output drive strength selection: MA 00=low drive strength 01=medium drive strength Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 774 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE4 field descriptions (continued) Field Description 10=high drive strength 11=reserved 9.4.21 PINCTRL Drive Strength and Voltage Register 5 (HW_PINCTRL_DRIVE5) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 1. HW_PINCTRL_DRIVE5: 0x350 HW_PINCTRL_DRIVE5_SET: 0x354 HW_PINCTRL_DRIVE5_CLR: 0x358 HW_PINCTRL_DRIVE5_TOG: 0x35C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK1_PINxx_V configure voltage for both input and output. Address: 8001_8000h base + 350h offset = 8001_8350h 24 23 BANK1_ PIN14_MA 22 21 20 19 RSRVD4 25 BANK1_ PIN13_MA 18 BANK1_PIN12_V BANK1_ PIN15_MA 26 BANK1_PIN13_V 27 RSRVD5 28 BANK1_PIN14_V 29 RSRVD6 R 30 BANK1_PIN15_V 31 RSRVD7 Bit 17 16 BANK1_ PIN12_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 775 Pin Control Memory Map/Register Definition 8 7 BANK1_ PIN10_MA 6 5 4 3 RSRVD0 9 BANK1_ PIN09_MA 2 BANK1_PIN08_V BANK1_ PIN11_MA 10 BANK1_PIN09_V 11 RSRVD1 12 BANK1_PIN10_V 13 RSRVD2 14 BANK1_PIN11_V R RSRVD3 15 Bit 1 0 BANK1_ PIN08_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE5 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 114, LCD_D15 pin voltage selection: BANK1_PIN15_V 0= 1.8V; 1= 3.3V. 29-28 Pin 114, LCD_D15 pin output drive strength selection: BANK1_PIN15_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 106, LCD_D14 pin voltage selection: BANK1_PIN14_V 0= 1.8V; 1= 3.3V. 25-24 Pin 106, LCD_D14 pin output drive strength selection: BANK1_PIN14_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 776 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE5 field descriptions (continued) Field Description 22 Pin 102, LCD_D13 pin voltage selection: BANK1_PIN13_V 0= 1.8V; 1= 3.3V. 21-20 Pin 102, LCD_D13 pin output drive strength selection: BANK1_PIN13_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 87, LCD_D12 pin voltage selection: BANK1_PIN12_V 0= 1.8V; 1= 3.3V. 17-16 Pin 87, LCD_D12 pin output drive strength selection: BANK1_PIN12_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 95, LCD_D11 pin voltage selection: BANK1_PIN11_V 0= 1.8V; 1= 3.3V. 13-12 Pin 95, LCD_D11 pin output drive strength selection: BANK1_PIN11_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 85, LCD_D10 pin voltage selection: BANK1_PIN10_V 0= 1.8V; 1= 3.3V. 9-8 Pin 85, LCD_D10 pin output drive strength selection: BANK1_PIN10_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 777 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE5 field descriptions (continued) Field 7 RSRVD1 Description Always write zeroes to this field. 6 Pin 99, LCD_D09 pin voltage selection: BANK1_PIN09_V 0= 1.8V; 1= 3.3V. 5-4 Pin 99, LCD_D09 pin output drive strength selection: BANK1_PIN09_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 93, LCD_D08 pin voltage selection: BANK1_PIN08_V 0= 1.8V; 1= 3.3V. BANK1_PIN08_ Pin 93, LCD_D08 pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved 9.4.22 PINCTRL Drive Strength and Voltage Register 6 (HW_PINCTRL_DRIVE6) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 1. HW_PINCTRL_DRIVE6: 0x360 HW_PINCTRL_DRIVE6_SET: 0x364 HW_PINCTRL_DRIVE6_CLR: 0x368 HW_PINCTRL_DRIVE6_TOG: 0x36C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK1_PINxx_V configure voltage for both input and output. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 778 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Address: 8001_8000h base + 360h offset = 8001_8360h 24 23 BANK1_ PIN22_MA 22 21 20 19 RSRVD4 25 BANK1_ PIN21_MA 18 BANK1_PIN20_V BANK1_ PIN23_MA 26 BANK1_PIN21_V 27 RSRVD5 28 BANK1_PIN22_V 29 RSRVD6 R 30 BANK1_PIN23_V 31 RSRVD7 Bit 17 16 BANK1_ PIN20_MA W 0 0 1 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK1_ PIN19_MA BANK1_ PIN18_MA BANK1_ PIN17_MA BANK1_PIN16_V 0 RSRVD0 1 BANK1_PIN17_V 0 RSRVD1 0 BANK1_PIN18_V 0 RSRVD2 R 1 BANK1_PIN19_V Bit 0 RSRVD3 Reset BANK1_ PIN16_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE6 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 108, LCD_D23 pin voltage selection: BANK1_PIN23_V 0= 1.8V; 1= 3.3V. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 779 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE6 field descriptions (continued) Field Description 29-28 Pin 108, LCD_D23 pin output drive strength selection: BANK1_PIN23_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 120, LCD_D22 pin voltage selection: BANK1_PIN22_V 0= 1.8V; 1= 3.3V. 25-24 Pin 120, LCD_D22 pin output drive strength selection: BANK1_PIN22_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. 22 Pin 122, LCD_D21 pin voltage selection: BANK1_PIN21_V 0= 1.8V; 1= 3.3V. 21-20 Pin 122, LCD_D21 pin output drive strength selection: BANK1_PIN21_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 107, LCD_D20 pin voltage selection: BANK1_PIN20_V 0= 1.8V; 1= 3.3V. 17-16 Pin 107, LCD_D20 pin output drive strength selection: BANK1_PIN20_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 112, LCD_D19 pin voltage selection: BANK1_PIN19_V 0= 1.8V; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 780 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE6 field descriptions (continued) Field Description 1= 3.3V. 13-12 Pin 112, LCD_D19 pin output drive strength selection: BANK1_PIN19_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 118, LCD_D18 pin voltage selection: BANK1_PIN18_V 0= 1.8V; 1= 3.3V. 9-8 Pin 118, LCD_D18 pin output drive strength selection: BANK1_PIN18_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 105, LCD_D17 pin voltage selection: BANK1_PIN17_V 0= 1.8V; 1= 3.3V. 5-4 Pin 105, LCD_D17 pin output drive strength selection: BANK1_PIN17_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 104, LCD_D16 pin voltage selection: BANK1_PIN16_V 0= 1.8V; 1= 3.3V. BANK1_PIN16_ Pin 104, LCD_D16 pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 781 Pin Control Memory Map/Register Definition 9.4.23 PINCTRL Drive Strength and Voltage Register 7 (HW_PINCTRL_DRIVE7) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 1. HW_PINCTRL_DRIVE7: 0x370 HW_PINCTRL_DRIVE7_SET: 0x374 HW_PINCTRL_DRIVE7_CLR: 0x378 HW_PINCTRL_DRIVE7_TOG: 0x37C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Address: 8001_8000h base + 370h offset = 8001_8370h 24 23 BANK1_ PIN30_MA 22 21 20 19 RSRVD4 25 BANK1_ PIN29_MA 18 BANK1_PIN28_V BANK1_ PIN31_MA 26 BANK1_PIN29_V 27 RSRVD5 28 BANK1_PIN30_V 29 RSRVD6 R 30 BANK1_PIN31_V 31 RSRVD7 Bit 17 16 BANK1_ PIN28_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 782 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 8 7 BANK1_ PIN26_MA 6 5 4 3 RSRVD0 9 BANK1_ PIN25_MA 2 BANK1_PIN24_V BANK1_ PIN27_MA 10 BANK1_PIN25_V 11 RSRVD1 12 BANK1_PIN26_V 13 RSRVD2 14 BANK1_PIN27_V R RSRVD3 15 Bit 1 0 BANK1_ PIN24_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE7 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 111, LCD_ENABLE pin voltage selection: BANK1_PIN31_V 0= 1.8V; 1= 3.3V. 29-28 Pin 111, LCD_ENABLE pin output drive strength selection: BANK1_PIN31_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 73, LCD_DOTCLK pin voltage selection: BANK1_PIN30_V 0= 1.8V; 1= 3.3V. 25-24 Pin 73, LCD_DOTCLK pin output drive strength selection: BANK1_PIN30_ 00=medium drive strength MA 01=medium drive strength 10=very high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 783 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE7 field descriptions (continued) Field Description 22 Pin 71, LCD_HSYNC pin voltage selection: BANK1_PIN29_V 0= 1.8V; 1= 3.3V. 21-20 Pin 71, LCD_HSYNC pin output drive strength selection: BANK1_PIN29_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 59, LCD_VSYNC pin voltage selection: BANK1_PIN28_V 0= 1.8V; 1= 3.3V. 17-16 Pin 59, LCD_VSYNC pin output drive strength selection: BANK1_PIN28_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 113, LCD_CS pin voltage selection: BANK1_PIN27_V 0= 1.8V; 1= 3.3V. 13-12 Pin 113, LCD_CS pin output drive strength selection: BANK1_PIN27_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 94, LCD_RS pin voltage selection: BANK1_PIN26_V 0= 1.8V; 1= 3.3V. 9-8 Pin 94, LCD_RS pin output drive strength selection: BANK1_PIN26_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 784 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE7 field descriptions (continued) Field 7 RSRVD1 Description Always write zeroes to this field. 6 Pin 55, LCD_WR_RWN pin voltage selection: BANK1_PIN25_V 0= 1.8V; 1= 3.3V. 5-4 Pin 55, LCD_WR_RWN pin output drive strength selection: BANK1_PIN25_ 00=medium drive strength MA 01=medium drive strength 10=very high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 96, LCD_RD_E pin voltage selection: BANK1_PIN24_V 0= 1.8V; 1= 3.3V. BANK1_PIN24_ Pin 96, LCD_RD_E pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved 9.4.24 PINCTRL Drive Strength and Voltage Register 8 (HW_PINCTRL_DRIVE8) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 2. HW_PINCTRL_DRIVE8: 0x380 HW_PINCTRL_DRIVE8_SET: 0x384 HW_PINCTRL_DRIVE8_CLR: 0x388 HW_PINCTRL_DRIVE8_TOG: 0x38C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK2_PINxx_V configure voltage for both input and output. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 785 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 380h offset = 8001_8380h 24 23 BANK2_ PIN06_MA 22 21 20 19 RSRVD4 25 BANK2_ PIN05_MA 18 BANK2_PIN04_V BANK2_ PIN07_MA 26 BANK2_PIN05_V 27 RSRVD5 28 BANK2_PIN06_V 29 RSRVD6 R 30 BANK2_PIN07_V 31 RSRVD7 Bit 17 16 BANK2_ PIN04_MA W 0 0 1 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK2_ PIN03_MA BANK2_ PIN02_MA BANK2_ PIN01_MA BANK2_PIN00_V 0 RSRVD0 1 BANK2_PIN01_V 0 RSRVD1 0 BANK2_PIN02_V 0 RSRVD2 R 1 BANK2_PIN03_V Bit 0 RSRVD3 Reset BANK2_ PIN00_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE8 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 282, SSP0_DATA7 pin voltage selection: BANK2_PIN07_V 0= 1.8V; 1= 3.3V. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 786 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE8 field descriptions (continued) Field Description 29-28 Pin 282, SSP0_DATA7 pin output drive strength selection: BANK2_PIN07_ 00=medium drive strength MA 01=medium drive strength 10=very high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 6, SSP0_DATA6 pin voltage selection: BANK2_PIN06_V 0= 1.8V; 1= 3.3V. 25-24 Pin 6, SSP0_DATA6 pin output drive strength selection: BANK2_PIN06_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. 22 Pin 284, SSP0_DATA5 pin voltage selection: BANK2_PIN05_V 0= 1.8V; 1= 3.3V. 21-20 Pin 284, SSP0_DATA5 pin output drive strength selection: BANK2_PIN05_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 278, SSP0_DATA4 pin voltage selection: BANK2_PIN04_V 0= 1.8V; 1= 3.3V. 17-16 Pin 278, SSP0_DATA4 pin output drive strength selection: BANK2_PIN04_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 274, SSP0_DATA3 pin voltage selection: BANK2_PIN03_V 0= 1.8V; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 787 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE8 field descriptions (continued) Field Description 1= 3.3V. 13-12 Pin 274, SSP0_DATA3 pin output drive strength selection: BANK2_PIN03_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 2, SSP0_DATA2 pin voltage selection: BANK2_PIN02_V 0= 1.8V; 1= 3.3V. 9-8 Pin 2, SSP0_DATA2 pin output drive strength selection: BANK2_PIN02_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 289, SSP0_DATA1 pin voltage selection: BANK2_PIN01_V 0= 1.8V; 1= 3.3V. 5-4 Pin 289, SSP0_DATA1 pin output drive strength selection: BANK2_PIN01_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 270, SSP0_DATA0 pin voltage selection: BANK2_PIN00_V 0= 1.8V; 1= 3.3V. BANK2_PIN00_ Pin 270, SSP0_DATA0 pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 788 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 9.4.25 PINCTRL Drive Strength and Voltage Register 9 (HW_PINCTRL_DRIVE9) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 7 pins of bank 2. HW_PINCTRL_DRIVE9: 0x390 HW_PINCTRL_DRIVE9_SET: 0x394 HW_PINCTRL_DRIVE9_CLR: 0x398 HW_PINCTRL_DRIVE9_TOG: 0x39C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK2_PINxx_V configure voltage for both input and output. Address: 8001_8000h base + 390h offset = 8001_8390h 24 23 BANK2_ PIN14_MA 22 21 20 19 RSRVD4 25 BANK2_ PIN13_MA 18 BANK2_PIN12_V BANK2_ PIN15_MA 26 BANK2_PIN13_V 27 RSRVD5 28 BANK2_PIN14_V 29 RSRVD6 R 30 BANK2_PIN15_V 31 RSRVD7 Bit 17 16 BANK2_ PIN12_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 789 Pin Control Memory Map/Register Definition 9 8 7 BANK2_ PIN10_MA 6 5 4 3 BANK2_ PIN09_MA 2 BANK2_PIN08_V 10 RSRVD0 RSRVD3 R 11 BANK2_PIN09_V 12 RSRVD1 13 BANK2_PIN10_V 14 RSRVD2 15 Bit 1 0 BANK2_ PIN08_MA W Reset 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE9 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 23, SSP1_DATA3 pin voltage selection: BANK2_PIN15_V 0= 1.8V; 1= 3.3V. 29-28 Pin 23, SSP1_DATA3 pin output drive strength selection: BANK2_PIN15_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 21, SSP1_DATA0 pin voltage selection: BANK2_PIN14_V 0= 1.8V; 1= 3.3V. 25-24 Pin 21, SSP1_DATA0 pin output drive strength selection: BANK2_PIN14_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 790 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE9 field descriptions (continued) Field Description 22 Pin 17, SSP1_CMD pin voltage selection: BANK2_PIN13_V 0= 1.8V; 1= 3.3V. 21-20 Pin 17, SSP1_CMD pin output drive strength selection: BANK2_PIN13_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 11, SSP1_SCK pin voltage selection: BANK2_PIN12_V 0= 1.8V; 1= 3.3V. 17-16 Pin 11, SSP1_SCK pin output drive strength selection: BANK2_PIN12_ 00=medium drive strength MA 01=medium drive strength 10=very high drive strength 11=reserved 15-12 RSRVD3 Always write zeroes to this field. 11 RSRVD2 Always write zeroes to this field. 10 Pin 268, SSP0_SCK pin voltage selection: BANK2_PIN10_V 0= 1.8V; 1= 3.3V. 9-8 Pin 268, SSP0_SCK pin output drive strength selection: BANK2_PIN10_ 00=medium drive strength MA 01=medium drive strength 10=very high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 275, SSP0_DETECT pin voltage selection: BANK2_PIN09_V 0= 1.8V; 1= 3.3V. 5-4 Pin 275, SSP0_DETECT pin output drive strength selection: BANK2_PIN09_ 00=low drive strength MA 01=medium drive strength 10=high drive strength Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 791 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE9 field descriptions (continued) Field Description 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 276, SSP0_CMD pin voltage selection: BANK2_PIN08_V 0= 1.8V; 1= 3.3V. BANK2_PIN08_ Pin 276, SSP0_CMD pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved 9.4.26 PINCTRL Drive Strength and Voltage Register 10 (HW_PINCTRL_DRIVE10) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 6 pins of bank 2. HW_PINCTRL_DRIVE10: 0x3a0 HW_PINCTRL_DRIVE10_SET: 0x3a4 HW_PINCTRL_DRIVE10_CLR: 0x3a8 HW_PINCTRL_DRIVE10_TOG: 0x3aC The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK2_PINxx_V configure voltage for both input and output. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 792 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Address: 8001_8000h base + 3A0h offset = 8001_83A0h 28 27 26 25 24 RSRVD6 R 23 22 21 20 19 BANK2_ PIN21_MA 18 BANK2_PIN20_V 29 RSRVD4 30 BANK2_PIN21_V 31 RSRVD5 Bit 17 16 BANK2_ PIN20_MA W 0 0 1 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK2_ PIN19_MA BANK2_ PIN18_MA BANK2_ PIN17_MA BANK2_PIN16_V 0 RSRVD0 0 BANK2_PIN17_V 0 RSRVD1 0 BANK2_PIN18_V 0 RSRVD2 R 0 BANK2_PIN19_V Bit 0 RSRVD3 Reset BANK2_ PIN16_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE10 field descriptions Field Description 31-24 RSRVD6 Always write zeroes to this field. 23 RSRVD5 Always write zeroes to this field. 22 Pin 18, SSP2_SS2 pin voltage selection: BANK2_PIN21_V 0= 1.8V; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 793 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE10 field descriptions (continued) Field Description 1= 3.3V. 21-20 Pin 18, SSP2_SS2 pin output drive strength selection: BANK2_PIN21_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 7, SSP2_SS1 pin voltage selection: BANK2_PIN20_V 0= 1.8V; 1= 3.3V. 17-16 Pin 7, SSP2_SS1 pin output drive strength selection: BANK2_PIN20_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 4, SSP2_SS0 pin voltage selection: BANK2_PIN19_V 0= 1.8V; 1= 3.3V. 13-12 Pin 4, SSP2_SS0 pin output drive strength selection: BANK2_PIN19_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 288, SSP2_MISO pin voltage selection: BANK2_PIN18_V 0= 1.8V; 1= 3.3V. 9-8 Pin 288, SSP2_MISO pin output drive strength selection: BANK2_PIN18_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 1, SSP2_MOSI pin voltage selection: BANK2_PIN17_V Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 794 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE10 field descriptions (continued) Field Description 0= 1.8V; 1= 3.3V. 5-4 Pin 1, SSP2_MOSI pin output drive strength selection: BANK2_PIN17_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 280, SSP2_SCK pin voltage selection: BANK2_PIN16_V 0= 1.8V; 1= 3.3V. BANK2_PIN16_ Pin 280, SSP2_SCK pin output drive strength selection: MA 00=medium drive strength 01=medium drive strength 10=very high drive strength 11=reserved 9.4.27 PINCTRL Drive Strength and Voltage Register 11 (HW_PINCTRL_DRIVE11) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 4 pins of bank 2. HW_PINCTRL_DRIVE11: 0x3b0 HW_PINCTRL_DRIVE11_SET: 0x3b4 HW_PINCTRL_DRIVE11_CLR: 0x3b8 HW_PINCTRL_DRIVE11_TOG: 0x3bC The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK2_PINxx_V configure voltage for both input and output. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 795 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 3B0h offset = 8001_83B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD4 R W 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK2_ PIN27_MA BANK2_ PIN26_MA BANK2_ PIN25_MA BANK2_PIN24_V 0 RSRVD0 0 BANK2_PIN25_V 0 RSRVD1 0 BANK2_PIN26_V 0 RSRVD2 R 0 BANK2_PIN27_V Bit 0 RSRVD3 Reset BANK2_ PIN24_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE11 field descriptions Field Description 31-16 RSRVD4 Always write zeroes to this field. 15 RSRVD3 Always write zeroes to this field. 14 Pin 15, SSP3_SS0 pin voltage selection: BANK2_PIN27_V 0= 1.8V; 1= 3.3V. 13-12 Pin 15, SSP3_SS0 pin output drive strength selection: BANK2_PIN27_ 00=low drive strength MA 01=medium drive strength Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 796 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE11 field descriptions (continued) Field Description 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 3, SSP3_MISO pin voltage selection: BANK2_PIN26_V 0= 1.8V; 1= 3.3V. 9-8 Pin 3, SSP3_MISO pin output drive strength selection: BANK2_PIN26_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 9, SSP3_MOSI pin voltage selection: BANK2_PIN25_V 0= 1.8V; 1= 3.3V. 5-4 Pin 9, SSP3_MOSI pin output drive strength selection: BANK2_PIN25_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 286, SSP3_SCK pin voltage selection: BANK2_PIN24_V 0= 1.8V; 1= 3.3V. BANK2_PIN24_ Pin 286, SSP3_SCK pin output drive strength selection: MA 00=medium drive strength 01=medium drive strength 10=very high drive strength 11=reserved 9.4.28 PINCTRL Drive Strength and Voltage Register 12 (HW_PINCTRL_DRIVE12) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 3. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 797 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE12: 0x3c0 HW_PINCTRL_DRIVE12_SET: 0x3c4 HW_PINCTRL_DRIVE12_CLR: 0x3c8 HW_PINCTRL_DRIVE12_TOG: 0x3cC The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK3_PINxx_V configure voltage for both input and output. Address: 8001_8000h base + 3C0h offset = 8001_83C0h 24 23 BANK3_ PIN06_MA 22 21 20 19 RSRVD4 25 BANK3_ PIN05_MA 18 BANK3_PIN04_V BANK3_ PIN07_MA 26 BANK3_PIN05_V 27 RSRVD5 28 BANK3_PIN06_V 29 RSRVD6 R 30 BANK3_PIN07_V 31 RSRVD7 Bit 17 16 BANK3_ PIN04_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 798 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 8 7 BANK3_ PIN02_MA 6 5 4 3 RSRVD0 9 BANK3_ PIN01_MA 2 BANK3_PIN00_V BANK3_ PIN03_MA 10 BANK3_PIN01_V 11 RSRVD1 12 BANK3_PIN02_V 13 RSRVD2 14 BANK3_PIN03_V R RSRVD3 15 Bit 1 0 BANK3_ PIN00_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE12 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 74, AUART1_RTS pin voltage selection: BANK3_PIN07_V 0= 1.8V; 1= 3.3V. 29-28 Pin 74, AUART1_RTS pin output drive strength selection: BANK3_PIN07_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 78, AUART1_CTS pin voltage selection: BANK3_PIN06_V 0= 1.8V; 1= 3.3V. 25-24 Pin 78, AUART1_CTS pin output drive strength selection: BANK3_PIN06_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 799 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE12 field descriptions (continued) Field Description 22 Pin 65, AUART1_TX pin voltage selection: BANK3_PIN05_V 0= 1.8V; 1= 3.3V. 21-20 Pin 65, AUART1_TX pin output drive strength selection: BANK3_PIN05_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 81, AUART1_RX pin voltage selection: BANK3_PIN04_V 0= 1.8V; 1= 3.3V. 17-16 Pin 81, AUART1_RX pin output drive strength selection: BANK3_PIN04_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 66, AUART0_RTS pin voltage selection: BANK3_PIN03_V 0= 1.8V; 1= 3.3V. 13-12 Pin 66, AUART0_RTS pin output drive strength selection: BANK3_PIN03_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 70, AUART0_CTS pin voltage selection: BANK3_PIN02_V 0= 1.8V; 1= 3.3V. 9-8 Pin 70, AUART0_CTS pin output drive strength selection: BANK3_PIN02_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 800 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE12 field descriptions (continued) Field 7 RSRVD1 Description Always write zeroes to this field. 6 Pin 38, AUART0_TX pin voltage selection: BANK3_PIN01_V 0= 1.8V; 1= 3.3V. 5-4 Pin 38, AUART0_TX pin output drive strength selection: BANK3_PIN01_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 30, AUART0_RX pin voltage selection: BANK3_PIN00_V 0= 1.8V; 1= 3.3V. BANK3_PIN00_ Pin 30, AUART0_RX pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved 9.4.29 PINCTRL Drive Strength and Voltage Register 13 (HW_PINCTRL_DRIVE13) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 3. HW_PINCTRL_DRIVE13: 0x3d0 HW_PINCTRL_DRIVE13_SET: 0x3d4 HW_PINCTRL_DRIVE13_CLR: 0x3d8 HW_PINCTRL_DRIVE13_TOG: 0x3dC The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK3_PINxx_V configure voltage for both input and output. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 801 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 3D0h offset = 8001_83D0h 24 23 BANK3_ PIN14_MA 22 21 20 19 RSRVD4 25 BANK3_ PIN13_MA 18 BANK3_PIN12_V BANK3_ PIN15_MA 26 BANK3_PIN13_V 27 RSRVD5 28 BANK3_PIN14_V 29 RSRVD6 R 30 BANK3_PIN15_V 31 RSRVD7 Bit 17 16 BANK3_ PIN12_MA W 0 0 1 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK3_ PIN11_MA BANK3_ PIN10_MA BANK3_ PIN09_MA BANK3_PIN08_V 0 RSRVD0 1 BANK3_PIN09_V 0 RSRVD1 0 BANK3_PIN10_V 0 RSRVD2 R 1 BANK3_PIN11_V Bit 0 RSRVD3 Reset BANK3_ PIN08_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE13 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 82, AUART3_RTS pin voltage selection: BANK3_PIN15_V 0= 1.8V; 1= 3.3V. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 802 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE13 field descriptions (continued) Field Description 29-28 Pin 82, AUART3_RTS pin output drive strength selection: BANK3_PIN15_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 90, AUART3_CTS pin voltage selection: BANK3_PIN14_V 0= 1.8V; 1= 3.3V. 25-24 Pin 90, AUART3_CTS pin output drive strength selection: BANK3_PIN14_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. 22 Pin 86, AUART3_TX pin voltage selection: BANK3_PIN13_V 0= 1.8V; 1= 3.3V. 21-20 Pin 86, AUART3_TX pin output drive strength selection: BANK3_PIN13_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 98, AUART3_RX pin voltage selection: BANK3_PIN12_V 0= 1.8V; 1= 3.3V. 17-16 Pin 98, AUART3_RX pin output drive strength selection: BANK3_PIN12_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 56, AUART2_RTS pin voltage selection: BANK3_PIN11_V 0= 1.8V; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 803 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE13 field descriptions (continued) Field Description 1= 3.3V. 13-12 Pin 56, AUART2_RTS pin output drive strength selection: BANK3_PIN11_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 50, AUART2_CTS pin voltage selection: BANK3_PIN10_V 0= 1.8V; 1= 3.3V. 9-8 Pin 50, AUART2_CTS pin output drive strength selection: BANK3_PIN10_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 26, AUART2_TX pin voltage selection: BANK3_PIN09_V 0= 1.8V; 1= 3.3V. 5-4 Pin 26, AUART2_TX pin output drive strength selection: BANK3_PIN09_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 22, AUART2_RX pin voltage selection: BANK3_PIN08_V 0= 1.8V; 1= 3.3V. BANK3_PIN08_ Pin 22, AUART2_RX pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 804 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 9.4.30 PINCTRL Drive Strength and Voltage Register 14 (HW_PINCTRL_DRIVE14) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 7 pins of bank 3. HW_PINCTRL_DRIVE14: 0x3e0 HW_PINCTRL_DRIVE14_SET: 0x3e4 HW_PINCTRL_DRIVE14_CLR: 0x3e8 HW_PINCTRL_DRIVE14_TOG: 0x3eC The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK3_PINxx_V configure voltage for both input and output. Address: 8001_8000h base + 3E0h offset = 8001_83E0h 24 23 BANK3_ PIN22_MA 22 21 20 19 RSRVD4 25 BANK3_ PIN21_MA 18 BANK3_PIN20_V BANK3_ PIN23_MA 26 BANK3_PIN21_V 27 RSRVD5 28 BANK3_PIN22_V 29 RSRVD6 R 30 BANK3_PIN23_V 31 RSRVD7 Bit 17 16 BANK3_ PIN20_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 805 Pin Control Memory Map/Register Definition 9 8 7 BANK3_ PIN18_MA 6 5 4 3 BANK3_ PIN17_MA 2 BANK3_PIN16_V 10 RSRVD0 RSRVD3 R 11 BANK3_PIN17_V 12 RSRVD1 13 BANK3_PIN18_V 14 RSRVD2 15 Bit 1 0 BANK3_ PIN16_MA W Reset 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE14 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 12, SAIF0_SDATA0 pin voltage selection: BANK3_PIN23_V 0= 1.8V; 1= 3.3V. 29-28 Pin 12, SAIF0_SDATA0 pin output drive strength selection: BANK3_PIN23_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 16, SAIF0_BITCLK pin voltage selection: BANK3_PIN22_V 0= 1.8V; 1= 3.3V. 25-24 Pin 16, SAIF0_BITCLK pin output drive strength selection: BANK3_PIN22_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 806 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE14 field descriptions (continued) Field Description 22 Pin 34, SAIF0_LRCLK pin voltage selection: BANK3_PIN21_V 0= 1.8V; 1= 3.3V. 21-20 Pin 34, SAIF0_LRCLK pin output drive strength selection: BANK3_PIN21_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 28, SAIF0_MCLK pin voltage selection: BANK3_PIN20_V 0= 1.8V; 1= 3.3V. 17-16 Pin 28, SAIF0_MCLK pin output drive strength selection: BANK3_PIN20_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15-12 RSRVD3 Always write zeroes to this field. 11 RSRVD2 Always write zeroes to this field. 10 Pin 68, PWM2 pin voltage selection: BANK3_PIN18_V 0= 1.8V; 1= 3.3V. 9-8 Pin 68, PWM2 pin output drive strength selection: BANK3_PIN18_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 84, PWM1 pin voltage selection: BANK3_PIN17_V 0= 1.8V; 1= 3.3V. 5-4 Pin 84, PWM1 pin output drive strength selection: BANK3_PIN17_ 00=low drive strength MA 01=medium drive strength 10=high drive strength Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 807 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE14 field descriptions (continued) Field Description 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 72, PWM0 pin voltage selection: BANK3_PIN16_V 0= 1.8V; 1= 3.3V. BANK3_PIN16_ Pin 72, PWM0 pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved 9.4.31 PINCTRL Drive Strength and Voltage Register 15 (HW_PINCTRL_DRIVE15) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 7 pins of bank 3. HW_PINCTRL_DRIVE15: 0x3f0 HW_PINCTRL_DRIVE15_SET: 0x3f4 HW_PINCTRL_DRIVE15_CLR: 0x3f8 HW_PINCTRL_DRIVE15_TOG: 0x3fC The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK3_PINxx_V configure voltage for both input and output. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 808 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Address: 8001_8000h base + 3F0h offset = 8001_83F0h 26 25 24 23 BANK3_ PIN30_MA 22 21 20 19 BANK3_ PIN29_MA 18 BANK3_PIN28_V RSRVD7 R 27 RSRVD4 28 BANK3_PIN29_V 29 RSRVD5 30 BANK3_PIN30_V 31 RSRVD6 Bit 17 16 BANK3_ PIN28_MA W 0 0 1 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK3_ PIN27_MA BANK3_ PIN26_MA BANK3_ PIN25_MA BANK3_PIN24_V 0 RSRVD0 1 BANK3_PIN25_V 0 RSRVD1 0 BANK3_PIN26_V 0 RSRVD2 R 0 BANK3_PIN27_V Bit 0 RSRVD3 Reset BANK3_ PIN24_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE15 field descriptions Field Description 31-28 RSRVD7 Always write zeroes to this field. 27 RSRVD6 Always write zeroes to this field. 26 Pin 101, LCD_RESET pin voltage selection: BANK3_PIN30_V 0= 1.8V; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 809 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE15 field descriptions (continued) Field Description 1= 3.3V. 25-24 Pin 101, LCD_RESET pin output drive strength selection: BANK3_PIN30_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. 22 Pin 279, PWM4 pin voltage selection: BANK3_PIN29_V 0= 1.8V; 1= 3.3V. 21-20 Pin 279, PWM4 pin output drive strength selection: BANK3_PIN29_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 287, PWM3 pin voltage selection: BANK3_PIN28_V 0= 1.8V; 1= 3.3V. 17-16 Pin 287, PWM3 pin output drive strength selection: BANK3_PIN28_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 285, SPDIF pin voltage selection: BANK3_PIN27_V 0= 1.8V; 1= 3.3V. 13-12 Pin 285, SPDIF pin output drive strength selection: BANK3_PIN27_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 8, SAIF1_SDATA0 pin voltage selection: BANK3_PIN26_V Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 810 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE15 field descriptions (continued) Field Description 0= 1.8V; 1= 3.3V. 9-8 Pin 8, SAIF1_SDATA0 pin output drive strength selection: BANK3_PIN26_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 281, I2C0_SDA pin voltage selection: BANK3_PIN25_V 0= 1.8V; 1= 3.3V. 5-4 Pin 281, I2C0_SDA pin output drive strength selection: BANK3_PIN25_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 272, I2C0_SCL pin voltage selection: BANK3_PIN24_V 0= 1.8V; 1= 3.3V. BANK3_PIN24_ Pin 272, I2C0_SCL pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved 9.4.32 PINCTRL Drive Strength and Voltage Register 16 (HW_PINCTRL_DRIVE16) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 4. HW_PINCTRL_DRIVE16: 0x400 HW_PINCTRL_DRIVE16_SET: 0x404 HW_PINCTRL_DRIVE16_CLR: 0x408 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 811 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE16_TOG: 0x40C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Address: 8001_8000h base + 400h offset = 8001_8400h 24 23 BANK4_ PIN06_MA 22 21 20 19 RSRVD4 25 BANK4_ PIN05_MA 18 BANK4_PIN04_V BANK4_ PIN07_MA 26 BANK4_PIN05_V 27 RSRVD5 28 BANK4_PIN06_V 29 RSRVD6 R 30 BANK4_PIN07_V 31 RSRVD7 Bit 17 16 BANK4_ PIN04_MA W 0 0 1 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK4_ PIN03_MA BANK4_ PIN02_MA BANK4_ PIN01_MA BANK4_PIN00_V 0 RSRVD0 1 BANK4_PIN01_V 0 RSRVD1 0 BANK4_PIN02_V 0 RSRVD2 R 1 BANK4_PIN03_V Bit 0 RSRVD3 Reset BANK4_ PIN00_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 812 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE16 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 37, ENET0_TXD0 pin voltage selection: BANK4_PIN07_V 0= 1.8V; 1= 3.3V. 29-28 Pin 37, ENET0_TXD0 pin output drive strength selection: BANK4_PIN07_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 29, ENET0_TX_EN pin voltage selection: BANK4_PIN06_V 0= 1.8V; 1= 3.3V. 25-24 Pin 29, ENET0_TX_EN pin output drive strength selection: BANK4_PIN06_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. 22 Pin 13, ENET0_TX_CLK pin voltage selection: BANK4_PIN05_V 0= 1.8V; 1= 3.3V. 21-20 Pin 13, ENET0_TX_CLK pin output drive strength selection: BANK4_PIN05_ 00=medium drive strength MA 01=medium drive strength 10=very high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 47, ENET0_RXD1 pin voltage selection: BANK4_PIN04_V 0= 1.8V; 1= 3.3V. 17-16 Pin 47, ENET0_RXD1 pin output drive strength selection: BANK4_PIN04_ 00=low drive strength MA 01=medium drive strength 10=high drive strength Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 813 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE16 field descriptions (continued) Field Description 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 45, ENET0_RXD0 pin voltage selection: BANK4_PIN03_V 0= 1.8V; 1= 3.3V. 13-12 Pin 45, ENET0_RXD0 pin output drive strength selection: BANK4_PIN03_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 27, ENET0_RX_EN pin voltage selection: BANK4_PIN02_V 0= 1.8V; 1= 3.3V. 9-8 Pin 27, ENET0_RX_EN pin output drive strength selection: BANK4_PIN02_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 7 RSRVD1 Always write zeroes to this field. 6 Pin 39, ENET0_MDIO pin voltage selection: BANK4_PIN01_V 0= 1.8V; 1= 3.3V. 5-4 Pin 39, ENET0_MDIO pin output drive strength selection: BANK4_PIN01_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 54, ENET0_MDC pin voltage selection: BANK4_PIN00_V 0= 1.8V; 1= 3.3V. BANK4_PIN00_ Pin 54, ENET0_MDC pin output drive strength selection: MA 00=low drive strength 01=medium drive strength Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 814 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE16 field descriptions (continued) Field Description 10=high drive strength 11=reserved 9.4.33 PINCTRL Drive Strength and Voltage Register 17 (HW_PINCTRL_DRIVE17) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 8 pins of bank 4. HW_PINCTRL_DRIVE17: 0x410 HW_PINCTRL_DRIVE17_SET: 0x414 HW_PINCTRL_DRIVE17_CLR: 0x418 HW_PINCTRL_DRIVE17_TOG: 0x41C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Address: 8001_8000h base + 410h offset = 8001_8410h 24 23 BANK4_ PIN14_MA 22 21 20 19 RSRVD4 25 BANK4_ PIN13_MA 18 BANK4_PIN12_V BANK4_ PIN15_MA 26 BANK4_PIN13_V 27 RSRVD5 28 BANK4_PIN14_V 29 RSRVD6 R 30 BANK4_PIN15_V 31 RSRVD7 Bit 17 16 BANK4_ PIN12_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 815 Pin Control Memory Map/Register Definition 8 7 BANK4_ PIN10_MA 6 5 4 3 RSRVD0 9 BANK4_ PIN09_MA 2 BANK4_PIN08_V BANK4_ PIN11_MA 10 BANK4_PIN09_V 11 RSRVD1 12 BANK4_PIN10_V 13 RSRVD2 14 BANK4_PIN11_V R RSRVD3 15 Bit 1 0 BANK4_ PIN08_MA W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 HW_PINCTRL_DRIVE17 field descriptions Field 31 RSRVD7 Description Always write zeroes to this field. 30 Pin 61, ENET0_CRS pin voltage selection: BANK4_PIN15_V 0= 1.8V; 1= 3.3V. 29-28 Pin 61, ENET0_CRS pin output drive strength selection: BANK4_PIN15_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 27 RSRVD6 Always write zeroes to this field. 26 Pin 57, ENET0_COL pin voltage selection: BANK4_PIN14_V 0= 1.8V; 1= 3.3V. 25-24 Pin 57, ENET0_COL pin output drive strength selection: BANK4_PIN14_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 23 RSRVD5 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 816 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DRIVE17 field descriptions (continued) Field Description 22 Pin 31, ENET0_RX_CLK pin voltage selection: BANK4_PIN13_V 0= 1.8V; 1= 3.3V. 21-20 Pin 31, ENET0_RX_CLK pin output drive strength selection: BANK4_PIN13_ 00=medium drive strength MA 01=medium drive strength 10=very high drive strength 11=reserved 19 RSRVD4 Always write zeroes to this field. 18 Pin 41, ENET0_TXD3 pin voltage selection: BANK4_PIN12_V 0= 1.8V; 1= 3.3V. 17-16 Pin 41, ENET0_TXD3 pin output drive strength selection: BANK4_PIN12_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15 RSRVD3 Always write zeroes to this field. 14 Pin 43, ENET0_TXD2 pin voltage selection: BANK4_PIN11_V 0= 1.8V; 1= 3.3V. 13-12 Pin 43, ENET0_TXD2 pin output drive strength selection: BANK4_PIN11_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 11 RSRVD2 Always write zeroes to this field. 10 Pin 53, ENET0_RXD3 pin voltage selection: BANK4_PIN10_V 0= 1.8V; 1= 3.3V. 9-8 Pin 53, ENET0_RXD3 pin output drive strength selection: BANK4_PIN10_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 817 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE17 field descriptions (continued) Field 7 RSRVD1 Description Always write zeroes to this field. 6 Pin 51, ENET0_RXD2 pin voltage selection: BANK4_PIN09_V 0= 1.8V; 1= 3.3V. 5-4 Pin 51, ENET0_RXD2 pin output drive strength selection: BANK4_PIN09_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 3 RSRVD0 Always write zeroes to this field. 2 Pin 35, ENET0_TXD1 pin voltage selection: BANK4_PIN08_V 0= 1.8V; 1= 3.3V. BANK4_PIN08_ Pin 35, ENET0_TXD1 pin output drive strength selection: MA 00=low drive strength 01=medium drive strength 10=high drive strength 11=reserved 9.4.34 PINCTRL Drive Strength and Voltage Register 18 (HW_PINCTRL_DRIVE18) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 2 pins of bank 4. HW_PINCTRL_DRIVE18: 0x420 HW_PINCTRL_DRIVE18_SET: 0x424 HW_PINCTRL_DRIVE18_CLR: 0x428 HW_PINCTRL_DRIVE18_TOG: 0x42C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 818 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Address: 8001_8000h base + 420h offset = 8001_8420h 30 29 28 27 26 25 24 23 22 21 20 RSRVD3 R 19 18 BANK4_PIN20_V 31 RSRVD2 Bit 17 16 BANK4_ PIN20_MA W 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD1 R BANK4_PIN16_V Bit 0 RSRVD0 Reset BANK4_ PIN16_MA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 HW_PINCTRL_DRIVE18 field descriptions Field Description 31-20 RSRVD3 Always write zeroes to this field. 19 RSRVD2 Always write zeroes to this field. 18 Pin 230, JTAG_RTCK pin voltage selection: BANK4_PIN20_V 0= 1.8V; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 819 Pin Control Memory Map/Register Definition HW_PINCTRL_DRIVE18 field descriptions (continued) Field Description 1= 3.3V. 17-16 Pin 230, JTAG_RTCK pin output drive strength selection: BANK4_PIN20_ 00=low drive strength MA 01=medium drive strength 10=high drive strength 11=reserved 15-4 RSRVD1 Always write zeroes to this field. 3 RSRVD0 Always write zeroes to this field. 2 Pin 19, ENET_CLK pin voltage selection: BANK4_PIN16_V 0= 1.8V; 1= 3.3V. BANK4_PIN16_ Pin 19, ENET_CLK pin output drive strength selection: MA 00=medium drive strength 01=medium drive strength 10=very high drive strength 11=reserved 9.4.35 PINCTRL Drive Strength and Voltage Register 19 (HW_PINCTRL_DRIVE19) The PINCTRL Drive Strength and Voltage Register selects the current drive strength for 0 pins of bank 4. HW_PINCTRL_DRIVE19: 0x430 HW_PINCTRL_DRIVE19_SET: 0x434 HW_PINCTRL_DRIVE19_CLR: 0x438 HW_PINCTRL_DRIVE19_TOG: 0x43C The Drive Strength and Voltage Register selects the drive strength and voltage for pins that are configured for output. Fields BANK4_PINxx_V configure voltage for both input and output. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 820 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Address: 8001_8000h base + 430h offset = 8001_8430h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DRIVE19 field descriptions Field Description RSRVD0 Always write zeroes to this field. 9.4.36 PINCTRL Bank 0 Pull Up Resistor Enable Register (HW_PINCTRL_PULL0) The PINCTRL Bank 0 PULL Register enables/disables the internal pull up resistors for those pins in bank 0 which support this operation. HW_PINCTRL_PULL0: 0x600 HW_PINCTRL_PULL0_SET: 0x604 HW_PINCTRL_PULL0_CLR: 0x608 HW_PINCTRL_PULL0_TOG: 0x60C The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. 22 21 20 19 18 17 16 BANK0_PIN18 BANK0_PIN17 BANK0_PIN16 0 23 BANK0_PIN19 0 24 BANK0_PIN20 0 25 BANK0_PIN21 Reset 26 BANK0_PIN22 W 27 BANK0_PIN23 RSRVD1 R 28 BANK0_PIN24 29 BANK0_PIN25 30 BANK0_PIN26 31 BANK0_PIN27 Bit BANK0_PIN28 Address: 8001_8000h base + 600h offset = 8001_8600h 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 821 8 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 7 6 5 4 3 2 1 0 BANK0_PIN00 9 BANK0_PIN01 10 BANK0_PIN02 11 BANK0_PIN03 12 BANK0_PIN04 13 BANK0_PIN05 14 BANK0_PIN06 15 Bit BANK0_PIN07 Pin Control Memory Map/Register Definition 0 0 0 0 0 0 0 0 HW_PINCTRL_PULL0 field descriptions Field 31-29 RSRVD1 28 BANK0_PIN28 27 BANK0_PIN27 26 BANK0_PIN26 25 BANK0_PIN25 24 BANK0_PIN24 23 BANK0_PIN23 22 BANK0_PIN22 21 BANK0_PIN21 20 BANK0_PIN20 19 BANK0_PIN19 18 BANK0_PIN18 17 BANK0_PIN17 16 BANK0_PIN16 Description Always write zeroes to this field. Set this bit to one to enable the internal pullup on pin 129, GPMI_RESETN. Set this bit to one to enable the internal pullup on pin 123, GPMI_CLE. Set this bit to one to enable the internal pullup on pin 117, GPMI_ALE. Set this bit to one to disable the internal keeper on pin 127, GPMI_WRN. Set this bit to one to enable the internal pullup on pin 110, GPMI_RDN. Set this bit to one to enable the internal pullup on pin 80, GPMI_RDY3. Set this bit to one to enable the internal pullup on pin 88, GPMI_RDY2. Set this bit to one to enable the internal pullup on pin 119, GPMI_RDY1. Set this bit to one to enable the internal pullup on pin 103, GPMI_RDY0. Set this bit to one to enable the internal pullup on pin 135, GPMI_CE3N. Set this bit to one to enable the internal pullup on pin 92, GPMI_CE2N. Set this bit to one to enable the internal pullup on pin 131, GPMI_CE1N. Set this bit to one to enable the internal pullup on pin 115, GPMI_CE0N. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 822 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_PULL0 field descriptions (continued) Field 15-8 RSRVD0 7 BANK0_PIN07 6 BANK0_PIN06 5 BANK0_PIN05 4 BANK0_PIN04 3 BANK0_PIN03 2 BANK0_PIN02 1 BANK0_PIN01 0 BANK0_PIN00 Description Always write zeroes to this field. Set this bit to one to enable the internal pullup on pin 124, GPMI_D07. Set this bit to one to enable the internal pullup on pin 130, GPMI_D06. Set this bit to one to enable the internal pullup on pin 116, GPMI_D05. Set this bit to one to enable the internal pullup on pin 128, GPMI_D04. Set this bit to one to enable the internal pullup on pin 132, GPMI_D03. Set this bit to one to enable the internal pullup on pin 126, GPMI_D02. Set this bit to one to enable the internal pullup on pin 136, GPMI_D01. Set this bit to one to enable the internal pullup on pin 134, GPMI_D00. 9.4.37 PINCTRL Bank 1 Pull Up Resistor Enable Register (HW_PINCTRL_PULL1) The PINCTRL Bank 1 PULL Register enables/disables the internal pull up resistors for those pins in bank 1 which support this operation. HW_PINCTRL_PULL1: 0x610 HW_PINCTRL_PULL1_SET: 0x614 HW_PINCTRL_PULL1_CLR: 0x618 HW_PINCTRL_PULL1_TOG: 0x61C The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 823 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 610h offset = 8001_8610h BANK1_PIN23 BANK1_PIN22 BANK1_PIN21 BANK1_PIN20 BANK1_PIN19 BANK1_PIN18 BANK1_PIN17 BANK1_PIN16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK1_PIN07 BANK1_PIN06 BANK1_PIN05 BANK1_PIN04 BANK1_PIN03 BANK1_PIN02 BANK1_PIN01 BANK1_PIN00 16 BANK1_PIN24 17 BANK1_PIN08 18 BANK1_PIN25 19 BANK1_PIN09 20 BANK1_PIN26 21 BANK1_PIN10 22 BANK1_PIN27 23 BANK1_PIN11 24 BANK1_PIN28 Reset 25 BANK1_PIN12 W 26 BANK1_PIN29 R 27 BANK1_PIN13 Bit 28 BANK1_PIN30 Reset 29 BANK1_PIN14 W 30 BANK1_PIN31 R 31 BANK1_PIN15 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_PULL1 field descriptions Field 31 BANK1_PIN31 30 BANK1_PIN30 29 BANK1_PIN29 28 BANK1_PIN28 27 BANK1_PIN27 26 BANK1_PIN26 25 BANK1_PIN25 24 BANK1_PIN24 23 BANK1_PIN23 22 BANK1_PIN22 21 BANK1_PIN21 20 BANK1_PIN20 Description Set this bit to one to disable the internal keeper on pin 111, LCD_ENABLE. Set this bit to one to disable the internal keeper on pin 73, LCD_DOTCLK. Set this bit to one to disable the internal keeper on pin 71, LCD_HSYNC. Set this bit to one to disable the internal keeper on pin 59, LCD_VSYNC. Set this bit to one to disable the internal keeper on pin 113, LCD_CS. Set this bit to one to disable the internal keeper on pin 94, LCD_RS. Set this bit to one to disable the internal keeper on pin 55, LCD_WR_RWN. Set this bit to one to disable the internal keeper on pin 96, LCD_RD_E. Set this bit to one to disable the internal keeper on pin 108, LCD_D23. Set this bit to one to disable the internal keeper on pin 120, LCD_D22. Set this bit to one to disable the internal keeper on pin 122, LCD_D21. Set this bit to one to disable the internal keeper on pin 107, LCD_D20. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 824 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_PULL1 field descriptions (continued) Field 19 BANK1_PIN19 18 BANK1_PIN18 17 BANK1_PIN17 16 BANK1_PIN16 15 BANK1_PIN15 14 BANK1_PIN14 13 BANK1_PIN13 12 BANK1_PIN12 11 BANK1_PIN11 10 BANK1_PIN10 9 BANK1_PIN09 8 BANK1_PIN08 7 BANK1_PIN07 6 BANK1_PIN06 5 BANK1_PIN05 4 BANK1_PIN04 3 BANK1_PIN03 2 BANK1_PIN02 1 BANK1_PIN01 Description Set this bit to one to disable the internal keeper on pin 112, LCD_D19. Set this bit to one to disable the internal keeper on pin 118, LCD_D18. Set this bit to one to disable the internal keeper on pin 105, LCD_D17. Set this bit to one to disable the internal keeper on pin 104, LCD_D16. Set this bit to one to disable the internal keeper on pin 114, LCD_D15. Set this bit to one to disable the internal keeper on pin 106, LCD_D14. Set this bit to one to disable the internal keeper on pin 102, LCD_D13. Set this bit to one to disable the internal keeper on pin 87, LCD_D12. Set this bit to one to disable the internal keeper on pin 95, LCD_D11. Set this bit to one to disable the internal keeper on pin 85, LCD_D10. Set this bit to one to disable the internal keeper on pin 99, LCD_D09. Set this bit to one to disable the internal keeper on pin 93, LCD_D08. Set this bit to one to disable the internal keeper on pin 75, LCD_D07. Set this bit to one to disable the internal keeper on pin 91, LCD_D06. Set this bit to one to disable the internal keeper on pin 89, LCD_D05. Set this bit to one to disable the internal keeper on pin 79, LCD_D04. Set this bit to one to disable the internal keeper on pin 77, LCD_D03. Set this bit to one to disable the internal keeper on pin 67, LCD_D02. Set this bit to one to disable the internal keeper on pin 69, LCD_D01. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 825 Pin Control Memory Map/Register Definition HW_PINCTRL_PULL1 field descriptions (continued) Field Description 0 BANK1_PIN00 Set this bit to one to disable the internal keeper on pin 63, LCD_D00. 9.4.38 PINCTRL Bank 2 Pull Up Resistor Enable Register (HW_PINCTRL_PULL2) The PINCTRL Bank 2 PULL Register enables/disables the internal pull up resistors for those pins in bank 2 which support this operation. HW_PINCTRL_PULL2: 0x620 HW_PINCTRL_PULL2_SET: 0x624 HW_PINCTRL_PULL2_CLR: 0x628 HW_PINCTRL_PULL2_TOG: 0x62C The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. 0 0 0 0 0 0 0 23 22 RSRVD1 0 0 21 20 19 18 17 16 BANK2_PIN16 0 24 BANK2_PIN17 Reset 25 BANK2_PIN18 W 26 BANK2_PIN19 RSRVD2 R 27 BANK2_PIN20 28 BANK2_PIN24 29 BANK2_PIN25 30 BANK2_PIN26 31 BANK2_PIN27 Bit BANK2_PIN21 Address: 8001_8000h base + 620h offset = 8001_8620h 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 826 Freescale Semiconductor, Inc. 7 6 5 4 3 2 1 0 BANK2_PIN05 BANK2_PIN04 BANK2_PIN03 BANK2_PIN02 BANK2_PIN01 BANK2_PIN00 0 8 BANK2_PIN06 0 9 BANK2_PIN07 0 10 BANK2_PIN08 BANK2_PIN12 0 11 BANK2_PIN09 12 BANK2_PIN10 13 RSRVD0 14 BANK2_PIN13 R 15 BANK2_PIN14 Bit BANK2_PIN15 Chapter 9 Pin Control and GPIO (PinCtrl) 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 HW_PINCTRL_PULL2 field descriptions Field 31-28 RSRVD2 27 BANK2_PIN27 26 BANK2_PIN26 25 BANK2_PIN25 24 BANK2_PIN24 23-22 RSRVD1 21 BANK2_PIN21 20 BANK2_PIN20 19 BANK2_PIN19 18 BANK2_PIN18 17 BANK2_PIN17 16 BANK2_PIN16 Description Always write zeroes to this field. Set this bit to one to enable the internal pullup on pin 15, SSP3_SS0. Set this bit to one to enable the internal pullup on pin 3, SSP3_MISO. Set this bit to one to enable the internal pullup on pin 9, SSP3_MOSI. Set this bit to one to disable the internal keeper on pin 286, SSP3_SCK. Always write zeroes to this field. Set this bit to one to enable the internal pullup on pin 18, SSP2_SS2. Set this bit to one to enable the internal pullup on pin 7, SSP2_SS1. Set this bit to one to enable the internal pullup on pin 4, SSP2_SS0. Set this bit to one to enable the internal pullup on pin 288, SSP2_MISO. Set this bit to one to enable the internal pullup on pin 1, SSP2_MOSI. Set this bit to one to disable the internal keeper on pin 280, SSP2_SCK. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 827 Pin Control Memory Map/Register Definition HW_PINCTRL_PULL2 field descriptions (continued) Field 15 BANK2_PIN15 14 BANK2_PIN14 13 BANK2_PIN13 12 BANK2_PIN12 11 RSRVD0 10 BANK2_PIN10 9 BANK2_PIN09 8 BANK2_PIN08 7 BANK2_PIN07 6 BANK2_PIN06 5 BANK2_PIN05 4 BANK2_PIN04 3 BANK2_PIN03 2 BANK2_PIN02 1 BANK2_PIN01 0 BANK2_PIN00 Description Set this bit to one to enable the internal pullup on pin 23, SSP1_DATA3. Set this bit to one to enable the internal pullup on pin 21, SSP1_DATA0. Set this bit to one to enable the internal pullup on pin 17, SSP1_CMD. Set this bit to one to enable the internal pullup on pin 11, SSP1_SCK. Always write zeroes to this field. Set this bit to one to disable the internal keeper on pin 268, SSP0_SCK. Set this bit to one to enable the internal pullup on pin 275, SSP0_DETECT. Set this bit to one to enable the internal pullup on pin 276, SSP0_CMD. Set this bit to one to enable the internal pullup on pin 282, SSP0_DATA7. Set this bit to one to enable the internal pullup on pin 6, SSP0_DATA6. Set this bit to one to enable the internal pullup on pin 284, SSP0_DATA5. Set this bit to one to enable the internal pullup on pin 278, SSP0_DATA4. Set this bit to one to enable the internal pullup on pin 274, SSP0_DATA3. Set this bit to one to enable the internal pullup on pin 2, SSP0_DATA2. Set this bit to one to enable the internal pullup on pin 289, SSP0_DATA1. Set this bit to one to enable the internal pullup on pin 270, SSP0_DATA0. 9.4.39 PINCTRL Bank 3 Pull Up Resistor Enable Register (HW_PINCTRL_PULL3) The PINCTRL Bank 3 PULL Register enables/disables the internal pull up resistors for those pins in bank 3 which support this operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 828 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_PULL3: 0x630 HW_PINCTRL_PULL3_SET: 0x634 HW_PINCTRL_PULL3_CLR: 0x638 HW_PINCTRL_PULL3_TOG: 0x63C The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. Address: 8001_8000h base + 630h offset = 8001_8630h BANK3_PIN23 BANK3_PIN22 BANK3_PIN21 BANK3_PIN20 BANK3_PIN18 BANK3_PIN17 BANK3_PIN16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK3_PIN06 BANK3_PIN05 BANK3_PIN04 BANK3_PIN03 BANK3_PIN02 BANK3_PIN01 BANK3_PIN00 16 BANK3_PIN07 17 BANK3_PIN24 18 BANK3_PIN08 RSRVD0 19 BANK3_PIN25 20 BANK3_PIN09 21 BANK3_PIN26 22 BANK3_PIN10 23 BANK3_PIN27 24 BANK3_PIN11 25 BANK3_PIN28 26 BANK3_PIN12 27 BANK3_PIN29 28 BANK3_PIN13 29 BANK3_PIN30 30 BANK3_PIN14 R RSRVD1 31 BANK3_PIN15 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Bit R W Reset HW_PINCTRL_PULL3 field descriptions Field 31 RSRVD1 30 BANK3_PIN30 Description Always write zeroes to this field. Set this bit to one to disable the internal keeper on pin 101, LCD_RESET. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 829 Pin Control Memory Map/Register Definition HW_PINCTRL_PULL3 field descriptions (continued) Field 29 BANK3_PIN29 28 BANK3_PIN28 27 BANK3_PIN27 26 BANK3_PIN26 25 BANK3_PIN25 24 BANK3_PIN24 23 BANK3_PIN23 22 BANK3_PIN22 21 BANK3_PIN21 20 BANK3_PIN20 19 RSRVD0 18 BANK3_PIN18 17 BANK3_PIN17 16 BANK3_PIN16 15 BANK3_PIN15 14 BANK3_PIN14 13 BANK3_PIN13 12 BANK3_PIN12 11 BANK3_PIN11 Description Set this bit to one to disable the internal keeper on pin 279, PWM4. Set this bit to one to disable the internal keeper on pin 287, PWM3. Set this bit to one to disable the internal keeper on pin 285, SPDIF. Set this bit to one to disable the internal keeper on pin 8, SAIF1_SDATA0. Set this bit to one to disable the internal keeper on pin 281, I2C0_SDA. Set this bit to one to disable the internal keeper on pin 272, I2C0_SCL. Set this bit to one to disable the internal keeper on pin 12, SAIF0_SDATA0. Set this bit to one to disable the internal keeper on pin 16, SAIF0_BITCLK. Set this bit to one to disable the internal keeper on pin 34, SAIF0_LRCLK. Set this bit to one to disable the internal keeper on pin 28, SAIF0_MCLK. Always write zeroes to this field. Set this bit to one to enable the internal pullup on pin 68, PWM2. Set this bit to one to disable the internal keeper on pin 84, PWM1. Set this bit to one to disable the internal keeper on pin 72, PWM0. Set this bit to one to disable the internal keeper on pin 82, AUART3_RTS. Set this bit to one to disable the internal keeper on pin 90, AUART3_CTS. Set this bit to one to disable the internal keeper on pin 86, AUART3_TX. Set this bit to one to disable the internal keeper on pin 98, AUART3_RX. Set this bit to one to disable the internal keeper on pin 56, AUART2_RTS. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 830 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_PULL3 field descriptions (continued) Field 10 BANK3_PIN10 9 BANK3_PIN09 8 BANK3_PIN08 7 BANK3_PIN07 6 BANK3_PIN06 5 BANK3_PIN05 4 BANK3_PIN04 3 BANK3_PIN03 2 BANK3_PIN02 1 BANK3_PIN01 0 BANK3_PIN00 Description Set this bit to one to disable the internal keeper on pin 50, AUART2_CTS. Set this bit to one to enable the internal pullup on pin 26, AUART2_TX. Set this bit to one to enable the internal pullup on pin 22, AUART2_RX. Set this bit to one to enable the internal pullup on pin 74, AUART1_RTS. Set this bit to one to enable the internal pullup on pin 78, AUART1_CTS. Set this bit to one to disable the internal keeper on pin 65, AUART1_TX. Set this bit to one to disable the internal keeper on pin 81, AUART1_RX. Set this bit to one to disable the internal keeper on pin 66, AUART0_RTS. Set this bit to one to disable the internal keeper on pin 70, AUART0_CTS. Set this bit to one to disable the internal keeper on pin 38, AUART0_TX. Set this bit to one to disable the internal keeper on pin 30, AUART0_RX. 9.4.40 PINCTRL Bank 4 Pull Up Resistor Enable Register (HW_PINCTRL_PULL4) The PINCTRL Bank 4 PULL Register enables/disables the internal pull up resistors for those pins in bank 4 which support this operation. HW_PINCTRL_PULL4: 0x640 HW_PINCTRL_PULL4_SET: 0x644 HW_PINCTRL_PULL4_CLR: 0x648 HW_PINCTRL_PULL4_TOG: 0x64C The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 831 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 640h offset = 8001_8640h 30 29 28 27 26 25 24 23 22 21 RSRVD1 R 18 17 RSRVD0 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK4_PIN14 BANK4_PIN13 BANK4_PIN12 BANK4_PIN11 BANK4_PIN10 BANK4_PIN09 BANK4_PIN08 BANK4_PIN07 BANK4_PIN06 BANK4_PIN05 BANK4_PIN04 BANK4_PIN03 BANK4_PIN02 BANK4_PIN01 BANK4_PIN00 Bit 19 BANK4_PIN15 W Reset 20 BANK4_PIN16 31 BANK4_PIN20 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W Reset HW_PINCTRL_PULL4 field descriptions Field 31-21 RSRVD1 20 BANK4_PIN20 19-17 RSRVD0 16 BANK4_PIN16 15 BANK4_PIN15 14 BANK4_PIN14 13 BANK4_PIN13 12 BANK4_PIN12 Description Always write zeroes to this field. Set this bit to one to disable the internal keeper on pin 230, JTAG_RTCK. Always write zeroes to this field. Set this bit to one to disable the internal keeper on pin 19, ENET_CLK. Set this bit to one to disable the internal keeper on pin 61, ENET0_CRS. Set this bit to one to disable the internal keeper on pin 57, ENET0_COL. Set this bit to one to disable the internal keeper on pin 31, ENET0_RX_CLK. Set this bit to one to disable the internal keeper on pin 41, ENET0_TXD3. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 832 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_PULL4 field descriptions (continued) Field 11 BANK4_PIN11 10 BANK4_PIN10 9 BANK4_PIN09 8 BANK4_PIN08 7 BANK4_PIN07 6 BANK4_PIN06 5 BANK4_PIN05 4 BANK4_PIN04 3 BANK4_PIN03 2 BANK4_PIN02 1 BANK4_PIN01 0 BANK4_PIN00 Description Set this bit to one to disable the internal keeper on pin 43, ENET0_TXD2. Set this bit to one to disable the internal keeper on pin 53, ENET0_RXD3. Set this bit to one to disable the internal keeper on pin 51, ENET0_RXD2. Set this bit to one to enable the internal pullup on pin 35, ENET0_TXD1. Set this bit to one to enable the internal pullup on pin 37, ENET0_TXD0. Set this bit to one to enable the internal pullup on pin 29, ENET0_TX_EN. Set this bit to one to disable the internal keeper on pin 13, ENET0_TX_CLK. Set this bit to one to enable the internal pullup on pin 47, ENET0_RXD1. Set this bit to one to enable the internal pullup on pin 45, ENET0_RXD0. Set this bit to one to enable the internal pullup on pin 27, ENET0_RX_EN. Set this bit to one to enable the internal pullup on pin 39, ENET0_MDIO. Set this bit to one to enable the internal pullup on pin 54, ENET0_MDC. 9.4.41 PINCTRL Bank 5 Pad Keeper Disable Register (HW_PINCTRL_PULL5) The PINCTRL Bank 5 PULL Register enables/disables the pad keepers for those pins in bank 5 which support this operation. HW_PINCTRL_PULL5: 0x650 HW_PINCTRL_PULL5_SET: 0x654 HW_PINCTRL_PULL5_CLR: 0x658 HW_PINCTRL_PULL5_TOG: 0x65C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 833 Pin Control Memory Map/Register Definition The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. Address: 8001_8000h base + 650h offset = 8001_8650h 31 30 29 28 27 RSRVD1 BANK5_PIN23 BANK5_PIN22 BANK5_PIN21 BANK5_PIN20 BANK5_PIN19 BANK5_PIN18 BANK5_PIN17 BANK5_PIN16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK5_PIN06 BANK5_PIN05 BANK5_PIN04 BANK5_PIN03 BANK5_PIN02 BANK5_PIN01 BANK5_PIN00 16 BANK5_PIN07 17 BANK5_PIN08 18 BANK5_PIN09 19 BANK5_PIN10 20 BANK5_PIN11 21 BANK5_PIN12 22 BANK5_PIN13 RSRVD0 23 BANK5_PIN14 Bit 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 25 BANK5_PIN15 R 26 BANK5_PIN26 Bit R W Reset HW_PINCTRL_PULL5 field descriptions Field 31-27 RSRVD1 26 BANK5_PIN26 25-24 RSRVD0 23 BANK5_PIN23 22 BANK5_PIN22 21 BANK5_PIN21 20 BANK5_PIN20 Description Always write zeroes to this field. Set this bit to one to disable the internal keeper on pin 196, EMI_DDR_OPEN. Always write zeroes to this field. Set this bit to one to disable the internal keeper on pin 204, EMI_DQS1. Set this bit to one to disable the internal keeper on pin 202, EMI_DQS0. Set this bit to one to disable the internal keeper on pin 200, EMI_CLK. Set this bit to one to disable the internal keeper on pin 195, EMI_DDR_OPEN_FB. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 834 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_PULL5 field descriptions (continued) Field 19 BANK5_PIN19 18 BANK5_PIN18 17 BANK5_PIN17 16 BANK5_PIN16 15 BANK5_PIN15 14 BANK5_PIN14 13 BANK5_PIN13 12 BANK5_PIN12 11 BANK5_PIN11 10 BANK5_PIN10 9 BANK5_PIN09 8 BANK5_PIN08 7 BANK5_PIN07 6 BANK5_PIN06 5 BANK5_PIN05 4 BANK5_PIN04 3 BANK5_PIN03 2 BANK5_PIN02 1 BANK5_PIN01 Description Set this bit to one to disable the internal keeper on pin 222, EMI_DQM1. Set this bit to one to disable the internal keeper on pin 171, EMI_ODT1. Set this bit to one to disable the internal keeper on pin 183, EMI_DQM0. Set this bit to one to disable the internal keeper on pin 173, EMI_ODT0. Set this bit to one to disable the internal keeper on pin 218, EMI_D15. Set this bit to one to disable the internal keeper on pin 223, EMI_D14. Set this bit to one to disable the internal keeper on pin 208, EMI_D13. Set this bit to one to disable the internal keeper on pin 213, EMI_D12. Set this bit to one to disable the internal keeper on pin 207, EMI_D11. Set this bit to one to disable the internal keeper on pin 217, EMI_D10. Set this bit to one to disable the internal keeper on pin 212, EMI_D09. Set this bit to one to disable the internal keeper on pin 216, EMI_D08. Set this bit to one to disable the internal keeper on pin 193, EMI_D07. Set this bit to one to disable the internal keeper on pin 189, EMI_D06. Set this bit to one to disable the internal keeper on pin 182, EMI_D05. Set this bit to one to disable the internal keeper on pin 180, EMI_D04. Set this bit to one to disable the internal keeper on pin 184, EMI_D03. Set this bit to one to disable the internal keeper on pin 177, EMI_D02. Set this bit to one to disable the internal keeper on pin 188, EMI_D01. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 835 Pin Control Memory Map/Register Definition HW_PINCTRL_PULL5 field descriptions (continued) Field Description 0 BANK5_PIN00 Set this bit to one to disable the internal keeper on pin 185, EMI_D00. 9.4.42 PINCTRL Bank 6 Pad Keeper Disable Register (HW_PINCTRL_PULL6) The PINCTRL Bank 6 PULL Register enables/disables the pad keepers for those pins in bank 6 which support this operation. HW_PINCTRL_PULL6: 0x660 HW_PINCTRL_PULL6_SET: 0x664 HW_PINCTRL_PULL6_CLR: 0x668 HW_PINCTRL_PULL6_TOG: 0x66C The Pull register enables/disables integrated on-chip pull up resistors or pad keepers for the pins. 0 0 0 RSRVD1 R W Reset 0 0 0 0 24 23 22 21 20 19 18 17 16 BANK6_PIN16 25 BANK6_PIN17 26 BANK6_PIN18 27 BANK6_PIN19 28 BANK6_PIN20 29 BANK6_PIN21 30 BANK6_PIN22 31 BANK6_PIN23 Bit BANK6_PIN24 Address: 8001_8000h base + 660h offset = 8001_8660h 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 836 Freescale Semiconductor, Inc. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BANK6_PIN13 BANK6_PIN12 BANK6_PIN11 BANK6_PIN10 BANK6_PIN09 BANK6_PIN08 BANK6_PIN07 BANK6_PIN06 BANK6_PIN05 BANK6_PIN04 BANK6_PIN03 BANK6_PIN02 BANK6_PIN01 BANK6_PIN00 R RSRVD0 15 Bit BANK6_PIN14 Chapter 9 Pin Control and GPIO (PinCtrl) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 HW_PINCTRL_PULL6 field descriptions Field 31-25 RSRVD1 24 BANK6_PIN24 23 BANK6_PIN23 22 BANK6_PIN22 21 BANK6_PIN21 20 BANK6_PIN20 19 BANK6_PIN19 18 BANK6_PIN18 17 BANK6_PIN17 16 BANK6_PIN16 15 RSRVD0 14 BANK6_PIN14 Description Always write zeroes to this field. Set this bit to one to disable the internal keeper on pin 166, EMI_CKE. Set this bit to one to disable the internal keeper on pin 139, EMI_CE1N. Set this bit to one to disable the internal keeper on pin 151, EMI_CE0N. Set this bit to one to disable the internal keeper on pin 176, EMI_WEN. Set this bit to one to disable the internal keeper on pin 167, EMI_RASN. Set this bit to one to disable the internal keeper on pin 172, EMI_CASN. Set this bit to one to disable the internal keeper on pin 165, EMI_BA2. Set this bit to one to disable the internal keeper on pin 160, EMI_BA1. Set this bit to one to disable the internal keeper on pin 157, EMI_BA0. Always write zeroes to this field. Set this bit to one to disable the internal keeper on pin 147, EMI_A14. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 837 Pin Control Memory Map/Register Definition HW_PINCTRL_PULL6 field descriptions (continued) Field 13 BANK6_PIN13 12 BANK6_PIN12 11 BANK6_PIN11 10 BANK6_PIN10 9 BANK6_PIN09 8 BANK6_PIN08 7 BANK6_PIN07 6 BANK6_PIN06 5 BANK6_PIN05 4 BANK6_PIN04 3 BANK6_PIN03 2 BANK6_PIN02 1 BANK6_PIN01 0 BANK6_PIN00 Description Set this bit to one to disable the internal keeper on pin 142, EMI_A13. Set this bit to one to disable the internal keeper on pin 150, EMI_A12. Set this bit to one to disable the internal keeper on pin 146, EMI_A11. Set this bit to one to disable the internal keeper on pin 162, EMI_A10. Set this bit to one to disable the internal keeper on pin 143, EMI_A09. Set this bit to one to disable the internal keeper on pin 140, EMI_A08. Set this bit to one to disable the internal keeper on pin 153, EMI_A07. Set this bit to one to disable the internal keeper on pin 138, EMI_A06. Set this bit to one to disable the internal keeper on pin 154, EMI_A05. Set this bit to one to disable the internal keeper on pin 144, EMI_A04. Set this bit to one to disable the internal keeper on pin 152, EMI_A03. Set this bit to one to disable the internal keeper on pin 164, EMI_A02. Set this bit to one to disable the internal keeper on pin 158, EMI_A01. Set this bit to one to disable the internal keeper on pin 170, EMI_A00. 9.4.43 PINCTRL Bank 0 Data Output Register (HW_PINCTRL_DOUT0) The Bank 0 Data Output register provides data for all pins in bank 0 that are configured for GPIO output mode. HW_PINCTRL_DOUT0: 0x700 HW_PINCTRL_DOUT0_SET: 0x704 HW_PINCTRL_DOUT0_CLR: 0x708 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 838 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DOUT0_TOG: 0x70C This register contains the data that will be driven out all bank 0 pins which are configured for GPIO output mode. For example, if HW_PINCTRL_MUXSEL0 contains 0x0000000F and HW_PINCTRL_DOE0 contains 0x00000001, then GPIO0[0] will be driven with the value from bit 0 of this register, GPIO0[1] will not be driven, and GPIO0[2:15] will be controlled by the associated primary interfaces. Address: 8001_8000h base + 700h offset = 8001_8700h Bit R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSRVD1 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT W Reset 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DOUT0 field descriptions Field Description 31-29 RSRVD1 Empty Description. DOUT This field selects the output value (0 or 1) for pins configured as GPIO outputs. Each bit in this register corresponds to one of the 29 pins in bank 0. 9.4.44 PINCTRL Bank 1 Data Output Register (HW_PINCTRL_DOUT1) The Bank 1 Data Output register provides data for all pins in bank 1 that are configured for GPIO output mode. HW_PINCTRL_DOUT1: 0x710 HW_PINCTRL_DOUT1_SET: 0x714 HW_PINCTRL_DOUT1_CLR: 0x718 HW_PINCTRL_DOUT1_TOG: 0x71C This register contains the data that will be driven out all bank 0 pins which are configured for GPIO output mode. For example, if HW_PINCTRL_MUXSEL0 contains 0x0000000F and HW_PINCTRL_DOE0 contains 0x00000001, then GPIO0[0] will be driven with the value from bit 0 of this register, GPIO0[1] will not be driven, and GPIO0[2:15] will be controlled by the associated primary interfaces. Address: 8001_8000h base + 710h offset = 8001_8710h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 839 Pin Control Memory Map/Register Definition HW_PINCTRL_DOUT1 field descriptions Field Description DOUT This field selects the output value (0 or 1) for pins configured as GPIO outputs. Each bit in this register corresponds to one of the 32 pins in bank 1. 9.4.45 PINCTRL Bank 2 Data Output Register (HW_PINCTRL_DOUT2) The Bank 2 Data Output register provides data for all pins in bank 2 that are configured for GPIO output mode. HW_PINCTRL_DOUT2: 0x720 HW_PINCTRL_DOUT2_SET: 0x724 HW_PINCTRL_DOUT2_CLR: 0x728 HW_PINCTRL_DOUT2_TOG: 0x72C This register contains the data that will be driven out all bank 0 pins which are configured for GPIO output mode. For example, if HW_PINCTRL_MUXSEL0 contains 0x0000000F and HW_PINCTRL_DOE0 contains 0x00000001, then GPIO0[0] will be driven with the value from bit 0 of this register, GPIO0[1] will not be driven, and GPIO0[2:15] will be controlled by the associated primary interfaces. Address: 8001_8000h base + 720h offset = 8001_8720h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSRVD1 R 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT W Reset 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DOUT2 field descriptions Field 31-28 RSRVD1 DOUT Description Empty Description. This field selects the output value (0 or 1) for pins configured as GPIO outputs. Each bit in this register corresponds to one of the 28 pins in bank 2. 9.4.46 PINCTRL Bank 3 Data Output Register (HW_PINCTRL_DOUT3) The Bank 3 Data Output register provides data for all pins in bank 3 that are configured for GPIO output mode. HW_PINCTRL_DOUT3: 0x730 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 840 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_DOUT3_SET: 0x734 HW_PINCTRL_DOUT3_CLR: 0x738 HW_PINCTRL_DOUT3_TOG: 0x73C This register contains the data that will be driven out all bank 0 pins which are configured for GPIO output mode. For example, if HW_PINCTRL_MUXSEL0 contains 0x0000000F and HW_PINCTRL_DOE0 contains 0x00000001, then GPIO0[0] will be driven with the value from bit 0 of this register, GPIO0[1] will not be driven, and GPIO0[2:15] will be controlled by the associated primary interfaces. Address: 8001_8000h base + 730h offset = 8001_8730h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 Bit DOUT W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R DOUT W Reset 0 0 0 0 0 0 0 0 HW_PINCTRL_DOUT3 field descriptions Field 31 RSRVD1 DOUT Description Empty Description. This field selects the output value (0 or 1) for pins configured as GPIO outputs. Each bit in this register corresponds to one of the 31 pins in bank 3. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 841 Pin Control Memory Map/Register Definition 9.4.47 PINCTRL Bank 4 Data Output Register (HW_PINCTRL_DOUT4) The Bank 4 Data Output register provides data for all pins in bank 4 that are configured for GPIO output mode. HW_PINCTRL_DOUT4: 0x740 HW_PINCTRL_DOUT4_SET: 0x744 HW_PINCTRL_DOUT4_CLR: 0x748 HW_PINCTRL_DOUT4_TOG: 0x74C This register contains the data that will be driven out all bank 0 pins which are configured for GPIO output mode. For example, if HW_PINCTRL_MUXSEL0 contains 0x0000000F and HW_PINCTRL_DOE0 contains 0x00000001, then GPIO0[0] will be driven with the value from bit 0 of this register, GPIO0[1] will not be driven, and GPIO0[2:15] will be controlled by the associated primary interfaces. Address: 8001_8000h base + 740h offset = 8001_8740h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD1 R 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 DOUT W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DOUT4 field descriptions Field 31-21 RSRVD1 DOUT Description Empty Description. This field selects the output value (0 or 1) for pins configured as GPIO outputs. Each bit in this register corresponds to one of the 21 pins in bank 4. 9.4.48 PINCTRL Bank 0 Data Input Register (HW_PINCTRL_DIN0) The current value of all bank 0 pins may be read from the PINCTRL Bank 0 Data Input Register. HW_PINCTRL_DIN0: 0x900 HW_PINCTRL_DIN0_SET: 0x904 HW_PINCTRL_DIN0_CLR: 0x908 HW_PINCTRL_DIN0_TOG: 0x90C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 842 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) This register reflects the current values of all the bank 0 pins. The register accurately reflects the state of the pin regardless of the setting of the HW_PINCTRL_MUXSELx or HW_PINCTRL_DOEx registers, but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the HW_PINCTRL_MUXSELx register should be set to 3 (GPIO mode) and the pin's bit in the HW_PINCTRL_DOEx register should be set to 0 (disabled) to insure that the chip is not driving the pin. Address: 8001_8000h base + 900h offset = 8001_8900h Bit R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSRVD1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DIN0 field descriptions Field 31-29 RSRVD1 DIN Description Empty Description. Each bit in this read-only register corresponds to one of the 29 pins in bank 0. The current state of each pin in bank 0, synchronized to HCLK, may be read here. 9.4.49 PINCTRL Bank 1 Data Input Register (HW_PINCTRL_DIN1) The current value of all bank 1 pins may be read from the PINCTRL Bank 1 Data Input Register. HW_PINCTRL_DIN1: 0x910 HW_PINCTRL_DIN1_SET: 0x914 HW_PINCTRL_DIN1_CLR: 0x918 HW_PINCTRL_DIN1_TOG: 0x91C This register reflects the current values of all the bank 1 pins. The register accurately reflects the state of the pin regardless of the setting of the HW_PINCTRL_MUXSELx or HW_PINCTRL_DOEx registers, but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the HW_PINCTRL_MUXSELx register should be set to 3 (GPIO mode) and the pin's bit in the HW_PINCTRL_DOEx register should be set to 0 (disabled) to insure that the chip is not driving the pin. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 843 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 910h offset = 8001_8910h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIN R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DIN1 field descriptions Field Description DIN Each bit in this read-only register corresponds to one of the 32 pins in bank 1. The current state of each pin in bank 1, synchronized to HCLK, may be read here. 9.4.50 PINCTRL Bank 2 Data Input Register (HW_PINCTRL_DIN2) The current value of all bank 2 pins may be read from the PINCTRL Bank 2 Data Input Register. HW_PINCTRL_DIN2: 0x920 HW_PINCTRL_DIN2_SET: 0x924 HW_PINCTRL_DIN2_CLR: 0x928 HW_PINCTRL_DIN2_TOG: 0x92C This register reflects the current values of all the bank 2 pins. The register accurately reflects the state of the pin regardless of the setting of the HW_PINCTRL_MUXSELx or HW_PINCTRL_DOEx registers, but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the HW_PINCTRL_MUXSELx register should be set to 3 (GPIO mode) and the pin's bit in the HW_PINCTRL_DOEx register should be set to 0 (disabled) to insure that the chip is not driving the pin. Address: 8001_8000h base + 920h offset = 8001_8920h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSRVD1 R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DIN2 field descriptions Field 31-28 RSRVD1 DIN Description Empty Description. Each bit in this read-only register corresponds to one of the 28 pins in bank 2. The current state of each pin in bank 2, synchronized to HCLK, may be read here. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 844 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 9.4.51 PINCTRL Bank 3 Data Input Register (HW_PINCTRL_DIN3) The current value of all bank 3 pins may be read from the PINCTRL Bank 3 Data Input Register. HW_PINCTRL_DIN3: 0x930 HW_PINCTRL_DIN3_SET: 0x934 HW_PINCTRL_DIN3_CLR: 0x938 HW_PINCTRL_DIN3_TOG: 0x93C This register reflects the current values of all the bank 3 pins. The register accurately reflects the state of the pin regardless of the setting of the HW_PINCTRL_MUXSELx or HW_PINCTRL_DOEx registers, but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the HW_PINCTRL_MUXSELx register should be set to 3 (GPIO mode) and the pin's bit in the HW_PINCTRL_DOEx register should be set to 0 (disabled) to insure that the chip is not driving the pin. Address: 8001_8000h base + 930h offset = 8001_8930h 31 R 30 29 28 27 26 25 24 RSRVD1 Bit 23 22 21 20 19 18 17 16 DIN W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 DIN R W Reset 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 845 Pin Control Memory Map/Register Definition HW_PINCTRL_DIN3 field descriptions Field Description 31 RSRVD1 Empty Description. DIN Each bit in this read-only register corresponds to one of the 31 pins in bank 3. The current state of each pin in bank 3, synchronized to HCLK, may be read here. 9.4.52 PINCTRL Bank 4 Data Input Register (HW_PINCTRL_DIN4) The current value of all bank 4 pins may be read from the PINCTRL Bank 4 Data Input Register. HW_PINCTRL_DIN4: 0x940 HW_PINCTRL_DIN4_SET: 0x944 HW_PINCTRL_DIN4_CLR: 0x948 HW_PINCTRL_DIN4_TOG: 0x94C This register reflects the current values of all the bank 4 pins. The register accurately reflects the state of the pin regardless of the setting of the HW_PINCTRL_MUXSELx or HW_PINCTRL_DOEx registers, but generally, if it is desired to use a pin as a general purpose input, the pin's two bits in the HW_PINCTRL_MUXSELx register should be set to 3 (GPIO mode) and the pin's bit in the HW_PINCTRL_DOEx register should be set to 0 (disabled) to insure that the chip is not driving the pin. Address: 8001_8000h base + 940h offset = 8001_8940h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD1 R 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 DIN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DIN4 field descriptions Field 31-21 RSRVD1 DIN Description Empty Description. Each bit in this read-only register corresponds to one of the 21 pins in bank 4. The current state of each pin in bank 4, synchronized to HCLK, may be read here. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 846 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 9.4.53 PINCTRL Bank 0 Data Output Enable Register (HW_PINCTRL_DOE0) The PINCTRL Bank 0 Output Enable Register controls the output enable signal for all pins in bank 0 that are configured for GPIO mode. HW_PINCTRL_DOE0: 0xb00 HW_PINCTRL_DOE0_SET: 0xb04 HW_PINCTRL_DOE0_CLR: 0xb08 HW_PINCTRL_DOE0_TOG: 0xb0C For pins in bank 0 that are configured as GPIOs, a 1 in this register will enable the corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin, and a 0 in this register will disable the corresponding driver. Address: 8001_8000h base + B00h offset = 8001_8B00h Bit R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSRVD1 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOE W Reset 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DOE0 field descriptions Field 31-29 RSRVD1 DOE Description Empty Description. Each bit in this register corresponds to one of the 29 pins in bank 0. Setting a bit in this register to one allows the chip to drive the corresponding pin in GPIO mode. 9.4.54 PINCTRL Bank 1 Data Output Enable Register (HW_PINCTRL_DOE1) The PINCTRL Bank 1 Output Enable Register controls the output enable signal for all pins in bank 1 that are configured for GPIO mode. HW_PINCTRL_DOE1: 0xb10 HW_PINCTRL_DOE1_SET: 0xb14 HW_PINCTRL_DOE1_CLR: 0xb18 HW_PINCTRL_DOE1_TOG: 0xb1C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 847 Pin Control Memory Map/Register Definition For pins in bank 1 that are configured as GPIOs, a 1 in this register will enable the corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin, and a 0 in this register will disable the corresponding driver. Address: 8001_8000h base + B10h offset = 8001_8B10h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DOE1 field descriptions Field Description DOE Each bit in this register corresponds to one of the 32 pins in bank 1. Setting a bit in this register to one allows the chip to drive the corresponding pin in GPIO mode. 9.4.55 PINCTRL Bank 2 Data Output Enable Register (HW_PINCTRL_DOE2) The PINCTRL Bank 2 Output Enable Register controls the output enable signal for all pins in bank 2 that are configured for GPIO mode. HW_PINCTRL_DOE2: 0xb20 HW_PINCTRL_DOE2_SET: 0xb24 HW_PINCTRL_DOE2_CLR: 0xb28 HW_PINCTRL_DOE2_TOG: 0xb2C For pins in bank 2 that are configured as GPIOs, a 1 in this register will enable the corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin, and a 0 in this register will disable the corresponding driver. Address: 8001_8000h base + B20h offset = 8001_8B20h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSRVD1 R 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOE W Reset 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DOE2 field descriptions Field 31-28 RSRVD1 DOE Description Empty Description. Each bit in this register corresponds to one of the 28 pins in bank 2. Setting a bit in this register to one allows the chip to drive the corresponding pin in GPIO mode. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 848 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 9.4.56 PINCTRL Bank 3 Data Output Enable Register (HW_PINCTRL_DOE3) The PINCTRL Bank 3 Output Enable Register controls the output enable signal for all pins in bank 3 that are configured for GPIO mode. HW_PINCTRL_DOE3: 0xb30 HW_PINCTRL_DOE3_SET: 0xb34 HW_PINCTRL_DOE3_CLR: 0xb38 HW_PINCTRL_DOE3_TOG: 0xb3C For pins in bank 3 that are configured as GPIOs, a 1 in this register will enable the corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin, and a 0 in this register will disable the corresponding driver. Address: 8001_8000h base + B30h offset = 8001_8B30h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 Bit DOE W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R DOE W Reset 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 849 Pin Control Memory Map/Register Definition HW_PINCTRL_DOE3 field descriptions Field Description 31 RSRVD1 Empty Description. DOE Each bit in this register corresponds to one of the 31 pins in bank 3. Setting a bit in this register to one allows the chip to drive the corresponding pin in GPIO mode. 9.4.57 PINCTRL Bank 4 Data Output Enable Register (HW_PINCTRL_DOE4) The PINCTRL Bank 4 Output Enable Register controls the output enable signal for all pins in bank 4 that are configured for GPIO mode. HW_PINCTRL_DOE4: 0xb40 HW_PINCTRL_DOE4_SET: 0xb44 HW_PINCTRL_DOE4_CLR: 0xb48 HW_PINCTRL_DOE4_TOG: 0xb4C For pins in bank 4 that are configured as GPIOs, a 1 in this register will enable the corresponding bit value from HW_PINCTRL_DOUTxx register to be driven out the pin, and a 0 in this register will disable the corresponding driver. Address: 8001_8000h base + B40h offset = 8001_8B40h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD1 R 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 DOE W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_DOE4 field descriptions Field 31-21 RSRVD1 DOE Description Empty Description. Each bit in this register corresponds to one of the 21 pins in bank 4. Setting a bit in this register to one allows the chip to drive the corresponding pin in GPIO mode. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 850 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 9.4.58 PINCTRL Bank 0 Interrupt Select Register (HW_PINCTRL_PIN2IRQ0) The Bank 0 Interrupt Select register selects which of the bank 0 pins may be used as interrupt sources. HW_PINCTRL_PIN2IRQ0: 0x1000 HW_PINCTRL_PIN2IRQ0_SET: 0x1004 HW_PINCTRL_PIN2IRQ0_CLR: 0x1008 HW_PINCTRL_PIN2IRQ0_TOG: 0x100C As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register selects which pins in bank 0 can be used to generate interrupts. If the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the HW_PINCTRL_IRQLEVEL0 and HW_PINCTRL_IRQPOL0 registers) will set the corresponding bit in the HW_PINCTRL_IRQSTAT0 register. If the pin is additionally enabled in the HW_PINCTRL_IRQEN0 register, then the interrupt will be propagated to the interrupt collector as interrupt GPIO0. For example, if this register contains 0x00000014, then pins GPIO0[2] and GPIO0[4] can be used as interrupt pins, and no other pins in bank 0 will cause bits to be set in the HW_PINCTRL_IRQSTAT0 register. Address: 8001_8000h base + 1000h offset = 8001_9000h Bit R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN2IRQ W Reset 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_PIN2IRQ0 field descriptions Field Description 31-29 RSRVD1 Empty Description. PIN2IRQ Each bit in this register corresponds to one of the 29 pins in bank 0: 0= Deselect the pin's interrupt functionality. 1= Select the pin to be used as an interrupt source. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 851 Pin Control Memory Map/Register Definition 9.4.59 PINCTRL Bank 1 Interrupt Select Register (HW_PINCTRL_PIN2IRQ1) The Bank 1 Interrupt Select register selects which of the bank 1 pins may be used as interrupt sources. HW_PINCTRL_PIN2IRQ1: 0x1010 HW_PINCTRL_PIN2IRQ1_SET: 0x1014 HW_PINCTRL_PIN2IRQ1_CLR: 0x1018 HW_PINCTRL_PIN2IRQ1_TOG: 0x101C As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register selects which pins in bank 1 can be used to generate interrupts. If the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the HW_PINCTRL_IRQLEVEL1 and HW_PINCTRL_IRQPOL1 registers) will set the corresponding bit in the HW_PINCTRL_IRQSTAT1 register. If the pin is additionally enabled in the HW_PINCTRL_IRQEN0 register, then the interrupt will be propagated to the interrupt collector as interrupt GPIO1. For example, if this register contains 0x00000014, then pins GPIO1[2] and GPIO1[4] can be used as interrupt pins, and no other pins in bank 0 will cause bits to be set in the HW_PINCTRL_IRQSTAT1 register. Address: 8001_8000h base + 1010h offset = 8001_9010h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN2IRQ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_PIN2IRQ1 field descriptions Field PIN2IRQ Description Each bit in this register corresponds to one of the 32 pins in bank 1: 0= Deselect the pin's interrupt functionality. 1= Select the pin to be used as an interrupt source. 9.4.60 PINCTRL Bank 2 Interrupt Select Register (HW_PINCTRL_PIN2IRQ2) The Bank 2 Interrupt Select register selects which of the bank 2 pins may be used as interrupt sources. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 852 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_PIN2IRQ2: 0x1020 HW_PINCTRL_PIN2IRQ2_SET: 0x1024 HW_PINCTRL_PIN2IRQ2_CLR: 0x1028 HW_PINCTRL_PIN2IRQ2_TOG: 0x102C As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register selects which pins in bank 2 can be used to generate interrupts. If the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the HW_PINCTRL_IRQLEVEL2 and HW_PINCTRL_IRQPOL2 registers) will set the corresponding bit in the HW_PINCTRL_IRQSTAT2 register. If the pin is additionally enabled in the HW_PINCTRL_IRQEN0 register, then the interrupt will be propagated to the interrupt collector as interrupt GPIO2. For example, if this register contains 0x00000014, then pins GPIO2[2] and GPIO2[4] can be used as interrupt pins, and no other pins in bank 0 will cause bits to be set in the HW_PINCTRL_IRQSTAT2 register. Address: 8001_8000h base + 1020h offset = 8001_9020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSRVD1 R 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN2IRQ W Reset 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_PIN2IRQ2 field descriptions Field Description 31-28 RSRVD1 Empty Description. PIN2IRQ Each bit in this register corresponds to one of the 28 pins in bank 2: 0= Deselect the pin's interrupt functionality. 1= Select the pin to be used as an interrupt source. 9.4.61 PINCTRL Bank 3 Interrupt Select Register (HW_PINCTRL_PIN2IRQ3) The Bank 3 Interrupt Select register selects which of the bank 3 pins may be used as interrupt sources. HW_PINCTRL_PIN2IRQ3: 0x1030 HW_PINCTRL_PIN2IRQ3_SET: 0x1034 HW_PINCTRL_PIN2IRQ3_CLR: 0x1038 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 853 Pin Control Memory Map/Register Definition HW_PINCTRL_PIN2IRQ3_TOG: 0x103C As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register selects which pins in bank 3 can be used to generate interrupts. If the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the HW_PINCTRL_IRQLEVEL3 and HW_PINCTRL_IRQPOL3 registers) will set the corresponding bit in the HW_PINCTRL_IRQSTAT3 register. If the pin is additionally enabled in the HW_PINCTRL_IRQEN0 register, then the interrupt will be propagated to the interrupt collector as interrupt GPIO3. For example, if this register contains 0x00000014, then pins GPIO3[2] and GPIO3[4] can be used as interrupt pins, and no other pins in bank 0 will cause bits to be set in the HW_PINCTRL_IRQSTAT3 register. Address: 8001_8000h base + 1030h offset = 8001_9030h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 Bit PIN2IRQ W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R PIN2IRQ W Reset 0 0 0 0 0 0 0 0 0 HW_PINCTRL_PIN2IRQ3 field descriptions Field Description 31 RSRVD1 Empty Description. PIN2IRQ Each bit in this register corresponds to one of the 31 pins in bank 3: Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 854 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_PIN2IRQ3 field descriptions (continued) Field Description 0= Deselect the pin's interrupt functionality. 1= Select the pin to be used as an interrupt source. 9.4.62 PINCTRL Bank 4 Interrupt Select Register (HW_PINCTRL_PIN2IRQ4) The Bank 4 Interrupt Select register selects which of the bank 4 pins may be used as interrupt sources. HW_PINCTRL_PIN2IRQ4: 0x1040 HW_PINCTRL_PIN2IRQ4_SET: 0x1044 HW_PINCTRL_PIN2IRQ4_CLR: 0x1048 HW_PINCTRL_PIN2IRQ4_TOG: 0x104C As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register selects which pins in bank 4 can be used to generate interrupts. If the pin is selected in this register by setting its bit to 1, then detection of the correct level or edge on the pin (as chosen by the HW_PINCTRL_IRQLEVEL4 and HW_PINCTRL_IRQPOL4 registers) will set the corresponding bit in the HW_PINCTRL_IRQSTAT4 register. If the pin is additionally enabled in the HW_PINCTRL_IRQEN0 register, then the interrupt will be propagated to the interrupt collector as interrupt GPIO4. For example, if this register contains 0x00000014, then pins GPIO4[2] and GPIO4[4] can be used as interrupt pins, and no other pins in bank 0 will cause bits to be set in the HW_PINCTRL_IRQSTAT4 register. Address: 8001_8000h base + 1040h offset = 8001_9040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 RSRVD1 R 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 PIN2IRQ W Reset 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_PIN2IRQ4 field descriptions Field Description 31-21 RSRVD1 Empty Description. PIN2IRQ Each bit in this register corresponds to one of the 21 pins in bank 4: 0= Deselect the pin's interrupt functionality. 1= Select the pin to be used as an interrupt source. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 855 Pin Control Memory Map/Register Definition 9.4.63 PINCTRL Bank 0 Interrupt Mask Register (HW_PINCTRL_IRQEN0) The PINCTRL Bank 0 Interrupt Mask Register contains interrupt enable masks for the pins in bank 0. HW_PINCTRL_IRQEN0: 0x1100 HW_PINCTRL_IRQEN0_SET: 0x1104 HW_PINCTRL_IRQEN0_CLR: 0x1108 HW_PINCTRL_IRQEN0_TOG: 0x110C As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register masks the interrupt sources from the pins in bank 0. If a bit is set in this register and the same bit is set in HW_PINCTRL_IRQSTAT0, an interrupt will be propagated to the interrupt collector as interrupt GPIO0. For example, if this register contains 0x00000014, then only bits 2 and 4 in HW_PINCTRL_IRQSTAT0 (corresponding to pins GPIO0[2] and GPIO0[4]) will cause interrupts from bank 0. Address: 8001_8000h base + 1100h offset = 8001_9100h Bit R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQEN W Reset 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQEN0 field descriptions Field 31-29 RSRVD1 IRQEN Description Empty Description. Each bit in this register corresponds to one of the 29 pins in bank 0: 1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT0. 0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT0. 9.4.64 PINCTRL Bank 1 Interrupt Mask Register (HW_PINCTRL_IRQEN1) The PINCTRL Bank 1 Interrupt Mask Register contains interrupt enable masks for the pins in bank 1. HW_PINCTRL_IRQEN1: 0x1110 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 856 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_IRQEN1_SET: 0x1114 HW_PINCTRL_IRQEN1_CLR: 0x1118 HW_PINCTRL_IRQEN1_TOG: 0x111C As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register masks the interrupt sources from the pins in bank 1. If a bit is set in this register and the same bit is set in HW_PINCTRL_IRQSTAT1, an interrupt will be propagated to the interrupt collector as interrupt GPIO1. For example, if this register contains 0x00000014, then only bits 2 and 4 in HW_PINCTRL_IRQSTAT1 (corresponding to pins GPIO1[2] and GPIO1[4]) will cause interrupts from bank 1. Address: 8001_8000h base + 1110h offset = 8001_9110h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQEN1 field descriptions Field IRQEN Description Each bit in this register corresponds to one of the 32 pins in bank 1: 1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT1. 0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT1. 9.4.65 PINCTRL Bank 2 Interrupt Mask Register (HW_PINCTRL_IRQEN2) The PINCTRL Bank 2 Interrupt Mask Register contains interrupt enable masks for the pins in bank 2. HW_PINCTRL_IRQEN2: 0x1120 HW_PINCTRL_IRQEN2_SET: 0x1124 HW_PINCTRL_IRQEN2_CLR: 0x1128 HW_PINCTRL_IRQEN2_TOG: 0x112C As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register masks the interrupt sources from the pins in bank 2. If a bit is set in this register and the same bit is set in HW_PINCTRL_IRQSTAT2, an interrupt will be propagated to the interrupt collector as interrupt GPIO2. For example, if this register contains 0x00000014, then only bits 2 and 4 in HW_PINCTRL_IRQSTAT2 (corresponding to pins GPIO2[2] and GPIO2[4]) will cause interrupts from bank 2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 857 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 1120h offset = 8001_9120h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSRVD1 R 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQEN W Reset 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQEN2 field descriptions Field 31-28 RSRVD1 IRQEN Description Empty Description. Each bit in this register corresponds to one of the 28 pins in bank 2: 1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT2. 0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT2. 9.4.66 PINCTRL Bank 3 Interrupt Mask Register (HW_PINCTRL_IRQEN3) The PINCTRL Bank 3 Interrupt Mask Register contains interrupt enable masks for the pins in bank 3. HW_PINCTRL_IRQEN3: 0x1130 HW_PINCTRL_IRQEN3_SET: 0x1134 HW_PINCTRL_IRQEN3_CLR: 0x1138 HW_PINCTRL_IRQEN3_TOG: 0x113C As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register masks the interrupt sources from the pins in bank 3. If a bit is set in this register and the same bit is set in HW_PINCTRL_IRQSTAT3, an interrupt will be propagated to the interrupt collector as interrupt GPIO3. For example, if this register contains 0x00000014, then only bits 2 and 4 in HW_PINCTRL_IRQSTAT3 (corresponding to pins GPIO3[2] and GPIO3[4]) will cause interrupts from bank 3. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 858 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Address: 8001_8000h base + 1130h offset = 8001_9130h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 Bit IRQEN W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R IRQEN W Reset 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQEN3 field descriptions Field 31 RSRVD1 IRQEN Description Empty Description. Each bit in this register corresponds to one of the 31 pins in bank 3: 1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT3. 0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT3. 9.4.67 PINCTRL Bank 4 Interrupt Mask Register (HW_PINCTRL_IRQEN4) The PINCTRL Bank 4 Interrupt Mask Register contains interrupt enable masks for the pins in bank 4. HW_PINCTRL_IRQEN4: 0x1140 HW_PINCTRL_IRQEN4_SET: 0x1144 HW_PINCTRL_IRQEN4_CLR: 0x1148 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 859 Pin Control Memory Map/Register Definition HW_PINCTRL_IRQEN4_TOG: 0x114C As described earlier in this chapter, any digital I/O pin can be used as an interrupt source. This register masks the interrupt sources from the pins in bank 4. If a bit is set in this register and the same bit is set in HW_PINCTRL_IRQSTAT4, an interrupt will be propagated to the interrupt collector as interrupt GPIO4. For example, if this register contains 0x00000014, then only bits 2 and 4 in HW_PINCTRL_IRQSTAT4 (corresponding to pins GPIO4[2] and GPIO4[4]) will cause interrupts from bank 4. Address: 8001_8000h base + 1140h offset = 8001_9140h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 RSRVD1 R 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 IRQEN W Reset 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQEN4 field descriptions Field 31-21 RSRVD1 IRQEN Description Empty Description. Each bit in this register corresponds to one of the 21 pins in bank 4: 1= Enable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT4. 0= Disable interrupts from the corresponding bit in HW_PINCTRL_IRQSTAT4. 9.4.68 PINCTRL Bank 0 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL0) The PINCTRL Bank 0 Interrupt Level/Edge Register selects level or edge sensitivity for interrupt requests for the pins in bank 0. HW_PINCTRL_IRQLEVEL0: 0x1200 HW_PINCTRL_IRQLEVEL0_SET: 0x1204 HW_PINCTRL_IRQLEVEL0_CLR: 0x1208 HW_PINCTRL_IRQLEVEL0_TOG: 0x120C This register selects level or edge detection for interrupt generation. Each pin in bank 0 that is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting bits in this register and HW_PINCTRL_IRQPOL0 (see below) appropriately. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 860 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) Address: 8001_8000h base + 1200h offset = 8001_9200h Bit R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQLEVEL W Reset 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQLEVEL0 field descriptions Field Description 31-29 RSRVD1 Empty Description. IRQLEVEL Each bit in this register corresponds to one of the 29 pins in bank 0: 1= Level detection; 0= Edge detection. 9.4.69 PINCTRL Bank 1 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL1) The PINCTRL Bank 1 Interrupt Level/Edge Register selects level or edge sensitivity for interrupt requests for the pins in bank 1. HW_PINCTRL_IRQLEVEL1: 0x1210 HW_PINCTRL_IRQLEVEL1_SET: 0x1214 HW_PINCTRL_IRQLEVEL1_CLR: 0x1218 HW_PINCTRL_IRQLEVEL1_TOG: 0x121C This register selects level or edge detection for interrupt generation. Each pin in bank 1 that is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting bits in this register and HW_PINCTRL_IRQPOL1 (see below) appropriately. Address: 8001_8000h base + 1210h offset = 8001_9210h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQLEVEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQLEVEL1 field descriptions Field IRQLEVEL Description Each bit in this register corresponds to one of the 32 pins in bank 1: 1= Level detection; 0= Edge detection. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 861 Pin Control Memory Map/Register Definition 9.4.70 PINCTRL Bank 2 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL2) The PINCTRL Bank 2 Interrupt Level/Edge Register selects level or edge sensitivity for interrupt requests for the pins in bank 2. HW_PINCTRL_IRQLEVEL2: 0x1220 HW_PINCTRL_IRQLEVEL2_SET: 0x1224 HW_PINCTRL_IRQLEVEL2_CLR: 0x1228 HW_PINCTRL_IRQLEVEL2_TOG: 0x122C This register selects level or edge detection for interrupt generation. Each pin in bank 2 that is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting bits in this register and HW_PINCTRL_IRQPOL2 (see below) appropriately. Address: 8001_8000h base + 1220h offset = 8001_9220h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQLEVEL W Reset 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQLEVEL2 field descriptions Field 31-28 RSRVD1 IRQLEVEL Description Empty Description. Each bit in this register corresponds to one of the 28 pins in bank 2: 1= Level detection; 0= Edge detection. 9.4.71 PINCTRL Bank 3 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL3) The PINCTRL Bank 3 Interrupt Level/Edge Register selects level or edge sensitivity for interrupt requests for the pins in bank 3. HW_PINCTRL_IRQLEVEL3: 0x1230 HW_PINCTRL_IRQLEVEL3_SET: 0x1234 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 862 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_IRQLEVEL3_CLR: 0x1238 HW_PINCTRL_IRQLEVEL3_TOG: 0x123C This register selects level or edge detection for interrupt generation. Each pin in bank 3 that is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting bits in this register and HW_PINCTRL_IRQPOL3 (see below) appropriately. Address: 8001_8000h base + 1230h offset = 8001_9230h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 Bit IRQLEVEL W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R IRQLEVEL W Reset 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQLEVEL3 field descriptions Field 31 RSRVD1 IRQLEVEL Description Empty Description. Each bit in this register corresponds to one of the 31 pins in bank 3: 1= Level detection; 0= Edge detection. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 863 Pin Control Memory Map/Register Definition 9.4.72 PINCTRL Bank 4 Interrupt Level/Edge Register (HW_PINCTRL_IRQLEVEL4) The PINCTRL Bank 4 Interrupt Level/Edge Register selects level or edge sensitivity for interrupt requests for the pins in bank 4. HW_PINCTRL_IRQLEVEL4: 0x1240 HW_PINCTRL_IRQLEVEL4_SET: 0x1244 HW_PINCTRL_IRQLEVEL4_CLR: 0x1248 HW_PINCTRL_IRQLEVEL4_TOG: 0x124C This register selects level or edge detection for interrupt generation. Each pin in bank 4 that is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting bits in this register and HW_PINCTRL_IRQPOL4 (see below) appropriately. Address: 8001_8000h base + 1240h offset = 8001_9240h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 RSRVD1 R 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 IRQLEVEL W Reset 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQLEVEL4 field descriptions Field 31-21 RSRVD1 IRQLEVEL Description Empty Description. Each bit in this register corresponds to one of the 21 pins in bank 4: 1= Level detection; 0= Edge detection. 9.4.73 PINCTRL Bank 0 Interrupt Polarity Register (HW_PINCTRL_IRQPOL0) The PINCTRL Bank 0 Interrupt Polarity Register selects the polarity for interrupt requests for the pins in bank 0. HW_PINCTRL_IRQPOL0: 0x1300 HW_PINCTRL_IRQPOL0_SET: 0x1304 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 864 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_IRQPOL0_CLR: 0x1308 HW_PINCTRL_IRQPOL0_TOG: 0x130C This register selects the polarity for interrupt generation. Each pin in bank 0 which is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting this register and HW_PINCTRL_IRQLEVEL0 (see above) appropriately. Address: 8001_8000h base + 1300h offset = 8001_9300h Bit R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQPOL W Reset 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQPOL0 field descriptions Field Description 31-29 RSRVD1 Empty Description. IRQPOL Each bit in this register corresponds to one of the 29 pins in bank 0: 0= Low or falling edge; 1= High or rising edge. 9.4.74 PINCTRL Bank 1 Interrupt Polarity Register (HW_PINCTRL_IRQPOL1) The PINCTRL Bank 1 Interrupt Polarity Register selects the polarity for interrupt requests for the pins in bank 1. HW_PINCTRL_IRQPOL1: 0x1310 HW_PINCTRL_IRQPOL1_SET: 0x1314 HW_PINCTRL_IRQPOL1_CLR: 0x1318 HW_PINCTRL_IRQPOL1_TOG: 0x131C This register selects the polarity for interrupt generation. Each pin in bank 1 which is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting this register and HW_PINCTRL_IRQLEVEL1 (see above) appropriately. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 865 Pin Control Memory Map/Register Definition Address: 8001_8000h base + 1310h offset = 8001_9310h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQPOL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQPOL1 field descriptions Field Description IRQPOL Each bit in this register corresponds to one of the 32 pins in bank 1: 0= Low or falling edge; 1= High or rising edge. 9.4.75 PINCTRL Bank 2 Interrupt Polarity Register (HW_PINCTRL_IRQPOL2) The PINCTRL Bank 2 Interrupt Polarity Register selects the polarity for interrupt requests for the pins in bank 2. HW_PINCTRL_IRQPOL2: 0x1320 HW_PINCTRL_IRQPOL2_SET: 0x1324 HW_PINCTRL_IRQPOL2_CLR: 0x1328 HW_PINCTRL_IRQPOL2_TOG: 0x132C This register selects the polarity for interrupt generation. Each pin in bank 2 which is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting this register and HW_PINCTRL_IRQLEVEL2 (see above) appropriately. Address: 8001_8000h base + 1320h offset = 8001_9320h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSRVD1 R 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQPOL W Reset 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQPOL2 field descriptions Field Description 31-28 RSRVD1 Empty Description. IRQPOL Each bit in this register corresponds to one of the 28 pins in bank 2: 0= Low or falling edge; 1= High or rising edge. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 866 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 9.4.76 PINCTRL Bank 3 Interrupt Polarity Register (HW_PINCTRL_IRQPOL3) The PINCTRL Bank 3 Interrupt Polarity Register selects the polarity for interrupt requests for the pins in bank 3. HW_PINCTRL_IRQPOL3: 0x1330 HW_PINCTRL_IRQPOL3_SET: 0x1334 HW_PINCTRL_IRQPOL3_CLR: 0x1338 HW_PINCTRL_IRQPOL3_TOG: 0x133C This register selects the polarity for interrupt generation. Each pin in bank 3 which is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting this register and HW_PINCTRL_IRQLEVEL3 (see above) appropriately. Address: 8001_8000h base + 1330h offset = 8001_9330h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 Bit IRQPOL W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R IRQPOL W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 867 Pin Control Memory Map/Register Definition HW_PINCTRL_IRQPOL3 field descriptions Field Description 31 RSRVD1 Empty Description. IRQPOL Each bit in this register corresponds to one of the 31 pins in bank 3: 0= Low or falling edge; 1= High or rising edge. 9.4.77 PINCTRL Bank 4 Interrupt Polarity Register (HW_PINCTRL_IRQPOL4) The PINCTRL Bank 4 Interrupt Polarity Register selects the polarity for interrupt requests for the pins in bank 4. HW_PINCTRL_IRQPOL4: 0x1340 HW_PINCTRL_IRQPOL4_SET: 0x1344 HW_PINCTRL_IRQPOL4_CLR: 0x1348 HW_PINCTRL_IRQPOL4_TOG: 0x134C This register selects the polarity for interrupt generation. Each pin in bank 4 which is configured for interrupt generation can be independently set to interrupt on low level, high level, rising edge, or falling edge by setting this register and HW_PINCTRL_IRQLEVEL4 (see above) appropriately. Address: 8001_8000h base + 1340h offset = 8001_9340h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 RSRVD1 R 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 IRQPOL W Reset 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQPOL4 field descriptions Field Description 31-21 RSRVD1 Empty Description. IRQPOL Each bit in this register corresponds to one of the 21 pins in bank 4: 0= Low or falling edge; 1= High or rising edge. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 868 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) 9.4.78 PINCTRL Bank 0 Interrupt Status Register (HW_PINCTRL_IRQSTAT0) The PINCTRL Bank 0 Interrupt Status Register reflects pending interrupt status for the pins in bank 0. HW_PINCTRL_IRQSTAT0: 0x1400 HW_PINCTRL_IRQSTAT0_SET: 0x1404 HW_PINCTRL_IRQSTAT0_CLR: 0x1408 HW_PINCTRL_IRQSTAT0_TOG: 0x140C This register reflects the pending interrupt status for pins in bank 0. Bits in this register are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling edge) occurs on a bank 0 pin which has been enabled as an interrupts source in the HW_PINCTRL_PIN2IRQ0 register. Software may clear any bit in this register by writing a 1 to the bit at the SCT clear address, for example, HW_PINCTRL_IRQSTAT0_CLR. Status bits for pins configured as level sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in HW_PINCTRL_PIN2IRQ0. If a bit is set in this register, and the corresponding bit is also set in the HW_PINCNTRL_IRQEN0 mask register, then the GPIO0 interrupt will be asserted to the interrupt collector. Address: 8001_8000h base + 1400h offset = 8001_9400h Bit R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 0 0 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQSTAT W Reset 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQSTAT0 field descriptions Field Description 31-29 RSRVD1 Empty Description. IRQSTAT Each bit in this register corresponds to one of the 29 pins in bank 0: 0= No interrupt pending; 1= Interrupt pending. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 869 Pin Control Memory Map/Register Definition 9.4.79 PINCTRL Bank 1 Interrupt Status Register (HW_PINCTRL_IRQSTAT1) The PINCTRL Bank 1 Interrupt Status Register reflects pending interrupt status for the pins in bank 1. HW_PINCTRL_IRQSTAT1: 0x1410 HW_PINCTRL_IRQSTAT1_SET: 0x1414 HW_PINCTRL_IRQSTAT1_CLR: 0x1418 HW_PINCTRL_IRQSTAT1_TOG: 0x141C This register reflects the pending interrupt status for pins in bank 1. Bits in this register are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling edge) occurs on a bank 1 pin which has been enabled as an interrupts source in the HW_PINCTRL_PIN2IRQ1 register. Software may clear any bit in this register by writing a 1 to the bit at the SCT clear address, e.g., HW_PINCTRL_IRQSTAT1_CLR. Status bits for pins configured as level sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in HW_PINCTRL_PIN2IRQ1. If a bit is set in this register, and the corresponding bit is also set in the HW_PINCNTRL_IRQEN1 mask register, then the GPIO1 interrupt will be asserted to the interrupt collector. Address: 8001_8000h base + 1410h offset = 8001_9410h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQSTAT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQSTAT1 field descriptions Field IRQSTAT Description Each bit in this register corresponds to one of the 32 pins in bank 1: 0= No interrupt pending; 1= Interrupt pending. 9.4.80 PINCTRL Bank 2 Interrupt Status Register (HW_PINCTRL_IRQSTAT2) The PINCTRL Bank 2 Interrupt Status Register reflects pending interrupt status for the pins in bank 2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 870 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_IRQSTAT2: 0x1420 HW_PINCTRL_IRQSTAT2_SET: 0x1424 HW_PINCTRL_IRQSTAT2_CLR: 0x1428 HW_PINCTRL_IRQSTAT2_TOG: 0x142C This register reflects the pending interrupt status for pins in bank 2. Bits in this register are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling edge) occurs on a bank 2 pin which has been enabled as an interrupts source in the HW_PINCTRL_PIN2IRQ2 register. Software may clear any bit in this register by writing a 1 to the bit at the SCT clear address, e.g., HW_PINCTRL_IRQSTAT2_CLR. Status bits for pins configured as level sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in HW_PINCTRL_PIN2IRQ2. If a bit is set in this register, and the corresponding bit is also set in the HW_PINCNTRL_IRQEN2 mask register, then the GPIO2 interrupt will be asserted to the interrupt collector. Address: 8001_8000h base + 1420h offset = 8001_9420h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSRVD1 R 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQSTAT W Reset 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PINCTRL_IRQSTAT2 field descriptions Field Description 31-28 RSRVD1 Empty Description. IRQSTAT Each bit in this register corresponds to one of the 28 pins in bank 2: 0= No interrupt pending; 1= Interrupt pending. 9.4.81 PINCTRL Bank 3 Interrupt Status Register (HW_PINCTRL_IRQSTAT3) The PINCTRL Bank 3 Interrupt Status Register reflects pending interrupt status for the pins in bank 3. HW_PINCTRL_IRQSTAT3: 0x1430 HW_PINCTRL_IRQSTAT3_SET: 0x1434 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 871 Pin Control Memory Map/Register Definition HW_PINCTRL_IRQSTAT3_CLR: 0x1438 HW_PINCTRL_IRQSTAT3_TOG: 0x143C This register reflects the pending interrupt status for pins in bank 3. Bits in this register are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling edge) occurs on a bank 3 pin which has been enabled as an interrupts source in the HW_PINCTRL_PIN2IRQ3 register. Software may clear any bit in this register by writing a 1 to the bit at the SCT clear address, e.g., HW_PINCTRL_IRQSTAT3_CLR. Status bits for pins configured as level sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in HW_PINCTRL_PIN2IRQ3. If a bit is set in this register, and the corresponding bit is also set in the HW_PINCNTRL_IRQEN3 mask register, then the GPIO3 interrupt will be asserted to the interrupt collector. Address: 8001_8000h base + 1430h offset = 8001_9430h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 Bit IRQSTAT W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R IRQSTAT W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 872 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_IRQSTAT3 field descriptions Field Description 31 RSRVD1 Empty Description. IRQSTAT Each bit in this register corresponds to one of the 31 pins in bank 3: 0= No interrupt pending; 1= Interrupt pending. 9.4.82 PINCTRL Bank 4 Interrupt Status Register (HW_PINCTRL_IRQSTAT4) The PINCTRL Bank 4 Interrupt Status Register reflects pending interrupt status for the pins in bank 4. HW_PINCTRL_IRQSTAT4: 0x1440 HW_PINCTRL_IRQSTAT4_SET: 0x1444 HW_PINCTRL_IRQSTAT4_CLR: 0x1448 HW_PINCTRL_IRQSTAT4_TOG: 0x144C This register reflects the pending interrupt status for pins in bank 4. Bits in this register are automatically set by hardware when an interrupt condition (level high, level low, rising edge, or falling edge) occurs on a bank 4 pin which has been enabled as an interrupts source in the HW_PINCTRL_PIN2IRQ4 register. Software may clear any bit in this register by writing a 1 to the bit at the SCT clear address, e.g., HW_PINCTRL_IRQSTAT4_CLR. Status bits for pins configured as level sensitive interrupts cannot be cleared unless either the actual pin is in the non-interrupting state, or the pin has been disabled as an interrupt source by clearing its bit in HW_PINCTRL_PIN2IRQ4. If a bit is set in this register, and the corresponding bit is also set in the HW_PINCNTRL_IRQEN4 mask register, then the GPIO4 interrupt will be asserted to the interrupt collector. Address: 8001_8000h base + 1440h offset = 8001_9440h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 RSRVD1 R 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 IRQSTAT W Reset 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 873 Pin Control Memory Map/Register Definition HW_PINCTRL_IRQSTAT4 field descriptions Field Description 31-21 RSRVD1 Empty Description. IRQSTAT Each bit in this register corresponds to one of the 21 pins in bank 4: 0= No interrupt pending; 1= Interrupt pending. 9.4.83 PINCTRL EMI Slice ODT Control (HW_PINCTRL_EMI_ODT_CTRL) The PINCTRL EMI On Die Termination (ODT) Control Register Controls the load and calibration of each EMI slice. HW_PINCTRL_EMI_ODT_CTRL: 0x1a40 HW_PINCTRL_EMI_ODT_CTRL_SET: 0x1a44 HW_PINCTRL_EMI_ODT_CTRL_CLR: 0x1a48 HW_PINCTRL_EMI_ODT_CTRL_TOG: 0x1a4C This register controls On Die Termination for the EMI SLices 0-3. Address: 8001_8000h base + 1A40h offset = 8001_9A40h Bit 31 30 29 28 RSRVD1 R Bit R W Reset 26 ADDRESS_ CALIB W Reset 27 25 24 ADDRESS_ TLOAD 23 22 CONTROL_ CALIB 21 20 CONTROL_ TLOAD 19 18 DUALPAD_ CALIB 17 16 DUALPAD_ TLOAD 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLICE3_ CALIB SLICE3_ TLOAD SLICE2_ CALIB SLICE2_ TLOAD SLICE1_ CALIB SLICE1_ TLOAD SLICE0_ CALIB SLICE0_ TLOAD 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 HW_PINCTRL_EMI_ODT_CTRL field descriptions Field 31-28 RSRVD1 27-26 ADDRESS_ CALIB Description Empty Description. ODT Calibration for EMI ADDRESS: Fine tuning of the ODT resistance for the EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 874 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_EMI_ODT_CTRL field descriptions (continued) Field Description 1= 1-step Adjustment; 2= 2-step Adjustment; 3= 3-step Adjustment; With ODT disabled: Disabled; 25-24 ADDRESS_ TLOAD Termination Resistince for EMI ADDRESS: Selection of the on-chip ODT resistance for EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled 1= 75 ohm 2= 150 ohm 3= 50 ohm With ODT disabled: Disabled; 23-22 CONTROL_ CALIB ODT Calibration for EMI CONTROL signals: Fine tuning of the ODT resistance for the EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled; 1= 1-step Adjustment; 2= 2-step Adjustment; 3= 3-step Adjustment; With ODT disabled: Disabled; 21-20 CONTROL_ TLOAD Termination Resistince for EMI CONTROL: Selection of the on-chip ODT resistance for EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled 1= 75 ohm 2= 150 ohm 3= 50 ohm With ODT disabled: Disabled; 19-18 DUALPAD_ CALIB ODT Calibration for EMI DUALPAD(Differential PAD): Fine tuning of the ODT resistance for the EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled; 1= 1-step Adjustment; 2= 2-step Adjustment; 3= 3-step Adjustment; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 875 Pin Control Memory Map/Register Definition HW_PINCTRL_EMI_ODT_CTRL field descriptions (continued) Field Description With ODT disabled: Disabled; 17-16 DUALPAD_ TLOAD Termination Resistince for EMI DUALPAD(Differential PAD): Selection of the on-chip ODT resistance for EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled 1= 75 ohm 2= 150 ohm 3= 50 ohm With ODT disabled: Disabled; 15-14 SLICE3_CALIB ODT Calibration for EMI SLICE3: Fine tuning of the ODT resistance for the EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled; 1= 1-step Adjustment; 2= 2-step Adjustment; 3= 3-step Adjustment; With ODT disabled: Disabled; 13-12 Termination Resistince for EMI SLICE3: SLICE3_TLOAD Selection of the on-chip ODT resistance for EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled 1= 75 ohm 2= 150 ohm 3= 50 ohm With ODT disabled: Disabled; 11-10 SLICE2_CALIB ODT Calibration for EMI SLICE2: Fine tuning of the ODT resistance for the EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled; 1= 1-step Adjustment; 2= 2-step Adjustment; 3= 3-step Adjustment; With ODT disabled: Disabled; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 876 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_EMI_ODT_CTRL field descriptions (continued) Field Description 9-8 Termination Resistince for EMI SLICE2: SLICE2_TLOAD Selection of the on-chip ODT resistance for EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled 1= 75 ohm 2= 150 ohm 3= 50 ohm With ODT disabled: Disabled; 7-6 SLICE1_CALIB ODT Calibration for EMI SLICE1: Fine tuning of the ODT resistance for the EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled; 1= 1-step Adjustment; 2= 2-step Adjustment; 3= 3-step Adjustment; With ODT disabled: Disabled; 5-4 Termination Resistince for EMI SLICE1: SLICE1_TLOAD Selection of the on-chip ODT resistance for EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled 1= 75 ohm 2= 150 ohm 3= 50 ohm With ODT disabled: Disabled; 3-2 SLICE0_CALIB ODT Calibration for EMI SLICE0: Fine tuning of the ODT resistance for the EMI pads. ODT must be enabled for this configuration to take effect 0= Disabled; 1= 1-step Adjustment; 2= 2-step Adjustment; 3= 3-step Adjustment; With ODT disabled: Disabled; SLICE0_TLOAD Termination Resistince for EMI SLICE0: Selection of the on-chip ODT resistance for EMI pads. ODT must be enabled for this configuration to take effect Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 877 Pin Control Memory Map/Register Definition HW_PINCTRL_EMI_ODT_CTRL field descriptions (continued) Field Description 0= Disabled 1= 75 ohm 2= 150 ohm 3= 50 ohm With ODT disabled: Disabled; 9.4.84 PINCTRL EMI Slice DS Control (HW_PINCTRL_EMI_DS_CTRL) The PINCTRL EMI On Die Termination (DS) Control Register Controls the load and calibration of each EMI slice. HW_PINCTRL_EMI_DS_CTRL: 0x1b80 HW_PINCTRL_EMI_DS_CTRL_SET: 0x1b84 HW_PINCTRL_EMI_DS_CTRL_CLR: 0x1b88 HW_PINCTRL_EMI_DS_CTRL_TOG: 0x1b8C This register controls Pad Drive Strength for the EMI SLices 0-3. Address: 8001_8000h base + 1B80h offset = 8001_9B80h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RSRVD1 R Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 W Reset 16 DDR_MODE W Reset 17 0 0 ADDRESS_ MA 0 0 CONTROL_ MA 0 0 DUALPAD_ MA 0 0 SLICE3_MA 0 0 SLICE2_MA 0 SLICE1_MA 0 0 0 SLICE0_MA 0 0 HW_PINCTRL_EMI_DS_CTRL field descriptions Field 31-18 RSRVD1 17-16 DDR_MODE Description Empty Description. set working mode for EMI pads, default is DDR2 mode: bit 1 controls DDR2_EN bit 0 controls LVDDR2_ENB Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 878 Freescale Semiconductor, Inc. Chapter 9 Pin Control and GPIO (PinCtrl) HW_PINCTRL_EMI_DS_CTRL field descriptions (continued) Field Description 00 01 10 11 15-14 RSRVD0 13-12 ADDRESS_MA mDDR -- mDDR(LPDDR1) mode DISABLED -- low power suspend mode, in which EMI pads are disabled LVDDR2 -- LVDDR2 mode DDR2 -- DDR2 mode Empty Description. Pin output drive strength selection for the EMI address signals: 00= 5 mA; 01= 10 mA; 10= 20 mA; 11= Reserved; 11-10 Pin output drive strength selection for the EMI control signals: CONTROL_MA 00= 5 mA; 01= 10 mA; 10= 20 mA; 11= Reserved; 9-8 DUALPAD_MA Pin output drive strength selection for the dual pads (CLK/CLKN and DQS/DQSN): 00= 5 mA; 01= 10 mA; 10= 20 mA; 11= Reserved; 7-6 SLICE3_MA Pin output drive strength selection for SLICE 3: 00= 5 mA; 01= 10 mA; 10= 20 mA; 11= Reserved; 5-4 SLICE2_MA Pin output drive strength selection for SLICE 2: 00= 5 mA; 01= 10 mA; 10= 20 mA; 11= Reserved; 3-2 SLICE1_MA Pin output drive strength selection for SLICE 1: 00= 5 mA; 01= 10 mA; 10= 20 mA; 11= Reserved; SLICE0_MA Pin output drive strength selection for SLICE 0: 00= 5 mA; 01= 10 mA; Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 879 Pin Control Memory Map/Register Definition HW_PINCTRL_EMI_DS_CTRL field descriptions (continued) Field Description 10= 20 mA; 11= Reserved; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 880 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) 10.1 Clock Generation and Control (CLKCTRL) Overview The clock control module, or CLKCTRL, generates the clock domains for all components in the i.MX28 system. The crystal clock or PLL clock are the two fundamental sources used to produce all the clock domains. For lower performance and reduced power consumption, the crystal clock is selected. The PLL is selected for higher performance requirements but requires increased power consumption. In most cases, when the PLL is used as the source, a phase fractional divider (PFD) can be programmed to reduce the PLL clock frequency by up to a factor of 2. The PLL and PFD clocks are used as reference clock sources to drive digital clock dividers in the clock control module. These reference clocks, or ref_, drive the digital clock dividers in CLKCTRL. The digital clock dividers have three modes of operation, integer divide mode, fractional divide mode, and gated clock mode. The details of these three modes will be described to understand which mode should be selected to achieve the desired frequency. All programming control for system clocks are contained in the CLKCTRL module. All clock domains have a programmable clock frequency to meet application requirements. Also, all analog clock control programming is done indirectly through the CLKCTRL module. This contains the complexity of overall system clock selection to a single device. Also, the hardware used to generate all clock domains is replicated. Following is a description of all clock domains in the i.MX28 system. 10.2 Clock Structure The reference clocks are used in CLKCTRL as fundamental clock sources to produce clock domains throughout the system. A reference clock can be either the crystal clock, 480 MHz PLL, or PFD output from the analog module. The selected reference clock is used by a digital clock divider to produce the desired clock domain. The table below i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 881 Clock Structure summarizes all available reference clocks used within the CLKCTRL and all clock domains used in the system. The diagram that follows depicts all clock domains and how they are connected within the CLKCTRL module. This should provide a reference for how clocks are generated within the i.MX28 system. 10.2.1 Table of System Clocks The following table summarizes the clocks produced by the clock control module. Table 10-1. System Clocks NAME REFERENC E DIVIDE/ FREQ DESCRIPTION Reference Clocks. ref_xtal xtal_24m/ 1 This is the muxed select between the internal ring oscillator and the external crystal. ring_24m ref_cpu PLL0 9 phase The 9 phase fractional divider output used as the reference for the CPU clock divider. ref_emi PLL0 9 phase The 9 phase fractional divider output used as the reference for the EMI clock divider. ref_io0 PLL0 9 phase The 9 phase fractional divider output used as the reference for the SSP0/SSP1 clock dividers. ref_io1 PLL0 9 phase The 9 phase fractional divider output used as the reference for the SSP2/SSP3 clock divider. ref_pix PLL0 9 phase The 9 phase fractional divider output used as the reference for the LCDIF clock divider. ref_hsadc PLL0 9 phase The 9 phase fractional divider output used as the reference for the HSADC clock divider. ref_gpmi PLL0 9 phase The 9 phase fractional divider output used as the reference for the GPMI clock divider. ref_pll PLL0 1 This is the raw PLL output used as the reference for the SAIF0 and SAIF1 clock divider. ref_enet_pll PLL2 1 This is the raw PLL output used as the reference for the ENET clock divider. clk_p ref_xtal 10/6 bits Divided clock domains referenced from PLL or Xtal clock. ARM core clock. /ref_cpu clk_h clk_p 5 bits AHB/APBH clock domain. clk_h is a gated branch of the clk_p domain. clk_h_flexcan 0_ipg clk_h 1 Flexcan0 Message Buffer Management (MBM) clock whose clock gating is controlled by hw_clkctrl_flexcan register. clk_h_flexcan 1_ipg clk_h 1 Flexcan1 Message Buffer Management (MBM) clock whose clock gating is controlled by hw_clkctrl_flexcan register. clk_h_flexcan 0 clk_h 1 Flexcan0 bus clock which is gated off when no access to flexcan0 module. clk_h_flexcan 1 clk_h 1 Flexcan1 bus clock which is gated off when no access to flexcan1 module. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 882 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) Table 10-1. System Clocks (continued) NAME REFERENC E DIVIDE/ FREQ DESCRIPTION clk_h_enet_s wi clk_h 1 Ethernet Switch bus clock whose clock gating is controlled by hw_clkctrl_enet register. clk_h_mac0 clk_h 1 Ethernet MAC0 bus clock whose clock gating is controlled by hw_clkctrl_enet register. clk_h_mac1 clk_h 1 Ethernet MAC1 bus clock whose clock gating is controlled by hw_clkctrl_enet register. clk_ocrom clk_h 1 OCROM bus clock whose clock gating is controlled by OCROM controller H/W. clk_etm ref_xtal 6/6 bits ARM etm clock. 4/6 bits External DDR interface clock. /ref_cpu clk_emi ref_xtal /ref_emi /ref_cpu clk_ssp0 ref_xtal/ ref_io0 9 bits SSP0 interface clock. clk_ssp1 ref_xtal/ ref_io0 9 bits SSP1 interface clock. clk_ssp2 ref_xtal/ ref_io1 9 bits SSP2 interface clock. clk_ssp3 ref_xtal/ ref_io1 9 bits SSP3 interface clock. clk_gpmi ref_xtal 8 bits General purpose memory interface clock domain. /ref_gpmi clk_spdif/ clk_pcmspdif ref_xtal Clk_spdif is an intermediate clock that drives the clk_pcmspdif fractional clock divider. clk_saif0 ref_xtal/ ref_pll DDA Serial Audio Interface clock domain. Its reference is the PLL clock output which drives a DDA (Digital Differential Analyzer) fractional divider. clk_saif1 ref_xtal/ ref_pll DDA Serial Audio Interface clock domain. Its reference is the PLL clock output which drives a DDA (Digital Differential Analyzer) fractional divider. clk_dis_lcdif ref_xtal/ ref_pix 13 bits clk_hsadc ref_hsadc 9/18/36/ 72 clk_enet_time ref_pll 6 bits /ref_pll LCD interface clock. High-Speed ADC clock. Ethernet 1588 timer clock /ref_xtal /ref_net_pll Divided clock domains referenced from Xtal clock. clk_x ref_xtal 10 bits APBX clock domain. clk_uart ref_xtal 2 bits UART clock domain. Fixed clock domains. clk_xtal24m ref_xtal 24Mhz Used for the PWM and analog 24 MHz clock domains. clk_32k ref_xtal 32khz Fixed 32 KHz clock domain. The reference is the 24 MHz crystal and divides by 768 to produce 32 KHz. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 883 Clock Structure Table 10-1. System Clocks (continued) NAME REFERENC E DIVIDE/ FREQ DESCRIPTION clk_flexcan0_ nogate ref_xtal 24MHz Flexcan0 CAN Protocol Interface(CPI) clock without gating. clk_flexcan1_ nogate ref_xtal 24MHz Flexcan1 CAN Protocol Interface(CPI) clock without gating. clk_flexcan0 ref_xtal 24MHz Flexcan0 CAN Protocol Interface (CPI) clock with gating which is controlled by FLEXCAN H/W. clk_flexcan1 ref_xtal 24MHz Flexcan1 CAN Protocol Interface (CPI) clock with gating which is controlled by FLEXCAN H/W. clk_lradc2k ref_xtal 2khz Fixed 2 KHz clock domain. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 884 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) 10.2.2 Logical Diagram of Clock Domains System PLL1, USB1 ------------------------------------- PLL1 HW_CLKCTRL_PLL1CTRL PLL 480M UTMI1_CLK480M HW_CLKCTRL_PLL0CTRL UTMI0_CLK480M 7 bit Int/Frac HW_CLKCTRL_ETM ICG ref_xtal Dynamic Power Adjust ICG ICG ICG ICG ICG ICG ICG PLL0 Phase Div Phase Div Phase Div Phase Div Phase Div Phase Div Phase Div HW_CLKCTRL_HBUS 5 bit 1 to 31 HW_CLKCTRL_CPU 6 bit HW_CLKCTRL_EMI 6 bit ref_cpu ref_emi ref_io0 ref_io1 ref_pix ref_hsadc ref_gpmi CLK_P_NG Int ICG ref_xtal HW_CLKCTRL_CPU & INTERRUPT WAIT circuit ICG 6 bit Int ICG Int HW_CLKCTRL_EMI 4 bit ref_emi ref_xtal ref_xtal ref_io1 CLK_SSP (X2) 9 bit Int/Frac ICG ref_xtal CLK_EMI HW_CLKCTRL_EMI_SYNC_MODE_EN 9 bit ICG Int/Frac HW_CLKCTRL_SSP0(1) ref_io0 CLK_P ICG Int/Frac HW_CLKCTRL_CPU 10 bit HW_CLKCTRL_EMI 4 bit ref_pll PLL 480M ICG CLK_H_FLEXCAN_IPG(x2) ICG CLK_H_ENET_SWI CLK_H ICG CLK_OCROM ICG CLK_H_MAC(x2) ICG CLK_H_FLEXCAN0(x2) EN1 ICG EN2 HW_CLKCTRL_HBUS System PLL0, Multi-Output PLL Each output configurable for frequency and bypass. ------------------------------------- CLK_ETM CLK_SSP (X2) HW_CLKCTRL_SSP2(3) ref_pix 13 bit ICG Int/Frac HW_CLKCTRL_DIS_LCDIF0 ref_xtal ref_hsadc HSADC DIV HW_CLKCTRL_HSADC ref_gpmi CLK_HSADC 10 bit Int/Frac ICG ref_xtal ICG CLK_DIS_LCDIF CLK_GPMI HW_CLKCTRL_GPMI ref_pll ref_xtal HW_CLKCTRL_SPDIF ICG 16 bit ICG Frac HW_CLKCTRL_SAIF CLK_SAIF (X2) 9 bit 4 Fixed Divider CLK_PCMSPDIF Frac via HW_SPDIF_SRR ref_pll 6 bit Crystal Clock XTAL_CLK24M 24.000 MHz ICG CLK_UART gl Ring Oscillator RING_CLK24M 24.000 MHz HW_CLKCTRL_ENET enet_rmii_clk_in 0 ICG CLK_ENET_TIME Int ref_xtal HW_CLKCTRL_ENET_TIME_SEL ref_xtal 1 HW_CLKCTRL_XTAL (2 Clock Gate control bits) ICG CLK_PWM24M HW_POWER_MINPWR HW_CLKCTRL_XTAL ICG CLK_32K 750 Fixed Divider CLK_LRADC2k 16 Fixed Divider 10 bit ICG Int/Frac HW_CLKCTRL_XBUS CLK_X CLK_ANA24M HW_CLKCTRL_XTAL ICG Crystal Clock XTAL_CLK32K 32.768 kHz / 32.0 kHz 768 CLK_RTC32K HW_RTC_PERSISTENT0_CLKSOURCE CLK_FLEXCAN_NOGATE(x2) ICG ref_enet_pll PLL2 50M ENET_CLK via ENET Controller H/W CLK_ENET_OUT Int enet_rmii_clk_in PAD CLK_ENET_OUT CLK_FLEXCAN (x2) via FLEXCAN Controller H/W ICG CLK_ENET_RMII HW_CLKCTRL_ENET HW_CLKCTRL_ENET_CLK_OUT_EN ENET_MII_PHY0 ICG CLK_MAC0_RX ICG CLK_MAC0_TX HW_CLKCTRL_ENET Others Analog Digital - Xtal Only Digital - Xtal or PLL Digital - PLL Only Legend Unless otherwise shown, all multiplexers are controlled via HW_CLKCTRL_CLKSEQ Within CLKCTRL Figure 10-1. Logical Diagram of Clock Domains i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 885 Clock Structure 10.2.3 Clock Domain Description All major functional clock domains/branches have trunk level clock gating for power management. The intent is to gate clock domains off when modules of certain applications are not necessary. This clock gating is instantiated using an ICG element from the standard cell library. Software will have to enable the clock domain that drives on chip devices where trunk level clock gating is implemented. The location of ICG elements to gate clock domains is not systematic. Since most of the clock structures throughout the system are unique, the location of ICGs for clock tree power reduction differs from one domain to the other. The location of these ICGs to gate off clock domains is apparent in the clock structure diagram. All clock domains are asynchronous unless noted otherwise. 10.2.3.1 CLK_P, CLK_H The clk_p domain is used to drive the integrated ARM9 core. The reference for clk_p can be either ref_xtal or ref_cpu. The reference ref_cpu drives a 6-bit clock divider to provide a maximum divide down of the reference clock by 2^6. The reference ref_xtal drives a 10-bit clock divider to provide a maximum divide down of the selected reference clock by 2^10. All of the ARM core and SoC components on the clk_h branch are considered to be on the clk_p domain. The clk_h is actually a branch of the clk_p domain. So, clk_h runs synchronous to clk_p. The clk_h domain can be programmed to any divided ratio with respect to the clk_p domain depending on performance and power requirements. A dynamic clock frequency management controller monitors the system performance requirements and scales the clk_h frequency to meet the performance needs. When the CPU or support components require data transfer to/from the system memory, the frequency manager scales the clk_h domain to meet the system performance requirements. Also, when the system is quiesced, the clk_h frequency is reduced to save power. The clk_h has a 5-bit divider that divides the clk_p domain to produce the clk_h domain. The frequency for clk_h can be clk_p/32 <= clk_h <= clk_p. Two divide modes exist for the clk_h branch: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 886 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) * Integer divide: In this mode, the value programmed in the hw_clkctrl_hbus.div field represents an integer divide value. * Fractional divide: In this mode, the value programmed in the hw_clkctrl_hbus.div field represents a binary fraction. When the accumulation of the current count and the programmed divide value carry out of the most significant bit, a clk_h pulse is generated. For example, to achieve a 8:3 clk_p:clk_h clock ratio, set the div field to 0.01100 which represents (0*1/2) + (1*1/4) + (1*1/8) + (0*1/16) + (0*1/32). Note, fractional divide can not be used when clk_emi is synchronous with clk_h. The clk_h branch can be further divided by the dynamic clock frequency adjustment logic, (hw_clkctrl_emi_sync_mode_en = 0 only). When all the system clk_h components are not busy and their respective busy signals are inactive, the clk_h branch is further divided down by the value in the hw_clkctrl_hbus register. The frequency reduction of the clk_h branch saves overall power consumption. Note, the dynamic clock frequency adjustment logic should not be enabled when clk_emi is synchronous with clk_h. 10.2.3.2 CLK_EMI The external memory interface domain is called clk_emi. This clock can be asynchronous to clk_h to achieve the highest possible clock rate for the EMI interface, or synchronously to minimize the incurred latency for CPU access to external DRAM. This option is provided to tradeoff the optimization of performace for systems that are dependent on memory access latency or throughput. When the hw_clkctrl_emi_sync_mode_en bit is set to 1, clk_h is synchronous and edge aligned with the emi clock and clk_p. The emi clock dividers will set the frequency of clk_h and clk_emi domains when synchronous mode is selected. In synchronous mode, the dynamic clock frequency adjust logic should be disabled. This is required since DRAM devices cannot operate correctly with changing clock frequencies. 10.2.3.3 System Clocks All reference clock domains used in the CLKCTRL are driven by replicated instances of the PFD pre dividers in the analog module. These PFD reference clocks drive replicated instances of a single digital clock divider design to create all system clocks. The following sections describe the features of the digital clock dividers and how these drives can be used to create clocks throughout the system. The CLKCTRL structural diagram should be used with the digital clock divider description to understand how clocks are generated in the i.MX28 system. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 887 CLKCTRL Digital Clock Divider 10.3 CLKCTRL Digital Clock Divider The digital clock divider that is used to drive all the functional clock domains has three modes of operation. These include: * Integer divide mode * Fractional divide mode * Gated clock divide mode These modes are described in the following three sections. 10.3.1 Integer Clock Divide Mode Each divider has the capability to divide an input reference frequency by a fixed integer value. This is the most common mode that will be used to select a particular clock frequency. For a desired clock frequency, first try to select a PFD reference clock frequency AND an integer clock divide value to achieve the desired clock domain frequency. This mode is selected when the respective frac_en field in the clock control register is logic 0. The divide value will be in the range of 1 to 2^N. When programming the DIV field to 1, the reference clock for the domain is passed and the clock domain assumes the same frequency as the reference domain. When a value of 2 is programmed, the clock domain frequency will be half the reference clock frequency. The maximum divide value depends on the number of bits each digital clock divider implements. This is different for each digital clock divider. The number of bits implemented for each divider is indicated by each DIV field that controls each clock domain. Divide by zero is NOT a valid programming value for the DIV field of any clock control PIO register. 10.3.2 Fractional Clock Divide Mode This mode is used to divide a reference clock in the range of 2 < div < 2^N. The fractional clock divider in the CLKCTRL module implements a fractional counter to approximate a divided clock with respect to the selected reference frequency. The accuracy of the output clock is dependent on the extent of the bits used to implement the fractional counter. The reference clock frequency and the fractional divide value must both be selected to achieve the desired output frequency. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 888 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) This mode is enabled when setting the FRAC_EN field of the respective clock domain control register to logic 1 AND the most significant bit of the DIV field is logic 0. Do NOT use this mode to divide the reference clock domain by an integer value (such as 4, 8, and so on). Use the integer divide mode to achieve the best results to divide by an integer. Note It is important to note that the nearest rising or falling edge of the input reference clock frequency is used to approximate the rising edge of the output clock domain. So, the output clock frequency will jitter based on the input reference clock frequency and the programmed fractional divide value. 10.3.2.1 Fractional Clock Divide Example, Divide by 3.5 As an example, if the desired divide value is 3.5, the digital approximation of 1/3.5 is 0.01001001 using a 8 bit fractional approximation. The most significant bit of the div field in this case is logic 0, so the fractional divide mode is selected. The following sequence indicates the first eight values of the fractional clock divider. The accumulated count is simply the current value incremented by the value programmed in the div field on each cycle. 1. 0.01001001 2. 0.10010010 3. 0.11011011 4. 1.00100100 (carry out of MSB initiates an output clock edge) 5. 0.01101101 6. 0.10110110 7. 0.11111111 8. 1.01001000 (output edge initiated) When the carry out of the fractional count is one, a rising edge output pulse is initiated and the remainder of the accumulator is preserved. The sub-fractional accumulated value is considered to determine if the output edge should occur on the falling edge of the reference clock or the rising edge of the reference clock to minimize the output clock jitter. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 889 CLKCTRL Digital Clock Divider 10.3.2.1.1 Fractional ClockDivide Example, Divide by 3/8 This example uses a 3-bit fractional accumulator to divide the reference clock input by 3/8. There are 3 output clock edges produced for every eight input reference clock edges. An output edge is generated on every cycle that the fractional accumulator carries out of the most significant bit. Notice when the fractional component is .01, the output edge is shifted and generated off the falling edge of the input reference clock. This is done to produce the best output duty cycle that can be achieved based on the input reference clock frequency. 3 output clocks repeats every 8 reference clocks CLK_REF 3 bit divider 0.000 0.011 0.110 1.001 0.100 0.111 1.010 0.101 1.000 0.011 CLK_OUT 2nd cycle on falling clk_ref 1/2 cycle shift Figure 10-2. Fractional Clock divide; 3/8 example 10.3.3 Gated Clock Divide Mode This mode is selected when the reference clock frequency is divided by a range of 1 < div < 2. To select this mode, program the FRAC_EN field to logic 1 and progarm the DIV field with the most significant bit set to logic 1. In this case, the reference clock is enabled/disabled on a cycle by cycle basis to pass to the output clock domain. Essentially, the reference clock is gated on or off depending on the carry out bit of the fractional count accumulator. This option is useful to divide the 24 MHz clock to a range between 12 to 24 MHz. The effective period is equal to the reference period since the output clock is a gated version of the reference clock. For example, a divide value of 4/3 will allow three consecutive pulses of the reference clock to propagate and will then gate off a single reference clock cycle. The edge to edge timing is effectively equal to the reference clock. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 890 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) Output clock period equal to reference clock. CLK_REF CLK_OUT 3 output clocks for every 4 reference clocks. Figure 10-3. Divide Range 1 < div < 2 10.4 Clock Frequency Management Clock frequency selection for some domains can be a function of multiple reference clock sources and divide parameters that are set in the CLKCTRL PIO control registers. The most extreme case is using a programmable fractional PLL clock divider, a multiplexer that selects either the xtal clock or fractional PLL clock as a source to drive the CLKCTRL divider, and the divide value for the CLKCTRL divider itself. When programming a selected frequency, the sequence of events to achieve a given frequency must maintain the integrity of the system as a whole. During a clock system context switch, intermediate clock frequencies for the selected domains cannot be faster than the sub system or the I/O interface which is designed to support. It is expected that the sequence of events when a clock domain is tuned to a desired frequency be managed by a software using a hardware status polling mechanism. Each parameter has an associated enable bit so that all the divide parameters can be programmed in advance of the parameters taking effect. A single register, hw_clkctrl_clkseq, contains all the enable bits that cause the divide parameters to take effect. The enable bits can be set, the busy bits can be polled for each parameter, and thus the enable/busy sequencing through software control can manage the tuning of clock frequencies throughout the system. 10.5 Analog Clock Control Analog clock control is performed indirectly through PIO accessable registers in the CLKCTRL module. The analog circuits that are controlled through CLKCTRL PIO access are the PLL and all instances of the phase fractional dividers, or PFDs. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 891 CPU and EMI Clock Programming 10.6 CPU and EMI Clock Programming A defined protocol is necessary for selecting clock frequencies and root sources for driving the clk_p and clk_emi domains. These two clock structures are unique in that each implement a separate divider, one referenced by xtal clock and the other referenced by a PLL/PFD structure. The roots of these clocks must be programmed in order of the sources furthest from the trunk first. Elements in the clock roots should subsequently be configured along the root path up to the desired clock trunk. The programming sequence to go from a clock that is referenced from the xtal clock to the PLL is outlined below. This is the case when the device is in low power operation and there exists the need for higher clock rates to meet the demands of a more compute-intensive application. 1. The crystal is the current source for the CPU or the EMI clock domain. 2. Enable the PLL. 3. Wait for PLL lock. 4. Program and enable the PFD with the desired configuration. 5. Clear the PFD clock gate to establish the desired reference clock frequency. 6. Program the CLKCTRL clock divider register (EMI or CPU) that uses the PLL/PFD as its reference clock. 7. Switch the bypass to off (select PLL, not crystal). The requirement is that the roots of the clock are configured and stable before the elements higher up in the tree are programmed. This will allow the roots to stabilize before selected as a valid source to drive a clock trunk/tree. If this sequence is not honored, unpredictable frequencies can occur which may violate the maximum operating frequency of components on the respective clock trees. Be sure to gate off the clock paths directly downstream from the PLL before powering off the PLL. When clk_emi is operating in synchronous mode, the following requirements must be maintained: * The clk_p divide value is less than or equal to the clk_emi divide value. * The clk_emi divide value must be divisable by the clk_p divide value. An example of possible clk_p:clk_emi divide values would be, but not limited, to 1:1, 1:2, 1:3, 2:2, 2:4, 2:6, 3:3, 3:6, 3:9. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 892 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) 10.7 Chip Reset Two PIO accessible soft reset bits exist to establish the initial state of the device. These bits are called HW_CLKCTRL_RESET_CHIP and HW_CLKCTRL_RESET_DIG. Setting these bits will result in a chip wide reset cycle. When setting the DIG software reset bit, the digital logic is reset with the exception of the power module and the DCDC converter control logic. The CHIP software reset bit also initiates the full reset cycle and the power and the DCDC converter logic are also reset. These two soft reset bits themselves reset during a soft reset sequence. Ethernet module is a special case. To avoid network traffic blocking, Ethernet Switch need to maintain working as long as possible. So when the Ethernet module is in Switch mode, it can be configured to only POR resettable by setting both HW_CLKCTRL_ENET_RESET_BY_SW_CHIP and HW_CLKCTRL_ENET_RESET_BY_SW to 0. If Ethernet module is not in Switch mode, it will be reset by both DIG software reset bit and CHIP reset bit regardless of the value of HW_CLKCTRL_ENET_RESET_BY_SW_CHIP and HW_CLKCTRL_ENET_RESET_BY_SW. The following figure shows the functionality of these two reset bits. Chip Chip_reset_n Digital Domain HW_CLKCTRL_RESET_DIG FSM ENET_swi_reset_n ENET HW_CLKCTRL_RESET_CHIP Reset sequence clock control signals Power_reset_n Power DCDC Figure 10-4. Reset Logic Functional Diagram 10.8 Programmable Registers CLKCTRL Hardware Register Format Summary i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 893 Programmable Registers HW_CLKCTRL memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8004_0000 System PLL0, System/USB0 PLL Control Register 0 (HW_CLKCTRL_PLL0CTRL0) 32 R/W 0000_0000h 10.8.1/895 8004_0010 System PLL0, System/USB0 PLL Control Register 1 (HW_CLKCTRL_PLL0CTRL1) 32 R/W 0000_0000h 10.8.2/897 8004_0020 System PLL1, USB1 PLL Control Register 0 (HW_CLKCTRL_PLL1CTRL0) 32 R/W 8000_0000h 10.8.3/898 8004_0030 System PLL1, USB1 PLL Control Register 1 (HW_CLKCTRL_PLL1CTRL1) 32 R/W 0000_0000h 10.8.4/900 8004_0040 System PLL2, Ethernet PLL Control Register 0 (HW_CLKCTRL_PLL2CTRL0) 32 R/W 8000_0000h 10.8.5/902 8004_0050 CPU Clock Control Register (HW_CLKCTRL_CPU) 32 R/W 0001_0001h 10.8.6/903 8004_0060 AHB, APBH Bus Clock Control Register (HW_CLKCTRL_HBUS) 32 R/W 0000_0001h 10.8.7/905 8004_0070 APBX Clock Control Register (HW_CLKCTRL_XBUS) 32 R/W 0000_0100h 10.8.8/908 8004_0080 XTAL Clock Control Register (HW_CLKCTRL_XTAL) 32 R/W 6000_0001h 10.8.9/910 8004_0090 Synchronous Serial Port0 Clock Control Register (HW_CLKCTRL_SSP0) 32 R/W 8000_0001h 10.8.10/ 912 8004_00A0 Synchronous Serial Port1 Clock Control Register (HW_CLKCTRL_SSP1) 32 R/W 8000_0001h 10.8.11/ 913 8004_00B0 Synchronous Serial Port2 Clock Control Register (HW_CLKCTRL_SSP2) 32 R/W 8000_0001h 10.8.12/ 914 8004_00C0 Synchronous Serial Port3 Clock Control Register (HW_CLKCTRL_SSP3) 32 R/W 8000_0001h 10.8.13/ 916 8004_00D0 General-Purpose Media Interface Clock Control Register (HW_CLKCTRL_GPMI) 32 R/W 8000_0001h 10.8.14/ 917 8004_00E0 SPDIF Clock Control Register (HW_CLKCTRL_SPDIF) 32 R/W 8000_0000h 10.8.15/ 918 8004_00F0 EMI Clock Control Register (HW_CLKCTRL_EMI) 32 R/W 8000_0101h 10.8.16/ 919 8004_0100 SAIF0 Clock Control Register (HW_CLKCTRL_SAIF0) 32 R/W 8000_0001h 10.8.17/ 921 8004_0110 SAIF1 Clock Control Register (HW_CLKCTRL_SAIF1) 32 R/W 8000_0001h 10.8.18/ 923 8004_0120 CLK_DIS_LCDIF Clock Control Register (HW_CLKCTRL_DIS_LCDIF) 32 R/W 8000_0001h 10.8.19/ 924 8004_0130 ETM Clock Control Register (HW_CLKCTRL_ETM) 32 R/W 8000_0001h 10.8.20/ 925 8004_0140 ENET Clock Control Register (HW_CLKCTRL_ENET) 32 R/W E010_0000h 10.8.21/ 927 8004_0150 HSADC Clock Control Register (HW_CLKCTRL_HSADC) 32 R/W 0000_0000h 10.8.22/ 928 8004_0160 FLEXCAN Clock Control Register (HW_CLKCTRL_FLEXCAN) 32 R/W 7800_0000h 10.8.23/ 929 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 894 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8004_01B0 Fractional Clock Control Register 0 (HW_CLKCTRL_FRAC0) 32 R/W 9292_9292h 10.8.24/ 931 8004_01C0 Fractional Clock Control Register 1 (HW_CLKCTRL_FRAC1) 32 R/W 0092_9292h 10.8.25/ 933 8004_01D0 Clock Frequency Sequence Control Register (HW_CLKCTRL_CLKSEQ) 32 R/W 0044_83FFh 10.8.26/ 935 8004_01E0 System Reset Control Register (HW_CLKCTRL_RESET) 32 R/W 0000_0012h 10.8.27/ 937 8004_01F0 ClkCtrl Status (HW_CLKCTRL_STATUS) 32 R 0000_0000h 10.8.28/ 939 8004_0200 ClkCtrl Version (HW_CLKCTRL_VERSION) 32 R 0C02_0000h 10.8.29/ 939 10.8.1 System PLL0, System/USB0 PLL Control Register 0 (HW_CLKCTRL_PLL0CTRL0) HW_CLKCTRL_PLL0CTRL0: 0x000 HW_CLKCTRL_PLL0CTRL0_SET: 0x004 HW_CLKCTRL_PLL0CTRL0_CLR: 0x008 HW_CLKCTRL_PLL0CTRL0_TOG: 0x00C The PLL0 Control Register 0 programs the 480 MHz PLL0 and the USB0-clock enables. EXAMPLE HW_CLKCTRL_PLL0CTRL0_WR(BF_CLKCTRL_PLL0CTRL0_POWER(1)); PLL0 lock before using it // enable PLL and wait 10 us to let i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 895 Programmable Registers Address: 8004_0000h base + 0h offset = 8004_0000h 31 29 28 26 25 24 23 RSRVD5 22 21 20 19 RSRVD4 18 17 16 RSRV D1 POWER RSRVD6 27 EN_USB_CLKS R 30 RSRVD3 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LFR_SEL CP_SEL DIV_SEL W Reset Bit RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_PLL0CTRL0 field descriptions Field Description 31-30 RSRVD6 Always set to zero (0). 29-28 LFR_SEL TEST MODE FOR FREESCALE USE ONLY. Adjusts loop filter resistor. 27-26 RSRVD5 Always set to zero (0). 25-24 CP_SEL TEST MODE FOR FREESCALE USE ONLY. Adjusts charge pump current 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 DEFAULT -- Default loop filter resistor TIMES_2 -- Doubles the loop filter resistor TIMES_05 -- Halves the loop filter resistor UNDEFINED -- Undefined DEFAULT -- Default charge pump current TIMES_2 -- Doubles charge pump current TIMES_05 -- Halves the charge pump current UNDEFINED -- Undefined Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 896 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_PLL0CTRL0 field descriptions (continued) Field Description 23-22 RSRVD4 Always set to zero (0). 21-20 DIV_SEL TEST MODE FOR FREESCALE USE ONLY. This field is currently NOT supported. 19 RSRVD3 Always set to zero (0). 0x0 0x1 0x2 0x3 DEFAULT -- PLL0 frequency is 480 Mhz LOWER -- Lower the PLL0 fequency from 480MHz to 384Mhz LOWEST -- Lower the PLL0 fequency from 480MHz to 288MHz UNDEFINED -- Undefined 18 0: 8-phase PLL outputs for USB0 PHY are powered down. If set to 1, 8-phase PLL outputs for USB0 PHY EN_USB_CLKS are powered up. Additionally, the utmi clock gate must be deasserted in the UTMI0 phy to enable USB0 operation. If HW_USBPHY_CTRL.ENAUTOSET_USBCLKS of USB0 is set, this bit will be set automatically when USB0 remote wakeup event happens. 17 POWER PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL0 on before using the PLL0 as a clock source. This is the time the PLL0 takes to lock to 480 MHz. If HW_USB_PHY_CTRL_ENAUTO_PWRON_PLL of UTM0 is set, this bit will be set to one (1'b1) automatically when either USB0 or USB1 remote wakeup event happens. Note: The POWER bit must be set to on to ungate the reference xtal to all of the PLLs. RSRVD1 Always set to zero (0). 10.8.2 System PLL0, System/USB0 PLL Control Register 1 (HW_CLKCTRL_PLL0CTRL1) PLL0 Lock Control Register The lock count is driven off of xtal. So after the PLL0 is powered on, the PLL0 Lock should be asserted after 50 us. EXAMPLE HW_CLKCTRL_PLL0CTRL1_WR(BF_CLKCTRL_PLL0CTRL1_FORCE_LOCK(1)); // force pll lock sequence HW_CLKCTRL_PLL0CTRL1_WR(BF_CLKCTRL_PLL0CTRL1_FORCE_LOCK(0)); // clear force pll lock i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 897 Programmable Registers Address: 8004_0000h base + 10h offset = 8004_0010h R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 FORCE_LOCK 31 LOCK Bit W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LOCK_COUNT R W Reset 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_PLL0CTRL1 field descriptions Field 31 LOCK 30 FORCE_LOCK 29-16 RSRVD1 LOCK_COUNT Description PLL0 Lock bit. 1=PLL0 Locked. 0=PLL0 Unlocked. Force the PLL0 Lock sequence to start. 1=Enable Force Lock. This bit is not self clearing. Reserved - Always set to zero (0). Status of the PLL0 lock count. The PLL0 lock bit will assert when the count reaches 0x4B0. The lock count is driven off of xtal, so it should be asserted after 50 us. 10.8.3 System PLL1, USB1 PLL Control Register 0 (HW_CLKCTRL_PLL1CTRL0) HW_CLKCTRL_PLL1CTRL0: 0x020 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 898 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_PLL1CTRL0_SET: 0x024 HW_CLKCTRL_PLL1CTRL0_CLR: 0x028 HW_CLKCTRL_PLL1CTRL0_TOG: 0x02C The PLL1 Control Register 0 programs the 480 MHz PLL1 and the USB1-clock enables. EXAMPLE HW_CLKCTRL_PLL1CTRL2_WR(BF_CLKCTRL_PLL1CTRL0_POWER(1)); PLL1 lock before using it // enable PLL and wait 10 us to let Address: 8004_0000h base + 20h offset = 8004_0020h 29 28 27 26 25 24 22 21 20 19 17 16 RSRV D1 POWER RSRVD4 18 EN_USB_CLKS RSRVD5 23 RSRVD3 R 30 RSRVD6 31 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CLKGATEEMI Bit LFR_SEL CP_SEL DIV_SEL W Reset Bit RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_PLL1CTRL0 field descriptions Field 31 CLKGATEEMI Description TEST MODE FOR FREESCALE USE ONLY. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 899 Programmable Registers HW_CLKCTRL_PLL1CTRL0 field descriptions (continued) Field Description 30 RSRVD6 Always set to zero (0). 29-28 LFR_SEL TEST MODE FOR FREESCALE USE ONLY. Adjusts loop filter resistor. 27-26 RSRVD5 Always set to zero (0). 25-24 CP_SEL TEST MODE FOR FREESCALE USE ONLY. Adjusts charge pump current 23-22 RSRVD4 Always set to zero (0). 21-20 DIV_SEL TEST MODE FOR FREESCALE USE ONLY. This field is currently NOT supported. 19 RSRVD3 Always set to zero (0). 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 DEFAULT -- Default loop filter resistor TIMES_2 -- Doubles the loop filter resistor TIMES_05 -- Halves the loop filter resistor UNDEFINED -- Undefined DEFAULT -- Default charge pump current TIMES_2 -- Doubles charge pump current TIMES_05 -- Halves the charge pump current UNDEFINED -- Undefined DEFAULT -- PLL1 frequency is 480 Mhz LOWER -- Lower the PLL1 fequency from 480MHz to 384Mhz LOWEST -- Lower the PLL1 fequency from 480MHz to 288MHz UNDEFINED -- Undefined 18 0: 8-phase PLL outputs for USB1 PHY are powered down. If set to 1, 8-phase PLL outputs for USB1 PHY EN_USB_CLKS are powered up. Additionally, the utmi clock gate must be deasserted in the UTMI1 phy to enable USB1 operation. If HW_USBPHY_CTRL.ENAUTOSET_USBCLKS of USB1 is set, this bit will be set automatically when USB0 remote wakeup event happens. 17 POWER PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL1 on before using the PLL1 as a clock source. This is the time the PLL1 takes to lock to 480 MHz. If HW_USB_PHY_CTRL_ENAUTO_PWRON_PLL of UTM1 is set, this bit will be set to one (1'b1) automatically when USB1 remote wakeup event happens. Note: The HW_CLKCTRL_PLL0CTRL0_POWER bit must be set to on to ungate the reference xtal to all of the PLLs. RSRVD1 Always set to zero (0). 10.8.4 System PLL1, USB1 PLL Control Register 1 (HW_CLKCTRL_PLL1CTRL1) PLL1 Lock Control Register The lock count is driven off of xtal. So after the PLL1 is powered on, the PLL1 Lock should be asserted after 50 us. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 900 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_PLL1CTRL1_WR(BF_CLKCTRL_PLL1CTRL1_FORCE_LOCK(1)); // force pll lock sequence HW_CLKCTRL_PLL1CTRL1_WR(BF_CLKCTRL_PLL1CTRL1_FORCE_LOCK(0)); // clear force pll lock Address: 8004_0000h base + 30h offset = 8004_0030h R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 FORCE_LOCK 31 LOCK Bit W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LOCK_COUNT R W Reset 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_PLL1CTRL1 field descriptions Field 31 LOCK 30 FORCE_LOCK 29-16 RSRVD1 LOCK_COUNT Description PLL1 Lock bit. 1=PLL1 Locked. 0=PLL1 Unlocked. Force the PLL1 Lock sequence to start. 1=Enable Force Lock. This bit is not self clearing. Reserved - Always set to zero (0). Status of the PLL1 lock count. The PLL1 lock bit will assert when the count reaches 0x4B0. The lock count is driven off of xtal, so it should be asserted after 50 us. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 901 Programmable Registers 10.8.5 System PLL2, Ethernet PLL Control Register 0 (HW_CLKCTRL_PLL2CTRL0) HW_CLKCTRL_PLL2CTRL0: 0x040 HW_CLKCTRL_PLL2CTRL0_SET: 0x044 HW_CLKCTRL_PLL2CTRL0_CLR: 0x048 HW_CLKCTRL_PLL2CTRL0_TOG: 0x04C The System PLL2 Control Register 0 programs the Ethernet PLL. EXAMPLE HW_CLKCTRL_PLL2CTRL0_WR(BF_CLKCTRL_PLL2CTRL0_POWER(1)); PLL lock before using it // enable PLL and wait 10 us to let Address: 8004_0000h base + 40h offset = 8004_0040h 28 27 LFR_SEL 26 25 24 23 22 21 20 19 18 17 16 0 0 0 RSRVD1 CP_SEL POWER 29 HOLD_RING_OFF_B CLKGATE R 30 RSRVD2 31 RSRVD3 Bit W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 902 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_PLL2CTRL0 field descriptions Field 31 CLKGATE Description PLL Clock Gate. If set to 1, the ENET PLL clock is off (power savings). 0: ENET PLL clock is enabled. 30 RSRVD3 Always set to zero (0). 29-28 LFR_SEL TEST MODE FOR FREESCALE USE ONLY. Adjusts loop filter resistor. 27 RSRVD2 Always set to zero (0). 26 HOLD_RING_ OFF_B TEST MODE FOR FREESCALE USE ONLY. Adjust VCO phase. 25-24 CP_SEL TEST MODE FOR FREESCALE USE ONLY. Adjusts charge pump current. 23 POWER PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL on before ungating the PLL and using it as a clock source. This is the time the PLL takes to lock. RSRVD1 Always set to zero (0). 10.8.6 CPU Clock Control Register (HW_CLKCTRL_CPU) The CPUCLK Clock Control Register provides controls for generating the ARM CPUCLK. HW_CLKCTRL_CPU: 0x050 HW_CLKCTRL_CPU_SET: 0x054 HW_CLKCTRL_CPU_CLR: 0x058 HW_CLKCTRL_CPU_TOG: 0x05c Note: Do not write register space when busy bit(s) are high. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 903 Programmable Registers EXAMPLE HW_CLKCTRL_CPU_WR(BF_CLKCTRL_DIV_CPU(12)); // 480 MHz / 12 = 40 MHz Address: 8004_0000h base + 50h offset = 8004_0050h 29 28 27 RSRVD5 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 DIV_XTAL_FRAC_EN RSRVD4 R 30 BUSY_REF_CPU 31 BUSY_REF_XTAL Bit DIV_XTAL RSRVD3 R RSRVD1 DIV_CPU_FRAC_EN Bit INTERRUPT_WAIT Reset RSRVD2 W DIV_CPU W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 904 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_CPU field descriptions Field 31-30 RSRVD5 Description Always set to zero (0). 29 BUSY_REF_ XTAL This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 28 BUSY_REF_ CPU This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 27 RSRVD4 Always set to zero (0). 26 DIV_XTAL_ FRAC_EN 1 = Enable fractional divide. 0 = Enable integer divide. 25-16 DIV_XTAL This field controls the divider connected to the crystal reference clock that drives the CLK_P domain when bypass is selected. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 15-13 RSRVD3 12 INTERRUPT_ WAIT 11 RSRVD2 10 DIV_CPU_ FRAC_EN Always set to zero (0). Gate off CLK_P while waiting for an interrupt. Always set to zero (0). Reserved - Always set to zero (0). 9-6 RSRVD1 Always set to zero (0). DIV_CPU This field controls the divider connected to the ref_cpu reference clock that drives the CLK_P domain when bypass is NOT selected. For changes to this field to take effect, the ref_cpu reference clock must be running. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 10.8.7 AHB, APBH Bus Clock Control Register (HW_CLKCTRL_HBUS) HW_CLKCTRL_HBUS: 0x060 HW_CLKCTRL_HBUS_SET: 0x064 HW_CLKCTRL_HBUS_CLR: 0x068 HW_CLKCTRL_HBUS_TOG: 0x06c i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 905 Programmable Registers This register controls the clock divider that generates the CLK_H, the clock used by the AHB and APBH buses, when HW_CLKCTRL_EMI_SYNC_MODE_EN = 0. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_HBUS_WR(BF_CLKCTRL_HBUS_DIV(2)); // set CLK_H to half the ARM clock (CLK_P) frequency 26 25 24 23 22 21 20 19 APBXDMA_AS_ENABLE TRAFFIC_JAM_AS_ENABLE TRAFFIC_AS_ENABLE CPU_DATA_AS_ENABLE CPU_INSTR_AS_ENABLE ASM_ENABLE AUTO_CLEAR_DIV_ENABLE 0 27 APBHDMA_AS_ENABLE 0 28 ASM_EMIPORT_AS_ENABLE 29 RSRVD2 R 30 PXP_AS_ENABLE 31 ASM_BUSY Bit DCP_AS_ENABLE Address: 8004_0000h base + 60h offset = 8004_0060h 0 0 0 0 0 0 0 0 0 18 17 16 SLOW_DIV W Reset 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 906 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 RSRVD1 DIV_FRAC_EN R DIV W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_HBUS field descriptions Field 31 ASM_BUSY Description This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 30 DCP_AS_ ENABLE Enable auto-slow mode based on DCP activity. 0 = Run at the programmed CLK_H frequency. 29 PXP_AS_ ENABLE Enable auto-slow mode based on PXP activity. 0 = Run at the programmed CLK_H frequency. 28 RSRVD2 Reserved 27 Enable auto-slow mode based on EMI axi0 port activity. 0 = Run at the programmed CLK_HS frequency. ASM_EMIPORT_ AS_ENABLE 26 Enable auto-slow mode based on APBH DMA activity. 0 = Run at the programmed CLK_H frequency. APBHDMA_AS_ ENABLE 25 Enable auto-slow mode based on APBX DMA activity. 0 = Run at the programmed CLK_H frequency. APBXDMA_AS_ ENABLE 24 Enable auto-slow mode when less than three masters are trying to use the AHB. More than three active TRAFFIC_JAM_ masters will engage the default mode. 0 = Run at the programmed CLK_H frequency. AS_ENABLE 23 TRAFFIC_AS_ ENABLE Enable auto-slow mode based on AHB master activity. 0 = Run at the programmed CLK_H frequency. 22 Enable auto-slow mode based on with CPU Data access to AHB. 0 = Run at the programmed CLK_H CPU_DATA_AS_ frequency. ENABLE Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 907 Programmable Registers HW_CLKCTRL_HBUS field descriptions (continued) Field Description 21 CPU_INSTR_ AS_ENABLE Enable auto-slow mode based on with CPU Instruction access to AHB. 0 = Run at the programmed CLK_H frequency. 20 ASM_ENABLE Enable CLK_H auto-slow mode. When this is set, then CLK_H will run at the slow rate until one of the fast mode events has occurred. 19 If this bit is set to one (1'b1), HW_CLKCTRL_HBUS_DIV is cleared to 1 automatically without S/W AUTO_CLEAR_ interaction when wakeup interrupt event happens. This feature is to accelerate the waking up from WaitDIV_ENABLE For-Interrupt Mode. Note: This bit is not self-cleared. This feature is intended for use when the clk_h is reduced to a very low frequency (24KHz, for example). 18-16 SLOW_DIV 15-6 RSRVD1 5 DIV_FRAC_EN DIV Slow mode divide ratio. Sets the ratio of CLK_H fast rate to the slow rate. 0x0 0x1 0x2 0x3 0x4 0x5 BY1 -- Slow mode divide ratio = 1 BY2 -- Slow mode divide ratio = 2 BY4 -- Slow mode divide ratio = 4 BY8 -- Slow mode divide ratio = 8 BY16 -- Slow mode divide ratio = 16 BY32 -- Slow mode divide ratio = 32 Reserved 1 = Enable fractional divide. 0 = Enable integer divide. CLK_P-to-CLK_H divide ratio. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 10.8.8 APBX Clock Control Register (HW_CLKCTRL_XBUS) This register controls the clock divider that generates the CLK_X, the clock used by the APBX bus. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_XBUS_WR(BF_CLKCTRL_XBUS_DIV(4)); // set apbx xbus clock to 1/4 the 24.0MHz crystal clock frequency i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 908 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) Address: 8004_0000h base + 70h offset = 8004_0070h 31 30 29 28 27 26 25 24 BUSY Bit R 23 22 21 20 19 18 17 16 RSRVD1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIV_FRAC_EN Reset AUTO_CLEAR_DIV_ENABLE W 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 DIV 0 1 0 0 0 HW_CLKCTRL_XBUS field descriptions Field 31 BUSY 30-12 RSRVD1 Description This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 909 Programmable Registers HW_CLKCTRL_XBUS field descriptions (continued) Field Description 11 If this bit is set to one (1'b1), HW_CLKCTRL_XBUS_DIV is cleared to 1 automaticlly without S/W AUTO_CLEAR_ interaction when wakeup interrupt event happens. This feature is to accelerate the waking up from WaitDIV_ENABLE For-Interrupt Mode. Note: This bit is not self-cleared. This feature is supposed to used when the clk_x is reduced to very low frequency, for example, 24KHz. 10 DIV_FRAC_EN DIV 1 = Enable fractional divide. 0 = Enable integer divide. This field controls the CLK_X divide ratio. CLK_X is sourced from the 24-MHz XTAL through this divider. Do NOT divide by 0. 10.8.9 XTAL Clock Control Register (HW_CLKCTRL_XTAL) The XTAL control register provides gating control for clocks sourced from the 24-MHz XTAL clock domain. HW_CLKCTRL_XTAL: 0x080 HW_CLKCTRL_XTAL_SET: 0x084 HW_CLKCTRL_XTAL_CLR: 0x088 HW_CLKCTRL_XTAL_TOG: 0x08C This register controls various fixed-rate divider clocks working off the 24.0-MHz crystal clock. EXAMPLE HW_CLKCTRL_XTAL_WR(BF_CLKCTRL_XTAL_UART_CLK_GATE(0)|BF_CLKCTRL_XTAL_DRI_CLK24M_GATE(1)); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 910 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) Bit 31 30 Bit 26 RSRVD2 25 24 23 22 21 20 19 18 17 16 RSRVD1 PWM_CLK24M_GATE Reset 27 RSRVD3 W 28 UART_CLK_GATE R 29 TIMROT_CLK32K_GATE Address: 8004_0000h base + 80h offset = 8004_0080h 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD1 R DIV_UART W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 HW_CLKCTRL_XTAL field descriptions Field 31 UART_CLK_ GATE 30 RSRVD3 Description If set to 1, fixed 24-MHz clock for the UART, CLK_UART, is gated off. Always set to zero (0). 29 If set to 1, fixed 24-MHz clock for the PWM, CLK_PWM24M, is gated off. PWM_CLK24M_ GATE 28-27 RSRVD2 Always set to zero (0). 26 If set to 1, fixed 32-kHz clock for the TIMROT block, CLK_32K, is gated off. TIMROT_ CLK32K_GATE 25-2 RSRVD1 DIV_UART Always set to zero (0). Reserved - Always set to one (1) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 911 Programmable Registers 10.8.10 Synchronous Serial Port0 Clock Control Register (HW_CLKCTRL_SSP0) This register controls the clock divider that generates the clock for the synchronous serial port (SSP0), CLK_SSP0. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_SSP0_WR(BF_CLKCTRL_SSP0_DIV(40)); Address: 8004_0000h base + 90h offset = 8004_0090h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BUSY 31 RSRVD2 Bit 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 CLKGATE R RSRVD1 W Bit RSRVD1 R DIV_FRAC_EN Reset W Reset 0 0 0 0 0 0 0 DIV 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 912 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_SSP0 field descriptions Field Description 31 CLKGATE CLK_SSP0 Gate. If set to 1, CLK_SSP0 is gated off. 0: CLK_SSP0 is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. 30 RSRVD2 Always set to zero (0). 29 BUSY This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 28-10 RSRVD1 Always set to zero (0). 9 DIV_FRAC_EN 1 = Enable fractional divide. 0 = Enable integer divide. DIV The synchronous serial port clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_io) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 10.8.11 Synchronous Serial Port1 Clock Control Register (HW_CLKCTRL_SSP1) This register controls the clock divider that generates the clock for the synchronous serial port (SSP1), CLK_SSP1. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_SSP1_WR(BF_CLKCTRL_SSP1_DIV(40)); 31 CLKGATE R 30 29 BUSY Bit RSRVD2 Address: 8004_0000h base + A0h offset = 8004_00A0h 0 0 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 RSRVD1 W Reset 1 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 913 Programmable Registers 15 Bit 14 13 12 11 10 W Reset 0 0 0 0 8 7 6 5 DIV_FRAC_EN RSRVD1 R 9 0 0 0 4 3 2 1 0 0 0 0 1 DIV 0 0 0 0 0 HW_CLKCTRL_SSP1 field descriptions Field Description 31 CLKGATE CLK_SSP1 Gate. If set to 1, CLK_SSP1 is gated off. 0: CLK_SSP1 is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. 30 RSRVD2 29 BUSY 28-10 RSRVD1 9 DIV_FRAC_EN DIV Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). 1 = Enable fractional divide. 0 = Enable integer divide. The synchronous serial port clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_io) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 10.8.12 Synchronous Serial Port2 Clock Control Register (HW_CLKCTRL_SSP2) This register controls the clock divider that generates the clock for the synchronous serial port (SSP2), CLK_SSP2. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_SSP2_WR(BF_CLKCTRL_SSP2_DIV(40)); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 914 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) Address: 8004_0000h base + B0h offset = 8004_00B0h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BUSY 31 RSRVD2 Bit 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 CLKGATE R RSRVD1 W Reset Bit DIV_FRAC_EN RSRVD1 R W Reset 0 0 0 0 0 0 0 DIV 0 0 0 0 0 HW_CLKCTRL_SSP2 field descriptions Field Description 31 CLKGATE CLK_SSP2 Gate. If set to 1, CLK_SSP2 is gated off. 0: CLK_SSP2 is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. 30 RSRVD2 29 BUSY 28-10 RSRVD1 9 DIV_FRAC_EN DIV Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). 1 = Enable fractional divide. 0 = Enable integer divide. The synchronous serial port clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_io) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 915 Programmable Registers 10.8.13 Synchronous Serial Port3 Clock Control Register (HW_CLKCTRL_SSP3) This register controls the clock divider that generates the clock for the synchronous serial port (SSP3), CLK_SSP3. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_SSP3_WR(BF_CLKCTRL_SSP3_DIV(40)); Address: 8004_0000h base + C0h offset = 8004_00C0h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BUSY 31 RSRVD2 Bit 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 CLKGATE R RSRVD1 W Bit RSRVD1 R DIV_FRAC_EN Reset W Reset 0 0 0 0 0 0 0 DIV 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 916 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_SSP3 field descriptions Field Description 31 CLKGATE CLK_SSP3 Gate. If set to 1, CLK_SSP3 is gated off. 0: CLK_SSP3 is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. 30 RSRVD2 Always set to zero (0). 29 BUSY This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 28-10 RSRVD1 Always set to zero (0). 9 DIV_FRAC_EN 1 = Enable fractional divide. 0 = Enable integer divide. DIV The synchronous serial port clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_io) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 10.8.14 General-Purpose Media Interface Clock Control Register (HW_CLKCTRL_GPMI) This register controls the divider that generates the General-Purpose Media Interface (GPMI) clock, CLK_GPMI. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_GPMI_WR(BF_CLKCTRL_GPMI_DIV(40)); 31 CLKGATE R 30 29 BUSY Bit RSRVD2 Address: 8004_0000h base + D0h offset = 8004_00D0h 0 0 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 RSRVD1 W Reset 1 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 917 Programmable Registers 15 Bit 14 13 12 11 W Reset 0 0 0 9 8 7 6 5 DIV_FRAC_EN RSRVD1 R 10 0 0 0 4 3 2 1 0 0 0 0 0 1 DIV 0 0 0 0 0 HW_CLKCTRL_GPMI field descriptions Field Description 31 CLKGATE CLK_GPMI Gate. If set to 1, CLK_GPMI is gated off. 0: CLK_GPMI is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. 30 RSRVD2 29 BUSY 28-11 RSRVD1 10 DIV_FRAC_EN DIV Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). 1 = Enable fractional divide. 0 = Enable integer divide. The GPMI clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_io) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 10.8.15 SPDIF Clock Control Register (HW_CLKCTRL_SPDIF) This register controls the clock gate on the SPDIF clock, CLK_PCMSPDIF. EXAMPLE HW_CLKCTRL_SPDIF_WR(BF_CLKCTRL_SPDIF_CLKGATE(1)); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 918 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) Address: 8004_0000h base + E0h offset = 8004_00E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD CLKGATE R W Reset Bit 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSRVD R W Reset 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_SPDIF field descriptions Field Description 31 CLKGATE CLK_PCMSPDIF Gate. If set to 1, CLK_PCMSPDIF is gated off. 0: CLK_PCMSPDIF is not gated. When this bit is modified, or when it is high, the SPDIF rate change field should not change its value. The SPDIF rate change field can change ONLY when this clock gate bit field is low. RSRVD Always set to zero (0). 10.8.16 EMI Clock Control Register (HW_CLKCTRL_EMI) This register controls the clock dividers that generate the External Memory Interface (EMI) clock. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_EMI_WR(BF_CLKCTRL_EMI_DIV_XTAL(1)); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 919 Programmable Registers Address: 8004_0000h base + F0h offset = 8004_00F0h 25 24 23 22 21 20 19 18 17 BUSY_DCC_RESYNC 26 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 R RSRVD3 DCC_RESYNC_ENABLE BUSY_SYNC_MODE 27 BUSY_REF_CPU 28 BUSY_REF_EMI 29 BUSY_REF_XTAL 30 SYNC_MODE_EN 31 CLKGATE Bit W Reset Bit RSRVD2 R RSRVD1 DIV_XTAL DIV_EMI W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 HW_CLKCTRL_EMI field descriptions Field 31 CLKGATE 30 SYNC_MODE_ EN Description CLK_EMI crystal divider Gate. If set to 1, the EMI_CLK divider that is sourced by the crystal reference clock, ref_xtal, is gated off. 0: CLK_EMI crystal divider is not gated If set to 1, EMI_CLK is synchronous with the APBH clock. If set to 0, EMI_CLK is aysnchronous. In synchronous operation, the EMI clock dividers control both EMI_CLK and APBH clock. Both xtal and ref_cpu must be active to switch between asynchronous/synchronous operation. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 920 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_EMI field descriptions (continued) Field 29 BUSY_REF_ XTAL Description This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. This bit is valid when HW_CLKCTRL_EMI_SYNC_MODE_EN = 0. 28 This read-only bit field returns a one when the clock divider is busy transfering a new divider value across BUSY_REF_EMI clock domains. 27 BUSY_REF_ CPU This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. This bit is valid when HW_CLKCTRL_EMI_SYNC_MODE_EN = 1. 26 BUSY_SYNC_ MODE This read-only bit field returns a one when there is a change in HW_CLKCTRL_EMI_SYNCE_MODE_EN or when there is a change in HW_CLKCTRL_CLKSEQ_BYPASS_CPU and HW_CLKCTRL_EMI_SYNCE_MODE_EN is set. When this bit returns a one, do not change the CPU or EMI divider values. 25-18 RSRVD3 17 BUSY_DCC_ RESYNC Always set to zero (0). Reserved. 16 Reserved. DCC_RESYNC_ ENABLE 15-12 RSRVD2 11-8 DIV_XTAL Always set to zero (0). This field controls the divider connected to the crystal reference clock, ref_xtal, that drives the CLK_EMI domain when bypass IS selected. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 7-6 RSRVD1 Always set to zero (0). DIV_EMI This field controls the divider connected to the ref_emi reference clock that drives the CLK_EMI domain when bypass IS NOT selected. For changes to this field to take effect, the ref_emi reference clock must be running. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 10.8.17 SAIF0 Clock Control Register (HW_CLKCTRL_SAIF0) This register controls the divider that generates the Serial Audio Interface (SAIF0) clock. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_SAIF0_WR(BF_CLKCTRL_SAIF0_DIV(40)); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 921 Programmable Registers Address: 8004_0000h base + 100h offset = 8004_0100h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BUSY 31 RSRVD2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 CLKGATE R RSRVD1 DIV_FRAC_EN Bit W Reset Bit R DIV W Reset 0 0 0 0 0 0 0 0 HW_CLKCTRL_SAIF0 field descriptions Field 31 CLKGATE 30 RSRVD2 29 BUSY 28-17 RSRVD1 16 DIV_FRAC_EN DIV Description CLK_SAIF0 Gate. If set to 1, CLK_SAIF0 is gated off. 0: CLK_SAIF0 is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). Always set to one (1) for functional operation. - Notice this is not the reset value. The SAIF0 clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_pll) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. ref_pll should be selected for functional operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 922 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) 10.8.18 SAIF1 Clock Control Register (HW_CLKCTRL_SAIF1) This register controls the divider that generates the Serial Audio Interface (SAIF1) clock. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_SAIF1_WR(BF_CLKCTRL_SAIF1_DIV(40)); Address: 8004_0000h base + 110h offset = 8004_0110h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BUSY 31 RSRVD2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 CLKGATE R RSRVD1 DIV_FRAC_EN Bit W Reset Bit R DIV W Reset 0 0 0 0 0 0 0 0 HW_CLKCTRL_SAIF1 field descriptions Field 31 CLKGATE Description CLK_SAIF1 Gate. If set to 1, CLK_SAIF1 is gated off. 0: CLK_SAIF1 is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 923 Programmable Registers HW_CLKCTRL_SAIF1 field descriptions (continued) Field Description 30 RSRVD2 Always set to zero (0). 29 BUSY This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. 28-17 RSRVD1 Always set to zero (0). 16 DIV_FRAC_EN Always set to one (1) for functional operation - Notice this is not the reset value. DIV The SAIF1 clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_pll) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. ref_pll should be selected for functional operation. 10.8.19 CLK_DIS_LCDIF Clock Control Register (HW_CLKCTRL_DIS_LCDIF) This register controls the divider that generates the CLK_DIS_LCDIF clock. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_DIS_LCDIF_WR(BF_CLKCTRL_DIS_LCDIF_DIV(40)); 31 CLKGATE R 30 29 BUSY Bit RSRVD2 Address: 8004_0000h base + 120h offset = 8004_0120h 0 0 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 RSRVD1 W Reset 1 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 924 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) 14 RSRVD1 R W Reset 0 0 13 12 11 10 9 8 7 DIV_FRAC_EN 15 Bit 0 6 5 4 3 2 1 0 0 0 0 0 0 1 DIV 0 0 0 0 0 0 0 HW_CLKCTRL_DIS_LCDIF field descriptions Field 31 CLKGATE 30 RSRVD2 29 BUSY 28-14 RSRVD1 13 DIV_FRAC_EN DIV Description CLK_DIS_LCDIF Gate. If set to 1, CLK_DIS_LCDIF is gated off. 0: CLK_DIS_LCDIF is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). 1 = Enable fractional divide. 0 = Enable integer divide. The DIS_LCDIF clock frequency is determined by dividing the reference clock, ref_xtal or ref_pix, by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. Do not divide by more than 255. 10.8.20 ETM Clock Control Register (HW_CLKCTRL_ETM) This register controls the clock divider that generates the clock for the ETM, CLK_ETM. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_ETM_WR(BF_CLKCTRL_ETM_DIV(4)); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 925 Programmable Registers Address: 8004_0000h base + 130h offset = 8004_0130h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BUSY 31 RSRVD2 Bit 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 CLKGATE R RSRVD1 W Reset Bit DIV_FRAC_EN RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 DIV 0 0 0 0 HW_CLKCTRL_ETM field descriptions Field 31 CLKGATE 30 RSRVD2 29 BUSY 28-8 RSRVD1 7 DIV_FRAC_EN DIV Description CLK_ETM Gate. If set to 1, CLK_ETM is gated off. 0: CLK_ETM is not gated. When this bit is modified, or when it is high, the DIV field should not change its value. The DIV field can change ONLY when this clock gate bit field is low. Always set to zero (0). This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. Always set to zero (0). 1 = Enable fractional divide. 0 = Enable integer divide. The ETM clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_cpu) by the value in this bit field. This field can be programmed with a new value only when CLKGATE = 0. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 926 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) 10.8.21 ENET Clock Control Register (HW_CLKCTRL_ENET) This register provides control for ETHERNET clock generation EXAMPLE HW_CLKCTRL_ENET_WR(BF_CLKCTRL_ENET_SLEEP(1)); BUSY_TIME 26 25 24 23 22 21 20 19 18 17 16 RESET_BY_SW 27 RESET_BY_SW_CHIP 28 CLK_OUT_EN 29 RSRVD1 30 DISABLE 31 SLEEP Bit STATUS Address: 8004_0000h base + 140h offset = 8004_0140h 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R DIV_TIME TIME_SEL W Reset Bit RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 927 Programmable Registers HW_CLKCTRL_ENET field descriptions Field 31 SLEEP Description CLOCK Gate. If set to 1, put Ethernet block in sleep mode. CLK_H_MAC0(1), CLK_H_MAC0(1)_S, and CLK_ENET0(1)_TX are gated off. Ethernet can be wakeup remotely in sleep mode 0: Resume Ethernet block to normal operation. CLK_H_MAC0(1), CLK_H_MAC0(1)_S, and CLK_ENET_TX are not gated. . 30 DISABLE This bit is used to gate off all Ethernet clocks when Ethernet is disabled in some use case. If set to 1, gate off all of the Ethernet clocks. Ethernet can not be wakeup remotely when Ethernet is disabled. 0: Do not gate off Ethernet's clocks. 29 STATUS This read-only bit indicates the status of Ehternet module. 1'b1: Ethernet is in SLEEP or DISABLE mode. 1'b0: Ethernet is in NORMAL mode. 28 RSRVD1 Always set to zero (0). 27 BUSY_TIME 26-21 DIV_TIME This read-only bit field returns a one when the clock divider is busy transfering a new divider value across clock domains. This field controls the divider that drives the CLK_ENET_TIME (1588 timer) domain. For changes to this field to take effect, the reference clock must be running. NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0. 20-19 TIME_SEL This field selects clock that drives the Ethernet 1588 timer between the xtal, ref_pll and enet_rmii_clk_in sources. 0x0 0x1 0x2 0x3 XTAL -- select xtal source PLL -- select ref_pll source RMII_CLK -- select enet_rmii_clk_in source which is from PAD UNDEFINED -- Undefined 18 CLK_OUT_EN This bit controls the ENET_CLK PAD direction. 1: Enable the output; 0: Disable the output. NOTE: This bit must be configured before ENET PLL is enabled. 17 RESET_BY_ SW_CHIP Setting this bit to a logic one will enable the function that ENET SWITCH can be reset by SW chip reset (HW_CLKCTRL_RESET.CHIP, or watchdog_reset when HW_CLKCTRL_RESET.WDOG_POR_DISABLE is set to 1'b1). This bit's reset value reflects OTP fuse ENET_SWITCH_RESET_BY_SW_CHIP. 16 Setting this bit to a logic one will enable the function that ENET SWITCH can be reset by all software reset RESET_BY_SW (Either HW_CLKCTRL_RESET.CHIP or HW_CLKCTRL_RESET.DIG). This bit's reset value reflects OTP fuse ENET_SWITCH_RESET_BY_SW. RSRVD0 Always set to zero (0). 10.8.22 HSADC Clock Control Register (HW_CLKCTRL_HSADC) This register controls the clock dividers that generate the High Speed ADC (HSADC) clock. Note: Do not write register space when busy bit(s) are high. EXAMPLE HW_CLKCTRL_HSADC_WR(BF_CLKCTRL_HSADC_CLKGATE(1)); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 928 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) Address: 8004_0000h base + 150h offset = 8004_0150h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 RESETB R RSRVD2 Bit FREQDIV W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_HSADC field descriptions Field Description 31 RSRVD2 Always set to zero (0). 30 RESETB 0: Reset the HSADC Divider. 1: Divider normal work. 29-28 FREQDIV This field selects HSADC Divider's divide factor. RSRVD1 Always set to zero (0). 00: Divide by 9; 01: Divide by 18; 10: Divide by 36; 11: Divide by 72 10.8.23 FLEXCAN Clock Control Register (HW_CLKCTRL_FLEXCAN) The FLEXCAN control register provides control for Flexcan0 and Flexcan1 clock generation. EXAMPLE HW_CLKCTRL_FLEXCAN_WR(BF_CLKCTRL_FLEXCAN_STOP_CAN0(1)); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 929 Programmable Registers Address: 8004_0000h base + 160h offset = 8004_0160h 27 26 25 24 23 22 CAN1_STATUS 28 STOP_CAN1 29 CAN0_STATUS R 30 STOP_CAN0 31 RSRVD2 Bit 21 20 19 18 17 16 RSRVD1 W Reset Bit 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_FLEXCAN field descriptions Field 31 RSRVD2 30 STOP_CAN0 Description Always set to zero (0). If this bit is set to one (1'b1), the FLEXCAN0 will be stopped and all the clocks to FLEXCAN0 are gated off. 29 This read-only bit indicates FLEXCAN0 status. 1'b1: FLEXCAN0 is in STOP mode. 1'b0: FLEXCAN0 is in CAN0_STATUS NORMAL Mode. 28 STOP_CAN1 If this bit is set to one (1'b1), the FLEXCAN1 will be stopped and all the clocks to FLEXCAN1 are gated off. 27 This read-only bit indicates FLEXCAN1 status. 1'b1: FLEXCAN1 is in STOP mode. 1'b0: FLEXCAN1 is in CAN1_STATUS NORMAL Mode. RSRVD1 Always set to zero (0). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 930 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) 10.8.24 Fractional Clock Control Register 0 (HW_CLKCTRL_FRAC0) The FRAC0 control register provides control for PFD clock generation. HW_CLKCTRL_FRAC0: 0x1B0 HW_CLKCTRL_FRAC0_SET: 0x1B4 HW_CLKCTRL_FRAC0_CLR: 0x1B8 HW_CLKCTRL_FRAC0_TOG: 0x1BC This register controls the 9-phase fractional clock dividers. The fractional clock frequencies are a product of the values in these registers. NOTE: This register can only be addressed by byte instructions. Addressing word or half-word are not allowed. EXAMPLE *((u8 *)(HW_CLKCTRL_FRAC0_ADDR + 1)) = 30; Address: 8004_0000h base + 1B0h offset = 8004_01B0h 29 28 27 26 25 24 23 IO0FRAC 22 21 20 19 18 17 16 1 0 IO1_STABLE CLKGATEIO0 R 30 CLKGATEIO1 31 IO0_STABLE Bit IO1FRAC W Reset 1 0 0 1 0 0 1 0 1 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 931 Programmable Registers 12 11 10 9 8 7 EMIFRAC 6 5 4 3 2 1 0 1 0 CPU_STABLE 13 CLKGATECPU CLKGATEEMI R 14 EMI_STABLE 15 Bit CPUFRAC W Reset 1 0 0 1 0 0 1 0 1 0 0 1 0 0 HW_CLKCTRL_FRAC0 field descriptions Field Description 31 CLKGATEIO0 IO0 Clock Gate. If set to 1, the IO0 fractional divider clock (reference PLL0 ref_io0) is off (power savings). 0: IO0 fractional divider clock is enabled. 30 IO0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. 29-24 IO0FRAC This field controls the IO0 clocks fractional divider. The resulting frequency shall be 480 * (18/IO0FRAC) where IO0FRAC = 18-35. 23 CLKGATEIO1 IO1 Clock Gate. If set to 1, the IO1 fractional divider clock (reference PLL0 ref_io1) is off (power savings). 0: IO1 fractional divider clock is enabled. 22 IO1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. 21-16 IO1FRAC This field controls the IO1 clocks fractional divider. The resulting frequency shall be 480 * (18/IO1FRAC) where IO1FRAC = 18-35. 15 CLKGATEEMI EMI Clock Gate. If set to 1, the EMI fractional divider clock (reference PLL0 ref_emi) is off (power savings). 0: EMI fractional divider clock is enabled. 14 EMI_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divide should become stable quickly enough that this field will never need to be used by either device driver or application code. This value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. 13-8 EMIFRAC This field controls the EMI clock fractional divider. The resulting frequency shall be 480 * (18/EMIFRAC) where EMIFRAC = 18-35. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 932 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_FRAC0 field descriptions (continued) Field Description 7 CLKGATECPU CPU Clock Gate. If set to 1, the CPU fractional divider clock (reference PLL0 ref_cpu) is off (power savings). 0: CPU fractional divider clock is enabled. 6 CPU_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divide should become stable quickly enough that this field will never need to be used by either device driver or application code. The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. CPUFRAC This field controls the CPU clock fractional divider. The resulting frequency shall be 480 * (18/CPUFRAC) where CPUFRAC = 18-35. 10.8.25 Fractional Clock Control Register 1 (HW_CLKCTRL_FRAC1) The FRAC1 control register provides control for PFD clock generation. HW_CLKCTRL_FRAC1: 0x1C0 HW_CLKCTRL_FRAC1_SET: 0x1C4 HW_CLKCTRL_FRAC1_CLR: 0x1C8 HW_CLKCTRL_FRAC1_TOG: 0x1CC This register controls the 9-phase fractional clock dividers. The fractional clock frequencies are a product of the values in these registers. NOTE: This register can only be addressed by byte instructions. Addressing word or half-word are not allowed. EXAMPLE *((u8 *)(HW_CLKCTRL_FRAC1_ADDR + 1)) = 30; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 933 Programmable Registers Address: 8004_0000h base + 1C0h offset = 8004_01C0h 31 30 29 28 27 26 25 24 23 RSRVD2 CLKGATEGPMI R 22 21 20 19 18 17 16 GPMI_STABLE Bit GPMIFRAC W 0 0 0 0 0 0 1 0 0 1 0 0 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 CLKGATEHSADC R HSADCFRAC PIX_STABLE 0 CLKGATEPIX Bit 0 HSADC_STABLE Reset PIXFRAC W Reset 1 0 0 1 0 0 1 0 1 0 0 1 0 0 HW_CLKCTRL_FRAC1 field descriptions Field 31-24 RSRVD2 Description Always set to zero (0). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 934 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_FRAC1 field descriptions (continued) Field Description 23 CLKGATEGPMI GPMI Clock Gate. If set to 1, the GPMI fractional divider clock (reference PLL0 ref_gpmi) is off (power savings). 0: GPMI fractional divider clock is enabled. 22 GPMI_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. 21-16 GPMIFRAC This field controls the GPMI clock fractional divider. The resulting frequency shall be 480 * (18/ GPMIFRAC) where GPMIFRAC = 18-35. 15 HSADC Clock Gate. If set to 1, the HSADC fractional divider clock (reference PLL0 ref_adc) is off (power CLKGATEHSADC savings). 0: HSADC fractional divider clock is enabled. 14 This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become HSADC_STABLE stable quickly enough that this field will never need to be used by either device driver or application code. The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. 13-8 HSADCFRAC This field controls the HSADC clock fractional divider. The resulting frequency shall be 480 * (18/ HSADCFRAC) where HSADCFRAC = 18-35. 7 CLKGATEPIX PIX Clock Gate. If set to 1, the PIX fractional divider clock (reference PLL0 ref_pix) is off (power savings). 0: PIX fractional divider clock is enabled. 6 PIX_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code. The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will not invert when the fractional divider is taken out of or placed into clock-gated state. PIXFRAC This field controls the PIX clock fractional divider. The resulting frequency shall be 480 * (18/PIXFRAC) where PIXFRAC = 18-35. 10.8.26 Clock Frequency Sequence Control Register (HW_CLKCTRL_CLKSEQ) The CLKSEQ control register provides control for switching between XTAL and PLL clock generation. HW_CLKCTRL_CLKSEQ: 0x1D0 HW_CLKCTRL_CLKSEQ_SET: 0x1D4 HW_CLKCTRL_CLKSEQ_CLR: 0x1D8 HW_CLKCTRL_CLKSEQ_TOG: 0x1DC This register controls the selection of clock sources (ref_xtal or ref_*) for various clock dividers. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 935 Programmable Registers HW_CLKCTRL_CLKSEQ_WR(BF_CLKCTRL_CLKSEQ_BYPASS_SAIF0(1)); Address: 8004_0000h base + 1D0h offset = 8004_01D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RSRVD0 16 RSRVD1 BYPASS_CPU R 17 0 0 0 0 0 0 0 1 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYPASS_SSP3 BYPASS_SSP2 BYPASS_SSP1 BYPASS_SSP0 BYPASS_GPMI BYPASS_SAIF1 BYPASS_SAIF0 R 0 BYPASS_EMI Bit 0 0 1 1 1 1 1 1 1 1 1 1 RSRV D1 W Reset RSRVD2 BYPASS_DIS_LCDIF Reset BYPASS_ETM W 1 0 0 0 0 HW_CLKCTRL_CLKSEQ field descriptions Field 31-19 RSRVD0 18 BYPASS_CPU 17-15 RSRVD1 14 BYPASS_DIS_ LCDIF Description Always set to zero (0). CPU bypsss select. 1 = Select ref_xtal path to generate the CPU clock domain. 0 = Select ref_cpu path to generate the CPU clock domain. PLL0 and 9-phase fractional divider must already be configured when changing from bypass mode. Always set to zero (0). LCDIF bypsss select. 1 = Select ref_xtal path to generate the LCDIF clock domain. 0 = Select ref_pix path to generate the LCDIF clock domain. PLL0 and 9-phase fractional divider must already be configured when changing from bypass mode. 0x1 0x0 13-9 RSRVD2 BYPASS -- select xtal source, bypass mode PFD -- select PFD, ref_pix Always set to zero (0). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 936 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_CLKSEQ field descriptions (continued) Field Description 8 BYPASS_ETM ETM bypass select. 1 = Select ref_xtal path to generate the ETM clock domain. 0 = Select ref_cpu path to generate the ETM clock domain. PLL0 and 9-phase fractional divider must already be configured when this bit is cleared. 7 BYPASS_EMI EMI bypass select. 1 = Select ref_xtal path to generate the EMI clock domain. 0 = Select ref_emi path to generate the EMI clock domain. PLL0 and 9-phase fractional divider must already be configured when this bit is cleared. 6 SSP3 bypass select. 1 = Select ref_xtal path to generate the SSP3 clock domain. 0 = Select ref_io1 path BYPASS_SSP3 to generate the SSP3 clock domain. PLL0 and 9-phase fractional divider must already be configured when this bit is cleared. 5 SSP2 bypass select. 1 = Select ref_xtal path to generate the SSP2 clock domain. 0 = Select ref_io1 path BYPASS_SSP2 to generate the SSP2 clock domain. PLL0 and 9-phase fractional divider must already be configured when this bit is cleared. 4 SSP1 bypass select. 1 = Select ref_xtal path to generate the SSP1 clock domain. 0 = Select ref_io0 path BYPASS_SSP1 to generate the SSP1 clock domain. PLL0 and 9-phase fractional divider must already be configured when this bit is cleared. 3 SSP0 bypass select. 1 = Select ref_xtal path to generate the SSP0 clock domain. 0 = Select ref_io0 path BYPASS_SSP0 to generate the SSP0 clock domain. PLL0 and 9-phase fractional divider must already be configured when this bit is cleared. 2 GPMI bypass select. 1 = Select ref_xtal path to generate the GPMI clock domain. 0 = Select ref_gpmi path BYPASS_GPMI to generate the GPMI clock domain. PLL0 and 9-phase fractional divider must already be configured when this bit is cleared. 1 Always set to zero (0) for functional operation. Bypass is only used for POR and SAIF1 divider BYPASS_SAIF1 configuration. 0 Always set to zero (0) for functional operation Bypass is only used for POR and SAIF0 divider BYPASS_SAIF0 configuration. 10.8.27 System Reset Control Register (HW_CLKCTRL_RESET) The RESET control register provides control for software reset and enable/disable reset control in analog. EXAMPLE HW_CLKCTRL_RESET_WR(BF_CLKCTRL_RESET_ALL(1)); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 937 Programmable Registers Address: 8004_0000h base + 1E0h offset = 8004_01E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 THERMAL_RESET_ENABLE THERMAL_RESET_DEFAULT Bit 0 EXTERNAL_RESET_ENABLE Reset WDOG_POR_DISABLE W CHIP DIG 0 1 0 0 1 0 RSRVD R W Reset 0 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_RESET field descriptions Field 31-6 RSRVD 5 WDOG_POR_ DISABLE Description Always set to zero (0). Analog Reset Control. Setting this bit to a logic one will disable the function that watchdog perform a POR. Then watchdog will function same with software reset HW_CLKCTRL_RESET.CHIP. Setting this bit to a logic zero, watchdog_reset will trigger a POR. This bit's reset value reflects OTP fuse WDOG_PERFORM_POR. 4 Analog Reset Control. Setting this bit to a logic one will enable the external pin reset control logic. EXTERNAL_ RESET_ENABLE 3 Analog Reset Control. Setting this bit to a logic one will enable the thermal reset control logic. THERMAL_ RESET_ENABLE Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 938 Freescale Semiconductor, Inc. Chapter 10 Clock Generation and Control (CLKCTRL) HW_CLKCTRL_RESET field descriptions (continued) Field Description 2 THERMAL_ RESET_ DEFAULT Reserved. 1 CHIP Software reset. Setting this bit to a logic one will reset the ENTIRE chip, no exceptions. This bit will also be reset after the full chip reset cycle completes. 0 DIG Software reset. Setting this bit to a logic one will reset the digital sections of the chip. The DCDC and power module will not be reset. This bit will also be reset after the reset cycle completes. 10.8.28 ClkCtrl Status (HW_CLKCTRL_STATUS) The STATUS control register provides read only status of the CPU frequecy limits. EXAMPLE HW_CLKCTRL_STATUS_RD(BF_CLKCTRL_STATUS_CPU_LIMIT()); Address: 8004_0000h base + 1F0h offset = 8004_01F0h Bit 31 R 30 29 28 27 26 25 24 23 CPU_LIMIT 22 21 20 19 18 17 16 RSRVD W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSRVD R W Reset 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_STATUS field descriptions Field 31-30 CPU_LIMIT RSRVD Description CPU Limiting. 00: full cpu frequency, 01: limit cpu frequency to 455 MHz, 10: limit cpu frequency to 411 MHz, 11: limit cpu frequency to 360 MHz Always set to zero (0). 10.8.29 ClkCtrl Version (HW_CLKCTRL_VERSION) This register indicates the RTL version in use. EXAMPLE HW_CLKCTRL_VERSION_RD(BF_CLKCTRL_VERSION_MAJOR()); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 939 Programmable Registers Address: 8004_0000h base + 200h offset = 8004_0200h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 HW_CLKCTRL_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 940 Freescale Semiconductor, Inc. Chapter 11 Power Supply 11.1 Overview This chapter describes the power supply subsystem provided on the i.MX28. It includes sections on the DC-DC converter, linear regulators, PSWITCH pin functions, battery monitor and charger, silicon speed sensor, thermal-overload protection circuit, bandgap reference and programmable registers. The i.MX28 integrates a comprehensive power supply subsystem, including the following features: * One integrated DC-DC converter that supports Li-Ion batteries. * Four linear regulators directly power the supply rails from 5 V. * Linear battery charger for Li-Ion cells. * Battery voltage and brownout detection monitoring for VDDD, VDDA, VDDIO, VDDMEM, VDD4P2 and 5V supplies. * Integrated current limiter from 5 V power source. * Reset controller. * System monitors for temperature and speed. * Generates USB-Host 5V from Li-Ion battery (using PWM). * Support for on-the-fly transitioning between 5V and battery power. * VDD4P2, a nominal 4.2 V supply, is available when the i.MX28 is connected to a 5 V source and allows the DCDC to run from a 5 V source with a depleted batteryintegrated current limiter from 5 V power source. * The 4.2 V regulated output also allows for programmable current limits: a. Battery Charge current + DCDC input current < the 5 V current limit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 941 Overview b. DCDC input current (which ultimately provides current to the on-chip and offchip loads) as the priority and battery charge current will be automatically reduced if the 5 V current limit is reached. The i.MX28 power supply is designed to offer maximum flexibility and performance, while minimizing external component requirements. Figure 11-1 shows a functional block diagram of the power supply components including switching converters, five regulators, battery charge support, as well as battery monitoring, supply brownout detection, and silicon process/temperature sensors. This figure can be used to understand which register and status bits relate to which subsystems, but it is not intended to be a complete architecture description. X VDD5V Current Limiter VDDIO HW_POWER_STS_VDDIO_BO VBG VDD4P2 HW_POWER_STS_VDD4P2_BO Battery Charge IOFB VBG X X X VDDIO X VDDA VDD4P2 Battery VDDA HW_POWER_STS_VDDA_BO VBG AFB VDDMEM DCDC VBG VDDD HW_POWER_STS_VDDD_BO IOFB, AFB, DFB VDDMEM VBG HW_POWER_CTRL_DC_OK_IRQ X DFB X VDDD Notes: Status Bits are in Italic Figure 11-1. Power Supply Block Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 942 Freescale Semiconductor, Inc. Chapter 11 Power Supply 11.2 DC-DC Converters The DC-DC converters efficiently scale battery voltage (or a regulated 4.2 V derived from a 5 V source) to the required supply voltages. The DC-DC converters include several advanced features: * Single inductor architecture * Programmable output voltages * Programmable brownout detection thresholds * Pulse frequency modulation (PFM) mode for low-current load operation 11.2.1 DC-DC Operation The i.MX28 DC-DC converter enables a low-power system and features programmable output voltages and control modes. Most products adjust VDDD dynamically to provide the minimum voltage required for proper system operation. VDDIO and VDDA are typically set once during system initialization and not changed during operation. 11.2.1.1 Brownout/Error Detection The power subsystem has several mechanisms active by default that safely return the device to off state if any one of the following errors or brownouts occur: * The crystal oscillator frequency is detected below a certain threshold--This threshold is process-and voltage-sensitive, but will always be between 100 KHz and 2 MHz. This feature can be disabled in DISABLE_XTALOK field in HW_RTC_PERSISTENT0 register. * The battery voltage falls below the battery brownout level (field BRWNOUT_LVL in HW_POWER_BATTMONITOR)--This feature is disabled by clearing PWDN_BATTBRNOUT in the same register. * 5 V is detected, then removed--This feature is disabled by clearing HW_POWER_5VCTRL_PWDN_5VBRNOUT. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 943 DC-DC Converters All three mechanisms are active by default to ensure that the device always has a valid transition to a known state in case the power source is unexpectedly removed before the software has completed the system configuration. Software will typically disable the functionality of PWDN_5VBRNOUT and PWDN_BATTBRNOUT after system configuration is complete, as shown in Figure 11-2. System configuration generally includes setting up brownout detection thresholds on the supply voltages, battery, and so on to obtain the desired system operation as the battery or power source is depleted or removed. Typically, each output target voltage is set to some voltage margin above the minimum operating level through the TRG field in HW_POWER_VDDDCTRL, HW_POWER_VDDACTRL, HW_POWER_VDDIOCTRL, and HW_POWER_VDDMEMCTRL registers. The brownout detection threshold is also set through the BO_OFFSET field in same three registers. The BO_OFFSET field determines how far the brownout voltage is below the output target voltage for each supply and might typically be set 75-100 mV below the target voltage. If the voltage drops to the brownout detector's level, then it optionally triggers a CPU Fast Interrupt (FIQ). The CPU can then alleviate the problem and/or shut down the system elegantly. See i.MX28 Datasheet for suggested voltage settings for the supply and brownout targets for different operating frequencies. To eliminate false detection, the brownout circuit filters transient noise above 1 MHz. Any system with an i.MX28 should include at least 33 F of decoupling capacitance on VDDIO, VDDA and VDDD power rails. The capacitors should be arranged to filter supply noise in 1 MHz and higher frequencies. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 944 Freescale Semiconductor, Inc. Chapter 11 Power Supply Base State Defaults: HW_POWER_5VCTRL_PWDN_5VBRNOUT=1 HW_POWER_BATTMONITOR_PWDN_BATTBRNOUT=1 Unplug = (On falling edge of HW_POWER_STS_VDD5V_GT_VDDIO) & (HW_POWER_5VCTRL_PWDN_5VBRNOUT=1) Unplug=1 Brownout=1 Off Brownout = (HW_POWER_STS_VDD5V_GT_VDDIO=0) & (HW_POWER_BATTMONITOR_PWDN _BATTBRNOUT=1) & (HW_POWER_STS_BATT_BO=1) (PSWITCH or RTC wakeup or HW_POWER_STS_VDD5V_GT_VDDIO=1) ROM Bist HW_POWER_STS_VDD5V_GT_VDDIO=0 Enable LRADC to measure battery and put value into HW_POWER_BATTMONITOR_BATT_VAL. Set up battery brownout code. HW_POWER_BATTMONITOR_EN _BATADJ=1 HW_POWER_STS_ VDD5V_GT_VDDIO=1 (any instance) Do you want to reset or continue on a future plugin? Reset 5V Device Plugin (interrupt-driven event) Do you want to reset or continue on a future unplug? Continue Set up IRQ for VDDIO5V plug in. HW_POWER_CTRL_POLARITY _VDD5V_GT_VDDIO=1 HW_POWER_CTRL_ENIRQ _VDD5V_GT_VDDIO=1 HW_POWER_5VCTRL_PWDN _5VBRNOUT=1 HW_POWER_STS_VDD5V_GT_VDDIO=1 HW_POWER_5VCTRL _ENABLE_DCDC=1 HW_POWER_5VCTRL _PWDN_5VBRNOUT=0 Reset Continue Configure* 5V unplug detection. HW_POWER_5VCTRL_DCDC_XFER=1 HW_POWER_5VCTRL_PWDN_5VBRNOUT=0 HW_POWER_BATTMONITOR_PWDN _BATTBRNOUT=1 HW_POWER_CTRL_ENIRQBATT_BO=1 HW_POWER_BATTMONITOR_PWDN _BATTBRNOUT=0 HW_POWER_5VCTRL _PWDN_5VBRNOUT=1 Application Figure 11-2. Brownout Detection Flowchart i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 945 DC-DC Converters 11.2.1.2 DC-DC Extended Battery Life Features The DC-DC converter has several other power-reducing programmable modes that are useful for maximizing battery life: * Li-Ion Buck/Boost--The Li-Ion battery configuration supports buck/boost operation, which means that a VDDIO voltage can be supported which is higher than the input Li-Ion battery voltage. This is important to maximize the battery life in all applications, but is crucial in hard drives that have large transient current requirements. * Transient Loading Optimizations--Several new incremental improvements have been made to the control architecture of the switching converters. At this time, Freescale recommends setting the following bits through software in HW_POWER_LOOPCTRL to obtain maximum efficiency and minimum supply ripple: TOGGLE_DIF, EN_CM_HYST and EN_RCSCALE=0x1. Also, set HW_POWER_BATTMONITOR_EN_BATADJ. The complete settings to optimize transient loading will be dependent on the application, component selection and board layout. * Pulse Frequency Modulation (PFM)--PFM, also known as pulse-skipping mode, is used to reduce power consumed by the DC-DC converter when the voltage outputs are lightly-loaded at a cost of higher transient noise. The DC-DC converter can be separately placed in PFM mode through the EN_DC_PFM bit in HW_POWER_MINPWR. * DC-DC Switching Frequency--The standard DC-DC switching frequency is 1.5 MHz, which provides a good mix of efficiency and power output. The frequency can be reduced to 750 KHz to reduce operating current in some light load situations through DC_HALFCLK in HW_POWER_MINPWR. The DC-DC converter can also be programmed to a frequency that is based on PLL using the SEL_PLLCLK and FREQSEL fields in the HW_POWER_MISC register. * DC-DC Converter Power Down--If the system is to operate from linear regulators or an external power supply, then the internal DC-DC converters can be powered down through DC_STOPCLK in HW_POWER_MINPWR. This bit is not intended to power down the whole system. Use the HW_POWER_RESET bits to power the system off. The DC-DC converter can be programmed to run off of the battery or the 4.2 V regulated voltage supply. It can be set up to opportunistically draw power from either source. This allows the system to draw up to the USB current limit from the 5 V supply and take the balance of the required power from the battery. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 946 Freescale Semiconductor, Inc. Chapter 11 Power Supply 11.3 Linear Regulators The i.MX28 integrates four linear regulators that can be used to directly power the supply rails when 5 V is present. All of these regulators have an output impedance of approximately one-quarter ohm. This means that the measured output voltage will be slightly dependent on the current consumed on each supply. Architecturally, one regulator generates VDDIO from the VDD5V pin, one generates VDDA from VDDIO, one generates VDDMEM from VDDA, and the other generates VDDD from the VDDA supply. Therefore, all of the current is supplied by the VDD5V->VDDIO regulator. In addition, the i.MX28 integrates a 4.2 V regulator which enables the DC-DC converter to run off the power supplied by 5 V. This allows the DC-DC converter operation when 5 V is present and the battery is exhausted. In addition, the path can provide better power consumption as compared to the other linear regulator generated supplies. A current limiter is implemented in a series with the 4.2 V regulator and the battery supply. The intent is to limit the Ibattery plus I4P2 to be less than Ilimit. The 4.2 V regulator has priority on the current and will dynamically reduce the battery charge current in order to preserve the Ilimit and the regulated 4.2 V. It should also be noted that the VDD5V voltage can dynamically change as the product is plugged into a USB port or other 5-V supply. The i.MX28 is programmable to provide a variety of behaviors when the VDD5V supply becomes valid or invalid, as well as to support operation through USB or external power. 11.3.1 USB Compliance Features Upon connection of 5 V to the powered-down device, the linear regulators will automatically power up the device. To meet USB inrush specifications, linear regulators have a current limit which is <100 mA, nominally 50 mA, and is active by default. This current limit is disabled in hardware after power-up, but can be re-enabled through the HW_POWER_5VCTRL_ENABLE_ILIMIT by software. System designers must understand that the current inrush limit during 5 V power-up places restrictions on application current consumption until it is disabled. Specifically, after connection to 5V, if the system draws more current than the current limit allows, the startup sequence does not complete and the ROM code does not execute. Further, USB Host implies that B-devices must draw very little current from 5 V. This requirement can be met by setting HW_POWER_5VCTRL_ILIMIT_EQ_ZERO when the Host application is active. The comparators required for Host capability can be i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 947 Linear Regulators enabled by HW_POWER_5VCTRL_PWRUP_VBUS_CMPS. It is also possible to change the threshold of the Vbus valid comparator using HW_POWER_5VCTRL_VBUSVALID_TRSH. If very low power operation is required, as in USB suspend, then the circuits required to elegantly switch to the DC-DC converter may have to be powered off. In those cases, the system must fully power down after VDD5V becomes invalid. It can auto restart with the DC-DC converter, if HW_RTC_PERSISTENT0_AUTO_RESTART is set. 11.3.2 5V to Battery Power Interaction The i.MX28 supports several different options related to the interaction of the switching converters with the linear regulators. The two primary options are a reset on 5V insertion/ removal or a handoff to the DC-DC converters that is invisible to the end-user of the application. Figure 11-3 includes these two options as the two system architecture decision boxes. 11.3.2.1 Battery Power to 5-V Power By default, the DC-DC converter turns off when VDD5V becomes valid and the system does not reset. If the system is operating from the DC-DC converter and is using more current than the linear regulators can supply, then the VDDD, VDDA, and VDDIO rails will droop when 5V is attached and the system may brownout and shut down. To avoid this issue, set the ENABLE_DCDC bit and set the LINREG_OFFSET fields to 0b2 in anticipation of VDD5V becoming present. The ENABLE_DCDC bit will cause the DCDC converter to remain on even after 5V is connected and, thus, guarantee a stable supply voltage until the system is configured for removal of 5V. The LINREG_OFFSET fields = 0b2 cause the linear regulators to regulate to a lower target voltage than the switching converter and prevent unwanted interaction between the two power supplies. After the system is configured for removal of 5V, ENABLE_DCDC can be set low and ENABLE_ILIMIT set low in register HW_POWER_5VCTRL to allow the linear regulators to supply the system power, if desired. 11.3.2.2 5-V Power to Battery Power Configuring the system for a 5-V-to-battery power handoff requires setup code to monitor the battery voltage as well as detect the removal of 5V. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 948 Freescale Semiconductor, Inc. Chapter 11 Power Supply Monitoring the battery voltage is performed by LRADC. Typically, this involves programming the LRADC registers to periodically monitor the battery voltage as described in LRADC Overview. The measured battery voltage should be written into the HW_POWER_BATTMONITOR register field BATT_VAL using the AUTOMATIC field in the HW_LRADC_CONVERSION register. Also, configuring battery brownout should be performed so that the system behaves as desired when 5V is no longer present and the battery is low. The recommended method to detect removal of 5V requires setting VBUSVALID_5VDETECT and programming the detection threshold VBUSVALID_TRSH to 0x1 in HW_POWER_5VCTRL. Next, in order to minimize linear regulator and DC-DC converter interaction, it is necessary to set the LINREG_OFFSET = 0b2 in the HW_POWER_VDDIOCTRL, HW_POWER_VDDACTRL, and HW_POWER_VDDDCTRL registers. Finally, set DCDC_XFER and clear PWDN_5VBRNOUT in the HW_POWER_5VCTRL register. This sequence is important because it is safe to disable the powerdown-on-unplug functionality of the device only after the system is completely ready for a transition to battery power. 11.3.2.3 5-V Power and Battery Power Battery charge can also be enabled to provide additional power efficiency when connected to 5V. If the DC-DC switching converter is also enabled, the buck switching converters will efficiently convert the battery voltage to the desired VDDA, VDDD, and VDDIO voltages (instead of using the less efficient internal linear regulators). 11.3.3 Power-Up Sequence The DC-DC converter controls the power-up and reset of the i.MX28. The power-up sequence begins when the battery is connected to the BATT pin of the device (or a 5V source is connected to the VDD5V pin). Either the BATT pin or VDD5V provides power to the DC-DC startup circuitry, the crystal oscillator, and the real-time clock. This means that the crystal oscillator can be running, if desired, whenever a battery is connected to BATT pin. This feature allows the real-time clock to operate when the chip is in the off state. The crystal oscillator/RTC is the only power drain on the battery in this state and consumes only a very small amount of power. During this time, the VDDIO, VDDD and VDDA supplies are held at ground. This is the off state that continues until the system power up begins. Power-up can be started with one of several events: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 949 Linear Regulators * PSWITCH pin >= minimum MID level PSWITCH for 100 ms * VDD5V power pin > 4.25 V for 100 ms * Real-time clock alarm wakeup When a power-up event has occurred, if VDD5V is valid, then the on-chip linear regulators charge the VDDD, VDDA and VDDIO rails to their default voltages. If VDD5V is not valid, then the DC-DC supplies the VDDD, VDDA, and VDDIO rails. When the voltage rails have reached their target values, the digital logic reset is deasserted and the CPU begins executing code. If the power supplies do not reach the target values by the time PSWITCH is deasserted or 5V is removed, the system returns to the off state. The power-up time is dependent on the VDDD/VDDA/VDDIO load and battery or VDD5V voltage, but should be less than 100 ms. The VDDD//VDDAVDDIO load should be minimal during power up to ensure proper startup of the DC-DC converter. There is an integrated 5-K resistor that can be switched in between the VDDXTAL pin and PSWITCH. If enabled using HW_RTC_PERSISTENT0_AUTO_RESTART, then the device immediately begins the power-up sequence after power-down. 11.3.4 Power-Down Sequence Power-down is also controlled by the DC-DC converters. When the DC-DC converter detects a power-down event, it returns the device to the off state described above. The power-down sequence is started when one of these events occur: * HW_POWER_RESET_PWD bit set while the register is unlocked. * Error condition occurs, as described in Brownout/Error Detection. * The watchdog timer expires while enabled. * Fast falling edge (<10 ns) on PSWITCH pin. The HW_POWER_RESET_PWD_OFF bit disables all the power-down paths except for the watchdog timer when it is set. The lower 16 bits of the HW_POWER_RESET register can only be written, if the value 0x3E77 is placed in the unlock field. An external capacitor on the PSWITCH can be used to prevent an unwanted power down due to falling edges. This can also be disabled in HW_POWER_RESET_PWD_OFF register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 950 Freescale Semiconductor, Inc. Chapter 11 Power Supply 11.3.4.1 Powered-Down State While the chip is powered down, the VDDIO, VDDD and VDDA rail are pulled down to ground. The VDDIO rail is shorted to ground. The crystal oscillator and the RTC can continue to operate by drawing power from the BATT pin. See RTC Overview for more information about operating a crystal and the RTC in the powered-down state. 11.3.5 Reset Sequence Figure 11-3 shows a flowchart for the power-up, power-down and reset sequences. A reset event can be triggered by unlocking the HW_POWER_RESET register and setting the HW_CLKCTRL_RESET_DIG bit. This reset affects the digital logic only, although the digital logic also includes most of the registers that control the analog portions of the chip. The persistent bits within the RTC block and the power module control bits are not reset using this method. To reset the analog as well as the digital logic, set the HW_CLKCTRL_RESET_CHIP bit. The DC-DC converter and/or linear regulators continue to maintain the power supply rails during the reset. 11.4 PSWITCH Pin Functions The PSWITCH pin has several functions whose operation is determined by the i.MX28based product's hardware and software design. 11.4.1 Power On When the PSWITCH pin voltage is higher than approximately the minimum MID level (as specified in Table 11-1) for >100 ms, the DC-DC converter begins its startup routine. This is the primary method of starting the system through PSWITCH. All products based on the i.MX28 must have a mechanism of bringing PSWITCH high to power up through an always-present supply (for example, battery or VDDXTAL). Table 11-1. PSWITCH Input Characteristics Parameter PSWITCH LOW LEVEL 1 PSWITCH MID LEVEL & STARTUP 12 HW_PWR_STS_PSWI TCH Min Max Uni ts 0x00 0.00 0.30 V 0x01 0.65 1.50 V Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 951 PSWITCH Pin Functions Table 11-1. PSWITCH Input Characteristics (continued) PSWITCH HIGH LEVEL 13 0x11 (1.1* VDDXTAL)+ 0.58 2.45 V 1. Consult the reference schematics for recommended PSWITCH button circuitry. 2. A MID LEVEL PSWITCH state can be generated by connecting the VDDXTAL output of the SOC to PSWITCH through a switch. 3. PSWITCH acts like a high impedance input (>300 k) when the voltage applied to it is less than 1.5 V. However, above 1.5 V it becomes lower impedance. To simplify design, it is recommended that a 10 k resistor to VDDIO be applied to PSWITCH to set the HIGH LEVEL state (the PSWITCH input can tolerate voltages greater than 2.45 V as long as there is a 10 k resistor in series to limit the current). 11.4.2 Power Down If the PSWITCH pin voltage has a falling edge faster than 15 ns, then this sends a powerdown request to the DC-DC converter. The fast-falling-edge power-down may be blocked by the HW_POWER_RESET_PWD_OFF function. The fast-falling edge can also be prevented by placing a RC filter on the PSWITCH pin. Most i.MX28-based systems do not use the PSWITCH fast-falling-edge power-down and include the RC filter to prevent it from occurring accidentally. 11.4.3 Software Functions/Recovery Mode When the PSWITCH pin voltage is pulled up to the minimum MID level (as specified in Table 11-1) the lower HW_POWER_STS_PSWITCH bit is set. Software can poll this bit and perform a function as desired by the product designer. Example functions include a play/pause/power-down button, delay for startup, and so on. When the PSWITCH pin is connected to VDDIO through a current limiting resistor, the upper HW_POWER_STS_PSWITCH bit is also set. If this bit is set for more than five seconds during ROM boot, the system executes the Freescale USB Firmware Recovery function, as described in Boot Modes. If the product designer does not wish to use Freescale USB Firmware Recovery, the product can be designed to not assert a voltage higher than the maximum MID level (as specified in Table 11-1) on the PSWITCH pin. Refer to the Freescale i.MX28 reference schematics for example configurations of the PSWITCH pin. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 952 Freescale Semiconductor, Inc. Chapter 11 Power Supply Software-Controlled Resets Normal Power-Up Flow No Power No Battery, no 5V. Battery Insert or 5V_Detect=1 Power-On Reset (Clock and Persistent Bits Reset) To Power Down: Set HW_POWER_RESET_PWD State Zero (Persistent bits retain state, XTAL and clock active if enabled) For Cold Reboot: HW_RTC_PERSISTENT0_AUTO_RESTART then HW_POWER_RESET_PWD PSWITCH=1 or RTC Alarm or AUTO_RESTART=1 or 5V_DETECT=1 Power Up (Start XTAL if it's off , Start 5V Linear Regs if 5V Detect, else start DCDC converter) Power is Stable To Reset DCDC and Digital: Start Digital Clocks (Digital Reset Asserted. Digital clocks all = 1 MHz) Set HW_CLKCTRL_RESET_CHIP To Reset Digital but not DCDC (warm boot): Set HW_CLKCTRL_RESET_DIG Reset DCDC PIO Registers (All non-persistent flop resets asserted, Note that the DCDC continues to operate even if the PIO registers are reset. Digital clocks all = 1 MHz) Reset Non-DCDC Digital Registers (Non persistent and non-POWER flop resets asserted. Digital clocks all = 1 MHz) Wait 16 cycles for all resets to propogate Release Reset (Digital clock domains at default frequency and gating, boot CPU ) Figure 11-3. Power-Up, Power-Down, and Reset Flow Chart 11.5 Battery Monitor The power control system includes a battery monitor. The battery monitor has two functions: battery brownout detection and battery voltage feedback to the DC-DC converter. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 953 Battery Charger If the battery voltage drops below the programmable brownout, then a fast interrupt (FIQ) can be generated for the CPU. Software typically uses the LRADC to monitor the battery voltage and shut down elegantly while there is a minimal operating margin. But, if an unexpected event (such as a battery removal) occurs, then the system needs to be placed immediately in the off state to ensure that it can restart properly. The brownout is controlled in the HW_POWER_BATTMONITOR register. The IRQ must also be enabled in the interrupt collector. To enable optimum performance over the battery range, the DC-DC converter needs to be provided with the battery voltage, which is measured by the battery pin LRADC. Normally, LRADC channel 7 is dedicated to periodically measuring the battery voltage with a period in the millisecond range for most applications. The voltage is automatically placed into the BATT_VAL field of the HW_POWER_BATTMONITOR register through the HW_LRADC_CONVERSION register. If necessary, software can turn off the automatic battery voltage update and set the BATT_VAL field manually. 11.6 Battery Charger The battery charger is essentially a linear regulator that has current and voltage limits. Charge current is software-programmable within the HW_POWER_CHARGE register. Li-Ion batteries can be charged at the lower of 1C, 785 mA, or the VDD5V current limit. USB charging is typically limited to 500 mA or less to meet compliance requirements. Also, battery charge current will be automatically reduced if the current demands from VDD4P2 and the battery charger exceed the CHARGE_4P2_ILIMIT. Full battery charge current will be restored once the VDD4P2 + battery charge current falls below the CHARGE_4P2_ILIMIT value. Typical charge times for a Li-Ion battery are 1.5 to 3 hours with >70% of the charge delivered in the first hour. The battery charge voltage limit is 4.2 V for the Li-Ion batteries. The Li-Ion charge is typically stopped after a certain time limit OR when the charging current drops below 10% of the charge current setting. The HW_POWER_CHARGE register includes controls for the maximum charge current and for the stop charge current. While the charger is delivering current greater than the stop charge limit, the HW_POWER_STS_CHRGSTS bit will be high. This bit should be polled (a low rate of 1 second or greater is fine) during charge. When the bit goes low, the charging is complete. It would be good practice to check that this bit is low for two consecutive checks, as the DC-DC switching might cause a spurious low result. Once this bit goes low, the charger can either be stopped immediately or stopped after a top-off time limit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 954 Freescale Semiconductor, Inc. Chapter 11 Power Supply Although the charger will avoid exceeding the charge voltage limit on the battery, it is NOT recommended to leave the charger active indefinitely. It should be turned off when the charge is complete. One can programatically monitor the battery voltage using the LRADC. The charger has its own (very robust) voltage limiting that operates independently of the LRADC. But monitoring the battery voltage during the charge might be helpful for reporting the charge progress. The battery charger is capable of generating a large amount of heat within the i.MX28, especially at currents above 400 mA. The dissipated power can be estimated as: (5V - battery_volt) * current. At max current (785 mA) and a 3-V battery, the charger can dissipate 1.57 W, raising the die temp as much as 80 C. To ensure that the system operates correctly, the die temperature sensor should be monitored every 100 ms. If the die temperature exceeds 115 C (the max value for the chip temp sensor), then the battery charge current must be reduced. The LRADC can also be used to monitor the battery temperature or chip temperature. There is an integrated current source for the external temperature sensor that can be configured and enabled through HW_LRADC_CTRL2 register. 11.7 11.5.1 Battery Detection The battery is detected by checking the battery brownout status or measuring the battery pin voltage. If either indicates the battery voltage is below an application-defined lowvoltage threshold, the battery is not attached. When the battery voltage is measured in the expected operational range, the FASTSETTLING bitfield in the HW_POWER_REFCTRL register should be set to enable an internal load on the battery. If no battery is connected, the internal load will discharge the capacitor on the battery pin to bring the voltage below the application-defined low-voltage threshold. If a battery is connected, the voltage should remain in the expected operational range. After battery detection is complete, the FASTSETTLING bitfield should be cleared to disable the internal load. The internal load is automatically disabled when a battery brownout is detected. In this case, the FASTSETTLING bitfield must be cycled to re-enabled the load. This is important for situations where the load is enabled at a battery voltage just above the battery brownout threshold and then the battery voltage drops below the threshold causing the brownout status to change. Software must account for this situation by reenabling the load when the battery voltage is below the brownout threshold. The length of time for the battery capacitor to discharge is variable between designs and is dependent on the amount of capacitance on the board. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 955 Silicon Speed Sensor 11.8 Silicon Speed Sensor The i.MX28 integrates three silicon speed sensors to measure the performance characteristics of an individual die at its ambient temperature and process parametrics. One is inside ARM9 to measure ARM9 performance, one is in core logic which including system bus and peripherals to measure core logic performance and another one is inside DC-DC block. A silicon speed sensor consists of a ring oscillator and a frequency counter. The ring oscillator runs on the VDDD power rail. Therefore, its frequency tracks the silicon performance as it changes in response to changes in operating voltage and temperature. The crystal oscillator is directly used as the precision time base for measuring the frequency of a ring oscillator. The ring oscillator is normally disabled. There is a 8-bit/16-bit counter connected to the ring oscillator that performs the frequency measurement. See HW_POWER_SPEED register. Thus, the counter holds the number of cycles the ring oscillator was able to generate during one crystal clock period. The natural frequency of the ring oscillator strongly tracks the silicon process parametrics, that is, faster silicon processes yield ring oscillators that run faster and thereby yield larger count values. The natural frequency tracks junction temperature effects on silicon speed as well. The information given by the speed sensors can be used with the silicon temperature and process parameters, which can also be monitored by system software. Freescale can provide a power management application note and firmware that takes full advantage of the on-chip monitoring functions to enable minimum-voltage operation. 11.9 Thermal-Overload Protection Circuit The i.MX28 integrates a thermal-overload protection circuit to shut down the device when the on-die temperature exceeds a programmed target value. It consists of a bipolar based voltage generator whose characteristics track the on-die temperature. This temperature-dependent voltage is compared to a fixed voltage level that does not vary with the temperature to trigger a shut down of the device. The thermal-overload protection circuit is disabled by default, but can be enabled after the system is up. Its default thermal trip-point is set to 115degC and can be programmed up to 150degC in 5degC steps. See HW_POWER_THERMAL register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 956 Freescale Semiconductor, Inc. Chapter 11 Power Supply 11.10 Bandgap Reference Generator The i.MX28 integrates a bandgap generator which creates supply and temperature stable voltage and current references for the on-chip blocks. Several bits are provided to adjust the reference voltages and currents. See HW_POWER_REFCTRL register. 11.11 Interrupts The power system supports nine CPU interrupt events that are programmable within the HW_POWER_CTRL register. The interrupts are listed in Table 11-2. Table 11-2. Power System Interrupts HW_POWER_CTRL INTERRUPT BIT Description VDDA_BO_IRQ VDDA Brownout VDDD_BO_IRQ VDDD Brownout VDDIO_BO_IRQ VDDIO Brownout BATT_BO_IRQ Battery Brownout VDD5V_GT_VDDIO_IRQ VDD5V > (VDDIO + 0.6) DC_OK_IRQ Voltage Supplies Ok after target voltage change VBUSVALID_IRQ VDD5V > Vbusvalid Threshold LINREG_OK_IRQ Debug use only PSWITCH_IRQ PSWITCH Status The VDDA_BO_IRQ, VDDD_BO_IRQ, VDDIO_BO_IRQ, and BATT_BO_IRQ each have their own interrupt line back to the interrupt collector. However, the remaining five interrupts--VDD5V_GT_VDDIO_IRQ, DC_OK_IRQ, VBUSVALID_IRQ, LINREG_OK_IRQ and PSWITCH_IRQ--all share a single interrupt line. In this case, software must read the interrupt status bits to discover which event caused the interrupt. 11.12 Power Memory Map/Register Definition iMX28 POWER Hardware Register Format Summary i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 957 Power Memory Map/Register Definition HW_POWER memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8004_4000 Power Control Register (HW_POWER_CTRL) 32 R/W 0001_0024h 11.12.1/ 959 8004_4010 DC-DC 5V Control Register (HW_POWER_5VCTRL) 32 R/W 2010_0490h 11.12.2/ 961 8004_4020 DC-DC Minimum Power and Miscellaneous Control Register (HW_POWER_MINPWR) 32 R/W 0000_0000h 11.12.3/ 964 8004_4030 Battery Charge Control Register (HW_POWER_CHARGE) 32 R/W 0001_0000h 11.12.4/ 966 8004_4040 VDDD Supply Targets and Brownouts Control Register (HW_POWER_VDDDCTRL) 32 R/W 0032_0710h 11.12.5/ 969 8004_4050 VDDA Supply Targets and Brownouts Control Register (HW_POWER_VDDACTRL) 32 R/W 0000_270Ch 11.12.6/ 971 8004_4060 VDDIO Supply Targets and Brownouts Control Register (HW_POWER_VDDIOCTRL) 32 R/W 0000_2406h 11.12.7/ 973 8004_4070 VDDMEM Supply Targets Control Register (HW_POWER_VDDMEMCTRL) 32 R/W 0000_0230h 11.12.8/ 976 8004_4080 DC-DC Converter 4.2V Control Register (HW_POWER_DCDC4P2) 32 R/W 0000_0018h 11.12.9/ 978 8004_4090 DC-DC Miscellaneous Register (HW_POWER_MISC) 32 R/W 0000_0000h 11.12.10/ 980 8004_40A0 DC-DC Duty Cycle Limits Control Register (HW_POWER_DCLIMITS) 32 R/W 0000_0C5Fh 11.12.11/ 982 8004_40B0 Converter Loop Behavior Control Register (HW_POWER_LOOPCTRL) 32 R/W 0000_0021h 11.12.12/ 983 8004_40C0 Power Subsystem Status Register (HW_POWER_STS) 32 R 0000_0200h 11.12.13/ 986 8004_40D0 Transistor Speed Control and Status Register (HW_POWER_SPEED) 32 R/W 0000_0000h 11.12.14/ 989 8004_40E0 Battery Level Monitor Register (HW_POWER_BATTMONITOR) 32 R/W 0000_0A00h 11.12.15/ 990 8004_4100 Power Module Reset Register (HW_POWER_RESET) 32 R/W 0000_0000h 11.12.16/ 991 8004_4110 Power Module Debug Register (HW_POWER_DEBUG) 32 R/W 0000_0000h 11.12.17/ 993 8004_4120 Power Module Thermal Reset Register (HW_POWER_THERMAL) 32 R/W 0000_0080h 11.12.18/ 994 8004_4130 Power Module USB1 Manual Controls Register (HW_POWER_USB1CTRL) 32 R/W 0000_000Eh 11.12.19/ 995 8004_4140 Power Module Special Register (HW_POWER_SPECIAL) 32 R/W 0000_0000h 11.12.20/ 996 8004_4150 Power Module Version Register (HW_POWER_VERSION) 32 R 0400_0000h 11.12.21/ 997 8004_4160 Analog Clock Control Register (HW_POWER_ANACLKCTRL) 32 R/W 8400_0400h 11.12.22/ 997 8004_4170 POWER Reference Control Register (HW_POWER_REFCTRL) 32 R/W 0000_0000h 11.12.23/ 999 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 958 Freescale Semiconductor, Inc. Chapter 11 Power Supply 11.12.1 Power Control Register (HW_POWER_CTRL) The Power Control Register contains control bits specific to the digital section. HW_POWER_CTRL: 0x000 HW_POWER_CTRL_SET: 0x004 HW_POWER_CTRL_CLR: 0x008 HW_POWER_CTRL_TOG: 0x00C Address: 8004_4000h base + 0h offset = 8004_4000h 31 30 29 28 RSRVD2 24 23 22 21 20 19 18 17 16 DCDC4P2_BO_IRQ ENIRQ_DCDC4P2_BO VDD5V_DROOP_IRQ ENIRQ_VDD5V_DROOP PSWITCH_IRQ PSWITCH_IRQ_SRC POLARITY_PSWITCH ENIRQ_PSWITCH POLARITY_DC_OK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DC_ OK_ IRQ ENIRQBATT_BO VDDIO_BO_IRQ ENIRQ_VDDIO_BO VDDA_BO_IRQ ENIRQ_VDDA_BO VDDD_BO_IRQ ENIRQ_VDDD_BO POLARITY_VBUSVALID VBUSVALID_IRQ ENIRQ_VBUS_VALID POLARITY_VDD5V_GT_VDDIO VDD5V_GT_VDDIO_IRQ ENIRQ_VDD5V_GT_VDDIO RSRVD1 BATT_BO_IRQ Bit 25 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 W Reset 26 ENIRQ_DC_OK R 27 PSWITCH_MID_TRAN Bit R W Reset i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 959 Power Memory Map/Register Definition HW_POWER_CTRL field descriptions Field 31-28 RSRVD2 Description Reserved. 27 When this bit is set, it selects the from-mid-transition interrupt functionality for PSWITCH. When set, in PSWITCH_MID_ conjuction with ENIRQ_PSWITCH, it will set PSWITCH_IRQ when either a 01 to 11 or 01 to 00 transition TRAN is detected on the PSWITCH comparators. When this bit is set, PSWITCH_IRQ_SRC and POLARITY_PSWITCH have no effect. 26-25 RSRVD1 Reserved. 24 Interrupt Status for 4P2_BO. Reset this bit by writing a one to the SCT clear address space and not by a DCDC4P2_BO_ general write. IRQ 23 ENIRQ_ DCDC4P2_BO 22 VDD5V_ DROOP_IRQ Set to 1 to enable interrupt for 4P2_BO. Interrupt Status for VDD5V_DROOP. Reset this bit by writing a one to the SCT clear address space and not by a general write. 21 Set to 1 to enable interrupt for VDD5V_DROOP. ENIRQ_VDD5V_ DROOP 20 PSWITCH_IRQ Interrupt status for PSWITCH signals. Interrupt polarity is set using POLARITY_PSWITCH. Comparator bit is selected through PSWITCH_IRQ_SRC. Reset this bit by writing a one to the SCT clear address space and not by a general write. 19 Set to 1 to use HW_POWER_STS_PSWITCH bit 1 as source, 0 for HW_POWER_STS_PSWITCH bit 0 PSWITCH_IRQ_ SRC 18 POLARITY_ PSWITCH 17 ENIRQ_ PSWITCH Set to 1 to interupt when the interrupt source is high, 0 for low Interrupt status for PSWITCH signal. Interrupt polarity is set using POLARITY_PWITCH and source selected by PSWITCH_SRC. 16 Debug use only. Set to 1 to check for linear regulators ok. Set to 0 to check for 5V disconnected. POLARITY_DC_ OK 15 DC_OK_IRQ Interrupt Status for DC_OK. Reset this bit by writing a one to the SCT clear address space and not by a general write. 14 Set to 1 to enable interrupt for DC_OK. ENIRQ_DC_OK 13 BATT_BO_IRQ Interrupt Status for BATT_BO. Reset this bit by writing a one to the SCT clear address space and not by a general write. 12 Set to 1 to enable interrupt for battery brownout. ENIRQBATT_BO 11 Interrupt Status for VDDIO_BO. Reset this bit by writing a one to the SCT clear address space and not by VDDIO_BO_IRQ a general write. 10 Set to 1 to enable interrupt for VDDIO brownout. ENIRQ_VDDIO_ BO Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 960 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_CTRL field descriptions (continued) Field Description 9 Interrupt Status for VDDA_BO. Reset this bit by writing a one to the SCT clear address space and not by a VDDA_BO_IRQ general write. 8 Set to 1 to enable interrupt for VDDIO brownout. ENIRQ_VDDA_ BO 7 Interrupt Status for VDDD_BO. Reset this bit by writing a one to the SCT clear address space and not by VDDD_BO_IRQ a general write. 6 Set to 1 to enable interrupt for VDDD brownout. ENIRQ_VDDD_ BO 5 POLARITY_ VBUSVALID Set to 1 to check for 5V connected using VBUSVALID status bit. Set to 0 to check for 5V disconnected. 4 Interrupt status for VBUSVALID signal. Interrupt polarity is set using POLARITY_VBUSVALID. Reset this VBUSVALID_IRQ bit by writing a one to the SCT clear address space and not by a general write. 3 Set to 1 to enable interrupt for 5V detect using VBUSVALID. ENIRQ_VBUS_ VALID 2 POLARITY_ VDD5V_GT_ VDDIO Set to 1 to check for 5V connected. Set to 0 to check for 5V disconnected. 1 VDD5V_GT_ VDDIO_IRQ Interrupt status for VDD5V_GT_VDDIO signal. Interrupt polarity is set using POLARITY_VDD5V_GT_VDDIO. Reset this bit by writing a one to the SCT clear address space and not by a general write. 0 Set to 1 to enable interrupt for 5V detect. ENIRQ_VDD5V_ GT_VDDIO 11.12.2 DC-DC 5V Control Register (HW_POWER_5VCTRL) This register contains the configuration options of the power management subsystem that are available when external 5V is applied. HW_POWER_5VCTRL: 0x010 HW_POWER_5VCTRL_SET: 0x014 HW_POWER_5VCTRL_CLR: 0x018 HW_POWER_5VCTRL_TOG: 0x01C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 961 Power Memory Map/Register Definition Address: 8004_4000h base + 10h offset = 8004_4010h 29 RSRVD6 28 27 26 25 24 23 22 21 RSRVD4 20 PWD_CHARGE_4P2 R 30 RSRVD5 31 VBUSDROOP_TRSH Bit HEADROOM_ADJ 19 18 17 16 RSRVD3 CHARGE_ 4P2_ILIMIT 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE_LINREG_ILIMIT DCDC_XFER VBUSVALID_5VDETECT VBUSVALID_TO_B ILIMIT_EQ_ZERO PWRUP_VBUS_CMPS ENABLE_DCDC Bit 0 1 0 0 1 0 0 0 0 RSRVD2 Reset PWDN_5VBRNOUT W R CHARGE_4P2_ILIMIT VBUSVALID_TRSH W Reset 0 0 0 0 0 1 0 0 HW_POWER_5VCTRL field descriptions Field 31-30 RSRVD6 Description Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 962 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_5VCTRL field descriptions (continued) Field 29-28 VBUSDROOP_ TRSH Description Set the threshold for the VBUSDROOP comparator. This comparator should typically be programmed at least 200mV above VBUSVALID, and can be used to terminate battery charge when the voltage on VDD5V falls below the programmed threshold. This comparator has ~50mV of hystersis to prevent chattering at the comparator trip point. 0b00: 4.3V 0b01: 4.4V 0b10: 4.5V(default) 0b11: 4.7V 27 RSRVD5 26-24 HEADROOM_ ADJ 23-21 RSRVD4 Reserved. Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages. Reserved. 20 Controls the power down of both the battery charger and 4.2V regulation circuit. Default is powered down. PWD_CHARGE_ 4P2 19-18 RSRVD3 Reserved. 17-12 Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume. Current CHARGE_4P2_ represented by each bits is as follows: (400 mA, 200 mA, 100 mA, 50 mA, 20 mA, 10 mA) = (bit 5,bit 4, bit ILIMIT 3, bit 2, bit 1, bit 0). The DCDC_4P2 circuit is given priority as the sum of the currents exceeds the limit. 11 RSRVD2 10-8 VBUSVALID_ TRSH Reserved. Set the threshold for the VBUSVALID comparator. This comparator is the most accurate method to determine the presence of 5v, and includes hystersis to minimize the need for software debounce of the detection. This comparator has ~50mV of hystersis to prevent chattering at the comparator trip point. 0b000: 2.9V 0b001: 4.0V 0b010: 4.1V 0b011: 4.2V 0b100: 4.3V(default) 0b101: 4.4V 0b110: 4.5V 0b111: 4.6V 7 PWDN_ 5VBRNOUT The purpose of this bit is to power down the device if 5V is removed before the system is completely initialized. Clear this bit to disable automatic hardware powerdown AFTER the system is configured for 5v removal. This bit should not be set if DCDC_XFER is set. 6 Enable the current limit in the linear regulators. The current limit is active during powerup from 5v and ENABLE_ automatically disables before the ROM executes. This limit is needed to meet the USB in rush current LINREG_ILIMIT specification of 100mA + 50uC. Note this linear regulator current limit is not related to the CHARGE_4P2_ILIMIT. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 963 Power Memory Map/Register Definition HW_POWER_5VCTRL field descriptions (continued) Field Description 5 DCDC_XFER Enable automatic transition to switching DC-DC converter when VDD5V is removed. The LRADC must be operational and the BATT_VAL field must be written with the battery voltage using 8-mV step-size. It is also important to set the EN_BATADJ field. 4 VBUSVALID_ 5VDETECT Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter. The VBUSVALID comparator provides a more accurate and adjustable threshold to determine the presence of 5V in the system, and is the recommended method of detecting 5V. 3 VBUSVALID_ TO_B This bit muxes the Bvalid comparator to the VBUSVALID comparator and is used for test purposes only. 2 ILIMIT_EQ_ ZERO The amount of current the device will consume from the 5V rail is minimized. The VDDIO linear regulator current limit is set to zero mA. Also, the source of current for the crystal oscillator and RTC is switched to the battery. Note that this functionality does not affect battery charge. 1 Powers up comparators for 5v PWRUP_VBUS_ CMPS 0 Enables the switching DC-DC converter when 5V is present. It is recommended to set ILIMIT_EQ_ZERO, ENABLE_DCDC ENABLE_ILIMIT, and all LINREG_OFFSET bits when enabling this functionality. 11.12.3 DC-DC Minimum Power and Miscellaneous Control Register (HW_POWER_MINPWR) This register controls options to drop the power used by the switching DC-DC converter. These bits should only be modified with guidance from Freescale. HW_POWER_MINPWR: 0x020 HW_POWER_MINPWR_SET: 0x024 HW_POWER_MINPWR_CLR: 0x028 HW_POWER_MINPWR_TOG: 0x02C Address: 8004_4000h base + 20h offset = 8004_4020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 964 Freescale Semiconductor, Inc. 11 10 9 8 7 6 5 4 3 2 1 0 USE_VDDXTAL_VBG PWD_ANA_CMPS ENABLE_OSC SELECT_OSC VBG_OFF DOUBLE_FETS HALF_FETS LESSANA_I PWD_XTAL24 DC_STOPCLK EN_ DC_ PFM DC_HALFCLK RSRV D1 12 PWD_BO R 13 RSVD1 15 Bit LOWPWR_4P2 Chapter 11 Power Supply 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 HW_POWER_MINPWR field descriptions Field 31-15 RSRVD1 Description Reserved. 14 Enable low power regulation of DCDC_4P2 limited to 2.5mA. LOWPWR_4P2 13 RSVD1 12 PWD_BO Program this field to 0x0. Powers down supply brownout comparators. This should only be used when monitoring supply brownouts is not needed. 11 Change the reference used in the dcdc converter to a low power, less accurate reference. This should USE_VDDXTAL_ only be used when achieving minimum system power is more important than supply voltage accuracy. VBG 10 PWD_ANA_ CMPS Powers down analog comparators used in the power module, including the VDD and VDDA brownout comparators, low power reference. This bit should only be set to reach absolute minimum system power when running from the linear regulators and supply accuracy and VDDD/VDDA brownout detection is not important. 9 ENABLE_OSC Enables the internal oscillator. This oscillator is less accurate , but lower power than the 24 MHz xtal. 8 SELECT_OSC Switch internal 24 MHz clock reference to the less accurate internal oscillator. This bit should be set only when accuracy of the 24 MHz clock is not important. The value of this bit should only be changed when ENABLE_OSC=1 and PWD_XTAL24=0. 7 VBG_OFF Powers down the bandgap reference. This should only be used in 5v-powered applications when absolute minimum power is more important than supply voltage accuracy. USB_I_SUSPEND must be set before this bit is set. 6 Approximately doubles the size of power transistors in DC-DC converter. This maybe be useful in high DOUBLE_FETS power conditions. 5 HALF_FETS Disable half the power transistors in DC-DC converter. This maybe be useful in low-power conditions when the increased resistance of the power FETs is acceptable. 4 LESSANA_I Reduce DC-DC analog bias current 20%. This bit is intended to reduce power in low-performance operating modes, such as USB suspend. 3 PWD_XTAL24 Powers down the 24 MHz oscillator, even when the system is still operating. This can be used with ENABLE_OSC and SELECT_OSC to reduce current in usb suspend and other low power modes where the accuracy of the clock is not important. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 965 Power Memory Map/Register Definition HW_POWER_MINPWR field descriptions (continued) Field Description 2 DC_STOPCLK Stop the clock to internal logic of switching DC-DC converter. This bit will take effect only after the switching FETs are off, due to battery configuration, PFM mode, or internal linear regulator operation. 1 EN_DC_PFM Forces DC-DC to operate in a Pulse Frequency Modulation mode. Intended to allow minimum system power in very low-power configurations when increased ripple on the supplies is acceptable. Also, HYST_SIGN in HW_POWER_LOOPCTRL should be set high when using PFM mode. 0 DC_HALFCLK Slow down DC-DC clock from 1.5 MHz to 750 kHz. This maybe be useful to improve efficiency at light loads or improve EMI radiation, although peak-to-peak voltage on the supplies will increase. 11.12.4 Battery Charge Control Register (HW_POWER_CHARGE) This register cotrols the battery charge features for both NiMH slow charge and Li-Ion charge. HW_POWER_CHARGE: 0x030 HW_POWER_CHARGE_SET: 0x034 HW_POWER_CHARGE_CLR: 0x038 HW_POWER_CHARGE_TOG: 0x03C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 966 Freescale Semiconductor, Inc. Chapter 11 Power Supply 29 28 27 26 25 24 RSRVD6 22 21 19 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 LIION_4P1 0 0 ENABLE_CHARGER_USB0 RSRVD2 W Reset PWD_BATTCHRG 0 ENABLE_LOAD 0 ENABLE_CHARGER_USB1 R 16 0 W Bit 17 0 ADJ_VOLT Reset 18 CHRG_STS_OFF 20 ENABLE_FAULT_DETECT R 23 RSRVD3 30 RSRVD4 31 RSRVD5 Bit LIION_4P1 Address: 8004_4000h base + 30h offset = 8004_4030h 0 0 RSRVD1 STOP_ILIMIT 0 0 0 BATTCHRG_I 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 967 Power Memory Map/Register Definition HW_POWER_CHARGE field descriptions Field 31-27 RSRVD6 26-24 ADJ_VOLT Description Reserved. Adjustments to the final LiIon final voltage. These bits should not be set unless recommended by Freescale. 0b000: no change 0b001: -0.25% 0b010: +0.50% 0b011: -0.75% 0b100: +0.25% 0b101: -0.50% 0b110: +0.75% 0b111: -1.00% 23 RSRVD5 Reserved. 22 Enable 100ohm load on the regulated 4.2V output. This bit should not be set unless recommended by ENABLE_LOAD Freescale. 21 RSRVD4 Reserved. 20 Enable fault detection in the battery charger. When enabled, this bit will power down the battery charger ENABLE_ when the VDD5V voltage falls below the battery voltage. The fault can be cleared by cycling FAULT_DETECT PWD_CHARGE_4P2. The fault detection is visible through HW_POWER_STS_VDD5V_FAULT. 19 CHRG_STS_ OFF Setting this bit disables the CHRGSTS status bit. Disabling CHRGSTS should only be done when the switching converter is enabled during battery charge if noise from the switching converter causes CHRGSTS to toggle excessively. 18 LIION_4P1 Reserved. 17 RSRVD3 Reserved. 16 PWD_ BATTCHRG 15-14 RSRVD2 Power-down the battery charge circuitry. This should only be set low when 5V is present. This bit can be set (charger turned off) automatically by the threshold units of the LRADC if programmed to do so. Reserved. 13 ENABLE_ CHARGER_ USB1 Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB1. This functionality is a new USB spec and should not be enabled unless recommended by Freescale. 12 ENABLE_ CHARGER_ USB0 Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB0. This functionality is a new USB spec and should not be enabled unless recommended by Freescale. 11-8 STOP_ILIMIT Current threshold at which the Li-Ion battery charger signals to stop charging. The current represented by each bit is as follows: (100 mA, 50 mA, 20 mA, 10 mA) = (bit 3, bit 2, bit 1, bit 0) It is recommended to set this value to 10% of the charge current. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 968 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_CHARGE field descriptions (continued) Field Description 7-6 RSRVD1 Reserved. BATTCHRG_I Magnitude of the battery charge current, the current represented by each bit is as follows: (400 mA, 200 mA, 100 mA, 50 mA, 20 mA, 10 mA) = (bit 5,bit 4, bit 3, bit 2, bit 1, bit 0) 11.12.5 VDDD Supply Targets and Brownouts Control Register (HW_POWER_VDDDCTRL) This register controls the voltage targets and brownout targets for the VDDD supply generated from the switching DC-DC converter and integrated linear regulators. The brownout comparators default enabled. Address: 8004_4000h base + 40h offset = 8004_4040h 31 30 29 28 27 26 25 24 20 19 18 17 16 ENABLE_LINREG DISABLE_FET RSRVD3 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 ADJTN W Bit 21 0 R Reset 22 DISABLE_STEPPING RSRVD4 23 PWDN_BRNOUT Bit RSRVD2 R LINREG_ OFFSET RSRVD1 BO_OFFSET TRG W Reset 0 0 0 0 0 1 1 1 0 0 0 1 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 969 Power Memory Map/Register Definition HW_POWER_VDDDCTRL field descriptions Field 31-28 ADJTN 27-24 RSRVD4 Description Two's complement number that can be used to adjust the duty cycle of VDDD. This is intended for test purposes only Reserved. 23 Powers down the device after the DC-DC converter completes startup if a VDDD brownout occurs. This PWDN_BRNOUT function is only active when 5V is not present. Additionally, software should clear this bit and disable this function after the system is configured for a VDDD brownout and the VDDD brownout interrupt is enabled. 22 DISABLE_ STEPPING Disables the default behavior of the voltage stepping algorithm when the TRG field is updated. By default, the control loop steps sequentially through 25mV steps on both target and brownout voltage to minimize transients during TRG adjustments. When this bit is set, the entire target voltage and brownout adjustment takes place at one time, which will speed transitions, but will result in increased supply transients as well as possible brownouts when the new (TRG - BO_OFFSET) >= old TRG. Thus, it is recommended to change TRG by less than the (BO_OFFSET-2) value when using DISABLE_STEPPING. This bit should be set high when powering VDDD from the integrated linear regulators. 21 ENABLE_ LINREG 20 DISABLE_FET Enables the VDDD linear regulator converter when the switching converter is active. By default, the linear regulator is not active when the switching converter is active. Disable the VDDD switching converter output. 19-18 RSRVD3 Reserved. 17-16 LINREG_ OFFSET Number of 25mV steps between linear regulator output voltage and switching converter target. 00b = 0 steps, recommended when powering VDDD only from linear regulator and ENABLE_DCDC=DCDC_XFER=0. It is also recommended to set DISABLE_STEPPING when powering VDDD from the linear regulators. 01b = 1 step above. 10b = 1 step below (default), important when powering VDDD from DC-DC converter and linear regulator simultaneously. 11b = 2 steps below. 15-11 RSRVD2 10-8 BO_OFFSET 7-5 RSRVD1 TRG Reserved. Brownout voltage offset in 25mV steps below the TRG value. Note that the hardware only supports brownout voltages between 0.8V and 1.475V, and values outside this range should not be programmed. The brownout trip voltage will adjust as the target voltage changes. Reserved. Voltage level of the VDDD supply. The step size of this field is 25 mV. 0x00 = 0.8 V, 0x1F = 1.575 V, and the reset value = 1.2 V. This field should not be set above the VDDD operating maximum voltage as specified in the Datasheet. It is also recommended to set DISABLE_STEPPING when powering VDDD from the integrated linear regulators. Setting DISABLE_STEPPING does set additional restrictions on TRG adjusments. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 970 Freescale Semiconductor, Inc. Chapter 11 Power Supply 11.12.6 VDDA Supply Targets and Brownouts Control Register (HW_POWER_VDDACTRL) This register controls the voltage targets and brownout targets for the VDDA supply generated from the switching DC-DC converter and integrated linear regulators. The brownout comparators default enabled. Address: 8004_4000h base + 50h offset = 8004_4050h 31 30 29 28 27 26 25 24 23 22 21 20 ENABLE_LINREG DISABLE_FET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSRVD2 R 16 0 W Bit 17 0 R Reset 18 DISABLE_STEPPING RSRVD4 19 PWDN_BRNOUT Bit RSRVD3 RSRVD1 LINREG_ OFFSET BO_OFFSET TRG W Reset 0 0 1 0 0 1 1 1 0 0 0 0 1 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 971 Power Memory Map/Register Definition HW_POWER_VDDACTRL field descriptions Field 31-20 RSRVD4 Description Reserved. 19 Powers down the device after the DC-DC converter completes startup if a VDDA brownout occurs. This PWDN_BRNOUT function is only active when 5V is not present. Additionally, software should clear this bit and disable this function after the system is configured for a VDDA brownout and the VDDA brownout interrupt is enabled. 18 DISABLE_ STEPPING Disables the default behavior of the voltage stepping algorithm when the TRG field is updated. By default, the control loop steps sequentially through 25mV steps on both target and brownout voltage to minimize transients during TRG adjustments. When this bit is set, the entire target voltage and brownout adjustment takes place at one time, which will speed transitions, but will result in increased supply transients as well as possible brownouts when the new (TRG - BO_OFFSET) >= old TRG. Thus, it is recommended to change TRG by less than the (BO_OFFSET-2) value when using DISABLE_STEPPING. This bit should be set high when powering VDDA from the integrated linear regulators. 17 ENABLE_ LINREG 16 DISABLE_FET Enables the VDDA linear regulator converter when the switching converter is active. By default, the linear regulator is not active when the switching converter is active. Disable the VDDA switching converter output. The switching converter is enabled by default when the battery is present or the ENABLE_DCDC is set. 15-14 RSRVD3 Reserved. 13-12 LINREG_ OFFSET Number of 25mV steps between linear regulator output voltage and switching converter target. 00b = 0 steps, recommended when powering VDDA from linear regulator and ENABLE_DCDC=DCDC_XFER=0. It is also recommended to set DISABLE_STEPPING when powering VDDA from the linear regulators. 01b = 1 step above. 10b = 1 step below (default), important when powering VDDA from DC-DC converter and linear regulator simultaneously. 11b = 2 steps below. 11 RSRVD2 10-8 BO_OFFSET 7-5 RSRVD1 TRG Reserved. Brownout voltage offset in 25mV steps below the TRG value. Note that the hardware only supports brownout voltages between 1.4V and 2.175V, and values outside this range should not be programmed. The brownout trip voltage will adjust as the target voltage changes. Reserved. Voltage level of the VDDA supply. The step size of this field is 25 mV. 0x00 = 1.5 V, 0x1F = 2.275 V, and the reset value = 1.8 V. This field should not be set above the VDDA operating maximum voltage as specified in the Datasheet. It is also recommended to set DISABLE_STEPPING when powering VDDA from the integrated linear regulators. Setting DISABLE_STEPPING does set additional restrictions on TRG adjusments. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 972 Freescale Semiconductor, Inc. Chapter 11 Power Supply 11.12.7 VDDIO Supply Targets and Brownouts Control Register (HW_POWER_VDDIOCTRL) This register controls the voltage targets and brownout targets for the VDDIO supply generated from the switching DC-DC converter and integrated linear regulators. The brownout comparators default enabled. 29 28 27 26 25 24 23 22 21 20 RSRVD5 R 19 ADJTN 18 17 16 DISABLE_FET 30 DISABLE_STEPPING 31 RSRVD4 Bit PWDN_BRNOUT Address: 8004_4000h base + 60h offset = 8004_4060h 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 973 Power Memory Map/Register Definition R 14 13 12 11 10 9 8 7 RSRVD2 15 Bit RSRVD3 6 5 4 3 2 1 0 1 0 RSRVD1 LINREG_ OFFSET BO_OFFSET TRG W Reset 0 0 1 0 0 1 0 0 0 0 0 0 0 1 HW_POWER_VDDIOCTRL field descriptions Field 31-24 RSRVD5 23-20 ADJTN 19 RSRVD4 Description Reserved. Two's complement number that can be used to adjust the duty cycle of VDDIO. This is intended for test purposes only Reserved. 18 Powers down the device after the DC-DC converter completes startup if a VDDIO brownout occurs. This PWDN_BRNOUT function is only active when 5V is not present. Additionally, software should clear this bit and disable this function after the system is configured for a VDDIO brownout and the VDDIO brownout interrupt is enabled. 17 DISABLE_ STEPPING Disables the default behavior of the voltage stepping algorithm when the TRG field is updated. By default, the control loop steps sequentially through 25mV steps on both target and brownout voltage to minimize transients during TRG adjustments. When this bit is set, the entire target voltage and brownout adjustment takes place at one time, which will speed transitions, but will result in increased supply transients as well as possible brownouts when the new (TRG - BO_OFFSET) >= old TRG. Thus, it is recommended to change TRG by less than the (BO_OFFSET-2) value when using DISABLE_STEPPING. This bit should be set high when powering VDDIO from the integrated linear regulators. 16 DISABLE_FET Disable the VDDIO switching converter output. The switching converter is enabled by default when the battery is present or the ENABLE_DCDC is set. 15-14 RSRVD3 Reserved. 13-12 LINREG_ OFFSET Number of 25mV steps between linear regulator output voltage and switching converter target. 00b = 0 steps, recommended when powering VDDIO from linear regulator and ENABLE_DCDC=DCDC_XFER=0. It is also recommended to set DISABLE_STEPPING when powering VDDIO from the linear regulators. 01b = 1 step above. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 974 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_VDDIOCTRL field descriptions (continued) Field Description 10b = 1 step below (default), important when powering VDDIO from DC-DC converter and linear regulator simultaneously. 11b = 2 steps below. 11 RSRVD2 10-8 BO_OFFSET 7-5 RSRVD1 TRG Reserved. Brownout voltage offset in 50 mV steps below the TRG value. Note that the hardware only supports brownout voltages between 2.7V and 3.475V, and values outside this range should not be programmed. The brownout trip voltage will adjust as the target voltage changes. Reserved. Voltage level of the VDDIO supply. The step size of this field is 50 mV. 0x00 = 2.8 V and the reset value = 3.1 V. Note that the maximum programmable voltage is 3.6V, therefore code values of 0x10 to 0x1F all map to 3.6 V. It is also recommended to set DISABLE_STEPPING when powering VDDIO from the integrated linear regulators. Setting DISABLE_STEPPING does set additional restrictions on TRG adjusments. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 975 Power Memory Map/Register Definition 11.12.8 VDDMEM Supply Targets Control Register (HW_POWER_VDDMEMCTRL) This register controls the voltage target for a memory supply generated from VDDA. This supply is intended for use with external memories such as LV-DDR that have unique voltage requirements not compatible with VDDIO, VDDA , or VDDD. Address: 8004_4000h base + 70h offset = 8004_4070h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD2 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE_LINREG Bit 0 ENABLE_ILIMIT Reset PULLDOWN_ACTIVE W 0 1 0 0 0 RSRVD2 R W Reset 0 0 0 0 0 BO_OFFSET 0 0 TRG 1 1 0 0 HW_POWER_VDDMEMCTRL field descriptions Field 31-11 RSRVD2 10 PULLDOWN_ ACTIVE Description Reserved. Activates pulldown on external memory supply. This bit should be set before the regulator is enabled to be sure the supply voltage powers up from ground. Default is pulldown inactive. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 976 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_VDDMEMCTRL field descriptions (continued) Field Description 9 Controls the inrush limit (~10mA) for the memory supply voltage. Default is active. This should remain ENABLE_ILIMIT active until the supply settles after enabling the linreg. This should be disabled before accessing the memory. 8 ENABLE_ LINREG Enables the regulator that creates the external memory supply voltage. After enabling the linreg need to wait until the VDDMEM rail is up before disabling the linreg current limit and accessing the memories. 500uS is usually an adequate delay, but it can be longer if VDDMEM cap is >1uF. 7-5 BO_OFFSET Brownout voltage offset in 25mV steps below the TRG value. Note that the hardware only supports brownout voltages between 1.1V and 1.75V, and values outside this range should not be programmed. The brownout trip voltage will adjust as the target voltage changes. TRG Voltage level of the external memory supply. The step size of this field is 25 mV. 0x00 = 1.1 V, 0x1A... 0x1F = 1.75 V, and the reset value = 1.5 V. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 977 Power Memory Map/Register Definition 11.12.9 DC-DC Converter 4.2V Control Register (HW_POWER_DCDC4P2) This register contains controls that need to be adjusted to select the 4.2V source as the input for the dcdc converter Address: 8004_4000h base + 80h offset = 8004_4080h 31 30 29 28 27 26 25 24 23 22 21 20 ISTEAL_ THRESH RSRVD5 18 17 16 ENABLE_4P2 ENABLE_DCDC HYST_DIR HYST_THRESH R 19 RSRVD3 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 DROPOUT_CTRL TRG W Reset Bit RSRVD2 R RSRVD1 BO CMPTRIP W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 HW_POWER_DCDC4P2 field descriptions Field 31-28 DROPOUT_ CTRL Description Adjusts the behavior of the dcdc converter and 4.2V regulation circuit. The two msbs control the VDD4P2 brownout below the target set by DCDC4p2_trg before the regulation circuit steals battery charge current to support the voltage on VDD4P2. The two lsbs control which power source is selected by the dcdc converter after ENABLE_DCDC is set. 0b11XX: 200mV 0b10XX: 100mV Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 978 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_DCDC4P2 field descriptions (continued) Field Description 0b01XX: 50mV 0b00XX: 25mV 0bXX00: DcDc Converter power source is DCDC_4P2 regardless of BATTERY voltage 0bXX01: DcDc converter uses DCDC_4P2 always, and only enables DCDC_BATT when VDD4P2 is less than BATTERY. 0bXX1X: DcDc converter selects either VDD4P2 or BATTERY, which ever is higher. 27-26 RSRVD5 Reserved. 25-24 ISTEAL_ THRESH Has no effect. 23 ENABLE_4P2 Enables the DCDC_4P2 regulation circuitry. The 4p2V load current has priority over the battery charge current when the sum of the two tries to exceed the limit set with CHARGE_4P2_ILIMIT. 22 Enable the dcdc converter to use the DCDC_4P2 pin as a power source based on a voltage comparison ENABLE_DCDC between the BATTERY pin voltage and the VDD4P2 pin voltage. The trip point of this comparator is controlled by the CMPTRIP bitfield. 21 HYST_DIR Enable hysteresis in analog comparator. 20 Increase the threshold detection for DCDC_4P2/BATTERY analog comparator. HYST_THRESH 19 RSRVD3 18-16 TRG Reserved. Regulation voltage of the DCDC_4P2 pin. 0b000 : 4.2V 0b001 : 4.1V 0b010 : 4.0V 0b011 : 3.9V 0b1XX : BATTERY 15-13 RSRVD2 12-8 BO Reserved. Brownout voltage in 25mV steps for the DCDC_4P2 pin. 0b00000 : 3.6V .. 0b11111 : 4.375V 7-5 RSRVD1 Reserved. CMPTRIP Sets the trip point for the comparison between the DCDC_4P2 and BATTERY pin. When the comparator output is high then, the switching converter may use the DCDC_4P2 pin as the source for the switching converter, otherwise it will use the DCDC_BATT pin. 0b00000 DCDC_4P2 pin >= 0.85 * BATTERY pin 0b00001 DCDC_4P2 pin >= 0.86 * BATTERY pin 0b11000 DCDC_4P2 pin >= BATTERY pin (default) 0b11111 DCDC_4P2 pin >= 1.05 * BATTERY pin i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 979 Power Memory Map/Register Definition 11.12.10 DC-DC Miscellaneous Register (HW_POWER_MISC) This register contains controls that may need to be adjusted to optimize DC-DC converter performance using the battery voltage information Address: 8004_4000h base + 90h offset = 8004_4090h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD2 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEST SEL_PLLCLK Bit 0 DELAY_TIMING Reset DISABLEFET_BO_LOGIC W 0 0 0 0 RSRVD2 R FREQSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_POWER_MISC field descriptions Field 31-7 RSRVD2 6-4 FREQSEL Description Reserved. This bit field selects the PLL/PFD based frequency that the DC-DC converter uses (i.e. DCDC_CLK) when SEL_PLLCLK is set to "1". The actual switching frequency driving the power inductor is DCDC_CLK/16. For FREQSEL = 0x4~0x7, need to program HW_CLKCTRL_FRAC1.GPMIFRAC and Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 980 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_MISC field descriptions (continued) Field Description HW_CLKCTRL_FRAC1.CLKGATEGPMI before using those values. FREQSEL must be programmed before setting SEL_PLLCLK to "1". 0x0: DCDC_CLK = ref_pll/16 = 30MHz 0x1: DCDC_CLK = ref_pll/24 = 20MHz 0x2: DCDC_CLK = ref_pll/20 = 24MHz 0x3: DCDC_CLK = ref_pll/25 = 19.2Hz 0x4: DCDC_CLK = ref_gpmi/16 0x5: DCDC_CLK = ref_gpmi/24 0x6: DCDC_CLK = ref_gpmi/20 0x7: DCDC_CLK = ref_gpmi/25 3 DISABLEFET_ BO_LOGIC This bit can be used to enable/disable the logic which stops the power-FETs in the DC-DC converter from switching when a brown-out condition is detected. 2 This bit delays the timing of the output fets in the switching dcdc converter. This may provide improved DELAY_TIMING ground noise performance in high power applications. 1 TEST 0 SEL_PLLCLK Reserved. Do not set. This bit selects the source of the clock used for the DC-DC converter. The default is to use the 24-MHz clock (ref_xtal). Setting this bit selects the PLL clock as a clock source for the DC-DC converter. It is required to program FREQSEL before setting this bit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 981 Power Memory Map/Register Definition 11.12.11 DC-DC Duty Cycle Limits Control Register (HW_POWER_DCLIMITS) This register defines the upper and lower duty cycle limits of DC-DC. These values depend on details of switching converter implementation and should not be changed without guidance from Freescale. Address: 8004_4000h base + A0h offset = 8004_40A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD3 R W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 RSRVD1 Bit 0 RSRVD2 Reset POSLIMIT_BUCK NEGLIMIT W Reset 0 0 0 0 1 1 0 0 0 1 0 1 1 HW_POWER_DCLIMITS field descriptions Field Description 31-16 RSRVD3 Reserved. 15 RSRVD2 Reserved. 14-8 POSLIMIT_ BUCK Upper limit duty cycle limit in DC-DC converter. This field will limit the maximum VDDIO acheivable for a given battery voltage, and it's value may be increased if very low battery operation is desired. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 982 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_DCLIMITS field descriptions (continued) Field Description 7 RSRVD1 Reserved. NEGLIMIT Negative duty cycle limit of DC-DC converter. 11.12.12 Converter Loop Behavior Control Register (HW_POWER_LOOPCTRL) This register defines the control loop parameters available for the DC-DC converter. HW_POWER_LOOPCTRL: 0x0B0 HW_POWER_LOOPCTRL_SET: 0x0B4 HW_POWER_LOOPCTRL_CLR: 0x0B8 HW_POWER_LOOPCTRL_TOG: 0x0BC 28 27 26 25 24 23 22 21 0 0 0 0 0 20 19 18 17 16 CM_HYST_THRESH 29 EN_DF_HYST 30 EN_CM_HYST 31 HYST_SIGN Bit TOGGLE_DIF Address: 8004_4000h base + B0h offset = 8004_40B0h 0 0 0 0 0 RSRVD3 R W Reset 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 983 0 0 13 12 11 10 9 8 7 6 5 4 RSRVD2 14 EN_RCSCALE R 15 RCSCALE_THRESH Bit DF_HYST_THRESH Power Memory Map/Register Definition 3 2 1 0 RSRVD1 DC_FF DC_R DC_C W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 1 HW_POWER_LOOPCTRL field descriptions Field 31-21 RSRVD3 20 TOGGLE_DIF 19 HYST_SIGN Description Reserved. Set high to enable supply stepping to change only after the differential control loop has toggled as well. This should eliminate any chance of large transients when supply voltage changes are made. Invert the sign of the hysteresis in DC-DC analog comparators. This bit should set when using PFM mode. 18 EN_CM_HYST Enable hysteresis in switching converter common mode analog comparator. This feature will improve transient supply ripple and efficiency. 17 EN_DF_HYST Enable hysteresis in switching converter differential mode analog comparators. This feature will improve transient supply ripple and efficiency. 16 CM_HYST_ THRESH Increase the threshold detection for common mode analog comparator. 15 DF_HYST_ THRESH Increase the threshold detection for common mode analog comparator. 14 RCSCALE_ THRESH Increase the threshold detection for RC scale circuit. 13-12 EN_RCSCALE Enable analog circuit of DC-DC converter to respond faster under transient load conditions. 00: disabled 01: 2X increase 10: 4X increase 11: 8X increase Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 984 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_LOOPCTRL field descriptions (continued) Field 11 RSRVD2 Description Reserved. 10-8 DC_FF Two's complement feed forward step in duty cycle in the switching DC-DC converter. Each time this field makes a transition from 0x0, the loop filter of the DC-DC converter is stepped once by a value proportional to the change. This can be used to force a certain control loop behavior, such as improving response under known heavy load transients. 7-4 DC_R Magnitude of proportional control parameter in the switching DC-DC converter control loop. 3-2 RSRVD1 DC_C Reserved. Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response. 00: Maximum 01: Decrease ratio 2X 10: Decrease ratio 4X 11: Lowest ratio. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 985 Power Memory Map/Register Definition 11.12.13 Power Subsystem Status Register (HW_POWER_STS) This register contains status information for the battery charger, DCDC converter and USB/OTG connections. 29 28 RSRVD3 27 26 25 24 PWRUP_SOURCE 23 22 RSRVD2 20 19 18 17 16 PSWITCH BVALID0_STATUS R 30 AVALID0_STATUS 31 VDDMEM_BO Bit THERMAL_WARNING Address: 8004_4000h base + C0h offset = 8004_40C0h 21 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 986 Freescale Semiconductor, Inc. 10 9 8 7 6 5 4 VDD5V_FAULT CHRGSTS DCDC_4P2_BO DC_OK VDDIO_BO VDDA_BO VDDD_BO VDD5V_GT_VDDIO VDD5V_DROOP 0 0 0 0 0 0 1 0 0 0 0 0 3 2 1 0 SESSEND0 11 VBUSVALID0 12 BVALID0 13 AVALID0 14 BATT_BO R 15 SESSEND0_STATUS Bit VBUSVALID0_STATUS Chapter 11 Power Supply 0 0 0 0 W Reset HW_POWER_STS field descriptions Field Description 31-30 RSRVD3 Reserved. 29-24 PWRUP_ SOURCE These read-only bits determine which source was active when the dcdc converter powerup sequence was complete. This can be used to determine what event caused the device to powerup. bit5 : five volts bit4 : rtc wakeup bit3 : reserved bit2 : reserved bit1 : high level pswitch voltage bit0 : midlevel pswitch voltage 23-22 RSRVD2 Reserved. 21-20 PSWITCH These read-only bits reflect the current state of the pswitch comparators. The lsb is high when voltage on the PSWITCH pin is above 0.8V, and the msb is high when the voltage on the PSWITCH pin is above 1.75V 19 THERMAL_ WARNING Asserting this signal is a last warning to the cpu before the temp sensor shuts down the power system . It will be asserted at a small temperature offset below the chip thermal limit. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 987 Power Memory Map/Register Definition HW_POWER_STS field descriptions (continued) Field 18 VDDMEM_BO Description Output of VDDMEM brownout comparator. High when a brownout is detected. This comparator's powerup/power-down follows the VDDMEM regulator power-up. 17 AVALID0_ STATUS Indicates VBus is valid for a A-peripheral. This bit is a read only version of the state of the analog signal. It can not be overwritten by software like the AVALID bit below. 16 BVALID0_ STATUS Indicates VBus is valid for a B-peripheral. This bit is a read only version of the state of the analog signal. It can not be overwritten by software like the BVALID bit below. 15 VBUSVALID0_ STATUS 14 SESSEND0_ STATUS 13 BATT_BO VBus valid for USB OTG. This bit is a read only version of the state of the analog signal. It can not be overwritten by software like the VBUSVALID bit below. Session End for USB OTG. This bit is a read only version of the state of the analog signal. It can not be overwritten by software like the SESSEND bit below. NOTE: This bit's default value depends on whether VDD5V is present, 0 if VDD5V presents, 1 if VDD5V not presents. Output of battery brownout comparator. 12 Battery charging fault status. If the battery charger is not powered down, the bit is high when the 5V supply VDD5V_FAULT falls below the battery voltage. If the charger is powered down, the bit asserts high when 5V falls to below roughly VDDIO/2. If the charger is not powered down, the bit is sticky and remains set until the PWD_CHARGE_4P2 bit is cycled. Otherwise, the bit is cleared when 5V is restored. NOTE: The default value depends on whether VDD5V is present, 0 if 5V presents, 1 if 5V not presents. 11 CHRGSTS Battery charging status. High during Li-Ion battery charge until the charging current falls below the STOP_ILIMIT threshold. 10 Output of the brownout comparator on the DCDC_4P2 pin. DCDC_4P2_BO 9 DC_OK High when switching DC-DC converter control loop has stabilized after a voltage target change. When linear regulators are active, this bit goes high when the actual voltage is above the target voltage. Therefore, DC_OK will go high when changing a linear regulator output to a lower value before the actual voltage decreases to the new target value. 8 VDDIO_BO Output of VDDIO brownout comparator. High when a brownout is detected. This comparator defaults powered up, but can be powered down through the POWER_MINPWR register. 7 VDDA_BO Output of VDDA brownout comparator. High when a brownout is detected. It is not possible to power-down this comparator. 6 VDDD_BO Output of VDDD brownout comparator. High when a brownout is detected. It is not possible to powerdown this comparator. 5 VDD5V_GT_ VDDIO Indicates the voltage on the VDD5V pin is higher than VDDIO by a Vt voltage, nominally 500 mV. 4 Indicates the voltage on the VDD5V pin is below the VBUSDROOP_TRSH defined in the 5VCTRL VDD5V_DROOP register. 3 AVALID0 Indicates VBus is above the VA_SESS_VLD threshold, that is, high if VBus greater than 2.0, low if VBus less than 0.8, otherwise unknown. 2 BVALID0 Indicates VBus is above the VB_SESS_VLD threshold, high if VBus greater than 4.0, low if VBus less than 0.8, otherwise unknown. 1 VBUSVALID0 Accurate detection of the presence of 5v power. This can be used for detection of 5v in all modes of operation including USB OTG. See POWER_5VCTRL to enable and set threshold for comparison. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 988 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_STS field descriptions (continued) Field Description 0 SESSEND0 Indicates VBus is below the VB_SESS_END threshold, that is, 0 if VBus is greater than 0.8 V, 1 if VBus is less than 0.2 V, otherwise unknown. See POWER_5VCTRL to enable comparators. NOTE: This bit's default value depends on whether VDD5V is present, 0 if VDD5V presents, 1 if VDD5V not presents. 11.12.14 Transistor Speed Control and Status Register (HW_POWER_SPEED) This register contains the setup and controls needed to measure silicon speed. HW_POWER_SPEED: 0x0D0 HW_POWER_SPEED_SET: 0x0D4 HW_POWER_SPEED_CLR: 0x0D8 HW_POWER_SPEED_TOG: 0x0DC Address: 8004_4000h base + D0h offset = 8004_40D0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSRVD1 R 20 19 18 17 16 STATUS W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 STATUS R Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 RSRVD0 STATUS_ SEL W 0 0 0 0 CTRL 0 0 0 HW_POWER_SPEED field descriptions Field Description 31-24 RSRVD1 Reserved. 23-8 STATUS Result from the speed sensor. This result is only valid when SPEEDCTRL=0b11; otherwise this field contains debug information from the switching DC-DC converter. 7-6 STATUS_SEL 5-2 RSRVD0 CTRL Speed Sensor Status Select. This defines the meaning on the STATUS field in this register. 0x0 0x1 0x2 DCDC_STAT -- DC-DC speed sensor (lower 8 bits) CORE_STAT -- core logic speed sensor ARM_STAT -- arm9 speed sensor Reserved. Speed Control bits. 00: Speed sensor off, 0b01: Speed sensor enabled, 11: Enable speed sensor measurement. Every time a measurement is taken, the sequence of 0x00 ; 01 ; 11 must be repeated. This sequence should proceed no faster than 1.5 MHz to ensure proper operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 989 Power Memory Map/Register Definition 11.12.15 Battery Level Monitor Register (HW_POWER_BATTMONITOR) This register provides brownout controls and monitors the battery voltage. Address: 8004_4000h base + E0h offset = 8004_40E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD3 R BATT_VAL W 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD2 R W Reset 0 0 0 0 BRWNOUT_PWD 0 PWDN_BATTBRNOUT 0 EN_BATADJ Bit 0 PWDN_BATTBRNOUT_5VDETECT_ENABLE Reset 1 0 1 0 RSRVD1 BRWNOUT_LVL 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 990 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_BATTMONITOR field descriptions Field 31-26 RSRVD3 25-16 BATT_VAL 15-12 RSRVD2 11 PWDN_ BATTBRNOUT_ 5VDETECT_ ENABLE Description Reserved. Software should be configured to place the battery voltage in this register measured with an 8-mV LSB resolution through the LRADC. This value is used by the DC-DC converter and must be correct before setting EN_BATADJ. Reserved. Enable the use of the programmed 5V detect signal to gate off the powering down of the device when a battery brownout occurs. Clear this bit to power-down the device when a battery brown-out occurs regardless of the state of the 5 V detect signal. 10 EN_BATADJ This bit enables the DC-DC to improve efficiency and minimize ripple using the information from the BATT_VAL field. It is very important that BATT_VAL contain accurate information before setting EN_BATADJ. Note: HW_LRADC_CONVERSION_SCALE_FACTOR must be programmed to 0x2 before setting this bit to 0x1. 9 PWDN_ BATTBRNOUT Powers down the device after the DC-DC converter completes startup if a battery brownout occurs. This function is only active when 5V is not present. Additionally, software should clear this bit and disable this function after the system is configured for a battery brownout and the battery brownout interrupt is enabled. 8 BRWNOUT_ PWD Power-down circuitry for battery brownout detection. This bit should only be set when it is not important to montior battery brownouts and minimum system power consumption is required. 7-5 RSRVD1 Reserved. BRWNOUT_LVL The default setting of the brownout settings decode to a voltage as follows: Li-Ion = 2.4 V The voltage level can be calculated for other values by the following equation: Li-Ion brownout voltage = 2.4 V + 0.04 * BRWNOUT_LVL 11.12.16 Power Module Reset Register (HW_POWER_RESET) This register allows software to put the chip into the off state. HW_POWER_RESET: 0x100 HW_POWER_RESET_SET: 0x104 HW_POWER_RESET_CLR: 0x108 HW_POWER_RESET_TOG: 0x10C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 991 Power Memory Map/Register Definition Address: 8004_4000h base + 100h offset = 8004_4100h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R UNLOCK Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWD_OFF Reset FASTFALLPSWITCH_OFF W PWD 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_POWER_RESET field descriptions Field 31-16 UNLOCK Description Write 0x3E77 to unlock this register and allow other bits to be changed. NOTE: This register must be unlocked on a write-by-write basis, so the UNLOCK bitfield must contain the correct key value during all writes to this register in order to update any other bitfield values in the register. 0x3E77 KEY -- Key needed to unlock HW_POWER_RESET register. 15-3 RSRVD1 Reserved. 2 Set this bit to 1'b1 to disable the chip shutting down by a fast falling edge of PSWITCH. Setting this FASTFALLPSWITCH_ bit will be useful for preventing fast falling edges on the PSWITCH pin from resetting the chip. It may OFF also be useful increasing system tolerance of noisy EMI environments. 1 PWD_OFF 0 PWD Optional bit to disable all paths to power off the chip except the watchdog timer. Setting this bit will be useful for preventing fast falling edges on the PSWITCH pin from resetting the chip. It may also be useful increasing system tolerance of noisy EMI environments. Powers down the chip. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 992 Freescale Semiconductor, Inc. Chapter 11 Power Supply 11.12.17 Power Module Debug Register (HW_POWER_DEBUG) Debug Register. HW_POWER_DEBUG: 0x110 HW_POWER_DEBUG_SET: 0x114 HW_POWER_DEBUG_CLR: 0x118 HW_POWER_DEBUG_TOG: 0x11C Address: 8004_4000h base + 110h offset = 8004_4110h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BVALIDPIOLOCK SESSENDPIOLOCK Bit 0 AVALIDPIOLOCK Reset VBUSVALIDPIOLOCK W 0 0 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 HW_POWER_DEBUG field descriptions Field 31-4 RSRVD0 Description Reserved. 3 Reserved for Freescale Debugging Purposes Only. VBUSVALIDPIOLOCK Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 993 Power Memory Map/Register Definition HW_POWER_DEBUG field descriptions (continued) Field Description 2 AVALIDPIOLOCK Reserved for Freescale Debugging Purposes Only. 1 BVALIDPIOLOCK Reserved for Freescale Debugging Purposes Only. 0 SESSENDPIOLOCK Reserved for Freescale Debugging Purposes Only. 11.12.18 Power Module Thermal Reset Register (HW_POWER_THERMAL) Thermal Reset Register. HW_POWER_THERMAL: 0x120 HW_POWER_THERMAL_SET: 0x124 HW_POWER_THERMAL_CLR: 0x128 HW_POWER_THERMAL_TOG: 0x12C This register contains the controls for the thermal temp sensor that can be used to reset the chip when a temperature threshold is reached. Address: 8004_4000h base + 120h offset = 8004_4120h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 994 Freescale Semiconductor, Inc. Chapter 11 Power Supply 14 13 12 11 10 9 8 7 6 5 4 OFFSET_ADJ TEST PWD LOW_POWER RSRVD0 R W Reset 0 0 0 0 0 0 0 0 1 0 0 3 OFFSET_ADJ_ENABLE 15 Bit 0 0 2 1 0 TEMP_ THRESHOLD 0 0 0 HW_POWER_THERMAL field descriptions Field 31-9 RSRVD0 Description Reserved. 8 TEST This bit is used for debug purposes only. 7 PWD Power-down the thermal temp sensor block. 6 LOW_POWER Set to operate thermal temp sensor with less power. 5-4 OFFSET_ADJ Add offset to the programmed trip point. 00 adds 5degC, 01 adds 10degC, 10 subtracts 5degC, 11 subtracts 10degC. These are valid only when HW_POWER_THERMAL_OFFSET_ADJ_ENABLE=1 3 Enable the offset adjustment capability. OFFSET_ADJ_ ENABLE TEMP_ THRESHOLD This field programs the thermal reset trip point. A value of 000 sets to 115degC and 111 sets to 150degC. The intermediate values are in steps of 5degC. When TEST=1, all the trip points are set to 65degC less than their programmed values. 11.12.19 Power Module USB1 Manual Controls Register (HW_POWER_USB1CTRL) USB1 control Register. HW_POWER_USB1CTRL: 0x130 HW_POWER_USB1CTRL_SET: 0x134 HW_POWER_USB1CTRL_CLR: 0x138 HW_POWER_USB1CTRL_TOG: 0x13C This register contains the connection controls for the USB instance 1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 995 Power Memory Map/Register Definition Address: 8004_4000h base + 130h offset = 8004_4130h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VBUSVALID1 SESSEND1 Bit 0 BVALID1 Reset AVALID1 W 0 0 0 0 0 1 1 1 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 HW_POWER_USB1CTRL field descriptions Field Description 31-4 RSRVD0 Reserved. 3 AVALID1 This bit indicates the value for the sessend signal for USB instance 1. It is analogous to the HW_POWER_STS_AVALID0 bit but this bit is not set by the hardware. It is controlled by software. 2 BVALID1 This bit indicates the value for the sessend signal for USB instance 1. It is analogous to the HW_POWER_STS_BVALID0 bit but this bit is not set by the hardware. It is controlled by software. 1 VBUSVALID1 0 SESSEND1 This bit indicates the value for the vbusvalid signal for USB instance 1. It is analogous to the HW_POWER_STS_VBUSVALID0 bit but this bit is not set by the hardware. It is controlled by software. This bit indicates the value for the sessend signal for USB instance 1. It is analogous to the HW_POWER_STS_SESSEND0 bit but this bit is not set by the hardware. It is controlled by software. 11.12.20 Power Module Special Register (HW_POWER_SPECIAL) Special test functionality. HW_POWER_SPECIAL: 0x140 HW_POWER_SPECIAL_SET: 0x144 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 996 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_SPECIAL_CLR: 0x148 HW_POWER_SPECIAL_TOG: 0x14C Address: 8004_4000h base + 140h offset = 8004_4140h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_POWER_SPECIAL field descriptions Field Description TEST Reserved for Freescale Debugging Purposes Only 11.12.21 Power Module Version Register (HW_POWER_VERSION) This register always returns a known read value for debug purposes it indicates the version of the block. This register indicates the RTL version in use. Address: 8004_4000h base + 150h offset = 8004_4150h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_POWER_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. 11.12.22 Analog Clock Control Register (HW_POWER_ANACLKCTRL) HW_POWER_ANACLKCTRL: 0x160 HW_POWER_ANACLKCTRL_SET: 0x164 HW_POWER_ANACLKCTRL_CLR: 0x168 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 997 Power Memory Map/Register Definition HW_POWER_ANACLKCTRL_TOG: 0x16C This register provides analog clock control. Address: 8004_4000h base + 160h offset = 8004_4160h 31 30 29 28 24 23 22 21 20 19 18 17 16 0 0 0 1 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLOW_DITHER INVERT_INCLK RSRVD4 R 1 0 0 RSRVD2 CKGATE_I RSRVD4 0 CKGATE_O Bit 25 1 OUTDIV W Reset 26 INVERT_OUTCLK R 27 DITHER_OFF Bit RSRVD3 INCLK_ SHIFT INDIV W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_POWER_ANACLKCTRL field descriptions Field 31 CKGATE_O Description Analog Output Clock Gate, Reserved for Freescale Debugging Purposes Only 30-28 OUTDIV Analog Output Clock Divider, Reserved for Freescale Debugging Purposes Only 27 INVERT_ OUTCLK Analog Output Clock Invert, Reserved for Freescale Debugging Purposes Only Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 998 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_ANACLKCTRL field descriptions (continued) Field 26 CKGATE_I 25-11 RSRVD4 10 DITHER_OFF Description Analog Input Clock Gate, Reserved for Freescale Debugging Purposes Only Reserved Clock Dither Disable, Reserved for Freescale Debugging Purposes Only 9 Set 0x1 to make the configuration INDIV<1:0> and INCLK_SHIFT available, but there would be <= 0.67us SLOW_DITHER timing delay between HSADC start conversion and `start run' command from software trigger or PWM trigger. If this delay is not desired, it is recommended to set INDIV<1:0> to 0x2 and using PWM trigger for HSADC. 8 Analog Input Clock Invert, Reserved for Freescale Debugging Purposes Only INVERT_INCLK 7-6 RSRVD3 5-4 INCLK_SHIFT 3 RSRVD2 INDIV Reserved Recommended value 0x2 when HSADC works at 1.5 MHz sampling rate with DCDC working. This configuration can attenuate the impact of DCDC noise on HSADC performance only when HSADC working at 1.5 MHz sampling rate, and the configuration is available only when set SLOW_DITHER to 0x1. Reserved INDIV<2>: Set 1 for HSADC working at 1.5 MHz sampling rate. INDIV<1:0>: Recommended value 0x2 when HSADC works at 1.5 MHz sampling rate with DCDC working. This configuration can attenuate the impact of DCDC noise on HSADC performance only when HSADC working at 1.5 MHz sampling rate, and the configuration is available when set SLOW_DITHER to 0x1 or using PWM trigger for HSADC. 11.12.23 POWER Reference Control Register (HW_POWER_REFCTRL) This register provides control bits for changing analog voltage and current references. HW_POWER_REFCTRL: 0x170 HW_POWER_REFCTRL_SET: 0x174 HW_POWER_REFCTRL_CLR: 0x178 HW_POWER_REFCTRL_TOG: 0x17C The power reference control register provides control over the voltage and power for the analog circuits. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 999 Power Memory Map/Register Definition Address: 8004_4000h base + 170h offset = 8004_4170h 30 29 28 27 RSRVD5 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOW_PWR XTAL_BGR_BIAS 24 RAISE_REF 25 FASTSETTLING R 26 RSRVD3 31 RSRVD4 Bit VBG_ADJ BIAS_CTRL Bit R VDDXTAL_TO_VDDD Reset RSRVD2 W RSRVD1 ADJ_ ADJ_ ANA VAG ANA_REFVAL VAG_VAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_POWER_REFCTRL field descriptions Field 31-27 RSRVD5 Description Reserved. Always write zeroes to this bit field. 26 Set to high to detect the existence of battery. After this bit is set to high, if no battery brownout is detected, FASTSETTLING then the battery really exists. Reset this bit to low after complete detecting. 25 RAISE_REF Reserved for Freescale Debugging Purposes Only Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1000 Freescale Semiconductor, Inc. Chapter 11 Power Supply HW_POWER_REFCTRL field descriptions (continued) Field Description 24 XTAL_BGR_ BIAS Switch the XTAL bias from self-bias to bandgap-based bias current. Also switches the source of the XTAL supply to the core supply to save power. Note that this bit is not reset by the POWER's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. 23 RSRVD4 Reserved. Always write zeroes to this bit field. 22-20 VBG_ADJ Small adjustment for VBG value. Will affect ALL reference voltages. Expected to be used to tweak final LiIon charge voltage. 000=Nominal. 001=+0.3%. 010=+0.6%. 011=0.85%. 100=-0.3%. 101=-0.6%. 110=-0.9%. 111=-1.2%. Note that this bit is not reset by the POWER's SFTRST bit. It is reset by a poweron reset only, and CLKGATE has no effect on reads/writes. 19 LOW_PWR Lowers power (~100 uA) in the bandgap amplifier. This mode is useful in USB suspend or standby when bandgap accuracy is not critical. Note that this bit is not reset by the POWER's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. 18 RSRVD3 17-16 BIAS_CTRL 15 RSRVD2 Reserved. Always write zeroes to this bit field. Bias current control for all analog blocks: 00=Nominal. 01=-20%. 10=-10%. 11=+10%. Note that this bit not reset by the POWER's SFTRST bit. It is reset by a power-on reset only, and CLKGATE has no effect on reads/writes. These bits should only be used for test/debug, and not in an application. Reserved. Always write zeroes to this bit field. 14 Shorts the supply of the XTAL oscillator to VDDD. This bit may be used to reduce power consumption, but VDDXTAL_TO_ should only be used on the advice of Freescale. VDDD 13 ADJ_ANA Reserved for Freescale Debugging Purposes Only 12 ADJ_VAG Reserved for Freescale Debugging Purposes Only 11-8 ANA_REFVAL Reserved for Freescale Debugging Purposes Only 7-4 VAG_VAL Reserved for Freescale Debugging Purposes Only RSRVD1 Reserved. Always write zeroes to this bit field. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1001 Power Memory Map/Register Definition i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1002 Freescale Semiconductor, Inc. Chapter 12 Boot Modes 12.1 Overview The i.MX28 boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM logic reads hardware inputs such as the boot pins on the IC or OCOTP bits to determine the boot flow behavior of the i.MX28. The main features of the ROM include: * Support for booting from various boot devices * USB recovery support * Encrypted boot image * Device Configuration Data (DCD) support in boot image * Digital signature based High Assurance Boot (HAB) * Secondary boot from NAND and SD/MMC boot devices The i.MX28 boot ROM supports the following boot devices: * * * * NAND Flash ONFI 2.x BA-NAND SD/eSD/MMC/eMMC Serial ROM devices, including SPI NOR/EEPROM and I2C EEPROM Secure Boot A key feature of the i.MX28 ROM is the ability to perform a secure boot. This is supported by * The encrypted boot feature and * The High Assurance Boot (HAB) These are independent features and are not dependent on each other. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1003 Boot Modes The encrypted boot feature is an inherent element of the SB boot format used by the i.MX28 ROM. The encrypted boot feature is easily enabled through the use of tools provided by Freescale to provide image confidentiality.. A HAB secure boot makes use of a security library which is a subcomponent of the i.MX28 ROM. The HAB uses a combination of hardware and software together with a Public Key Infrastructure (PKI) protocol to protect the system from executing unauthorized programs. HAB differs from the encrypted boot feature in that image authentication is performed. Before the HAB allows a user's image to execute, the image must be signed. The signing process is done during the image build process by the private key holder and the signatures are then included as part of the final Program Image. If configured to do so, the i.MX28 verifies the signatures using the public keys included in the Program Image. A secure boot with HAB can be performed on all boot devices supported on i.MX28. The HAB library in the i.MX28 boot ROM also provides API functions, allowing additional boot chain components (bootloaders) to extend the secure boot chain. The out-of-fab setting for SEC_CONFIG is the Open configuration in which the ROM/HAB performs image authentication but all authentication errors are ignored and the image is still allowed to execute. The remainder of this chapter provides information on above features and boot modes and how to configure and use boot features of i.MX28 ROM. 12.2 Boot Modes Table 12-1 lists all the boot modes supported by i.MX28 ROM. The boot mode can be selected either through external resistors or through OTP eFuse bit programming. Table 12-1. Boot Modes PORT BOOT MODE USB Encrypted/unencrypted USB slave boot mode. I2C Encrypted/unencrypted I2C0 master--Boots from 1.8- and 3.3-V EEPROM. SPI2 Encrypted/unencrypted SPI2 master from SSP2--Boots from 1.8- and 3.3-V flash memory. SPI3 Encrypted/unencrypted SPI3 master from SSP3--Boots from 1.8- and 3.3-V flash and EEPROM. SSP0 Encrypted/unencrypted SD/MMC master from SSP1--Boots from 1.8- and 3.3-V 1-bit, 4-bit, and 8bit SD/MMC/eSD/eMMC cards. SSP1 Encrypted/unencrypted SD/MMC master from SSP2--Boots from 1.8- and 3.3-V 1-bit, 4-bit, and 8bit SD/MMC/eSD/eMMC cards. GPMI Encrypted/unencrypted NAND, 1.8- and 3.3-V, 8-bit wide, BCH2 to BCH20. JTAG Wait JTAG connection i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1004 Freescale Semiconductor, Inc. Chapter 12 Boot Modes 12.2.1 Boot Pins Definition and Mode Selection Boot pins are located on LCD_RS, LCD_DATA[5:0]. To enable boot mode selection from the LCD data pins, pull up LCD_RS. The ROM probes the LCD_RS pin and then, if valid, decodes the boot mode vector from the pins LCD_DATA[3:0], and LCD_DATA[4] is blown to support 1.8 boot device. If LCD_RS is pulled down, then the boot mode is determined by the OTP eFuse bits, as defined in Table 12-4. The following table shows the boot pins, and Table 12-3 lists the boot mode vectors. Table 12-2. Boot Pins PIN Name BOOT FUNCTION Bit Name LCD_RS Determines if there is a need to examine the other boot pins. LCD_DATA[6] Reserved TBM2 LCD_DATA[5] Reserved TBM1 LCD_DATA[4] Voltage Selector TBM0 LCD_DATA[3] Boot Mode Bit 3 BM3 LCD_DATA[2] Boot Mode Bit 2 BM2 LCD_DATA[1] Boot Mode Bit 1 BM1 LCD_DATA[0] Boot Mode Bit 0 BM0 These pads are powered during the initial startup sequence. The pads are enabled as GPIOs for sensing and then disabled. However, the pads remain powered. 12.2.2 Boot Mode Selection Map Table 12-3. Boot Mode Selection Map VOLTAG E SELECT( BM4)/ BM3/ BM2/ BM1/ BM0/ LCD_ LCD_ LCD_ LCD_ LCD_ LCD_ D05 D04 D03 D02 D01 D00 x x 0 0 0 x 0 0 0 x 1 0 0 PORT BOOT MODE 0 USB0 USB (unencrypted vs. encrypted is under OTP control) 0 1 I2C0 I2C0 master, 3.3 V 0 1 I2C0 I2C0 master, 1.8 V Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1005 OTP eFuse and Persistent Bit Definitions Table 12-3. Boot Mode Selection Map (continued) VOLTAG E SELECT( BM4)/ BM3/ BM2/ BM1/ BM0/ LCD_ LCD_ LCD_ LCD_ LCD_ LCD_ D05 D04 D03 D02 D01 D00 x 0 0 0 1 x 1 0 0 x 0 0 x 1 x PORT BOOT MODE 0 SPI2 SPI master SSP2 boot from flash, 3.3 V 1 0 SPI2 SPI master SSP2 boot from flash, 1.8 V 0 1 1 SPI3 SPI master SSP3 boot from flash, 3.3 V 0 0 1 1 SPI3 SPI master SSP3 boot from flash, 1.8 V 0 0 1 0 0 GPMI NAND, 3.3 V x 1 0 1 0 0 GPMI NAND, 1.8 V x 0 0 1 0 1 x 0 0 1 1 0 x 0 0 1 1 1 x 0 1 0 0 0 SPI3 SPI master SSP3 boot from EEPROM, 3.3 V x 1 1 0 0 0 SPI3 SPI master SSP3 boot from EEPROM, 1.8 V x 0 1 0 0 1 SSP0 SD/MMC master on SSP0, 3.3 V x 1 1 0 0 1 SSP0 SD/MMC master on SSP0 1.8 V x 0 1 0 1 0 SSP1 SD/MMC master on SSP1, 3.3 V x 1 1 0 1 0 SSP1 SD/MMC master on SSP1, 1.8 V x 0 1 0 1 1 Reserved x 0 1 1 0 0 Reserved x 0 1 1 0 1 Reserved x 0 1 1 1 0 Reserved x 0 1 1 1 1 Reserved Reserved JTAG Wait JTAG connection mode Reserved 12.3 OTP eFuse and Persistent Bit Definitions This section provides tables that show the location and function of the OTP eFuse and persistent bits. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1006 Freescale Semiconductor, Inc. Chapter 12 Boot Modes 12.3.1 OTP eFuse The device contains a 1280-bit array of OTP eFuse bits, some of which are used by ROM. The bits listed in Table 12-4 - Table 12-6 can be configured by the customers and are typically programmed on the customer's board assembly line. For more information about the OTP bits, see OCOTP Overview. Table 12-4. General ROM Bits eFuse eFuse Function Bank:Address:Bit HW_OCOTP_ROM0:0x8002C1A0:31:24 Boot Modes OCOTP bits. See Boot Mode Selection Map for definitions. HW_OCOTP_ROM0:0x8002C1A0:23:22 SD_MMC_MODE[1:0] 00 = MBR 01 = RESERVED 10 = eMMC fast boot 11 = eSD fast boot HW_OCOTP_ROM0:0x8002C1A0:21:20 POWER_GATE_GPIO-SD/MMC card power gate GPIO pin select. 00 = PWM3 01 = PWM4 10 = LCD_DOTCLK 11 = NO_GATE HW_OCOTP_ROM0:0x8002C1A0:19:14 POWER_UP_DELAY--SD/MMC card power up delay required after enabling GPIO power gate. 000000 = 20 ms (default) 000001 = 10 ms 000010 = 20 ms .... 111111 = 630 ms HW_OCOTP_ROM0:0x8002C1A0:13:12 SD_BUS_WIDTH--SD/MMC card bus width. 00 = 4-bit 01 = 1-bit 10 = 8-bit 11 = Reserved HW_OCOTP_ROM0:0x8002C1A0:11:8 Index to SSP clock speed. By default (0x0), the clock speed is set to 12 MHz. The value of the index will modify the SPI clock speed accordingly. HW_OCOTP_ROM0:0x8002C1A0:7 EMMC_USE_DDR - Blow to enable DDR access mode when fast boot from eMMC4.4 card. HW_OCOTP_ROM0:0x8002C1A0:6 DISABLE_SPI_NOR_FAST_READ--Blow to disable SPI NOR fast reads, which are used by default. Some SPI NORs do not support this functionality. HW_OCOTP_ROM0:0x8002C1A0:5 ENABLE_USB_BOOT_SERIAL_NUMBER--If set, the device serial number is reported to the host during USB boot mode initialization, else no serial number is reported. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1007 OTP eFuse and Persistent Bit Definitions Table 12-4. General ROM Bits (continued) eFuse eFuse Function Bank:Address:Bit HW_OCOTP_ROM0:0x8002C1A0:4 ENABLE_UNENCRYPTED_BOOT--If clear, allows only booting of encrypted images. If set, both encrypted/unencrypted images are valid. HW_OCOTP_ROM0:0x8002C1A0:3 Reserved. HW_OCOTP_ROM0:0x8002C1A0:2 DISABLE_RECOVERY_MODE--If set, does not allow booting in recovery mode. HW_OCOTP_ROM0:0x8002C1A0:1:0 USE_ALT_DEBUG_UART_PINS[1:0] 00 - PWM 01 - AUART0 10 - I2C0 11 - reserved Table 12-5. NAND/SD-MMC-Related Bits eFuse eFuse Function Bank:Address:Bit HW_OCOTP_ROM1:0x8002C1B0:30 DISABLE_SECONDARY_BOOT - Blow this bit to disable the secondary boot. HW_OCOTP_ROM1:0x8002C1B0:29 SSP3_EXT_PULLUP - Blow this bit to disable the internal pull-ups for SSP3 DATA and CMD signals. HW_OCOTP_ROM1:0x8002C1B0:28 SSP2_EXT_PULLUP - Blow this bit to disable the internal pull-ups for SSP2 DATA and CMD signals. HW_OCOTP_ROM1:0x8002C1B0:27 ENABLE_NAND7_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE7 and GPMI_RDY7 pins. HW_OCOTP_ROM1:0x8002C1B0:26 ENABLE_NAND6_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE6 and GPMI_RDY6 pins. HW_OCOTP_ROM1:0x8002C1B0:25 ENABLE_NAND5_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE5 and GPMI_RDY5 pins. HW_OCOTP_ROM1:0x8002C1B0:24 ENABLE_NAND4_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE4 and GPMI_RDY4 pins. HW_OCOTP_ROM1:0x8002C1B0:23 ENABLE_NAND3_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE3 and GPMI_RDY3 pins. HW_OCOTP_ROM1:0x8002C1B0:22 ENABLE_NAND2_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE2 and GPMI_RDY2 pins. HW_OCOTP_ROM1:0x8002C1B0:21 ENABLE_NAND1_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE1 and GPMI_RDY1 pins. HW_OCOTP_ROM1:0x8002C1B0:20 ENABLE_NAND0_CE_RDY_PULLUP - If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE0 and GPMI_RDY0 pins. HW_OCOTP_ROM1:0x8002C1B0:19 UNTOUCH_INTERNAL_SSP_PULLUP - If this bit is blown, the internal pull-ups will not be disabled even if SSP0_EXT_PULLUP, SSP1_EXT_PULLUP, SSP2_EXT_PULLUP, or SSP3_EXT_PULLUP is blown. HW_OCOTP_ROM1:0x8002C1B0:18 SSP1_EXT_PULLUP - Blow this bit to disable the internal pull-ups for SSP1 DATA and CMD signals. HW_OCOTP_ROM1:0x8002C1B0:17 SSP0_EXT_PULLUP - Blow this bit to disable the internal pull-ups for SSP0 DATA and CMD signals. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1008 Freescale Semiconductor, Inc. Chapter 12 Boot Modes Table 12-5. NAND/SD-MMC-Related Bits (continued) eFuse eFuse Function Bank:Address:Bit HW_OCOTP_ROM1:0x8002C1B0:16 SD_INCREASE_INIT_SEQ_TIME - Blow to increase the SD card initialization sequence time from 1 ms (default) to 4 ms. HW_OCOTP_ROM1:0x8002C1B0:15 SD_INIT_SEQ_2_ENABLE - Blow to enable the second initialization sequence for SD boot. HW_OCOTP_ROM1:0x8002C1B0:14 SD_CMD0_DISABLE - Cmd0 (reset cmd) is called by default to reset the SD card during startup. Blow this bit to not to reset the card during SD boot. HW_OCOTP_ROM1:0x8002C1B0:13 SD_INIT_SEQ_1_DISABLE - Blow to disable the first initialization sequence for SD. HW_OCOTP_ROM1:0x8002C1B0:11:8 BOOT_SEARCH_COUNT - Number of 64-page blocks skipped by the NAND driver when searching for information saved into the NAND (see NAND Boot Mode for details). Default value of 0 means 4 blocks to skip. HW_OCOTP_ROM1:0x8002C1B0:7:4 BOOT_SEARCH_STRIDE - the value of these bits is multiplied by 64 to get boot search stride. The default is 1 boot search stride, that is, 64 pages. HW_OCOTP_ROM1:0x8002C1B0:2:0 NUMBER_OF_NANDS - Indicates the number of external NANDs. A 0 value means that the NAND driver will scan the chip selects to dynamically find the correct number of NANDs. Table 12-6. USB-Related Bits eFuse eFuse Function Bank:Address:Bit HW_OCOTP_ROM2:0x8002C1C0:31:16 USB_VID--Vendor ID used in recovery mode. If the field is 0, Freescale vendor ID is used. HW_OCOTP_ROM2:0x8002C1C0:15:0 USB_PID--Product ID used in recovery mode. Table 12-7. eMMC Fast Boot-Related Bits eFuse eFuse Function Bank:Address:Bit HW_OCOTP_ROM3:0x8002C1D0:11 FAST_BOOT_ACK--Enable the fast boot acknowledge. HW_OCOTP_ROM3:0x8002C1D0:10 ALT_FAST_BOOT--Enable the alternative fast boot mode. Table 12-8. NAND Access-Related Bits eFuse eFuse Function Bank:Address:Bit HW_OCOTP_ROM4:0x8002C1E0:31 NAND_BADBLOCK_MARKER_RESERVE If this bit is blown, the factory bad block marker preservation will be disabled. HW_OCOTP_ROM4:0x8002C1E0:23:16 NAND_READ_CMD_CODE2 NAND Flash read command confirm code. HW_OCOTP_ROM4:0x8002C1E0:15:8 NAND_READ_CMD_CODE1 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1009 OTP eFuse and Persistent Bit Definitions Table 12-8. NAND Access-Related Bits (continued) eFuse eFuse Function Bank:Address:Bit NAND Flash read command setup code. HW_OCOTP_ROM4:0x8002C1E0:7:4 NAND_COLUMN_ADDRESS_BYTES NAND Flash column address cycles. HW_OCOTP_ROM4:0x8002C1E0:3:0 NAND_ROW_ADDRESS_BYTES NAND Flash row address cycles. Table 12-9. General ROM Bit in ROM7 OCOTP Bank eFuse eFuse Function Bank:Address:Bit HW_OCOTP_ROM7:0x8002C210:23 Reserved HW_OCOTP_ROM7:0x8002C210:22 ARM_PLL_DISABLE PLL is enabled by default, the ARM clock will run at 240 MHz. If blown, the PLL will be disabled and ROM will run at 24 MHz during the boot except for USB mode. HW_OCOTP_ROM7:0x8002C210:21:20 HAB_CONFIG 00 = Reserved 01 = HAB_OPEN, default mode Other = HAB_CLOSED HW_OCOTP_ROM7:0x8002C210:19:12 Reserved HW_OCOTP_ROM7:0x8002C210:8 ENABLE_SSP_12MA_DRIVE Blow to force SSP pins to drive 12 mA, default is 4 mA. HW_OCOTP_ROM7:0x8002C210:7:4 Reserved. HW_OCOTP_ROM7:0x8002C210:3 I2C_USE_400 KHZ Blow to force the I2C to be programmed by the boot loader to run at 400 KHz. 100 KHz is the default. HW_OCOTP_ROM7:0x8002C210:2 ENABLE_ARM_ICACHE Blow to enable the ARM 926 ICache during boot. HW_OCOTP_ROM7:0x8002C210:1 MMU_DISABLE 0 =MMU and D-Cache are enabled in default to speed up HAB functions execution speed. 1 =MMU and D-Cache are disabled during boot if blown. HW_OCOTP_ROM7:0x8002C210:0 ENABLE_PIN_BOOT_CHECK Blow to enable boot loader to first test the LCD_RS pin to determine if the pin boot mode is enabled. If this bit is blown and LCD_RS is pulled high, then boot mode is determined by the state of LCD_D[5:0] pins. If this bit is not blown, skip testing the LCD_RS pin and go directly to determine the boot mode by reading the state of LCD_D[5:0]. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1010 Freescale Semiconductor, Inc. Chapter 12 Boot Modes The following bits are used to store super root key hash value, which will be used by the ROM HAB (high assurance boot) library to check the boot image has the correct super root key. The SRK hash value will be read by the ARM CPU, so those registers are shadowed and can also be locked. If HAB is not used, these fuses can be used for other purposes. Table 12-10. Super Root Key Hash Bits eFuse eFuse Function Bank:Add:Bit HW_OCOTP_SRK0: 0x8002C220:31:0 Super Root Key hash value bits 255-254 HW_OCOTP_SRK1: 0x8002C230:31:0 Super Root Key hash value bits 223-192 HW_OCOTP_SRK2: 0x8002C240:31:0 Super Root Key hash value bits 191-160 HW_OCOTP_SRK3: 0x8002C250:31:0 Super Root Key hash value bits 159-128 HW_OCOTP_SRK4: 0x8002C260:31:0 Super Root Key hash value bits 127-96 HW_OCOTP_SRK5: 0x8002C270:31:0 Super Root Key hash value bits 95-64 HW_OCOTP_SRK6: 0x8002C280:31:0 Super Root Key hash value bits 63-32 HW_OCOTP_SRK7: 0x8002C290:31:0 Super Root Key hash value bits 31-0 12.3.2 Persistent Bits Persistent bits are used to control certain features in ROM, as shown in Table 12-11. For more information on persistent bits, see RTC Overview. Table 12-11. Persistent Bits Persistent Bit Function HW_RTC_PERSISTENT1:0x8005C070:3 SD_SPEED_ENABLE--If this bit is set, ROM puts the SD/MMC card in high-speed mode. HW_RTC_PERSISTENT1:0x8005C070:2 NAND_SDK_BLOCK_REWRITE--The NAND driver sets this bit to indicate to the SDK that the boot image has ECC errors that reached the warning threshold. The SDK regenerates the firmware by copying it from the backup image. The SDK clears this bit. HW_RTC_PERSISTENT1:0x8005C070:1 ROM_SECONDARY_BOOT--When this bit is set, ROM attempts to boot from the secondary image if the boot driver supports it. This bit is set by the ROM boot driver and cleared by the SDK after repair. HW_RTC_PERSISTENT1:0x8005C070:0 FORCE_RECOVERY--When this bit is set, the ROM code forces the system to boot in recovery mode, regardless of the selected mode. The ROM clears the bit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1011 Memory Map 12.4 Memory Map The illustration below shows the memory map of the boot loader. ROM boot code resides in the top 128 K address space. The boot code uses the top 16 K of OCRAM for MMU first level page table. The lowest 57K of OCRAM is used for loading application data. The 42 KB of OCRAM region called "ROM Data" is used for data by ROM code. If a system uses external memory, then a boot image may be created which first loads a small SDRAM initialization program into OCRAM. The program will set up the SDRAM, and then the rest of the boot image may continue to load, overwriting the initialization program in OCRAM. 0xFFFF_FFFF First Level Page Table(16kB) RESERVED (9kB) 0x0001_FFFF 0x0001_C000 0x0001_BFFF 0x0001_9 C00 0x0001_9 BFC ROM Data (42kB) 0x0000_F400 Boot ROM Code Vector table @0xFFFF_0000 0x0000_F3FC RESERVED(4kB) 0x0000_E400 0x0000_E3FC Application Load Region (57kB) 0xFFFE_0000 OCROM 0x0000_0000 OCRAM Figure 12-1. i.MX28 ROM Code Memory Map i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1012 Freescale Semiconductor, Inc. Chapter 12 Boot Modes 12.5 General Boot Procedure During ROM startup, the boot mode is sampled by boot pins, and then the ROM loader will take control. The ROM loader first calls an initialization function for the selected boot driver, which initializes the hardware port and external device corresponding to the boot mode. After that, the loader requests for the stream of boot image data from the driver. The boot image contains a stream of boot commands, such as LOAD, LOAD DCD, SKIP, HAB JUMP and HAB CALL commands. The loader implemented in ROM code will interpret these commands and load the boot image into memory and execute HAB JUMP or HAB CALL command. In the case of HAB JUMP, the ROM will pass control to the boot image and will leave the ROM context. Boot images can be encrypted and customers have full control over the encryption keys through the CRYPTO_KEY OTP fuse bits. Encryption can be turned on/off by ENABLE_UNENCRYPTED_BOOT fuse (boot unencrypted image if the fuse is blown). Also, the HAB_CONFIG fuse (01'b for HAB_OPEN and 10'b and 11'b for HAB_CLOSED) control the type of HAB security type. If HAB_CONFIG is programmed as HAB_CLOSED, the boot image will not be executed unless the HAB authenticates the boot image. If HAB_CONFIG is programmed as HAB_Open , the boot image will be executed even if the HAB authentication fails. The Open configuration is used for non-secure products or for development purposes on secure products. Customers have the control over the HAB super root key hash through HW_OTP_SRK fuses, which will be used to compare the DCP SHA-256 generated super root key (public key) hash from the boot image. To accelerate the boot process, the MMU/d-cache is enabled during the time consuming HAB authentication process (RSA). This feature can be turned off by blowing the MMU_DISABLE fuse. For the same purpose of speeding boot, the ARM clock has been boosted from 24 MHz to 240 MHz. The feature could be disabled by blowing the ARM_PLL_DISABLE fuse. The i-Cache can be turned on by blowing the ENABLE_ARM_ICACHE fuse. 12.6 Program Image This section describes the data structures that are required to be included in a user's Program Image. A Program Image consists of: * Image Vector Table - a list of pointers that the ROM examines to determine where other components of the program image are located. * Boot Data: This field is not used on i.MX28 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1013 Program Image * Device Configuration Data: IC configuration data * User Code and Data Additional data is required if the High Assurance Boot (HAB) feature of the ROM is used. In this case, additional HAB Command Sequence File (CSF) data is also required. See High Assurance Boot (HAB) for additional details. 12.6.1 Image Vector Table (IVT) The IVT is the data structure that the ROM reads from the boot device supplying the program image containing the required data components to perform a successful boot. The IVT includes the program image entry point, a pointer to Device Configuration Data (DCD) and other pointers used by the ROM during the boot process. The ROM locates the IVT at a fixed address that is determined based on the boot device connected to i.MX28. The IVT offset from the base address and initial load region size for each boot device type is defined in the following table. The location of the IVT is the only fixed requirement by the ROM. The remainder or the image memory map is flexible and is determined by the contents of the IVT. NOTE On i.MX28 the IVT must not be placed at offset 0x00000000. The ROM will interpret this as a NULL pointer and reject the location of the IVT as invalid. NOTE The i.MX28 ROM does not make use of the DCD or boot data fields of the IVT. These fields must be set to NULL. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1014 Freescale Semiconductor, Inc. Chapter 12 Boot Modes Destination Device Memory Boot Device Memory Image Vector Table NULL header entry reserved1 dcd boot data self csf reserved2 CSF CSF DCD DCD Program Image Program Image NULL header entry reserved1 dcd boot data self csf reserved2 Image Vector Table Boot Device Base Address 12.6.1.1 Image Vector Table Structure The IVT has the following format where each entry is a 32 bit word: Table 12-12. IVT Format header entry reserved1 dcd boot data self csf reserved2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1015 Program Image * header: The IVT header has the following format: Table 12-13. IVT Header Format Tag * * * * * * * Length Version where: * Tag: A single byte field set to 0xD1 * Length: a two byte field in big endian format containing the overall length of the IVT, in bytes, including the header. (the length is fixed and must have a value of 32 bytes) * Version: A single byte field set to 0x40 entry: Absolute address of the first instruction to execute from the image. reserved1: Reserved and should be zero. dcd: Absolute address of the image DCD. The DCD is optional so this field may be set to NULL if no DCD is required. See Device Configuration Data (DCD) for further details on DCD. boot data: Absolute address of the Boot Data. For i.MX28 this field should be zero. self: Absolute address of the IVT. Used internally by the ROM. csf: Absolute address of Command Sequence File (CSF) used by the HAB library. See High Assurance Boot (HAB) for details on secure boot using HAB. This field must be set to NULL when not performing a secure boot when HAB is enabled. reserved2: Reserved and should be zero. 12.6.2 Device Configuration Data (DCD) Upon reset the i.MX28 uses the default register values for all peripherals in the system. The i.MX50 ROM changes some of these defaults such as clock frequencies for boot purposes. However, these settings typically are not ideal for achieving optimal system performance and there are even some peripherals that must configured before they can be used. The DCD is configuration information contained in a Program Image, external to the ROM, that the ROM interprets to configure various peripherals on i.MX28. Some components such as SDRAM require some sequence of register programming as part of configuration before it is ready to be used. The DCD feature can be used to program the EIM registers and DATABAHN SDRAM control registers to the optimal settings. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1016 Freescale Semiconductor, Inc. Chapter 12 Boot Modes NOTE The i.MX28 ROM does not use the Image Vector Table (IVT) to locate the DCD. Instead, the i.MX28 ROM uses the Load DCD command. See ROM Commands for details on the Load DCD ROM command. The DCD table shown in below is a big endian byte array of the allowable DCD commands. The maximum size of the DCD limited by the ROM to 1768 bytes. Table 12-14. DCD Data Format Header [CMD] [CMD] ... The DCD header is 4 bytes with the following format: Table 12-15. DCD Header Tag Length Version where: * Tag: A single byte field set to 0xD2 * Length: a two byte field in big endian format containing the overall length of the DCD, in bytes, including the header. * Version: A single byte field set to 0x40 Below is an example DCD for i.MX28. Note that this example is not a complete DCD and is shown here to illustrate how a DCD is structured. // Multi Write Data Command // // Creates Write Data Command header which performs writes to multiple taget // addresses // // inputs: flags - DCD command flags // bytes - size of write by command (1, 2, or 4) // number - number of writes performed by the DCD write data command #define MULTI_WRT_DAT(flags, bytes, number) \ HDR(HAB_CMD_WRT_DAT, (number * 2 + 1) * 4, WRT_DAT_PAR((flags), (bytes))) // DCD Table definition i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1017 Program Image uint8_t input_dcd[] = { /* DCD header */ DCD_HDR(HDR_BYTES + 26 * WRT_DAT_BYTES + (63 * 2 + 1) * 4, HAB_VER(4,0)), //void POWER_Init(void) just pick one register since no impact on RTL // HW_POWER_LOOPCTRL.B.EN_RCSCALE = 3; WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800440b4, 0x00003000), // PLL already turn on by ROM // HW_CLKCTRL_FRAC0_CLR(BM_CLKCTRL_FRAC0_CLKGATEEMI); // Turn on fractional clock control 0 EMI clkgate, // setmem /32 0x800401b8=0x00008000 WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800401b8, 0x00008000), // Set up the EMI clock // case EMI_CLK_150MHz: // use_xtal_src = 0; // new_pll_frac_div = 29; // new_pll_int_div = 2; // Write the PLL fractional divider W_CLKCTRL_FRAC0_WR(frac_val); // Clear the EMI frac first WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800401b8, 0x00003F00), // write new_pll_frac_div WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800401b4, 29 << 8), . . . // init_dram_regs(); // Write the Databahn SDRAM setup register values // use mobile_ddr_mt46h32m16lf_5_150MHz_for_dcd.c -- for 150MHz mDDR, 63 entries MULTI_WRT_DAT(0, HAB_DATA_WIDTH_WORD, 63), // DRAM_REG[0] = 0x00000000; EXPAND_UINT32(0x800e0000 + 0 * 4), EXPAND_UINT32(0x00000000), . . . // DRAM_REG[177] = 0x01030101; //000_00001 tccd(RW) 0000_0011 trp_ab(RW) //0000_0001 cksrx(RW) 0000_0001 cksre(RW) EXPAND_UINT32(0x800e0000 + 177 * 4), EXPAND_UINT32(0x01030101), // DRAM_REG[178] = 0x01001901; //0_0100001 axi5_bdw(RW) 0_0000000 axi4_current_bdw(RD) //0_0100001 axi4_bdw(RW) 000_00001 tckesr(RW) EXPAND_UINT32(0x800e0000 + 178 * 4), EXPAND_UINT32(0x01001901), // DRAM_REG[181] = 0x00320032; //0_000000000110010 mr0_data_1(RW) 0_000000000110010 mr0_data_0(RW) EXPAND_UINT32(0x800e0000 + 181 * 4), EXPAND_UINT32(0x00320032), // DRAM_REG[183] = 0x00000000; //0_000000000000000 mr1_data_1(RW) 0_000000000000000 mr1_data_0(RW) EXPAND_UINT32(0x800e0000 + 183 * 4), EXPAND_UINT32(0x00000000), // DRAM_REG[189] = 0xffffffff; EXPAND_UINT32(0x800e0000 + 189 * 4), EXPAND_UINT32(0xffffffff), // HW_DRAM_CTL17.B.SREFRESH = 0; WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800e0044, 0x00000000), // HW_DRAM_CTL16_SET(0x00000001); //set "start" WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800e0040, 0x00000001), // temp = HW_DRAM_CTL58_RD(); //Wait for EMI initialization completed // while ( (temp & 0x00100000) != 0x00100000 ){ // temp = HW_DRAM_CTL58_RD(); CHK_DAT_FOREVER(HAB_CMD_CHK_DAT_SET, HAB_DATA_WIDTH_WORD, 0x800e00e8, 0x00100000), // Now try to write something to ddr addresses 0x40200000 and 0x40200400 WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x40200000, 0xAAAAAAAA), i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1018 Freescale Semiconductor, Inc. Chapter 12 Boot Modes WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x40200400, 0x12345678), // Verify above two writes to ddr addresses CHK_DAT_FOREVER(HAB_CMD_CHK_DAT_SET, HAB_DATA_WIDTH_WORD, 0x40200000, 0xAAAAAAAA), CHK_DAT_FOREVER(HAB_CMD_CHK_DAT_SET, HAB_DATA_WIDTH_WORD, 0x40200400, 0x12345678), }; 12.6.2.1 Write Data Command The Write Data Command is used to write a list of given 1, 2 or 4-byte values or bitmasks to a corresponding list of target addresses. The format of Write Data Command, again a big endian byte array, is shown in the Write Data Command table below. Table 12-16. Write Data Command Format Tag Length Parameter Address Value/Mask [Address] [Value/Mask] ... [Address] [Value/Mask] where: * Tag: A single byte field set to 0xCC * Length: A two byte field in big endian format containing the length of the Write Data Command, in bytes, including the header. * Address: Target address to which the data should be written * Value/Mask: Data value or bit mask to be written to the preceding address The Parameter field is a single byte divided into bit fields as follows: Table 12-17. Write Data Command Parameter Field 7 6 5 4 3 2 flags 1 0 bytes where: * bytes: width of target location(s) in bytes. Either 1, 2 or 4. * flags: control flags for command behavior. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1019 Program Image One or more target address and value/bitmask pairs can be specified. The same bytes and flags parameters apply to all locations in the command. When successful, this command writes to each target address in accordance with the flags as follows: Table 12-18. Interpretation of Write Data Command Flags "Mask: "Set" Action Interpretation 0 0 *address = val msk Write value 0 1 *address = val_msk Write value 1 0 *address &= ~val_msk Clear bitmask 1 1 *address |= val_msk Set bitmask Notes: * If any of the target addresses does not have the same alignment as the data width indicated in the parameter field, none of the values are written. * If any of the values is larger or any of the bitmasks is wider than permitted by the data width indicated in the parameter field, none of the values are written. * If any of the target addresses do not lie within an allowed region, none of the values are written. The list of allowable modules and target addresses for i.MX28 are given below. Table 12-19. Valid DCD Address Ranges for i.MX28 Address Range Start Address Last Address DRAM Controller registers 0x800E0000 0x800EFFFF BCH ECC Accelerator 0x8000A000 0x8000BFFF GMPI registers 0x8000C000 0x8000DFFF Synchronous Serial Port 0 registers 0x80010000 0x80011FFF Synchronous Serial Port 1 registers 0x80012000 0x80013FFF Synchronous Serial Port 2 registers 0x80014000 0x80015FFF Synchronous Serial Port 3 registers 0x80016000 0x80017FFF Pin Control Block registers 0x80018000 0x80019FFF Digital Control registers 0x8001C000 0x8001DFFF GPIO Control registers 0x8003C500 0x8003C5FF Clock Control registers 0x80040000 0x80041FFF Power Control registers 0x80044000 0x80045FFF Real Time Clock registers 0x80056000 0x80057FFF I2C0 registers 0x80058000 0x80059FFF I2C1 registers 0x8005A000 0x8005BFFF Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1020 Freescale Semiconductor, Inc. Chapter 12 Boot Modes Table 12-19. Valid DCD Address Ranges for i.MX28 (continued) Address Range Start Address Last Address UART0 registers 0x8006A000 0x80000000 UART1 registers 0x8006C000 0x8006DFFF UART2 registers 0x8006E000 0x8006FFFF UART3 registers 0x80070000 0x80071FFF UART4 registers 0x80072000 0x80073FFF UARTDBG registers 0x80074000 0x80075FFF External memory 0x40000000 0x5FFFFFFF OCRAM free space 0x00000000 0x0000E3FF 12.6.2.2 Check Data Command The Check Data Command is used to test for a given 1, 2 or 4-byte bit masks from a source address. The Check Data Command is a big endian byte array with format shown below. Table 12-20. Check Data Command Format Tag Length Parameter Address [Count] where: * Tag: A single byte field set to 0xCF * Length: A two byte field in big endian format containing the length of the Check Data Command, in bytes, including the header. * Address: Source Address to test * Mask: Bit mask to test * Count: optional poll count. If count is not specified this command will poll indefinitely until the exit condition is met. If count = 0, this command behaves as for NOP. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1021 Program Image The Parameter field is a single byte divided into bit fields as follows: Table 12-21. Write Data Command Parameter Field 7 6 5 4 3 2 flags 1 0 bytes where: * bytes: width of target location in bytes. Either 1, 2 or 4. * flags: control flags for command behavior. * Data Mask = bit 3: if set, only specific bits may be overwritten at target address (otherwise all bits may be overwritten) * Data Set = bit 4: if set, bits at the target address overwritten with this flag (otherwise it is ignored) This command polls the source address until either the exit condition is satisfied, or the poll count is reached. The exit condition is determined by the flags as follows: Table 12-22. Interpretation of Check Data Command Flags "Mask: "Set" Action Interpretation 0 0 (*address & mask) == 0 All bits clear 0 1 (*address & mask) == mask All bits set 1 0 (*address & mask) != mask Any bit clear 1 1 (*address & mask) != 0 Any bit set Notes: * If the source address does not have the same alignment as the data width indicated in the parameter field, the value is not read. * If the bit mask is wider than permitted by the data width indicated in the parameter field, the value is not read. 12.6.2.3 NOP Command This command has no effect. The format of NOP Command is a little endian four byte array as shown below: Table 12-23. NOP Command Format Tag Length Undefined i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1022 Freescale Semiconductor, Inc. Chapter 12 Boot Modes where: * Tag: A single byte field set to 0xC0 * Length: A two byte field containing the length of the NOP Command in bytes. Fixed to a value of 4. * Undefined: This byte is ignored and can be set to any value. 12.7 High Assurance Boot (HAB) ARM 926 Processor Core Boot ROM Boot Device HAB Library Security Hardware (DCP) The High Assurance Boot (HAB) component of the ROM protects against the potential threat of attackers modifying areas of code or data in programmable memory to make it behave in an incorrect manner. The HAB also prevents attempts to gain access to features which should not be available. The integration of the HAB feature with the ROM code ensures that i.MX28 does not enter an operational state if the existing hardware security modules have detected a condition that may be a security compromise or areas of memory deemed to be important have been modified. The HAB uses RSA digital signatures to enforce these policies. The RSA key sizes supported are 1024 and 2048 bits. Note that the HAB feature is independent of the encrypted boot feature. The HAB checks the authenticity of a Progam Image using a public key infrastructure whereas the encrypted boot feature provides confidentiality. RAM The figure above illustrates the components used during a secure boot using HAB. The HAB makes use of the DCP2 hardware module to accelerate SHA-256 message digest operations performed during signature verifications. The HAB also includes a software i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1023 Constructing Boot Image (SB Files) to Be Loaded by ROM implementation of SHA-256 for cases where a hardware accelerator cannot be used. The core RSA signature verification operations are performed by a software implementation contained in the HAB library. The main features supported by HAB are: * X.509 public key certificate support * CMS signature format support For further details on making use of the High Assurance Boot feature of i.MX28, please contact your local Freescale representative. 12.7.1 ROM Vector Table Addresses For devices that are performing a secure boot using HAB, the HAB library may be called from additional boot stages that execute after ROM code. The RVT table contains the pointers to the HAB API functions such that these boot stage can authenticate the stage that follows. The RVT is fixed in ROM and is located at 0xFFFF8AF8. For additional information on using HAB on i.MX28, including the HAB API, please contact your local Freescale representative. 12.8 Constructing Boot Image (SB Files) to Be Loaded by ROM Boot images are created by the Freescale supplied elftosb application, which handles both encryption and HAB signature if required. Freescale provides a sample code signing tool. It can be used for reference purposes in integrating with third-party tools or a proprietary signing infrastructure. Preparing a bootable image for all boot modes includes the following high-level steps: 1. Prepare the unsigned Image ELF file for the firmware that is to be booted by the ROM. 2. Sign the image with the code signing tool, which generates one HAB.ELF file (Freescale provides example tools, and third party code signing tools may also be available. Contact your local Freescale representative for further details). This file contains the CSF (HAB command sequence file) and certificates. 3. Use the elftosb tool to combine the unsigned Image ELF and HAB.ELF together and convert them to a boot stream (SB file), which the ROM loader will understand. The elftosb tool also handles encryption if an encryption key is provided. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1024 Freescale Semiconductor, Inc. Chapter 12 Boot Modes The following figures shows the process of creating a boot loader image from ELF files by elftosb. A key set must be input to the elftosb program to properly encrypt and authenticate the image. LIBs C and ASM LIBs Figure 12-2. i.MX28 Boot Image Generation ELF Tools (GHS or GNU) Load Image (SB) elftosb Figure 12-3. i.MX28 Boot Image Build Process i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1025 Constructing Boot Image (SB Files) to Be Loaded by ROM 12.8.1 ROM Commands The i.MX28 ROM boots from an image residing on an external boot device using a number of built in commands. These commands are used by the ROM to establish the boot image including the Image Vector Table (IVT). The ElftoSB tool provided by Freescale converts a typical image file in ELF format to the Freescale SB format consisting of the following commands: LOAD DCD Command LOAD DCD is an extension from LOAD command by adding an additional flag. When the DCD flag is set, ROM runs DCD to configure the external memory. The ROM command is 16 bytes in length. The following table shows the field description. Bold indicates the changes. Table 12-24. LOAD DCD Command Field Descriptions Field Description m_checksum Simple checksum of other fields of boot_command_t. m_tag 0x02 or ROM_LOAD_CMD. m_flags Normal load 0x0000, DCD load 0x0001. m_address Memory address to which data is stored. m_count Number of bytes to load. This is also the number of valid bytes in the data cipher blocks following this command. m_data CRC-32 over the data to be loaded. 1 0 ROM_LOAD_CMD 2 data data padding m_count = 18 Figure 12-4. LOAD DCD Command HAB Jump Command The HAB Jump command is overload from Jump command by adding an additional flag. When the HAB flag is set, ROM calls the HAB4 Authenticate image function with IVT as argument. The authenticate image function returns the image entry, and then ROM performs a real jump to that address. The following table shows the HAB Jump command fields. Bold indicates the changes. For i.MX28, JUMP without HAB is no longer valid hence HAB flag should always be set. Table 12-25. HAB Jump Command Field Descriptions Field Description m_checksum Simple checksum of other fields of boot_command_t. m_tag 0x04 or ROM_JUMP_CMD. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1026 Freescale Semiconductor, Inc. Chapter 12 Boot Modes Table 12-25. HAB Jump Command Field Descriptions (continued) Field Description m_flags HAB jump 0x0001. HAB flag should always be set for i.MX28. m_address Address of the IVT pointer for HAB jump. m_count 0 m_data Argument to pass to the entry point in R0. HAB Call Command The HAB Call command is overload from Call command by adding an additional flag. When the HAB flag is set, ROM calls the HAB4 authenticate image function with IVT as an argument. The authenticate image function returns the image entry, and then ROM performs a real call to that address. Bold indicates the changes. For i.MX28,CALL without HAB is no longer valid hence HAB flag should always be set. Table 12-26. HAB Call Command Field Descriptions Field Description m_checksum Simple checksum of other fields of boot_command_t. m_tag 0x05 or ROM_CALL_CMD. m_flags HAB call 0x0001. HAB flag should always be set for i.MX28. m_address Address of the IVT pointer for HAB call. m_count 0 m_data Argument to pass to the function in R0. 12.9 I2C Boot Mode EEPROMs must have the slave address 0xA0 (that is, 1010000R, where R indicates a read if 1 and a write if 0). Also, the EEPROM must have exactly a two-byte subaddress. Boot images must start at address 0x0 of the EEPROM and cannot exceed 64 Kbytes in size. The I2C port is set to run at 100 KHz by default. The clock is increased to 400 KHz if I2C_USE_400 KHz is blown. 12.10 SPI Boot Mode SPI memories are either EEPROMs or NORs. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1027 SPI Boot Mode By default, the SPI serial clock is set to 1 MHz for EEPROMs and 12 MHz for NORs. The SSP_SCK_INDEX OTP 4 bits are used to change the SPI serial clock from defaults. These bits serve as the index for the SSP HAL clock rate array (see SSP for details on the clock rate array). The defaults may also be changed by using the ConfigBlock.Clocks field. If ConfigBlock.Clocks.SspClockConfig is non-zero, then that struct will be used to change the SPI SCK rate and will override the SSP_SCK_INDEX OTP setting. This driver supports only 2-byte addresses for EEPROMs and 3-byte addresses for NORs. SSP2 and SSP3 are used for SPI boot mode. 12.10.1 SSP Pin Configuration SSP boot mode supports the standard package and the small package of i.MX28. Table 12-27. SSP Ports Pin-Mux Configuration SSP Pins SSP0 SSP1 SSP2 SSP3 SSP3 (standard package) (small package) SCK SSP0_CLK GPMI_WRN SSP2_SCK SSP3_SCK GPMI_RDN DETECT SSP0_DETECT GPMI_RDY0 -- -- -- CMD SSP0_CMD GPMI_RDY1 SSP2_MOSI SSP3_MOSI GPMI_RESETN DATA7 SSP0_DATA7 GPMI_D07 -- -- -- DATA6 SSP0_DATA6 GPMI_D06 -- -- -- DATA5 SSP0_DATA5 GPMI_D05 -- -- -- DATA4 SSP0_DATA4 GPMI_D04 -- -- -- DATA3 SSP0_DATA3 GPMI_D03 SSP2_S30 SSP3_S30 GPMI_CE1N DATA2 SSP0_DATA2 GPMI_D02 -- -- -- DATA1 SSP0_DATA1 GPMI_D01 -- -- -- DATA0 SSP0_DATA0 GPMI_D00 SSP2_MISO SSP3_MISO GPMI_CE0N 12.10.2 Media Format The media is arbitrarily partitioned into 128-byte sectors. An optional configuration block may reside on the media at byte address 0. This block has the following format: //! \brief Spi media configuration block structs typedef struct _spi_ConfigBlockFlags { i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1028 Freescale Semiconductor, Inc. Chapter 12 Boot Modes uint32_t DisableFastRead:1; // Ignored for Spis // 0 - Do not disable fast reads // 1 - Disable fast reads } spi_ConfigBlockFlags_t; typedef struct _spi_ConfigBlockClocks { uint32_t SizeOfSspClockConfig; // sizeof(ssp_ClockConfig_t) ssp_ClockConfig_t SspClockConfig; // SSP clock configuration structure. A null // structure indicates no clock change. } spi_ConfigBlockClocks_t; typedef struct _spi_ConfigBlock // Little Endian { uint32_t Signature; // 0x4D454D53, or "SMEM" uint32_t BootStartAddr; // Start address of boot image. Must be >= // sizeof(spi_ConfigBlock_t) uint32_t SectorSize; // Sector size in bytes. Overrides ROM default // of 128-bytes. Max is 1024-bytes. 0 is // default 128-bytes. spi_ConfigBlockFlags_t Flags; // Various flags. See spi_ConfigBlockFlags spi_ConfigBlockClocks_t Clocks; // SCK clock update structure. } spi_ConfigBlock_t; If the block is present, then the boot image is found at the address specified by BootStartAddr. If the block is not present, then it assumes that the boot image resides on the media starting at byte address 0. 12.10.3 SSP The SSP2 and SSP3 ports are used for the SPI boot mode. The following table is used to look up a requested speed. If the speed is not an exact match, the boot ROM picks the next lowest value. Speed values can range from 1 to 51.4 MHz. A speed value of 0 is not allowed. // Lookup Table entry typedef struct _ssp_clockConfig { int clkSel :1; //!< Clock Select (0=io_ref 1=xtal_ref) int io_frac :6; //!< IO FRAC 18-35 (io_frac+16) int ssp_frac :9; //!< SSP FRAC (1=default) int ssp_div :8; //!< Divider: Must be an even value 2-254 int ssp_rate :8; //!< Serial Clock Rate } ssp_clockConfig_t; The table is loaded with the clock rates listed in Table 12-28. Table 12-28. SCK Clock Standard Values Lookup Table SCK N/A .24 1 2 4 6 8 10 12 16 20 30 40 48 51.4 X INDEX 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK_SEL X 1 1 1 1 1 0 0 1 0 0 0 0 0 0 IOFRAC X X X X X X 18 18 X 18 18 18 18 18 21 X SSP_FRAC X X X X X X 6 6 X 5 6 8 6 5 4 X Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1029 SD/MMC Boot Mode Table 12-28. SCK Clock Standard Values Lookup Table (continued) SSP_CLK 24 24 24 24 24 80 80 24 96 80 60 80 96 102. 8 X SSP_DIV X 100 24 12 6 4 10 8 2 6 4 2 2 2 2 X SSP_RATE X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 12.11 SD/MMC Boot Mode SD/MMC boot mode supports booting from SD/MMC cards adhering to the following specifications: * iNand Product Manual, Version 2.1 * SD Specifications, Part 1, Physical Layer Specification, Version 1.10 * SD Specifications, Part 1, Physical Layer Specifications, Version 2.0 Draft * SD Specifications, Part 1, eSD (Embedded SD Specifications), Version 2.10 Draft Rev * MultiMediaCard System Specification, Version 4.1 * MultiMediaCard System Specification, Version 4.2 * MultiMediaCard System Specification, Version 4.3 * MultiMediaCard System Specification, Version 4.4 Note, however, that this mode does not support dynamic insertion removal, so the systems will typically not include removable cards. The following modes are supported: * SD/MMC on SSP0 * SD/MMC on SSP1 The SD_POWER_GATE_GPIO eFuse bits indicate which GPIO pin to use for controlling an external power gate for the connected device. SD_POWER_GATE_GPIO Gate GPIO 00b PWM3 01b PWM4 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1030 Freescale Semiconductor, Inc. Chapter 12 Boot Modes SD_POWER_GATE_GPIO Gate GPIO 10b LCD DOTCK 11b NONE If a gate GPIO is used, then the driver will use the SD_POWER_UP_DELAY eFuse to determine the amount of time, in 10-ms increments, to wait until starting the 1-ms initialization sequence. This eFuse field is 6-bits wide, providing from 10-600 ms of delay. If the field is 000000b, then the delay is a default 20 ms. If no gate GPIO is specified in SD_POWER_GATE_GPIO, then the delay is skipped. The SSP ports on the i.MX28 top out at 51.4 MHz with 20-40 pF loading. By default, the serial clock is set to 12 MHz. If the SD_SPEED_ENABLE persistent bit is set, then the driver will use a maximum speed based on the results of device identification and limited by choices available in the SSP clock index. For eMMC fast boot mode, serial clock is just decided by SSP_SCK_INDEX OTP bits. If SSP_SCK_INDEX is not burned, that is invalid clock index, then ROM chooses the default clock (12 MHz). This mode supports the 1-bit, 4-bit, and 8-bit data MMC/SD buses. The SD_BUS_WIDTH efuse bits selects how many bus pins are physically available for the SSP port. Bus width will be limited based on these bits, as well as the bus width capabilities indicated by the connected device. SD_BUS_WIDTH Width 00b 4-bit 01b 1-bit 10b 8-bit 11b Reserved The eFuse ROM0:23:22 defines one of four possible media formats, as shown in the following table. Table 12-29. Media Formats SD_MMC_MODE Media Format 00b MBR_MEDIA_FORMAT 01b RESERVED 10b eMMC_FASTBOOT_MEDIA_FORMAT 11b eSD_FASTBOOT_MEDIA_FORMAT i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1031 SD/MMC Boot Mode 12.11.1 Boot Control Block (BCB) Data Structure The design of BCB is to allow multiple copies of firmware to be stored on media each identified by its unique tag. The tags can be defined either by the user or the firmware download application. The ROM is only interested in user-defined primary and secondary boot tags. The ROM loads primary firmware, if ROM_REDUNDANT_BOOT persistent bit is not set; otherwise it loads a secondary image, providing support for a redundant boot. The config block has the following format: typedef struct _DriveInfo_t { uint32_t u32ChipNum; uint32_t u32DriveType; uint32_t u32Tag; uint32_t u32FirstSectorNumber; uint32_t u32SectorCount; } DriveInfo_t; typedef struct _ConfigBlock_t { uint32_t u32Signature; uint32_t u32PrimaryBootTag; uint32_t u32SecondaryBootTag; uint32_t u32NumCopies; DriveInfo_t aDriveInfo[]; future //!< //!< //!< //!< //!< Chip Select, ROM does not use it Always system drive, ROM does not use it Drive Tag Start sector/block address of firmware. Not used by ROM //!< //!< //!< //!< //!< //!< Signature 0x00112233 Primary boot drive identified by this tag Secondary boot drive identified by this tag Num elements in aFWSizeLoc array Let array aDriveInfo be last in this data structure to be able to add more drives in //!< without changing ROM code } ConfigBlock_t; The driver first verifies the signature and version, then searches all NumRegions for the appropriate tag. The following table shows the expected values for these parameters. Table 12-30. Media Config Block Parameters Field Value Signature 0x00112233 u32PrimaryBootTag User-defined primary boot firmware tag u32SecondaryBootTag User- defined secondary boot tag u32NumCopies Number of firmware copies present in array aDriveInfo aDriveInfo Each element in array describes the tag and start address for the image i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1032 Freescale Semiconductor, Inc. Chapter 12 Boot Modes 12.11.2 Master Boot Record (MBR) Media Format If the eFuse media format mode is MBR_MEDIA_FORMAT, then ROM expects a valid master boot record (MBR) to be present on the first block of media. The MBR is identified by its signature located at offset 0x1FE of the first sector. The partition table is stored at address 0x1BE. The Freescale firmware partition is identified by MBR_SIGMATEL_ID at an offset 0x04 from partition table. The firmware partition's start block address is located at offset 0x08 of firmware partition entry of partition table. Field Value MBR Signature 0x55AA MBR_SIGMATEL_ID 'S' The first block of firmware partition contains BCB, allowing multiple copies of firmware to reside inside firmware partition and to support redundant boot feature of ROM. Refer to Boot Control Block (BCB) Data Structure for a detailed view of BCB data structure and its use. All firmware copies specified in BCB should be located inside the firmware partition. 12.11.3 eMMC Fast Boot Media Format This section describes the behavior of ROM when the eFuse state of SD_MMC_MODE is 0x10 (eMMC_FASTBOOT_MEDIA_FORMAT). The eMMC4.3 and eMMC4.4 fast boot modes are supported. By default, primary fast boot mode, pull down CMD line after eMMC card power up, is enabled. The ALT_FAST_BOOT OTP bit enables the alternative fast boot mode, which sends CMD0 with an argument 0xFFFF_FFFA after power up. The boot image for eMMC fast boot does not contain a MBR block or a configuration block. It is the user's responsibility to program the EXT_CSD register when loading the boot image into an eMMC card. The bytes in EXT_CSD register have to be read or programmed to include the following: * * * * [228] BOOT_INFO [226] BOOT_SIZE_MULT [179] BOOT_CONFIG(eMMC4.3) PARTITION_CONFIG(eMMC4.4) [177] BOOT_BUS_WIDTH The ALT_FAST_BOOT, FAST_BOOT_ACK, EMMC_USE_DDR and SD_BUS_WIDTH OTP bits must be consistent with the setting in EXT_CSD register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1033 NAND Boot Mode 12.11.4 eSD Fast Boot Media Format The ROM supports eSD by following the same flow as SD 2.0, except that ROM selects the physical partition 1(boot code area) by sending CMD43. The CMD43 is reserved command in SD2.0. Therefore, for eSD boot mode, boot image has to be located in partition 1. If eSD fast boot mode is enabled, the FAST_BOOT bit in the argument of ACMD41 is set. The eSD device partition 1 should be defined as a fast boot physical partition. Otherwise, the device still initializes the entire media and not a partial initialization. The ROM expects the BCB data structure to be present on the first block of boot partition. Like the BCB and MBR media formats, the ROM uses the persistent bit ROM_REDUNDANT_BOOT to decide whether to load primary or secondary boot firmware. 12.11.5 Device Identification SD/MMC boot mode uses the identification processes specified as follows: * SD Specifications, Part 1, Physical Layer Specifications, Version 2.0 Draft. * SD Specifications, Part 1, eSD (Embedded SD) Specification Version 2.10 Draft Rev. 0.91. * MultiMediaCard System Specification Version 4.2, Version 4.3, Version 4.4. 12.12 NAND Boot Mode NAND boot mode is used to boot from both raw NAND devices and block abstracted ONFi BA NAND devices, with error correction capability in the controller. 12.12.1 Raw NAND Device Boot The ROM relies on the BCH hardware engine for handling error corrections when reading data from a raw NAND device. The boot ROM expects the NAND Flash to be partitioned into the following areas: * Search Area for Firmware Configuration Block (FCB) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1034 Freescale Semiconductor, Inc. Chapter 12 Boot Modes * Search Area for Discovered Bad Block Table (DBBT) * Firmware blocks with primary and secondary boot firmware The rest of NAND Flash is available for non-boot purposes. FCB and DBBT together are referred to as boot control blocks, or BCB. 12.12.1.1 Search Area The search area is defined by search count times search stride. 12.12.1.2 Search Count Search count is defined as the number of copies of BCB data structures present in a given search area. It is 2^efNANDBootSearchCount (a value from OTP/eFuses). The default search count when OTP is not programmed is 4. This is the most common case. The minimum search count is 2 and the maximum search count is 32768. 12.12.1.3 Search Stride Search stride is defined as the distance in pages between two BCB data structures in a given search area. It is 64 pages times efNANDBootSearchStride (a value from OTP/ eFuses). When efNANDBootSearchStride is not blown, the boot ROM defaults it to 1. Therefore, the minimum search stride is always 64 pages apart (the most common case), and the maximum search stride is (64 * 15 = 960) pages apart. 12.12.1.4 Boot Control Blocks (BCB) There are two BCB data structures: FCB and DBBT. As part of the NAND media initialization, the ROM driver uses safe NAND timings to search for a Firmware Configuration Block (FCB) that contains the optimum NAND timings, the page address of Discovered Bad Block Table (DBBT) Search Area and the start page address of the primary and secondary firmware. In i.MX28, there are no separate boot modes for each type of ECC level. The hardware ECC level to use is embedded inside FCB block. The FCB data structure is itself protected using software ECC (SEC-DED Hamming Codes). Driver reads raw 2112 bytes of first sector and runs through software ECC engine that determines whether FCB data is valid or not. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1035 NAND Boot Mode If the FCB is found, the optimum NAND timings are loaded for further reads. If the ECC fails, or the fingerprints do not match, the Block Search state machine increments the page number to Search Stride number of pages to read for the next BCB until 2^n efNANDBootSearchCount pages have been read. If search fails to find a valid FCB, the NAND driver responds with an error and the boot ROM enters into the recovery mode. The FCB contains the page address of DBBT Search Area, and the page address of primary and secondary boot images. DBBT is searched in DBBT Search Area just like how FCB is searched. A flowchart for this process is shown in Figure 12-5. After the FCB is read, the DBBT is loaded, and the primary or secondary boot image is loaded using the starting page address from FCB. START CurrentPage = 0; BootSearchStride = (value read from OTP * 64) BootSearchCount = 2 ^ (value read from OTP) ReadCount = 0; Read NAND Page at address CurrentPage; ReadCount ++; CurrentPage = CurrentPage + BootSearchStride YES Is Page FCB NO ReadCount < BootSearchCount YES NO FCB Found FCB Not Found Figure 12-5. Firmware Control Blocks Flowchart i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1036 Freescale Semiconductor, Inc. Chapter 12 Boot Modes START CurrentPage = DBBT Search Area Start Address From FCB; BootSearchStride = (value read from OTP * 64) BootSearchCount = 2 ^ (value read from OTP) ReadCount = 0; Read NAND Page at address CurrentPage; ReadCount ++; CurrentPage = CurrentPage + BootSearchStride YES Is Page DBBT NO ReadCount < BootSearchCount YES NO DBBT Found DBBT Not Found Figure 12-6. DBBT Search Process Flowchart The BCB search and the load function also monitors the ECC correction threshold and sets the NAND_SDK_BLOCK_REWRITE persistent bit if the threshold exceeds the max ecc correction ability. One bit is used for all boot block images. If the NAND_SDK_BLOCK_REWRITE bit is set, the ROM continues loading the image, but the SDK needs to refresh the boot blocks at a later time. 12.12.1.5 Redundant Boot Support in ROM NAND driver ROM checks the state of ROM_SECONDARY_BOOT persistent bit to decide which firmware to load, either primary or secondary. If the bit is not set, it will load the primary image. Otherwise, it will load the secondary image. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1037 NAND Boot Mode If ROM fails to load from primary boot image due to ECC failures, it will set the persistent bit ROM_SECONDARY_BOOT and soft resets the chip to let ROM come up again and load from secondary image. The persistent bit will retain its status until power down. If ROM NAND driver fails to load from primary boot image due to non-ECC failures like invalid header, and so on, it will return an error code to the ROM loader. The secondary boot will be initiated by the loader if the driver supports redundant boot. ROM NAND driver and ROM SD driver are the only two drivers that currently support ROM redundant boot. 12.12.1.6 NAND Patch Boot using FCB A secondary mechanism to boot NAND patch image is implemented in i.MX28 ROM. A flag is used in the FCB data structure which indicates to the ROM to boot the patch binary image present on the second page of first good block of NAND. If this flag is set, the ROM does not try to locate other boot blocks, but rather starts loading the patch image. 12.12.1.7 Expected NAND Layout This section shows several potential expected NAND layouts. The following figure shows the default layout if no efuses are blown. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1038 Freescale Semiconductor, Inc. Chapter 12 Boot Modes FCB Search Area Page 0 Page 64 Page 128 DBBT Search Area Firmware Configuration Block (FCB) Firmware Configuration Block (FCB) Firmware Configuration Block (FCB) Page 192 Firmware Configuration Block (FCB) Page 256 Discovered Bad Block Table (DBBT) Page 320 Page 384 Page 448 Page 512 Discovered Bad Block Table (DBBT) Discovered Bad Block Table (DBBT) Discovered Bad Block Table (DBBT) Boot Firmware 1 Page 1024 Boot Firmware 2 Figure 12-7. Expected NAND Layout with search count = 4 and search stride = 1*64 To work with the following layout, efuses need to be blown, efNANDBootSearchCount to 0x1 and efNANDBootSearchStride to 0x2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1039 NAND Boot Mode FCB Search Area DBBT Search Area Page 0 Firmware Configuration Block (FCB) Page 128 Firmware Configuration Block (FCB) Page 256 Discovered Bad Block Table (DBBT) Page 384 Discovered Bad Block Table (DBBT) Page 512 Boot Firmware 1 Page 1024 Boot Firmware 2 Figure 12-8. Expected NAND Layout with search count = 2 and search stride = 2*64 To work with the following layout efuses need to be blown, efNANDBootSearchCount to 0x1 and efNANDBootSearchStride to 0xF. FCB Search Area Page 0 Firmware Configuration Block (FCB) Page 1 Boot Firmware 1 Page 500 Page 960 Boot Firmware 2 Firmware Configuration Block (FCB) Figure 12-9. Expected NAND Layout for patch boot with search count = 2 and search stride = 15*64 and no DBBT To work with the following layout, efuses need to be blown, efNANDBootSearchCount to 0x1 and efNANDBootSearchStride to 0xF. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1040 Freescale Semiconductor, Inc. Chapter 12 Boot Modes FCB Search Area Page 0 Firmware Configuration Block (FCB) Page 1 Boot Firmware 1 Page 500 Page 960 Boot Firmware 2 Firmware Configuration Block (FCB) Figure 12-10. Expected NAND Layout for patch boot with search count = 2 and search stride = 15*64 and valid DBBT 12.12.1.8 Firmware Configuration Block The FCB is the first sector in the first good block. The FCB should be present at each search stride of the search area. The search area contains copies of the FCB at each stride distance, so in case the first NAND block becomes corrupted, the ROM will find its copy in the next NAND block. The search area should span over at least two NAND blocks. The location information of DBBT search area, FW1 and FW2 are all specified in the FCB. This case is shown in more detail in Firmware Layout on the NAND. The layout of the first good page containing FCB is shown in the following figure. 2111 Spare 1036 Parity Bits For FCB Data 524 FCB Data 12 Bytes Left 0 Figure 12-11. Layout of Boot Page Containing FCB i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1041 NAND Boot Mode The FCB is located on the first good page of the NAND; the minimum size of a page is 2112 bytes. The first 12 bytes of an FCB page are reserved and left blank (all zeros); the next 512 bytes are reserved for FCB data. The remaining 512 bytes are available for software ECC, and the rest are all zeros. FCB is protected using SEC-DED Hamming codes. 12.12.1.9 Single Error Correct and Double Error Detect (SEC-DED) Hamming For each 8-bit of data in the 512 byte FCB, 5-bit parity is used. Each byte of parity area contains 5 parity bits (LSB) and 3 unused bits (MSB). For each 8-bit of FCB data, parity is calculated and compared with the corresponding parity bits read from the parity area of the FCB page to detect errors and correct any single error. If there is more than one error, a flag is raised against the block. To determine a good FCB, all three fingerprints must match and the ECC must not fail. The data held in the FCB includes the following: * NAND Timing parameters * Geometry information (sectors per block, sectors per page, and so on) * The page address of the discovered bad block table (DBBT) * BCH ECC type * A flag to boot the NAND patch image located at sector 2 of first block * Starting page addresses of primary and secondary firmware * Bad block marker bit offset in page data Additionally, the FCB is marked with three fingerprints in the sector. 12.12.1.10 Firmware Layout on the NAND The boot image is typically located on the first good block after the FCB, DBBT blocks and any additional blocks reserved for BCBs in case they go bad. ROM shall support boot from only first NAND. In case of multi-NAND system, both firmware copies should be located on first NAND, same as in the single-NAND system. The DBBT will be located in its own search area and a copy of DBBT will be present at each stride of the search area. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1042 Freescale Semiconductor, Inc. Chapter 12 Boot Modes 12.12.1.11 Recovery From a Failed Boot Firmware Image Read The mechanism for recovering from a failed FCB read is covered in Boot Control Blocks (BCB). The SDK is warned about impending errors with the NAND_SDK_BLOCK_REWRITE persistent bit and is notified of firmware boot errors with the ROM_SECONDARY_BOOT persistent bit. In the case of a warning, the read routine will monitor the ECC threshold and set the NAND_SDK_BLOCK_REWRITE bit if the threshold is within one symbol of the maximum correctable number of symbols. The ROM continues to load from the primary boot image. At a later time, the SDK will refresh the primary boot images by copying and rewriting the primary boot image blocks. If an error is discovered while reading the boot firmware image, the NAND driver sets the ROM_SECONDARY_BOOT persistent bit and resets the device. Booting will proceed the second time from the secondary boot images. If booting continues uninterrupted, no unwinding needs to take place at the loader level. Boot Image Load Do ReadSector() until image is loaded N Boot Image Loaded Did error occur during read ? Y Boot Complete Exit Set ROM_SECONDARY_BOOT persistent bit Reset Device Figure 12-12. Boot Image Recovery 12.12.1.12 Bad Block Handling in the ROM Bad blocks are not an issue for the FCB, because FCB found from a search. The search for the DBBT works with a similar mechanism. The search starts where the FCB indicates the DBBT Search Area should be and progresses until efNANDBootSearchLimit times in the same fashion as the search described in Boot Control Blocks (BCB). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1043 NAND Boot Mode ROM uses DBBT to skip any bad block that falls within firmware data on NAND Flash device. If the address of DBBT Search Area in FCB is 0, ROM will rely on factory marked bad block markers to find out if a block is good or bad. The location of bad block information is at the first 3 or last 3 pages in every block of the NAND Flash. NAND manufacturers normally use one byte in the spare area of certain pages within a block to mark a block to be good or bad. 0xFF means good block, non FF means bad block. In order to preserve the BI (bad block information), flash updater or gang programmer applications need to swap Bad Block Information (BI) data to byte 0 of metadata area for every page before programming NAND Flash. ROM when loading firmware, copies back the value at metadata[0] to BI offset in page data. The following figure shows how the factory bad block marker is preserved. Bad block information at column address 2048 64B spare 2KB Main area 512 main parity 512 main parity 512 main metadata Swap byte parity 512 main parity Bad block information at 4th block's data area Figure 12-13. Factory Bad Block Marker Preservation In the FCB structure, there are two elements m_u32BadBlockMarkerByte and m_u32BadBlockMarkerStartBit to indicate the byte offset and start bit of BI. ROM will use 8 bits from start bit as BI. The DBBT structure is contained within a block and is discussed in more detail below. The figure below depicts the layout of the Discovered Bad Block Table block. The first 8K are reserved for the DBBT Header. The following pages are used by the DBBT for each NAND. The Bad Block table for each NAND begins on a 2 KB boundary that coincides with current NAND page sizes and is a subset of future NAND page sizes. The BBT can extend beyond 2K, which is the purpose of the #2K_num, and translates to the number of 2K pages that NAND0 through NAND3 require. In this way, the ROM can quickly index to the appropriate NAND table. Only the Bad Blocks for NAND0 are required and loaded. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1044 Freescale Semiconductor, Inc. Chapter 12 Boot Modes 8K FGR1 #BB_0 #BB_1 #BB_3 #2K_0 #2K_1 #2K_2 #2K_3 FGR2 Discovered Bad Block Table Header FGR3 NAND0 # of 2K pages NAND0 #BB BB5 # of 2K pages NAND1 BB511 BB512 BB513 NAND1 #BB BB1 BB511 BB512 BB513 NAND2 #BB BB1 BB4 BB2 BB3 BB4 BB2 BB3 BB4 BB3 BB4 NAND2 Bad Block Table BB511 BB512 BB513 NAND3 #BB BB1 BB5 BB511 BB3 NAND1 Bad Block Table BB5 # of 2K pages NAND3 BB2 NAND0 Bad Block Table BB5 # of 2K pages NAND2 BB1 #BB_2 BB2 NAND3 Bad Block Table BB512 BB513 Figure 12-14. DBBT Structure 12.12.1.13 Firmware Configuration Block Structure and Definitions The FCB structure is as follows: Table 12-31. Firmware Configuration Block Structure Name Start Byte Size in bytes Description m_u32Checksum 0 4 32 bit checksum of 508 bytes of FCB data from offset 4 to 512 XOR with 0xFFFFFFFF. m_u32FingerPrint 4 4 32 bit word with a value of 0x20424346, in ascii "FCB ". m_u32Version 8 4 32 bit version number; this version of FCB is 0x01000000. m_NANDTiming 12 4 8 bytes of data for 8 NAND Timing Parameters from NAND datasheet. The 8 parameters are: data_setup, data_hold, address_setup, dsample_time, nand_timing_state, REA, RLOH, RHOH. m_u32PageDataSize 20 4 Number of bytes of data in a page. Typically, this is 2048 bytes for 2112 bytes page size or 4096 bytes for 4314 bytes page size. m_u32TotalPageSize 24 4 Total number of bytes in page. Typically, 2112 for 2K page or 4224 or 4314 for 4K page. m_u32SectorsPerBlock 28 4 Number of pages per block. Typically 64 or 128 or depending on NAND device type. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1045 NAND Boot Mode Table 12-31. Firmware Configuration Block Structure (continued) Name Start Byte Size in bytes Description m_u32NumberOfNANDs 32 4 Number of NAND devices present on the chip, this is ignored in i.MX28 ROM. May be useful for by other applications. m_u32TotalInternalDie 36 4 Number of internal dice present on the NAND chip. Not used by ROM. m_u32CellType 40 4 MLC or SLC, not used by ROM. m_u32EccBlockNEccType 44 4 Type of BCH Error Correction Level used for encoding BCH Blocks B1 through BN. Should be one of the following: 0 - BCH0 1 - BCH2 2 - BCH4 3 - BCH6 4 - BCH8 5 - BCH10 6 - BCH12 7 - BCH14 8 - BCH16 9 - BCH18 10 - BCH20 m_u32EccBlock0Size 48 4 Size of BCH Block B0. Typically 512 but can be any value limited to 900 bytes. m_u32EccBlockNSize 52 4 Size of BCH Blocks B1 through BN. Typically 512 but can be any value limited to 900 bytes. m_u32EccBlock0EccType 56 4 Type of BCH Error Correction Level used for encoding BCH Block B0. Should be one of the following: 0 - BCH0 1 - BCH2 2 - BCH4 3 - BCH6 4 - BCH8 5 - BCH10 6 - BCH12 7 - BCH14 8 - BCH16 9 - BCH18 10 - BCH20 m_u32MetadataBytes 60 4 Number of bytes in metadata of a page. Minimum value allowed is 1. If set to 0, ROM may not boot the image successfully. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1046 Freescale Semiconductor, Inc. Chapter 12 Boot Modes Table 12-31. Firmware Configuration Block Structure (continued) Name Start Byte Size in bytes Description m_u32NumEccBlocksPerPage 64 4 Number of BCH Blocks excluding B0. m_u32EccBlockNEccLevelSDK 68 4 This is for SDK/Application use only. Not used by ROM. m_u32EccBlock0SizeSDK 72 4 This is for SDK/Application use only. Not used by ROM. m_u32EccBlockNSizeSDK 76 4 This is for SDK/Application use only. Not used by ROM. m_u32EccBlock0EccLevelSDK 80 4 This is for SDK/Application use only. Not used by ROM. m_u32NumEccBlocksPerPageSDK 84 4 This is for SDK/Application use only. Not used by ROM. m_u32MetadataBytesSDK 88 4 This is for SDK/Application use only. Not used by ROM. m_u32EraseThreshold 92 4 This value will be set into BCH_MODE register. m_u32BootPatch 96 4 0 for normal boot and 1 for NAND patch boot. m_u32PatchSectors 100 4 Size of patch in pages. m_u32Firmware1_StartingSector 104 4 Starting page address of primary boot firmware. m_u32Firmware2_StartingSector 108 4 Starting page address of secondary boot firmware. m_u32SectorsInFirmware1 112 4 Number of pages occupied by primary boot firmware. m_u32SectorsInFirmware2 116 4 Number of pages occupied by secondary boot firmware. m_u32DBBTSearchAreaStartAddres 120 s 4 Starting page address of DBBT Search Area. m_u32BadBlockMarkerByte 124 4 Byte offset in page data containing manufacturer marked bad block marker information. m_u32BadBlockMarkerStartBit 128 4 For BCH ECC Levels other than BCH8 or BCH16 BI byte does not start at a byte boundary. This field will give the start bit number of BI in m_u32BadBlockMarkerByte. m_u32BBMarkerPhysicalOffset 132 4 This is the physical byte offset where manufacturer marked bad block marker. - 136 376 Spare bytes, should be set to 0. 12.12.1.14 Discovered Bad Block Table Header Layout Block Structure and Definitions The first 512 bytes of the DBBT header structure are as follows: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1047 NAND Boot Mode Table 12-32. DPPT Header Structure Name Start Byte Size in Bytes Description m_u32Checksum 0 4 32 bit checksum of 508 bytes of DBBT data from offset 4 to 512 XOR with 0xFFFF_FFFF m_u32FingerPrint 4 4 32 bit word with a value of 0x54424244, in ascii "DBBT" m_u32Version 8 4 32 bit version number; this version of DBBT is 0x0100_0000 m_u32NumberBB 12 4 Number of bad blocks present in the table. m_u32Number2KPagesBB 16 4 Bad blocks consume these many 2048 byte size pages. -- 20 492 Spare bytes, should be set to 0. 12.12.1.15 Discovered Bad Block Table Layout Block Structure and Definitions The actual bad block table structure is as follows: Table 12-33. Bad Block Table Structure Name Start Byte Size in Bytes Description uNAND 0 4 NAND number uNumberBB 4 4 Number of entries in DBBT u32BadBlock 8 2040 Array or Table for bad block entries, each 4 byte word in this array contain the block number that is bad. 12.12.2 Typical NAND Page Organization This section discusses the typical NAND page organization. In particular, it discusses the BCH ECC page organization, metadata requirements, and efuses/OTP bits used by the ROM NAND driver 12.12.2.1 BCH ECC Page Organization. For NAND boot, ROM restricts the size of a BCH data block to 512 bytes. The first data block is called block 0 and the rest of the blocks are called block N. Separate ECC levels can be used for block 0 and block N. The metadata bytes should be located at the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1048 Freescale Semiconductor, Inc. Chapter 12 Boot Modes beginning of a page, starting at byte 0, followed by data block 0, followed by ECC bytes for data block 0, followed by block 1 and its ECC bytes, and so on until N data blocks. The ECC level for block 0 can be different from the ECC level of rest of the blocks. Metadata bytes can be 0. For NAND boot, with page size restrictions and data block size restricted to 512 bytes, only few combinations of ECC for block 0 and block N are possible. M Block 0 512 bytes EccB 0 Block 1 512 bytes EccBN Block 2 512 bytes EccBN Block 3 512 bytes EccBN Figure 12-15. Valid layout for 2112 bytes sized page The number of ECC bits required for a data block is calculated using (ECC_Correction_Level * 13) bits. In the above layout, the ECC size for EccB0 and EccBN should be selected to not exceed a total page size of 2112 bytes. EccB0 and EccBN can be one of 2, 4, 6, 8, 10, 12, 14, 16, 18, 20 bits ECC correction level. The total bytes would then be: [M + (data_block_size * 4) + ([EccB0 + (EccBN * 3)] * 13) / 8] <= 2112; M=metadata bytes and data_block_size is 512. There are four data blocks of 512 bytes, each in a page of 2K page sized NAND. The values of EccB0 and EccBN should be such that the above calculation would not result in a value greater than 2112 bytes. M Block 0 5 1 2 bytes EccB 0 Block 1 5 1 2 bytes EccBN Block 2 5 1 2 bytes EccBN Block 3 5 1 2 bytes EccBN Block 4 5 1 2 bytes EccBN Block 5 5 1 2 bytes EccBN Block 6 5 1 2 bytes EccBN Block 7 5 1 2 bytes EccBN Figure 12-16. Valid layout for 4K bytes sized page Different NAND manufacturers have different sizes for a 4K page, 4314 bytes is typical. [M + (data_block_size * 8) + ([EccB0 + (EccBN * 7)] * 13) / 8] <= 4314; M=metadata bytes and data_block_size is 512. There are eight data blocks of 512 bytes, each in a page of a 4K page sized NAND. The values of EccB0 and EccBN should be such that above calculation should not result in a value greater than the size of a page in a 4K page NAND. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1049 NAND Boot Mode 12.12.2.2 Metadata The number of bytes used for metadata are specified in FCB. Metadata for BCH encoded pages will be placed at the beginning of a page. ROM only cares about the first byte of metadata to swap it with bad block marker byte in page data after each page read. It is therefore important to have at least one byte for metadata bytes field in FCB data structure. 12.12.2.3 efuses/OTP bits used by ROM NAND Driver Table 12-34. eFuses Register Name Description ROM1:2.. NUMBER_OF_NANDS 0 Three bits used for number of NANDs on the device. If left unblown, boot ROM will default to 1 device. It is important to program these bits to exact number of NANDs in the system, using this information ROM will enable internal pullups. The boot may fail if this field is incorrectly programmed. Max number of NAND devices allowed in MX28 is 8, but ROM only supports boot from NAND0. ROM1:7.. BOOT_SEARCH_STRIDE 4 Four bits for boot search stride. Boot ROM defaults it to 1. ROM multiplies this number with 64 to get search stride in pages. Typically, this should be left 0 or 1 for NAND devices with number of pages per block as 64. For 128 pages per block, it is recommended to program these bits to a value of 2 in order for each BCB to be placed in a new block. ROM1:11. BOOT_SEARCH_COUNT .8 Four bits for boot search count. If not programmed, boot ROM will default to 2. This value is raised to the power of 2 to get actual boot search count. Boot search count will tell ROM how many times a BCB is duplicated in a search area. ROM1:27. ENABLE_NAND_CE_RDY_PULLUPS .20 Eight bits to enable internal pullups on CE and RDY pins. Bit 20 is used to enable pullups on NAND0, Bit 21 is used to enable pullups on NAND1,... ... Bit 27 is used to enable pullups on NAND7. ROM1:30 DISABLE_SECONDARY_BOOT One bit to disable redundant boot. If this bit is programmed to 1, ROM will not try to boot from the secondary image if the primary image failed to boot. ROM4:3.. NAND_ROW_ADDRESS_BYTES 0 Four bits for number of row address bytes. If not programmed, ROM will default to 3 bytes for row (page) address. ROM4:7.. NAND_COLUMN_ADDRESS_BYTES 4 Four bits for number of column address bytes. If not programmed, ROM will default to 2 column address bytes. ROM4:15. NAND_READ_CMD_CODE1 .8 Eight bits for NAND read cmd code 1. If not programmed, ROM will default to 0 as NAND read cmd code 1. For BA NAND, these bits should be programmed to a value of 0xC0. ROM4:23. NAND_READ_CMD_CODE2 .16 Eight bits for NAND read cmd code 2. If not programmed, ROM will default to 0x30 as NAND read cmd code 2. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1050 Freescale Semiconductor, Inc. Chapter 12 Boot Modes Table 12-34. eFuses (continued) Register Name Description ROM4:31 NAND_BADBLOCK_MARKER_PRESERVE One bit to indicate that bad block marker byte is not preserved for _DISABLE page data, this will result in ROM not swapping metadata[0] with bad block byte offset in page data. This bit should never be programmed. It is available to cover up any defective ROM code in handling bad block marker byte swapping. 12.12.3 ONFi BA NAND Device Boot i.MX28 ROM supports boot from ONFI-BA (Open NAND Flash Interface - Block Abstracted) NAND. BA-NAND manages ECC, bad-blocks and wear-leveling inside its controller. ROM reads ONFI NAND device's parameter page to determine if the NAND device is ONFI-BA. The command set of BA NAND is different from the traditional raw NAND devices. For ONFI-BA NAND, ROM expects the first sector to contain a MBR with partition table. One of the partitions is firmware partition. ROM then expects a configuration block to be present on the first sector of firmware partition. The configuration block will have start address for FW1 and FW2. Here is the data structure of configuration block, it is same as config block described in SD Boot. #define FIRMWARE_CONFIG_BLOCK_SIGNATURE (0x00112233) //STMP typedef struct _DriveInfo_t { uint32_t u32ChipNum; //!< Chip Select, ROM does not use it uint32_t u32DriveType; //!< Always system drive, ROM does not use it uint32_t u32Tag; //!< Drive Tag // Below field u32FirstSectorNumber should be divisible by 4. Protocol is set to 4 sectors // of 512 bytes. Firmware can start at sectors 4, 8, 12, 16, ... uint32_t u32FirstSectorNumber; //!< Start sector/block address of firmware. uint32_t u32SectorCount; //!< Not used by ROM } DriveInfo_t; typedef struct _ConfigBlock_t { uint32_t u32Signature; //!< Signature 0x00112233 uint32_t u32PrimaryBootTag; //!< Primary boot drive identified by this tag uint32_t u32SecondaryBootTag; //!< Secondary boot drive identified by this tag uint32_t u32NumCopies; //!< Num elements in aFWSizeLoc array DriveInfo_t aDriveInfo[]; //!< Let array aDriveInfo be last in this data //!< structure to be able to add more drives in future //!< without changing ROM code } ConfigBlock_t; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1051 USB Boot Driver 12.13 USB Boot Driver The USB Boot Driver is implemented as a USB HID class and is referred to as the Recovery HID, or RHID. The RHID serves as a fail-safe mechanism for downloading and communicating with application-specific code. The system is based on two HID Application collections: the Boot Loader Transfer Controller (BLTC) and the Plug-in Transfer Controller (PITC). Each collection has its own set of HID reports. 12.13.1 Boot Loader Transaction Controller (BLTC) The BLTC provides a tunnel to download application-specific PITCs to the local system memory. The BLTC runs completely from ROM and interfaces directly to the ROM Loader. Typically, a PITC will be packaged on the host and downloaded through the BLTC and ROM Loader straight to OCRAM (or SDRAM). Four HID reports are provided for communication with the BLTC: * BLTC Command Out (BLCO) * BLTC Data Out (BLDO) * BLTC Data In (BLDI) * BLTC Status In (BLSI) The BLTC provides a command/data protocol for downloading code to the ROM Loader. The BLTC has no knowledge of the contents of the data passing through so, it is really possible to download anything (not just PITCs). 12.13.2 Plug-in Transaction Controller (PITC) The PITC is a generic command/data/status tunnel that may be used for any type of application. The implementation only specifies the HID report structure and the ROM HID-stack installation for a PITC--the protocol implementation is specific to a given PITC. Typically, a PITC will be downloaded to memory through the BLTC. Four HID reports are provided for communication with a PITC: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1052 Freescale Semiconductor, Inc. Chapter 12 Boot Modes * PITC Command Out (PICO) * PITC Data Out (PIDO) * PITC Data In (PIDI) * PITC Status In (PISI) The command/data protocol is specific to any given PITC. Only one PITC may be installed at any given time. 12.13.3 USB IDs and Serial Number By default, the USB Device Descriptor Vendor ID, Product ID, and serial number are reported as follows: * Vendor ID--0x15A2 * Product ID--0x004F * Serial Number String--none If any of the HW_OCOTP_ROM2 bits are blown, then the full contents of that OTP register are used to report the Vendor ID and Product ID. If the ENABLE_USB_BOOT_SERIAL_NUMBER OTP is blown, then a unique serial number will be generated from the factory-programmed SGTL_OPS3 OTP registers. 12.13.4 USB Recovery Mode USB boot mode is provided as a fail-safe mechanism for writing system firmware to the boot media. The boot mode is not usually entered by the normal methods of setting the boot pins or OTP, the other methods of entering USB boot mode are referred to generally as recovery mode. An end user can manually start the recovery mode by holding the recovery switch for several seconds while plugging in USB. Holding the recovery switch is defined as reading the i.MX28 PSWITCH input as a 0x3. There are several switch circuits that will produce this input. The loader also automatically starts recovery mode if a nonrecoverable error is detected from any boot mode other than USB. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1053 USB Boot Driver If the DISABLE_RECOVERY_MODE OTP bit is blown, then USB boot mode is disabled completely. Attempts to enter USB boot mode through boot pins, OTP, or recovery methods will result in a chip power-down. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1054 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 13.1 Data Co-Processor (DCP) Overview The DCP module provides support for general encryption and hashing functions typically used for security functions. Because the basic job of the DCP module is moving data from memory to memory, the DCP module also incorporates memory-copy (memcopy) function for both debugging and as a more efficient method of copying data between memory blocks than the DMA-based approach. The memcopy function also has a blit mode of operation where it can transfer a rectangular block of data to a video frame buffer. AXI Bus Master Hash Dual-Port FIFO Control Cipher APBH Slave Figure 13-1. Data Co-Processor (DCP) Block Diagram The i.MX28 DCP module implementation supports AES-128 encryption and CRC32, SHA-1, and SHA-256 hashing (see the Capability Register). The DCP module processes data based on chained command structures written to the system memory by software (in a manner similar to the DMA engine). The control block maintains registers to support four independent and concurrent chains, allowing software i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1055 Data Co-Processor (DCP) Overview to virtualize access to the DCP block. Each command in a chain represents a work unit that the module will process to completion. At the end of each work unit, the control logic arbitrates among chains with outstanding commands and processes a command from that chain. Arbitration among the channels is round-robin, allowing all active channels equal access to the data engine. Each channel also supports a high-priority mode that allows it to have priority over the remaining channels. If multiple channels are selected as high-priority, the channel arbiter selects among the high-priority channels in a round-robin fashion. The data flow through the DCP module can be configured in one of five fashions, depending on the functionality activated by the control packet: * Memcopy/Blit Mode--Data is moved unchanged from one memory buffer to another. AXI FIFO AXI Figure 13-2. Memcopy/Blit Mode * Encryption Only--Data from source buffer is encrypted/decrypted into the destination buffer. AXI Encryption Decryption FIFO FIFO AXI Figure 13-3. Encryption Only * Hashing Only--Data from source buffer is read, and a hash is generated. AXI Hash Figure 13-4. Hashing Only * Encryption and Input Hashing--Data from source buffer is encrypted/decrypted into destination, and source buffer is hashed. AXI FIFO Encryption Decryption FIFO AXI Hash Figure 13-5. Encryption and Input Hashing * Encryption and Output Hashing--Data from source buffer is encrypted/decrypted into destination, and output data is hashed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1056 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) AXI FIFO Encryption Decryption FIFO AXI Hash Figure 13-6. Encryption and Output Hashing 13.1.1 DCP Limitations for Software While the DCP module has been designed to be as flexible as possible, there are a few limitations to which software must adhere: * Buffer sizes for all operations MUST be aligned to the natural size of the transfer algorithm used. Memcopy operations can transfer any number of bytes (one-byte granularity) and AES operations must be multiples of 16 bytes (four-word granularity). For all operations, if the byte count is not a word granularity, the hardware rounds up to the next word. Hashing is supported at a byte granularity. * The DCP module supports buffer operations to any byte alignment, but performance will be improved if buffers are aligned to a four-byte boundary, since fetch/store operations can be performed without having to do byte operations to accommodate the misaligned addresses. * Hash operations are limited to a 512 Mbyte buffer size. The hardware only implements a 32-bit hash length counter instead of the 64-bit counter supported by the SHA-1/SHA-256 algorithm (counter counts bits, not bytes, therefore a total of 512 Mbytes). * For chained hashing operations (operations involving multiple descriptors), every descriptor except the last must have a byte count that is a 16-word multiple (granularity of the hash algorithm). * Key values cannot be written while the AES block is active. This limitation exists because the key RAM is in use while AES is operational. Any writes from the APB cannot be held in wait states; therefore, the RAM must be accessible during key writes. * The byte-swap controls can only be used with modulo-4 length buffers. For nonmodulo-4 lengths, the final partial word will contain incorrect data. Any address alignment can be used with byte swapping, however. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1057 Operation * The word-swap controls are only useful with cipher operations, because the logic forms the 128-bit cipher data from four words from system memory. The word-swap controls are ignored for memcopy or hashing operations. * DCP only supports writes to word boundaries to OCRAM. This is not required for EMI DRAM address. 13.2 Operation The top-level DCP module contains the AXI master, APB slave bus interface units, the main control block and FIFO, and any encryption or hashing blocks included with the design. The controller manages the fetching of work blocks, the fetching/storing of context information when switching between chain pointers, and the data flow through FIFO, SHA, and AES blocks. Data entering the block from the AXI master is placed in the FIFO for consumption by the cipher block. After the cipher module has finished its operation, data is placed back into the FIFO and stored back to memory through the AXI master. When hashing is enabled, the SHA block takes its inputs from the bus side of the FIFO to allow it to operate without waiting for the cipher block to complete. The APB slave provides all register controls and interfaces mainly with the control block. 13.2.1 Memory Copy, Blit, and Fill Functionality In its most basic operation, the DCP supports moving unmodified data from one place in system memory to another. This functionality is referred to as memcopy, because it operates only on memory and it copies data from one place to another. Typical uses of memcopy might be for fast virtual memory page moves or repositioning data blocks in memory. Memcopy buffers can be aligned to any memory address and can be of any length (byte granularity). For best performance, buffers should be word-aligned, although the DCP includes enhancements to improve performance for unaligned cases. The DCP also has the ability to perform basic blit operations that are typical in graphics operations. To specify a blit, the control packet must have the ENABLE_BLIT bit set in the packet control register. Blit source buffers must be contiguous. The output destination buffer for a blit operation is defined as a "M runs of N bytes" that define a rectangular region in a frame buffer. For blit operations, each line of the blit may consist of any number of bytes. After performing a run, the DCP updates the destination pointer such i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1058 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) that the next destination address falls on the pixel below the start of the previous run operation. This is performed by incrementing the starting pointer by the frame buffer width, which is specified in Control1 field. In addition to being able to copy data within memory, the DCP also provides a fill operation, where source data comes not from another memory location, but from an internal register (the source buffer address in the control packet). This is performed whenever the CONSTANT_FILL flag is set in the packet control register. This feature may be used with memcopy to prefill memory with a specified value or during a blit operation to fill a rectangular region with a constant color. 13.2.2 Advanced Encryption Standard (AES) The AES block implements a 128-bit key/data encryption/decryption block as defined by the National Institute of Standards and Technology (NIST) as US FIPS PUB 197, dated November 2001 (see references for specifications and toolkits)1. There are three variations of AES, each corresponding to the key size used: AES-128, AES-192 or AES-256. AES always operates on 128 bits of data at a time. Only the AES-128 algorithm is implemented at this time. 13.2.2.1 Key Storage The DCP implements four SRAM-based keys that may be used by software to securely store keys on a semi-permanent basis. The keys may be written through the PIO interface by specifying a key index to specify which key to load and a subword pointer that indicates which word to write within the key. After a subword is written, the logic automatically increments the subword pointer so that software can program the higherorder words of the key without rewriting the key index. Keys written into the key storage are not readable. To use a key in the key storage, the cipher descriptor packet should select the key by setting the KEY_SELECT field in the Control1 descriptor field without setting the OTP_KEY or PAYLOAD_KEY fields in the Control0 register. 1. The AES core used in the design was derived from the AES design available from OpenCores.org under a modified BSD license as described here: http://www.opencores.org/projects.cgi/web/aes_core/overview The license for this code is documented in Disclaimer for compliance. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1059 Operation 13.2.2.2 AES OTP Key After a system reset, the OTP controller reads the e-fuse devices and provides OTP key information to the DCP. The DCP receives a 64-bit UNIQUE KEY and a 128-bit CRYPTO KEY. Depending on a key path control fuse the DCP receives the CRYTPO KEY either directly or indirectly through the SNVS trust controller module. The CRYPTO KEY in fuses is actually 256 bits and a mux is used to select the high or low 128 bits of the key. The DCP internally generates the control logic signals to capture this key into the key RAM. The system reset controller coordinates the deassertion of reset such that the OTP key is stable before the DCP reads it. If the SNVS key path is chosen then a security violation removes the CRYPTO KEY, resets the key in the DCP, and makes the key unavailable to the DCP until the next successful secure boot. To use the OTP key, the descriptor packet should set the OTP_KEY field in the Control1 register. 13.2.2.3 Encryption Modes The most basic form of encryption is the Electronic Code Book (ECB) mode. In this mode, the encryption output is a function only of the key and the plaintext, therefore, it can be visualized as a giant lookup table. While this provides a great deal of security, there are a few limitations. For instance, if the same plaintext appears more than once in a block of data, the same ciphertext will also appear. This can be very evident if the plaintext contains large blocks of constant data (0s for example) and can be used to formulate attacks against a key. In order to make ciphers stronger, several modes of operation can be implemented around the basic ECB cipher to provide additional security. One such mode is CBC mode (Cipher Block Chaining), which takes the previous encrypted data and logically XORs it with the next incoming plaintext before performing the encryption. During decryption, the process is reversed and the previous encrypted data is XORed with the decrypted ECB data to provide the plaintext again. The AES engine supports handling the various modes of operation. The core AES block supports ECB mode and other algorithms are handled in the wrapper around the encryption blocks. The DCP module supports Cipher Block Chaining (CBC), which chains the data blocks by XORing the previously encrypted data with the plaintext before encryption. Cipher block chaining encryption is illustrated in Figure 13-7. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1060 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) Plaintext Plaintext Block Cipher Encryption Block Cipher Encryption Plaintext Initialization Vector (IV) Key Key Key Ciphertext Ciphertext Block Cipher Encryption Ciphertext Figure 13-7. Cipher Block Chaining (CBC) Mode Encryption Decryption (shown in the following figure) works in a similar manner, where the cipher text is first decrypted and then XORed with the previous ciphertext. For the first encryption/decryption operation, an initialization vector (IV) is used to seed the operation. The IV must be the same for both the encryption and decryption steps; otherwise, decrypted data will not match the original plaintext. Ciphertext Ciphertext Ciphertext Block Cipher Decryption Block Cipher Decryption Block Cipher Decryption Initialization Vector (IV) Key Plaintext Key Key Plaintext Plaintext Figure 13-8. Cipher Block Chaining (CBC) Mode Decryption 13.2.3 Hashing The hashing module implements SHA-1 and SHA-256 hashing algorithms and a modified CRC-32 checksum algorithm. These algorithms produce a signature for a block of data that can be used to determine whether the data is intact. The CRC-32 algorithm implements a 32-bit CRC algorithm similar to the one used by Ethernet and many other protocols. The CRC differs from Unix cksum() function in three ways: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1061 Operation * The CRC is initialized as 0xFFFFFFFF instead of 0x00000000. * Logic pads zeros to a 32-bit boundary for trailing bytes. * Logic does not post-pend the file length. The SHA-1 block implements a 160-bit hashing algorithm that operates on 512-bit (64byte) blocks as defined by US FIPS PUB 180-1 in 1995. The SHA-256 mode implements a 256-bit hashing algorithm that operates on 512-bit (64-byte) blocks as defined by US FIPS PUB 180-2 in 2002. The purpose of the hashing module is to generate a unique signature for a block of data that can be used to validate the integrity of the data by comparing the resulting digest with the original digest. Results from hash operations are written to the beginning of the payload for the descriptor. The DCP also has the ability to check the resulting hash against a value in the payload and issue an interrupt if a mismatch occurs. 13.2.4 One Time Programmable (OTP) Key While OTP key is normally not available to read operations, the module will allow the key to be read if the otp_crypto_key_ren (read-enable) input is active (high). This allows verification of the key after it has been programmed into the eFuse device. After programming has been validated, another fuse will be set to disable the read capability. The OTP key (crypto key) may be selected using the DCP_Control1[OTP_KEY] bit in the control field of the packet descriptor or by using key select 0xFF in the CTRL1 field of the descriptor. DCP also supports a second hardware key called the UNIQUE_KEY which is generated from the OTP KEY and key modifier bits from other OTP fuse fields. This key is unique to the device and may be used for encrypting private data stored on the NAND. This key may be selected by writing 0xFE to the KEY_SELECT field in the CTRL1 packet data. 13.2.5 Managing DCP Channel Arbitration and Performance The DCP can have four channels all competing for DCP resources to complete their operations. Depending on the situation, critical operations may need to be prioritized above less important operations to ensure smooth system operation. To help software achieve this goal, the DCP implements a programmable arbiter for internal DCP operations and provides recovery timers on each channel to throttle channel activity. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1062 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 13.2.5.1 DCP Arbitration Priority Level The DCP implements a multi-tiered arbitration policy that allows software a lot of flexibility in scheduling DCP operations. The following figure illustrates the arbitration levels and where each channel fits into the arbitration scheme. 0 Channels 2 1 3 High 1 1 1 1 Low 0 0 0 0 Figure 13-9. DCP Arbitration Each channel can be programmed as being in either the high-priority or low-priority arbitration pool, depending on the setting in the HIGH_PRIORITY_CHANNEL field of the HW_DCP_CHANNELCTRL register. When the corresponding bit is programmed as a 1, the channel arbitrates in the high-priority pool; otherwise, it arbitrates in the lowpriority pool. Once a channel has been selected, it completes one packet and then the arbiter re-arbitrates. The channel that just completed participates in the new arbitration round. 13.2.5.2 Channel Recovery Timers Each channel also contains a channel recovery timer in its HW_DCP_CHnOPTS register. The purpose of the recovery timer is to keep the channel inactive for a period of time after it completes an operation. This capability could be used for a high-priority channel to ensure that at least some lower-priority requests get serviced between packets or to simply allow more timeslices for other channels to perform operations. The value programmed into the recovery timers register delays the channel from operations until 16 times the programmed value. Any non-zero value should prevent the channel from participating in the next arbitration cycle. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1063 Operation 13.2.6 Programming Channel Operations The control logic block maintains the channel pointers and manages arbitration and context switching between the different channels. It also manages the fetching of work packets and data fetch/store operations from the AXI master interface and coordinates the actions of the hashing and encryption blocks. The control logic maintains four channels that allow software to effectively create four independent work sets for the DCP module. Software can construct chained control packets in memory that describe encryption/hashing/memcopy operations to the hardware unit. The address for this first control packet can be written to one of the four virtual channels and enabled. When one or more of the channels is enabled, the controller fetches the control packet pointed to by that channel and initiates data fetches from the source buffer. Data is then processed as described in the control packet and stored back to the system memory. Once the processing for a control packet is complete, the controller writes completion status information back to the control packet, and optionally stores relevant state information to the context buffer. If the control packet specifies a subsequent control packet, the channel's pointer is updated to the address for the next packet and an optional interrupt can be issued to the processor. At this point, the DCP module arbitrates among the virtual channels for the next operation and processes its control packet. If a subsequent operation is continued from a previous operation, the controller automatically loads the context from the previous session into the working registers before resuming operation for that channel. 13.2.6.1 Virtual Channels The DCP module processes data through work packets stored in memory. Each of the channels contains a pointer to the current work packet and enough control logic to determine whether the channel is active and to provide status to the processor. Each channel also provides a recovery timer to help throttle processing by a particular channel. After processing a packet, the channel enables its 16-bit recovery timer (if the recovery time is set to a non-zero value). The channel will not become active again until its recovery timer has expired. The recovery timer timebase is 16 HCLK cycles, so the timer acts as a 20-bit timer with the bottom four bits implicitly tied to 0. This provides an effective range of zero to 220-1 clocks or 0 ns to 7.8 ms at 133 MHz. A channel is activated any time its semaphore is non-zero and its recovery timer is cleared. The semaphore can be incremented by software to indicate that the chain pointer has been loaded with a valid pointer. As the hardware completes the work packets, it decrements the semaphore if the Decrement Semaphore flag in the Control 0 field is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1064 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) Work packets may be chained together using the CHAIN or CHAIN_CONTIGUOUS bits in the Control0 field, which causes the channel to automatically update the work packet pointer to the value in the NEXT_COMMAND_ADDRESS field at the end of the current work packet. 13.2.6.2 Context Switching The control logic maintains four virtual channels that allow the DCP block to timemultiplex encryption, hashing and memcopy operations, it must also retain state information when changing channels so that when a channel is resumed, it can resume the operation from where it left off. This process is called context-switching. To minimize the number of registers used in the design, the controller saves context information from each channel into a private context area in the system memory. When initializing the DCP module, software must allocate memory for the context buffer and write the address into the Context Buffer Pointer register. As the DCP module processes packets, it saves the context information for each channel to the buffer after completing each control packet. When the channel is subsequently activated, the DCP module's internal registers are then reloaded with the proper context before resuming the operation. Each channel reserves one-fourth of the context buffer area for its context storage. The context buffer consumes 208 bytes of system memory and is formatted as shown in the following table. Table 13-1. DCP Context Buffer Layout RANGE Channel Data Size 0x00-0x0C 3 Cipher Context 16 bytes Hash Context 36 bytes 2 Cipher Context 16 bytes Hash Context 36 bytes 1 Cipher Context 16 bytes Hash Context 36 bytes Cipher Context 16 bytes Hash Context 36 bytes 0x10-0x30 0x34-0x40 0x44-0x64 0x68-0x74 0x78-0x98 0x9C-0xA8 0xAC-0xCC 0 The control logic writes to the context buffer only if the function is being used. This effectively means that the cipher context is stored for CBC encryption/decryption operations only and the hash context is written only if SHA-1/SHA-256 is utilized. If neither of these modes are used for a given channel, the memory for the context buffer need not be allocated by the software. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1065 Operation Since channel 0 is likely to be used for VMI in an SDRAM-based system-to-page data from the SDRAM to on-chip SRAM, the buffer allocation table has been organized so that the highest numbered channel uses the lowest area in the context buffer. For this reason, software should allocate the higher numbered channels for encryption/hashing operations and the lower numbered channels for memcopy operations to reduce the size of the context buffer. If only a single channel is used for CBC mode operations or hashing operations, the controller provides a bit in the control register to disable context switching. In this scenario, context switching is not required, because other channels will not corrupt the state of the hashing or cipher modes. Therefore, when the channel resumes, a context load is not required. Additionally, the control logic monitors the use of CBC/hashing, so that a context reload is not performed if the previous channel resumes an operation without an intermediate operation from another channel. 13.2.6.3 Working with Semaphores Each channel has a semaphore register to indicate that control packets are ready to be processed. Several techniques can be used when programming the semaphores to control the execution of packets within a channel. The channel will continue to execute packets as long as the semaphore is non-zero, a chain bit is set in the descriptor and no error has occurred. * Software can write the number of pending packets into the semaphore register with the Decrement Semaphore bit in each control packet set. In this scenario, the channel simply decrements the semaphore for each packet set and terminates at the end of the packet chain. The benefit of this method is that software can easily determine how many packets have executed by reading the semaphore status register. * Software can create a packet chain with the Decrement Semaphore bit set only in the last packet. In this case, software would write a 1 to the semaphore register to start the chains and the DCP will terminate after executing the last packet. * Software can create a packet chain with the Decrement Semaphore bit set for each packet and write either a 1 or a number less than the number of packets to the semaphore register. This can be useful when debugging, because it allows the channel to execute only a portion of the packets and software can inspect intermediate values before restarting the channel again. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1066 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) If an error occurs, the channel issues an interrupt and clears the semaphore register. The channel does not perform any further operations until the error bits in the status register have been cleared. Software can manually clear a non-zero semaphore by writing 0xFF to the CLR (clear) address of the semaphore register. 13.2.6.4 Work Packet Structure Work packets for the DCP module are created in memory by the processor. Each work packet includes all information required for the hardware to process the data. The general structure of the packet is shown below. Table 13-2. DCP Work Packet Structure Word0 Next Cmd Addr Word1 Control0 Word2 Control1 Word3 Source Buffer Addr Word4 Destination Buffer Addr Word5 Buffer Size Word6 Payload Pointer Word7 Status For some operations, additional information is required to process the data in the packet. This additional information is provided in the variable-sized payload buffer, which can be found at the address specified in the payload pointer field. When encryption is specified, the payload may include the encryption key (if the key selected resides in the packet), an initialization vector (for modes of operation such as CBC), and expected hash values when data hashing is indicated. The hardware can automatically compare the expected hash with the actual hash and interrupt the processor only on a mismatch. The payload area is used by software to store the calculated hash value at the end of hashing operations (when the HASH_TERM control bit is set). 13.2.6.4.1 Next Command Address Field The NEXT_COMMAND_ADDRESS field (as shown in the following table) is used to point to the next work packet in the chain. This field is loaded into the channel's command pointer after the current packet has completed processing if the CHAIN bit in the CONTROL0 field (see Table 13-4) is set. The Next Command Address field should be programmed to a non-zero value when the CHAIN bit is set; otherwise, the channel will flag an invalid setup error. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1067 Operation Table 13-3. DCP Next Command Address Field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 NEXT_COMMAND_ADDRESS 13.2.6.4.2 Control0 Field The main functions of the DCP module are enabled with the ENABLE_MEMCOPY, ENABLE_BLIT, ENABLE_CIPHER and ENABLE_HASH bits from the Control0 field in the work packet. The combinations of these bits determine the function performed by the DCP. Table 13-5 summarizes the function performed for each combination. Table 13-4. DCP Control0 Field DECR_SEMAPHOR E INTERRUPT_ENABL E CHAIN CHAIN_CONTINUOUS ENABLE_CIPHE R ENABLE_MEMCOPY ENABLE_HASH CIPHER_ENCRYP T ENABLE_BLIT OTP_KEY CIPHER_INIT PAYLOAD_KEY HASH_INIT HASH_TERM HASH_CHECK HASH_OUTPUT CONSTANT_FILL KEY_BYTESWA P TEST_SEMA_IRQ KEY_WORDSWAP INPUT_BYTESWAP INPUT_WORDSWAP OUTPUT_WORDSWAP TAG OUTPUT_BYTESWAP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Table 13-5. DCP Function Enable Bits HASH Cipher Blit Memcopy 0 0 0 X Simple memcopy operation. 0 0 1 0 Blit operation. 0 1 0 0 Simple encrypt/decrypt operation. 1 0 0 0 Simple hash. Only reads performed. 1 0 0 1 Memcopy and hash operation. 1 1 0 0 Hash with encryption/decryption. All Others Description Invalid setup. The CHAIN bit should be set if the NEXT_COMMAND_ADDRESS field has a valid pointer to the next work packet. When set, this bit causes the channel to update its pointer to the next packet. The CHAIN_CONTINUOUS bit is similar, but it indicates that the next packet follows immediately after the current packet. This allows software to generate templates of operations without regard to the actual physical addresses used, which makes programming easier, especially in a virtual memory environment. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1068 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) If the INTERRUPT_ENABLE bit is set, the channel generates an interrupt to the processor after completing the work for this packet. When the interrupt is issued, the packet will have been completely processed, including the update of the status/payload fields in the work packet. Each channel contains an eight-bit counting semaphore that controls whether it is in the run or idle state. When the semaphore in non-zero, the channel is ready to run and process commands. Whenever a command finishes its operation, it checks the DECR_SEMAPHORE bit. If set, it decrements the counting semaphore. If the semaphore goes to 0 as a result, then the channel enters the idle state and remains there until the semaphore is incremented by software. When the semaphore goes to non-zero and the channel is in its idle state, it then uses the value in the NEXT_COMMAND_ADDRESS field to begin processing. If the ENABLE_CIPHER bit is set, the data is encrypted or decrypted based on the CIPHER_ENCRYPT bit using the key/encryption settings from the Control1 field. The OTP_KEY and PAYLOAD_KEY indicates the source of the keys for the operation. If the OTP_KEY value is set, the KEY_SELECT field from the Control1 register indicates which OTP key is to be used. If the PAYLOAD_KEY bit is set, the first entry in the payload is the key to be used for the operation. If neither bit is set, the KEY_SELECT field indicates an index in the key RAM that contains the key to be used. (For cases when both the OTP_KEY and PAYLOAD_KEY bits are set, the PAYLOAD_KEY takes precedence.) The HASH_ENABLE enables hashing of the data with the HASH_OUTPUT bit controlling whether the input data (HASH_OUTPUT=0) or output data (HASH_OUTPUT=1) is hashed. In addition, the hardware can be programmed to automatically check the hashed data if the HASH_CHECK bit is set. If the hash does not match, an interrupt is generated and the channel terminates operation on the current chain. The hashing algorithms also require two additional fields in order to operate properly. The HASH_INIT bit should be set for the first block in a hashing pass to properly initialize the hashing function. The HASH_TERM bit must be set on the final block of a hash to notify the hardware that the hashing operation is complete so that it can properly pad the tail of the buffer according to the hashing algorithm. This flag also triggers the write-back of the hash output to the work packet's payload area. The CONSTANT_FILL flag may be used for both memcopy and blit operations. When this is set, the source address field is used instead as a constant that is written to all locations in the output buffer. The WORDSWAP and BYTESWAP bits enable muxes around the FIFO to swap data to handle little-endian and big-endian storage of data in system memory. When these bits are cleared, data is assumed to be in little-endian format. When all bits are set, data is assumed to be in big-endian format. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1069 Operation The TAG field is used to identify the work packet and the associated completion status. As each packet is completed, the channel provides the status and tag information of the last packet processed. 13.2.6.4.3 Control1 Field The Control1 field (shown in the following table) provides additional values used when hashing or encrypting/decrypting data. For blit operations, this field indicates the number of bytes in a frame buffer line, which is used to calculate the address for successive lines in each blit operation. Table 13-6. DCP Control1 Field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CIPHER_CONFIG HASH_SELE CT KEY_SELECT CIPHER_MO CIPHER_SEL DE ECT FRAMEBUFFER_LENGTH (in bytes, blit mode) The CIPHER_SELECT field selects from one of sixteen possible encryption algorithms (0=AES128). The CIPHER_MODE selects the mode of operation for that cipher (0=ECB, 1=CBC). The KEY_SELECT field allows key selection for one of several sources. Keys can be included in the packet payload or may come from OTP or write-only registers. The HASH_SELECT field selects a hashing algorithm for the operation (0=SHA-1, 1=CRC32, 2=SHA-256). The CIPHER_CONFIG field provides the optional configuration information for the selected cipher. An example would be a key length for the RC4 algorithm. 13.2.6.4.4 Source Buffer The SOURCE_BUFFER pointer (shown in the following table) specifies the location of the source buffer in memory. The buffer may reside at any byte alignment and should refer to an on-chip SRAM of off-chip SDRAM location. For optimal performance, buffers should be word aligned. When the CONSTANT_FILL flag is set in the Control0 field, the value in this field is used as the data written to all destination buffer locations. Table 13-7. DCP Source Buffer Field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SOURCE_BUFFER CONSTANT (CONSTANT_FILL mode) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1070 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 13.2.6.4.5 Destination Buffer The DESTINATION_BUFFER (shown in the following table) specifies the location of the destination buffer in on-chip SRAM or off-chip SDRAM memory and may be set to any byte alignment. For in-place encryption, the destination buffer and source buffer should be the same value. For optimal performance, the buffer location should be wordaligned. Table 13-8. DCP Destination Buffer Field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 DESTINATION_BUFFER 13.2.6.4.6 Buffer Size Field The BUFFER_SIZE field (shown in the following table) indicates the size of the buffers for memcopy, encryption, and hashing modes. For memcopy and hashing operations, the value may be any number of bytes (byte granularity) and for encryption modes, the length must be a multiple of the selected encryption algorithm's natural data size (16 bytes for AES). Table 13-9. DCP Buffer Size Field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 NUMBER_LINES (blit mode) BLIT_WIDTH (in bytes, blit mode) BUFFER_SIZE (in bytes, memcopy, encryption, hashing modes) For blit operations, the buffer size field is split into two portions, a BLIT_WIDTH value, which specifies the number of bytes in each line of the blit operation and a NUMBER_LINES value, which specifies how many vertical rows of pixels are in the image buffer. 13.2.6.4.7 Payload Pointer Some operations require additional control values that are stored in a Payload Buffer (shown in the table below), which is pointed to by this field. After the DCP reads the control packet, it examines the Control0 register and determines whether any payload information is required. If so, the DCP loads the payload from the address specified in this field. (See Payload for more details.) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1071 Operation Table 13-10. DCP Payload Buffer Pointer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PAYLOAD_POINTER The payload area is also written to by the DCP at the completion of a hash operation (when the HASH_TERM) bit is set. Software must allocate the appropriate amount of storage (20 bytes for SHA-1 and 4 bytes for CRC32) in the payload or risk having the DCP write to an unallocated address. 13.2.6.4.8 Status After the DCP engine has completed processing a descriptor, it writes the packet status (shown in the following table) back to the descriptor In the Status field. The packet status is the value of the channel status register at the time the packet completed processing. Table 13-11. DCP Status Field COMPLETE ERROR_CODE ERROR_DS T ERROR_SR C ERROR_PACKET TAG ERROR_SETU P HASH_MISMATCH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 For various error conditions, the DCP encodes additional error information in the ERROR_CODE field. See Programmable Registers for more details on assignments of error codes. For any completion codes besides the COMPLETE flag, the channel suspends processing the command chain until the error status values are cleared in the channel status register. The format for this field is same as the channel status register, with the exception that the COMPLETE bit is written to the payload status but is not present in the channel status register. 13.2.6.4.9 Payload The payload is a variable-length field that is used to provide key, initialization values, and expected results from hashing operations. The payload may consist of the data fields listed in the following table. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1072 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) Table 13-12. DCP Payload Field FIELD NAME SIZE DESCRIPTION CONDITION Cipher Key 16 bytes AES key Cipher enable with PAYLOAD_KEY Cipher IV 16 bytes CBC initialization vector Cipher enable with CBC mode. Hash Check 20 bytes Hash completion value Hash enabled with HASH_TERM fields set. If fields are not used, they do not appear in the payload and the other payload values move upwards in the payload area. For instance, if only hashing is used, then the HASH_CHECK value would appear at offset 0 in the payload area. The following table should be used by software to determine the amount of payload to allocate and initialize. Table 13-13. DCP Payload Allocation by Software CONTROL BITS PRESENT HASH_CHECK CIPHER_INIT PAYLOAD_KEY PAYLOAD SIZE 0 0 0 0 words / 0 bytes 0 0 1 4 words / 16 bytes 0 1 0 4 words / 16 bytes 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 8 words / 32 bytes SHA-1: 5 words / 20 bytes SHA-2: 8 words / 32 bytes SHA-1: 9 words / 36 bytes SHA-2: 12 words / 48 bytes SHA-1: 9 words / 36 bytes SHA-2: 12 words / 48 bytes SHA-1: 13 words / 52 bytes SHA-2 16 words / 64 bytes For hashing operations, the DCP module writes the final hash value back to the start of the payload area for descriptors with the HASH_TERM bit set in the control packet. It is important that software allocates the required payload space, even though it is not required to set up the payload for control purposes. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1073 Programming DCP Functions 13.2.7 Programming DCP Functions 13.2.7.1 Basic Memory Copy Programming Example To perform a basic memcopy operation, only a single descriptor is required. The DCP simply copies data from the source to the destination buffer. This process is illustrated in the following figure. Next Ctrl0 Tag 0x13 Ctrl1 Src Source Buffer Address Dst Destination Buffer Address Bytes Byte Count Payld Source Buffer Destination Buffer Stat 0x13 = Memcopy | DecrSema | Interrupt Figure 13-10. Basic Memory Copy Operation typedef struct _dcp_descriptor { u32 *next; hw_dcp_packet1_t ctrl0; hw_dcp_packet2_t ctrl1; u32 *src, *dst, buf_size, *payload, stat; } DCP_DESCRIPTOR; DCP_DESCRIPTOR dcp1; u32 *srcbuffer, *dstbuffer; // set up control packet dcp1.next = 0; // single packet in chain dcp1.ctrl0.U = 0; // clear ctrl0 field dcp1.ctrl0.B.ENABLE_MEMCOPY = 1; // enable memcopy dcp1.ctrl0.B.DECR_SEMAPHORE = 1; // decrement semaphore dcp1.ctrl0.B.INTERRUPT = 1; // interrupt dcp1.ctrl1.U = 0; // clear ctrl1 dcp1.src = srcbuffer; // source buffer dcp1.dst = dstbuffer; // destination buffer dcp1.buf_size = 512; // 512 bytes dcp1.payload = NULL; // not required dcp1.status = 0; // clear status // Enable channel 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1074 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) HW_DCP_CHnCMDPTR_WR(0, dcp1); HW_DCP_CHnSEMA_WR(0, 1); // write packet address to pointer register // increment semaphore by 1 // now wait for interrupt or poll // polling code while ( (HW_DCP_STAT_RD() & 0x01) == 0x00 ); // now check/clear channel status if ( (HW_DCP_CHnSTAT_RD(0) & 0xFF) != 0 ) { // an error occurred HW_DCP_CHnSTAT_CLR(0, 0xff); } // clear interrupt register HW_DCP_STAT_CLR(1); 13.2.7.2 Basic Hash Operation Programming Example To perform a basic hash operation, only a single descriptor is required. The DCP simply reads data from the source buffer and computes the hash value on the contents. This process is illustrated below. Next Ctrl0 Tag 0x70 Ctrl1 Src SHA1 Source Buffer Address Dst Payload Bytes Payld Source Buffer 0x43 Byte Count Payload Addrses Expected Hash Stat 0x70 = Hash Check | Hash Term | Hash Init 0x43 = Hash Enable | DecrSema | Interrupt Figure 13-11. Basic Hash Operation typedef struct _dcp_descriptor { u32 *next; hw_dcp_packet1_t ctrl0; hw_dcp_packet2_t ctrl1; u32 *src, *dst, buf_size, *payload, stat; } DCP_DESCRIPTOR; DCP_DESCRIPTOR dcp1; u32 *srcbuffer; u32 payload[5]; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1075 Programming DCP Functions // set up expected hash check value payload[0]=0x01234567; payload[1]=0x89ABCDEF; payload[2]=0x00112233; payload[3]=0x44556677; payload[4]=0x8899aabb; // set up control packet dcp1.next = 0; // single packet in chain dcp1.ctrl0.U = 0; // clear ctrl0 field dcp1.ctrl0.B.HASH_CHECK = 1; // check hash when complete dcp1.ctrl0.B.HASH_INIT = 1; // initialize hash with this block dcp1.ctrl0.B.HASH_TERM = 1; // terminate hash with this block dcp1.ctrl0.B.ENABLE_HASH = 1; // enable hash dcp1.ctrl0.B.DECR_SEMAPHORE = 1; // decrement semaphore dcp1.ctrl0.B.INTERRUPT = 1; // interrupt dcp1.ctrl1.U = 0; // clear ctrl1 dcp1.src = srcbuffer; // source buffer dcp1.dst = 0; // no destination buffer dcp1.buf_size = 512; // 512 bytes dcp1.payload = payload; // holds expected hash value dcp1.status = 0; // clear status // Enable channel 0 HW_DCP_CHnCMDPTR_WR(0, dcp1); HW_DCP_CHnSEMA_WR(0, 1); // write packet address to pointer register // increment semaphore by 1 // now wait for interrupt or poll // polling code while ( (HW_DCP_STAT_RD() & 0x01) == 0x00 ); // now check/clear channel status if ( (HW_DCP_CHnSTAT_RD(0) & 0xFF) != 0 ) { // an error occurred HW_DCP_CHnSTAT_CLR(0, 0xff); } // clear interrupt register HW_DCP_STAT_CLR(1); 13.2.7.3 Basic Cipher Operation Programming Example To perform a basic cipher operation, only a single descriptor is required. The DCP reads data from the source buffer, encrypts it, and writes it to the destination buffer. For this example, the key is provided in the payload and the algorithm uses the AES CBC mode of operation. This requires a payload with both the key and CBC initialization value. This process is illustrated below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1076 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) Next Ctrl0 Tag 0x0B Ctrl1 Src Dst Source Buffer 0x23 CBC AES Source Buffer Address Destination Buffer Address Bytes Byte Count Payld Payload Address Destination Buffer Stat 0x0B = Payload Key | Cipher Init | Encrypt 0x23 = Cipher Enable | DecrSema | Interrupt Payload Key CBC Init Figure 13-12. Basic Cipher Operation typedef struct _dcp_descriptor { u32 *next; hw_dcp_packet1_t ctrl0; hw_dcp_packet2_t ctrl1; u32 *src, *dst, buf_size, *payload, stat; } DCP_DESCRIPTOR; DCP_DESCRIPTOR dcp1; u32 *srcbuffer; u32 *dstbuffer; u32 payload[8]; // set up key/CBC init in the payload payload[0]=0x01234567; // key payload[1]=0x89ABCDEF; payload[2]=0xfedcba98; payload[3]=0x76543210; payload[4]=0x00112233; // CBC initialization payload[5]=0x44556677; payload[6]=0x8899aabb; payload[7]=0xccddeeff; // set up control packet dcp1.next = 0; dcp1.ctrl0.U = 0; dcp1.ctrl0.B.PAYLOAD_KEY = 1; dcp1.ctrl0.B.CIPHER_ENCRYPT = 1; dcp1.ctrl0.B.CIPHER_INIT = 1; dcp1.ctrl0.B.ENABLE_CIPHER = 1; dcp1.ctrl0.B.DECR_SEMAPHORE = 1; dcp1.ctrl0.B.INTERRUPT = 1; dcp1.ctrl1.U = 0; dcp1.ctrl1.B.CIPHER_MODE = 1; dcp1.src = srcbuffer; dcp1.dst = dstbuffer; dcp1.buf_size = 512; dcp1.payload = payload; // // // // // // // // // // // // // // single packet in chain clear ctrl0 field key is located in payload encryption operation init CBC for this block (from payload) enable cipher decrement semaphore interrupt clear ctrl1 select CBC mode of operation source buffer destination buffer 512 bytes holds key/CBC init i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1077 Programming DCP Functions dcp1.status = 0; // clear status // Enable channel 0 HW_DCP_CHnCMDPTR_WR(0, dcp1); HW_DCP_CHnSEMA_WR(0, 1); // write packet address to pointer register // increment semaphore by 1 // now wait for interrupt or poll // polling code while ( (HW_DCP_STAT_RD() & 0x01) == 0x00 ); // now check/clear channel status if ( (HW_DCP_CHnSTAT_RD(0) & 0xFF) != 0 ) { // an error occurred HW_DCP_CHnSTAT_CLR(0, 0xff); } // clear interrupt register HW_DCP_STAT_CLR(1); 13.2.7.4 Multi-Buffer Scatter/Gather Cipher and Hash Operation Programming Example For this example, three separate buffers are encrypted and hashed with the results being directed to a unified buffer (gather operation). Three descriptors are used for the operation because there are three separate source buffer pointers. The DCP reads data from the source buffer and computes a hash on the unencrypted data. It then encrypts the data and writes it to the destination buffer. For this example, the key is located in the key RAM, and the algorithm uses the AES CBC mode of operation with a SHA-1 hash. The payload for the first operation contains the CBC initialization value, and the payload for the last packet contains the expected hash value. The middle packet requires no payload. This process is illustrated below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1078 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) Next Ctrl0 Packet 1 Address Tag 0x00 Ctrl1 SHA1 0x13 0x66 Key# CBC AES Src Source Buffer 0 Address Dst Destination Buffer 0 Address Bytes Byte Count Payld Source Buffer 0 Payload Payload 0 Address CBC Init Stat 0x13 = Hash Init | Cipher Init | Encrypt 0x66 = Hash Enable | Cipher Enable | Chain | DecrSema Next Ctrl0 Packet 2 Address Tag 0x00 Ctrl1 SHA1 0x01 0x66 Key# CBC AES Src Source Buffer 1 Address Dst Destination Buffer 1 Address Bytes Source Buffer 1 Dest Buffer 0 Dest Buffer 1 Byte Count Payld Stat Dest Buffer 2 0x01 = Encrypt 0x66 = Hash Enable | Cipher Enable | Chain | DecrSema Next Ctrl0 Tag 0x00 Ctrl1 SHA1 0x61 0x63 Key# CBC AES Source Buffer 2 Src Source Buffer 2 Address Dst Destination Buffer 2 Address Payload Byte Count Hash Check Bytes Payld Payload 2 Address Stat 0x61 = Hash Check | Hash Term | Encrypt 0x63 = Hash Enable | Cipher Enable | DecrSema | Interrupt Figure 13-13. Multi-Buffer Scatter/Gather Cipher and Hash Operation typedef struct _dcp_descriptor { u32 *next; hw_dcp_packet1_t ctrl0; hw_dcp_packet2_t ctrl1; u32 *src, *dst, buf_size, *payload, stat; } DCP_DESCRIPTOR; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1079 Programming DCP Functions DCP_DESCRIPTOR dcp1, dcp2, dcp3; u32 *srcbuffer0, *srcbuffer2, *srcbuffer3; u32 *dstbuffer; u32 payload0[4], payload2[5]; // set up CBC init in the payload payload0[0]=0x01234567; // key payload0[1]=0x89ABCDEF; payload0[2]=0xfedcba98; payload0[3]=0x76543210; payload2[0]=0x00112233; payload2[1]=0x44556677; payload2[2]=0x8899aabb; payload2[3]=0xccddeeff; payload2[3]=0xaabbccdd; // CBC initialization // set up control packet dcp1.next = dcp2; // point to packet 2 dcp1.ctrl0.U = 0; // clear ctrl0 field dcp1.ctrl0.B.CIPHER_ENCRYPT = 1; // encryption operation dcp1.ctrl0.B.CIPHER_INIT = 1; // init CBC for this block (from payload) dcp1.ctrl0.B.HASH_INIT = 1; // init hash this block dcp1.ctrl0.B.ENABLE_CIPHER = 1; // enable cipher dcp1.ctrl0.B.ENABLE_HASH = 1; // enable cipher dcp1.ctrl0.B.DECR_SEMAPHORE = 1; // decrement semaphore dcp1.ctrl0.B.CHAIN = 1; // chain to next packet dcp1.ctrl1.U = 0; // clear ctrl1 dcp1.ctrl1.B.CIPHER_MODE = BV_DCP_PACKET2_CIPHER_MODE_CBC; //select CBC mode of operation dcp1.ctrl1.B.HASH_SELECT = BV_DCP_PACKET2_HASH_SELECT_SHA1; // select SHA1 hash dcp1.ctrl1.B.KEY_SELECT = 2; // select key #2 dcp1.src = srcbuffer0; // source buffer dcp1.dst = dstbuffer; // destination buffer dcp1.buf_size = 512; // 512 bytes dcp1.payload = payload0; // holds key/CBC init dcp1.status = 0; // clear status // set up control packet dcp2.next = dcp3; // point to packet 2 dcp2.ctrl0.U = 0; // clear ctrl0 field dcp2.ctrl0.B.CIPHER_ENCRYPT = 1; // encryption operation dcp2.ctrl0.B.ENABLE_CIPHER = 1; // enable cipher dcp2.ctrl0.B.ENABLE_HASH = 1; // enable cipher dcp2.ctrl0.B.DECR_SEMAPHORE = 1; // decrement semaphore dcp2.ctrl0.B.CHAIN = 1; // chain to next packet dcp2.ctrl1.U = 0; // clear ctrl1 dcp2.ctrl1.B.CIPHER_MODE = BV_DCP_PACKET2_CIPHER_MODE_CBC; //select CBC mode of operation dcp2.ctrl1.B.HASH_SELECT = BV_DCP_PACKET2_HASH_SELECT_SHA1; // select SHA1 hash dcp2.ctrl1.B.KEY_SELECT = 2; // select key #2 dcp2.src = srcbuffer1; // source buffer dcp2.dst = dstbuffer+512; // destination buffer dcp2.buf_size = 512; // 512 bytes dcp2.payload = NULL; // no payload required dcp2.status = 0; // clear status // set up control packet dcp3.next = dcp3; // point to packet 2 dcp3.ctrl0.U = 0; // clear ctrl0 field dcp3.ctrl0.B.HASH_TERM = 1; // terminate hash block dcp3.ctrl0.B.HASH_CHECK = 1; // check hash against payload value dcp3.ctrl0.B.CIPHER_ENCRYPT = 1; // encryption operation dcp3.ctrl0.B.ENABLE_CIPHER = 1; // enable cipher dcp3.ctrl0.B.ENABLE_HASH = 1; // enable cipher dcp3.ctrl0.B.DECR_SEMAPHORE = 1; // decrement semaphore dcp3.ctrl0.B.INTERRUPT = 1; // interrupt on completion dcp3.ctrl1.U = 0; // clear ctrl1 dcp3.ctrl1.B.CIPHER_MODE = BV_DCP_PACKET2_CIPHER_MODE_CBC; //select CBC mode of operation dcp3.ctrl1.B.HASH_SELECT = BV_DCP_PACKET2_HASH_SELECT_SHA1; // select SHA1 hash dcp3.ctrl1.B.KEY_SELECT = 2; // select key #2 dcp3.src = srcbuffer1; // source buffer i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1080 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) dcp3.dst = dstbuffer+1024; dcp3.buf_size = 512; dcp3.payload = payload2; dcp3.status = 0; // // // // destination buffer 512 bytes payload is hash check value clear status // Enable channel 0 HW_DCP_CHnCMDPTR_WR(0, dcp1); HW_DCP_CHnSEMA_WR(0, 3); // write packet address to pointer register // increment semaphore by 3 (for 3 packets) // now wait for interrupt or poll // polling code while ( (HW_DCP_STAT_RD() & 0x01) == 0x00 ); // now check/clear channel status if ( (HW_DCP_CHnSTAT_RD(0) & 0xFF) != 0 ) { // an error occurred HW_DCP_CHnSTAT_CLR(0, 0xff); } // clear interrupt register HW_DCP_STAT_CLR(1); 13.3 Programmable Registers DCP Hardware Register Format Summary HW_DCP memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8002_8000 DCP Control Register 0 (HW_DCP_CTRL) 32 R/W F080_0000h 13.3.1/1083 8002_8010 DCP Status Register (HW_DCP_STAT) 32 R/W 1000_0000h 13.3.2/1086 8002_8020 DCP Channel Control Register (HW_DCP_CHANNELCTRL) 32 R/W 0000_0000h 13.3.3/1088 8002_8030 DCP Capability 0 Register (HW_DCP_CAPABILITY0) 32 R/W 0000_0404h 13.3.4/1090 8002_8040 DCP Capability 1 Register (HW_DCP_CAPABILITY1) 32 R/W 0007_0001h 13.3.5/1091 8002_8050 DCP Context Buffer Pointer (HW_DCP_CONTEXT) 32 R/W 0000_0000h 13.3.6/1092 8002_8060 DCP Key Index (HW_DCP_KEY) 32 R/W 0000_0000h 13.3.7/1092 8002_8070 DCP Key Data (HW_DCP_KEYDATA) 32 R/W 0000_0000h 13.3.8/1093 8002_8080 DCP Work Packet 0 Status Register (HW_DCP_PACKET0) 32 R/W 0000_0000h 13.3.9/1094 8002_8090 DCP Work Packet 1 Status Register (HW_DCP_PACKET1) 32 R/W 0000_0000h 13.3.10/ 1094 8002_80A0 DCP Work Packet 2 Status Register (HW_DCP_PACKET2) 32 R/W 0000_0000h 13.3.11/ 1098 8002_80B0 DCP Work Packet 3 Status Register (HW_DCP_PACKET3) 32 R/W 0000_0000h 13.3.12/ 1099 8002_80C0 DCP Work Packet 4 Status Register (HW_DCP_PACKET4) 32 R/W 0000_0000h 13.3.13/ 1099 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1081 Programmable Registers HW_DCP memory map (continued) Absolute address (hex) Register name 8002_80D0 DCP Work Packet 5 Status Register (HW_DCP_PACKET5) 32 8002_80E0 DCP Work Packet 6 Status Register (HW_DCP_PACKET6) 8002_8100 Width Access (in bits) Reset value Section/ page R/W 0000_0000h 13.3.14/ 1100 32 R/W 0000_0000h 13.3.15/ 1100 DCP Channel 0 Command Pointer Address Register (HW_DCP_CH0CMDPTR) 32 R/W 0000_0000h 13.3.16/ 1101 8002_8110 DCP Channel 0 Semaphore Register (HW_DCP_CH0SEMA) 32 R/W 0000_0000h 13.3.17/ 1102 8002_8120 DCP Channel 0 Status Register (HW_DCP_CH0STAT) 32 R/W 0000_0000h 13.3.18/ 1103 8002_8130 DCP Channel 0 Options Register (HW_DCP_CH0OPTS) 32 R/W 0000_0000h 13.3.19/ 1105 8002_8140 DCP Channel 1 Command Pointer Address Register (HW_DCP_CH1CMDPTR) 32 R/W 0000_0000h 13.3.20/ 1106 8002_8150 DCP Channel 1 Semaphore Register (HW_DCP_CH1SEMA) 32 R/W 0000_0000h 13.3.21/ 1107 8002_8160 DCP Channel 1 Status Register (HW_DCP_CH1STAT) 32 R/W 0000_0000h 13.3.22/ 1108 8002_8170 DCP Channel 1 Options Register (HW_DCP_CH1OPTS) 32 R/W 0000_0000h 13.3.23/ 1110 8002_8180 DCP Channel 2 Command Pointer Address Register (HW_DCP_CH2CMDPTR) 32 R/W 0000_0000h 13.3.24/ 1111 8002_8190 DCP Channel 2 Semaphore Register (HW_DCP_CH2SEMA) 32 R/W 0000_0000h 13.3.25/ 1112 8002_81A0 DCP Channel 2 Status Register (HW_DCP_CH2STAT) 32 R/W 0000_0000h 13.3.26/ 1113 8002_81B0 DCP Channel 2 Options Register (HW_DCP_CH2OPTS) 32 R/W 0000_0000h 13.3.27/ 1115 8002_81C0 DCP Channel 3 Command Pointer Address Register (HW_DCP_CH3CMDPTR) 32 R/W 0000_0000h 13.3.28/ 1116 8002_81D0 DCP Channel 3 Semaphore Register (HW_DCP_CH3SEMA) 32 R/W 0000_0000h 13.3.29/ 1117 8002_81E0 DCP Channel 3 Status Register (HW_DCP_CH3STAT) 32 R/W 0000_0000h 13.3.30/ 1118 8002_81F0 DCP Channel 3 Options Register (HW_DCP_CH3OPTS) 32 R/W 0000_0000h 13.3.31/ 1120 8002_8400 DCP Debug Select Register (HW_DCP_DBGSELECT) 32 R/W 0000_0000h 13.3.32/ 1121 8002_8410 DCP Debug Data Register (HW_DCP_DBGDATA) 32 R/W 0000_0000h 13.3.33/ 1121 8002_8420 DCP Page Table Register (HW_DCP_PAGETABLE) 32 R/W 0000_0000h 13.3.34/ 1122 8002_8430 DCP Version Register (HW_DCP_VERSION) 32 R/W 0201_0000h 13.3.35/ 1122 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1082 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 13.3.1 DCP Control Register 0 (HW_DCP_CTRL) The CTRL register contains controls for the DCP module. HW_DCP_CTRL: 0x000 HW_DCP_CTRL_SET: 0x004 HW_DCP_CTRL_CLR: 0x008 HW_DCP_CTRL_TOG: 0x00C The Control register contains the primary controls for the DCP block. The present bits indicate which of the sub-features of the block are present in the hardware. The context control bits control how the DCP utilizes it's context buffer and the gather residual writes bit controls how the master handles writing misaligned data to the bus. Each channel and the color-space converter contains an independent interrupt enable. EXAMPLE HW_DCP_CTRL_SET(BM_DCP_CTRL_SFTRST); HW_DCP_CTRL_CLR(BM_DCP_CTRL_SFTRST | BM_DCP_CTRL_CLKGATE); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1083 Programmable Registers CLKGATE 1 1 28 1 1 27 26 25 24 RSVD1 23 22 21 ENABLE_CONTEXT_SWITCHING SFTRST R 29 ENABLE_CONTEXT_CACHING 30 GATHER_RESIDUAL_WRITES 31 PRESENT_SHA Bit PRESENT_CRYPTO Address: 8002_8000h base + 0h offset = 8002_8000h 1 0 0 20 19 18 17 16 0 0 RSVD0 W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1084 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 14 13 12 11 10 9 RSVD0 R 8 7 6 RSVD_CSC_INTERRUPT_ENABLE 15 Bit 5 4 3 2 1 0 0 0 CHANNEL_INTERRUPT_ENABLE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CTRL field descriptions Field Description 31 SFTRST Set this bit to zero to enable normal DCP operation. Set this bit to one (default) to disable clocking with the DCP and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the DCP block to its default state. 30 CLKGATE 29 PRESENT_ CRYPTO This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. Indicates whether the crypto (Cipher/Hash) functions are present. 0x1 0x0 Present -- Absent -- 28 Indicates whether the SHA1/SHA2 functions are present. PRESENT_SHA Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1085 Programmable Registers HW_DCP_CTRL field descriptions (continued) Field Description Present -- Absent -- 0x1 0x0 27-24 RSVD1 Reserved, always set to zero. 23 GATHER_ RESIDUAL_ WRITES Software should set this bit to enable ragged writes to unaligned buffers to be gathered between multiple write operations. This improves performance by removing several byte operations between write bursts. Trailing byte writes are held in a residual write data buffer and combined with a subsequent write to the buffer to form a word write. 22 ENABLE_ CONTEXT_ CACHING Software should set this bit to enable caching of contexts between operations. If only a single channel is used for encryption/hashing, enabling caching causes the context to not be reloaded if the channel was the last to be used. 21 ENABLE_ CONTEXT_ SWITCHING Enable automatic context switching for the channels. Software should set this bit if more than one channel is doing hashing or cipher operations that require context to be saved (for instance, when CBC mode is enabled). By disabling context switching, software can save the 208 bytes used for the context buffer. 20-9 RSVD0 Reserved, always set to zero. 8 RSVD_CSC_ INTERRUPT_ ENABLE Reserved, always set to zero. CHANNEL_ INTERRUPT_ ENABLE Per-channel interrupt enable bit. When set, the channel's interrupt will get routed to the interrupt controller. Channel 0 is routed to the dcp_vmi_irq signal and the other channels are combined (along with the CRC interrupt) into the dcp_irq signal. 0x01 0x02 0x04 0x08 CH0 -- CH1 -- CH2 -- CH3 -- 13.3.2 DCP Status Register (HW_DCP_STAT) The DCP Interrupt Status register provides channel interrupt status information. HW_DCP_STAT: 0x010 HW_DCP_STAT_SET: 0x014 HW_DCP_STAT_CLR: 0x018 HW_DCP_STAT_TOG: 0x01C This register provides status feedback indicating the channel currently performing an operation and which channels have pending operations. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1086 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) Address: 8002_8000h base + 10h offset = 8002_8010h 31 30 29 28 RSVD2 R 27 OTP_KEY_READY Bit 26 25 24 23 22 21 CUR_CHANNEL 20 19 18 17 16 READY_CHANNELS W Bit 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSVD_IRQ Reset RSVD1 R RSVD0 IRQ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_STAT field descriptions Field 31-29 RSVD2 Description Reserved, always set to zero. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1087 Programmable Registers HW_DCP_STAT field descriptions (continued) Field 28 OTP_KEY_ READY Description When set, indicates that the OTP key has been shifted from the fuse block and is ready for use. 27-24 Current (active) channel (encoded). CUR_CHANNEL 0x0 None -- 0x1 CH0 -- 0x2 CH1 -- 0x3 CH2 -- 0x4 CH3 -- 23-16 READY_ CHANNELS Indicates which channels are ready to proceed with a transfer (active channel also included). Each bit is a one-hot indicating the request status for the associated channel. 0x01 0x02 0x04 0x08 CH0 -- CH1 -- CH2 -- CH3 -- 15-9 RSVD1 Reserved, always set to zero. 8 RSVD_IRQ Reserved, always set to zero. 7-4 RSVD0 Reserved, always set to zero. IRQ Indicates which channels have pending interrupt requests. Channel 0's interrupt is routed through the dcp_vmi_irq and the other interrupt bits are routed through the dcp_irq. 13.3.3 DCP Channel Control Register (HW_DCP_CHANNELCTRL) The DCP Channel Control register provides controls for channel arbitration and channel enables. HW_DCP_CHANNELCTRL: 0x020 HW_DCP_CHANNELCTRL_SET: 0x024 HW_DCP_CHANNELCTRL_CLR: 0x028 HW_DCP_CHANNELCTRL_TOG: 0x02C This register provides status feedback indicating the channel currently performing an operation and which channels have pending operations. EXAMPLE BW_DCP_CHANNELCTRL_ENABLE_CHANNEL(BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0); enable channel 0 // i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1088 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) Address: 8002_8000h base + 20h offset = 8002_8020h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RSVD R W Reset Bit 16 CH0_IRQ_MERGED Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 R HIGH_PRIORITY_CHANNEL ENABLE_CHANNEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CHANNELCTRL field descriptions Field 31-17 RSVD Description Reserved, always set to zero. 16 CH0_IRQ_ MERGED Indicates that the interrupt for channel 0 should be merged with the other interrupts on the shared dcp_irq interrupt. When set to 0, channel 0's interrupt will be routed to the separate dcp_vmi_irq. When set to 1, the interrupt will be routed to the shared DCP interrupt. 15-8 HIGH_ PRIORITY_ CHANNEL Setting a bit in this field causes the corresponding channel to have high-priority arbitration. High priority channels will be arbitrated round-robin and will take precedence over other channels that are not marked as high priority. ENABLE_ CHANNEL Setting a bit in this field will enabled the DMA channel associated with it. This field is a direct input to the DMA channel arbiter. When not enabled, the channel is denied access to the central DMA resources. 0x01 0x02 0x04 0x08 0x01 0x02 CH0 -- CH1 -- CH2 -- CH3 -- CH0 -- CH1 -- Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1089 Programmable Registers HW_DCP_CHANNELCTRL field descriptions (continued) Field Description CH2 -- CH3 -- 0x04 0x08 13.3.4 DCP Capability 0 Register (HW_DCP_CAPABILITY0) This register contains additional information about the DCP module implementation parameters. This register provides capability information for the DCP block. It indicates the number of channels implemented as well as the number of key storage locations available for software use. Address: 8002_8000h base + 30h offset = 8002_8030h 29 28 27 26 25 24 23 22 21 20 19 18 17 16 W DISABLE_UNIQUE_KEY 30 ENABLE_TZONE 31 DISABLE_DECRYPT Bit Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 R Bit RSVD RSVD R NUM_CHANNELS NUM_KEYS W Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1090 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) HW_DCP_CAPABILITY0 field descriptions Field Description 31 DISABLE_ DECRYPT Write to a 1 to disable decryption. This bit can only be written by secure software and the value can only be cleared by a reset. 30 Write to a 1 to enable trustzone support. Channel operations initiated by secure operations will be ENABLE_TZONE protected from non-secure operations and the secure channel interrupts will be routed to the secure DCP interrupt. This bit can only be written by secure software and the value can only be cleared by a reset. 29 DISABLE_ UNIQUE_KEY 28-12 RSVD Write to a 1 to disable the per-device unique key. The device-specific hardware key may be selected by using a value of 0xFE in the key select field. Reserved, always set to zero. 11-8 NUM_ CHANNELS Encoded value indicating the number of channels implemented in the design. NUM_KEYS Encoded value indicating the number of key storage locations implemented in the design. 13.3.5 DCP Capability 1 Register (HW_DCP_CAPABILITY1) This register contains information about the algorithms available on the implementation. This register provides capability information for the DCP block. It contains two fields indicating which encryption and hashing algorithms are present in the design. Each bit set indicates that support for the associated function is present. Address: 8002_8000h base + 40h offset = 8002_8040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 HASH_ALGORITHMS R 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 CIPHER_ALGORITHMS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CAPABILITY1 field descriptions Field Description 31-16 HASH_ ALGORITHMS One-hot field indicating which hashing features are implemented in HW. CIPHER_ ALGORITHMS One-hot field indicating which cipher algorithms are available. 0x0001 0x0002 0x0004 0x0001 SHA1 -- CRC32 -- SHA256 -- AES128 -- i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1091 Programmable Registers 13.3.6 DCP Context Buffer Pointer (HW_DCP_CONTEXT) This register contains a pointer to the memory region to be used for DCP context swap operations. This register contains a pointer to the start of the context pointer memory in on-chip SRAM or off-chip SDRAM. This buffer will be used to store state information when the DCP module changes from one channel to another. Address: 8002_8000h base + 50h offset = 8002_8050h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CONTEXT field descriptions Field ADDR Description Context pointer address. Address should be located in system RAM and should be word-aligned for optimal performance. 13.3.7 DCP Key Index (HW_DCP_KEY) This register contains a pointer to the key location to be written. The DCP module maintains a set of write-only keys that may be used by software. To write a key, software must first write the desired key index/subword to this register and then write the key values to the key registers (below). After each write to the key data register, the SUBWORD field will increment to allow software to write the subsequent key to be written without having to rewrite the key index. EXAMPLE // write key 0 to 0x00112233_44556677_8899aabb_ccddeeff HW_DCP_KEY_WR(BF_DCP_KEY_INDEX(0) | BF_DCP_KEY_SUBWORD(0)); subword 0 HW_DCP_KEYDATA_WR(0xccddeeff); // write key values (subword HW_DCP_KEYDATA_WR(0x8899aabb); // write key values (subword HW_DCP_KEYDATA_WR(0x44556677); // write key values (subword HW_DCP_KEYDATA_WR(0x00112233); // write key values (subword // set key index to key 0, 0) 1) 2) 3) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1092 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) Address: 8002_8000h base + 60h offset = 8002_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD_ INDEX RSVD R INDEX RSVD_ SUBWORD SUBWORD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_KEY field descriptions Field Description 31-8 RSVD Reserved, always set to zero. 7-6 RSVD_INDEX Reserved, always set to zero. 5-4 INDEX Key index pointer. Valid indices are 0-[number_keys]. 3-2 RSVD_ SUBWORD Reserved, always set to zero. SUBWORD Key subword pointer. Valid indices are 0-3. After each write to the key data register, this field will increment. 13.3.8 DCP Key Data (HW_DCP_KEYDATA) This register provides write access to the key/key subword specified by the Key Index Register. Writing this location updates the selected subword for the key located at the index specified by the Key Index Register. A write also triggers the SUBWORD field of the KEY register to increment to the next higher word in the key. EXAMPLE // write key 0 to 0x00112233_44556677_8899aabb_ccddeeff HW_DCP_KEY_WR(BF_DCP_KEY_INDEX(0) | BF_DCP_KEY_SUBWORD(0)); subword 0 HW_DCP_KEYDATA_WR(0xccddeeff); // write key values (subword HW_DCP_KEYDATA_WR(0x8899aabb); // write key values (subword HW_DCP_KEYDATA_WR(0x44556677); // write key values (subword HW_DCP_KEYDATA_WR(0x00112233); // write key values (subword // set key index to key 0, 0) 1) 2) 3) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1093 Programmable Registers Address: 8002_8000h base + 70h offset = 8002_8070h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_KEYDATA field descriptions Field Description DATA Word 0 data for key. This is the least-significant word. 13.3.9 DCP Work Packet 0 Status Register (HW_DCP_PACKET0) This register displays the values for the current work packet offset 0x00 (Next Command) field. The Work Packet Status Registers show the contents of the currently executing packet. When the channels are inactive, the packet status register return 0. The register bits are fully documented here to document the packet structure in memory. Address: 8002_8000h base + 80h offset = 8002_8080h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_PACKET0 field descriptions Field ADDR Description Next Pointer Register, 13.3.10 DCP Work Packet 1 Status Register (HW_DCP_PACKET1) This register displays the values for the current work packet offset 0x04 (control) field. This register shows the contents of the Control0 register from the packet being processed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1094 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 25 24 0 0 0 0 TAG R 23 22 21 20 19 18 17 16 CONSTANT_FILL 26 TEST_SEMA_IRQ 27 KEY_BYTESWAP 28 KEY_WORDSWAP 29 INPUT_BYTESWAP 30 INPUT_WORDSWAP 31 OUTPUT_BYTESWAP Bit OUTPUT_WORDSWAP Address: 8002_8000h base + 90h offset = 8002_8090h 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1095 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HASH_TERM HASH_INIT PAYLOAD_KEY OTP_KEY CIPHER_INIT CIPHER_ENCRYPT ENABLE_BLIT ENABLE_HASH ENABLE_CIPHER ENABLE_MEMCOPY CHAIN_CONTIGUOUS CHAIN DECR_SEMAPHORE INTERRUPT R 15 CHECK_HASH Bit HASH_OUTPUT Programmable Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset HW_DCP_PACKET1 field descriptions Field 31-24 TAG Description Packet Tag 23 OUTPUT_ WORDSWAP Reflects whether the DCP engine will wordswap output data (big-endian data). 22 OUTPUT_ BYTESWAP Reflects whether the DCP engine will byteswap output data (big-endian data). 21 INPUT_ WORDSWAP Reflects whether the DCP engine will wordswap input data (big-endian data). 20 INPUT_ BYTESWAP Reflects whether the DCP engine will byteswap input data (big-endian data). 19 KEY_ WORDSWAP Reflects whether the DCP engine will swap key words (big-endian key). 18 KEY_ BYTESWAP Reflects whether the DCP engine will swap key bytes (big-endian key). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1096 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) HW_DCP_PACKET1 field descriptions (continued) Field Description 17 TEST_SEMA_ IRQ This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY! 16 CONSTANT_ FILL When this bit is set (MEMCOPY and BLIT modes only), the DCP will simply fill the destination buffer with the value found in the Source Address field. 15 When hashing is enabled, this bit controls whether the input or output data is hashed. HASH_OUTPUT 0x00 INPUT -- 0x01 OUTPUT -- 14 CHECK_HASH Reflects whether the calculated hash value should be compared against the hash provided in the payload. 13 HASH_TERM Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding should be applied by hardware. 12 HASH_INIT Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers should be initialized before the operation. 11 When set, indicates the payload contains the key. This bit takes precedence over the OTP_KEY control PAYLOAD_KEY 10 OTP_KEY 9 CIPHER_INIT Reflects whether a hardware-based key should be used. The KEY_SELECT field from the Control1 field is used to select from multiple hardware keys. The PAYLOAD_KEY bit takes precedence over the OTP_KEY bit. Reflects whether the cipher block should load the initialization vector from the payload for this operation. 8 CIPHER_ ENCRYPT When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption. 7 ENABLE_BLIT Reflects whether the DCP should perform a blit operation. Source data is always continuous and the destination buffer is written in run/stride format. When set, the 0x01 0x00 ENCRYPT -- DECRYPT -- BUFFER_SIZE field is treated as two 16-bit values for the X-Y extents of the blit operation. 6 Reflects whether the selected hashing function should be enabled for this operation. ENABLE_HASH 5 ENABLE_ CIPHER Reflects whether the selected cipher function should be enabled for this operation. 4 ENABLE_ MEMCOPY Reflects whether the selected hashing function should be enabled for this operation. 3 CHAIN_ CONTIGUOUS Reflects whether the next packet's address is located following this packet's payload. 2 CHAIN 1 DECR_ SEMAPHORE Reflects whether the next command pointer register should be loaded into the channel's current descriptor pointer. Reflects whether the channel's semaphore should be decremented at the end of the current operation. When the semaphore reaches a value of zero, no more operations will be issued from the channel. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1097 Programmable Registers HW_DCP_PACKET1 field descriptions (continued) Field Description 0 INTERRUPT Reflects whether the channel should issue an interrupt upon completion of the packet. 13.3.11 DCP Work Packet 2 Status Register (HW_DCP_PACKET2) This register displays the values for the current work packet offset 0x08 (Control1) field. This register shows the contents of the Control0 register from the packet being processed. Address: 8002_8000h base + A0h offset = 8002_80A0h Bit 31 30 29 28 27 26 25 24 23 22 CIPHER_CFG R 21 20 19 RSVD 18 17 16 HASH_SELECT W Reset Bit 0 0 0 15 14 13 0 0 0 0 0 0 12 11 10 9 8 7 KEY_SELECT R 0 0 0 0 6 5 4 3 CIPHER_MODE 0 0 0 2 1 0 CIPHER_SELECT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_PACKET2 field descriptions Field 31-24 CIPHER_CFG 23-20 RSVD Description Cipher configuration bits. Optional configuration bits required for ciphers Reserved, always set to zero. 19-16 Hash Selection Field HASH_SELECT 0x00 SHA1 -- 0x01 CRC32 -- 0x02 SHA256 -- 15-8 KEY_SELECT Key Selection Field. The value here reflects the key index for the cipher operation. Values 0-3 refer to the software keys that can be written to the key RAM. The OTP key or the unique device-specific key may also be selected with a value of 0xFF (OTP key) or 0xFE (unique key). 0x00 0x01 0x02 0x03 0xFE 0xFF KEY0 -- KEY1 -- KEY2 -- KEY3 -- UNIQUE_KEY -- OTP_KEY -- 7-4 Cipher Mode Selection Field. Reflects the mode of operation for cipher operations. CIPHER_MODE Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1098 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) HW_DCP_PACKET2 field descriptions (continued) Field Description 0x00 0x01 CIPHER_ SELECT ECB -- CBC -- Cipher Selection Field 0x00 AES128 -- 13.3.12 DCP Work Packet 3 Status Register (HW_DCP_PACKET3) This register displays the values for the current work packet offset 0x0C (Source Address) field. This register shows the contents of the Source Address register from the packet being processed. When the CONSTANT_FILL bit in the Control 0 field is set, this field contains the data written to the destination buffer. Address: 8002_8000h base + B0h offset = 8002_80B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_PACKET3 field descriptions Field Description ADDR Source Buffer Address Pointer. This value is the working value and will update as the operation proceeds. 13.3.13 DCP Work Packet 4 Status Register (HW_DCP_PACKET4) This register displays the values for the current work packet offset 0x10 (Destination Address) field. This register shows the contents of the Destination Address register from the packet being processed. Address: 8002_8000h base + C0h offset = 8002_80C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1099 Programmable Registers HW_DCP_PACKET4 field descriptions Field Description ADDR Destination Buffer Address Pointer. This value is the working value and will update as the operation proceeds. 13.3.14 DCP Work Packet 5 Status Register (HW_DCP_PACKET5) This register displays the values for the current work packet offset 0x14 (Buffer Size) field. This register shows the contents of the bytecount register from the packet being processed. The field can be considered either a byte count or a buffer size. The logic treats this as a decrmenting count of bytes from the buffer size programmed into the field. As the transaction proceeds, the logic will decrement the bytecount as data is written to the destination buffer. For blit operations, the top 16-bits of this field represents the number of lines (y size) in the blit and the lower 16-bits represent the number of bytes in a line (x size). Address: 8002_8000h base + D0h offset = 8002_80D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_PACKET5 field descriptions Field COUNT Description Byte Count register. This value is the working value and will update as the operation proceeds. 13.3.15 DCP Work Packet 6 Status Register (HW_DCP_PACKET6) This register displays the values for the current work packet offset 0x1C (Payload Pointer) field. This register shows the contents of the payload pointer fieldr from the packet being processed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1100 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) Address: 8002_8000h base + E0h offset = 8002_80E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_PACKET6 field descriptions Field Description ADDR This regiser reflects the payload pointer for the current control packet. 13.3.16 DCP Channel 0 Command Pointer Address Register (HW_DCP_CH0CMDPTR) The DCP channel 0 current command address register points to the multiword descriptor that is to be executed (or currently being executed). The channel may be activated by writing the command pointer address to a valid descriptor in memory and then updating the semaphore to a non-zero value. After the engine completes processing of a descriptor, the next_ptr field from the descriptor is moved into this register to enable processing of the next descriptor. All channels with a non-zero semaphore value will arbitrate for access to the engine for the subsequent operation. DCP Channel 0 is controlled by a variable sized command structure. This register points to the command structure to be executed. EXAMPLE HW_DCP_CHnCMDPTR_WR(0, v); // Write channel 0 command pointer pCurptr = (hw_DCP_chncmdptr_t *) HW_DCP_CHnCMDPTR_RD(0); // Read current command pointer Address: 8002_8000h base + 100h offset = 8002_8100h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CH0CMDPTR field descriptions Field ADDR Description Pointer to descriptor structure to be processed for channel 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1101 Programmable Registers 13.3.17 DCP Channel 0 Semaphore Register (HW_DCP_CH0SEMA) The DCP Channel 0 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. After a command chain has been generated in memory, software should write the address of the first command descriptor to the CMDPTR register and then write a non-zero value to the semaphore register to indicate that the channel is active. Each command packet has a chaining bit which indicates that another descriptor should be loaded into the channel upon completion of the current descriptor. If the chaining bit is not set, the next address will not be loaded into the CMDPTR register. Each packet also contains a decrement semaphore bit, which indicates that the counting semaphore should be decremented after the operation. A channel is considered active when the semaphore is a non-zero value. When programming a series operations, software must properly program the semaphore values in conjunction with the decrement_semaphore bits in the control packets to ensure that the proper number of descriptors are activated. A semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. The logic will also clear the semaphore if an error has occurred. Each DCP channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DCP chain processing. After processing each control packet, the DCP decrements the semaphore if it is non-zero. The channel will continue processing packets as long as the semaphore contains a non-zero value and the CHAIN or CHAIN_CONTIGOUS control bits in the Control0 field are set. Address: 8002_8000h base + 110h offset = 8002_8110h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 VALUE 12 11 10 9 8 7 6 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 INCREMENT W Reset 5 0 0 0 0 0 0 0 0 0 HW_DCP_CH0SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 VALUE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP channel decrements the count on the same clock, then the count is incremented by a net one. The semaphore may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1102 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 13.3.18 DCP Channel 0 Status Register (HW_DCP_CH0STAT) The DCP Channel 0 Interrupt Status register contains the interrupt status bit and the tag of the last completed operation from the command chain. If an error occurs during processing, the ERROR bit is set and an interrupt is generated. HW_DCP_CH0STAT: 0x120 HW_DCP_CH0STAT_SET: 0x124 HW_DCP_CH0STAT_CLR: 0x128 HW_DCP_CH0STAT_TOG: 0x12C The interrupt status register is updated at the end of each work packet. If the interrupt bit is set in the command packet's command field, an interrupt will be generated once the packet has completed. In addition, the tag value from the command is stored in the TAG field so that software can identify which command structure was the last to complete. If an error occurs, the ERROR bit is set and processing of the command chain is halted. Address: 8002_8000h base + 120h offset = 8002_8120h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 TAG R ERROR_CODE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1103 9 8 7 0 0 0 0 RSVD0 R 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD_COMPLETE 10 HASH_MISMATCH 11 ERROR_SETUP 12 ERROR_PACKET 13 ERROR_SRC 14 ERROR_DST 15 Bit ERROR_PAGEFAULT Programmable Registers W Reset 0 0 0 0 0 0 HW_DCP_CH0STAT field descriptions Field 31-24 TAG Description Indicates the tag from the last completed packet in the command structure 23-16 Indicates additional error codes for some error conditions. ERROR_CODE 0x01 NEXT_CHAIN_IS_0 -- Error signalled because the next pointer is 0x00000000 0x02 NO_CHAIN -- Error signalled because the semaphore is nonzero and neither chain bit is set 0x03 CONTEXT_ERROR -- Error signalled because an error was reported reading/writing the context buffer 0x04 PAYLOAD_ERROR -- Error signalled because an error was reported reading/writing the payload 0x05 INVALID_MODE -- Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 15-7 RSVD0 Reserved, always set to zero. 6 ERROR_ PAGEFAULT This bit indicates a page fault occurred while converting a virtual address to a physical address.. When an error is detected, the channel's processing will stop until the error handled by software. 5 ERROR_DST This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the channel's processing will stop until the error handled by software. 4 ERROR_SRC This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the channel's processing will stop until the error handled by software. 3 ERROR_ PACKET This bit indicates that a a bus error occurred when reading the packet or payload or when writing status back to the packet payload. When an error is detected, the channel's processing will stop until the error is handled by software. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1104 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) HW_DCP_CH0STAT field descriptions (continued) Field Description 2 This bit indicates that the hardware has detected an invalid programming configuration such as a buffer ERROR_SETUP length that is not a multiple of the natural data size for the operation. When an error is detected, the channel's processing will stop until the error is handled by software. 1 HASH_ MISMATCH The bit indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled by software. 0 RSVD_ COMPLETE This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing of the packet has completed. This was done so that software can verify that each packet completed properly in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion bit for the channel is effectively the channel interrupt status bit. 13.3.19 DCP Channel 0 Options Register (HW_DCP_CH0OPTS) The DCP Channel 0 Options Status register contains optional control information that may be used to further tune the behavior of the channel. HW_DCP_CH0OPTS: 0x130 HW_DCP_CH0OPTS_SET: 0x134 HW_DCP_CH0OPTS_CLR: 0x138 HW_DCP_CH0OPTS_TOG: 0x13C The options register can be used to control optional features of the channels. Address: 8002_8000h base + 130h offset = 8002_8130h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSVD R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 RECOVERY_TIMER W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CH0OPTS field descriptions Field 31-16 RSVD RECOVERY_ TIMER Description Reserved, always set to zero. This field indicates the recovery time for the channel. After each operation, the recover timer for the channel is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate another operation for the next packet in the chain until the recovery time has been satisfied. The timebase for the recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1105 Programmable Registers 13.3.20 DCP Channel 1 Command Pointer Address Register (HW_DCP_CH1CMDPTR) The DCP channel 1 current command address register points to the multiword descriptor that is to be executed (or currently being executed). The channel may be activated by writing the command pointer address to a valid descriptor in memory and then updating the semaphore to a non-zero value. After the engine completes processing of a descriptor, the next_ptr field from the descriptor is moved into this register to enable processing of the next descriptor. All channels with a non-zero semaphore value will arbitrate for access to the engine for the subsequent operation. DCP Channel 1 is controlled by a variable sized command structure. This register points to the command structure to be executed. EXAMPLE HW_DCP_CHn_CMDPTR_WR(1, v); // Write channel 1 command pointer pCurptr = (hw_DCP_chn_cmdptr_t *) HW_DCP_CHn_CMDPTR_RD(1); // Read current command pointer Address: 8002_8000h base + 140h offset = 8002_8140h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CH1CMDPTR field descriptions Field ADDR Description Pointer to descriptor structure to be processed for channel 1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1106 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 13.3.21 DCP Channel 1 Semaphore Register (HW_DCP_CH1SEMA) The DCP Channel 1 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. After a command chain has been generated in memory, software should write the address of the first command descriptor to the CMDPTR register and then write a non-zero value to the semaphore register to indicate that the channel is active. Each command packet has a chaining bit which indicates that another descriptor should be loaded into the channel upon completion of the current descriptor. If the chaining bit is not set, the next address will not be loaded into the CMDPTR register. Each packet also contains a decrement semaphore bit, which indicates that the counting semaphore should be decremented after the operation. A channel is considered active when the semaphore is a non-zero value. When programming a series operations, software must properly program the semaphore values in conjunction with the decrement_semaphore bits in the control packets to ensure that the proper number of descriptors are activated. A semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. The logic will also clear the semaphore if an error has occurred. Each DCP channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DCP chain processing. DCP processing continues until the engine attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DCP channel is stalled until software increments the semaphore count. Address: 8002_8000h base + 150h offset = 8002_8150h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 VALUE 12 11 10 9 8 7 6 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 INCREMENT W Reset 5 0 0 0 0 0 0 0 0 0 HW_DCP_CH1SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 VALUE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP channel decrements the count on the same clock, then the count is incremented by a net one. The semaphore may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1107 Programmable Registers 13.3.22 DCP Channel 1 Status Register (HW_DCP_CH1STAT) The DCP Channel 1 Interrupt Status register contains the interrupt status bit and the tag of the last completed operation from the command chain. If an error occurs during processing, the ERROR bit is set and an interrupt is generated. HW_DCP_CH1STAT: 0x160 HW_DCP_CH1STAT_SET: 0x164 HW_DCP_CH1STAT_CLR: 0x168 HW_DCP_CH1STAT_TOG: 0x16C The interrupt status register is updated at the end of each work packet. If the interrupt bit is set in the command packet's command field, an interrupt will be generated once the packet has completed. In addition, the tag value from the command is stored in the TAG field so that software can identify which command structure was the last to complete. If an error occurs, the ERROR bit is set and processing of the command chain is halted. Address: 8002_8000h base + 160h offset = 8002_8160h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 TAG R ERROR_CODE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1108 Freescale Semiconductor, Inc. 9 8 7 0 0 0 0 RSVD0 R 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD_COMPLETE 10 HASH_MISMATCH 11 ERROR_SETUP 12 ERROR_PACKET 13 ERROR_SRC 14 ERROR_DST 15 Bit ERROR_PAGEFAULT Chapter 13 Data Co-Processor (DCP) W Reset 0 0 0 0 0 0 HW_DCP_CH1STAT field descriptions Field 31-24 TAG Description Indicates the tag from the last completed packet in the command structure 23-16 Indicates additional error codes for some error conditions. ERROR_CODE 0x01 NEXT_CHAIN_IS_0 -- Error signalled because the next pointer is 0x00000000 0x02 NO_CHAIN -- Error signalled because the semaphore is nonzero and neither chain bit is set 0x03 CONTEXT_ERROR -- Error signalled because an error was reported reading/writing the context buffer 0x04 PAYLOAD_ERROR -- Error signalled because an error was reported reading/writing the payload 0x05 INVALID_MODE -- Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 15-7 RSVD0 Reserved, always set to zero. 6 ERROR_ PAGEFAULT This bit indicates a page fault occurred while converting a virtual address to a physical address.. When an error is detected, the channel's processing will stop until the error handled by software. 5 ERROR_DST This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the channel's processing will stop until the error handled by software. 4 ERROR_SRC This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the channel's processing will stop until the error handled by software. 3 ERROR_ PACKET This bit indicates that a bus error occurs when reading the packet or payload or when writing status back to the packet paylaod. When an error is detected, the channel's processing will stop until the error is handled by software. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1109 Programmable Registers HW_DCP_CH1STAT field descriptions (continued) Field Description 2 This bit indicates that the hardware detected an invalid programming configuration such as a buffer length ERROR_SETUP that is not a multiple of the natural data size for the operation. When an error is detected, the channel's processing will stop until the error is handled by software. 1 HASH_ MISMATCH The bit indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled by software. 0 RSVD_ COMPLETE This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing of the packet has completed. This was done so that software can verify that each packet completed properly in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion bit for the channel is effectively the channel interrupt status bit. 13.3.23 DCP Channel 1 Options Register (HW_DCP_CH1OPTS) The DCP Channel 1 Options Status register contains optional control information that may be used to further tune the behavior of the channel. HW_DCP_CH1OPTS: 0x170 HW_DCP_CH1OPTS_SET: 0x174 HW_DCP_CH1OPTS_CLR: 0x178 HW_DCP_CH1OPTS_TOG: 0x17C The options register can be used to control optional features of the channels. Address: 8002_8000h base + 170h offset = 8002_8170h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSVD R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 RECOVERY_TIMER W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CH1OPTS field descriptions Field 31-16 RSVD RECOVERY_ TIMER Description Reserved, always set to zero. This field indicates the recovery time for the channel. After each operation, the recover timer for the channel is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate operation on the next packet in the chain until the recovery time has been satisfied. The timebase for the recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1110 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 13.3.24 DCP Channel 2 Command Pointer Address Register (HW_DCP_CH2CMDPTR) The DCP channel 2 current command address register points to the multiword descriptor that is to be executed (or currently being executed). The channel may be activated by writing the command pointer address to a valid descriptor in memory and then updating the semaphore to a non-zero value. After the engine completes processing of a descriptor, the next_ptr field from the descriptor is moved into this register to enable processing of the next descriptor. All channels with a non-zero semaphore value will arbitrate for access to the engine for the subsequent operation. DCP Channel 2 is controlled by a variable sized command structure. This register points to the command structure to be executed. EXAMPLE HW_DCP_CHn_CMDPTR_WR(2, v); // Write channel 2 command pointer pCurptr = (hw_DCP_chn_cmdptr_t *) HW_DCP_CHn_CMDPTR_RD(2); // Read current command pointer Address: 8002_8000h base + 180h offset = 8002_8180h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CH2CMDPTR field descriptions Field ADDR Description Pointer to descriptor structure to be processed for channel 2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1111 Programmable Registers 13.3.25 DCP Channel 2 Semaphore Register (HW_DCP_CH2SEMA) The DCP Channel 2 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. After a command chain has been generated in memory, software should write the address of the first command descriptor to the CMDPTR register and then write a non-zero value to the semaphore register to indicate that the channel is active. Each command packet has a chaining bit which indicates that another descriptor should be loaded into the channel upon completion of the current descriptor. If the chaining bit is not set, the next address will not be loaded into the CMDPTR register. Each packet also contains a decrement semaphore bit, which indicates that the counting semaphore should be decremented after the operation. A channel is considered active when the semaphore is a non-zero value. When programming a series operations, software must properly program the semaphore values in conjunction with the decrement_semaphore bits in the control packets to ensure that the proper number of descriptors are activated. A semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. The logic will also clear the semaphore if an error has occurred. Each DCP channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DCP chain processing. DCP processing continues until the engine attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DCP channel is stalled until software increments the semaphore count. Address: 8002_8000h base + 190h offset = 8002_8190h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 VALUE 12 11 10 9 8 7 6 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 INCREMENT W Reset 5 0 0 0 0 0 0 0 0 0 HW_DCP_CH2SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 VALUE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP channel decrements the count on the same clock, then the count is incremented by a net one. The semaphore may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1112 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 13.3.26 DCP Channel 2 Status Register (HW_DCP_CH2STAT) The DCP Channel 2 Interrupt Status register contains the interrupt status bit and the tag of the last completed operation from the command chain. If an error occurs during processing, the ERROR bit is set and an interrupt is generated. HW_DCP_CH2STAT: 0x1A0 HW_DCP_CH2STAT_SET: 0x1A4 HW_DCP_CH2STAT_CLR: 0x1A8 HW_DCP_CH2STAT_TOG: 0x1AC The interrupt status register is updated at the end of each work packet. If the interrupt bit is set in the command packet's command field, an interrupt will be generated once the packet has completed. In addition, the tag value from the command is stored in the TAG field so that software can identify which command structure was the last to complete. If an error occurs, the ERROR bit is set and processing of the command chain is halted. Address: 8002_8000h base + 1A0h offset = 8002_81A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 TAG R ERROR_CODE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1113 9 8 7 0 0 0 0 RSVD0 R 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD_COMPLETE 10 HASH_MISMATCH 11 ERROR_SETUP 12 ERROR_PACKET 13 ERROR_SRC 14 ERROR_DST 15 Bit ERROR_PAGEFAULT Programmable Registers W Reset 0 0 0 0 0 0 HW_DCP_CH2STAT field descriptions Field 31-24 TAG Description Indicates the tag from the last completed packet in the command structure 23-16 Indicates additional error codes for some error conditions. ERROR_CODE 0x01 NEXT_CHAIN_IS_0 -- Error signalled because the next pointer is 0x00000000 0x02 NO_CHAIN -- Error signalled because the semaphore is nonzero and neither chain bit is set 0x03 CONTEXT_ERROR -- Error signalled because an error was reported reading/writing the context buffer 0x04 PAYLOAD_ERROR -- Error signalled because an error was reported reading/writing the payload 0x05 INVALID_MODE -- Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 15-7 RSVD0 Reserved, always set to zero. 6 ERROR_ PAGEFAULT This bit indicates a page fault occurred while converting a virtual address to a physical address.. When an error is detected, the channel's processing will stop until the error handled by software. 5 ERROR_DST This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the channel's processing will stop until the error handled by software. 4 ERROR_SRC This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the channel's processing will stop until the error handled by software. 3 ERROR_ PACKET This bit indicates that a bus error occurred when reading the packet or payload or when writing status back to the packet paylaod. When an error is detected, the channel's processing will stop until the error is handled by software. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1114 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) HW_DCP_CH2STAT field descriptions (continued) Field Description 2 This bit indicates that the hardware detected an invalid programming configuration such as a buffer length ERROR_SETUP that is not a multiple of the natural data size for the operation. When an error is detected, the channel's processing will stop until the error is handled by software. 1 HASH_ MISMATCH The bit indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled by software. 0 RSVD_ COMPLETE This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing of the packet has completed. This was done so that software can verify that each packet completed properly in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion bit for the channel is effectively the channel interrupt status bit. 13.3.27 DCP Channel 2 Options Register (HW_DCP_CH2OPTS) The DCP Channel 2 Options Status register contains optional control information that may be used to further tune the behavior of the channel. HW_DCP_CH2OPTS: 0x1B0 HW_DCP_CH2OPTS_SET: 0x1B4 HW_DCP_CH2OPTS_CLR: 0x1B8 HW_DCP_CH2OPTS_TOG: 0x1BC The options register can be used to control optional features of the channels. Address: 8002_8000h base + 1B0h offset = 8002_81B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSVD R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 RECOVERY_TIMER W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CH2OPTS field descriptions Field 31-16 RSVD RECOVERY_ TIMER Description Reserved, always set to zero. This field indicates the recovery time for the channel. After each operation, the recover timer for the channel is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate operation on the next packet in the chain until the recovery time has been satisfied. The timebase for the recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1115 Programmable Registers 13.3.28 DCP Channel 3 Command Pointer Address Register (HW_DCP_CH3CMDPTR) The DCP channel 3 current command address register points to the multiword descriptor that is to be executed (or currently being executed). The channel may be activated by writing the command pointer address to a valid descriptor in memory and then updating the semaphore to a non-zero value. After the engine completes processing of a descriptor, the next_ptr field from the descriptor is moved into this register to enable processing of the next descriptor. All channels with a non-zero semaphore value will arbitrate for access to the engine for the subsequent operation. DCP Channel 3 is controlled by a variable sized command structure. This register points to the command structure to be executed. EXAMPLE HW_DCP_CHn_CMDPTR_WR(3, v); // Write channel 3 command pointer pCurptr = (hw_DCP_chn_cmdptr_t *) HW_DCP_CHn_CMDPTR_RD(3); // Read current command pointer Address: 8002_8000h base + 1C0h offset = 8002_81C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CH3CMDPTR field descriptions Field ADDR Description Pointer to descriptor structure to be processed for channel 3. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1116 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 13.3.29 DCP Channel 3 Semaphore Register (HW_DCP_CH3SEMA) The DCP Channel 3 semaphore register is used to synchronize the CPU instruction stream and the DMA chain processing state. After a command chain has been generated in memory, software should write the address of the first command descriptor to the CMDPTR register and then write a non-zero value to the semaphore register to indicate that the channel is active. Each command packet has a chaining bit which indicates that another descriptor should be loaded into the channel upon completion of the current descriptor. If the chaining bit is not set, the next address will not be loaded into the CMDPTR register. Each packet also contains a decrement semaphore bit, which indicates that the counting semaphore should be decremented after the operation. A channel is considered active when the semaphore is a non-zero value. When programming a series operations, software must properly program the semaphore values in conjunction with the decrement_semaphore bits in the control packets to ensure that the proper number of descriptors are activated. A semaphore may be cleared by software by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. The logic will also clear the semaphore if an error has occurred. Each DCP channel has an 8 bit counting semaphore that is used to synchronize between the program stream and and the DCP chain processing. DCP processing continues until the engine attempts to decrement a semaphore that has already reached a value of zero. When the attempt is made, the DCP channel is stalled until software increments the semaphore count. Address: 8002_8000h base + 1D0h offset = 8002_81D0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD2 R 20 19 18 17 16 15 14 13 VALUE 12 11 10 9 8 7 6 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 INCREMENT W Reset 5 0 0 0 0 0 0 0 0 0 HW_DCP_CH3SEMA field descriptions Field Description 31-24 RSVD2 Reserved, always set to zero. 23-16 VALUE This read-only field shows the current (instantaneous) value of the semaphore counter. 15-8 RSVD1 Reserved, always set to zero. INCREMENT The value written to this field is added to the semaphore count in an atomic way such that simultaneous software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP channel decrements the count on the same clock, then the count is incremented by a net one. The semaphore may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1117 Programmable Registers 13.3.30 DCP Channel 3 Status Register (HW_DCP_CH3STAT) The DCP Channel 3 Interrupt Status register contains the interrupt status bit and the tag of the last completed operation from the command chain. If an error occurs during processing, the ERROR bit is set and an interrupt is generated. HW_DCP_CH3STAT: 0x1E0 HW_DCP_CH3STAT_SET: 0x1E4 HW_DCP_CH3STAT_CLR: 0x1E8 HW_DCP_CH3STAT_TOG: 0x1EC The interrupt status register is updated at the end of each work packet. If the interrupt bit is set in the command packet's command field, an interrupt will be generated once the packet has completed. In addition, the tag value from the command is stored in the TAG field so that software can identify which command structure was the last to complete. If an error occurs, the ERROR bit is set and processing of the command chain is halted. Address: 8002_8000h base + 1E0h offset = 8002_81E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 TAG R ERROR_CODE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1118 Freescale Semiconductor, Inc. 9 8 7 0 0 0 0 RSVD0 R 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD_COMPLETE 10 HASH_MISMATCH 11 ERROR_SETUP 12 ERROR_PACKET 13 ERROR_SRC 14 ERROR_DST 15 Bit ERROR_PAGEFAULT Chapter 13 Data Co-Processor (DCP) W Reset 0 0 0 0 0 0 HW_DCP_CH3STAT field descriptions Field 31-24 TAG Description Indicates the tag from the last completed packet in the command structure 23-16 Indicates additional error codes for some error conditions. ERROR_CODE 0x01 NEXT_CHAIN_IS_0 -- Error signalled because the next pointer is 0x00000000 0x02 NO_CHAIN -- Error signalled because the semaphore is nonzero and neither chain bit is set 0x03 CONTEXT_ERROR -- Error signalled because an error was reported reading/writing the context buffer 0x04 PAYLOAD_ERROR -- Error signalled because an error was reported reading/writing the payload 0x05 INVALID_MODE -- Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) 15-7 RSVD0 Reserved, always set to zero. 6 ERROR_ PAGEFAULT This bit indicates a page fault occurred while converting a virtual address to a physical address.. When an error is detected, the channel's processing will stop until the error handled by software. 5 ERROR_DST This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the channel's processing will stop until the error handled by software. 4 ERROR_SRC This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the channel's processing will stop until the error handled by software. 3 ERROR_ PACKET This bit indicates that a bus error occurred when reading the packet or payload or when writing status back to the packet paylaod. When an error is detected, the channel's processing will stop until the error is handled by software. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1119 Programmable Registers HW_DCP_CH3STAT field descriptions (continued) Field Description 2 This bit indicates that the hardware detected an invalid programming configuration such as a buffer length ERROR_SETUP that is not a multiple of the natural data size for the operation. When an error is detected, the channel's processing will stop until the error is handled by software. 1 HASH_ MISMATCH The bit indicates that a hashing check operation mismatched for control packets that enable the HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled by software. 0 RSVD_ COMPLETE This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing of the packet has completed. This was done so that software can verify that each packet completed properly in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion bit for the channel is effectively the channel interrupt status bit. 13.3.31 DCP Channel 3 Options Register (HW_DCP_CH3OPTS) The DCP Channel 3 Options Status register contains optional control information that may be used to further tune the behavior of the channel. HW_DCP_CH3OPTS: 0x1F0 HW_DCP_CH3OPTS_SET: 0x1F4 HW_DCP_CH3OPTS_CLR: 0x1F8 HW_DCP_CH3OPTS_TOG: 0x1FC The options register can be used to control optional features of the channels. Address: 8002_8000h base + 1F0h offset = 8002_81F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSVD R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 RECOVERY_TIMER W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_CH3OPTS field descriptions Field 31-16 RSVD RECOVERY_ TIMER Description Reserved, always set to zero. This field indicates the recovery time for the channel. After each operation, the recover timer for the channel is initiallized with this value and then decremented until the timer reaches zero. The channel will not initiate operation on the next packet in the chain until the recovery time has been satisfied. The timebase for the recovery timer is 16 HCLK clock cycles, providing a range of 0ns to 8.3ms at 133 MHz operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1120 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) 13.3.32 DCP Debug Select Register (HW_DCP_DBGSELECT) This register selects a debug register to view. This register selects debug information to return in the debug data register. Address: 8002_8000h base + 400h offset = 8002_8400h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 RSVD R 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 INDEX W Reset 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_DBGSELECT field descriptions Field Description 31-8 RSVD Reserved, always set to zero. INDEX Selects a value to read through the debug data register. 0x01 0x10 0x11 0x12 0x13 CONTROL -- OTPKEY0 -- OTPKEY1 -- OTPKEY2 -- OTPKEY3 -- 13.3.33 DCP Debug Data Register (HW_DCP_DBGDATA) Reading this register returns the debug data value from the selected index. This register returns the debug data from the selected debug index source. Address: 8002_8000h base + 410h offset = 8002_8410h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DCP_DBGDATA field descriptions Field DATA Description Debug Data i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1121 Programmable Registers 13.3.34 DCP Page Table Register (HW_DCP_PAGETABLE) The DCP Page Table register controls the virtual memory functionality of the DCP. It provides a base address for the page table as well as an enable/disable bit and the ability to flush the cached page table entries. This register returns the debug data from the selected debug index source. Address: 8002_8000h base + 420h offset = 8002_8420h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BASE W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE Bit 0 FLUSH Reset 0 0 0 0 0 0 0 0 0 R BASE W Reset 0 0 0 0 0 0 0 HW_DCP_PAGETABLE field descriptions Field Description 31-2 BASE Page Table Base Address. The page table must be word aligned and the pointer should reference a page table in the standard ARM format. 1 FLUSH Page Table Flush control. To flush the TLB, write this bit to a 1 then back to a 0. 0 ENABLE Page Table Enable control. Virtual addressing will only be used when this bit is set to a 1. Disabling the page table will not flush any cached entries, so software should write the FLUSH high and enable LOW when updating page tables. 13.3.35 DCP Version Register (HW_DCP_VERSION) Read-only register indicating implemented version of the DCP. This register returns the debug data from the selected debug index source. Address: 8002_8000h base + 430h offset = 8002_8430h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1122 Freescale Semiconductor, Inc. Chapter 13 Data Co-Processor (DCP) HW_DCP_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-onlyl value reflecting the MAJOR version of the design implementation. 23-16 MINOR Fixed read-onlyl value reflecting the MINOR version of the design implementation. STEP Fixed read-onlyl value reflecting the stepping of version of the design implementation. 13.4 Disclaimer The license for the AEC code is documented here for compliance: Copyright (C) 2000-2003, ASICS World Services, LTD., AUTHORS All rights reserved. Redistribution and use in source, netlist, binary and silicon forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of ASICS World Services, the Authors and/or the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1123 Disclaimer i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1124 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.1 Overview The i.MX28 supports off-chip DRAM storage through the EMI controller, which is connected to the four internal AHB/AXI busses. The EMI supports multiple external memory types, including the following: * 1.8-V mobile DDR1 (LP-DDR1) * Standard 1.8 V DDR2 * Low-voltage 1.5 V DDR2 (LV-DDR2) The EMI uses two primary clocks: the AHB bus, HCLK, and the DRAM source clock, EMI_CLK. The maximum specified frequencies for these two clocks are 200 MHz. The HCLK and EMI_CLK can be either synchronous or asynchronous, configurable. The EMI consists of the following 3 major components: * AXI/AHB bus interface and multi-port arbiter * DRAM Control Logic * DRAM PHY 14.1.1 Block Diagram A high-level block diagram of the EMI is shown in the following figure. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1125 EMI Address Mapping EMI AXI Interface AXI - 64 AHB - 32 AHB-2-AXI Bridge AXI Interface AHB - 32 AHB-2-AXI Bridge AXI Interface AHB - 32 AHB-2-AXI Bridge AXI Interface AHB - 32 AHB Register Port Bus Arbiter & Read/Write Command Queue & Read/Write Data Queues DDR Control Logic DFI DDR PHY External DDR Memory Programmable Register Settings Figure 14-1. EMI Top-Level Block Diagram EMI implements the following five bus interfaces: * One 64-bit AXI bus interface * Three 32-bit AHB bus interfaces to read or write data from or to external DDR memory * One AHB interface dedicated to read/write PIO registers 14.2 EMI Address Mapping The EMI automatically maps AXI and AHB bus addresses to the DRAM memory in a contiguous block. Addressing starts at user address 0 and ends at the highest available address according to the size and number of DRAM devices present. This mapping is dependent on how the memory controller was configured and how the parameters in the internal EMI registers are programmed. The exact number and values of these parameters depends on the configuration and the type of memory for which the memory controller was designed. The mapping of the address space to the internal data storage structure of the DRAM devices is based on the actual size of the DRAM devices available. The size is stored in user-programmable parameters that must be initialized at power up. Certain DRAM devices allow for different mapping options to be chosen, while other DRAM devices depend on the burst length chosen. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1126 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.2.1 DDR SDRAM Address Mapping Options The address structure of DDR SDRAM devices contains five fields. Each of these fields can be individually addressed when accessing the DRAM. The address map for this EMI is ordered as follows: Chip Select Row Bank Column Data Path The maximum widths of the fields are based on the configuration settings. The actual widths of the fields may be smaller if the device address width parameters (addr_pins, eight_bank_mode, and column_size) are programmed differently. * Chip Select--EMI supports 2 chip-select. The "Chip Select" field occupies 1-bit. * Datapath--EMI supports 16-bit data width for external DDR memory. The "Datapath" field occupies 1-bit. * Bank--The DDR memory device defines the bank number. The EMI supports 4 or 8 banks of DDR memory, which occupies 2 or 3-bits * Row, Column--The DDR memory device defines the width of these fields 14.2.2 Maximum Address Space The maximum user address range is determined by the width of the memory datapath, the number of chip select pins, and the address space of the DRAM device. The maximum amount of memory can be calculated by the following formula: chip-selects x bank x 2^(row + column) x datapath (unit: byte) For this DRAM controller, the maximum values for these fields are as follows: * * * * * Chip Selects = 2 Bank : 4 or 8, max 8 Row : max 15-bits Column : max 12-bits Datapath width = 2 bytes (16-bits) As a result, the maximum memory area supported by EMI module is 4 Gbytes. But in i.MX28, the system memory-map limits the maximum accessible area to 1 Gbytes. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1127 EMI Clocking 14.2.3 Memory Mapping to Address Space The following figures provide examples of address space mapping from a 32-bit bus address to DRAM address fields. The first example corresponds to a memory device with 8 banks, 13 row bits, and 10 column bits. The second example corresponds to a memory device with 8 banks, 14 row bits, and 10 column bits. dont care [31:29] chip-select [28] row [27:14] bank [13:11] column [10:1] datapath [0] Figure 14-2. Memory Address Mapping Example 1 dont care [31:28] chip-select [27] row [26:14] bank [13:11] column [10:1] datapath [0] Figure 14-3. Memory Address Mapping Example 2 14.3 EMI Clocking The EMI uses an external clock input from the ASIC device. Considering the design speed and complexity, this design may not be able to adhere to the skew and delay requirements of a PLL-based clocking scheme. As an alternative, this EMI uses a clocking system that propagates a clock from the memory controller to the memory devices. The largest challenge with this clock forwarding scheme is the management of the clock skew for the round-trip data transfer. 14.3.1 General System Behavior In this system, the command and address for the transaction are sent from the memory controller coincident with the falling edge of the memory controller clock. Because the clock, command, and address signals all have roughly the same pad and flight delays to travel to the memory, the rising edge of the clock at the memory is centered with the command and address signals, allowing reliable capture. In addition, because all signals are sourced from the same location, this clocking system can tolerate a significant skew and provides more flexibility in timing. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1128 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.3.2 Changing Input Clock Frequency The operating frequency of the EMI is dependent on an ASIC-level input clock. There are situations in which the user may wish to modify the frequency of the clock without resetting the memory controller. To change the clock frequency at which the EMI operates, the memory controller must stop processing requests, the clock must be adjusted, the memory controller's timing parameters must be reprogrammed, and then the memory controller can be restarted. The procedure to follow for changing the clock frequency is as follows: 1. Ensure that the EMI is idle, which is when the controller_busy signal is low. 2. Put the memory devices into self-refresh mode by asserting the srefresh parameter to `b1. It is imperative that the memory devices be placed into self-refresh through this parameter and not through any other means. If the devices were placed into selfrefresh mode through one of the low-power modes (programming of the lowpower_control parameter), then the user should first bring the devices out of that low power mode manually and then program the srefresh parameter with a `b1. 3. Wait until the memory devices have been placed into self-refresh mode, as indicated by the cke_status signal. This signal is the value of the control_cke signal inside the memory controller, delayed by the number of clocks specified in the cke_delay parameter. 4. Mask the DLL lock state change bit (bit 8) in the int_status parameter by setting bit 8 in the int_mask parameter to `b1. 5. Stop the memory controller by writing a `b0 to the start parameter. 6. Clear the DLL lock state change bit (bit 8) in the int_status parameter by writing bit 8 in the int_ack parameter to `b1. Also, clear any other interrupts in the int_status parameter by writing to the int_ack parameter. 7. If the user wishes to use a controller interrupt to signal when the DLL has relocked, then unmask the DLL lock state change bit (bit 8) in the int_status parameter by clearing bit 8 in the int_mask parameter to a `b0. If the user wishes to poll the dlllockreg parameter for this indication, then this step may be skipped. 8. The clock frequency may now be changed. Once the clock frequency has stabilized, the user should modify any parameters that may be affected by the frequency change such as caslat_lin, caslat_lin_gate, any of the timing parameters, and so on. The user should review the parameters carefully to ensure that all parameters that require modification are changed. 9. After all parameters have been updated, restart the EMI by writing a `b1 to the start parameter. This forces the DLL to lock to the new frequency. 10. Once the DLL has locked and the PHY has initialized, the memory controller input signal dfi_init_complete will be asserted. If the user is using a controller interrupt to monitor DLL re-lock, then wait for a controller interrupt or poll the int_status i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1129 EMI AHB and AXI Interface parameter for the DLL lock state change bit (bit 8) to be set. If the controller interrupt is not being used, poll the dlllockreg parameter for the bit to be set. 11. At this point, the user may bring the memory devices out of self-refresh by clearing the srefresh parameter to `b0. The user does not need to wait to send commands to the memory controller after clearing the srefresh parameter; the memory controller will adjust for self-refresh exit time before processing memory commands. 14.4 EMI AHB and AXI Interface This section discusses how to cofingure and use the EMI AHB and AXI interface. 14.4.1 AHB-AXI Bridges An incoming AHB transaction is translated to an AXI command in the AHB-AXI bridge. The AHB-AXI bridges support the AHB-lite protocol and are designed for multilayer AHB architectures. This implies that an AHB slave port never responds with a SPLIT or a RETRY response type. Early termination of AHB bursts is fully supported. Note that an the AHB slave port can be used in a system with masters that support the full AHB protocol as long as the system is multilayer AHB. For simplicity, the AHB-AXI bridges do not support exclusive access or lock accesses. 14.4.2 AXI Interfaces The AXI interfaces function as AXI slaves to the AHB-AXI bridges. Transfers are burstbased of variable byte counts. The transfer types INCR and WRAP are fully supported. FIXED burst types are not supported. Each interface contains five separate channels of traffic to/from the memory: write response, read command, write command, read data, and write data. 14.4.2.1 Internal Command Handling The EMI uses placement logic to fill the command queue with a command order that maximizes the throughput and efficiency of the core logic. Command reordering in the placement queue supports AXI and AHB restrictions. Note: The AHB bus does not allow multiple threads on a single port; therefore, ports with an AHB-AXI bridge only use thread ID "0" for all commands. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1130 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) Note: For simplicity, ports that connect to an AHB bus through an AHB-AXI bridge will be referenced as "AHB-bridged" ports. Ports that connect directly to an AXI bus will be referenced as "native AXI" ports. If the placement logic is being used, the EMI will optimize the core by re-ordering read and write commands as necessary based on these rules: * For the AHB-bridged ports, read commands will always execute in the same order as they were accepted into the port. Similarly, write commands will always execute in the same order as they were accepted into the port. * For the native AXI ports, read commands from the same thread ID will always execute in the same order as they were accepted into the port. However, read commands from different thread IDs on the native AXI ports may be automatically re-arranged in the core logic to execute out-of-order. When commands from different thread IDs are re-ordered, read data returned to the AXI port interfaces will also be out-of-order and may be interleaved. To avoid re-ordering within a port, the AXI bus master should use one thread ID for all commands from any port. * For the native AXI ports, write commands from the same or different thread IDs will always execute in the same order as they were accepted into the port. * Read or Write commands from different AHB-bridged or native AXI ports may be automatically re-arranged in the EMI to execute out-of-order. * Within an AHB-bridged port, a write command that is accepted into the port after a read will not be executed ahead of the read command. However, a read command that is accepted into the port after a write may be indeterminably re-arranged in the EMI ahead of the write command. * Within a native AXI port, read and write commands from the same or different thread IDs may be re-arranged in the core logic. Read and write commands with different thread IDs will be automatically re-arranged to execute in an optimal order, as long as there are no collisions between the commands. Command handling is summarized in the following table. Table 14-1. Reordering/Interleaving Behavior Commands Thread ID Can Commands be Rearranged and Data be Interleaved? Two Read Commands from 1 port Same No Two Read Commands from 1 port Different Yes1 Same or Different Yes Two Write Commands from 1 port Same No Two Write Commands from 1 port Different No 1 Same or Different Yes Two Read Commands from Different ports Two Write Commands from Different ports Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1131 EMI AHB and AXI Interface Table 14-1. Reordering/Interleaving Behavior (continued) Commands Thread ID Can Commands be Rearranged and Data be Interleaved? Read/Write or Write/Read Command from 1 port Same Maybe2 Read/Write or Write/Read Command from 1 port Different Yes 1 Read/Write or Write/Read Command from Different ports Same or Different Yes 1. Since all commands from an AHB-bridged port use a single thread ID, this option is not applicable for AHB-bridged ports. 2. For a native AXI port, read and write commands may be interleaved. For an AHB-bridged port, a write command will not be placed ahead of a read command from the same port. However, a read command may be placed ahead of a write command. An incoming AXI transaction is mapped into a core logic-level transaction, then synchronized from the AXI clock domain to the core logic clock domain and stored in the AXI port FIFOs. Each instruction consists of an address, size, length and thread ID. Since a port may utilize multiple thread IDs, the source ID that is used in the core logic is a combination of both the port and thread information. This concatenation occurs in the Arbiter and this source ID is used in the placement logic. From the AXI FIFOs, the transaction is presented to the Arbiter which arbitrates requests from all ports and forwards a single transaction to the core logic. 14.4.2.2 AHB Signal to AXI Signal Translation Table 14-2. Burst Type Translation AHB AXI Burst type AXI Burst length (ahb_hburst) (axi_awburst / axi_arburst) (axi_awlen / axi_arlen) SINGLE `b000 FIXED `b00 1 word `b0000 INCR `b001 INCR `b01 4 words `b0011 WRAP4 `b010 WRAP `b10 4 words `b0011 INCR4 `b011 INCR `b01 4 words `b0011 WRAP8 `b100 WRAP `b10 8 words `b0111 INCR8 `b101 INCR `b01 8 words `b0111 WRAP16 `b110 WRAP `b10 16 words `b1111 INCR16 `b111 INCR `b01 16 words `b1111 14.4.2.3 Configured Options Each AXI port has been defined for the requirements of the intended system. The configured options are: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1132 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) * Type of interface to the EMI core clock (emi_clk) All ports are clock domain programmable relative to the emi_clk. These ports initialize in asynchronous operation, but can be changed by programming the associated axiY_fifo_type_reg parameter. For more information on the programming of this parameter, refer to section Port Clocking. Asynchronous FIFOs handle the clock domain crossing when operating in any of the non-synchronous modes. * Width of the ID Each port is configured with a thread ID of 10 bits. * Priority Definition Command priority is defined based on the port and the command type. For each port Y, there is an axiY_r_priority parameter which defines priorities for all read commands and an axiY_w_priority parameter which defines priorities for all write commands. Supported priority values range from 0 to 7, with 0 as the highest priority. * Register Port The 32-bit AHB register port is fixed in Asynchronous mode between the AHB bus clock domain and the emi_clk domain. * Port Bridging The following table shows the front-end bridge settings. Table 14-3. Front-End Bridge Settings Port Number Bus Connection Internal Port Type Port 0 AXI Native AXI Port 1 AHB AHB-AXI Bridged Port 2 AHB AHB-AXI Bridged Port 3 AHB AHB-AXI Bridged * Buffering i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1133 EMI AHB and AXI Interface Each AXI interface contains a command, a read and a write FIFO, and a response storage array. In addition, each programmable port contains an asynchronous response FIFO to synchronize the memory response to the port clock domain when operating asynchronously. Table 14-4. AXI Port FIFOs Port Number Port Data Width Clock Domain Type Command Write FIFO Read FIFO FIFO Depth Depth Depth Response FIFO Depth Response Storage Array Depth Port 0 64 Programmable 4 8 8 4 8 Port 1 32 Programmable 2 8 8 4 4 Port 2 32 Programmable 2 8 8 4 4 Port 3 32 Programmable 4 8 8 4 8 * Exclusive Access Buffer Depth Exclusive access is an optional AXI feature that is only supported for the native AXI ports. This type of access will only be used if exclusive access commands are issued to the memory controller by driving the axiY_ARLOCK signal to `b10 with a read command. Each native AXI port contains 1 exclusive buffer and therefore each port may monitor the exclusivity of up to 1 transaction at any time. Refer to section Exclusive Access for more information. * Error Detection When an illegal operational condition is detected on a new AXI transaction entering the port, the port responds through an AXI error signal and the controller interrupt signal, and the error signature is recorded in the register space. The AXI error signal flagged is dependent on the type of transaction that caused the error (read or write). The controller interrupt and the signature information is dependent on type of error (command or data). Refer to section Error Responses for more information on error detection. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1134 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.4.3 Port Clocking There are four user-selectable modes of operation for each of the AXI port interfaces. The mode is set by programming the corresponding axiY_fifo_type_reg parameter. The four settings are: * Synchronous (`b11) The AXI port clock and the emi_clk must be aligned in frequency in phase. The AXI port interface block will not be required to perform any clock synchronization in any of the FIFOs. * 1:2 Port:Core Pseudo-Synchronous (`b10) Reserved. Do not select this mode. Select "Asynchronous" instead. The port operates at half of the frequency of the emi_clk frequency, with clocks that are aligned in phase. One stage of the two-stage synchronization logic of the FIFOs will be utilized to synchronize commands, write data and read data to the appropriate clock domain. * 2:1 Port:Core Pseudo-Synchronous (`b01) Reserved. Do not select this mode. Select "Asynchronous" instead. The port frequency is twice the emi_clk frequency, although the clocks are aligned in phase. One stage of the two-stage synchronization logic of the FIFOs will be utilized to synchronize commands, write data, and read data to the appropriate clock domain. * Asynchronous (`b00) The AXI bus and the core logic operate on clocks that are mismatched in frequency and phase. The AXI port FIFOs use two stages of synchronization logic to synchronize commands, write data, and read data to the appropriate clock domain. 14.4.4 AXI Interface FIFOs Each programmable port contains four FIFOs for commands, read data, write data and response synchronization. The response synchronization FIFOs are only used when operating in asynchronous mode. In addition to the FIFOs, each port contains a storage array to hold the read and write responses. The depths and clock domain relativity of the FIFOs and the array are shown in Table 14-4. The five channels of traffic and their relationship to the port FIFOs are shown below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1135 EMI AHB and AXI Interface AXI Interface AXI Write Response Channel Synch FIFO Resp Array AXI Write Data Channel Bus Arbiter & Read/Write Command Queue & Read/Write Data Queues Write Data FIFO AXI Write Command Channel AXI Port AXI Read Command Channel AXI Read Data Channel Command FIFO Arbiter Read Data FIFO Figure 14-4. AXI Interface FIFOs 14.4.5 AXI Write Response Channel When a write request is accepted into the AXI interface, an entry will be created in the Write-Response FIFO for that command. When a write response is ready, the response will be returned to the AXI master. Different masters may require this response at different stages of the write command. A master that needs to quickly release the bus would optimally receive the completion response as soon as the port has accepted the write command and all of the corresponding data. Another master may wish to wait until the data has been accepted into the core logic, or successfully written to memory. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1136 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) Each AXI interface is configured with two signals that work together to determine when an instruction is considered complete and the write completion response will be returned to the master. These signals are axi_AWCACHE [0] and axi_AWCOBUF. The following table details the relationship between these signals. Table 14-5. Write Response Types Response Information1 axi_AWCACHE[0] axi_AWCOBUF 0 Irrelevant 1 0 Standard bufferable write command. Response is ready when the command and all associated data have been received by the AXI data port. There is no guarantee of data coherency across all AXI ports. 1 1 Coherent bufferable write command. Response is ready when the command has been accepted by the command queue in the core logic. This guarantees data coherency across all ports but reduces the overall write response latency relative to the non-bufferable option. Non-bufferable write command. Response is ready after the write data is committed to memory. 1. The response will only be sent if all of the older write responses have been issued for any thread ID on that port. axi_AWCACHE [0] comes from the standard AXI bus signal and the axi_AWCOBUF is configured by user-defined register "BRESP_TIMING" (Bit [0] of register HW_DRAM_CTL00). Note that in the "AHB-AXI Bridge", axi_AWCACHE [0] is tied-off to 1, and the axi_AWCOBUF is tied-off to 0. Therefore, the write reponse type of AXI Interface 1~3 is forced to "Standard Bufferable Write." 14.4.6 AHB Register Port The register port is an independent AHB port to the EMI. This port operates asynchronously. The register port only supports the AHB SINGLE burst type. The register port only supports transfer types of NONSEQ or IDLE. There is no support for INCR or WRAP burst types. There is no support for SEQ or BUSY transfer types. 14.4.7 AXI Transactions The AXI Interface supports burst tpye of INCR and WRAP. The AXI Interface supports burst length of 1-16 beats. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1137 EMI AHB and AXI Interface 14.4.8 Exclusive Access Note: The exclusive access option is an AXI-specific feature that requires use of the axi_ARLOCK and axi_AWLOCK signals. Therefore, this feature is only relevant for the native AXI ports. The exclusive access feature allows a master to monitor if a memory area has been altered since its last read. Exclusive access does not imply that the memory area is locked; other thread IDs of that port, or other ports, may access the area for reads or writes even though an exclusive access exists. If any writes occur to a memory area with a valid exclusive access request, the master will lose exclusivity and be informed of this status when it attempts to write to the area again. A loss of exclusivity does not trigger an interrupt or any error conditions; however, the AXI protocol requires that the write data is not written to memory if an exclusive write fails its exclusivity check. The master that has lost exclusivity must determine whether to restart the sequence by requesting another exclusive read or to write the data to the memory regardless through a non-exclusive write. 14.4.8.1 Initiating an Exclusive Access Request Exclusivity is enabled by issuing a read command to memory with the axi_ARLOCK signal driven to `b01. 14.4.8.2 Verifying the Request The AXI specification dictates restrictions for exclusive access requests. After being accepted in the port, an exclusive read request will be checked against these requirements. If any of these conditions are violated, the command will be passed to the core logic as a non-exclusive read. These restrictions are: * The address must be aligned to the total byte count. (Byte Count = (axi_ARLEN + 1) x 2^axi_ARSIZE) * The byte count must be a power-of-two, and less than 128 bytes. In addition, the AXI specification states that exclusive accesses can not be cacheable. However, since the EMI does not support cacheable commands, this bit is ignored and any cacheable exclusive access requests will be processed as non-cacheable exclusive accesses. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1138 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.4.8.3 Validity of an Exclusive Request The exclusive access will be considered valid from the point that the entry is created in the buffer until an activity occurs to invalidate it. These activities cause the "valid" bit of the exclusive access buffer entry to be cleared: * The same source ID issues a write command for the same starting addressing of the same length and beat size. * Any other source ID, from that port or another port, writes to any memory address in that memory span. Note: The EMI assumes that a single master will only communicate with a single port. Therefore, a command to another port, with the same AXI ID (axi_AWID or axi_AWID) will not violate the exclusivity of another port's exclusive region simply based on ID match. * The user is tracking enough exclusive access commands that the exclusive access buffer for this port is full. Newer commands will be stored, overriding a previous exclusive access entry. * The same source ID issues another exclusive read request for another memory region. This will not clear the valid bit, but will actually overwrite the entire exclusive access buffer entry (and then set the valid bit). The EMI will only track one exclusive region for each source ID. 14.4.8.4 Read Commands to Exclusive Access Regions A memory area is not locked while an exclusive access is valid and therefore other source IDs may issue read commands to a memory area identified as exclusive. Reads, even other exclusive reads, do not affect the exclusivity of a region. Normal read commands will be processed as usual and, if successful, respond to the master with an OKAY (`b00) on the axi_RRESP signal. Exclusive read commands will result in additional entries being created in the exclusive access buffers and, if successful, an EXOKAY (`b01) response will be sent on the axi_RRESP signal. Note: An exclusive read request from any source ID, from the same port or another port, even to an overlapping address within an exclusive access region, will not affect the initial exclusive access. Another entry will be created in that port's buffer for this request. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1139 EMI AHB and AXI Interface 14.4.8.5 Non-Exclusive Write Commands to Exclusive Access Regions Any master in the system may issue a write command to a memory area identified as exclusive. However, a standard write to any address within an active exclusive access region will invalidate the exclusivity of that region. In this case, the "valid" bit of any exclusive access buffer entry that spans the modified locations in memory will be cleared and future exclusive write requests to this region will fail their exclusivity check. 14.4.8.6 Exclusive Writes An exclusive write command is only distinguished from a standard write command by the axi_AWLOCK signal being driven to `b01. When an exclusive write is received, the EMI first compares the source ID (axi_AWID and port number), transaction beat length (axi_AWLEN), transaction start address (axi_AWADDR), and transaction beat size (axi_AWSIZE) to the entries in the exclusive access buffer of that port. 14.4.8.7 Passing Exclusive Access Check If any of the valid buffer entries exactly match the incoming command, the following activities occur: * That buffer entry's "valid" bit is cleared. * All other buffer entries, from this port or other ports, are checked to see if this write invalidates any other exclusive access regions. If so, the "valid" bits of these entries will be cleared. * The transaction is processed. * If successful, the write response channel (axi_BRESP) returns an EXOKAY response (`b01) to the master. 14.4.8.8 Failing Exclusive Access Check If an invalid buffer entry exactly matches the incoming command, or no buffer entries exactly match the incoming command, then the write will fail. The command will be processed internally as a flushed write command. For a flushed write, the write data will be cleared out of the memory controller FIFOs but the data stored in external DRAM memory will NOT change. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1140 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) The user will be informed of this condition through the write response channel (axi_BRESP). However, instead of an EXOKAY response, the memory controller will issue an OKAY response. This indicates to the master that the exclusive write did not occur. The master may re-issue the request as a non-exclusive write, or may restart the process by re-issuing the exclusive read. 14.4.9 Error Responses This section discusses AXI error responses and AXI error reporting. 14.4.9.1 AXI Error Response When an illegal operational condition is detected on a new AXI transaction entering the port, the port responds with an error condition. Instructions that generate AXI errors result in unpredictable behavior and may cause memory corruption and/or hang conditions. 14.4.9.2 AXI Error Reporting If an AXI command error occurs, a bit will be set in the int_status parameter and the address and source ID of the command are saved in the port_cmd_error_addr and port_cmd_error_id parameters, respectively. In addition, the access type that relate to the error are stored in the port_cmd_error_type parameter. Similarly, when a data error occurs, the source ID of the command is saved in the port_data_error_id parameter. The access type that relate to the error are stored in the port_data_error_type parameter. The bits in the error type parameters are not exclusive. Multiple bits may be set to indicate the type of errors that occurred. Reading the int_ack parameter will allow future errors to be captured in these error parameters. If multiple errors occur prior to an acknowledgment of the first error, the parameters will still represent the first error attributes. Other error signatures will be lost. If multiple errors occur simultaneously on different ports, the error information will represent the lowest numbered erring port. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1141 EMI AHB and AXI Interface 14.4.10 Arbiter From the port interface blocks, commands are presented to the Arbiter, which is responsible for arbitrating between the port requests and sending a single command to the core logic. Refer to the "EMI Multi-Port Arbiter" Chapter for details. 14.4.11 Write Data Queue The write data queue is a write data storage array for transactions. The queue consists of multiple buffers holding write data for the write requests of a particular port. Write data is stored in these buffers for commands in the command queue until the command is processed in the placement logic and needed by the DRAM command arbitration logic. The buffers can accept data whenever any space is available. 14.4.12 DRAM Command Processing The DRAM command processing logic is used to process the commands in the Command Queue. The logic organizes the commands to the memory devices in such a way that data throughput is maximized. DRAM-Bank opening and closing cycles are used for data transfers. The logic uses a variety of factors to determine when to issue bank open and close commands. The logic reviews the entire Command Queue for look-ahead of which banks are to be accessed in the future. The timing is then set to meet the trc and tras_min timing parameters of the memory devices, values which were programmed into the memory controller on initialization. This flexibility allows the memory controller to be tuned to extract the maximum performance out of memory devices. The parameters that relate to DRAM device protocol are listed in the "EMI Parameter Descriptions" Chapter. 14.4.13 Latency By using the placement logic of the command queue in the core logic, a new request through any port can be immediately placed at the top of the command queue or can interrupt an ongoing request. This scheme allows a high priority request to be serviced in the shortest possible time. However, since there are many factors that determine the placement into the command queue, there are also many factors that affect the actual latency of the command. These factors include: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1142 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) * The coherency status of the transactions already in the command queue: If there is a data coherency conflict with a transaction already in the command queue, the new transaction will be placed after the transaction that produced the conflict. The position of the conflicting transaction determines the latency of the high priority read or write command. * The priority status of the transactions already in the command queue: If the new command has a higher priority than those already in the command queue, the new request will be serviced ahead of the lower priority command. As a result, the latency of the new command will be lower than the latency of the older command. * The read, write, and bank information of the transactions already in the command queue: In general, reads will be placed ahead of writes when both are of the same priority level. Read commands are grouped with other read commands of similar priorities and write commands are grouped with other write commands of similar priorities. Among these groupings, transactions with similar bank and different row destinations are separated as much as possible. If all of the placement conditions are met, then a new command would be placed at the top of the command queue. However, if the new command is of a higher priority than the transaction that is executing, the current command will be interrupted and the new command will execute first. The interruption will occur at a natural burst boundary of the DRAMs. The interrupted transaction will be placed at the top of the placement queue and it will resume after the new request is completed. The page status of the new transaction determines when the current transaction is interrupted. If the page for the new transaction is already open, then the current transaction will be interrupted at the next natural burst boundary of the DRAM device. If the page is not currently open, then the new request will be placed at the top of the command queue while its page is prepared. There are a fixed number of latency cycles in the memory controller, based on the pipeline through the memory controller logic. These steps are: 1. 2. 3. 4. 5. 6. 7. 8. 9. Command passing through the port interface. (fixed) Arbitration through the Arbiter. (fixed) Placement into the Command Queue. (fixed) Memory Command Generation. (variable) Sending of control signals from the core logic to flip-flops near the I/O drivers. (fixed) Flight time to the DRAM device. (variable) Flight time from the DRAM device. (variable) For reads, synchronization of read data from the data strobe domain. (fixed) For reads, data pass through the port interface. (fixed) For asynchronous AXI interfaces, an additional 4-5 cycles are included for the round-trip transaction to synchronize to the EMI_CLK. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1143 EMI Multi-Port Arbiter 14.5 EMI Multi-Port Arbiter Resp Array Synch FIFO Write Response Control Logic Write Data FIFO AXI Port Arbiter Command FIFO Read Data FIFO Write Data Queue Resp Array Synch FIFO ( N channels ) Write Data FIFO AXI Port Arbiter Command FIFO Command Queue Read Data FIFO Core Resp Array with Arbiter Synch FIFO DDR Control Placement Logic DFI Logic Write Data FIFO AXI Port Arbiter Command FIFO Read Data FIFO Resp Array ( 1 channel ) Synch FIFO Write Data FIFO AXI Port Arbiter Read Data Queue Core Logic Command FIFO Read Data FIFO Figure 14-5. EMI Core Logic i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1144 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) The Arbiter is responsible for arbitrating requests from the ports and sending requests to the core logic. Each transaction received at the Arbiter logic has an associated priority, which works with each port's arbitration logic to determine how ports issue requests to the core logic. This memory controller supports the Bandwidth Allocation/Priority Round-Robin arbitration scheme. The Arbiter logic routes read data from the core logic to the appropriate port. The requesting port is assumed able to receive the data. Write data from each port is connected directly to its own write data interface in the core logic, allowing the ports to independently pass write data to the core buffers. 14.5.1 Arbitration Overview The bandwidth allocation scheme is an extension of simple round-robin arbitration. It is based on the priority of the requests and is influenced by the actual bandwidth consumed by the port inside the core logic. Priority round-robin arbitration is a complex arbitration scheme. In order to understand its operation, each concept must be first understood individually. Section Understanding Round-Robin Arbitration through section Understanding Port Bandwidth Hold-Off describe the various components of priority round-robin arbitration. 14.5.2 Understanding Round-Robin Arbitration Round-robin operation is a simple form of arbitration which offers each port an opportunity to issue a command. This scheme uses a counter that rotates through the port numbers, incrementing every time a port request is granted. If the port that the counter is referencing has an active request, and the core command queue is not full, then this request will be sent to the core. If there is not an active request for that port, then the port will be skipped and the next port will be checked. The counter will increment by one whenever any request has been processed, regardless of which port's request was arbitrated. Round-robin operation ensures that each port's requests can be successfully arbitrated into the core logic every N cycles, where N is the number of ports in the EMI. No port will ever be locked out, and any port can have its requests serviced on every cycle as long as all other ports are quiet and the command queue is not full. An example of the round-robin scheme is shown in Table "Round-Robin Operation Example". i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1145 EMI Multi-Port Arbiter Cycles 0, 2 and 6 show the system behavior when the command queue is full. Cycle 8 shows the system behavior when the port addressed by the arbitration counter does not have an active request. All other cycles show normal behavior. Table 14-6. Round-Robin Operation Example CYCLE PORT ADDRESS ED BY THE ARBITRATI ON COUNTER PORTS REQUESTING PORT 0 PORT 1 PORT 2 PORT 3 COMMAND WINNER QUEUE OF FULL ? ARBITRATI ON VALUE OF COUNTER AT NEXT CYCLE 0 0 Y Y Y Y Yes None 0 1 0 Y Y Y Y No P0 1 2 1 - Y Y Y Yes None 1 3 1 Y Y Y Y No P1 2 4 2 Y - Y Y No P2 3 5 3 Y - - Y No P3 0 6 0 Y - Y - Yes None 0 7 0 Y - Y - No P0 1 8 1 - - Y - No P2 2 9 2 - - Y Y No P2 3 10 3 Y - - Y No P3 0 14.5.3 Understanding Port Priority For AXI ports, the priority is associated with a port and each port has separate priority parameter for reads and writes. These values are stored into the programmable parameters axiY_r_priority and axiY_w_priority (where Y represents the port number) at controller initialization. Internally, the ports are organized into priority groups based on their priority settings. All ports within a priority group are treated equally for arbitration unless a port has exceeded its allocated bandwidth. The priority value is also used by the placement logic inside the core logic when filling the command queue. A priority value of 0 is highest priority, and a priority value of (decimal) 7 is the lowest priority. The user may program at priority level 0; however, it is best to reserve this priority value so that the placement queue can elevate to this level through aging. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1146 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.5.4 Understanding Port Bandwidth Each port has an associated bandwidth limit that sets the maximum percentage of the core logic bandwidth that the port is allowed to use. Once this level is reached, the Arbiter will no longer accept requests from this port until the bandwidth usage drops below the threshold. This scheme allows for the bandwidth to be shared between the ports. If required, an overflow option allows the port to continue to receive requests after the bandwidth limit has been reached. The bandwidth limits are stored in the programmable parameters axiY_bdw for each port Y at EMI initialization. The axiY_current_bdw parameters are used to track the actual bandwidth utilized as computed by the bandwidth calculation module inside the Arbiter. Port bandwidth is computed by counting the number of cycles that the core logic is busy actively processing that port's request in each 100 cycle period, referred to as the statistics window. In the EMI, 10 counters are used for this computation. The counters track the number of active cycles in each statistics window, generating a moving average bandwidth value for each port. This is the actual bandwidth utilized value saved in the current bandwidth parameters (axiY_current_bdw). The values in the current bandwidth parameters are updated every 10 cycles with the actual bandwidth used in the last 100 cycles. The core logic is defined as actively processing for a port if any of the following situations occur: * The core logic is ready to transfer write data from the port to memory, but the data has not arrived from the port. * The core logic is holding the port's command and is ready to transfer to memory, but is waiting to open a bank, precharge a bank, or some other memory-related action. * The core logic is actively transferring data from the port to memory. * The core logic is ready to transfer read data from memory to the port but the port is busy and unable to accept the data. If all ports are assigned 100% bandwidth, then bandwidth usage will not factor and arbitration will be purely based on priority. The following figure shows bandwidth usage for a 4-port system with a 100-cycle calculation window and 10 counters. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1147 EMI Multi-Port Arbiter Number of Active Cycles Bandwidth out of 10 Cycles Cycle Window Port 0 Port 1 Port 2 Port 3 10 5 7 2 9 7 1 9 9 2 3 0 0 3 3 6 8 1 3 3 10 3 3 10 1 3 3 7 4 1 4 0 0 3 3 0 1 2 3 1 0 3 3 3 3 5 5 5 8 2 3 10 10 1 0 7 8 3 5 0 0 5 5 3 4 3 7 3 2 9 3 10 10 1 0 1 1 5 3 0 Counter 0 Counter 9 Counter 8 Counter 7 Counter 6 Counter 5 Counter 4 Counter 3 Counter 2 Counter 1 Counter 0 0-9 10-19 20-29 30-39 40-49 50-59 60-69 70-79 80-89 90-99 100-109 110-119 120-129 130-139 140-149 150-159 160-169 170-179 180-189 190-199 Figure 14-6. System Bandwidth Example For this system, the bandwidth will be monitored over each 100 cycles. The bandwidth calculation parameters will be updated every 10 cycles with the bandwidth usage of the last 100 cycles as shown graphically in the figure. The bandwidth totals are shown in the previous figure. In the system, these values would be stored in the axiY_current_bdw parameters after each calculation. Table 14-7. System Bandwidth Usage Example COUNTER NUMBER CYCLES COUNTING CALCULATED USAGE PORT 0 PORT 1 PORT 2 PORT 3 0 0 - 99 61 / 100 = 61% 45 / 100 = 45% 37 / 100 = 37% 41 / 100 = 41% 1 10 - 109 54 / 100 = 54% 39 / 100 = 39% 40 / 100 = 40% 44 / 100 = 44% 2 20 - 119 49 / 100 = 49% 36 / 100 = 36% 47 / 100 = 47% 49 / 100 = 49% 3 30 - 129 42 / 100 = 42% 33 / 100 = 33% 54 / 100 = 54% 54 / 100 = 54% Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1148 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) Table 14-7. System Bandwidth Usage Example (continued) COUNTER NUMBER CYCLES COUNTING CALCULATED USAGE PORT 0 PORT 1 PORT 2 PORT 3 4 40 - 139 43 / 100 = 43% 26 / 100 = 26% 52 / 100 = 52% 52 / 100 = 52% 5 50 - 149 37 / 100 = 37% 28 / 100 = 28% 49 / 100 = 49% 48 / 100 = 48% 6 60 - 159 36 / 100 = 36% 25 / 100 = 25% 51 / 100 = 51% 46 / 100 = 46% 7 70 - 169 43 / 100 = 43% 23 / 100 = 23% 54 / 100 = 54% 40 / 100 = 40% 8 80 - 179 35 / 100 = 35% 18 / 100 = 18% 52 / 100 = 52% 42 / 100 = 42% 9 90 - 189 29 / 100 = 29% 17 / 100 = 17% 49 / 100 = 49% 43 / 100 = 43% 0 100 - 199 30 / 100 = 30% 17 / 100 = 17% 47 / 100 = 47% 34 / 100 = 34% 14.5.5 Understanding Port Bandwidth Hold-Off When the bandwidth used by a port exceeds its specified limit, that port is held off from subsequent arbitration decisions for a period of time known as the statistics reporting time. This causes a period of inactivity from that port, allowing the actual bandwidth used for that port to fall below the threshold. Since the bandwidth used is updated every ten cycles, the minimum hold off period for this system is ten cycles. This scheme is designed to constrain individual ports (especially ports programmed at higher priority) from overtaking all available bandwidth and locking out other ports. However, this can have its drawbacks. Consider a situation where only one port has been actively requesting and has therefore used all of its available bandwidth. The bandwidth hold-off will prevent additional requests from being accepted, even though no other ports are requesting. The core logic command queue will sit empty for several cycles while the hold-off is cleared. This is obviously wasted bandwidth and is detrimental to overall system performance. EMI has incorporated a bandwidth hold-off override function for such a situation in the axiY_bdw_ovflow parameters. A port will be allowed to exceed its allocated bandwidth when all of these conditions are true: * The bandwidth overflow parameter (axiY_bdw_ovflow) is set to `b1 for port Y. * No other port, whose bandwidth has not been exceeded, is requesting at the same priority level. * The command queue has less than the number of entries specified in the arb_cmd_q_threshold parameter. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1149 EMI Multi-Port Arbiter This last condition is a preventative measure to maintain latency requirements for ports programmed at higher priority. When a port is allowed to exceed bandwidth, it may fill the command queue with transactions. If this occurs, and a higher priority port starts requesting, then there will be no room in the command queue for the new requests. This means that the higher priority port will actually be held off for potentially several cycles. In this situation, even though the core logic bandwidth is being utilized well, the latency requirements of the higher priority port are not being met. The arb_cmd_q_threshold parameter is used to limit the bandwidth overflow and prevent this condition. It ensures that a certain number of slots remain available in the command queue for other ports. As a result, bandwidth overflow will be allowed as long as there are less than arb_cmd_q_threshold number of entries in the command queue. 14.5.6 Priority Round-Robin Arbitration Summary The MC priority round-robin arbitration system combines the concepts of round-robin operation, priority, bandwidth, and port bandwidth hold-off. The incoming commands are separated into priority groups based on the priority of the associated port for that type of command. Within each priority group, the Arbiter evaluates the requesting ports, the command queue, the priority of the requests, the bandwidth being used and the overflow option to determine the winner of the arbitration. The order of steps is as follows: 1. Is the core logic command queue full? * Yes: No further action is taken. * No: Review the ports. 2. For all requests at each priority level, use round-robin arbitration to select a request for that priority level. 3. For the highest priority port that is selected, has the bandwidth allocation for this port been exceeded? * No: This request wins arbitration. Move to step 6. * Yes: Check the bandwidth overflow status. 4. Is bandwidth overflow enabled? * No: Repeat step 3 for the next highest priority request. * Yes: Check the conditions for overflow. 5. Are the overflow conditions met? * No: Repeat step 3 for the next highest priority request. * Yes: This request wins arbitration. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1150 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 6. Once a request wins arbitration, it is processed into the command queue and the round-robin counter is updated to the next port in the circular queue. 14.5.7 Arbitration Examples To demonstrate arbitration behavior, consider the following system: * Four ports. * Ports 0 and 1 request only at priority 1. Ports 2 and 3 request only at priority 2. * All ports have bandwidth allocations of 100% and the bandwidth overflow bit is set to `b1. (Bandwidth will not affect arbitration.) An example with these settings is shown in Table 14-8. Note that priority 2 requests will only win arbitration when there are no priority 1 requests. Also note that each arbitration counter only increments, and always increments, when a request of that priority is processed. Cycle 5 demonstrates the always condition of counter incrementing: even though the arbitration was won by the other port of highest priority instead of the one in the counter, the counter still increments. Table 14-8. Priority Round-Robin without Bandwidth Consideration Cycle Current Arbitration Counter Ports Requesting Command Queue Full PG 1 PG 2 Port 0 Port 1 Port 2 Port 3 0 0 2 Y Y Y Y Yes 1 0 2 Y Y Y Y 2 1 2 -- Y Y 3 9 2 Y -- Y 4 1 2 -- -- 5 1 3 Y 6 0 3 7 0 8 Winner of Arbitration Next Arbitration Counter PG 1 PG 2 None 0 2 No P0 1 2 Y No P1 0 2 Y No P0 1 2 Y Y No P2 1 3 -- -- Y No P0 1 3 -- -- -- Y No P3 0 2 2 -- -- -- -- No None 0 2 0 2 -- -- Y Y Yes None 0 2 9 0 2 Y -- Y Y No P0 1 2 10 1 2 -- -- Y Y No P2 1 3 11 1 3 -- -- -- Y No P3 1 2 PG1 = Priority Group 1 and PG2 = Priority Group 2 The example was a very simplified case without considering bandwidth. However, in most cases, bandwidth will factor into the arbitration. Therefore, consider the same system as used in the previous example. However, now the allocated bandwidth is less than 100%. This system is shown in Table 14-9. The "Bandwidth Held Off" column i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1151 EMI Multi-Port Arbiter indicates if the bandwidth was held off for any port in that cycle. (Note cycles 3 and 11.) Even though the priority group 1 arbitration counter is pointing to port 0 in both cases, because the port is held off, port 0 does not win arbitration. A lower priority port, from priority group 2, wins arbitration instead. Table 14-9. Priority Round-Robin with Bandwidth Consideration Cycle Current Arbitration Counter Ports Requesting Command Queue Full Bandwidth Held Off PG 1 PG 2 0 0 2 Y Y Y Y Yes No 1 0 2 Y Y Y Y No 2 1 2 -- Y Y Y 3 0 2 Y -- Y 4 0 3 Y -- 5 1 3 Y -- 6 0 3 -- 7 0 2 8 0 9 Winner of Arbitration Port 0 Port 1 Port 2 Port 3 Next Arbitration Counter PG 1 PG 2 None 0 2 No P0 1 2 No No P1 0 2 Y No Yes, port 0 P2 0 3 -- Y No No P0 1 3 -- Y No No P0 0 3 -- -- Y No No P3 0 2 -- -- -- -- No No None 0 2 2 -- -- Y Y Yes No None 0 2 0 2 Y -- Y Y No No P0 1 2 10 1 2 Y -- Y Y No No P0 0 2 11 0 2 Y -- Y Y No Yes, port 0 P2 0 3 12 0 3 Y -- -- Y No No P0 1 3 13 1 3 -- -- -- Y No No P3 1 2 PG1 = Priority Group 1 and PG2 = Priority Group 2 14.5.8 Configuring and Programming for Priority Round-Robin Arbitration The priority round-robin arbitration scheme requires the use of the following programmable parameters: * axiY_r_priority, axiY_w_priority, axiY_bdw, axiY_current_bdw, axiY_bdw_ovflow * arb_cmd_q_threshold Since these parameters work together, there are trade-offs for the settings. Note: All of the arbitration parameters must be programmed prior to setting the start parameter to `b1. Any subsequent changes to the arbitration parameters may result in unpredictable system operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1152 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.5.8.1 Definition of the Statistics Window and the Number of Counters The statistics window sets the length of time used to measure port bandwidth and the number of counters determines the granularity of the measurement. The values set for both factors affect bandwidth measurement accuracy, gate area and arbitration latency. Accuracy can be added to the bandwidth measurements by increasing the number of counters and the length of time for a calculation. However, this results in a large increase in the gate area. Arbitration latency for a port is affected by how often bandwidth is updated. This is based on the amount of time over which each counter tabulates activity: the statistics window divided by the number of counters. As a general guideline, the statistics window should be just large enough that the bandwidth used for one complete transaction does not exceed the allocated bandwidth. In the EMI, the statistics window is defined as 100 cycles, and there are ten counters per port. 14.5.8.2 Command Priority, Port Bandwidth, and Bandwidth Overflow Command priority, bandwidth and bandwidth overflow play an important role in arbitration. Priority is the most important factor since commands are first sorted into priority groups based on their priority settings. In a multi-port system, all ports with tight latency requirements should be assigned higher priority values (lower numbers). Note that the priority of the command affects both arbitration and placement into the core logic command queue. As a result, it is more complicated to meet the latency requirements of all ports. For high priority commands or ports with low allocated bandwidths, bandwidth overflow may be useful. To mimic simple round-robin arbitration, program all ports to have the same priority and full bandwidth allocations. Note: The bandwidth parameter (axiY_bdw) is a seven-bit parameter. However, any programmed value greater than 0x64 is interpreted as 100%. 14.5.9 Command Queue with Placement Logic From the Arbiter, commands are routed to the command queue of the core logic. The command queue is fed using a placement algorithm. For more information on this algorithm, refer to section Core Command Queue with Placement Logic. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1153 Core Command Queue with Placement Logic 14.6 Core Command Queue with Placement Logic The core logic contains a command queue that accepts commands from the Arbiter. This command queue uses a placement algorithm to determine the order that commands will execute in the core logic. The placement logic follows many rules to determine where new commands should be inserted into the queue, relative to the contents of the command queue at the time. Placement is determined by considering address collisions, source collisions, data collisions, command types and priorities. In addition, the placement logic attempts to maximize efficiency of the core logic through command grouping and bank splitting. Once placed into the command queue, the relative order of commands is constant. Many of the rules used in placement may be individually enabled/disabled. In addition, the queue may be disabled by clearing the placement_en parameter, resulting in an in-line queue that services requests in the order they are received. If the placement_en parameter is cleared to `b0, the placement algorithm will be ignored. 14.6.1 Rules of the Placement Algorithm The factors affecting command placement all work together to identify where a new command fits into the execution order. They are listed in order of importance, as follows: * * * * * * Address collision/data coherency violation Source ID collision Write buffer collision Priority Bank splitting Read/write grouping 14.6.1.1 Address Collision/Data Coherency Violation The order in which read and write commands are processed in the memory controller is critical for proper system behavior. While reads and writes to different addresses are independent and may be re-ordered without affecting system performance, reads and writes that access the same address are significantly related. If the port requests a read after a write to the same address, then repositioning the read before the write would return the original data, not the changed data. Similarly, if the read was requested ahead i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1154 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) of the write but accidentally positioned after the write, then the read would return the new data, not the original data prior to being overwritten. These are significant data coherency mistakes. To avoid address collisions, reads or writes that access the same chip select, bank and row as a command already in the command queue will be inserted into the command queue after the original command, even if the new command is of a higher priority. This factor may be enabled/disabled through the addr_cmp_en parameter and should only be disabled if the system can guarantee coherency of reads and writes. 14.6.1.2 Source ID Collision Each port is assigned a specific source ID that is a combination of the port and thread ID information, and identifies the source uniquely. This allows the memory controller to map data from/to the correct source/destination. Note that a source ID does contain port identification information, which means that the rules for placement are dependent on the requesting port. There will not be source ID collisions between ports. In general, read commands from the same source ID will be placed in the command queue in order. Therefore, a read command with the same source ID as a read command already in the command queue will be processed after the original read command. All write commands from a port, even with different source IDs, will be executed in order. The behavior of commands of different types from the same source ID is dependent on the user configuration. For this Memory Controller, the placement of new read/write commands that collide in terms of source ID with existing entries in the command queue will only depend on other commands of the same type, not on different types. This means that, if there are no address conflicts, a read command could be executed ahead of a write command with the same source ID, and likewise a write command could be executed ahead of a read command with the same source ID. This feature will always be enabled. 14.6.1.3 Write Buffer Collision Incoming write requests in the command queue are allocated to one of the four write buffers of the core logic automatically based on availability. New write commands will be designated to any of the available buffers. However, back-to-back write requests from a particular source ID will be allocated to the same write buffer as the previous command. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1155 Core Command Queue with Placement Logic Since the core logic must pull data out of the buffers in the order it was stored, if a write command is linked to a buffer that is associated with another command in the queue, then the new command will be placed in the command queue after that command, regardless of priority. This feature will always be enabled. 14.6.1.4 Priority Priorities are used to distinguish important commands from less important commands. Each command is given a priority based on the command type through the programmable parameters axiY_r_priority and axiY_w_priority (where Y represents the port number). A priority value of 0 is the highest priority, and a priority value of 7 is the lowest priority. The placement algorithm will attempt to place higher priority commands ahead of lower priority commands, as long as they have no source ID, write buffer or address collisions. Higher priority commands will be placed lower in the command queue if they access the same address, are from the same requestor or use the same buffer as lower priority commands already in the command queue. 14.6.1.5 Bank Splitting Before accesses can be made to two different rows within the same bank, the first active row must be closed (pre-charged) and the new row must be opened (activated). Both activities require some timing overhead; therefore, for optimization, the placement queue will attempt to insert the new command into the command queue such that commands to other banks may execute during this timing overhead. The placement of the new commands will still follow priority, source ID, write buffer and address collision rules. The placement logic will also attempt to optimize the core logic by inserting a command to the same bank as an existing command in the command queue immediately after the original command. This reduces the overall timing overhead by potentially eliminating one pre-charging/activating cycle. This placement will only be possible if there are no priority, source ID, write buffer or address collisions or conflicts with other commands in the command queue. All bank splitting features are enabled through the bank_split_en parameter. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1156 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.6.1.6 Read/Write Grouping The memory suffers a small timing overhead when switching from read to write mode. For efficiency, the placement queue will attempt to place a new read command sequentially with other read commands in the command queue, or a new write command sequentially with other write commands in the command queue. Grouping will only be possible if no priority, source ID, write buffer or address collision rules are violated. This feature is enabled through the rw_same_en parameter. 14.6.2 Command Execution Order After Placement Once a command has been placed in the command queue, its order relative to the other commands in the queue at that time is fixed. While this provides simplicity in the algorithm, there are drawbacks. For this reason, the Memory Controller offers two options that affect commands once they have been placed in the command queue. 14.6.2.1 Command Aging Since commands can be inserted ahead of existing commands in the command queue, the situation could occur where a low priority command remains at the bottom of the queue indefinitely. To avoid such a lockout condition, aging counters have been included in the placement logic that measure the number of cycles that each command has been waiting. If command aging is enabled through the active_aging parameter, then if an aging counter hits its maximum, the priority of the associated command will be decremented by one (lower priority commands are executed first). This increases the likelihood that this command will move to the top of the command queue and be executed. Note that this command does not move relative positions in the command queue when it ages; the new priority will be considered when placing new commands into the command queue. Aging is controlled through a master aging counter and command aging counters associated with each command in the command queue. The age_count and command_age_count parameters hold the initial values for each of these counters, respectively. When the master counter counts down the age_count value, a signal is sent to the command aging counters to decrement. When the command aging counters have completely decremented, then the priority of the associated command is decremented by one number and the counter is reset. Therefore, a command does not age by a priority level until the total elapsed cycles has reached the product of the age_count and command_age_count values. The maximum number of cycles that any command can i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1157 Core Command Queue with Placement Logic wait in the command queue until reaching the top priority level is the product of the age_count value, the command_age_count value, and the number of priority levels in the system. 14.6.2.2 High-Priority Command Swapping Commands are assigned priority values to ensure that critical commands are executed more quickly in the memory controller than less important commands. Therefore, it is desirable that high-priority commands pass into the core logic as soon as possible. The placement algorithm takes priority into account when determining the order of commands, but still allows a scenario in which a high-priority command sits waiting at the top of the command queue while another command, perhaps of a lower priority, is in process. The high-priority command swapping feature allows this new high-priority command to be executed more quickly. If the user has enabled the swapping function through the swap_en parameter, then the entry at the top of the command queue will be compared with the current command in progress. If the command queue's top entry is of a higher priority (not the same priority), and it does not have an address, source ID or write buffer conflict with the current command being executed, then the original command will be interrupted. For this memory controller, an additional check is performed before a read command is interrupted. If the read command in progress and the read command at the top of the command queue is from the same port, then the executing command will only be interrupted if the swap_port_rw_same_en parameter is set to `b1. If this parameter is cleared to `b0, a read command from the same port as a read command in progress, even with a higher priority and without any conflicts, would remain at the top of the command queue while the current command completes. Note: All write commands from a single port, even with different source IDs, will be executed in order. Therefore, two write commands from the same port will never be swapped regardless of the settings of the swap_en and swap_port_rw_same_en parameters. Note: Priorities are assigned to read commands based on the settings in the axiY_r_priority parameters. While all read commands from a port are assigned the same priority when placed in the command queue, their priorities may change over time through command aging. While uncommon, it is possible that a higher-priority read command may be at the top of the command queue while a lower-priority read command is executing. The behavior of the system in this scenario is based on the value of the swap_en and swap_port_rw_same_en parameters. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1158 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) Refer to the following table for details: Table 14-10. Swapping Behavior Active Command Priority New Command Priority Originating Port for Commands Conflicts? Action Higher Lower Same or Different Yes or No Current command continues Lower Higher Same Yes Current command continues Lower Higher Same No Will swap IF swap_en = 1 and swap_port_rw_same_en = 1 Lower Higher Different No Will swap IF swap_en = 1 If the command is to be interrupted, it will be halted after completing the current burst, stored and placed at the top of the queue, and the new command will be executed. As long as the command queue is not full, new commands may continue to be inserted into the command queue based on the placement rules, even at the head of the queue ahead of the interrupted command. The top entry in the command queue will be executed next. Whenever the interrupted command is resumed, it will start from the point at which it was interrupted. Note that priority 0 commands will never be interrupted, so the user should set any commands that should not be interrupted to priority 0. If supported by the port interfaces, setting the swap_port_rw_same_en parameter will enable interleaving. 14.7 DDR PHY The DDR PHY encapsulates all functionality required to interface to external DDR DRAM devices into a single module. This module is used to control the off-chip data capture and synchronization logic for the read data. This module performs the following functions: * Contains all data registers used to launch data, address and control signals to the DDR memory and the memory controller. * Controls the off-chip data capture and synchronization logic for the read data. * Includes a DLL for timing. 14.7.1 High Level Block Diagram EMI uses a slice-based approach for the DDR PHY. Each slice manages a byte (8-bit) of data and it's corresponding dqs and dm signals. A high level block diagram of the PHY is provided below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1159 DDR PHY DFI EMI Core Logic Other I/Os Addr, Command & Misc I/O control DQS [1] DM [1] DQ [15:8] DQS [0] Data Slice 1 DM [0] Data Slice 0 DQ [7:0] DDR PHY I/O PADs External DRAM Device Figure 14-7. DDR PHY High-Level Block Diagram 14.7.2 DFI The interface between the EMI core logic and the DDR_PHY is named as "DFI". "D" stands for "DRAM Controller" while "FI" is alias to "PHY". 14.7.3 I/O Timing of Address and Command The figure below illustrates the I/O timing of Address and Command. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1160 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) emi_clk io_addr_out addr At the port of DDR_PHY fly time = PAD_Delay + Board_Delay At the DRAM device Pins emi_addr_o addr emi_clk_o DRAM device capture ADDR by the rise-edge of emi_clk_o Figure 14-8. I/O Address Timing The address and command signals including all DRAM interface signals except the DQ and DQS: clock-enable (CKE), chip-select, bank-address, row/cloumn_address, CASn, RASn, WEn, and so on. * The Address and command signals are latched out by the falling-edge of emi_clk; In another words, the rise-edge of emi_clk is center-aligned with the output Address and Command signals. * The fly-time is the signal's propagation time start from the DDR_PHY logic, go across the output I/O (PAD) of i.MX28, go through the signal trace on the board, then arrive the PIN of the DRAM device. * The DRAM device captures the Address and Command signals with the rising edge of emi_clk_o. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1161 DDR PHY 14.7.4 Data Slice Overview Data Slice read data write data Read Data Path io_dq_in [7:0] Write Data Path io_dq_out [7:0] io_dq_oe [7:0] delayed_dqs io_dqs_in Read Delay-Line Control Registers EMI Core Logic EMI_CLK Write Delay-Line Digital DLL & Delay Control clk_wr (delayed) io_dqs_out io_dqs_oe io_dm io_dm_oe I/O Control io_tsel io_tsel_dm Figure 14-9. DDR PHY Data Slice Each data-slice manages a byte (8-bit) of data and it's corresponding signals. The Read Data Path captures read data by latching it into read data buffers by both the posedge and negedge of delayed_dqs. Then, the read data is synchronized from delayed_dqs clock domain to emi_clk domain. The Write Data Path synchronizes write data and write data mask (the dm) from emi_clk domain to the dqs_out domain. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1162 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) The Digital DLL controls the delay values of read delay-line and write delay-line. It can be bypassed and switched to manual delay control mode. In manual delay control mode, the delay values of read/write delay-line can be programmed separately into the control registers. 14.7.5 Read Data Capture When reading, DDR (dual data rate) devices send a data strobe (DQS) signal coincident with the read data. The edges of this DQS strobe are aligned (edge-aligned) with the data output by the DDR devices. To latch read data into the EMI read data buffer, it is required that the latch clock edge is center-aligned with the data. Thus, a delayed version of the DQS strobe signal must be used to capture the data. Because the frequency of the DQS strobe signal is matched to the emi_clk, the delay is a relative number based on the period of the emi_clk. In the example shown below, the delay is set to approximately 25% of the emi_clk cycle. emi_clk io_dqs_in d0 io_dq_in d1 d2 d3 dqs delay = 1/4 cycle delayed_dqs capture data by the rise & fall edge of delayed_dqs Figure 14-10. Read Data Capture i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1163 DDR PHY 14.7.6 Synchronize Read Data From delayed_dqs to emi_clk Domain Read data is captured into data buffers by the delayed_dqs. It need to be synchronized to the emi_clk domain, then returned to EMI core logic. The following figure illustrates how the read data from an external DRAM device was captured and synchronized to EMI core logic. 1 2 3 4 emi_clk d0 io_dq_in d1 d2 d3 d4 d5 delayed_dqs d0 d1 data buffers @delayed_dqs clock domain d2 d3 d4 d5 1 Synchronize data to emi_clk doamin 2 d0,d1 3 4 d2,d3 d4,d5 phy_ctrl_reg_0 [26:24] dfi_rddata: data returned to core-logic @ emi_clk domain d0,d1 d2,d3 d4,d5 dfi_rddata_valid: phy_ctrl_reg_2 [3:0] Figure 14-11. Synchronized Read Data io_dq_in and io_dqs_in are not aligned with emi_clk in phase. Many factors affect the phase of io_dq/dqs_in, such as voltage, temperature, board layout, manufacturing process, and so on. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1164 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 1. Must capture the io_dq_in by delayed_dqs to meet the critical timing requirement in high frequency. 2. The data path width @emi_clk domain is twice the data path width @delayed_dqs domain. 3. The EMI core logic fetch read data by the rise-edge of emi_clk. 4. The EMI core logic fetch read data by two important signals: dfi_rddata and dfi_rddata_valid. 5. The user can program the timing position of dfi_rddata and dfi_rddata_valid by programmable registers phy_ctrl_reg_0[26:24] and phy_ctrl_reg_2[3:0]. The unit is one cycle of emi_clk. 6. In this example, read data d0,d1 getting valid before edge number 1 of emi_clk and is synchronized at edge 2 of emi_clk. Both the setup and hold time requirement are met which means that the read data could be fetched by core logic safely. Alternatively, read data can also be returned to core logic at edge number 1 of emi_clk, a cycle prior to the example. In this scenario, you need to set the value of register phy_ctrl_reg_0[26:24] and phy_ctrl_reg_2[3:0] to one number less. Then, the dfi_rddata and dfi_rddata_valid would become valid one cycle earlier. NOTE The benefit is that the read latency is shortened by one cycle, which helps increase the system performance. But, there's a timing risk on the setup time. If the io_dq/dqs_in comes a little late, a setup time violation can occur and the unexpected data is returned to core logic, which can cause a system crash. 14.7.7 Write Data Path The following figure illustrates the write data path. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1165 DDR PHY emi_clk clk_wr delay = 1/4 cycle 1 write data latch @emi_clk domain d0 d1 d2 d3 clk_wr d0 write data latch @clk_wr domain d2 d1 d3 clk_wr io_dq_out : write data muxed out mux_sel = clk_wr d0 d1 d2 d3 io_dqs_out DRAM device capture write data by the edge of io_dqs_out Figure 14-12. Write Data Path NOTE The marker 1 emphasizes that the setup time here for data d0 is only 1/4 cycle, that would be critical in timing. Write Data Path Low-Latency Option provides more details. The io_dqs_out and the emi_clk are edge-aligned in this EMI design. This help to meet the tDQSS timing requirement defined by DRAM device. The io_dqs_out and the io_dq_out are center-aligned which is required by the DRAM device. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1166 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.7.8 Write Data Path Low-Latency Option In the example of Figure 14-12, note the marker 1. It emphasizes that the setup time is only 1/4 cycle for data d0, which is critical in timing. This DDR_PHY provides two write data path options for the user : * The Standard Latency option. An extra latch at emi_clk domain is asserted into the write data path, right ahead of the latch at clk_wr domain (at the place of marker 1 in Figure 14-12). By this means, the asserted-latch and the latch at clk_wr are put back-to-back. The total delay in write data path is 1 + 1/4 cycle. It is safe in timing, but decreases performance by adding one cycle of latency. * The Low-Latency option. The asserted latch for standard-latency is bypassed. The total delay in write data path is 1/4 cycle. There is risk in the timing of the write data path, but it has higher performance than the standard-latency case. 14.7.9 Digital DLL and the Delay-Line Due to the asynchronous nature of the DRAM devices, the timing requirements for capturing and receiving data between the i.MX28 and the DRAM devices must be addressed. This EMI contains a circuit that, in conjunction with I/O cell circuitry, can be used to meet the timing requirements for DRAM devices. The delay compensation circuit was designed with the following features: * Programmable read strobe delay specified as a percentage of a clock cycle. * Programmable write data delays specified as percentages of a clock cycle. * Delay compensation circuit re-sync circuitry activated during refresh cycles to compensate for temperature and voltage drift. * Separate delay chains for each read DQS signal from the DRAM devices. The delay compensation circuitry relies on a master/slave approach. There is a master delay line which is used to determine how many delay elements constitute a complete cycle. This count is used, along with the programmable fractional delay settings, to determine the actual number of delay elements to program into the slave delay lines. The i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1167 DDR PHY master and slave delay lines are identical. This approach allows the memory controller to observe a clock and then delay other signals a fixed percentage of that clock. The DLL logic does not actively generate clock signals. The actual delay element for the delay lines is user-selectable. The following figure shows the block diagram for a digital DLL. dll phase detector emi_clk detector control logic Detector Delay-Line dll_lock Digital DLL Main Control Logic dll_lock_value programmable Write delay value delay-line control logic (select number of delay elements) clk_wr Write Delay-Line programmable Read delay value io_dqs_in delay-line control logic (select number of delay elements) delayed_dqs Read Delay-Line Figure 14-13. Digital DLL i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1168 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) The delay-line is comprised of 137 tiny delay-elements. The delay value of each delay element is almost the same. And the number of delay elements which is used to form a delay result is configurable. There are two modes for the delay-line control : * Auto configure mode This process begins by the "phase-detector". Once the phase-detector successfully complete the detection, it will raise the "dll_lock" signal and output "dll_lock_value" which indicates the delay of cone cycle. The number of elements that are needed to capture an entire clock cycle is then converted into an unsigned integer named encoder [7:0]. This integer is used as the dividend for the read and write delay parameters. The actual delay setting for the delay lines is calculated by multiplying the encoder [7:0] integer by the parameter settings for each delay line and then dividing by 128 and rounding. These values are then encoded into a one-hot counter and updated at initialization and at every refresh interval. * Bypass mode, or manual configure mode The phase-detector can be bypassed. The number of delay elements for read and write delay-line is programmed manually. NOTE In case the number of delay elements is fixed, the actual delay value (in nano-second) of a delay-line would change according to the environmental conditions, such as voltage, temperature, and so on. Using the "auto configure mode" help to eliminate the change of delay value because the reference delay itself also changes along with environmental conditions. 14.7.10 Configure output enable of I/O Control Some EMI I/Os require a control signal named "output enable". The I/O can drive signals out only when the "output enable" signal is active. Refer to the figure below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1169 DDR PHY d0 io_dq_out d1 d2 d3 io_dq_out_oen io_dqs_out io_dqs_out_oen Figure 14-14. EMI I/O Output Enable There are three kinds of output enable signals in this EMI design: * io_dq_out_oen output enable for write data. * io_dqm_oen output enable for write data mask. Please configure it exactly the same as io_dq_out_oen. * io_dqs_oen output enable for write data strobe. The suffix "_oen" means the output enable signal is active low. The start time and the end time of a output enable signal can be configured separately. The start time and the end time can be adjusted by 1/4 clock cycle in unit. To meet the timing requirement of the I/O circuits, the start time of each output enable must be prior to it's corresponding output signal, and, the end time must be later than it's corresponding signal. In another word, the output enable signal must be "wider" than the output signal. The margin at start time is named "pre-amble" and the margin at end time is named "post-amble". In the example of Figure 14-14, pre-amble = 1/2 cycle while post-amble = 1/4 cycle. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1170 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8 Programmable Registers EMI Register Format Summary HW_DRAM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800E_0000 DRAM Control Register 00 (HW_DRAM_CTL00) 32 R/W 0000_0000h 14.8.1/1179 800E_0004 AXI Monitor Control (HW_DRAM_CTL01) 32 R/W 0000_0000h 14.8.2/1180 800E_0008 DRAM Control Register 02 (HW_DRAM_CTL02) 32 R/W 0000_0000h 14.8.3/1181 800E_000C DRAM Control Register 03 (HW_DRAM_CTL03) 32 R/W 0000_0000h 14.8.4/1181 800E_0010 DRAM Control Register 04 (HW_DRAM_CTL04) 32 R/W 0000_0000h 14.8.5/1182 800E_0014 DRAM Control Register 05 (HW_DRAM_CTL05) 32 R/W 0000_0000h 14.8.6/1182 800E_0018 DRAM Control Register 06 (HW_DRAM_CTL06) 32 R/W 0000_0000h 14.8.7/1183 800E_001C DRAM Control Register 07 (HW_DRAM_CTL07) 32 R/W 0000_0000h 14.8.8/1183 800E_0020 DRAM Control Register 08 (HW_DRAM_CTL08) 32 R 0000_0010h 14.8.9/1184 800E_0024 DRAM Control Register 09 (HW_DRAM_CTL09) 32 R 0000_0000h 14.8.10/ 1186 800E_0028 AXI0 Debug 0 (HW_DRAM_CTL10) 32 R 0000_0000h 14.8.11/ 1186 800E_002C AXI0 Debug 1 (HW_DRAM_CTL11) 32 R 0000_0000h 14.8.12/ 1187 800E_0030 AXI1 Debug 0 (HW_DRAM_CTL12) 32 R 0000_0000h 14.8.13/ 1187 800E_0034 AXI1 Debug 1 (HW_DRAM_CTL13) 32 R 0000_0000h 14.8.14/ 1188 800E_0038 AXI2 Debug 0 (HW_DRAM_CTL14) 32 R 0000_0000h 14.8.15/ 1188 800E_003C AXI2 Debug 1 (HW_DRAM_CTL15) 32 R 0000_0000h 14.8.16/ 1189 800E_0040 DRAM Control Register 16 (HW_DRAM_CTL16) 32 R/W 0000_0000h 14.8.17/ 1190 800E_0044 DRAM Control Register 17 (HW_DRAM_CTL17) 32 R/W 0000_0000h 14.8.18/ 1192 800E_0054 DRAM Control Register 21 (HW_DRAM_CTL21) 32 R/W 0000_0000h 14.8.19/ 1194 800E_0058 DRAM Control Register 22 (HW_DRAM_CTL22) 32 R/W 0000_0000h 14.8.20/ 1195 800E_005C DRAM Control Register 23 (HW_DRAM_CTL23) 32 R/W 0000_0000h 14.8.21/ 1197 800E_0060 32 R/W 0000_0000h 14.8.22/ 1197 DRAM Control Register 24 (HW_DRAM_CTL24) Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1171 Programmable Registers HW_DRAM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800E_0064 DRAM Control Register 25 (HW_DRAM_CTL25) 32 R/W 0000_0000h 14.8.23/ 1198 800E_0068 DRAM Control Register 26 (HW_DRAM_CTL26) 32 R/W 0000_0000h 14.8.24/ 1199 800E_006C DRAM Control Register 27 (HW_DRAM_CTL27) 32 R/W 0000_0000h 14.8.25/ 1201 800E_0070 DRAM Control Register 28 (HW_DRAM_CTL28) 32 R/W 0000_0000h 14.8.26/ 1203 800E_0074 DRAM Control Register 29 (HW_DRAM_CTL29) 32 R/W 0000_0000h 14.8.27/ 1204 800E_0078 DRAM Control Register 30 (HW_DRAM_CTL30) 32 R 0004_0F0Ch 14.8.28/ 1205 800E_007C DRAM Control Register 31 (HW_DRAM_CTL31) 32 R/W 0000_0000h 14.8.29/ 1207 800E_0080 DRAM Control Register 32 (HW_DRAM_CTL32) 32 R/W 0000_0000h 14.8.30/ 1209 800E_0084 DRAM Control Register 33 (HW_DRAM_CTL33) 32 R/W 0000_0000h 14.8.31/ 1210 800E_0088 DRAM Control Register 34 (HW_DRAM_CTL34) 32 R/W 0000_0000h 14.8.32/ 1212 800E_008C DRAM Control Register 35 (HW_DRAM_CTL35) 32 R/W 0000_0000h 14.8.33/ 1214 800E_0090 DRAM Control Register 36 (HW_DRAM_CTL36) 32 R/W 0000_0000h 14.8.34/ 1216 800E_0094 DRAM Control Register 37 (HW_DRAM_CTL37) 32 R/W 0000_0000h 14.8.35/ 1217 800E_0098 DRAM Control Register 38 (HW_DRAM_CTL38) 32 R/W 0000_0000h 14.8.36/ 1219 800E_009C DRAM Control Register 39 (HW_DRAM_CTL39) 32 R/W 0000_0000h 14.8.37/ 1220 800E_00A0 DRAM Control Register 40 (HW_DRAM_CTL40) 32 R/W 0000_0000h 14.8.38/ 1221 800E_00A4 DRAM Control Register 41 (HW_DRAM_CTL41) 32 R/W 0000_0000h 14.8.39/ 1221 800E_00A8 DRAM Control Register 42 (HW_DRAM_CTL42) 32 R/W 0000_0000h 14.8.40/ 1222 800E_00AC DRAM Control Register 43 (HW_DRAM_CTL43) 32 R/W 0000_0000h 14.8.41/ 1223 800E_00B0 DRAM Control Register 44 (HW_DRAM_CTL44) 32 R/W 0000_0000h 14.8.42/ 1223 800E_00B4 DRAM Control Register 45 (HW_DRAM_CTL45) 32 R/W 0000_0000h 14.8.43/ 1224 800E_00C0 DRAM Control Register 48 (HW_DRAM_CTL48) 32 R/W 0000_0000h 14.8.44/ 1225 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1172 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800E_00C4 DRAM Control Register 49 (HW_DRAM_CTL49) 32 R/W 0000_0000h 14.8.45/ 1226 800E_00C8 DRAM Control Register 50 (HW_DRAM_CTL50) 32 R/W 0000_0000h 14.8.46/ 1228 800E_00CC DRAM Control Register 51 (HW_DRAM_CTL51) 32 R/W 0000_0000h 14.8.47/ 1229 800E_00D0 DRAM Control Register 52 (HW_DRAM_CTL52) 32 R/W 0000_0000h 14.8.48/ 1231 800E_00D4 DRAM Control Register 53 (HW_DRAM_CTL53) 32 R/W 0000_0000h 14.8.49/ 1232 800E_00D8 DRAM Control Register 54 (HW_DRAM_CTL54) 32 R/W 0000_0000h 14.8.50/ 1234 800E_00DC DRAM Control Register 55 (HW_DRAM_CTL55) 32 R/W 0000_0000h 14.8.51/ 1235 800E_00E0 DRAM Control Register 56 (HW_DRAM_CTL56) 32 R/W 0000_0000h 14.8.52/ 1236 800E_00E8 DRAM Control Register 58 (HW_DRAM_CTL58) 32 R/W 0000_0000h 14.8.53/ 1237 800E_00EC DRAM Control Register 59 (HW_DRAM_CTL59) 32 R 0000_0000h 14.8.54/ 1238 800E_00F0 DRAM Control Register 60 (HW_DRAM_CTL60) 32 R 0000_0000h 14.8.55/ 1238 800E_00F4 DRAM Control Register 61 (HW_DRAM_CTL61) 32 R 0000_0000h 14.8.56/ 1239 800E_00F8 DRAM Control Register 62 (HW_DRAM_CTL62) 32 R 0000_0000h 14.8.57/ 1240 800E_00FC DRAM Control Register 63 (HW_DRAM_CTL63) 32 R 0000_0000h 14.8.58/ 1241 800E_0100 DRAM Control Register 64 (HW_DRAM_CTL64) 32 R 0000_0000h 14.8.59/ 1241 800E_0104 DRAM Control Register 65 (HW_DRAM_CTL65) 32 R 0000_0000h 14.8.60/ 1242 800E_0108 DRAM Control Register 66 (HW_DRAM_CTL66) 32 R/W 0004_0000h 14.8.61/ 1243 800E_010C DRAM Control Register 67 (HW_DRAM_CTL67) 32 R/W 0000_0000h 14.8.62/ 1244 800E_0110 DRAM Control Register 68 (HW_DRAM_CTL68) 32 R/W 0000_0000h 14.8.63/ 1245 800E_0114 DRAM Control Register 69 (HW_DRAM_CTL69) 32 R/W 0000_0000h 14.8.64/ 1246 800E_0118 DRAM Control Register 70 (HW_DRAM_CTL70) 32 R/W 0000_0000h 14.8.65/ 1247 800E_011C DRAM Control Register 71 (HW_DRAM_CTL71) 32 R/W 0000_0000h 14.8.66/ 1248 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1173 Programmable Registers HW_DRAM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800E_0120 DRAM Control Register 72 (HW_DRAM_CTL72) 32 R/W 0000_0000h 14.8.67/ 1250 800E_0124 DRAM Control Register 73 (HW_DRAM_CTL73) 32 R/W 0000_0000h 14.8.68/ 1250 800E_0128 DRAM Control Register 74 (HW_DRAM_CTL74) 32 R/W 0000_0000h 14.8.69/ 1251 800E_012C DRAM Control Register 75 (HW_DRAM_CTL75) 32 R/W 0000_0000h 14.8.70/ 1251 800E_0130 DRAM Control Register 76 (HW_DRAM_CTL76) 32 R/W 0000_0000h 14.8.71/ 1252 800E_0134 DRAM Control Register 77 (HW_DRAM_CTL77) 32 R/W 0000_0000h 14.8.72/ 1253 800E_0138 DRAM Control Register 78 (HW_DRAM_CTL78) 32 R/W 0000_0000h 14.8.73/ 1253 800E_013C DRAM Control Register 79 (HW_DRAM_CTL79) 32 R/W 0000_0000h 14.8.74/ 1254 800E_0140 DRAM Control Register 80 (HW_DRAM_CTL80) 32 R/W 0000_0000h 14.8.75/ 1255 800E_0144 DRAM Control Register 81 (HW_DRAM_CTL81) 32 R/W 0000_0000h 14.8.76/ 1255 800E_0148 DRAM Control Register 82 (HW_DRAM_CTL82) 32 R/W 0000_0000h 14.8.77/ 1256 800E_014C DRAM Control Register 83 (HW_DRAM_CTL83) 32 R/W 0000_0000h 14.8.78/ 1257 800E_0150 DRAM Control Register 84 (HW_DRAM_CTL84) 32 R/W 0000_0000h 14.8.79/ 1259 800E_0154 DRAM Control Register 85 (HW_DRAM_CTL85) 32 R/W 0000_0000h 14.8.80/ 1260 800E_0158 DRAM Control Register 86 (HW_DRAM_CTL86) 32 R 0000_2040h 14.8.81/ 1261 800E_015C DRAM Control Register 87 (HW_DRAM_CTL87) 32 R/W 0000_0000h 14.8.82/ 1262 800E_0160 DRAM Control Register 88 (HW_DRAM_CTL88) 32 R/W 0000_0000h 14.8.83/ 1263 800E_0164 DRAM Control Register 89 (HW_DRAM_CTL89) 32 R/W 0000_0000h 14.8.84/ 1263 800E_0168 DRAM Control Register 90 (HW_DRAM_CTL90) 32 R/W 0000_0000h 14.8.85/ 1264 800E_016C DRAM Control Register 91 (HW_DRAM_CTL91) 32 R/W 0000_0000h 14.8.86/ 1265 800E_0170 DRAM Control Register 92 (HW_DRAM_CTL92) 32 R/W 0000_0000h 14.8.87/ 1265 800E_0174 DRAM Control Register 93 (HW_DRAM_CTL93) 32 R/W 0000_0000h 14.8.88/ 1266 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1174 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page DRAM Control Register 94 (HW_DRAM_CTL94) 32 R/W 0000_0000h 14.8.89/ 1267 800E_017C DRAM Control Register 95 (HW_DRAM_CTL95) 32 R 0000_0000h 14.8.90/ 1267 800E_0180 DRAM Control Register 96 (HW_DRAM_CTL96) 32 R 0000_0000h 14.8.91/ 1268 800E_0184 DRAM Control Register 97 (HW_DRAM_CTL97) 32 R 0000_0000h 14.8.92/ 1268 800E_0188 DRAM Control Register 98 (HW_DRAM_CTL98) 32 R 0000_0000h 14.8.93/ 1269 800E_018C DRAM Control Register 99 (HW_DRAM_CTL99) 32 R 0000_0000h 14.8.94/ 1270 800E_0190 DRAM Control Register 100 (HW_DRAM_CTL100) 32 R 0000_0000h 14.8.95/ 1271 800E_0194 DRAM Control Register 101 (HW_DRAM_CTL101) 32 R 0000_0000h 14.8.96/ 1272 800E_0198 DRAM Control Register 102 (HW_DRAM_CTL102) 32 R 0000_0000h 14.8.97/ 1273 800E_019C DRAM Control Register 103 (HW_DRAM_CTL103) 32 R 0000_0000h 14.8.98/ 1274 800E_01A0 DRAM Control Register 104 (HW_DRAM_CTL104) 32 R 0000_0000h 14.8.99/ 1274 800E_01A4 DRAM Control Register 105 (HW_DRAM_CTL105) 32 R 0000_0000h 14.8.100/ 1275 800E_01A8 DRAM Control Register 106 (HW_DRAM_CTL106) 32 R 0000_0000h 14.8.101/ 1275 800E_01AC DRAM Control Register 107 (HW_DRAM_CTL107) 32 R 0000_0000h 14.8.102/ 1276 800E_01B0 DRAM Control Register 108 (HW_DRAM_CTL108) 32 R 0000_0000h 14.8.103/ 1276 800E_01B4 DRAM Control Register 109 (HW_DRAM_CTL109) 32 R 0000_0000h 14.8.104/ 1277 800E_01B8 DRAM Control Register 110 (HW_DRAM_CTL110) 32 R 0000_0000h 14.8.105/ 1277 800E_01BC DRAM Control Register 111 (HW_DRAM_CTL111) 32 R 0000_0000h 14.8.106/ 1278 800E_01C0 DRAM Control Register 112 (HW_DRAM_CTL112) 32 R 0000_0000h 14.8.107/ 1278 800E_01C4 DRAM Control Register 113 (HW_DRAM_CTL113) 32 R 0000_0000h 14.8.108/ 1279 800E_01C8 DRAM Control Register 114 (HW_DRAM_CTL114) 32 R 0000_0000h 14.8.109/ 1279 800E_01CC DRAM Control Register 115 (HW_DRAM_CTL115) 32 R 0000_0000h 14.8.110/ 1280 800E_0178 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1175 Programmable Registers HW_DRAM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800E_01D0 DRAM Control Register 116 (HW_DRAM_CTL116) 32 R 0000_0000h 14.8.111/ 1280 800E_01D4 DRAM Control Register 117 (HW_DRAM_CTL117) 32 R 0000_0000h 14.8.112/ 1281 800E_01D8 DRAM Control Register 118 (HW_DRAM_CTL118) 32 R 0000_0000h 14.8.113/ 1281 800E_01DC DRAM Control Register 119 (HW_DRAM_CTL119) 32 R 0000_0000h 14.8.114/ 1282 800E_01E0 DRAM Control Register 120 (HW_DRAM_CTL120) 32 R 0000_0000h 14.8.115/ 1282 800E_01E4 DRAM Control Register 121 (HW_DRAM_CTL121) 32 R 0000_0000h 14.8.116/ 1283 800E_01E8 DRAM Control Register 122 (HW_DRAM_CTL122) 32 R 0000_0000h 14.8.117/ 1283 800E_01EC DRAM Control Register 123 (HW_DRAM_CTL123) 32 R 0000_0000h 14.8.118/ 1284 800E_01F0 DRAM Control Register 124 (HW_DRAM_CTL124) 32 R 0000_0000h 14.8.119/ 1284 800E_01F4 DRAM Control Register 125 (HW_DRAM_CTL125) 32 R 0000_0000h 14.8.120/ 1285 800E_01F8 DRAM Control Register 126 (HW_DRAM_CTL126) 32 R 0000_0000h 14.8.121/ 1285 800E_01FC DRAM Control Register 127 (HW_DRAM_CTL127) 32 R 0000_0000h 14.8.122/ 1286 800E_0200 DRAM Control Register 128 (HW_DRAM_CTL128) 32 R 0000_0000h 14.8.123/ 1286 800E_0204 DRAM Control Register 129 (HW_DRAM_CTL129) 32 R 0000_0000h 14.8.124/ 1287 800E_0208 DRAM Control Register 130 (HW_DRAM_CTL130) 32 R 0000_0000h 14.8.125/ 1287 800E_020C DRAM Control Register 131 (HW_DRAM_CTL131) 32 R 0000_0000h 14.8.126/ 1288 800E_0210 DRAM Control Register 132 (HW_DRAM_CTL132) 32 R 0000_0000h 14.8.127/ 1288 800E_0214 DRAM Control Register 133 (HW_DRAM_CTL133) 32 R 0000_0000h 14.8.128/ 1289 800E_0218 DRAM Control Register 134 (HW_DRAM_CTL134) 32 R 0000_0000h 14.8.129/ 1289 800E_021C DRAM Control Register 135 (HW_DRAM_CTL135) 32 R 0000_0000h 14.8.130/ 1290 800E_0220 DRAM Control Register 136 (HW_DRAM_CTL136) 32 R 0000_0000h 14.8.131/ 1290 800E_0224 DRAM Control Register 137 (HW_DRAM_CTL137) 32 R 0000_0000h 14.8.132/ 1291 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1176 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page DRAM Control Register 138 (HW_DRAM_CTL138) 32 R 0000_0000h 14.8.133/ 1291 800E_022C DRAM Control Register 139 (HW_DRAM_CTL139) 32 R 0000_0000h 14.8.134/ 1292 800E_0230 DRAM Control Register 140 (HW_DRAM_CTL140) 32 R 0000_0000h 14.8.135/ 1292 800E_0234 DRAM Control Register 141 (HW_DRAM_CTL141) 32 R 0000_0000h 14.8.136/ 1293 800E_0238 DRAM Control Register 142 (HW_DRAM_CTL142) 32 R 0000_0000h 14.8.137/ 1293 800E_023C DRAM Control Register 143 (HW_DRAM_CTL143) 32 R 0000_0000h 14.8.138/ 1294 800E_0240 DRAM Control Register 144 (HW_DRAM_CTL144) 32 R 0000_0000h 14.8.139/ 1294 800E_0244 DRAM Control Register 145 (HW_DRAM_CTL145) 32 R 0000_0000h 14.8.140/ 1295 800E_0248 DRAM Control Register 146 (HW_DRAM_CTL146) 32 R 0000_0000h 14.8.141/ 1295 800E_024C DRAM Control Register 147 (HW_DRAM_CTL147) 32 R 0000_0000h 14.8.142/ 1296 800E_0250 DRAM Control Register 148 (HW_DRAM_CTL148) 32 R 0000_0000h 14.8.143/ 1296 800E_0254 DRAM Control Register 149 (HW_DRAM_CTL149) 32 R 0000_0000h 14.8.144/ 1297 800E_0258 DRAM Control Register 150 (HW_DRAM_CTL150) 32 R 0000_0000h 14.8.145/ 1297 800E_025C DRAM Control Register 151 (HW_DRAM_CTL151) 32 R 0000_0000h 14.8.146/ 1298 800E_0260 DRAM Control Register 152 (HW_DRAM_CTL152) 32 R 0000_0000h 14.8.147/ 1298 800E_0264 DRAM Control Register 153 (HW_DRAM_CTL153) 32 R 0000_0000h 14.8.148/ 1299 800E_0268 DRAM Control Register 154 (HW_DRAM_CTL154) 32 R 0000_0000h 14.8.149/ 1299 800E_026C DRAM Control Register 155 (HW_DRAM_CTL155) 32 R 0000_0000h 14.8.150/ 1300 800E_0270 DRAM Control Register 156 (HW_DRAM_CTL156) 32 R 0000_0000h 14.8.151/ 1300 800E_0274 DRAM Control Register 157 (HW_DRAM_CTL157) 32 R 0000_0000h 14.8.152/ 1301 800E_0278 DRAM Control Register 158 (HW_DRAM_CTL158) 32 R 0000_0000h 14.8.153/ 1301 800E_027C DRAM Control Register 159 (HW_DRAM_CTL159) 32 R 0000_0000h 14.8.154/ 1302 800E_0228 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1177 Programmable Registers HW_DRAM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800E_0280 DRAM Control Register 160 (HW_DRAM_CTL160) 32 R 0000_0000h 14.8.155/ 1302 800E_0284 DRAM Control Register 161 (HW_DRAM_CTL161) 32 R 0000_0000h 14.8.156/ 1303 800E_0288 DRAM Control Register 162 (HW_DRAM_CTL162) 32 R/W 0000_0000h 14.8.157/ 1303 800E_028C DRAM Control Register 163 (HW_DRAM_CTL163) 32 R/W 0000_0000h 14.8.158/ 1304 800E_0290 DRAM Control Register 164 (HW_DRAM_CTL164) 32 R/W 0000_0000h 14.8.159/ 1305 800E_02AC DRAM Control Register 171 (HW_DRAM_CTL171) 32 R/W 0000_0000h 14.8.160/ 1306 800E_02B0 DRAM Control Register 172 (HW_DRAM_CTL172) 32 R/W 0000_0000h 14.8.161/ 1308 800E_02B4 DRAM Control Register 173 (HW_DRAM_CTL173) 32 R/W 0000_0000h 14.8.162/ 1309 800E_02B8 DRAM Control Register 174 (HW_DRAM_CTL174) 32 R/W 0000_0000h 14.8.163/ 1310 800E_02BC DRAM Control Register 175 (HW_DRAM_CTL175) 32 R/W 0000_0000h 14.8.164/ 1311 800E_02C0 DRAM Control Register 176 (HW_DRAM_CTL176) 32 R/W 0000_0000h 14.8.165/ 1313 800E_02C4 DRAM Control Register 177 (HW_DRAM_CTL177) 32 R/W 0000_0000h 14.8.166/ 1314 800E_02C8 DRAM Control Register 178 (HW_DRAM_CTL178) 32 R/W 0000_0000h 14.8.167/ 1315 800E_02CC DRAM Control Register 179 (HW_DRAM_CTL179) 32 R/W 0000_0000h 14.8.168/ 1316 800E_02D0 DRAM Control Register 180 (HW_DRAM_CTL180) 32 R/W 0000_0000h 14.8.169/ 1317 800E_02D4 DRAM Control Register 181 (HW_DRAM_CTL181) 32 R/W 0000_0000h 14.8.170/ 1318 800E_02D8 DRAM Control Register 182 (HW_DRAM_CTL182) 32 R/W 0000_0000h 14.8.171/ 1320 800E_02DC DRAM Control Register 183 (HW_DRAM_CTL183) 32 R/W 0000_0000h 14.8.172/ 1322 800E_02E0 DRAM Control Register 184 (HW_DRAM_CTL184) 32 R/W 0000_0000h 14.8.173/ 1324 800E_02E4 DRAM Control Register 185 (HW_DRAM_CTL185) 32 R/W 0000_0000h 14.8.174/ 1326 800E_02E8 DRAM Control Register 186 (HW_DRAM_CTL186) 32 R/W 0000_0000h 14.8.175/ 1328 800E_02EC DRAM Control Register 187 (HW_DRAM_CTL187) 32 R/W 0000_0000h 14.8.176/ 1330 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1178 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 800E_02F0 DRAM Control Register 188 (HW_DRAM_CTL188) 32 R/W 0000_0000h 14.8.177/ 1332 800E_02F4 DRAM Control Register 189 (HW_DRAM_CTL189) 32 R/W 0000_0000h 14.8.178/ 1333 14.8.1 DRAM Control Register 00 (HW_DRAM_CTL00) This is a DRAM configuration register. Address: 800E_0000h base + 0h offset = 800E_0000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R USER_DEF_REG_0_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRESP_TIMING Bit 0 SREFRESH_ ENTER Reset CKE_SELECT W 0 0 0 0 0 0 0 0 R USER_DEF_REG_0_1 W Reset 0 0 0 0 0 0 0 0 HW_DRAM_CTL00 field descriptions Field 31-3 USER_DEF_ REG_0_1 Description User-defined output register 0. Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges from 0 to 7) 2 CKE_SELECT This bit is not used in i.MX28. Always write zero to this bit. 1 SREFRESH_ ENTER Initiates a self-refresh to the DRAMs. This pin updates the srefresh parameter. 0 This bit changes when the BRESP is issued over the AXI bus interface for bufferable AXI write BRESP_TIMING transactions. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1179 Programmable Registers HW_DRAM_CTL00 field descriptions (continued) Field Description 0x0 0x1 BUFFERABLE -- BRESP is returned when command and data are received by the AXI port. SEMI_BUFFERABLE -- BRESP is returned when command is accepted into the internal EMI command queue. 14.8.2 AXI Monitor Control (HW_DRAM_CTL01) This is a DRAM configuration register. Address: 800E_0000h base + 4h offset = 800E_0004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R USER_DEF_REG_1 W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MON_DBG_ STB Reset R USER_DEF_REG_1 W Reset 0 0 0 0 0 0 0 0 SLVERR 0 0 0 MON_DISABLE 0 0 0 0 0 HW_DRAM_CTL01 field descriptions Field 31-9 USER_DEF_ REG_1 Description User-defined output register 1. Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges from 0 to 7) 8 Setting this bit to a logic 1 will initiate sampling the state of each AXI interface monitor. The diagnostic MON_DBG_STB information available in the debug registers is valid only after this bit is set to a logic one. To take a subsequent snapshot of the state of each AXI monitor, set this bit low, and then high again. 7-4 SLVERR Setting this bit will cause all AXI transactions to be processed with a slave error when the respective monitor is enabled. MON_DISABLE Setting this bit will disable the AXI monitors. None of the EMI AXI error conditions will be checked and all AXI traffic will proceed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1180 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.3 DRAM Control Register 02 (HW_DRAM_CTL02) This is a DRAM configuration register. Address: 800E_0000h base + 8h offset = 800E_0008h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER_DEF_REG_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL02 field descriptions Field Description USER_DEF_ REG_2 User-defined output register 2. Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges from 0 to 7) 14.8.4 DRAM Control Register 03 (HW_DRAM_CTL03) This is a DRAM configuration register. Address: 800E_0000h base + Ch offset = 800E_000Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER_DEF_REG_3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL03 field descriptions Field USER_DEF_ REG_3 Description User-defined output register 3. Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges from 0 to 7) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1181 Programmable Registers 14.8.5 DRAM Control Register 04 (HW_DRAM_CTL04) This is a DRAM configuration register. Address: 800E_0000h base + 10h offset = 800E_0010h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER_DEF_REG_4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL04 field descriptions Field Description USER_DEF_ REG_4 User-defined output register 4. Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges from 0 to 7) 14.8.6 DRAM Control Register 05 (HW_DRAM_CTL05) This is a DRAM configuration register. Address: 800E_0000h base + 14h offset = 800E_0014h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER_DEF_REG_5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL05 field descriptions Field USER_DEF_ REG_5 Description User-defined output register 5. Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges from 0 to 7) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1182 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.7 DRAM Control Register 06 (HW_DRAM_CTL06) This is a DRAM configuration register. Address: 800E_0000h base + 18h offset = 800E_0018h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER_DEF_REG_6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL06 field descriptions Field Description USER_DEF_ REG_6 User-defined output register 6. Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges from 0 to 7) 14.8.8 DRAM Control Register 07 (HW_DRAM_CTL07) This is a DRAM configuration register. Address: 800E_0000h base + 1Ch offset = 800E_001Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER_DEF_REG_7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL07 field descriptions Field USER_DEF_ REG_7 Description User-defined output register 7. Holds user-defined values that will be available as output signals param_user_def_reg_X (where X ranges from 0 to 7) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1183 Programmable Registers 14.8.9 DRAM Control Register 08 (HW_DRAM_CTL08) This is a DRAM configuration register. Address: 800E_0000h base + 20h offset = 800E_0020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 USER_DEF_REG_RO_0 R W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1184 Freescale Semiconductor, Inc. 11 10 9 USER_DEF_REG_RO_0 R 8 7 6 5 4 CKE_STATUS 12 SREFRESH_ACK 13 Q_ALMOST_FULL 14 REFRESH_IN_PROCESS 15 Bit CONTROLLER_BUSY Chapter 14 External Memory Interface (EMI) 0 0 0 0 1 3 2 1 0 COMMAND_ACCEPTED W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL08 field descriptions Field 31-9 USER_DEF_ REG_RO_0 Description User-defined input register 0. Holds the value driven to the MC by the PHY on the signals param_user_def_reg_ro_X (where X ranges from 0 to 7) at the EMI core level. There are a total of 8 user-defined input registers. 8 Status signal from the EMI. This will only be low when the EMI is not reading data, writing data or CONTROLLER_ processing a command. BUSY 7 REFRESH_IN_ PROCESS Active-high signal that indicates that the EMI is executing a refresh command. This signals is asserted when a refresh command is sent t othe DRAM devices and the remains asserted until the refresh command has completed. 6 Q_ALMOST_ FULL Indicates that the queue has reached the value set in the q_fullness parameter in the controller. 5 SREFRESH_ ACK Acknowledge signal that indicates that the memory devices are in self-refresh mode. This signal will only be asserted if the DRAMs have been placed into self-refresh mode through the assertion of the srefresh_enter signal and if the signal is still held high until the memory enters self-refresh mode. 4 CKE_STATUS Indicates the memory devices are in either their self-refresh or power-down mode. This signals is the status of the control_cke signal inside the EMI, but may be delayed through the cke_delay paramter in the contoller to reflect the inverted CKE status on the memory bus. NOTE: this parameter is inverted with respect to the logic state on the external CKE pin. COMMAND_ ACCEPTED Indicates when bus interface commands are accepted. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1185 Programmable Registers 14.8.10 DRAM Control Register 09 (HW_DRAM_CTL09) This is a DRAM configuration register. Address: 800E_0000h base + 24h offset = 800E_0024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 USER_DEF_REG_RO_1 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL09 field descriptions Field Description USER_DEF_ REG_RO_1 User-defined input register 1. Holds the value driven to the MC by the PHY on the signals param_user_def_reg_ro_X (where X ranges from 0 to 7) at the EMI core level. There are a total of 8 user-defined input registers. 14.8.11 AXI0 Debug 0 (HW_DRAM_CTL10) AXI0 Monitor Debug register 0. Address: 800E_0000h base + 28h offset = 800E_0028h Bit 31 30 29 28 27 26 25 24 23 22 RSVD R 21 20 19 18 17 16 15 14 READ_CNT 13 12 11 10 9 8 7 6 WRESP_CNT 5 4 3 2 1 0 0 0 WDATA_CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL10 field descriptions Field 31-24 RSVD 23-16 READ_CNT Description Reserved. This field will indicate how many read commands have been accepted in which their respective data beats have not been returned over the data bus. 15-8 WRESP_CNT This field will indicate how many write commands have been accepted in which their respective RESP signaling has not completed. WDATA_CNT This field will indicate how many write commands have been accepted in which their respective data beats have not been transferred over the data bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1186 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.12 AXI0 Debug 1 (HW_DRAM_CTL11) AXI0 Monitor Debug register 1. Address: 800E_0000h base + 2Ch offset = 800E_002Ch Bit 31 30 29 28 27 26 25 24 23 22 21 WSTATE R 20 19 18 17 16 15 14 13 RSTATE 12 11 10 9 8 7 6 5 RLEN 4 3 2 1 0 WLEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 0 0 0 0 0 0 5 4 3 2 1 0 0 0 HW_DRAM_CTL11 field descriptions Field Description 31-24 WSTATE This reflects the monitor write machine's state. 23-16 RSTATE This reflects the monitor read machine's state. 15-8 RLEN This reflects the read length beat counter. WLEN This reflects the write length beat counter. 14.8.13 AXI1 Debug 0 (HW_DRAM_CTL12) AXI1 Monitor Debug register 0. Address: 800E_0000h base + 30h offset = 800E_0030h Bit 31 30 29 28 27 26 25 24 23 22 RSVD R 21 20 19 18 17 16 15 14 READ_CNT 13 12 11 10 WRESP_CNT WDATA_CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL12 field descriptions Field 31-24 RSVD 23-16 READ_CNT Description Reserved. This field will indicate how many read commands have been accepted in which their respective data beats have not been returned over the data bus. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1187 Programmable Registers HW_DRAM_CTL12 field descriptions (continued) Field Description 15-8 WRESP_CNT This field will indicate how many write commands have been accepted in which their respective RESP signaling has not completed. WDATA_CNT This field will indicate how many write commands have been accepted in which their respective data beats have not been transferred over the data bus. 14.8.14 AXI1 Debug 1 (HW_DRAM_CTL13) AXI1 Monitor Debug register 1. Address: 800E_0000h base + 34h offset = 800E_0034h Bit 31 30 29 28 27 26 25 24 23 22 21 WSTATE R 20 19 18 17 16 15 14 13 RSTATE 12 11 10 9 8 7 6 5 RLEN 4 3 2 1 0 WLEN W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 HW_DRAM_CTL13 field descriptions Field Description 31-24 WSTATE This reflects the monitor write machine's state. 23-16 RSTATE This reflects the monitor read machine's state. 15-8 RLEN This reflects the read length beat counter. WLEN This reflects the write length beat counter. 14.8.15 AXI2 Debug 0 (HW_DRAM_CTL14) AXI2 Monitor Debug register 0. Address: 800E_0000h base + 38h offset = 800E_0038h Bit 31 30 29 28 27 26 25 24 23 22 RSVD R 21 20 19 18 17 16 15 14 READ_CNT 13 12 11 10 WRESP_CNT WDATA_CNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1188 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL14 field descriptions Field Description 31-24 RSVD Reserved. 23-16 READ_CNT This field will indicate how many read commands have been accepted in which their respective data beats have not been returned over the data bus. 15-8 WRESP_CNT This field will indicate how many write commands have been accepted in which their respective RESP signaling has not completed. WDATA_CNT This field will indicate how many write commands have been accepted in which their respective data beats have not been transferred over the data bus. 14.8.16 AXI2 Debug 1 (HW_DRAM_CTL15) AXI2 Monitor Debug register 1. Address: 800E_0000h base + 3Ch offset = 800E_003Ch Bit 31 30 29 28 27 26 25 24 23 22 21 WSTATE R 20 19 18 17 16 15 14 13 RSTATE 12 11 10 9 8 7 6 5 RLEN 4 3 2 1 0 0 0 0 WLEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL15 field descriptions Field Description 31-24 WSTATE This reflects the monitor write machine's state. 23-16 RSTATE This reflects the monitor read machine's state. 15-8 RLEN This reflects the read length beat counter. WLEN This reflects the write length beat counter. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1189 Programmable Registers 14.8.17 DRAM Control Register 16 (HW_DRAM_CTL16) This is a DRAM configuration register. Address: 800E_0000h base + 40h offset = 800E_0040h 31 30 29 28 27 26 25 22 21 20 19 18 17 16 RSVD2 WRITE_MODEREG W Bit 23 RSVD3 R Reset 24 POWER_DOWN Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 OBSOLETE RSVD1 START R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL16 field descriptions Field 31-25 RSVD3 24 WRITE_ MODEREG Description Always write zeroes to this field. Write mode register data to the DRAMs. WRITE-ONLY Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1190 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL16 field descriptions (continued) Field Description Writes mode register information into the memory devices. The user should program the appropriate mrY_data_X parameters with valid information based on the memory type being used. All of the mode registers that are relevant for the memory type specified in the dram_class parameter will be written on each write_modereg setting. This parameter will always read back as 'b0. The mode registers are automatically written at initialization of the EMI. There is no need to initiate a mode register write after setting the start parameter in the EMI unless some value in these registers needs to be changed after initialization. This parameter may not be changed when the memory is in power-down mode (when the CKE input is deasserted). 23-17 RSVD2 Always write zeroes to this field. 16 Disable clock enable and set DRAMs in power-down state. POWER_DOWN When this parameter is set to 'b1, the EMI will complete processing of the current burst for the current transaction (if any), issue a pre-charge all command and then disable the clock enable signal to the DRAM devices. Any subsequent commands in the command queue will be suspended until this parameter is cleared to 'b0. 'b0 = Enable full power state. 'b1 = Disable the clock enable and power down the EMI. 15-8 OBSOLETE Always write zeroes to this field. 7-1 RSVD1 Always write zeroes to this field. 0 START Initiate cmd processing in the controller. Prior to setting this parameter to 1'b1, the EMI will not issue any commands to the DRAM devices or respond to any signal activity except for reading and writing parameters and accepting traffic that the customer may send to the EMI internal queues. Once this parameter is set to 1'b1, the EMI will respond to inputs from the ASIC and begin to process memory access commands. Note that resetting this parameter to 1'b0 will not shut off traffic. However, cycling this parameter to 1'b0 and then resetting it to 1'b1 will reset the digital DLL to a new input clock frequency if desired. This protocol is described in detail in section Changing Input Clock Frequency. Note: Until the initialization complete bit is set in the int_status parameter and the dfi_init_complete signal is asserted from the PHY, commands will not be accepted into the core command queue. 'b0 = Controller is not in active mode. 'b1 = Initiate active mode for the EMI. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1191 Programmable Registers 14.8.18 DRAM Control Register 17 (HW_DRAM_CTL17) This is a DRAM configuration register. Address: 800E_0000h base + 44h offset = 800E_0044h 30 29 28 27 26 25 RSVD4 R W 21 20 19 18 17 16 RSVD3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD2 R W Reset 22 0 0 0 0 0 0 0 0 RSVD1 SREFRESH Bit 23 ENABLE_QUICK_SREFRESH Reset 24 AREFRESH 31 AUTO_REFRESH_MODE Bit 0 0 0 0 0 HW_DRAM_CTL17 field descriptions Field 31-25 RSVD4 24 AUTO_ REFRESH_ MODE Description Always write zeroes to this field. Define auto-refresh to occur at next burst or next cmd boundary. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1192 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL17 field descriptions (continued) Field Description Sets the mode for when the automatic refresh will occur. If the auto_refresh_mode parameter is set and a refresh is required to memory, the EMI will delay this refresh until the end of the current transaction (if the transaction is fully contained inside a single page), or until the current transaction hits the end of the current page. 'b0 = Issue refresh on the next DRAM burst boundary, even if the current command is not complete. 'b1 = Issue refresh on the next command boundary. 23-17 RSVD3 16 AREFRESH Always write zeroes to this field. Trigger auto-refresh at boundary specified by AUTO_REFRESH_MODE. WRITE-ONLY Initiates an automatic refresh to the DRAM devices based on the setting of the auto_refresh_mode parameter. If there are any open banks when this parameter is set, the EMI will automatically close these banks before issuing the auto-refresh command. This parameter will always read back as 0x0. 'b0 = No action 'b1 = Issue refresh to the DRAM devices 15-9 RSVD2 8 ENABLE_ QUICK_ SREFRESH Always write zeroes to this field. Allow user to interrupt memory initialization to enter self-refresh mode. When this bit is set to 'b1, the memory initialization sequence may be interrupted and the memory may enter self-refresh mode. This is used to place the memory devices into self-refresh mode when a power loss is detected during the initialization process. 'b0 = Continue memory initialization. 'b1 = Interrupt memory initialization and enter self-refresh mode. 7-1 RSVD1 0 SREFRESH Always write zeroes to this field. Place DRAMs in self-refresh mode. When this parameter is set to 'b1, the DRAM device(s) will be placed in self-refresh mode. For this, the current burst for the current transaction (if any) will complete, all banks will be closed, the self-refresh command will be issued to the DRAM, and the clock enable signal will be de-asserted. The system will remain in self-refresh mode until this parameter is cleared to 'b0. The DRAM devices will return to normal operating mode after the self-refresh exit time (the txsr parameter) of the device and any DLL initialization time for the DRAM is reached. The EMI will resume processing of the commands from the interruption point. This parameter will be updated with an assertion of the srefresh_enter pin, regardless of the behavior on the register interface. To disable self-refresh again after a srefresh_enter pin assertion, the user will need to clear the parameter to 'b0. 'b0 = Disable self-refresh mode. 'b1 = Initiate self-refresh of the DRAM devices. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1193 Programmable Registers 14.8.19 DRAM Control Register 21 (HW_DRAM_CTL21) This is a DRAM configuration register. Address: 800E_0000h base + 54h offset = 800E_0054h Bit 31 30 29 28 27 26 25 24 23 22 21 20 RSVD3 R 19 18 17 16 DLL_LOCK CKE_DELAY W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD2 R DLL_BYPASS_MODE Bit 0 DLLLOCKREG Reset RSVD1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL21 field descriptions Field 31-27 RSVD3 26-24 CKE_DELAY Description Always write zeroes to this field. Additional cycles to delay CKE for status reporting. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1194 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL21 field descriptions (continued) Field Description Sets the number of additional cycles of delay to include in the CKE signal cke_status for status reporting. The default delay is 0 cycles. 23-16 DLL_LOCK Number of delay elements in master DLL lock. READ-ONLY Defines the actual number of delay elements used to capture one full clock cycle. This parameter is automatically updated every time a refresh operation is performed. This parameter is read-only. 15-9 RSVD2 Always write zeroes to this field. 8 DLLLOCKREG Status of DLL lock coming out of master delay. READ-ONLY Shows status of the DLL as locked or unlocked. This parameter is read-only 'b0 = DLL is unlocked. 'b1 = DLL is locked. 7-1 RSVD1 Always write zeroes to this field. 0 Enable the DLL bypass feature of the controller. DLL_BYPASS_ This parameter has no meaning for this EMI. MODE 14.8.20 DRAM Control Register 22 (HW_DRAM_CTL22) This is a DRAM configuration register. Address: 800E_0000h base + 58h offset = 800E_0058h Bit 31 30 29 28 27 26 25 24 23 OBSOLETE R 22 21 20 RSVD3 W Reset 0 0 0 0 0 0 0 0 0 0 0 19 18 17 16 LOWPOWER _REFRESH_ ENABLE 0 0 0 0 0 15 14 13 RSVD2 0 0 0 12 11 10 9 8 LOWPOWER_ CONTROL 0 0 0 0 0 7 6 5 RSVD1 0 0 0 4 3 2 1 0 LOWPOWER_ AUTO_ENABLE 0 0 0 0 0 HW_DRAM_CTL22 field descriptions Field Description 31-24 OBSOLETE Always write zeroes to this field. 23-20 RSVD3 Always write zeroes to this field. 19-16 LOWPOWER_ REFRESH_ ENABLE Enable refreshes while in low power mode. Sets whether refreshes will occur while the EMI is in any of the low power modes. This parameter is active low. 'b0 = Refreshes still occur 'b1 = Refreshes do not occur Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1195 Programmable Registers HW_DRAM_CTL22 field descriptions (continued) Field 15-13 RSVD2 12-8 LOWPOWER_ CONTROL Description Always write zeroes to this field. Controls entry into the low power modes. Enables the individual low power modes of the device. Bit [4] = Controls memory power-down mode (Mode 1). Bit [3] = Controls memory power-down with memory clock gating mode (Mode 2). Bit [2] = Controls memory self-refresh mode (Mode 3). Bit [1] = Controls memory self-refresh with memory clock gating mode (Mode 4). Bit [0] = Controls memory self-refresh with memory and controller clock gating mode (Mode 5). For all bits: 'b0 = Disabled. 'b1 = Enabled. 7-5 RSVD1 Always write zeroes to this field. LOWPOWER_ Enables automatic entry into the low power mode on idle. AUTO_ENABLE Enables automatic entry into the low power modes of the EMI. Bit [4] = Controls memory power-down mode (Mode 1). Bit [3] = Controls memory power-down with memory clock gating mode (Mode 2). Bit [2] = Controls memory self-refresh mode (Mode 3). Bit [1] = Controls memory self-refresh with memory clock gating mode (Mode 4). Bit [0] = Controls memory self-refresh with memory and controller clock gating mode (Mode 5). It is not possible to enter Mode 5 manually. Setting bit [0] of lowpower_control with bit [0] of this parameter cleared will not result in any change. The user should not use both automatic and manual modes for the various low power modes. All modes should be entered automatically or all entered manually. For all bits: 'b0 = Automatic entry into this mode is disabled. The user may enter this mode manually by setting the associated lowpower_control bit. 'b1 = Automatic entry into this mode is enabled. The mode will be entered automatically when the proper counters expire, and only if the associated lowpower_control bit is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1196 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.21 DRAM Control Register 23 (HW_DRAM_CTL23) This is a DRAM configuration register. Address: 800E_0000h base + 5Ch offset = 800E_005Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 LOWPOWER_INTERNAL_CNT 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 LOWPOWER_EXTERNAL_CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL23 field descriptions Field Description 31-16 Counts idle cycles to self-refresh with memory and controller clk gating. LOWPOWER_ Counts the number of idle cycles before memory self-refresh with memory and controller clock gating low INTERNAL_CNT power mode. LOWPOWER_ Counts idle cycles to self-refresh with memory clock gating. EXTERNAL_CNT Counts the number of idle cycles before memory self-refresh with memory clock gating low power mode. 14.8.22 DRAM Control Register 24 (HW_DRAM_CTL24) This is a DRAM configuration register. Address: 800E_0000h base + 60h offset = 800E_0060h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 LOWPOWER_SELF_REFRESH_CNT 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 LOWPOWER_REFRESH_HOLD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL24 field descriptions Field Description 31-16 Counts idle cycles to memory self-refresh. LOWPOWER_ Counts the number of cycles to the next memory self-refresh low power mode. SELF_ REFRESH_CNT LOWPOWER_ REFRESH_ HOLD Re-Sync counter for DLL in Clock Gate Mode. Sets the number of cycles that the EMI will wait before attempting to re-lock the DLL when using the controller clock gating mode low power mode. This counter will ONLY be used in this mode, the deepest low power mode. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1197 Programmable Registers HW_DRAM_CTL24 field descriptions (continued) Field Description When this counter expires, the DLL will be un-gated for at least 16 cycles during which the DLL will attempt to re-lock. After 16 cycles have elapsed and the DLL has locked, then the DLL controller clock will be gated again and the counter will reset to this value. If the DLL requires more than 16 cycles to re-lock, then the un-gated time will be longer. 14.8.23 DRAM Control Register 25 (HW_DRAM_CTL25) This is a DRAM configuration register. Address: 800E_0000h base + 64h offset = 800E_0064h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 OBSOLETE R 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 LOWPOWER_POWER_DOWN_CNT W Reset 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL25 field descriptions Field 31-16 OBSOLETE LOWPOWER_ POWER_ DOWN_CNT Description Always write zeroes to this field. Counts idle cycles to memory power-down. Counts the number of idle cycles before memory power-down or power-down with memory clock gating low power mode. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1198 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.24 DRAM Control Register 26 (HW_DRAM_CTL26) This is a DRAM configuration register. Address: 800E_0000h base + 68h offset = 800E_0068h Bit 31 30 29 28 27 26 25 24 23 22 21 OBSOLETE 19 18 17 16 RSVD3 PRIORITY_EN R 20 W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD2 R W Reset 0 0 0 0 RSVD1 0 0 0 0 0 0 0 0 PLACEMENT_EN Bit 0 ADDR_CMP_EN Reset 0 HW_DRAM_CTL26 field descriptions Field Description 31-24 OBSOLETE Always write zeroes to this field. 23-17 RSVD3 Always write zeroes to this field. 16 PRIORITY_EN Enable priority for cmd queue placement logic. Enables priority as a condition when using the placement logic to fill the command queue. 'b0 = Disabled 'b1 = Enabled Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1199 Programmable Registers HW_DRAM_CTL26 field descriptions (continued) Field 15-9 RSVD2 Description Always write zeroes to this field. 8 Enable address collision detection for cmd queue placement logic. ADDR_CMP_EN Enables address collision/data coherency detection as a condition when using the placement logic to fill the command queue. 'b0 = Disabled 'b1 = Enabled 7-1 RSVD1 0 PLACEMENT_ EN Always write zeroes to this field. Enable placement logic for cmd queue. Enables using the placement logic to fill the command queue. 'b0 = Placement logic is disabled. The command queue is a straight FIFO. 'b1 = Placement logic is enabled. The command queue will be filled according to the placement logic factors. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1200 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.25 DRAM Control Register 27 (HW_DRAM_CTL27) This is a DRAM configuration register. Address: 800E_0000h base + 6Ch offset = 800E_006Ch 30 29 28 27 26 25 RSVD4 R W Reset Bit 24 23 22 21 20 19 18 17 16 RSVD3 SWAP_EN 31 SWAP_PORT_RW_SAME_EN Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD2 RSVD1 RW_SAME_EN BANK_SPLIT_EN R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL27 field descriptions Field 31-25 RSVD4 Description Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1201 Programmable Registers HW_DRAM_CTL27 field descriptions (continued) Field Description 24 No meaning for this MC. SWAP_PORT_ When swapping in enabled (swap_en is set to 'b1), this parameter enables swapping between read RW_SAME_EN commands on the same port from different requestors. Commands from the same requestor can not be swapped. While read data may be interleaved, write data must be accepted in order on a port. The MC logic will not swap write commands from the same port, even if this bit is enabled. This situation will be uncommon since all read commands on the same port enter the command queue at the priority defined in axiY_r_priority. However, this situation may occur through command aging. 'b0 = Disabled 'b1 = Enabled 23-17 RSVD3 16 SWAP_EN Always write zeroes to this field. Enable command swapping logic in execution unit. Enables swapping of the active command for a new higher-priority command when using the placement logic. 'b0 = Disabled 'b1 = Enabled 15-9 RSVD2 8 BANK_SPLIT_ EN Always write zeroes to this field. Enable bank splitting for cmd queue placement logic. Enables bank splitting as a condition when using the placement logic to fill the command queue. 'b0 = Disabled 'b1 = Enabled 7-1 RSVD1 Always write zeroes to this field. 0 Enable read/write grouping for cmd queue placement logic. RW_SAME_EN Enables read/write grouping as a condition when using the placement logic to fill the command queue. 'b0 = Disabled 'b1 = Enabled i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1202 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.26 DRAM Control Register 28 (HW_DRAM_CTL28) This is a DRAM configuration register. Address: 800E_0000h base + 70h offset = 800E_0070h Bit 31 30 29 28 27 26 25 24 23 RSVD4 R 22 21 20 19 18 17 16 RSVD3 Q_FULLNESS AGE_COUNT W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD2 R RSVD1 ACTIVE_AGING Reset COMMAND_AGE_COUNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL28 field descriptions Field 31-27 RSVD4 26-24 Q_FULLNESS 23-20 RSVD3 19-16 AGE_COUNT 15-12 RSVD2 Description Always write zeroes to this field. Quantity that determines cmd queue full. Defines quantity of data that will be considered full for the command queue. Always write zeroes to this field. Initial value of master aging-rate counter for cmd aging. Holds the initial value of the master aging-rate counter. When using the placement logic to fill the command queue, the command aging counters will be decremented one each time the master aging-rate counter counts down age_count cycles. Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1203 Programmable Registers HW_DRAM_CTL28 field descriptions (continued) Field Description 11-8 COMMAND_ AGE_COUNT Initial value of individual cmd aging counters for cmd aging. Holds the initial value of the command aging counters associated with each command in the command queue. When using the placement logic to fill the command queue, the command aging counters decrement one each time the master aging-rate counter counts down the number of cycles in the age_count parameter. 7-1 RSVD1 Always write zeroes to this field. 0 Enable command aging in the command queue. ACTIVE_AGING Enables aging of commands in the command queue when using the placement logic to fill the command queue. The total number of cycles required to decrement the priority value on a command by one is the product of the values in the age_count and command_age_count parameters. 'b0 = Disabled 'b1 = Enabled 14.8.27 DRAM Control Register 29 (HW_DRAM_CTL29) This is a DRAM configuration register. Address: 800E_0000h base + 74h offset = 800E_0074h Bit 31 30 29 28 27 RSVD4 R Bit 0 0 15 14 0 0 23 22 21 20 19 RSVD3 18 17 16 COLUMN_SIZE 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RSVD1 ADDR_PINS W Reset 24 0 RSVD2 R 25 CS_MAP W Reset 26 0 0 0 0 0 0 0 0 APREBIT 0 0 0 0 0 HW_DRAM_CTL29 field descriptions Field 31-28 RSVD4 27-24 CS_MAP Description Always write zeroes to this field. Defines which chip selects are active. Sets the mask that determines which chip select pins are active, with each bit representing a different chip select. The user address chip select field will be mapped into the active chip selects indicated by this parameter in ascending order from lowest to highest. This allows the EMI to map the entire contiguous Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1204 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL29 field descriptions (continued) Field Description user address into any group of chip selects. Bit [0] of this parameter corresponds to chip select [0], bit [1] corresponds to chip select [1], etc. The number of chip selects, the number of bits set to 1 in this parameter, must be a power of 2. 23-19 RSVD3 Always write zeroes to this field. 18-16 Difference between number of column pins available and number being used. COLUMN_SIZE Shows the difference between the maximum column width available (12) and the actual number of column pins being used. The user address is automatically shifted so that the user address space is mapped contiguously into the memory map based on the value of this parameter. 15-11 RSVD2 Always write zeroes to this field. 10-8 ADDR_PINS Difference between number of addr pins available and number being used. Defines the difference between the maximum number of address pins configured (15) and the actual number of pins being used. The user address is automatically shifted so that the user address space is mapped contiguously into the memory map based on the value of this parameter. 7-4 RSVD1 Always write zeroes to this field. APREBIT Location of the auto pre-charge bit in the DRAM address. Defines the location of the auto pre-charge bit in the DRAM address in decimal encoding. 14.8.28 DRAM Control Register 30 (HW_DRAM_CTL30) This is a DRAM configuration register. Address: 800E_0000h base + 78h offset = 800E_0078h Bit 31 30 29 28 27 26 25 24 23 22 OBSOLETE R 21 20 19 RSVD3 18 17 16 MAX_CS_REG W Reset Bit 0 0 0 0 0 15 14 13 12 11 RSVD2 R 0 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 MAX_ROW_REG RSVD1 1 0 0 2 1 0 MAX_COL_REG W Reset 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 HW_DRAM_CTL30 field descriptions Field 31-24 OBSOLETE Description Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1205 Programmable Registers HW_DRAM_CTL30 field descriptions (continued) Field 23-19 RSVD3 18-16 MAX_CS_REG 15-12 RSVD2 Description Always write zeroes to this field. Maximum number of chip selects available. READ-ONLY Displays the maximum number of chip selects configured for this EMI. This parameter is read-only. Always write zeroes to this field. 11-8 Maximum width of memory address bus. READ-ONLY MAX_ROW_REG Defines the maximum width of the memory address bus for the EMI. This value can be used to set the addr_pins parameter. This parameter is read-only. addr_pins = max_row_reg - . 7-4 RSVD1 Always write zeroes to this field. MAX_COL_REG Maximum width of column address in DRAMs. READ-ONLY Defines the maximum width of column address in the DRAM devices. This value can be used to set the column_size parameter. This parameter is read-only. column_size = max_col_reg - . i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1206 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.29 DRAM Control Register 31 (HW_DRAM_CTL31) This is a DRAM configuration register. Address: 800E_0000h base + 7Ch offset = 800E_007Ch 31 30 29 28 27 26 25 24 23 22 21 OBSOLETE R 20 19 18 17 RSVD3 W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD2 R W Reset 0 0 0 0 RSVD1 0 0 0 0 DQS_N_EN Bit 0 DRIVE_DQ_DQS Reset 16 EIGHT_BANK_MODE Bit 0 0 0 0 0 HW_DRAM_CTL31 field descriptions Field Description 31-24 OBSOLETE Always write zeroes to this field. 23-17 RSVD3 Always write zeroes to this field. 16 EIGHT_BANK_ MODE Number of banks on the DRAM(s). Indicates that the memory devices have eight banks. 'b0 = Memory devices have 4 banks. 'b1 = Memory devices have 8 banks. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1207 Programmable Registers HW_DRAM_CTL31 field descriptions (continued) Field 15-9 RSVD2 Description Always write zeroes to this field. 8 Sets DQ/DQS output enable behavior when controller is idle. DRIVE_DQ_DQS Selects if the DQ output enables and DQS output enables will be driven active when the EMI is in an idle state. 'b0 = Leave the output enables in their current state when idle. 'b1 = Drive the idle_drive_enable signal high when idle. 7-1 RSVD1 0 DQS_N_EN Always write zeroes to this field. Set DQS pin as single-ended or differential. Enables differential data strobe signals from the DRAM. This parameter is only relevant for the DDR PHY. 'b0 = Single-ended DQS signal from the DRAM. 'b1 = Differential DQS signal from the DRAM. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1208 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.30 DRAM Control Register 32 (HW_DRAM_CTL32) This is a DRAM configuration register. Address: 800E_0000h base + 80h offset = 800E_0080h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OBSOLETE R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD2 RSVD1 REDUC R REG_DIMM_ENABLE Reset W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL32 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD2 Always write zeroes to this field. 8 REDUC Enable the half datapath feature of the controller. Controls the width of the memory datapath. When enabled, the upper half of the memory buses (DQ, DQS and DM) are unused and relevant data only exists in the lower half of the buses. This parameter expands the EMI for use with memory devices of the configured width or half of the configured width. The entire user datapath is used regardless of this setting. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1209 Programmable Registers HW_DRAM_CTL32 field descriptions (continued) Field Description 'b0 = Standard operation using full memory bus. 'b1 = Memory datapath width is half of the maximum size. The upper half of the data_byte_disable bus will be driven to 'b1. 7-1 RSVD1 Always write zeroes to this field. 0 REG_DIMM_ ENABLE Enable registered DIMM operation of the controller. Enables registered DIMM operations to control the address and command pipeline of the EMI. 'b0 = Normal operation 'b1 = Enable registered DIMM operation 14.8.31 DRAM Control Register 33 (HW_DRAM_CTL33) This is a DRAM configuration register. Address: 800E_0000h base + 84h offset = 800E_0084h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OBSOLETE R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 R W Reset 0 0 0 0 RSVD1 CONCURRENTAP Reset 0 0 0 0 AP 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1210 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL33 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD2 Always write zeroes to this field. 8 Allow controller to issue cmds to other banks while a bank is in auto pre-charge. CONCURRENTAP Enables concurrent auto pre-charge. Some DRAM devices do not allow one bank to be auto precharged while another bank is reading or writing. The JEDEC standard allows concurrent auto precharge. The user should set this parameter if the DRAM device supports this feature. 'b0 = Concurrent auto pre-charge disabled. 'b1 = Concurrent auto pre-charge enabled. 7-1 RSVD1 0 AP Always write zeroes to this field. Enable auto pre-charge mode of controller. Enables auto pre-charge mode for DRAM devices. This parameter may not be modified after the start parameter has been asserted. 'b0 = Auto pre-charge mode disabled. Memory banks will stay open until another request requires this bank, the maximum open time (tras_max) has elapsed, or a refresh command closes all the banks. 'b1 = Auto pre-charge mode enabled. All read and write transactions must be terminated by an auto precharge command. If a transaction consists of multiple read or write bursts, only the last command is issued with an auto pre-charge. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1211 Programmable Registers 14.8.32 DRAM Control Register 34 (HW_DRAM_CTL34) This is a DRAM configuration register. Address: 800E_0000h base + 88h offset = 800E_0088h 30 29 28 27 26 25 RSVD4 R W 21 20 19 18 17 RSVD3 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD2 R W Reset 22 0 0 0 0 RSVD1 0 0 0 0 0 0 0 0 INTRPTAPBURST Bit 23 INTRPTREADA Reset 24 INTRPTWRITEA 31 WRITEINTERP Bit 0 HW_DRAM_CTL34 field descriptions Field 31-25 RSVD4 24 WRITEINTERP Description Always write zeroes to this field. Allow controller to interrupt a write burst to the DRAMs with a read cmd. Defines whether the EMI can interrupt a write burst with a read command. Some memory devices do not allow this functionality. For DDR1 or LPDDR1 memory devices, consult the memory specification for the setting for this parameter. For DDR2memory devices, this parameter must be cleared to 'b0. 'b0 = The device does not support read commands interrupting write commands. 'b1 = The device does support read commands interrupting write commands. 23-17 RSVD3 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1212 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL34 field descriptions (continued) Field 16 INTRPTWRITEA Description Allow the controller to interrupt a combined write with auto pre-charge cmd with another write cmd. Enables interrupting of a combined write with auto pre-charge command with another read or write command to the same bank before the first write command is completed. 'b0 = Disable interrupting a combined write with auto pre-charge command with another read or write command to the same bank. 'b1 = Enable interrupting a combined write with auto pre-charge command with another read or write command to the same bank. 15-9 RSVD2 8 INTRPTREADA Always write zeroes to this field. Allow the controller to interrupt a combined read with auto pre-charge cmd with another read cmd. Enables interrupting of a combined read with auto pre-charge command with another read command to the same bank before the first read command is completed. 'b0 = Disable interrupting the combined read with auto pre-charge command with another read command to the same bank. 'b1 = Enable interrupting the combined read with auto pre-charge command with another read command to the same bank. 7-1 RSVD1 Always write zeroes to this field. 0 Allow the controller to interrupt an auto pre-charge cmd with another cmd. INTRPTAPBURST Enables interrupting an auto pre-charge command with another command for a different bank. If enabled, the current operation will be interrupted. However, the bank will be pre-charged as if the current operation were allowed to continue. 'b0 = Disable interrupting an auto pre-charge operation on a different bank. 'b1 = Enable interrupting an auto pre-charge operation on a different bank. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1213 Programmable Registers 14.8.33 DRAM Control Register 35 (HW_DRAM_CTL35) This is a DRAM configuration register. Address: 800E_0000h base + 8Ch offset = 800E_008Ch 31 30 29 28 27 26 25 24 23 22 21 OBSOLETE R 20 19 18 17 RSVD3 W Reset Bit 16 PWRUP_SREFRESH_EXIT Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 RSVD1 NO_CMD_INIT R INITAREF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL35 field descriptions Field Description 31-24 OBSOLETE Always write zeroes to this field. 23-17 RSVD3 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1214 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL35 field descriptions (continued) Field 16 PWRUP_ SREFRESH_ EXIT Description Allow powerup through self-refresh instead of full memory initialization. Allows controller to exit power-down mode by executing a self-refresh exit instead of the full memory initialization. This parameter provides a means to skip full initialization when the DRAM devices are in a known self-refresh state. 'b0 = Disabled 'b1 = Enabled 15-9 RSVD2 8 NO_CMD_INIT Always write zeroes to this field. Disable DRAM cmds until TDLL has expired during initialization. Disables DRAM commands until DLL initialization is complete and tdll has expired. 'b0 = Issue only REF and PRE commands during DLL initialization of the DRAM devices. If PRE commands are issued before DLL initialization is complete, the command will be executed immediately, and then the DLL initialization will continue. 'b1 = Do not issue any type of command during DLL initialization of the DRAM devices. If any other commands are issued during the initialization time, they will be held off until DLL initialization is complete. 7-4 RSVD1 INITAREF Always write zeroes to this field. Number of auto-refresh cmds to execute during DRAM initialization. Defines the number of auto-refresh commands needed by the DRAM devices to satisfy the initialization sequence. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1215 Programmable Registers 14.8.34 DRAM Control Register 36 (HW_DRAM_CTL36) This is a DRAM configuration register. Address: 800E_0000h base + 90h offset = 800E_0090h 31 30 29 28 27 26 25 22 21 20 19 18 17 RSVD2 TREF_ENABLE W Bit 23 RSVD3 R Reset 24 16 TRAS_LOCKOUT Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 OBSOLETE RSVD1 FAST_WRITE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL36 field descriptions Field 31-25 RSVD3 Description Always write zeroes to this field. 24 Issue auto-refresh cmds to the DRAMs every TREF cycles. TREF_ENABLE Enables refresh commands. If command refresh mode is configured, then refresh commands will be automatically issued based on the tref parameter value and any refresh commands sent through the command interface or the register interface. Refreshes will still occur even if the DRAM devices have been placed in power down state by the assertion of the power_down parameter. 'b0 = Refresh commands disabled. 'b1 = Refresh commands enabled. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1216 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL36 field descriptions (continued) Field Description 23-17 RSVD2 Always write zeroes to this field. 16 TRAS_ LOCKOUT Allow the controller to execute auto pre-charge cmds before TRAS_MIN expires. Defines the tRAS lockout setting for the DRAM device. tRAS lockout allows the EMI to execute auto precharge commands before the tras_min parameter has expired. 'b0 = tRAS lockout not supported by memory device. 'b1 = tRAS lockout supported by memory device. 15-8 OBSOLETE Always write zeroes to this field. 7-1 RSVD1 Always write zeroes to this field. 0 FAST_WRITE Define when write cmds are issued to DRAM devices. Controls when the write commands are issued to the DRAM devices. 'b0 = The EMI will issue a write command to the DRAM devices when it has received enough data for one DRAM burst. In this mode, write data can be sent in any cycle relative to the write command. This mode also allows for multi-word write command data to arrive in non-sequential cycles. 'b1 = The EMI will issue a write command to the DRAM devices after the first word of the write data is received by the EMI. The first word can be sent at any time relative to the write command. In this mode, multi-word write command data must be available to the EMI in sequential cycles. 14.8.35 DRAM Control Register 37 (HW_DRAM_CTL37) This is a DRAM configuration register. Address: 800E_0000h base + 94h offset = 800E_0094h Bit 31 30 29 28 RSVD4 R 0 0 0 26 25 24 23 0 0 0 0 0 22 21 20 RSVD3 CASLAT_ LIN_GATE W Reset 27 0 0 0 19 18 17 16 15 0 0 0 0 13 12 11 RSVD2 CASLAT_LIN 0 14 0 0 0 0 10 9 8 7 0 0 0 5 4 3 RSVD1 CASLAT 0 6 0 0 0 2 1 0 WRLAT 0 0 0 0 0 HW_DRAM_CTL37 field descriptions Field 31-28 RSVD4 27-24 CASLAT_LIN_ GATE Description Always write zeroes to this field. Adjusts data capture gate open by half cycles. Adjusts the data capture gate open time by 1/2 cycle increments. This parameter is programmed differently than caslat_lin when there are fixed offsets in the flight path between the memories and the EMI for clock gating. When caslat_lin_gate is a larger value than caslat_lin, the data capture window will become shorter. A caslat_lin_gate value smaller than caslat_lin may have no effect on the data capture window, depending on the fixed offsets in the ASIC and the board. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1217 Programmable Registers HW_DRAM_CTL37 field descriptions (continued) Field Description For optimal synthesis behavior, the ODT path for a CAS latency of three is clocked at a 200 MHz clock regardless of configured maximum speed. 'b0000 - 'b0001 = Reserved 'b0010 = 1 cycle 'b0011 = 1.5 cycles 'b0100 = 2 cycles 'b0101 = 2.5 cycles 'b0110 = 3 cycles 'b0111 = 3.5 cycles 'b1000 = 4 cycles 'b1001 = 4.5 cycles 'b1010 = 5 cycles 'b1011 = 5.5 cycles 'b1100 = 6 cycles 'b1101 = 6.5 cycles 'b1110 = 7 cycles 'b1111 = 7.5 cycles 23-20 RSVD3 19-16 CASLAT_LIN Always write zeroes to this field. Sets latency from read cmd send to data receive from/to controller. Sets the CAS latency linear value in 1/2 cycle increments. This sets an internal adjustment for the delay from when the read command is sent from the EMI to when data will be received back. The window of time in which the data is captured is a fixed length. The caslat_lin parameter adjusts the start of this data capture window. Not all linear values will be supported for the memory devices being used. Refer to the specification for the memory devices being used. For optimal synthesis behavior, the ODT path for a CAS latency of three is clocked at a 200 MHz clock regardless of configured maximum speed. 'b0000 - 'b0001 = Reserved 'b0010 = 1 cycle 'b0011 = 1.5 cycles 'b0100 = 2 cycles 'b0101 = 2.5 cycles 'b0110 = 3 cycles 'b0111 = 3.5 cycles 'b1000 = 4 cycles 'b1001 = 4.5 cycles 'b1010 = 5 cycles 'b1011 = 5.5 cycles 'b1100 = 6 cycles Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1218 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL37 field descriptions (continued) Field Description 'b1101 = 6.5 cycles 'b1110 = 7 cycles 'b1111 = 7.5 cycles 15-11 RSVD2 Always write zeroes to this field. 10-8 CASLAT Encoded CAS latency sent to DRAMs during initialization. Sets the CAS (Column Address Strobe) latency encoding that the memory uses. The binary value programmed into this parameter is dependent on the memory device, since the same caslat value may have different meanings to different memories. This will be programmed into the DRAM devices at initialization. The CAS encoding will be specified in the DRAM spec sheet, and should correspond to the caslat_lin parameter. Refer to the files in the regconfigs/ directory in the release for actual settings for each particular device. For optimal synthesis behavior, the ODT path for a CAS latency of three is clocked at a 200 MHz clock regardless of configured maximum speed. 7-4 RSVD1 Always write zeroes to this field. WRLAT DRAM WRLAT parameter in cycles. Defines the write latency from when the write command is issued to the time the write data is presented to the DRAM devices, in cycles. This parameter must be set to 'b1 when the EMI is used in DDR1 mode. 14.8.36 DRAM Control Register 38 (HW_DRAM_CTL38) This is a DRAM configuration register. Address: 800E_0000h base + 98h offset = 800E_0098h Bit R 31 30 29 28 27 RSVD2 0 0 0 25 24 23 22 21 20 19 18 17 TDAL W Reset 26 0 0 0 16 15 14 13 12 11 10 9 8 7 0 0 0 0 0 0 0 0 0 0 5 4 3 2 RSVD1 TCPD 0 6 0 0 0 0 0 0 0 0 0 0 0 1 0 TCKE 0 0 0 0 HW_DRAM_CTL38 field descriptions Field Description 31-29 RSVD2 Always write zeroes to this field. 28-24 TDAL DRAM TDAL parameter in cycles. Defines the auto pre-charge write recovery time when auto pre-charge is enabled (the ap parameter is set to 'b1), in cycles. This is defined internally as tRP (pre-charge time) + auto pre-charge write recovery time. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1219 Programmable Registers HW_DRAM_CTL38 field descriptions (continued) Field Description Not all memories use this parameter. If tDAL is defined in the memory specification, then program this parameter to the specified value. If the memory does not specify a tDAL time, then program this parameter to tWR + tRP. DO NOT program this parameter with a value of 0x0 or the EMI will not function properly when auto pre-charge is enabled. 23-8 TCPD DRAM TCPD parameter in cycles. Defines the clock enable to pre-charge delay time for the DRAM devices, in cycles. 7-3 RSVD1 Always write zeroes to this field. TCKE Minimum CKE pulse width. Defines the minimum CKE pulse width, in cycles. 14.8.37 DRAM Control Register 39 (HW_DRAM_CTL39) This is a DRAM configuration register. Address: 800E_0000h base + 9Ch offset = 800E_009Ch Bit 31 R 30 29 28 RSVD1 Bit 26 25 24 22 21 20 19 18 17 16 OBSOLETE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R TDLL W Reset 23 TFAW W Reset 27 0 0 0 0 0 0 0 0 HW_DRAM_CTL39 field descriptions Field Description 31-30 RSVD1 Always write zeroes to this field. 29-24 TFAW DRAM TFAW parameter in cycles. 23-16 OBSOLETE TDLL Defines the DRAM tFAW parameter, in cycles. Always write zeroes to this field. DRAM TDLL parameter in cycles. Defines the DRAM DLL lock time, in cycles. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1220 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.38 DRAM Control Register 40 (HW_DRAM_CTL40) This is a DRAM configuration register. Address: 800E_0000h base + A0h offset = 800E_00A0h Bit R 31 30 29 28 27 RSVD1 0 0 0 25 24 23 22 21 20 19 18 17 16 15 14 13 TMRD W Reset 26 0 0 0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 TINIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL40 field descriptions Field Description 31-29 RSVD1 Always write zeroes to this field. 28-24 TMRD DRAM TMRD parameter in cycles. TINIT DRAM TINIT parameter in cycles. Defines the minimum number of cycles required between two mode register write commands. This is the time required to complete the write operation to the mode register. Defines the DRAM initialization time, in cycles. 14.8.39 DRAM Control Register 41 (HW_DRAM_CTL41) This is a DRAM configuration register. Address: 800E_0000h base + A4h offset = 800E_00A4h Bit 31 30 29 28 27 26 25 R Bit 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 R RSVD1 TRCD_INT W Reset 23 TPDEX W Reset 24 0 0 0 0 0 0 0 0 0 0 TRC 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1221 Programmable Registers HW_DRAM_CTL41 field descriptions Field Description 31-16 TPDEX DRAM TPDEX parameter in cycles. 15-8 TRCD_INT DRAM TRCD parameter in cycles. Defines the DRAM power-down exit command period, in cycles. Defines the DRAM RAS to CAS delay, in cycles. 7-6 RSVD1 Always write zeroes to this field. TRC DRAM TRC parameter in cycles. Defines the DRAM period between active commands for the same bank, in cycles. 14.8.40 DRAM Control Register 42 (HW_DRAM_CTL42) This is a DRAM configuration register. Address: 800E_0000h base + A8h offset = 800E_00A8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OBSOLETE R 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 TRAS_MAX W Reset 16 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 TRAS_MIN 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL42 field descriptions Field Description 31-24 OBSOLETE Always write zeroes to this field. 23-8 TRAS_MAX DRAM TRAS_MAX parameter in cycles. TRAS_MIN DRAM TRAS_MIN parameter in cycles. Defines the DRAM maximum row active time, in cycles. Defines the DRAM minimum row activate time, in cycles. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1222 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.41 DRAM Control Register 43 (HW_DRAM_CTL43) This is a DRAM configuration register. Address: 800E_0000h base + ACh offset = 800E_00ACh Bit 31 30 29 28 27 26 RSVD2 R Bit 24 23 22 21 20 TRP W Reset 25 19 18 17 16 TRFC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSVD1 R TREF W Reset 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL43 field descriptions Field Description 31-28 RSVD2 Always write zeroes to this field. 27-24 TRP DRAM TRP parameter in cycles. 23-16 TRFC DRAM TRFC parameter in cycles. 15-14 RSVD1 Always write zeroes to this field. Defines the DRAM pre-charge command time, in cycles. Defines the DRAM refresh command time, in cycles. TREF DRAM TREF parameter in cycles. Defines the DRAM cycles between refresh commands. 14.8.42 DRAM Control Register 44 (HW_DRAM_CTL44) This is a DRAM configuration register. Address: 800E_0000h base + B0h offset = 800E_00B0h Bit 31 30 29 28 27 RSVD4 R 0 0 0 25 24 0 0 0 0 23 22 21 20 RSVD3 TWTR W Reset 26 0 0 0 0 19 18 17 16 15 0 0 0 13 12 11 10 RSVD2 TWR_INT 0 14 0 0 0 0 0 9 8 7 0 0 5 4 3 2 RSVD1 TRTP 0 6 0 0 0 0 0 1 0 TRRD 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1223 Programmable Registers HW_DRAM_CTL44 field descriptions Field Description 31-28 RSVD4 Always write zeroes to this field. 27-24 TWTR DRAM TWTR parameter in cycles. 23-21 RSVD3 Always write zeroes to this field. 20-16 TWR_INT DRAM TWR parameter in cycles. 15-11 RSVD2 Always write zeroes to this field. Sets the number of cycles needed to switch from a write to a read operation, as dictated by the DDR SDRAM specification. Defines the DRAM write recovery time, in cycles. 10-8 TRTP DRAM TRTP parameter in cycles. For DDR1, this parameter has no meaning. For LPDDR1 or DDR2, defines the DRAM tRTP (read to precharge time) parameter, in cycles. 7-3 RSVD1 Always write zeroes to this field. TRRD DRAM TRRD parameter in cycles. Defines the DRAM activate to activate delay for different banks, in cycles. 14.8.43 DRAM Control Register 45 (HW_DRAM_CTL45) This is a DRAM configuration register. Address: 800E_0000h base + B4h offset = 800E_00B4h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TXSR 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TXSNR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL45 field descriptions Field 31-16 TXSR TXSNR Description DRAM TXSR parameter in cycles. Defines the DRAM time from a self-refresh exit to a command that requires the memory DLL to be locked. DRAM TXSNR parameter in cycles. Defines the DRAM time from a self-refresh exit to a command that does not require the memory DLL to be locked. (txs) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1224 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.44 DRAM Control Register 48 (HW_DRAM_CTL48) This is a DRAM configuration register. Address: 800E_0000h base + C0h offset = 800E_00C0h R 30 29 28 27 26 25 24 23 22 21 AXI0_CURRENT_BDW 20 19 18 17 16 AXI0_BDW_OVFLOW 31 RSVD4 Bit RSVD3 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 Reset RSVD1 AXI0_FIFO_ TYPE_REG AXI0_BDW W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1225 Programmable Registers HW_DRAM_CTL48 field descriptions Field Description 31 RSVD4 Always write zeroes to this field. 30-24 Current bandwidth usage percentage for port 0. READ-ONLY. AXI0_ CURRENT_BDW 23-17 RSVD3 Always write zeroes to this field. 16 AXI0_BDW_ OVFLOW Port 0 behavior when bandwidth maximized. 15 RSVD2 Always write zeroes to this field. 14-8 AXI0_BDW Maximum bandwidth percentage for port 0. 7-2 RSVD1 Always write zeroes to this field. AXI0_FIFO_ TYPE_REG Clock domain relativity between AXI port 0 and core logic. 14.8.45 DRAM Control Register 49 (HW_DRAM_CTL49) This is a DRAM configuration register. Address: 800E_0000h base + C4h offset = 800E_00C4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AXI0_EN_SIZE_LT_WIDTH_INSTR W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 0 0 0 0 0 0 0 10 9 8 7 AXI0_W_ PRIORIT Y RSVD2 R 0 0 0 0 6 5 4 3 RSVD1 0 0 0 0 2 1 0 AXI0_R_ PRIORIT Y 0 0 0 0 HW_DRAM_CTL49 field descriptions Field Description 31-16 Allow narrow instructions from AXI port 0 requestors with bit enabled. AXI0_EN_SIZE_ LT_WIDTH_ INSTR 15-11 RSVD2 10-8 AXI0_W_ PRIORITY Always write zeroes to this field. Priority of write cmds from AXI port 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1226 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL49 field descriptions (continued) Field 7-3 RSVD1 AXI0_R_ PRIORITY Description Always write zeroes to this field. Priority of read cmds from AXI port 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1227 Programmable Registers 14.8.46 DRAM Control Register 50 (HW_DRAM_CTL50) This is a DRAM configuration register. Address: 800E_0000h base + C8h offset = 800E_00C8h R 30 29 28 27 26 25 24 23 22 21 AXI1_CURRENT_BDW 20 19 18 17 16 AXI1_BDW_OVFLOW 31 RSVD4 Bit RSVD3 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 Reset RSVD1 AXI1_FIFO_ TYPE_REG AXI1_BDW W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1228 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL50 field descriptions Field Description 31 RSVD4 Always write zeroes to this field. 30-24 Current bandwidth usage percentage for port 1. READ-ONLY. AXI1_ CURRENT_BDW 23-17 RSVD3 Always write zeroes to this field. 16 AXI1_BDW_ OVFLOW Port 1 behavior when bandwidth maximized. 15 RSVD2 Always write zeroes to this field. 14-8 AXI1_BDW Maximum bandwidth percentage for port 1. 7-2 RSVD1 Always write zeroes to this field. AXI1_FIFO_ TYPE_REG Clock domain relativity between AXI port 1 and core logic. 14.8.47 DRAM Control Register 51 (HW_DRAM_CTL51) This is a DRAM configuration register. Address: 800E_0000h base + CCh offset = 800E_00CCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AXI1_EN_SIZE_LT_WIDTH_INSTR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 0 0 0 0 0 0 0 10 9 8 7 AXI1_W_ PRIORIT Y RSVD2 R 0 0 0 0 6 5 4 3 RSVD1 0 0 0 0 2 1 0 AXI1_R_ PRIORIT Y 0 0 0 0 HW_DRAM_CTL51 field descriptions Field Description 31-16 Allow narrow instructions from AXI port 1 requestors with bit enabled. AXI1_EN_SIZE_ LT_WIDTH_ INSTR 15-11 RSVD2 10-8 AXI1_W_ PRIORITY Always write zeroes to this field. Priority of write cmds from AXI port 1. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1229 Programmable Registers HW_DRAM_CTL51 field descriptions (continued) Field 7-3 RSVD1 AXI1_R_ PRIORITY Description Always write zeroes to this field. Priority of read cmds from AXI port 1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1230 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.48 DRAM Control Register 52 (HW_DRAM_CTL52) This is a DRAM configuration register. Address: 800E_0000h base + D0h offset = 800E_00D0h R 30 29 28 27 26 25 24 23 22 21 AXI2_CURRENT_BDW 20 19 18 17 16 AXI2_BDW_OVFLOW 31 RSVD4 Bit RSVD3 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 Reset RSVD1 AXI2_FIFO_ TYPE_REG AXI2_BDW W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1231 Programmable Registers HW_DRAM_CTL52 field descriptions Field Description 31 RSVD4 Always write zeroes to this field. 30-24 Current bandwidth usage percentage for port 2. READ-ONLY. AXI2_ CURRENT_BDW 23-17 RSVD3 Always write zeroes to this field. 16 AXI2_BDW_ OVFLOW Port 2 behavior when bandwidth maximized. 15 RSVD2 Always write zeroes to this field. 14-8 AXI2_BDW Maximum bandwidth percentage for port 2. 7-2 RSVD1 Always write zeroes to this field. AXI2_FIFO_ TYPE_REG Clock domain relativity between AXI port 2 and core logic. 14.8.49 DRAM Control Register 53 (HW_DRAM_CTL53) This is a DRAM configuration register. Address: 800E_0000h base + D4h offset = 800E_00D4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AXI2_EN_SIZE_LT_WIDTH_INSTR W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 0 0 0 0 0 0 0 10 9 8 7 AXI2_W_ PRIORIT Y RSVD2 R 0 0 0 0 6 5 4 3 RSVD1 0 0 0 0 2 1 0 AXI2_R_ PRIORIT Y 0 0 0 0 HW_DRAM_CTL53 field descriptions Field Description 31-16 Allow narrow instructions from AXI port 2 requestors with bit enabled. AXI2_EN_SIZE_ LT_WIDTH_ INSTR 15-11 RSVD2 10-8 AXI2_W_ PRIORITY Always write zeroes to this field. Priority of write cmds from AXI port 2. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1232 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL53 field descriptions (continued) Field 7-3 RSVD1 AXI2_R_ PRIORITY Description Always write zeroes to this field. Priority of read cmds from AXI port 2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1233 Programmable Registers 14.8.50 DRAM Control Register 54 (HW_DRAM_CTL54) This is a DRAM configuration register. Address: 800E_0000h base + D8h offset = 800E_00D8h R 30 29 28 27 26 25 24 23 22 21 AXI3_CURRENT_BDW 20 19 18 17 16 AXI3_BDW_OVFLOW 31 RSVD4 Bit RSVD3 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 Reset RSVD1 AXI3_FIFO_ TYPE_REG AXI3_BDW W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1234 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL54 field descriptions Field Description 31 RSVD4 Always write zeroes to this field. 30-24 Current bandwidth usage percentage for port 3. READ-ONLY. AXI3_ CURRENT_BDW 23-17 RSVD3 Always write zeroes to this field. 16 AXI3_BDW_ OVFLOW Port 3 behavior when bandwidth maximized. 15 RSVD2 Always write zeroes to this field. 14-8 AXI3_BDW Maximum bandwidth percentage for port 3. 7-2 RSVD1 Always write zeroes to this field. AXI3_FIFO_ TYPE_REG Clock domain relativity between AXI port 3 and core logic. 14.8.51 DRAM Control Register 55 (HW_DRAM_CTL55) This is a DRAM configuration register. Address: 800E_0000h base + DCh offset = 800E_00DCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AXI3_EN_SIZE_LT_WIDTH_INSTR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 14 13 12 11 0 0 0 0 0 0 0 10 9 8 7 AXI3_W_ PRIORIT Y RSVD2 R 0 0 0 0 6 5 4 3 RSVD1 0 0 0 0 2 1 0 AXI3_R_ PRIORIT Y 0 0 0 0 HW_DRAM_CTL55 field descriptions Field Description 31-16 Allow narrow instructions from AXI port 3 requestors with bit enabled. AXI3_EN_SIZE_ LT_WIDTH_ INSTR 15-11 RSVD2 10-8 AXI3_W_ PRIORITY Always write zeroes to this field. Priority of write cmds from AXI port 3. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1235 Programmable Registers HW_DRAM_CTL55 field descriptions (continued) Field Description 7-3 RSVD1 Always write zeroes to this field. AXI3_R_ PRIORITY Priority of read cmds from AXI port 3. 14.8.52 DRAM Control Register 56 (HW_DRAM_CTL56) This is a DRAM configuration register. Address: 800E_0000h base + E0h offset = 800E_00E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OBSOLETE R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OBSOLETE R RSVD1 ARB_CMD_Q_ THRESHOLD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL56 field descriptions Field Description 31-8 OBSOLETE Always write zeroes to this field. 7-3 RSVD1 Always write zeroes to this field. ARB_CMD_Q_ THRESHOLD Threshold for cmd queue fullness related to overflow. Sets the command queue fullness that determines if ports will be allowed to overflow. This parameter is used in conjunction with the axiY_bdw_ovflow parameters. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1236 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.53 DRAM Control Register 58 (HW_DRAM_CTL58) This is a DRAM configuration register. Address: 800E_0000h base + E8h offset = 800E_00E8h Bit 31 30 29 28 27 26 25 24 23 RSVD2 R 22 21 20 19 18 17 16 15 INT_STATUS 14 13 12 11 10 9 8 7 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 0 0 INT_MASK W Reset 6 0 0 0 0 0 0 0 0 HW_DRAM_CTL58 field descriptions Field 31-27 RSVD2 26-16 INT_STATUS Description Always write zeroes to this field. Status of interrupt features in the controller. READ-ONLY Shows the status of all possible interrupts generated by the EMI. The MSB is the result of a logical OR of all the lower bits. This parameter is read-only. Backwards compatibility is available for register parameters across configurations. However, even with this compatibility, the individual bits, their meaning and the size of the int_status parameter may change. The int_status bits correspond to these interrupts: Bit [10] = Logical OR of all lower bits. Bit [9] = User-initiated DLL resync is finished. Bit [8] = DLL lock state change condition detected. (i.e. lock to unlock or unlock to lock) Bit [7] = Indicates that a read DQS gate error occurred. Bit [6] = ODT enabled and CAS Latency 3 programmed error detected. This is an unsupported programming option. Bit [5] = Both DDR2 and Mobile modes have been enabled. Bit [4] = DRAM initialization complete. Bit [3] = Error was found with command data channel in a port. Bit [2] = Error was found with command channel in a port. Bit [1] = Multiple accesses outside the defined PHYSICAL memory space detected. Bit [0] = A single access outside the defined PHYSICAL memory space detected. 15-11 RSVD1 INT_MASK Always write zeroes to this field. Mask for controller_int signals from the INT_STATUS parameter. Active-high mask bits that control the value of the EMI_int signal on the ASIC interface. Unless the user has suppressed interrupt reporting (by setting bit [10] of this parameter to 'b1), bits [9:0] of the int_mask parameter will be inverted and logically AND'ed with bits [9:0] of the int_status parameter and the result is reported on the controller_int signal. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1237 Programmable Registers 14.8.54 DRAM Control Register 59 (HW_DRAM_CTL59) This is a DRAM configuration register. Address: 800E_0000h base + ECh offset = 800E_00ECh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_OF_RANGE_ADDR R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL59 field descriptions Field Description OUT_OF_ Address of cmd that caused an Out-of-Range interrupt. READ-ONLY. RANGE_ADDR 14.8.55 DRAM Control Register 60 (HW_DRAM_CTL60) This is a DRAM configuration register. Address: 800E_0000h base + F0h offset = 800E_00F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OBSOLETE R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OBSOLETE R OUT_OF_ RANGE_ ADDR RSVD1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL60 field descriptions Field Description 31-8 OBSOLETE Always write zeroes to this field. 7-2 RSVD1 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1238 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL60 field descriptions (continued) Field Description OUT_OF_ Address of cmd that caused an Out-of-Range interrupt. READ-ONLY. RANGE_ADDR 14.8.56 DRAM Control Register 61 (HW_DRAM_CTL61) This is a DRAM configuration register. Address: 800E_0000h base + F4h offset = 800E_00F4h 31 R 30 29 RSVD3 28 27 26 25 24 23 22 21 RSVD2 Bit OUT_OF_RANGE_TYPE 20 19 18 17 16 OUT_OF_RANGE_LENGTH W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 RSVD1 R OUT_OF_RANGE_SOURCE_ID W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL61 field descriptions Field 31-30 RSVD3 29-24 OUT_OF_ RANGE_TYPE 23 RSVD2 Description Always write zeroes to this field. Type of cmd that caused an Out-of-Range interrupt. READ-ONLY Holds the type of command that caused an out-of-range interrupt request to the memory devices. This parameter is read-only. Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1239 Programmable Registers HW_DRAM_CTL61 field descriptions (continued) Field Description 22-16 OUT_OF_ RANGE_ LENGTH Length of cmd that caused an Out-of-Range interrupt. READ-ONLY Holds the length of the command that caused an out-of-range interrupt request to the memory devices. This parameter is read-only. 15-13 RSVD1 Always write zeroes to this field. OUT_OF_ RANGE_ SOURCE_ID Source ID of cmd that caused an Out-of-Range interrupt. READ-ONLY Holds the Source ID of the command that caused an out-of-range interrupt request to the memory devices. This parameter is read-only. 14.8.57 DRAM Control Register 62 (HW_DRAM_CTL62) This is a DRAM configuration register. Address: 800E_0000h base + F8h offset = 800E_00F8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_CMD_ERROR_ADDR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL62 field descriptions Field Description PORT_CMD_ Address of port that caused the PORT cmd error. READ-ONLY. ERROR_ADDR i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1240 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.58 DRAM Control Register 63 (HW_DRAM_CTL63) This is a DRAM configuration register. Address: 800E_0000h base + FCh offset = 800E_00FCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OBSOLETE R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OBSOLETE R PORT_ CMD_ ERROR_ ADDR RSVD1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL63 field descriptions Field Description 31-8 OBSOLETE Always write zeroes to this field. 7-2 RSVD1 Always write zeroes to this field. PORT_CMD_ Address of port that caused the PORT cmd error. READ-ONLY. ERROR_ADDR 14.8.59 DRAM Control Register 64 (HW_DRAM_CTL64) This is a DRAM configuration register. Address: 800E_0000h base + 100h offset = 800E_0100h Bit 31 30 29 28 27 26 25 24 OBSOLETE R 23 22 21 20 19 18 RSVD2 17 16 15 14 13 12 11 10 9 8 7 PORT_CMD_ERROR_ID 6 5 4 3 2 1 0 PORT_CMD_ ERROR_ TYPE RSVD1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1241 Programmable Registers HW_DRAM_CTL64 field descriptions Field Description 31-24 OBSOLETE Always write zeroes to this field. 23-21 RSVD2 Always write zeroes to this field. 20-8 PORT_CMD_ ERROR_ID Source ID of cmd that caused the PORT cmd error. READ-ONLY Holds the source ID of the command that caused a port command error condition. For AXI ports, the source ID is comprised of the Port ID and the Requestor ID, where the Requestor ID is the axiY_AWID for write commands or the axiY_ARID for read commands. This parameter is read-only. 7-4 RSVD1 Always write zeroes to this field. PORT_CMD_ ERROR_TYPE Type of error and access type that caused the PORT cmd error. READ-ONLY Defines the type of error and the access type that caused the port command error condition. If multiple bits are set to 'b1, then multiple errors were found. This parameter is read-only. Bit [3] = Narrow transfer requested for a requestor Y whose axiY_en_size_lt_width_instr parameter is clear. Bit [2] = Reserved. Bit [1] = Reserved. Bit [0] = Reserved. 14.8.60 DRAM Control Register 65 (HW_DRAM_CTL65) This is a DRAM configuration register. Address: 800E_0000h base + 104h offset = 800E_0104h Bit 31 30 29 28 27 26 25 24 23 OBSOLETE R 22 21 20 RSVD2 19 18 17 16 PORT_DATA_ERROR_ID W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PORT_DATA_ERROR_ID R PORT_DATA_ ERROR_TYPE RSVD1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1242 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL65 field descriptions Field Description 31-24 OBSOLETE Always write zeroes to this field. 23-21 RSVD2 Always write zeroes to this field. 20-8 PORT_DATA_ ERROR_ID Source ID of cmd that caused the PORT data error. READ-ONLY Holds the source ID of the command that caused a port data error condition. For AXI ports, the source ID is comprised of the Port ID and the Requestor ID, where the Requestor ID is the axiY_BID for write response errors, the axiY_RID for read data errors, or the axiY_WID for write data errors. This parameter is read-only. 7-3 RSVD1 Always write zeroes to this field. PORT_DATA_ ERROR_TYPE Type of error and access type that caused the PORT data error. READ-ONLY Defines the type of error and the access type that caused the port data error condition. If multiple bits are set to 'b1, then multiple errors were found. This parameter is read-only. Bit [2] = Reserved. Bit [1] = Reserved. Bit [0] = Reserved. 14.8.61 DRAM Control Register 66 (HW_DRAM_CTL66) This is a DRAM configuration register. Address: 800E_0000h base + 108h offset = 800E_0108h Bit 31 30 29 28 27 26 25 24 23 OBSOLETE R 22 21 20 RSVD2 19 18 17 16 TDFI_CTRLUPD_MIN W Reset Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 RSVD1 TDFI_CTRLUPD_MAX W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL66 field descriptions Field 31-24 OBSOLETE Description Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1243 Programmable Registers HW_DRAM_CTL66 field descriptions (continued) Field Description 23-20 RSVD2 Always write zeroes to this field. 19-16 Holds the DFI tCTRLUPD_MIN timing parameter. READ-ONLY TDFI_ Holds the DFI tctrlupd_min timing parameter. This parameter is read-only. CTRLUPD_MIN 15-14 RSVD1 Always write zeroes to this field. TDFI_ Holds the DFI tCTRLUPD_MAX timing parameter. CTRLUPD_MAX Holds the DFI tctrlupd_max timing parameter. This parameter is read-only. 14.8.62 DRAM Control Register 67 (HW_DRAM_CTL67) This is a DRAM configuration register. Address: 800E_0000h base + 10Ch offset = 800E_010Ch Bit 31 30 29 28 RSVD4 R 0 0 0 26 25 24 23 0 0 0 0 0 22 21 20 19 0 0 0 0 18 17 16 15 TDFI_ DRAM_ CLK_ DISABLE RSVD3 TDFI_DRAM_ CLK_ ENABLE W Reset 27 0 0 0 0 14 13 12 RSVD2 0 0 0 11 10 9 8 7 0 0 0 0 5 4 RSVD1 DRAM_CLK_ ENABLE 0 6 0 0 0 3 2 1 0 TDFI_CTRL_ DELAY 0 0 0 0 0 HW_DRAM_CTL67 field descriptions Field 31-28 RSVD4 27-24 TDFI_DRAM_ CLK_ENABLE 23-19 RSVD3 18-16 TDFI_DRAM_ CLK_DISABLE 15-12 RSVD2 11-8 DRAM_CLK_ ENABLE Description Always write zeroes to this field. Delay from DFI clock enable to memory clock enable. Holds the DFI tdram_clk_enable timing parameter. This parameter is currently unused in the EMI. Always write zeroes to this field. Delay from DFI clock disable to memory clock disable. Holds the DFI tdram_clk_disable timing parameter. This parameter should be programmed with the number of cycles that the PHY requires to disable the clock after the dfi_dram_clk_disable signal is asserted. Always write zeroes to this field. Set value for the dfi_dram_clk_disable signal. Sets value for the DFI output signal dfi_dram_clk_disable. Bit [0] controls CS0, Bit [1] controls CS1. For each bit: 'b0 = Memory clock/s should be disabled. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1244 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL67 field descriptions (continued) Field Description 'b1 = Memory clock/s should be active. 7-4 RSVD1 Always write zeroes to this field. TDFI_CTRL_ DELAY Delay from DFI command to memory command. Holds the DFI tctrl_delay timing parameter. This parameter should be programmed with the number of cycles that the PHY requires to send a power-down or self-refresh command to the DRAM devices. 14.8.63 DRAM Control Register 68 (HW_DRAM_CTL68) This is a DRAM configuration register. Address: 800E_0000h base + 110h offset = 800E_0110h Bit 31 R 30 29 28 27 26 25 RSVD2 Bit R 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 RSVD1 TDFI_PHYUPD_RESP W Reset 23 TDFI_PHYUPD_TYPE0 W Reset 24 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL68 field descriptions Field 31-30 RSVD2 Description Always write zeroes to this field. 29-16 Holds the DFI tPHYUPD_TYPE0 timing parameter. TDFI_PHYUPD_ Holds the DFI tphyupd_typeX timing parameter. This parameter is read-only. TYPE0 15-14 RSVD1 Always write zeroes to this field. TDFI_PHYUPD_ Holds the DFI tPHYUPD_RESP timing parameter. RESP Holds the DFI tphyupd_resp timing parameter. This parameter is read-only. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1245 Programmable Registers 14.8.64 DRAM Control Register 69 (HW_DRAM_CTL69) This is a DRAM configuration register. Address: 800E_0000h base + 114h offset = 800E_0114h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OBSOLETE R 14 13 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 9 8 7 TDFI_PHY_ WRLAT_ BASE RSVD2 W Reset 11 0 0 0 0 0 6 5 4 0 0 2 1 0 TDFI_PHY_ WRLAT RSVD1 0 3 0 0 0 0 0 HW_DRAM_CTL69 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-12 RSVD2 Always write zeroes to this field. 11-8 TDFI_PHY_ WRLAT_BASE Sets DFI base value for the tPHY_WRLAT timing parameter. Used to adjust the tdfi_phy_wrlat parameter for the difference between the PHY's command path delay and data path delay. 'b0000 = Command path delay is 2 cycles shorter than the data path delay. 'b0001 = Command path delay is 1 cycle shorter than the data path delay. 'b0010 = Command path delay and data path delay are equivalent. 'b0011 = Command path delay is 1 cycle longer than the data path delay. 'b0100 = Command path delay is 2 cycles longer than the data path delay. 'b0101 = Command path delay is 3 cycles longer than the data path delay. 'b0110, etc. 7-4 RSVD1 TDFI_PHY_ WRLAT Always write zeroes to this field. Holds the calculated DFI tPHY_WRLAT timing parameter. READ-ONLY Holds the calculated value of the tphy_wrlat timing parameter and is used to adjust the dfi_wrdata_en signal timing. This equation is dependent on the latency setting for the address / control path of the PHY as set in the phy_ctrl_reg_2 [25] parameter bit. If phy_ctrl_reg_2 [25] = 0: If (tdfi_phy_wrlat_base + wrlat_adj) = 2: tdfi_phy_wrlat = reg_dimm_enable If (tdfi_phy_wrlat_base + wrlat_adj) > 2: tdfi_phy_wrlat = tdfi_phy_wrlat_base + wrlat_adj + reg_dimm_enable - WRLAT_WIDTH'h3 Values of (tdfi_phy_wrlat_base + wrlat_adj) < 2 are not supported. If phy_ctrl_reg_2 [25] = 1: Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1246 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL69 field descriptions (continued) Field Description If (tdfi_phy_wrlat_base + wrlat_adj) < 4: tdfi_phy_wrlat = reg_dimm_enable If (tdfi_phy_wrlat_base + wrlat_adj) >= 4: tdfi_phy_wrlat = tdfi_phy_wrlat_base + wrlat_adj + reg_dimm_enable - WRLAT_WIDTH'h4 This parameter is read-only. 14.8.65 DRAM Control Register 70 (HW_DRAM_CTL70) This is a DRAM configuration register. Address: 800E_0000h base + 118h offset = 800E_0118h Bit 31 30 29 28 27 26 25 24 23 OBSOLETE R 22 21 20 19 0 0 0 0 0 0 0 0 0 0 0 17 16 15 TDFI_ RDDATA_ EN_BASE RSVD3 W Reset 18 0 0 0 0 0 14 13 12 0 0 10 9 8 7 TDFI_ RDDATA_EN RSVD2 0 11 0 0 0 0 0 6 5 4 RSVD1 0 0 0 3 2 1 0 TDFI_PHY_ RDLAT 0 0 0 0 0 HW_DRAM_CTL70 field descriptions Field Description 31-24 OBSOLETE Always write zeroes to this field. 23-20 RSVD3 Always write zeroes to this field. 19-16 Sets DFI base value for the tRDDATA_EN timing parameter. TDFI_RDDATA_ Used to adjust the tdfi_rddata_en parameter to account for the desired delay from the read command to EN_BASE the the read data enable signal. The CAS latency is defined in the caslat parameter. The dfi_rddata_en signal can only be sent at a minimum of 1 cycle after the read command. If the programmed value results in a delay less than 1 cycle, this value will be ignored and a delay value of 1 will be used. 'b0000 = Delay from read command to read data enable is equivalent to CAS latency-3. 'b0001 = Delay from read command to read data enable is equivalent to CAS latency-2. 'b0010 = Delay from read command to read data enable is equivalent to CAS latency-1. 'b0011 = Delay from read command to read data enable is equivalent to CAS latency. 'b0100 = Delay from read command to read data enable is equivalent to CAS latency+1. 'b0101 = Delay from read command to read data enable is equivalent to CAS latency+2. 'b0110, etc. 15-12 RSVD2 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1247 Programmable Registers HW_DRAM_CTL70 field descriptions (continued) Field Description 11-8 Holds the calculated DFI tRDDATA_EN timing parameter. READ-ONLY TDFI_RDDATA_ Holds the calculated value of the trddata_en timing parameter. This equation is dependent on the latency EN setting for the address / control path of the PHY as set in the phy_ctrl_reg_2 [25] parameter bit. If phy_ctrl_reg_2 [25] = 0: If (tdfi_rddata_en_base + rdlat_adj) = 2: tdfi_rddata_en = reg_dimm_enable If (tdfi_rddata_en_base + rdlat_adj) > 2: tdfi_rddata_en = tdfi_rddata_en_base + rdlat_adj + reg_dimm_enable - RDLAT_WIDTH'h3 Values of (tdfi_rddata_en_base + rdlat_adj) < 2 are not supported. If phy_ctrl_reg_2 [25] = 1: If (tdfi_rddata_en_base + rdlat_adj) < 4: tdfi_rddata_en = reg_dimm_enable If (tdfi_rddata_en_base + rdlat_adj) >= 4: tdfi_rddata_en = tdfi_rddata_en_base + rdlat_adj + reg_dimm_enable - RDLAT_WIDTH'h4 This parameter is read-only. 7-4 RSVD1 Always write zeroes to this field. TDFI_PHY_ RDLAT Holds the tPHY_RDLAT timing parameter. Holds the tphy_rdlat timing parameter. 14.8.66 DRAM Control Register 71 (HW_DRAM_CTL71) This is a DRAM configuration register. Address: 800E_0000h base + 11Ch offset = 800E_011Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_CTRL_REG_0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL71 field descriptions Field PHY_CTRL_ REG_0_0 Description Controls pad output enable times and other PHY parameters for data slice 0. There is a separate phy_ctrl_reg_0_X parameter for each of the slices of data sent on the DFI data bus. Bit [31] = Enables dynamic termination select in the PHY for the DM pads. 'b0 = Disabled 'b1 = Enabled Bit [29] = Controls termination enable for the DM pads. Set to 'b1 to disable termination. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1248 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL71 field descriptions (continued) Field Description 'b0 = Enabled 'b1 = Disabled Bits [28] = Echo gate control for data slice X. Default 0x0. 'b0 = Uses the dfi_rddata_en signal to create a gate. 'b1 = Creates an echo_gate signal. Bit [27] = Gather FIFO Enable 'b0 = Disabled 'b1 = Enabled Bits [26:24] = Defines the read data delay. Holds the number of cycles to delay the dfi_rddata_en signal prior to enabling the read FIFO. After this delay, the read pointers begin incrementing the read FIFO. Default 0x3. Bit [20] = Sets the pad output enable polarity. Default 0x0. 'b0 = OEN pad 'b1 = OE pad Bit [16] = Subtracts 1/2 cycle from the DQS gate value programmed into phy_ctrl_reg_1_X [2:0] by 1/2 cycle. Default 0x0. This is used when the gate is being aligned to the first DQS, and then is removed to move the gate back into the center of the preamble. This parameter is controlled by the hardware logic when hardware gate training is enabled but should be controlled by software when software leveling is used. 'b0 = Do not adjust 'b1 = Adjust the DQS gate by 1/2 clock forward. Bits [15:12] = Adjusts the starting point of the DQS pad output enable window. Lower numbers pull the rising edge earlier in time, and larger numbers cause the rising edge to be delayed. Each bit changes the output enable time by a 1/4 cycle resolution. Default 0x2. Bits [11:8] = Adjusts the ending point of the DQS pad output enable window. Lower numbers pull the falling edge earlier in time, and larger numbers cause the falling edge to be delayed. Each bit changes the output enable time by a 1/4 cycle resolution. Default 0x7. Bits [6:4] = Adjusts the starting point of the DQ pad output enable window. Lower numbers pull the rising edge earlier in time, and larger numbers cause the rising edge to be delayed. Each bit changes the output enable time by a 1/4 cycle resolution. Default 0x1. Bits [2:0] = Adjusts the ending point of the DQ pad output enable window. Lower numbers pull the falling edge earlier in time, and larger numbers cause the falling edge to be delayed. Each bit changes the output enable time by a 1/4 cycle resolution. Default 0x4. All other bits undefined. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1249 Programmable Registers 14.8.67 DRAM Control Register 72 (HW_DRAM_CTL72) This is a DRAM configuration register. Address: 800E_0000h base + 120h offset = 800E_0120h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_CTRL_REG_0_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL72 field descriptions Field Description PHY_CTRL_ REG_0_1 Controls pad output enable times and other PHY parameters for data slice 1. There is a separate phy_ctrl_reg_0_X parameter for each of the slices of data sent on the DFI data bus. The definition of phy_ctrl_reg_0_X parameter is same for data slice 0~3. 14.8.68 DRAM Control Register 73 (HW_DRAM_CTL73) This is a DRAM configuration register. Address: 800E_0000h base + 124h offset = 800E_0124h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_CTRL_REG_0_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL73 field descriptions Field PHY_CTRL_ REG_0_2 Description Controls pad output enable times and other PHY parameters for data slice 2. Data slice 2 is disabled. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1250 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.69 DRAM Control Register 74 (HW_DRAM_CTL74) This is a DRAM configuration register. Address: 800E_0000h base + 128h offset = 800E_0128h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_CTRL_REG_0_3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL74 field descriptions Field Description PHY_CTRL_ REG_0_3 Controls pad output enable times and other PHY parameters for data slice 3. Data slice 3 is disabled. 14.8.70 DRAM Control Register 75 (HW_DRAM_CTL75) This is a DRAM configuration register. Address: 800E_0000h base + 12Ch offset = 800E_012Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_CTRL_REG_1_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL75 field descriptions Field PHY_CTRL_ REG_1_0 Description Controls pad termination and loopback for data slice 0. There is a separate phy_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus. Bits [31:28] = Defines the pad dynamic termination select enable time. Larger values add greater delay to when tsel turns on. Each bit changes the output enable time by a 1/2 cycle resolution. Bits [27:24] = Defines the pad dynamic termination select disable time. Larger values reduce the delay to when tsel turns off. Each bit changes the output enable time by a 1/2 cycle resolution. Bit [23] = Enables dynamic termination select in the PHY for the DQS pads. 'b0 = Disabled 'b1 = Enabled Bit [22] = Controls the polarity of the tsel signal for the DQS and DM pads. 'b0 = Positive Polarity 'b1 = Negative Polarity i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1251 Programmable Registers HW_DRAM_CTL75 field descriptions (continued) Field Description Bit [21] = Triggers a data return to the EMI. 'b0 = No action 'b1 = Sends loopback data on the dfi_rddata signal. Bit [20] = Selects data output type for phy_obs_reg_0_X [23:8]. 'b0 = Return the expected data. 'b1 = Return the actual data. Bits [19:18] = Loopback control. 'b00 = Normal operational mode. 'b01 = Enables loopback write mode. 'b10 = Stop loopback to check the error register. 'b11 = Clear loopback registers. Bits [17] = Controls the loopback read multiplexer. Bits [16] = Controls the internal write multiplexer. Bits [14:12] = Sets the cycle delay between the LFSR and loopback error check logic. Note that 'h7 is not a valid selection and will result in a false passing result. Bits [10:8] = Gate Error Delay. Allows the user to adjust the length of time from the dfi_rddata_en assertion to the maximum time in which all of the data should have been returned. If the data is not returned in the time expected by the MC, an error condition may occur. This field default value is based on the delay information provided at configuration. Bits [5:4] = Adjusts the closing of the gate. This field default value is based on the delay information provided at configuration. Bits [2:0] = Coarse adjust of gate open time. This value is the number of cycles to delay the dfi_rddata_en signal prior to opening the gate in full cycle increments. Decreasing this value pulls the gate earlier in time. This field, along with the phy_ctrl_reg_0_X [16] bit should be programmed such that the gate signal lands in the valid DQS gate window. 14.8.71 DRAM Control Register 76 (HW_DRAM_CTL76) This is a DRAM configuration register. Address: 800E_0000h base + 130h offset = 800E_0130h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_CTRL_REG_1_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL76 field descriptions Field PHY_CTRL_ REG_1_1 Description Controls pad termination and loopback for data slice 1. There is a separate phy_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1252 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL76 field descriptions (continued) Field Description The definition of phy_ctrl_reg_1_X parameter is same for data slice 0~3. 14.8.72 DRAM Control Register 77 (HW_DRAM_CTL77) This is a DRAM configuration register. Address: 800E_0000h base + 134h offset = 800E_0134h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_CTRL_REG_1_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL77 field descriptions Field Description PHY_CTRL_ REG_1_2 Controls pad termination and loopback for data slice 2. Data slice 2 is disabled. 14.8.73 DRAM Control Register 78 (HW_DRAM_CTL78) This is a DRAM configuration register. Address: 800E_0000h base + 138h offset = 800E_0138h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_CTRL_REG_1_3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL78 field descriptions Field PHY_CTRL_ REG_1_3 Description Controls pad termination and loopback for data slice 3. Data slice 3 is disabled. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1253 Programmable Registers 14.8.74 DRAM Control Register 79 (HW_DRAM_CTL79) This is a DRAM configuration register. Address: 800E_0000h base + 13Ch offset = 800E_013Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_CTRL_REG_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL79 field descriptions Field PHY_CTRL_ REG_2 Description Selects the dfi_rddata_valid delay. Controls PHY functionality. Bit [25] = Selects the address / command path. 'b0 = DFI control signals are captured 1 cycle after being sent from the MC. 'b1 = DFI control signals are captured 1/4 cycle after being sent from the MC. The Low Latency option is not functional at this time. Bit [24] = Selects the write latency path. 'b0 = Write Data is captured 1 cycle after being sent from the MC 'b1 = Write data is captured 1/4 cycle after being sent from the MC. The Low Latency option is not functional at this time. Bit [23] = DFI control for Mobile MCs. Bit [5] = Enables the pad inputs specifically for external loopback. This bit is tied to the internal signal lpbk_rddata_en. 'b0 = Normal Operation 'b1 = Loopback Mode Bit [4] = Enables the pad outputs specifically for external loopback. This bit is tied to the internal signal lpbk_wrdata_en. 'b0 = Normal Operation 'b1 = Loopback Mode Bits [3:0] = Sets the dfi_rddata_valid delay relative to dfi_rddata_en. All other bits undefined. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1254 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.75 DRAM Control Register 80 (HW_DRAM_CTL80) This is a DRAM configuration register. Address: 800E_0000h base + 140h offset = 800E_0140h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 DFT_CTRL_REG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL80 field descriptions Field Description DFT_CTRL_REG Enables the PHY testing mode. Enables the PHY testing mode. Bits [2:1] are used. Bits [2:1] ='b10 = Normal Mode Bits [2:1] ='b01 = Scan Mode Currently Not Functional 14.8.76 DRAM Control Register 81 (HW_DRAM_CTL81) This is a DRAM configuration register. Address: 800E_0000h base + 144h offset = 800E_0144h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OBSOLETE R 15 14 13 RSVD2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 11 10 9 8 OCD_ADJUST_ PUP_CS_0 0 0 0 0 0 7 RSVD1 0 0 0 OCD_ADJUST_ PDN_CS_0 0 0 0 0 0 HW_DRAM_CTL81 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-13 RSVD2 Always write zeroes to this field. 12-8 OCD pull-up adjust setting for DRAMs for chip select 0. OCD_ADJUST_ This parameter is reserved for future use and should be programmed to 0x0. PUP_CS_0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1255 Programmable Registers HW_DRAM_CTL81 field descriptions (continued) Field Description 7-5 RSVD1 Always write zeroes to this field. OCD_ADJUST_ OCD pull-down adjust setting for DRAMs for chip select 0. PDN_CS_0 This parameter is reserved for future use and should be programmed to 0x0. 14.8.77 DRAM Control Register 82 (HW_DRAM_CTL82) This is a DRAM configuration register. Address: 800E_0000h base + 148h offset = 800E_0148h Bit 31 30 29 28 27 26 25 22 21 20 19 18 17 16 ODT_ALT_EN OBSOLETE W Bit 23 RSVD1 R Reset 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 OBSOLETE R W Reset 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL82 field descriptions Field 31-25 RSVD1 24 ODT_ALT_EN Description Always write zeroes to this field. Enable use of non-DFI odt_alt signal. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1256 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL82 field descriptions (continued) Field Description Enables the use of the non-DFI compliant alternative ODT internal signal odt_alt, which is externally viewed as the signal reserved0. This signal is only required if the user intends to use a CAS latency of 3 with ODT support. The user will need to modify the dram_asic.v file for this support. 'b0 = ODT support with CAS latency 3 is not supported. 'b1 = ODT support with CAS latency 3 is supported but is not DFI compliant. This disables the interrupt bit for ODT-with-CAS3 and disables the OVL error. OBSOLETE Always write zeroes to this field. 14.8.78 DRAM Control Register 83 (HW_DRAM_CTL83) This is a DRAM configuration register. Address: 800E_0000h base + 14Ch offset = 800E_014Ch Bit 31 30 29 28 RSVD4 R 0 0 0 26 25 24 23 0 0 0 0 0 22 21 20 19 RSVD3 ODT_RD_ MAP_CS3 W Reset 27 0 0 0 18 17 16 15 0 0 0 0 13 12 RSVD2 ODT_RD_ MAP_CS2 0 14 0 0 0 11 10 9 8 7 0 0 0 0 5 4 RSVD1 ODT_RD_ MAP_CS1 0 6 0 0 0 3 2 1 0 ODT_RD_ MAP_CS0 0 0 0 0 0 HW_DRAM_CTL83 field descriptions Field 31-28 RSVD4 Description Always write zeroes to this field. 27-24 Determines which chip(s) will have termination when a read occurs on chip 3. ODT_RD_MAP_ Sets up which (if any) chip(s) will have their ODT termination active while a read occurs on chip select X. CS3 EMI will define this parameter at default for internal testing. The user is required is to change this setting to meet system specifications. Example: If the system consists of 4 chip selects and odt_rd_map_cs0 is set to 'b0010, then when CS0 is performing a read, CS1 will have active ODT termination. And if odt_rd_map_cs0 was set to 'b1000, then instead CS3 would be active. Bit [3] = CS3 will have active ODT termination when chip select X is performing a read. Bit [2] = CS2 will have active ODT termination when chip select X is performing a read. Bit [1] = CS1 will have active ODT termination when chip select X is performing a read. Bit [0] = CS0 will have active ODT termination when chip select X is performing a read. Etc. 23-20 RSVD3 Always write zeroes to this field. 19-16 Determines which chip(s) will have termination when a read occurs on chip 2. ODT_RD_MAP_ Sets up which (if any) chip(s) will have their ODT termination active while a read occurs on chip select X. CS2 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1257 Programmable Registers HW_DRAM_CTL83 field descriptions (continued) Field Description EMI will define this parameter at default for internal testing. The user is required is to change this setting to meet system specifications. Example: If the system consists of 4 chip selects and odt_rd_map_cs0 is set to 'b0010, then when CS0 is performing a read, CS1 will have active ODT termination. And if odt_rd_map_cs0 was set to 'b1000, then instead CS3 would be active. Bit [3] = CS3 will have active ODT termination when chip select X is performing a read. Bit [2] = CS2 will have active ODT termination when chip select X is performing a read. Bit [1] = CS1 will have active ODT termination when chip select X is performing a read. Bit [0] = CS0 will have active ODT termination when chip select X is performing a read. Etc. 15-12 RSVD2 Always write zeroes to this field. 11-8 Determines which chip(s) will have termination when a read occurs on chip 1. ODT_RD_MAP_ Sets up which (if any) chip(s) will have their ODT termination active while a read occurs on chip select X. CS1 EMI will define this parameter at default for internal testing. The user is required is to change this setting to meet system specifications. Example: If the system consists of 4 chip selects and odt_rd_map_cs0 is set to 'b0010, then when CS0 is performing a read, CS1 will have active ODT termination. And if odt_rd_map_cs0 was set to 'b1000, then instead CS3 would be active. Bit [3] = CS3 will have active ODT termination when chip select X is performing a read. Bit [2] = CS2 will have active ODT termination when chip select X is performing a read. Bit [1] = CS1 will have active ODT termination when chip select X is performing a read. Bit [0] = CS0 will have active ODT termination when chip select X is performing a read. Etc. 7-4 RSVD1 Always write zeroes to this field. ODT_RD_MAP_ Determines which chip(s) will have termination when a read occurs on chip 0. CS0 Sets up which (if any) chip(s) will have their ODT termination active while a read occurs on chip select X. EMI will define this parameter at default for internal testing. The user is required is to change this setting to meet system specifications. Example: If the system consists of 4 chip selects and odt_rd_map_cs0 is set to 'b0010, then when CS0 is performing a read, CS1 will have active ODT termination. And if odt_rd_map_cs0 was set to 'b1000, then instead CS3 would be active. Bit [3] = CS3 will have active ODT termination when chip select X is performing a read. Bit [2] = CS2 will have active ODT termination when chip select X is performing a read. Bit [1] = CS1 will have active ODT termination when chip select X is performing a read. Bit [0] = CS0 will have active ODT termination when chip select X is performing a read. Etc. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1258 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.79 DRAM Control Register 84 (HW_DRAM_CTL84) This is a DRAM configuration register. Address: 800E_0000h base + 150h offset = 800E_0150h Bit 31 30 29 28 RSVD4 R 0 0 0 26 25 24 23 0 0 0 0 0 22 21 20 19 RSVD3 ODT_WR_ MAP_CS3 W Reset 27 0 0 0 18 17 16 15 0 0 0 0 13 12 RSVD2 ODT_WR_ MAP_CS2 0 14 0 0 0 11 10 9 8 7 0 0 0 0 5 4 RSVD1 ODT_WR_ MAP_CS1 0 6 0 0 0 3 2 1 0 ODT_WR_ MAP_CS0 0 0 0 0 0 HW_DRAM_CTL84 field descriptions Field 31-28 RSVD4 Description Always write zeroes to this field. 27-24 Determines which chip(s) will have termination when a write occurs on chip 3. ODT_WR_MAP_ Sets up which (if any) chip(s) will have their ODT termination active while a write occurs on chip select X. CS3 EMI will define this parameter at default for internal testing. The user is required is to change this setting to meet system specifications. Example: If the system consists of 4 chip selects and odt_wr_map_cs0 is set to 'b0010, then when CS0 is performing a write, CS1 will have active ODT termination. And if odt_wr_map_cs0 was set to 'b1000, then instead CS3 would be active. Bit [3] = CS3 will have active ODT termination when chip select X is performing a write. Bit [2] = CS2 will have active ODT termination when chip select X is performing a write. Bit [1] = CS1 will have active ODT termination when chip select X is performing a write. Bit [0] = CS0 will have active ODT termination when chip select X is performing a write. Etc. 23-20 RSVD3 Always write zeroes to this field. 19-16 Determines which chip(s) will have termination when a write occurs on chip 2. ODT_WR_MAP_ Sets up which (if any) chip(s) will have their ODT termination active while a write occurs on chip select X. CS2 EMI will define this parameter at default for internal testing. The user is required is to change this setting to meet system specifications. Example: If the system consists of 4 chip selects and odt_wr_map_cs0 is set to 'b0010, then when CS0 is performing a write, CS1 will have active ODT termination. And if odt_wr_map_cs0 was set to 'b1000, then instead CS3 would be active. Bit [3] = CS3 will have active ODT termination when chip select X is performing a write. Bit [2] = CS2 will have active ODT termination when chip select X is performing a write. Bit [1] = CS1 will have active ODT termination when chip select X is performing a write. Bit [0] = CS0 will have active ODT termination when chip select X is performing a write. Etc. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1259 Programmable Registers HW_DRAM_CTL84 field descriptions (continued) Field Description 15-12 RSVD2 Always write zeroes to this field. 11-8 Determines which chip(s) will have termination when a write occurs on chip 1. ODT_WR_MAP_ Sets up which (if any) chip(s) will have their ODT termination active while a write occurs on chip select X. CS1 EMI will define this parameter at default for internal testing. The user is required is to change this setting to meet system specifications. Example: If the system consists of 4 chip selects and odt_wr_map_cs0 is set to 'b0010, then when CS0 is performing a write, CS1 will have active ODT termination. And if odt_wr_map_cs0 was set to 'b1000, then instead CS3 would be active. Bit [3] = CS3 will have active ODT termination when chip select X is performing a write. Bit [2] = CS2 will have active ODT termination when chip select X is performing a write. Bit [1] = CS1 will have active ODT termination when chip select X is performing a write. Bit [0] = CS0 will have active ODT termination when chip select X is performing a write. Etc. 7-4 RSVD1 Always write zeroes to this field. ODT_WR_MAP_ Determines which chip(s) will have termination when a write occurs on chip 0. CS0 Sets up which (if any) chip(s) will have their ODT termination active while a write occurs on chip select X. EMI will define this parameter at default for internal testing. The user is required is to change this setting to meet system specifications. Example: If the system consists of 4 chip selects and odt_wr_map_cs0 is set to 'b0010, then when CS0 is performing a write, CS1 will have active ODT termination. And if odt_wr_map_cs0 was set to 'b1000, then instead CS3 would be active. Bit [3] = CS3 will have active ODT termination when chip select X is performing a write. Bit [2] = CS2 will have active ODT termination when chip select X is performing a write. Bit [1] = CS1 will have active ODT termination when chip select X is performing a write. Bit [0] = CS0 will have active ODT termination when chip select X is performing a write. Etc. 14.8.80 DRAM Control Register 85 (HW_DRAM_CTL85) This is a DRAM configuration register. Address: 800E_0000h base + 154h offset = 800E_0154h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAD_CTRL_REG_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1260 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL85 field descriptions Field Description PAD_CTRL_ REG_0 Controls pad termination, type and IDDQ settings. These bit settings are specific to the pad models included with this PHY. The user should alter the programming relative to the particular pads being used in their design. EMI provides a dynamic termination signal tsel that provides one bit per byte of memory data. The user must attach this signal to the pads dependent on pad requirements. Bit [12] = Defines the pad impedance if the parallel termination option is enabled. Default 'b1. 'b0 = 75 Ohm 'b1 = 150 Ohm Bit [8] = Defines the pad type. Default 'b1. 'b0 = DDR1 'b1 = DDR2 Bit [5] = Defines the IDDQ_RX select for the signal pads. Default 'b1. 'b0 = Do not feed input into IDDQ 'b1 = Feed input into IDDQ Bit [4] = Defines the IDDQ_TX select for the signal pads. Default 'b1. 'b0 = Do not feed output into IDDQ 'b1 = Feed output into IDDQ Bit [1] = Defines the IDDQ_RX select for the clock pads. Default 'b1. 'b0 = Do not feed input into IDDQ 'b1 = Feed input into IDDQ Bit [0] = Defines the IDDQ_TX select for the clock pads. Default 'b1. 'b0 = Do not feed output into IDDQ 'b1 = Feed output into IDDQ All other bits Reserved. 14.8.81 DRAM Control Register 86 (HW_DRAM_CTL86) This is a DRAM configuration register. Address: 800E_0000h base + 158h offset = 800E_0158h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OBSOLETE R 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 VERSION W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1261 Programmable Registers HW_DRAM_CTL86 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. VERSION Controller version number. READ-ONLY Holds the EMI version number for this controller. This parameter is read-only. 14.8.82 DRAM Control Register 87 (HW_DRAM_CTL87) This is a DRAM configuration register. Address: 800E_0000h base + 15Ch offset = 800E_015Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_CTRL_REG_0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL87 field descriptions Field DLL_CTRL_ REG_0_0 Description Controls the DLL bypass logic and holds the DLL start point and read DQS delay settings for data slice 0. There is a separate dll_ctrl_reg_0_X parameters for each of the slices of data sent on the DFI data bus. Bit [28] = DLL Bypass Control. 'b0 = Normal operational mode. In this mode, the DLL uses dll_ctrl_reg_0_X [14:8] for the read DQS and dll_ctrl_reg_1_X [14:8] for clk_wr. 'b1 = Bypass Mode is on. In this mode, the DLL uses dll_ctrl_reg_0_X [23:15] for the read DQS and dll_ctrl_reg_1_X [23:15] for clk_wr. Bits [23:15] = Holds the read DQS delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X [28] = 'b1) Bits [14:8] = Holds the read DQS delay setting when the DLL is operating in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value is 1/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle. Bits [7:0] = DLL Start Point Control. This value is loaded into the DLL at initialization and is the value at which the DLL will begin searching for a lock. Each increment of this field represents 1/128th of a clock cycle. This value MUST be >= 3. All other bits undefined. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1262 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.83 DRAM Control Register 88 (HW_DRAM_CTL88) This is a DRAM configuration register. Address: 800E_0000h base + 160h offset = 800E_0160h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_CTRL_REG_0_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL88 field descriptions Field Description DLL_CTRL_ REG_0_1 Controls the DLL bypass logic and holds the DLL start point and read DQS delay settings for data slice 1. There is a separate dll_ctrl_reg_0_X parameters for each of the slices of data sent on the DFI data bus. Bit [28] = DLL Bypass Control. 'b0 = Normal operational mode. In this mode, the DLL uses dll_ctrl_reg_0_X [14:8] for the read DQS and dll_ctrl_reg_1_X [14:8] for clk_wr. 'b1 = Bypass Mode is on. In this mode, the DLL uses dll_ctrl_reg_0_X [23:15] for the read DQS and dll_ctrl_reg_1_X [23:15] for clk_wr. Bits [23:15] = Holds the read DQS delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X [28] = 'b1) Bits [14:8] = Holds the read DQS delay setting when the DLL is operating in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value is 1/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle. Bits [7:0] = DLL Start Point Control. This value is loaded into the DLL at initialization and is the value at which the DLL will begin searching for a lock. Each increment of this field represents 1/128th of a clock cycle. This value MUST be >= 3. All other bits undefined. 14.8.84 DRAM Control Register 89 (HW_DRAM_CTL89) This is a DRAM configuration register. Address: 800E_0000h base + 164h offset = 800E_0164h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_CTRL_REG_0_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1263 Programmable Registers HW_DRAM_CTL89 field descriptions Field Description DLL_CTRL_ REG_0_2 Controls the DLL bypass logic and holds the DLL start point and read DQS delay settings for data slice 2. There is a separate dll_ctrl_reg_0_X parameters for each of the slices of data sent on the DFI data bus. Bit [28] = DLL Bypass Control. 'b0 = Normal operational mode. In this mode, the DLL uses dll_ctrl_reg_0_X [14:8] for the read DQS and dll_ctrl_reg_1_X [14:8] for clk_wr. 'b1 = Bypass Mode is on. In this mode, the DLL uses dll_ctrl_reg_0_X [23:15] for the read DQS and dll_ctrl_reg_1_X [23:15] for clk_wr. Bits [23:15] = Holds the read DQS delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X [28] = 'b1) Bits [14:8] = Holds the read DQS delay setting when the DLL is operating in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value is 1/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle. Bits [7:0] = DLL Start Point Control. This value is loaded into the DLL at initialization and is the value at which the DLL will begin searching for a lock. Each increment of this field represents 1/128th of a clock cycle. This value MUST be >= 3. All other bits undefined. 14.8.85 DRAM Control Register 90 (HW_DRAM_CTL90) This is a DRAM configuration register. Address: 800E_0000h base + 168h offset = 800E_0168h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_CTRL_REG_0_3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL90 field descriptions Field DLL_CTRL_ REG_0_3 Description Controls the DLL bypass logic and holds the DLL start point and read DQS delay settings for data slice 3. There is a separate dll_ctrl_reg_0_X parameters for each of the slices of data sent on the DFI data bus. Bit [28] = DLL Bypass Control. 'b0 = Normal operational mode. In this mode, the DLL uses dll_ctrl_reg_0_X [14:8] for the read DQS and dll_ctrl_reg_1_X [14:8] for clk_wr. 'b1 = Bypass Mode is on. In this mode, the DLL uses dll_ctrl_reg_0_X [23:15] for the read DQS and dll_ctrl_reg_1_X [23:15] for clk_wr. Bits [23:15] = Holds the read DQS delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X [28] = 'b1) Bits [14:8] = Holds the read DQS delay setting when the DLL is operating in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value is 1/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1264 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL90 field descriptions (continued) Field Description Bits [7:0] = DLL Start Point Control. This value is loaded into the DLL at initialization and is the value at which the DLL will begin searching for a lock. Each increment of this field represents 1/128th of a clock cycle. This value MUST be >= 3. All other bits undefined. 14.8.86 DRAM Control Register 91 (HW_DRAM_CTL91) This is a DRAM configuration register. Address: 800E_0000h base + 16Ch offset = 800E_016Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_CTRL_REG_1_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL91 field descriptions Field Description DLL_CTRL_ REG_1_0 Holds the clk_wr settings and the Dll increment value for data slice 0. There is a separate dll_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus. Bits [23:15] = Holds the clk_wr delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X [28] = 'b1) Each increment of this field represents 1/128th of a clock cycle. Bits [14:8] = Holds the clk_wr delay setting in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value is 3/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle. Bits [7:0] = DLL Increment Value. This sets the increment used by the DLL when searching for a lock. It is recommended to keep this field small (around 0x4) to keep the steps gradual. All other bits undefined. 14.8.87 DRAM Control Register 92 (HW_DRAM_CTL92) This is a DRAM configuration register. Address: 800E_0000h base + 170h offset = 800E_0170h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_CTRL_REG_1_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1265 Programmable Registers HW_DRAM_CTL92 field descriptions Field Description DLL_CTRL_ REG_1_1 Holds the clk_wr settings and the Dll increment value for data slice 1. There is a separate dll_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus. Bits [23:15] = Holds the clk_wr delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X [28] = 'b1) Each increment of this field represents 1/128th of a clock cycle. Bits [14:8] = Holds the clk_wr delay setting in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value is 3/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle. Bits [7:0] = DLL Increment Value. This sets the increment used by the DLL when searching for a lock. It is recommended to keep this field small (around 0x4) to keep the steps gradual. All other bits undefined. 14.8.88 DRAM Control Register 93 (HW_DRAM_CTL93) This is a DRAM configuration register. Address: 800E_0000h base + 174h offset = 800E_0174h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_CTRL_REG_1_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL93 field descriptions Field DLL_CTRL_ REG_1_2 Description Holds the clk_wr settings and the Dll increment value for data slice 2. There is a separate dll_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus. Bits [23:15] = Holds the clk_wr delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X [28] = 'b1) Each increment of this field represents 1/128th of a clock cycle. Bits [14:8] = Holds the clk_wr delay setting in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value is 3/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle. Bits [7:0] = DLL Increment Value. This sets the increment used by the DLL when searching for a lock. It is recommended to keep this field small (around 0x4) to keep the steps gradual. All other bits undefined. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1266 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.89 DRAM Control Register 94 (HW_DRAM_CTL94) This is a DRAM configuration register. Address: 800E_0000h base + 178h offset = 800E_0178h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_CTRL_REG_1_3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL94 field descriptions Field Description DLL_CTRL_ REG_1_3 Holds the clk_wr settings and the Dll increment value for data slice 3. There is a separate dll_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus. Bits [23:15] = Holds the clk_wr delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X [28] = 'b1) Each increment of this field represents 1/128th of a clock cycle. Bits [14:8] = Holds the clk_wr delay setting in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value is 3/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle. Bits [7:0] = DLL Increment Value. This sets the increment used by the DLL when searching for a lock. It is recommended to keep this field small (around 0x4) to keep the steps gradual. All other bits undefined. 14.8.90 DRAM Control Register 95 (HW_DRAM_CTL95) This is a DRAM configuration register. Address: 800E_0000h base + 17Ch offset = 800E_017Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_0_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL95 field descriptions Field Description DLL_OBS_REG_ Reports the lock status and the encoder value for data slice 0. READ-ONLY 0_0 There is a separate dll_obs_reg_0_X parameter for each of the slices of data sent on the DFI data bus. Bits [31:1] = Reports the DLL encoder value from the master DLL to the slave DLL's. The slaves use this value to set up their delays for the clk_wr and read DQS signals. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1267 Programmable Registers HW_DRAM_CTL95 field descriptions (continued) Field Description Bit [0] = DLL Lock Indicator. 'b0 = DLL has not locked. 'b1 = DLL is locked. 14.8.91 DRAM Control Register 96 (HW_DRAM_CTL96) This is a DRAM configuration register. Address: 800E_0000h base + 180h offset = 800E_0180h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_0_1 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL96 field descriptions Field Description DLL_OBS_REG_ Reports the lock status and the encoder value for data slice 1. READ-ONLY 0_1 There is a separate dll_obs_reg_0_X parameter for each of the slices of data sent on the DFI data bus. Bits [31:1] = Reports the DLL encoder value from the master DLL to the slave DLL's. The slaves use this value to set up their delays for the clk_wr and read DQS signals. Bit [0] = DLL Lock Indicator. 'b0 = DLL has not locked. 'b1 = DLL is locked. 14.8.92 DRAM Control Register 97 (HW_DRAM_CTL97) This is a DRAM configuration register. Address: 800E_0000h base + 184h offset = 800E_0184h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_0_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1268 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL97 field descriptions Field Description DLL_OBS_REG_ Reports the lock status and the encoder value for data slice 2. READ-ONLY 0_2 There is a separate dll_obs_reg_0_X parameter for each of the slices of data sent on the DFI data bus. Bits [31:1] = Reports the DLL encoder value from the master DLL to the slave DLL's. The slaves use this value to set up their delays for the clk_wr and read DQS signals. Bit [0] = DLL Lock Indicator. 'b0 = DLL has not locked. 'b1 = DLL is locked. 14.8.93 DRAM Control Register 98 (HW_DRAM_CTL98) This is a DRAM configuration register. Address: 800E_0000h base + 188h offset = 800E_0188h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_0_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL98 field descriptions Field Description DLL_OBS_REG_ Reports the lock status and the encoder value for data slice 3. READ-ONLY 0_3 There is a separate dll_obs_reg_0_X parameter for each of the slices of data sent on the DFI data bus. Bits [31:1] = Reports the DLL encoder value from the master DLL to the slave DLL's. The slaves use this value to set up their delays for the clk_wr and read DQS signals. Bit [0] = DLL Lock Indicator. 'b0 = DLL has not locked. 'b1 = DLL is locked. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1269 Programmable Registers 14.8.94 DRAM Control Register 99 (HW_DRAM_CTL99) This is a DRAM configuration register. Address: 800E_0000h base + 18Ch offset = 800E_018Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_OBS_REG_0_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL99 field descriptions Field PHY_OBS_ REG_0_0 Description Controls loopback status, data and masking info for slice 0. READ-ONLY Reports status for the PHY. Bit [24] = Status signal to indicate that the logic gate had to be forced closed. 'b0 = Normal operation 'b1 = Gate close was forced Bits [23:8] = Loopback data. Reports the actual data or expected data, depending on the setting of the phy_ctrl_reg_1_X [20] parameter bit. Bits [5:4] = Loopback mask data. Reports the actual data mask or the expected data mask, depending on the setting of the phy_ctrl_reg_1_X [20] parameter bit. Bit [1] = Reports status of loopback errors. 'b0 = Last Loopback test had no errors. 'b1 = Last Loopback test contained data errors. Bit [0] = Defines the status of the loopback mode. 'b0 = Not in loopback mode. 'b1 = In Loopback mode. All other bits Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1270 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.95 DRAM Control Register 100 (HW_DRAM_CTL100) This is a DRAM configuration register. Address: 800E_0000h base + 190h offset = 800E_0190h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_OBS_REG_0_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL100 field descriptions Field PHY_OBS_ REG_0_1 Description Controls loopback status, data and masking info for slice 1. READ-ONLY Reports status for the PHY. Bit [24] = Status signal to indicate that the logic gate had to be forced closed. 'b0 = Normal operation 'b1 = Gate close was forced Bits [23:8] = Loopback data. Reports the actual data or expected data, depending on the setting of the phy_ctrl_reg_1_X [20] parameter bit. Bits [5:4] = Loopback mask data. Reports the actual data mask or the expected data mask, depending on the setting of the phy_ctrl_reg_1_X [20] parameter bit. Bit [1] = Reports status of loopback errors. 'b0 = Last Loopback test had no errors. 'b1 = Last Loopback test contained data errors. Bit [0] = Defines the status of the loopback mode. 'b0 = Not in loopback mode. 'b1 = In Loopback mode. All other bits Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1271 Programmable Registers 14.8.96 DRAM Control Register 101 (HW_DRAM_CTL101) This is a DRAM configuration register. Address: 800E_0000h base + 194h offset = 800E_0194h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_OBS_REG_0_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL101 field descriptions Field PHY_OBS_ REG_0_2 Description Controls loopback status, data and masking info for slice 2. READ-ONLY Reports status for the PHY. Bit [24] = Status signal to indicate that the logic gate had to be forced closed. 'b0 = Normal operation 'b1 = Gate close was forced Bits [23:8] = Loopback data. Reports the actual data or expected data, depending on the setting of the phy_ctrl_reg_1_X [20] parameter bit. Bits [5:4] = Loopback mask data. Reports the actual data mask or the expected data mask, depending on the setting of the phy_ctrl_reg_1_X [20] parameter bit. Bit [1] = Reports status of loopback errors. 'b0 = Last Loopback test had no errors. 'b1 = Last Loopback test contained data errors. Bit [0] = Defines the status of the loopback mode. 'b0 = Not in loopback mode. 'b1 = In Loopback mode. All other bits Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1272 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.97 DRAM Control Register 102 (HW_DRAM_CTL102) This is a DRAM configuration register. Address: 800E_0000h base + 198h offset = 800E_0198h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHY_OBS_REG_0_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL102 field descriptions Field PHY_OBS_ REG_0_3 Description Controls loopback status, data and masking info for slice 3. READ-ONLY Reports status for the PHY. Bit [24] = Status signal to indicate that the logic gate had to be forced closed. 'b0 = Normal operation 'b1 = Gate close was forced Bits [23:8] = Loopback data. Reports the actual data or expected data, depending on the setting of the phy_ctrl_reg_1_X [20] parameter bit. Bits [5:4] = Loopback mask data. Reports the actual data mask or the expected data mask, depending on the setting of the phy_ctrl_reg_1_X [20] parameter bit. Bit [1] = Reports status of loopback errors. 'b0 = Last Loopback test had no errors. 'b1 = Last Loopback test contained data errors. Bit [0] = Defines the status of the loopback mode. 'b0 = Not in loopback mode. 'b1 = In Loopback mode. All other bits Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1273 Programmable Registers 14.8.98 DRAM Control Register 103 (HW_DRAM_CTL103) This is a DRAM configuration register. Address: 800E_0000h base + 19Ch offset = 800E_019Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_0 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL103 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 0. READ-ONLY. 1_0 14.8.99 DRAM Control Register 104 (HW_DRAM_CTL104) This is a DRAM configuration register. Address: 800E_0000h base + 1A0h offset = 800E_01A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL104 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 0. READ-ONLY. 1_0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1274 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.100 DRAM Control Register 105 (HW_DRAM_CTL105) This is a DRAM configuration register. Address: 800E_0000h base + 1A4h offset = 800E_01A4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL105 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 0. READ-ONLY. 1_0 14.8.101 DRAM Control Register 106 (HW_DRAM_CTL106) This is a DRAM configuration register. Address: 800E_0000h base + 1A8h offset = 800E_01A8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL106 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 0. READ-ONLY. 1_0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1275 Programmable Registers 14.8.102 DRAM Control Register 107 (HW_DRAM_CTL107) This is a DRAM configuration register. Address: 800E_0000h base + 1ACh offset = 800E_01ACh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 OBSOLETE R 12 11 10 9 8 7 RSVD1 6 5 4 3 2 1 0 DLL_OBS_REG_1_0 W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL107 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports master DLL info for delay line 0. READ-ONLY. 1_0 14.8.103 DRAM Control Register 108 (HW_DRAM_CTL108) This is a DRAM configuration register. Address: 800E_0000h base + 1B0h offset = 800E_01B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL108 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 1. READ-ONLY. 1_1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1276 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.104 DRAM Control Register 109 (HW_DRAM_CTL109) This is a DRAM configuration register. Address: 800E_0000h base + 1B4h offset = 800E_01B4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL109 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 1. READ-ONLY. 1_1 14.8.105 DRAM Control Register 110 (HW_DRAM_CTL110) This is a DRAM configuration register. Address: 800E_0000h base + 1B8h offset = 800E_01B8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL110 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 1. READ-ONLY. 1_1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1277 Programmable Registers 14.8.106 DRAM Control Register 111 (HW_DRAM_CTL111) This is a DRAM configuration register. Address: 800E_0000h base + 1BCh offset = 800E_01BCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 DLL_OBS_REG_1_1 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL111 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 1. READ-ONLY. 1_1 14.8.107 DRAM Control Register 112 (HW_DRAM_CTL112) This is a DRAM configuration register. Address: 800E_0000h base + 1C0h offset = 800E_01C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 OBSOLETE R 12 11 10 9 8 7 RSVD1 6 5 DLL_OBS_REG_1_1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL112 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports master DLL info for delay line 1. READ-ONLY. 1_1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1278 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.108 DRAM Control Register 113 (HW_DRAM_CTL113) This is a DRAM configuration register. Address: 800E_0000h base + 1C4h offset = 800E_01C4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL113 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 2. READ-ONLY. 1_2 14.8.109 DRAM Control Register 114 (HW_DRAM_CTL114) This is a DRAM configuration register. Address: 800E_0000h base + 1C8h offset = 800E_01C8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL114 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 2. READ-ONLY. 1_2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1279 Programmable Registers 14.8.110 DRAM Control Register 115 (HW_DRAM_CTL115) This is a DRAM configuration register. Address: 800E_0000h base + 1CCh offset = 800E_01CCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_2 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL115 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 2. READ-ONLY. 1_2 14.8.111 DRAM Control Register 116 (HW_DRAM_CTL116) This is a DRAM configuration register. Address: 800E_0000h base + 1D0h offset = 800E_01D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL116 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 2. READ-ONLY. 1_2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1280 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.112 DRAM Control Register 117 (HW_DRAM_CTL117) This is a DRAM configuration register. Address: 800E_0000h base + 1D4h offset = 800E_01D4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 OBSOLETE R 12 11 10 9 8 7 RSVD1 6 5 4 3 2 1 0 DLL_OBS_REG_1_2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL117 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports master DLL info for delay line 2. READ-ONLY. 1_2 14.8.113 DRAM Control Register 118 (HW_DRAM_CTL118) This is a DRAM configuration register. Address: 800E_0000h base + 1D8h offset = 800E_01D8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL118 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 3. READ-ONLY. 1_3 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1281 Programmable Registers 14.8.114 DRAM Control Register 119 (HW_DRAM_CTL119) This is a DRAM configuration register. Address: 800E_0000h base + 1DCh offset = 800E_01DCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_3 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL119 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 3. READ-ONLY. 1_3 14.8.115 DRAM Control Register 120 (HW_DRAM_CTL120) This is a DRAM configuration register. Address: 800E_0000h base + 1E0h offset = 800E_01E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_1_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL120 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 3. READ-ONLY. 1_3 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1282 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.116 DRAM Control Register 121 (HW_DRAM_CTL121) This is a DRAM configuration register. Address: 800E_0000h base + 1E4h offset = 800E_01E4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 DLL_OBS_REG_1_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL121 field descriptions Field Description DLL_OBS_REG_ Reports master DLL info for delay line 3. READ-ONLY. 1_3 14.8.117 DRAM Control Register 122 (HW_DRAM_CTL122) This is a DRAM configuration register. Address: 800E_0000h base + 1E8h offset = 800E_01E8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 OBSOLETE R 12 11 10 9 8 7 RSVD1 6 5 DLL_OBS_REG_1_3 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL122 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports master DLL info for delay line 3. READ-ONLY. 1_3 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1283 Programmable Registers 14.8.118 DRAM Control Register 123 (HW_DRAM_CTL123) This is a DRAM configuration register. Address: 800E_0000h base + 1ECh offset = 800E_01ECh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_0 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL123 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 0. READ-ONLY. 2_0 14.8.119 DRAM Control Register 124 (HW_DRAM_CTL124) This is a DRAM configuration register. Address: 800E_0000h base + 1F0h offset = 800E_01F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL124 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 0. READ-ONLY. 2_0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1284 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.120 DRAM Control Register 125 (HW_DRAM_CTL125) This is a DRAM configuration register. Address: 800E_0000h base + 1F4h offset = 800E_01F4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL125 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 0. READ-ONLY. 2_0 14.8.121 DRAM Control Register 126 (HW_DRAM_CTL126) This is a DRAM configuration register. Address: 800E_0000h base + 1F8h offset = 800E_01F8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL126 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 0. READ-ONLY. 2_0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1285 Programmable Registers 14.8.122 DRAM Control Register 127 (HW_DRAM_CTL127) This is a DRAM configuration register. Address: 800E_0000h base + 1FCh offset = 800E_01FCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 OBSOLETE R 13 12 11 10 9 8 7 RSVD1 6 5 4 3 2 1 0 DLL_OBS_REG_2_0 W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL127 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports the read DQS delay value for data slice 0. READ-ONLY. 2_0 14.8.123 DRAM Control Register 128 (HW_DRAM_CTL128) This is a DRAM configuration register. Address: 800E_0000h base + 200h offset = 800E_0200h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL128 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 1. READ-ONLY. 2_1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1286 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.124 DRAM Control Register 129 (HW_DRAM_CTL129) This is a DRAM configuration register. Address: 800E_0000h base + 204h offset = 800E_0204h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL129 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 1. READ-ONLY. 2_1 14.8.125 DRAM Control Register 130 (HW_DRAM_CTL130) This is a DRAM configuration register. Address: 800E_0000h base + 208h offset = 800E_0208h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL130 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 1. READ-ONLY. 2_1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1287 Programmable Registers 14.8.126 DRAM Control Register 131 (HW_DRAM_CTL131) This is a DRAM configuration register. Address: 800E_0000h base + 20Ch offset = 800E_020Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 DLL_OBS_REG_2_1 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL131 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 1. READ-ONLY. 2_1 14.8.127 DRAM Control Register 132 (HW_DRAM_CTL132) This is a DRAM configuration register. Address: 800E_0000h base + 210h offset = 800E_0210h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 OBSOLETE R 13 12 11 10 9 8 7 RSVD1 6 5 DLL_OBS_REG_2_1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL132 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports the read DQS delay value for data slice 1. READ-ONLY. 2_1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1288 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.128 DRAM Control Register 133 (HW_DRAM_CTL133) This is a DRAM configuration register. Address: 800E_0000h base + 214h offset = 800E_0214h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL133 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 2. READ-ONLY. 2_2 14.8.129 DRAM Control Register 134 (HW_DRAM_CTL134) This is a DRAM configuration register. Address: 800E_0000h base + 218h offset = 800E_0218h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL134 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 2. READ-ONLY. 2_2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1289 Programmable Registers 14.8.130 DRAM Control Register 135 (HW_DRAM_CTL135) This is a DRAM configuration register. Address: 800E_0000h base + 21Ch offset = 800E_021Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_2 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL135 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 2. READ-ONLY. 2_2 14.8.131 DRAM Control Register 136 (HW_DRAM_CTL136) This is a DRAM configuration register. Address: 800E_0000h base + 220h offset = 800E_0220h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL136 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 2. READ-ONLY. 2_2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1290 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.132 DRAM Control Register 137 (HW_DRAM_CTL137) This is a DRAM configuration register. Address: 800E_0000h base + 224h offset = 800E_0224h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 OBSOLETE R 13 12 11 10 9 8 7 RSVD1 6 5 4 3 2 1 0 DLL_OBS_REG_2_2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL137 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports the read DQS delay value for data slice 2. READ-ONLY. 2_2 14.8.133 DRAM Control Register 138 (HW_DRAM_CTL138) This is a DRAM configuration register. Address: 800E_0000h base + 228h offset = 800E_0228h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL138 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 3. READ-ONLY. 2_3 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1291 Programmable Registers 14.8.134 DRAM Control Register 139 (HW_DRAM_CTL139) This is a DRAM configuration register. Address: 800E_0000h base + 22Ch offset = 800E_022Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_3 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL139 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 3. READ-ONLY. 2_3 14.8.135 DRAM Control Register 140 (HW_DRAM_CTL140) This is a DRAM configuration register. Address: 800E_0000h base + 230h offset = 800E_0230h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_2_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL140 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 3. READ-ONLY. 2_3 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1292 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.136 DRAM Control Register 141 (HW_DRAM_CTL141) This is a DRAM configuration register. Address: 800E_0000h base + 234h offset = 800E_0234h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 DLL_OBS_REG_2_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL141 field descriptions Field Description DLL_OBS_REG_ Reports the read DQS delay value for data slice 3. READ-ONLY. 2_3 14.8.137 DRAM Control Register 142 (HW_DRAM_CTL142) This is a DRAM configuration register. Address: 800E_0000h base + 238h offset = 800E_0238h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 OBSOLETE R 13 12 11 10 9 8 7 RSVD1 6 5 DLL_OBS_REG_2_3 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL142 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports the read DQS delay value for data slice 3. READ-ONLY. 2_3 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1293 Programmable Registers 14.8.138 DRAM Control Register 143 (HW_DRAM_CTL143) This is a DRAM configuration register. Address: 800E_0000h base + 23Ch offset = 800E_023Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_0 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL143 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 0. READ-ONLY. 3_0 14.8.139 DRAM Control Register 144 (HW_DRAM_CTL144) This is a DRAM configuration register. Address: 800E_0000h base + 240h offset = 800E_0240h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL144 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 0. READ-ONLY. 3_0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1294 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.140 DRAM Control Register 145 (HW_DRAM_CTL145) This is a DRAM configuration register. Address: 800E_0000h base + 244h offset = 800E_0244h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL145 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 0. READ-ONLY. 3_0 14.8.141 DRAM Control Register 146 (HW_DRAM_CTL146) This is a DRAM configuration register. Address: 800E_0000h base + 248h offset = 800E_0248h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL146 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 0. READ-ONLY. 3_0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1295 Programmable Registers 14.8.142 DRAM Control Register 147 (HW_DRAM_CTL147) This is a DRAM configuration register. Address: 800E_0000h base + 24Ch offset = 800E_024Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 OBSOLETE R 13 12 11 10 9 8 7 RSVD1 6 5 4 3 2 1 0 DLL_OBS_REG_3_0 W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL147 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports the clk_wr delay value for data slice 0. READ-ONLY. 3_0 14.8.143 DRAM Control Register 148 (HW_DRAM_CTL148) This is a DRAM configuration register. Address: 800E_0000h base + 250h offset = 800E_0250h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL148 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 1. READ-ONLY. 3_1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1296 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.144 DRAM Control Register 149 (HW_DRAM_CTL149) This is a DRAM configuration register. Address: 800E_0000h base + 254h offset = 800E_0254h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL149 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 1. READ-ONLY. 3_1 14.8.145 DRAM Control Register 150 (HW_DRAM_CTL150) This is a DRAM configuration register. Address: 800E_0000h base + 258h offset = 800E_0258h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL150 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 1. READ-ONLY. 3_1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1297 Programmable Registers 14.8.146 DRAM Control Register 151 (HW_DRAM_CTL151) This is a DRAM configuration register. Address: 800E_0000h base + 25Ch offset = 800E_025Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 DLL_OBS_REG_3_1 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL151 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 1. READ-ONLY. 3_1 14.8.147 DRAM Control Register 152 (HW_DRAM_CTL152) This is a DRAM configuration register. Address: 800E_0000h base + 260h offset = 800E_0260h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 OBSOLETE R 13 12 11 10 9 8 7 RSVD1 6 5 DLL_OBS_REG_3_1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL152 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports the clk_wr delay value for data slice 1. READ-ONLY. 3_1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1298 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.148 DRAM Control Register 153 (HW_DRAM_CTL153) This is a DRAM configuration register. Address: 800E_0000h base + 264h offset = 800E_0264h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL153 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 2. READ-ONLY. 3_2 14.8.149 DRAM Control Register 154 (HW_DRAM_CTL154) This is a DRAM configuration register. Address: 800E_0000h base + 268h offset = 800E_0268h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL154 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 2. READ-ONLY. 3_2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1299 Programmable Registers 14.8.150 DRAM Control Register 155 (HW_DRAM_CTL155) This is a DRAM configuration register. Address: 800E_0000h base + 26Ch offset = 800E_026Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_2 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL155 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 2. READ-ONLY. 3_2 14.8.151 DRAM Control Register 156 (HW_DRAM_CTL156) This is a DRAM configuration register. Address: 800E_0000h base + 270h offset = 800E_0270h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL156 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 2. READ-ONLY. 3_2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1300 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.152 DRAM Control Register 157 (HW_DRAM_CTL157) This is a DRAM configuration register. Address: 800E_0000h base + 274h offset = 800E_0274h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 OBSOLETE R 13 12 11 10 9 8 7 RSVD1 6 5 4 3 2 1 0 DLL_OBS_REG_3_2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL157 field descriptions Field Description 31-16 OBSOLETE Always write zeroes to this field. 15-9 RSVD1 Always write zeroes to this field. DLL_OBS_REG_ Reports the clk_wr delay value for data slice 2. READ-ONLY. 3_2 14.8.153 DRAM Control Register 158 (HW_DRAM_CTL158) This is a DRAM configuration register. Address: 800E_0000h base + 278h offset = 800E_0278h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL158 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 3. READ-ONLY. 3_3 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1301 Programmable Registers 14.8.154 DRAM Control Register 159 (HW_DRAM_CTL159) This is a DRAM configuration register. Address: 800E_0000h base + 27Ch offset = 800E_027Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_3 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL159 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 3. READ-ONLY. 3_3 14.8.155 DRAM Control Register 160 (HW_DRAM_CTL160) This is a DRAM configuration register. Address: 800E_0000h base + 280h offset = 800E_0280h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL160 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 3. READ-ONLY. 3_3 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1302 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.156 DRAM Control Register 161 (HW_DRAM_CTL161) This is a DRAM configuration register. Address: 800E_0000h base + 284h offset = 800E_0284h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL_OBS_REG_3_3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL161 field descriptions Field Description DLL_OBS_REG_ Reports the clk_wr delay value for data slice 3. READ-ONLY. 3_3 14.8.157 DRAM Control Register 162 (HW_DRAM_CTL162) This is a DRAM configuration register. Address: 800E_0000h base + 288h offset = 800E_0288h Bit 31 30 29 28 27 RSVD3 R Bit 25 24 23 22 21 20 19 RSVD2 W2R_SAMECS_ DLY W Reset 26 18 17 16 W2R_DIFFCS_DLY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD1 R DLL_OBS_REG_3_3 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL162 field descriptions Field 31-27 RSVD3 Description Always write zeroes to this field. 26-24 Additional delay to insert between writes and reads to the same chip select. W2R_SAMECS_ Defines the number of additional clocks of delay to insert from a write command to a read command to the DLY same chip select. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1303 Programmable Registers HW_DRAM_CTL162 field descriptions (continued) Field Description 23-19 RSVD2 Always write zeroes to this field. 18-16 W2R_DIFFCS_ DLY 15-9 RSVD1 Additional delay to insert between writes and reads to different chip selects. Defines the number of additional clocks of delay to insert from a write command to one chip select to a read command to a different chip select. Always write zeroes to this field. DLL_OBS_REG_ Reports the clk_wr delay value for data slice 3. READ-ONLY. 3_3 14.8.158 DRAM Control Register 163 (HW_DRAM_CTL163) This is a DRAM configuration register. Address: 800E_0000h base + 28Ch offset = 800E_028Ch Bit 31 R 30 29 28 27 26 25 24 23 Reset 0 0 0 0 0 0 0 21 20 RSVD3 DLL_RST_ADJ_DLY W 22 0 0 0 0 19 18 17 16 15 0 0 0 0 13 12 RSVD2 WRLAT_ADJ 0 14 0 0 0 11 10 9 8 7 0 0 0 0 5 4 3 RSVD1 RDLAT_ADJ 0 6 0 0 0 2 1 0 DRAM_ CLASS 0 0 0 0 0 HW_DRAM_CTL163 field descriptions Field Description 31-24 Minimum number of cycles after setting master delay in DLL until reset is released. DLL_RST_ADJ_ Specifies the minimum number of cycles after the master delay value is programmed before the DLL reset DLY may be asserted. 23-20 RSVD3 19-16 WRLAT_ADJ 15-12 RSVD2 11-8 RDLAT_ADJ 7-4 RSVD1 DRAM_CLASS Always write zeroes to this field. Adjustment value for PHY write timing. Adjusts the relative timing between DFI write commands and the dfi_wrdata_en signal to conform to PHY timing requirements. When this parameter is programmed to 0x0, dfi_wrdata_en will assert on the same cycle as the dfi_address. This parameter only affects the DFI. Always write zeroes to this field. Adjustment value for PHY read timing. Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal to conform to PHY timing requirements. When this parameter is programmed to 0x0, dfi_rddata_en will assert one cycle after the dfi_address. This parameter only affects the DFI. Always write zeroes to this field. Defines the mode of operation of the controller. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1304 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL163 field descriptions (continued) Field Description Selects the mode of operation for the EMI. 'b0000 = DDR1 'b0001 = DDR1 with Mobile (LPDDR1) 'b0100 = DDR2 All other settings reserved. 14.8.159 DRAM Control Register 164 (HW_DRAM_CTL164) This is a DRAM configuration register. Address: 800E_0000h base + 290h offset = 800E_0290h Bit 31 30 29 28 27 26 25 24 23 22 OBSOLETE R 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 RSVD1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 0 0 0 TMOD INT_ACK W 4 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL164 field descriptions Field Description 31-24 OBSOLETE Always write zeroes to this field. 23-18 RSVD1 Always write zeroes to this field. 17-8 INT_ACK TMOD Clear mask of the INT_STATUS parameter. WRITE-ONLY Controls the clearing of the int_status parameter. If any of the int_ack bits are set to 'b1, the corresponding bit in the int_status parameter will be cleared to 'b0. Any int_ack bits cleared to 'b0 will not alter the corresponding bit in the int_status parameter. This parameter will always read back as 0x0. Number of clock cycles after MRS command and before any other command. Defines the number of cycles of wait time after a mode register write to any non-mode register write command. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1305 Programmable Registers 14.8.160 DRAM Control Register 171 (HW_DRAM_CTL171) This is a DRAM configuration register. Address: 800E_0000h base + 2ACh offset = 800E_02ACh 30 29 28 27 26 25 RSVD2 R W Reset Bit 24 23 22 21 20 19 18 17 16 AXI4_BDW_OVFLOW 31 AXI5_BDW_OVFLOW Bit RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R DLL_RST_DELAY W Reset 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL171 field descriptions Field 31-25 RSVD2 24 AXI5_BDW_ OVFLOW 23-17 RSVD1 16 AXI4_BDW_ OVFLOW Description Always write zeroes to this field. Port 5 behavior when bandwidth maximized. Always write zeroes to this field. Port 4 behavior when bandwidth maximized. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1306 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL171 field descriptions (continued) Field DLL_RST_ DELAY Description Minimum number of cycles required for DLL reset. Sets the number of cycles that the reset must be held asserted for the DLL. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1307 Programmable Registers 14.8.161 DRAM Control Register 172 (HW_DRAM_CTL172) This is a DRAM configuration register. Address: 800E_0000h base + 2B0h offset = 800E_02B0h 30 29 28 27 26 25 RSVD4 R W 22 21 20 19 18 17 16 RSVD3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD2 R CKE_STATUS Bit 23 CONCURRENTAP_WR_ONLY Reset 24 RESYNC_DLL 31 RESYNC_DLL_PER_AREF_EN Bit RSVD1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1308 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL172 field descriptions Field Description 31-25 RSVD4 Always write zeroes to this field. 24 RESYNC_DLL_ PER_AREF_EN 23-17 RSVD3 Enables automatic DLL resyncs after every refresh. Enables an automatic re-synchronization of the DLL after every refresh. Always write zeroes to this field. 16 RESYNC_DLL 15-9 RSVD2 Initiate a DLL resync. WRITE-ONLY Initiates a re-synchronization of the DLL. This parameter is write-only. Always write zeroes to this field. 8 Limit concurrent auto-precharge by waiting for the write recovery time, tWR, before issuing a read. CONCURRENTAP_ Limit concurrent auto-precharge by waiting for the write recovery time, tWR, to complete after a write WR_ONLY before issuing a read. 'b0 = Do not restrict concurrent auto-precharge. 'b1 = Wait tWR after a write before issuing a read. 7-1 RSVD1 Always write zeroes to this field. 0 CKE_STATUS Register access to cke_status signal. This value also indicates the inverted state of the CKE pin on the external memory bus. READ-ONLY Provides the value of the cke_status signal in a parameter. This parameter is read-only. 14.8.162 DRAM Control Register 173 (HW_DRAM_CTL173) This is a DRAM configuration register. Address: 800E_0000h base + 2B4h offset = 800E_02B4h Bit 31 30 29 28 27 RSVD4 R Bit 24 23 22 21 20 19 RSVD3 18 17 16 AXI4_R_PRIORITY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 R 0 0 0 0 RSVD1 AXI5_FIFO_ TYPE_REG W Reset 25 AXI4_W_PRIORITY W Reset 26 0 0 0 0 0 0 0 0 AXI4_FIFO_ TYPE_REG 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1309 Programmable Registers HW_DRAM_CTL173 field descriptions Field Description 31-27 RSVD4 Always write zeroes to this field. 26-24 AXI4_W_ PRIORITY Priority of write cmds from AXI port 4. 23-19 RSVD3 Always write zeroes to this field. 18-16 AXI4_R_ PRIORITY Priority of read cmds from AXI port 4. 15-10 RSVD2 Always write zeroes to this field. 9-8 AXI5_FIFO_ TYPE_REG Clock domain relativity between AXI port 5 and core logic. 7-2 RSVD1 Always write zeroes to this field. AXI4_FIFO_ TYPE_REG Clock domain relativity between AXI port 4 and core logic. 14.8.163 DRAM Control Register 174 (HW_DRAM_CTL174) This is a DRAM configuration register. Address: 800E_0000h base + 2B8h offset = 800E_02B8h Bit 31 30 29 28 27 RSVD4 R Bit 24 23 22 21 20 19 RSVD3 18 17 16 R2R_DIFFCS_DLY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 R 0 0 0 RSVD1 AXI5_W_PRIORITY W Reset 25 R2R_SAMECS_DLY W Reset 26 0 0 0 0 0 0 0 0 AXI5_R_PRIORITY 0 0 0 0 0 HW_DRAM_CTL174 field descriptions Field 31-27 RSVD4 Description Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1310 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL174 field descriptions (continued) Field Description 26-24 Additional delay to insert between reads and reads to the same chip select. R2R_SAMECS_ Defines the number of additional clocks of delay to insert between two read commands to the same chip DLY select. 23-19 RSVD3 Always write zeroes to this field. 18-16 R2R_DIFFCS_ DLY Additional delay to insert between reads and reads to different chip selects. Defines the number of additional clocks of delay to insert from a read command to one chip select to a read command to a different chip select. 15-11 RSVD2 Always write zeroes to this field. 10-8 AXI5_W_ PRIORITY Priority of write cmds from AXI port 5. 7-3 RSVD1 Always write zeroes to this field. AXI5_R_ PRIORITY Priority of read cmds from AXI port 5. 14.8.164 DRAM Control Register 175 (HW_DRAM_CTL175) This is a DRAM configuration register. Address: 800E_0000h base + 2BCh offset = 800E_02BCh Bit 31 30 29 28 27 RSVD4 R Bit 24 23 22 21 20 19 18 RSVD3 17 16 TBST_INT_ INTERVAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 R 0 0 0 RSVD1 R2W_SAMECS_ DLY W Reset 25 W2W_DIFFCS_DLY W Reset 26 0 0 0 0 0 0 0 0 R2W_DIFFCS_DLY 0 0 0 0 0 HW_DRAM_CTL175 field descriptions Field 31-27 RSVD4 Description Always write zeroes to this field. 26-24 Additional delay to insert between writes and writes to different chip selects. W2W_DIFFCS_ DLY Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1311 Programmable Registers HW_DRAM_CTL175 field descriptions (continued) Field Description Defines the number of additional clocks of delay to insert from a write command to one chip select to a write command to a different chip select. 23-19 RSVD3 18-16 TBST_INT_ INTERVAL Always write zeroes to this field. DRAM burst interrupt interval in cycles. Defines the burst interrupt interval. This parameter is only relevant if the burst has not completed. This value is loaded into a parameter when a burst is issued and another command may only interrupt the current burst when this counter value hits 0. If the counter value hits 0 and the burst has not completed, the counter will be reset with the tbst_int_interval value. If a command is in progress and the burst has not completed, another command may only be issued on cycles after the parameter tccd value cycles have elapsed since the last CAS command and this counter value hits 0. For example, if the burst length is 8, tccd is 2, tbst_int_interval is 2 and a CAS command was issued on cycle 0, another CAS command could interrupt the current burst on cycle 2. After cycle 3, the current burst will complete and this parameter would not be relevant. If instead the tbst_int_interval was 1 for the same system, then the command could interrupt on cycles 2 or 3. 15-11 RSVD2 Always write zeroes to this field. 10-8 Additional delay to insert between reads and writes to the same chip select. R2W_SAMECS_ Defines the number of additional clocks of delay to insert from a read command to a write command to the DLY same chip select. 7-3 RSVD1 Always write zeroes to this field. R2W_DIFFCS_ Additional delay to insert between reads and writes to different chip selects. DLY Defines the number of additional clocks of delay to insert from a read command to one chip select to a write command to a different chip select. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1312 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.165 DRAM Control Register 176 (HW_DRAM_CTL176) This is a DRAM configuration register. Address: 800E_0000h base + 2C0h offset = 800E_02C0h Bit 31 30 29 28 RSVD4 R Bit 25 24 23 22 21 20 RSVD3 19 18 17 16 ADD_ODT_CLK_ DIFFTYPE_SAMECS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD2 R 0 0 0 RSVD1 ADD_ODT_CLK_ DIFFTYPE_DIFFCS W Reset 26 ADD_ODT_CLK_ SAMETYPE_DIFFCS W Reset 27 0 0 0 0 0 0 0 0 W2W_SAMECS_ DLY 0 0 0 0 0 HW_DRAM_CTL176 field descriptions Field 31-28 RSVD4 Description Always write zeroes to this field. 27-24 Additional delay to insert between same transaction types to different chip selects to meet ODT timing ADD_ODT_CLK_ requirements. SAMETYPE_ Defines the number of additional clocks of delay to insert between commands of the same type (read to DIFFCS read, write to write) to different chip selects to meet ODT timing requirements. 23-20 RSVD3 Always write zeroes to this field. 19-16 Additional delay to insert between different transaction types to the same chip select to meet ODT timing ADD_ODT_CLK_ requirements. DIFFTYPE_ Defines the number of additional clocks of delay to insert between commands of different types (read to SAMECS write, write to read) to the same chip select to meet ODT timing requirements. 15-12 RSVD2 Always write zeroes to this field. 11-8 Additional delay to insert between different transaction types to different chip selects to meet ODT timing ADD_ODT_CLK_ requirements. DIFFTYPE_ Defines the number of additional clocks of delay to insert between commands of different types (read to DIFFCS write, write to read) to different chip selects to meet ODT timing requirements. 7-3 RSVD1 Always write zeroes to this field. W2W_SAMECS_ Additional delay to insert between writes and writes to the same chip select. DLY Defines the number of additional clocks of delay to insert between two write commands to the same chip select. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1313 Programmable Registers 14.8.166 DRAM Control Register 177 (HW_DRAM_CTL177) This is a DRAM configuration register. Address: 800E_0000h base + 2C4h offset = 800E_02C4h Bit 31 R 30 29 28 27 RSVD4 0 0 0 25 24 23 0 0 0 22 21 20 19 RSVD3 TCCD W Reset 26 0 0 0 0 0 18 17 16 15 0 0 0 13 12 11 RSVD2 TRP_AB 0 14 0 0 0 0 10 9 8 7 0 0 0 5 4 3 RSVD1 CKSRX 0 6 0 0 0 0 2 1 0 CKSRE 0 0 0 0 0 HW_DRAM_CTL177 field descriptions Field Description 31-29 RSVD4 Always write zeroes to this field. 28-24 TCCD DRAM CAS-to-CAS parameter in cycles. 23-20 RSVD3 Always write zeroes to this field. 19-16 TRP_AB DRAM TRP All Bank parameter in cycles. 15-12 RSVD2 Always write zeroes to this field. 11-8 CKSRX Clock stable delay on self-refresh exit. 7-4 RSVD1 Always write zeroes to this field. CKSRE Clock hold delay on self-refresh entry. Defines the minimum delay between CAS commands, in cycles. This value is loaded into a counter when a burst is issued and a new command may be issued when the counter reaches 0. Defines the DRAM TRP time for all banks, in cycles. Sets the number of cycles to hold the clock stable before exiting self-refresh mode. The clock will run for a minimum of cksrx cycles before CKE rises. Sets the number of cycles to hold the clock stable after entering self-refresh mode. The clock will run for a minimum of cksre cycles after CKE falls. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1314 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) 14.8.167 DRAM Control Register 178 (HW_DRAM_CTL178) This is a DRAM configuration register. Address: 800E_0000h base + 2C8h offset = 800E_02C8h R 30 29 28 27 26 25 24 23 22 21 RSVD3 31 RSVD4 Bit 20 19 18 17 16 AXI4_CURRENT_BDW AXI5_BDW W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSVD2 Reset RSVD1 AXI4_BDW TCKESR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL178 field descriptions Field 31 RSVD4 30-24 AXI5_BDW 23 RSVD3 Description Always write zeroes to this field. Maximum bandwidth percentage for port 5. Always write zeroes to this field. 22-16 Current bandwidth usage percentage for port 4. READ-ONLY. AXI4_ CURRENT_BDW 15 RSVD2 Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1315 Programmable Registers HW_DRAM_CTL178 field descriptions (continued) Field Description 14-8 AXI4_BDW Maximum bandwidth percentage for port 4. 7-5 RSVD1 Always write zeroes to this field. TCKESR Minimum CKE low pulse width during a self-refresh. Defines the minimum number of cycles that CKE must be held low during self-refresh. pulse width, in cycles. If the memory specification does not define a tckesr, then the tckesr parameter should be programmed with the tcke value. 14.8.168 DRAM Control Register 179 (HW_DRAM_CTL179) This is a DRAM configuration register. Address: 800E_0000h base + 2CCh offset = 800E_02CCh Bit 31 30 29 28 27 26 25 24 RSVD3 R 23 22 21 20 19 18 17 16 RSVD2 TDFI_PHYUPD_TYPE1 W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSVD1 Reset R AXI5_CURRENT_BDW TDFI_PHYUPD_TYPE1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL179 field descriptions Field 31-24 RSVD3 Description Always write zeroes to this field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1316 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL179 field descriptions (continued) Field Description 23-22 RSVD2 Always write zeroes to this field. 21-8 Holds the DFI tPHYUPD_TYPE1 timing parameter. TDFI_PHYUPD_ Holds the DFI tphyupd_typeX timing parameter. This parameter is read-only. TYPE1 7 RSVD1 Always write zeroes to this field. AXI5_ Current bandwidth usage percentage for port 5. READ-ONLY. CURRENT_BDW 14.8.169 DRAM Control Register 180 (HW_DRAM_CTL180) This is a DRAM configuration register. Address: 800E_0000h base + 2D0h offset = 800E_02D0h Bit 31 R 30 29 28 27 26 25 RSVD2 Bit R 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 RSVD1 TDFI_PHYUPD_TYPE2 W Reset 23 TDFI_PHYUPD_TYPE3 W Reset 24 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL180 field descriptions Field 31-30 RSVD2 Description Always write zeroes to this field. 29-16 Holds the DFI tPHYUPD_TYPE3 timing parameter. TDFI_PHYUPD_ Holds the DFI tphyupd_typeX timing parameter. This parameter is read-only. TYPE3 15-14 RSVD1 Always write zeroes to this field. TDFI_PHYUPD_ Holds the DFI tPHYUPD_TYPE2 timing parameter. TYPE2 Holds the DFI tphyupd_typeX timing parameter. This parameter is read-only. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1317 Programmable Registers 14.8.170 DRAM Control Register 181 (HW_DRAM_CTL181) This is a DRAM configuration register. Address: 800E_0000h base + 2D4h offset = 800E_02D4h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 Bit MR0_DATA_1 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD1 Reset MR0_DATA_0 W Reset 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL181 field descriptions Field 31 RSVD2 30-16 MR0_DATA_1 Description Always write zeroes to this field. MRS data to program to memory mode register 0 for chip select 1. Holds the memory mode register 0 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. This parameter correlates to the memory mode register (MR). The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1318 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL181 field descriptions (continued) Field Description A2:A0 should be set to 'b010.For DDR2 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010. For LPDDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010. This data will be programmed into the memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. 15 RSVD1 MR0_DATA_0 Always write zeroes to this field. MRS data to program to memory mode register 0 for chip select 0. Holds the memory mode register 0 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. This parameter correlates to the memory mode register (MR). The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010.For DDR2 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010. For LPDDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010. This data will be programmed into the memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1319 Programmable Registers 14.8.171 DRAM Control Register 182 (HW_DRAM_CTL182) This is a DRAM configuration register. Address: 800E_0000h base + 2D8h offset = 800E_02D8h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 Bit MR0_DATA_3 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD1 Reset MR0_DATA_2 W Reset 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL182 field descriptions Field 31 RSVD2 30-16 MR0_DATA_3 Description Always write zeroes to this field. MRS data to program to memory mode register 0 for chip select 3. Holds the memory mode register 0 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. This parameter correlates to the memory mode register (MR). The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1320 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL182 field descriptions (continued) Field Description A2:A0 should be set to 'b010.For DDR2 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010. For LPDDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010. This data will be programmed into the memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. 15 RSVD1 MR0_DATA_2 Always write zeroes to this field. MRS data to program to memory mode register 0 for chip select 2. Holds the memory mode register 0 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. This parameter correlates to the memory mode register (MR). The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010.For DDR2 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. In addition, the DLL Reset bit (A8) will be ignored in favor of an internal state machine that sets the DLL Reset bit during initialization. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010. For LPDDR1 memories: The EMI does not support interleaving and therefore the A3 bit should be cleared to 'b0. Also, the EMI only supports a burst length of 4 and therefore the bits A2:A0 should be set to 'b010. This data will be programmed into the memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1321 Programmable Registers 14.8.172 DRAM Control Register 183 (HW_DRAM_CTL183) This is a DRAM configuration register. Address: 800E_0000h base + 2DCh offset = 800E_02DCh 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 Bit MR1_DATA_1 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD1 Reset MR1_DATA_0 W Reset 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL183 field descriptions Field 31 RSVD2 30-16 MR1_DATA_1 Description Always write zeroes to this field. Data to program into memory mode register 1 for chip select 1. Holds the memory mode register 1 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter correlates to the extended memory mode register (EMR). For DDR2 memories: This parameter correlates to the extended memory mode register 1 (EMR1). The EMI does not support additive latency and therefore the A5:A3 bits should be cleared to 'b000. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1322 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL183 field descriptions (continued) Field Description For LPDDR1 memories: This parameter has no meaning for this memory type. This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. 15 RSVD1 MR1_DATA_0 Always write zeroes to this field. Data to program into memory mode register 1 for chip select 0. Holds the memory mode register 1 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter correlates to the extended memory mode register (EMR). For DDR2 memories: This parameter correlates to the extended memory mode register 1 (EMR1). The EMI does not support additive latency and therefore the A5:A3 bits should be cleared to 'b000. For LPDDR1 memories: This parameter has no meaning for this memory type. This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1323 Programmable Registers 14.8.173 DRAM Control Register 184 (HW_DRAM_CTL184) This is a DRAM configuration register. Address: 800E_0000h base + 2E0h offset = 800E_02E0h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 Bit MR1_DATA_3 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD1 Reset MR1_DATA_2 W Reset 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL184 field descriptions Field 31 RSVD2 30-16 MR1_DATA_3 Description Always write zeroes to this field. Data to program into memory mode register 1 for chip select 3. Holds the memory mode register 1 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter correlates to the extended memory mode register (EMR). For DDR2 memories: This parameter correlates to the extended memory mode register 1 (EMR1). The EMI does not support additive latency and therefore the A5:A3 bits should be cleared to 'b000. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1324 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL184 field descriptions (continued) Field Description For LPDDR1 memories: This parameter has no meaning for this memory type. This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. 15 RSVD1 MR1_DATA_2 Always write zeroes to this field. Data to program into memory mode register 1 for chip select 2. Holds the memory mode register 1 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter correlates to the extended memory mode register (EMR). For DDR2 memories: This parameter correlates to the extended memory mode register 1 (EMR1). The EMI does not support additive latency and therefore the A5:A3 bits should be cleared to 'b000. For LPDDR1 memories: This parameter has no meaning for this memory type. This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1325 Programmable Registers 14.8.174 DRAM Control Register 185 (HW_DRAM_CTL185) This is a DRAM configuration register. Address: 800E_0000h base + 2E4h offset = 800E_02E4h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 Bit MR2_DATA_1 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD1 Reset MR2_DATA_0 W Reset 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL185 field descriptions Field 31 RSVD2 30-16 MR2_DATA_1 Description Always write zeroes to this field. Data to program into memory mode register 2 for chip select 1. Holds the memory mode register 2 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter has no meaning for this memory type. For DDR2 memories: This parameter correlates to the extended memory mode register 2 (EMR2). For LPDDR1 memories: This parameter correlates to the extended mode register (EMR). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1326 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL185 field descriptions (continued) Field Description This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. 15 RSVD1 MR2_DATA_0 Always write zeroes to this field. Data to program into memory mode register 2 for chip select 0. Holds the memory mode register 2 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter has no meaning for this memory type. For DDR2 memories: This parameter correlates to the extended memory mode register 2 (EMR2). For LPDDR1 memories: This parameter correlates to the extended mode register (EMR). This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1327 Programmable Registers 14.8.175 DRAM Control Register 186 (HW_DRAM_CTL186) This is a DRAM configuration register. Address: 800E_0000h base + 2E8h offset = 800E_02E8h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 Bit MR2_DATA_3 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD1 Reset MR2_DATA_2 W Reset 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL186 field descriptions Field 31 RSVD2 30-16 MR2_DATA_3 Description Always write zeroes to this field. Data to program into memory mode register 2 for chip select 3. Holds the memory mode register 2 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter has no meaning for this memory type. For DDR2 memories: This parameter correlates to the extended memory mode register 2 (EMR2). For LPDDR1 memories: This parameter correlates to the extended mode register (EMR). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1328 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL186 field descriptions (continued) Field Description This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. 15 RSVD1 MR2_DATA_2 Always write zeroes to this field. Data to program into memory mode register 2 for chip select 2. Holds the memory mode register 2 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter has no meaning for this memory type. For DDR2 memories: This parameter correlates to the extended memory mode register 2 (EMR2). For LPDDR1 memories: This parameter correlates to the extended mode register (EMR). This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1329 Programmable Registers 14.8.176 DRAM Control Register 187 (HW_DRAM_CTL187) This is a DRAM configuration register. Address: 800E_0000h base + 2ECh offset = 800E_02ECh 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 Bit MR3_DATA_1 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD1 Reset MR3_DATA_0 W Reset 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL187 field descriptions Field 31 RSVD2 30-16 MR3_DATA_1 Description Always write zeroes to this field. Data to program into memory mode register 3 for chip select 1. Holds the memory mode register 3 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter has no meaning for this memory type. For DDR2 memories: This parameter correlates to the extended memory mode register 3 (EMR3). For LPDDR1 memories: This parameter has no meaning for this memory type. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1330 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL187 field descriptions (continued) Field Description This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. 15 RSVD1 MR3_DATA_0 Always write zeroes to this field. Data to program into memory mode register 3 for chip select 0. Holds the memory mode register 3 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter has no meaning for this memory type. For DDR2 memories: This parameter correlates to the extended memory mode register 3 (EMR3). For LPDDR1 memories: This parameter has no meaning for this memory type. This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1331 Programmable Registers 14.8.177 DRAM Control Register 188 (HW_DRAM_CTL188) This is a DRAM configuration register. Address: 800E_0000h base + 2F0h offset = 800E_02F0h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 Bit MR3_DATA_3 W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD1 Reset MR3_DATA_2 W Reset 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL188 field descriptions Field 31 RSVD2 30-16 MR3_DATA_3 Description Always write zeroes to this field. Data to program into memory mode register 3 for chip select 3. Holds the memory mode register 3 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter has no meaning for this memory type. For DDR2 memories: This parameter correlates to the extended memory mode register 3 (EMR3). For LPDDR1 memories: This parameter has no meaning for this memory type. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1332 Freescale Semiconductor, Inc. Chapter 14 External Memory Interface (EMI) HW_DRAM_CTL188 field descriptions (continued) Field Description This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. 15 RSVD1 Always write zeroes to this field. MR3_DATA_2 Data to program into memory mode register 3 for chip select 2. Holds the memory mode register 3 data for chip select X written during memory initialization. Consult the memory specification for the fields of this mode register. The use of this parameter varies based on the memory type connected to this EMI: For DDR1 memories: This parameter has no meaning for this memory type. For DDR2 memories: This parameter correlates to the extended memory mode register 3 (EMR3). For LPDDR1 memories: This parameter has no meaning for this memory type. This data will be programmed into the appropriate memory register of the DRAM at initialization or when the write_modereg parameter is set to 'b1. 14.8.178 DRAM Control Register 189 (HW_DRAM_CTL189) This is a DRAM configuration register. Address: 800E_0000h base + 2F4h offset = 800E_02F4h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 AXI5_EN_SIZE_LT_WIDTH_INSTR 0 0 0 0 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 AXI4_EN_SIZE_LT_WIDTH_INSTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DRAM_CTL189 field descriptions Field Description 31-16 Allow narrow instructions from AXI port 5 requestors with bit enabled. AXI5_EN_SIZE_ LT_WIDTH_ INSTR AXI4_EN_SIZE_ Allow narrow instructions from AXI port 4 requestors with bit enabled. LT_WIDTH_ INSTR i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1333 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1334 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) 15.1 General-Purpose Media Interface Overview This chapter describes the general-purpose media interface. The GPMI controller is a flexible interface to up to eight NAND Flash with configurable address and command behavior, providing support for future devices not yet specified. The GPMI resides on the APBH and provides an interface to the 20-bit BCH module to allow direct parity processing. Registers are clocked on the HCLK domain. The I/O and pin timing are clocked on a dedicated GPMICLK domain. GPMICLK can be set to maximize I/O performance. The following figure shows a block diagram of the GPMI controller. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1335 GPMI NAND Mode ARM Core SRAM System Clock Generator AHB AHB SLAVE AHB-to-APBH Bridge AHB MASTER APBH HCLK DMA Request 7 DMA Request 6 DMA Request 5 DMA Request 4 DMA Request 3 DMA Request 2 DMA Request 1 APBH MASTER DMA Request 0 SHARED DMA GPMI DMA Interface State Machine HCLK GPMI FIFO BCH GPMI GPMICLK GPMI Pin State Machine Memory Controller GPIO GPMI / Memory / GPIO Pin Mux Pins Figure 15-1. General-Purpose Media Interface Controller Block Diagram 15.2 GPMI NAND Mode The general-purpose media interface has several features to efficiently support NAND: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1336 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) * Individual chip select and ready/busy pins for up to eight NANDs. * Individual state machine and DMA channel for each chip select. * Special command modes work with DMA controller to perform all normal NAND functions without CPU intervention. * Configurable timing based on a dedicated clock allows optimal balance of high NAND performance and low system power. Since current NAND Flash does not support multiple page read/write commands, the GPMI and DMA have been designed to handle complex multi-page operations without CPU intervention. The DMA uses a linked descriptor function with branching capability to automatically handle all of the operations needed to read/write multiple pages: * Data/Register Read/Write--The GPMI can be programmed to read or write multiple cycles to the NAND address, command or data registers. * Wait for NAND Ready--The GPMI's Wait-for-Ready mode can monitor the ready/ busy signal of a single NAND Flash and signal the DMA when the device has become ready. It also has a time-out counter and can indicate to the DMA that a time-out error has occurred. The DMAs can conditionally branch to a different descriptor in the case of an error. * Check Status--The Read-and-Compare mode allows the GPMI to check NAND status against a reference. If an error is found, the GPMI can instruct the DMA to branch to an alternate descriptor, which attempts to fix the problem or asserts a CPU IRQ. 15.2.1 Multiple NAND Support The GPMI supports up to eight NAND chip selects, each with independent ready/busy signals. Since they share a data bus and control lines, the GPMI can only actively communicate with a single NAND at a time. However, all NANDs can concurrently perform internal read, write, or erase operations. With fast NAND Flash and software support for concurrent NAND operations, this architecture allows the total throughput to approach the data bus speed, which can be as high as 50 MB/s (8-bit bus running at 50 MHz). There are two options for controlling the eight NAND chip selects through the DMA interface. The first option is one to one mapping, where each DMA channel is attached to its own NAND. For example DMA channel 'n' accesses only NAND attached to chip select 'n'. The second option is the decoupled mode where a DMA channel can access any i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1337 GPMI NAND Mode or all NANDs connected to the GPMI. A DMA channel will signify the NAND it wants to access by writing its chip select value in the HW_GPMI_CTRL0_CS field and setting the HW_GPMI_CTRL1_DECOUPLE_CS to '1'. This option is useful if software chooses to use only one DMA channel to access all the attached NAND devices. 15.2.2 GPMI NAND Timing and Clocking The dedicated clock, GPMICLK, is used as a timing reference for NAND Flash I/O. Since various NANDs have different timing requirements, GPMICLK may need to be adjusted for each application. While the actual pin timings are limited by the NAND chips used, the GPMI can support data bus speeds of up to 50 MHz x 8 bits. The actual read/write strobe timing parameters are adjusted as indicated in the GPMI register descriptions. See Clock Structure for more information about setting GPMICLK. 15.2.3 Basic NAND Timing The following figure illustrates the operation of the timing parameters in NAND mode. GPMI_CE[7:0] / ALE / CLE GPMI_OEn/ GPMI_WRn TDH TAS TDS GPMI_DATA TDH Data0 Data1 Figure 15-2. BASIC NAND Timing 15.2.4 High-Speed NAND Timing In high-speed NANDs, the read data may not be valid until after the read strobe (RDN) deasserts. This is the case when the minimum tDS is programmed to achieve higher bandwidth. The GPMI implements a feedback read strobe to sample the read data. The feedback read strobe can be delayed to support fast NAND EDO (Extended Data Out) timing where the read strobe may deassert before the read data is valid, and read data is valid for some time after read strobe. NAND EDO timings is applied typically for read cycle frequency above 33 MHz.See Figure 15-3. The GPMI provides control over the amount of delay applied to the feedback read strobe. This delay depends on the maximum read access time (tREA) of the NAND and the read pulse width (tRP) used to access the NAND. tRP is specified by i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1338 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) HW_GPMI_TIMING0_DATA_SETUP register. When (tREA + 4 ns) is less than tRP, no delay is required to sample the NAND read data. (The 4 ns provides adequate data setup time for the GPMI.) In this case, set HW_GPMI_CTRL1_HALF_PERIOD=0; HW_GPMI_CTRL1_RDN_DELAY=0; HW_GPMI_CTRL1_DLL_ENABLE=0. When (tREA + 4 ns) is greater than or equal to tRP, a delay of the feedback read strobe is required to sample the NAND read data. This delay is equal to the difference between these two timings: DELAY= tREA+4 ns - tRP. Since the GPMI delay chain is limited to 16 ns maximum, if DELAY > 16 ns then increase tRP by increasing the value of HW_GPMI_TIMING0_DATA_SETUP until DELAY is less than or equal to 16 ns. The GPMI programming for this DELAY depends on the GPMICLK period. The GPMI DLL will not function properly if the GPMICLK period is greater than 32 ns: disable the DLL if this is the case. If the GPMICLK period is greater than 16 ns (and not greater than 32 ns), set the HW_GPMI_CTRL1_HALF_PERIOD=1; This will cause the DLL reference period (RP) to be one-half of the GPMICLK period. If the GPMICLK period is 16 ns or less then set the HW_GPMI_CTRL1_HALF_PERIOD=0; This will cause the DLL reference period (RP) to be equal to the GPMICLK period. DELAY is a multiple (0 to 1.875) of RP. The HW_GPMI_CTRL1_RDN_DELAY is encoded as a 1-bit integer and 3-bit fraction delay factor. See table below. DELAY is a multiple of the delay factor and the reference period: HW_GPMI_CTRL1_RDN_DELAY 0 1 2 3 4 5 6 7 Delay Factor 0.000 0.125 0.250 0.375 0.500 0.625 0.750 0.875 HW_GPMI_CTRL1_RDN_DELAY 8 9 10 11 12 13 14 15 Delay Factor 1.000 1.125 1.250 1.375 1.500 1.625 1.750 1.875 DELAY = DelayFactor x RP or DELAY = HW_GPMI_CTRL1_RDN_DELAY x 0.125 x RP. Use this equation to calculate the value for HW_GPMI_CTRL1_RDN_DELAY. Then set HW_GPMI_CTRL1_DLL_ENABLE=1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1339 GPMI NAND Mode GPMI NAND Read Path Timing Diagram (Non-EDO) tRP tREA RDN Read Data C B A FeedbackRDN (tREA + 4ns) is less than tRP, no delay is required on rising edge of FeedbackRDN to sample Read Data GPMI NAND Read Path Timing Diagram (EDO mode) tREA tRP RDN Read Data A C B Delay FeedbackRDN When (tREA + 4ns) is greater than or equal to tRP, a delay of the FeedbackRDN is required to sample to nand read data Figure 15-3. NAND Read Path Timing For example, a NAND with tREAmax=20 ns, tRPmin=12 ns, and tRCmin=25 ns (read cycle time) may be programmed as follows: * GPMICLK clock frequency: Consider 480/6=80 MHz which is 12.5 ns clock period. This is too close to the minimum NAND spec if we program the data setup and hold to 1 GPMICLK cycle. Consider 480/7=68.57 MHz which is 14.58 ns clock period. With data setup and hold set to 1, we have a tRP of 14.58 ns and a tRC of 29.16 ns (good margins). * Since (tREA +4 ns) is greater than tRP, required DELAY = tREA+4 ns - tRP = 20 + 4 - 14.58 ns = 9.42 ns. * HALF_PERIOD =0, since GPMICLK period is less than 16 ns. So RP=GPMICLK period = 14.58 ns. * DELAY = HW_GPMI_CTRL1_RDN_DELAY x 0.125 x RP.9.42 ns = HW_GPMI_CTRL1_RDN_DELAY x 0.125 x 14.58 ns.HW_GPMI_CTRL1_RDN_DELAY = 5 (round off 5.169) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1340 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) Note It is recommended that the drive strength of GPMI_RDn and GPMI_WRn output pins be set to 8 mA. This will reduce the transition time under heavy loads. Low transition times will be important when NAND interface read and write cycle times are below 30 ns. The other GPMI pins may remain at 4 mA, since their frequency is only up to half that of GPMI_RDn and GPMI_WRn. 15.2.5 NAND Command and Address Timing Example The following figure illustrates a command and address being sent to a NAND Flash. Run=1 Run=0 Run=1 Run=0 GPMI_CEn TAS GPMI_ALE TAS GPMI_CLE TDH TDH GPMI_WEn TDS TDS TDH read cmd GPMI_DATA $00 AL[7:0] AL[15:8] Figure 15-4. NAND Command and Address Timing Example 15.2.6 Hardware BCH Interface The GPMI provides an interface to the BCH module. This reduces the SOC bus traffic and the software involvement. When in BCH mode, parity information is inserted on-thefly during writes to 8-bit NAND devices. The BCH will supply payload and parity to the GPMI to write to the NAND. During NAND reads, parity is checked and ECC processing is performed after each read block. In this case, the GPMI reads the NAND device and redirects the data and parity to the BCH module for ECC processing. To program the BCH for NAND writes, remove the soft reset and clock gates from HW_BCH_CTRL_SFTRST and HW_BCH_CTRL_CLKGATE. The bulk of BCH programming is actually applied to the GPMI through PIO operations embedded in its DMA command structures. This has a subtle implication when writing to the GPMI ECC registers: access to these registers must be written in a progressive register order. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1341 Behavior During Reset Therefore, to write to the HW_GPMI_ECCCOUNT register, write first (in order) to registers HW_GPMI_CTRL0, HW_GPMI_COMPARE, and HW_GPMI_ECCCTRL before writing to HW_GPMI_ECCCOUNT. These additional register writes need to be accounted for in the CMDWORDS field of the respective DMA channel command register. See the descriptive text, flowcharts, and code examples in Programming the BCH/GPMI Interfaces for more information about using GPMI registers to program the ECC function. The HW_GPMI_PAYLOAD and HW_GPMI_AUXILIARY pointers need to be wordaligned for proper ECC operation. If those pointers are non-word-aligned, then the BCH engine will not operate properly and could possibly corrupt system memory in the adjoining memory regions. 15.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. 15.4 Programmable Registers GPMI Hardware Register Format Summary HW_GPMI memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_C000 GPMI Control Register 0 (HW_GPMI_CTRL0) 32 R/W C000_0000h 15.4.1/1343 8000_C010 GPMI Compare Register (HW_GPMI_COMPARE) 32 R/W 0000_0000h 15.4.2/1346 8000_C020 GPMI Integrated ECC Control Register (HW_GPMI_ECCCTRL) 32 R/W 0000_0000h 15.4.3/1346 8000_C030 GPMI Integrated ECC Transfer Count Register (HW_GPMI_ECCCOUNT) 32 R/W 0000_0000h 15.4.4/1348 8000_C040 GPMI Payload Address Register (HW_GPMI_PAYLOAD) 32 R/W 0000_0000h 15.4.5/1348 8000_C050 GPMI Auxiliary Address Register (HW_GPMI_AUXILIARY) 32 R/W 0000_0000h 15.4.6/1349 8000_C060 GPMI Control Register 1 (HW_GPMI_CTRL1) 32 R/W 0004_0004h 15.4.7/1349 8000_C070 GPMI Timing Register 0 (HW_GPMI_TIMING0) 32 R/W 0001_0203h 15.4.8/1352 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1342 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) HW_GPMI memory map (continued) Absolute address (hex) 8000_C080 Register name GPMI Timing Register 1 (HW_GPMI_TIMING1) Width Access (in bits) Reset value Section/ page 32 R/W 0000_0000h 15.4.9/1353 8000_C0A0 GPMI DMA Data Transfer Register (HW_GPMI_DATA) 32 R/W 0000_0000h 15.4.10/ 1353 8000_C0B0 GPMI Status Register (HW_GPMI_STAT) 32 R 0000_0005h 15.4.11/ 1354 8000_C0C0 GPMI Debug Information Register (HW_GPMI_DEBUG) 32 R 0000_0000h 15.4.12/ 1357 8000_C0D0 GPMI Version Register (HW_GPMI_VERSION) 32 R 0301_0000h 15.4.13/ 1357 15.4.1 GPMI Control Register 0 (HW_GPMI_CTRL0) HW_GPMI_CTRL0: 0x000 HW_GPMI_CTRL0_SET: 0x004 HW_GPMI_CTRL0_CLR: 0x008 HW_GPMI_CTRL0_TOG: 0x00C The GPMI control register 0 specifies the GPMI transaction to perform for the current command chain item. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1343 Programmable Registers Address: 8000_C000h base + 0h offset = 8000_C000h 27 25 24 23 21 20 19 18 17 16 CLKGATE LOCK_CS 22 SFTRST R 26 ADDRESS_INCREMENT 28 WORD_LENGTH 29 COMMAND_MODE 30 RSVD0 31 RSVD1 Bit RUN 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 CS ADDRESS W Reset Bit R XFER_COUNT W Reset 0 0 0 0 0 0 0 0 0 HW_GPMI_CTRL0 field descriptions Field 31 SFTRST Description Set to zero for normal operation. When this bit is set to one (default), then the entire block is held in its reset state. This will not work if the CLKGATE bit is already set to 1. CLKGATE must be cleared to 0 before issuing a soft reset. Also the GPMICLK must be running for this to work properly. 0x0 0x1 RUN -- Allow GPMI to operate normally. RESET -- Hold GPMI in reset. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1344 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) HW_GPMI_CTRL0 field descriptions (continued) Field 30 CLKGATE Description Set this bit zero for normal operation. Setting this bit to one (default), gates all of the block level clocks off for miniminizing AC energy consumption. 0x0 0x1 29 RUN The GPMI is busy running a command whenever this bit is set to 1. The GPMI is idle whenever this bit set to zero. This can be set to one by a CPU write. In addition, the DMA sets this bit each time a DMA command has finished its PIO transfer phase. 0x0 0x1 28 RSVD1 27 LOCK_CS 25-24 COMMAND_ MODE IDLE -- The GPMI is idle. BUSY -- The GPMI is busy running a command. Always write zeros to this field. For NAND mode: 0= Deassert chip select (CS) after RUN is complete. 1= Continue to assert chip select (CS) after RUN is complete. 0x0 0x1 26 RSVD0 RUN -- Allow GPMI to operate normally. NO_CLKS -- Do not clock GPMI gates in order to minimize power consumption. DISABLED -- Deassert chip select (CS) after RUN is complete. ENABLED -- Continue to assert chip select (CS) after RUN is complete. Always write zeros to this field. 00= Write mode. 01= Read Mode. 10= Read and Compare Mode (setting sense flop). 11= Wait for Ready. 0x0 0x1 0x2 0x3 WRITE -- Write mode. READ -- Read mode. READ_AND_COMPARE -- Read and Compare mode (setting sense flop). WAIT_FOR_READY -- Wait for Ready mode. 23 0= not support. WORD_LENGTH 1= 8-bit Data Bus mode. This bit should only 1. 22-20 CS 19-17 ADDRESS 16 ADDRESS_ INCREMENT Selects which chip select is active for this command. In NAND mode, use A0 for CLE and A1 for ALE. 0x0 0x1 0x2 NAND_DATA -- In NAND mode, this address is used to read and write data bytes. NAND_CLE -- In NAND mode, this address is used to write command bytes. NAND_ALE -- In NAND mode, this address is used to write address bytes. 0= Address does not increment. 1= Increment address. In NAND mode, the address will increment once, after the first cycle (going from CLE to ALE). 0x0 0x1 XFER_COUNT DISABLED -- Address does not increment. ENABLED -- Increment address. Number of words (8 bit wide) to transfer for this command. A value of zero will transfer 64K words. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1345 Programmable Registers 15.4.2 GPMI Compare Register (HW_GPMI_COMPARE) The GPMI compare register specifies the expect data and the xor mask for comparing to the status values read from the device. This register is used by the Read and Compare command. Address: 8000_C000h base + 10h offset = 8000_C010h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MASK 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 REFERENCE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_GPMI_COMPARE field descriptions Field Description 31-16 MASK 16-bit mask which is applied after the read data is XORed with the REFERENCE bit field. REFERENCE 16-bit value which is XORed with data read from the NAND device. 15.4.3 GPMI Integrated ECC Control Register (HW_GPMI_ECCCTRL) HW_GPMI_ECCCTRL: 0x020 HW_GPMI_ECCCTRL_SET: 0x024 HW_GPMI_ECCCTRL_CLR: 0x028 HW_GPMI_ECCCTRL_TOG: 0x02C The GPMI ECC control register handles configuration of the integrated ECC accelerator. Address: 8000_C000h base + 20h offset = 8000_C020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 R HANDLE W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1346 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) 13 12 11 ECC_CMD 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD0 ENABLE_ECC R 14 RSVD1 15 Bit BUFFER_MASK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_GPMI_ECCCTRL field descriptions Field 31-16 HANDLE 15 RSVD1 14-13 ECC_CMD 12 ENABLE_ECC 11-9 RSVD0 Description This is a register available to software to attach an identifier to a transaction in progress. This handle will be available from the ECC register space when the completion interrupt occurs. Always write zeroes to this bit field. ECC Command information. DECODE -- Decode. ENCODE -- Encode. RESERVE2 -- Reserved. RESERVE3 -- Reserved. 0x0 0x1 0x2 0x3 Enable ECC processing of GPMI transfers. ENABLE -- Use integrated ECC for read and write transfers. DISABLE -- Integrated ECC remains in idle. 0x1 0x0 Always write zeroes to this bit field. BUFFER_MASK ECC buffer information. The BCH error correction only allows two configurations of the buffer mask software may either read just the first block on the flash page or the entire flash page. Write operations must be for the entire flash page. Invalid buffer mask values will cause the DMA descriptor command to be terminated. 0x100 0x1FF BCH_AUXONLY -- Set to request transfer from only the auxiliary buffer (block 0 on flash). BCH_PAGE -- Set to request transfer to/from the entire page. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1347 Programmable Registers 15.4.4 GPMI Integrated ECC Transfer Count Register (HW_GPMI_ECCCOUNT) The GPMI ECC Transfer Count Register contains the count of bytes that flow through the ECC subsystem. Address: 8000_C000h base + 30h offset = 8000_C030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RSVD0 R 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 COUNT W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_GPMI_ECCCOUNT field descriptions Field Description 31-16 RSVD0 Always write zeroes to this bit field. COUNT Number of bytes to pass through ECC. This is the GPMI transfer count plus the syndrome count that will be inserted into the stream by the ECC. In DMA2ECC_MODE this count must match the HW_GPMI_CTRL0_XFER_COUNT. A value of zero will transfer 64K words. 15.4.5 GPMI Payload Address Register (HW_GPMI_PAYLOAD) The GPMI payload address register specifies the location of the data buffers in system memory. This value must be word aligned. Address: 8000_C000h base + 40h offset = 8000_C040h Bit 31 30 29 28 27 26 25 R Bit 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RSVD0 ADDRESS W Reset 23 ADDRESS W Reset 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1348 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) HW_GPMI_PAYLOAD field descriptions Field Description 31-2 ADDRESS Pointer to an array of one or more 512 byte payload buffers. RSVD0 Always write zeroes to this bit field. 15.4.6 GPMI Auxiliary Address Register (HW_GPMI_AUXILIARY) The GPMI auxiliary address register specifies the location of the auxiliary buffers in system memory. This value must be word aligned. Address: 8000_C000h base + 50h offset = 8000_C050h Bit 31 30 29 28 27 26 25 R Bit 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RSVD0 ADDRESS W Reset 23 ADDRESS W Reset 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_GPMI_AUXILIARY field descriptions Field 31-2 ADDRESS RSVD0 Description Pointer to ECC control structure and meta-data storage. Always write zeroes to this bit field. 15.4.7 GPMI Control Register 1 (HW_GPMI_CTRL1) HW_GPMI_CTRL1: 0x060 HW_GPMI_CTRL1_SET: 0x064 HW_GPMI_CTRL1_CLR: 0x068 HW_GPMI_CTRL1_TOG: 0x06C The GPMI control register 1 specifies additional control fields that are not used on a pertransaction basis. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1349 Programmable Registers Address: 8000_C000h base + 60h offset = 8000_C060h 31 30 29 28 27 26 25 24 23 22 RSVD2 BCH_MODE DLL_ENABLE HALF_PERIOD 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATA_IRQRDY_POLARITY RSVD0 0 0 0 0 1 0 DECOUPLE_CS GANGED_RDYBUSY 16 DEV_RESET 17 TIMEOUT_IRQ_EN 18 ABORT_WAIT_REQUEST 19 BURST_EN 20 TIMEOUT_IRQ R 21 RSVD1 Bit WRN_DLY_ SEL Bit DMA2ECC_MODE R RDN_DELAY ABORT_WAIT_ FOR_READY_ CHANNEL GPMI_MODE Reset RSVD W W Reset 0 0 0 0 0 0 0 0 0 0 HW_GPMI_CTRL1 field descriptions Field 31-25 RSVD2 Description Always write zeroes to this bit field. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1350 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) HW_GPMI_CTRL1 field descriptions (continued) Field Description 24 Decouple Chip Select from DMA Channel. Setting this bit to 1 will allow a DMA channel to specify any DECOUPLE_CS value in the CTRL0_CS register field. Software can use one DMA channel to access all 8 Nand devices. 23-22 Since the GPMI write strobe (WRN) is a fast clock pin, the delay on this signal can be programmed to WRN_DLY_SEL match the load on this pin. 0 = 4ns to 8ns; 1 = 6ns to 10ns; 2 = 7ns to 12ns; 3 = no delay. 21 RSVD1 Always write zeroes to this bit field. 20 Setting this bit to 1 will enable timeout IRQ for WAIT_FOR_READY commands in Nand mode. The TIMEOUT_IRQ_ Device_Busy_Timeout value is used for this timeout. EN 19 GANGED_ RDYBUSY Set this bit to 1 will force all Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0. This will free up all, except one, RDY_BUSY input pins. 18 BCH_MODE This bit selects which error correction unit will access GPMI. This bit must always be set to 1, since only the BCH unit is available in this design. 17 DLL_ENABLE Set this bit to 1 to enable the GPMI DLL. This is required for fast NAND reads (above 30MHz read strobe). After setting this bit, wait 64 GPMI clock cycles for the DLL to lock before performing a NAND read. 16 HALF_PERIOD Set this bit to 1 if the GPMI clock period is greater than 16ns for proper DLL operation. DLL_ENABLE must be zero while changing this field. 15-12 RDN_DELAY This variable is a factor in the calculated delay to apply to the internal read strobe for correct read data sampling. The applied delay (AD) is between 0 and 1.875 times the reference period (RP). RP is one half of the GPMI clock period if HALF_PERIOD=1 otherwise it is the full GPMI clock period. The equation is: AD = RDN_DELAY x 0.125 x RP. This value must not exceed 16ns. This variable is used to achieve faster NAND access. For example if the Read Strobe is asserted from time 0 to 13ns but the read access time is 20ns, then choose AD=12ns will cause the data to be sampled at time 25ns (13+12) giving a 5ns data setup time. If RP=13ns then RDN_DELAY = 12/(0.125 x 13ns) = 7.38 (0111b). DLL_ENABLE must be zero while changing this field. 11 DMA2ECC_ MODE 10 RSVD 9 TIMEOUT_IRQ 8 BURST_EN This is mainly for testing HWECC without involving the Nand device. Setting this bit will cause DMA write data to redirected to HWECC module (instead of Nand Device) for encoding or decoding. Always write zeros to this bit field. This bit is set when a timeout occurs using the Device_Busy_Timeout value. Write 0 to clear. When set to 1 each DMA request will generate a 4-transfer burst on the APB bus. 7 Request to abort the wait for ready command on the channel indicated by ABORT_WAIT_ ABORT_WAIT_FOR_READY_CHANNEL. Hardware clears this bit when the abort is done. REQUEST 6-4 Abort a wait for ready command on selected channel. Set the ABORT_WAIT_REQUEST to kick of ABORT_WAIT_ operation. FOR_READY_ CHANNEL Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1351 Programmable Registers HW_GPMI_CTRL1 field descriptions (continued) Field Description 3 DEV_RESET Nand Flash write protection control. ENABLED -- enable write protection for all Nand devices. DISABLED -- disable write protection for all Nand devices. 0x0 0x1 2 ATA_IRQRDY_ POLARITY 1 RSVD0 Always set this bit to 1. Always write zeros to this bit field. 0 GPMI_MODE 0= NAND mode. This bit should be 0 only. 15.4.8 GPMI Timing Register 0 (HW_GPMI_TIMING0) The GPMI timing register 0 specifies the timing parameters that are used by the cycle state machine to guarantee the various setup, hold and cycle times for the external media type. Address: 8000_C000h base + 70h offset = 8000_C070h Bit 31 30 29 28 27 26 25 24 23 RSVD0 R 0 0 0 0 0 21 20 19 18 17 16 15 14 ADDRESS_SETUP W Reset 22 0 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 DATA_HOLD 1 0 0 0 0 0 0 5 4 3 2 1 0 1 1 DATA_SETUP 1 0 0 0 0 0 0 0 HW_GPMI_TIMING0 field descriptions Field 31-24 RSVD0 23-16 ADDRESS_ SETUP Description Always write zeroes to this bit field. Number of GPMICLK cycles that the CE/ADDR signals are active before a strobe is asserted. A value of zero is interpreted as 0. 15-8 DATA_HOLD Data bus hold time in GPMICLK cycles. Also the time that the data strobe is de-asserted in a cycle. A value of zero is interpreted as 256. DATA_SETUP Data bus setup time in GPMICLK cycles. Also the time that the data strobe is asserted in a cycle. A value of zero is interpreted as 256. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1352 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) 15.4.9 GPMI Timing Register 1 (HW_GPMI_TIMING1) The GPMI timing register 1 specifies the timeouts used when monitoring the NAND READY pin and IOWAIT signals. Address: 8000_C000h base + 80h offset = 8000_C080h Bit 31 30 29 28 R 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 0 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSVD0 DEVICE_BUSY_TIMEOUT W Reset 27 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_GPMI_TIMING1 field descriptions Field Description 31-16 Timeout waiting for NAND Ready/Busy. Used in WAIT_FOR_READY mode. This value is the number of DEVICE_BUSY_ GPMI_CLK cycles multiplied by 4096. TIMEOUT RSVD0 Always write zeroes to this bit field. 15.4.10 GPMI DMA Data Transfer Register (HW_GPMI_DATA) The GPMI DMA data transfer register is used by the DMA to read or write data to or from the NAND control state machine. Address: 8000_C000h base + A0h offset = 8000_C0A0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_GPMI_DATA field descriptions Field DATA Description In 8-bit mode, one, two, three or four bytes can can be accessed to send the same number of bus cycles. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1353 Programmable Registers 15.4.11 GPMI Status Register (HW_GPMI_STAT) The GPMI control and status register provides a read back path for various operational states of the GPMI controller. Address: 8000_C000h base + B0h offset = 8000_C0B0h Bit 31 30 29 28 27 26 25 24 23 22 21 READY_BUSY R 20 19 18 17 16 0 0 0 RDY_TIMEOUT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1354 Freescale Semiconductor, Inc. 9 8 DEV4_ERROR DEV3_ERROR DEV2_ERROR DEV1_ERROR DEV0_ERROR 0 0 0 0 0 0 0 0 7 6 5 RSVD0 4 3 2 1 0 PRESENT 10 FIFO_FULL 11 FIFO_EMPTY 12 INVALID_BUFFER_MASK 13 GPMI_RDY1 14 DEV5_ERROR R 15 DEV6_ERROR Bit DEV7_ERROR Chapter 15 General-Purpose Media Interface(GPMI) 0 0 1 0 1 W Reset 0 0 0 HW_GPMI_STAT field descriptions Field 31-24 READY_BUSY Description Read-only view of NAND Ready_Busy Input pins. 23-16 State of the RDY/BUSY Timeout Flags. When any bit is set to '1' in this field, it indicates that a time out RDY_TIMEOUT has occurred while waiting for the ready state of the requested NAND device. Multiple bits may be set simultaneously. When HW_GPMI_CTRL1_DECOUPLE_CS = 0, RDY_TIMEOUT[n] is associated with the NAND device on chip_select[n]. When HW_GPMI_CTRL1_DECOUPLE_CS = 1, these flags become associated to a DMA channel instead of a NAND device. For example if DMA channel 6 sends a WAIT_FOR_READY command for NAND Device 2, and a timeout occured on READY_BUSY2, then READY_TIMEOUT[6] will be set instead of READY_TIMEOUT[2]. 15 DEV7_ERROR 0= No error condition present on NAND Device accessed by DMA channel 7. 14 DEV6_ERROR 0= No error condition present on NAND Device accessed by DMA channel 6. 1= An Error has occurred on NAND Device accessed by DMA channel 7 (Timeout or compare failure, depending on COMMAND_MODE). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1355 Programmable Registers HW_GPMI_STAT field descriptions (continued) Field Description 1= An Error has occurred on NAND Device accessed by DMA channel 6 (Timeout or compare failure, depending on COMMAND_MODE). 13 DEV5_ERROR 0= No error condition present on NAND Device accessed by DMA channel 5. 12 DEV4_ERROR 0= No error condition present on NAND Device accessed by DMA channel 4. 11 DEV3_ERROR 0= No error condition present on NAND Device accessed by DMA channel 3. 10 DEV2_ERROR 0= No error condition present on NAND Device accessed by DMA channel 2. 9 DEV1_ERROR 0= No error condition present on NAND Device accessed by DMA channel 1. 8 DEV0_ERROR 0= No error condition present on NAND Device accessed by DMA channel 0. 1= An Error has occurred on NAND Device accessed by DMA channel 5 (Timeout or compare failure, depending on COMMAND_MODE). 1= An Error has occurred on NAND Device accessed by DMA channel 4 (Timeout or compare failure, depending on COMMAND_MODE). 1= An Error has occurred on NAND Device accessed by DMA channel 3 (Timeout or compare failure, depending on COMMAND_MODE). 1= An Error has occurred on NAND Device accessed by DMA channel 2 (Timeout or compare failure, depending on COMMAND_MODE). 1= An Error has occurred onNAND Device accessed by DMA channel 1 (Timeout or compare failure, depending on COMMAND_MODE). 1= An Error has occurred on NAND Device accessed by DMA channel 0 (Timeout or compare failure, depending on COMMAND_MODE). 7-5 RSVD0 Always write zeroes to this bit field. 4 GPMI_RDY1 Status of theGPMI_RDY1 input pin. 3 0= ECC Buffer Mask is not invalid. INVALID_ 1= ECC Buffer Mask is invalid. BUFFER_MASK 2 FIFO_EMPTY 0= FIFO is not empty. 1= FIFO is empty. 0x0 0x1 1 FIFO_FULL 0= FIFO is not full. 1= FIFO is full. 0x0 0x1 0 PRESENT NOT_EMPTY -- FIFO is not empty. EMPTY -- FIFO is empty. NOT_FULL -- FIFO is not full. FULL -- FIFO is full. 0= GPMI is not present in this product. 1= GPMI is present is in this product. 0x0 0x1 UNAVAILABLE -- GPMI is not present in this product. AVAILABLE -- GPMI is present in this product. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1356 Freescale Semiconductor, Inc. Chapter 15 General-Purpose Media Interface(GPMI) 15.4.12 GPMI Debug Information Register (HW_GPMI_DEBUG) The GPMI debug information register provides a read back path for diagnostics to determine the current operating state of the GPMI controller. Address: 8000_C000h base + C0h offset = 8000_C0C0h Bit 31 R 30 29 28 27 26 25 24 23 22 WAIT_FOR_READY_END 21 20 19 18 17 16 15 14 13 DMA_SENSE 12 11 10 9 8 7 6 DMAREQ 5 4 3 2 1 0 0 0 CMD_END W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_GPMI_DEBUG field descriptions Field Description 31-24 WAIT_FOR_ READY_END Read Only view of the Wait_For_Ready End toggle signals to DMA. One per channel 23-16 DMA_SENSE Read-only view of sense state of the 8 DMA channels. A value of 1 in any bit position indicates that a read and compare command failed or a timeout occured for the corresponding channel. 15-8 DMAREQ Read-only view of DMA request line for 8 DMA channels. A toggle on any bit position indicates a DMA request for the corresponding channel. CMD_END Read Only view of the Command End toggle signals to DMA. One per channel 15.4.13 GPMI Version Register (HW_GPMI_VERSION) This register reflects the version number for the GPMI. Address: 8000_C000h base + D0h offset = 8000_C0D0h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 HW_GPMI_VERSION field descriptions Field 31-24 MAJOR Description Fixed read-only value reflecting the MAJOR field of the RTL version. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1357 Programmable Registers HW_GPMI_VERSION field descriptions (continued) Field 23-16 MINOR STEP Description Fixed read-only value reflecting the MINOR field of the RTL version. Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1358 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 16.1 Overview The hardware ECC accelerator provides a forward error-correction function for improving the reliability of various storage media that may be attached to the device. For example, NAND flash devices use a spare area to store ecc codes to correct some hard bit errors in data stored within the device, allowing higher device yields and, therefore, lower NAND device costs. The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is capable of correcting from 2 to 20 single bit errors within a block of data no larger than about 900 bytes (512 bytes or 1024 bytes are typical) in applications such as protecting data and resources stored on modern NAND flash devices. The correction level in the BCH block is programmable to provide flexibility for varying applications and configurations of flash page size. The design can be programmed to encode protection of 2, 4, 6, 8, 10, 12, 14, 16, 18, or 20 bit errors when writing flash and to correct the corresponding number of errors on decode. The correction level when decoding MUST be programmed to the same correction level as was used during the encode phase. BCH-codes are a type of block-code, which implies that all error-correction is performed over a block of N-symbols. The BCH operation will be performed over GF(213 = 8192), which is the Galois Field consisting of 8191 one-bit symbols. BCH-encoding (or encode for any block-code) can be performed by two algorithms: systematic encoding or multiplicative encoding. Systematic encoding is the process of reading all the symbols which constitute a block, dividing continuously these symbols by the generator polynomial for the GF(8192) and appending the resulting t parity symbols to the block to create a BCH codeword (where t is the number of correctable bits). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1359 Overview The BCH encode process creates t*13-bit parity symbols for each data block when the data is written to the flash device. The parity symbols are written to the flash device after the corresponding data block, and together these are collectively called the codeword. The codeword can be used during the decode process to correct errors that occur in either the data or parity blocks. The BCH decoder processes code words in a 4-step fashion: 1. Syndrome Calculation (SC): This is the process of reading in all of the symbols of the codeword and continuously dividing by the generator polynomial for the field. 2*t syndromes must be calculated for each codeword and inspection of the syndromes determines if there are errors: a non-zero set of syndromes indicates one or more errors. This process is implemented parallel hardware to minimize processing time since it must be done every time the decode is performed. 2. Key Equation Solver (KES): The syndromes represent 2t-linear equations with 2tunknown variables. The process of solving these equations and selecting from the numerous solutions constitutes the KES module. When the KES block completes its operations, it generates an error locator polynomial (sigma) that is used in the proceeding block to determine the locations and values of the errors. 3. Chien Search (CS): This block takes input from the KES block and uses the Chien Algorithm for finding the locations of the errors based on the error locator polynomial. The method basically involves substituting all 8191 symbols from the GF(8192) into the locator polynomial. All evaluations that produce a zero solution indicate locations of the various errors. Since each located error corresponds to a single bit, the bit in the original data may be corrected by simply flipping the polarity of the incorrect location. 4. Correction: this block has to convert the symbol index and mask information to memory byte indexes and masks. The BCH block, shown in the figure, was designed to operate in a pipelined fashion to maximize throughput. Aside from the initial latency to fill the pipeline stages, the BCH throughput is faster than the fastest GPMI read rate of 2 cycles/byte. Thus, the bottleneck in performing NAND reads and error corrections is the GPMI read rate. Current GPMI read rates are approximately 3 cycles/byte for the current generation of NAND flash. The CPU is not directly involved in generating parity symbols, checking for errors, or correcting them. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1360 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) AXI APBH GPMI Programmable Registers APBH Bridge/DMA BCH Programmable Registers BCH Engine Transfer Controls Parity Generation Write Data GPMI NAND CONTROLLER Write Data synpar Read Data Syndrome Calculation Read Data syndromes AXI master & transfer FSM Key Equation Solver error-locator polynomial GPMI clock domain Chien Search corrections Figure 16-1. Hardware BCH Accelerator 16.2 Operation Before performing any NAND flash read or write operations, software should first program the BCH's flash layout registers (see Flash Page Layout) to specify how data is to be formatted on the flash device. The BCH hardware allows full programmability over the flash page layout to enable users flexibility in balancing ECC correction levels and ever-changing flash page sizes. To initiate a NAND Flash write, software will program a GPMI DMA operation. The DMA need only program the GPMI control registers (and handle the requisite flash addressing handshakes) since the BCH will handle all data operations using its AXI bus interface. The BCH will then send the data to the GPMI controller to be written to flash i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1361 Operation as it computes the parity symbols. At the end of each data block the BCH will insert the parity symbols into the data stream so that the GPMI sees only a continuous stream of data to be written. NAND Flash read operations operate in a similar manner. As the GPMI controller reads the device, all data is sent to the BCH hardware for error detection/correction. The BCH controller writes all incoming read data to system memory and in parallel computes the syndromes used to detect bit errors. If errors are detected within a block, the BCH hardware activates the error correction logic to determine where bit errors have occurred and ultimately correct them in the data buffer in system memory. After an entire flash page has been read and corrected, the BCH will signal an interrupt to the CPU. The figure below indicates how data read from the GPMI is operated on within the BCH hardware. As the BCH receives data from the GPMI (top row), it is written to memory by the BCH's Bus Interface Unit (BIU) (second row). For blocks requiring correction, the KES logic will be activated after the entire block has been received. Once the error locator polynomial has been computed, the corrections are determined by the Chien Search and fed back to the BIU, which performs a read, modify, write operation on the buffer in memory to correct the data. GPMI/ Syndrome BIU KES Chien Search ECC Done Interrupt Read Block 0 Read Block 1 Read Block 2 Read Block 3 Read Block 4 Read Block 5 Read Block 6 Read Block 7 Write Block 0 Write Block 1 Write Block 2 / Correct Block 0 Write Block 3 / Correct Block 1 Write Block 4 / Correct Block 2 Write Block 5 / Correct Block 3 Write Block 6 / Correct Block 4 Write Block 7 / Correct Block 5 KES Block 3 KES Block 4 KES Block 5 KES Block 6 KES Block 7 CS Block 3 CS Block 4 CS Block 5 CS Block 6 KES Block 0 KES Block 1 CS Block 0 KES Block 2 CS Block 1 CS Block 2 Correct Block 6 Correct Block 7 CS Block 7 Figure 16-2. Block Pipeline while Reading Flash 16.2.1 BCH Limitations and Assumptions * The BCH is programmable to support 2, 4, 6, 8, 10, 12, 14, 16, 18, and 20 bit error correction. ECC0 is supported as a pass-through, non-correcting mode. * Data block sizes must be a multiple of 4 bytes and be aligned in system memory. * The BCH supports a programmable number of metadata/auxiliary data bytes, from 0 to 255. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1362 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) * Metadata will be written at the beginning of the flash page to facilitate fast access for filesystem operations. * Metadata may be treated as an independent block for ECC purposes or combined with the first data block to conserve bits in the flash. * The BCH does not support a partial page write (this can be accomplished by programming the BCH layout registers such that the BCH only sees a portion of the page). * Flash read operations can read the entire page or the first block on the page. * The BCH also supports a memory-to-memory mode of operation that does not require the use of DMA or the GPMI. 16.2.2 Flash Page Layout The BCH supports a fully programmable flash page layout. The BCH maintains four independent layout registers that can describe four completely different NAND devices or layouts. When the BCH initiates an operation, it selects one of the layouts by using the chip select as an index into the BCH_LAYOUTSELECT register that determines which layout should be used for the operation. Three possible (generic) flash layout schemes are supported, as indicated in the figure below. (In each case, the metadata size may also be programmed to 0 bytes). Metadata may either be combined with the first block of data or the size of the first data block can be programmed to 0 to allow the metadata to be protected by its own ECC parity bits. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1363 Operation Block 0 Size=10B ECC=4 Block 1 Size=512B ECC=14 dn-1 512B parity d2 512B parity d1 512B parity d0 512B parity parity meta 10B parity Separate ECC over Metadata dn 512B Block 2 Size=512B ECC=14 parity dn-1 512B dn 512B parity Block 1 Size=512B ECC=16 d2 512B dn 516B parity Block 0 Size=522B ECC=16 d1 512B parity d0 512B parity meta 10B parity Combined Metadata & Block 0, unbalanced ECC coverage Block 2 Size=512B ECC=16 Block 0 Size=516B ECC=14 Block 1 Size=516B ECC=14 d2 2 516B dn-1 516B parity d1 516B parity d0 484B parity meta 32B parity Combined Metadata & Block 0, balanced ECC coverage Block 2 Size=516B ECC=14 Figure 16-3. FLASH Page Layout Options Each layout is determined by a pair of registers that define the following parameters: * DATA0_SIZE: Indicates the number of data bytes in the first block on the page (this should not include parity or metadata bytes). This should be set to 0 when the metadata is to be covered separately with its own ECC. This must be a multiple of 4 bytes. * ECC0: Indicates the ECC level to be used for the first block on the flash (data0+metadata). * META_SIZE: Indicates the number of bytes (from 0-255) that are stored as metadata. * NBLOCKS: Indicates the number of subsequent DATAN blocks on the flash, or the number of blocks following the DATA0 block. * DATAN_SIZE: Indicates the number of data bytes in all subsequent data blocks. This MUST be a multiple of 4 bytes. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1364 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) * ECCN: Indicates the ECC level to be used for the subsequent data blocks. * PAGE_SIZE: Indicates the total number of bytes available per page on the physical flash device. This includes the spare area and is typically 4096+128, 4096+218, or 2048+64 bytes. 16.2.3 Determining the ECC layout for a device Since the BCH is programmable, a system can trade off ECC levels for flash size and layout configurations. The following examples indicate how to determine a valid layout based on the required storage space and flash size. For all cases, the size of the parity will be 13*ECC level bits-- so for ECC8, 13 bytes are required (per block). 16.2.3.1 4K+218 flash, 10 bytes metadata, 512 byte data blocks, separate metadata In this case, we have 8 data blocks each consisting of 512 bytes. Since the flash has 218 spare bytes (1744 bits), first estimate an ECC level for the data blocks by first subtracting the number of metadata bytes from the spare bytes (218 - 10 = 208 bytes = 1664 bits) then dividing the number of bits by 8 (number of blocks) and then by 13 (bits per ECC level). (218 - 10) x 8 = 1664/13(8) = 16 Therefore all the data blocks could be covered by ECC16 if the metadata had no parity. This isn't acceptable, so assume ECC14 for all the data blocks. Now calculate the number of free bits for the metadata parity as 1664 - (14) x 13 x 8 = 208 Therefore, 208 bits remain for metadata parity. Dividing by 13 (bits/ECC) gives 16, so the metadata can be covered with ECC16. The settings for this device would then be Table 16-1. Settings for 4K+218 FLASH Setting Value PAGE_SIZE 4096+218=4314=0x10DA META_SIZE 10=0x0A DATA0_SIZE 0 ECC0 16=0x10 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1365 Operation Table 16-1. Settings for 4K+218 FLASH (continued) Setting Value DATAN_SIZE 512=0x200 ECCN 14=0x0E NBLOCKS 8 16.2.3.2 4K+128 flash, 10 bytes metadata, 512 byte data blocks, separate metadata This flash will have 118 bytes available for ECC (after subtracting the metadata size), therefore, 994 bits. Dividing by 8*13 (number of blocks * ECC level) we get 9.07, therefore we can support ECC8 on the data blocks. The number of free spare bits becomes 944 - 8 * 8 * 13 = 944 832 = 112, divided by 13 = 8.6, therefore the metadata can be also covered by ECC8. Table 16-2. Settings for 4K+128 FLASH Setting Value PAGE_SIZE 4096+128=4224=0x1080 META_SIZE 10=0x0A DATA0_SIZE 0 ECC0 8 DATAN_SIZE 512=0x200 ECCN 8 NBLOCKS 8 In this case, there will be additional unused spare bits, with the BCH will pad out with zeros. 16.2.4 Data Buffers in System Memory While the data on the flash is interleaved with parity symbols, the BCH assumes that the data buffers in memory are contiguous. Metadata read from the flash will be stored to the location pointed to by the GPMI_AUXILIARY register and data will be written to the address specified in the GPMI_PAYLOAD register as is shown in the following figure. Since the number of blocks on a flash page is programmable, the BCH also writes individual block correction i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1366 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) status to the auxiliary pointer at the word-aligned address following the end of the metadata. Optionally, the computed syndromes may also be written to the auxiliary area if the DEBUGSYNDROME bit is set in the control register. As blocks complete processing, the bus master will accumulate the status for each block and write it to the auxiliary data buffer following the metadata. The metadata area will be padded with 0's until the next word boundary and the status for blocks 0-3 will be written to the next word. The status for subsequent blocks will then be written to the buffer. The status for the first block (metadata block) is also stored in the STATUS_BLK0 register in the BCH_STATUS register. The completion codes for the blocks are indicated in the Table 16-3. Note that the definition of the bytes and their ordering in the auxiliary and payload storage areas are user defined. When this data is read back from the flash and put into memory, it will resemble the original buffer that was written out to the flash. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1367 Operation Minimum System Memory Footprint: HW_GPMI_AUXILIARY HW_GPMI_PAYLOAD 512 byte Payload A 512 byte Payload B 512 byte Payload C 512 byte Payload D META_SIZE bytes of auxiliary storage (programmable - block is padded w/ 0's to word boundary) Status for each block. (Optional n bytes syndromes for Payload A) (Optional n bytes syndrome for Payload B) (Optional n bytes syndrome for Payload C) (Optional n bytes syndrome for Payload D) Computed syndrome area consists of 2*t 13-bit symbols written as 16-bit half word. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1368 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) Table 16-3. Status Block Completion Codes Code Description 0xFF Block is erased 0xFE Block is uncorrectable 0x00 No errors found 0x01-0x14 Number of errors corrected The following figure shows the layout of the bytes within the status field. 3 2 1 0 Metadata 0 0 Block 3 Status Block 2 Status Block 1 Status block 0 Status Block 7 Status Block 6 Status Block 5 Status Block 4 Status 0 0 0 Block 8 Status Status bytes are allocated based on the NBLOCKS programmed into the flash format register. The number of status bytes will be computed by the NBLOCKS+1. The status area will be padded with zeros to the next word boundary. Syndrome data written for debug purposes will follow the end of the status block. Figure 16-5. Memory-to-Memory Operations 16.3 Memory to Memory (Loopback) Operation The BCH supports a memory-to-memory mode of operation where both the encoded and decoded buffers reside in system memory. This can be useful for applications where data must be protected by ECC, but the storage device does not reside on the GPMI bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1369 Programming the BCH/GPMI Interfaces The BCH operation in memory to memory mode is much simpler than in GPMI mode since DMAs are not required to manage the operation. Instead, software simply writes the BCH_DATAPTR and BCH_METAPTR with the addresses of the data and metadata (auxiliary) buffers and the BCH_ENCODEPTR with the address of the buffer for encoded data. To initiate the operation, software simply sets the M2M_ENCODE and M2M_ENABLE bits in the control register. The BCH can be programmed to either issue an interrupt at the end of the operation or software may poll the status bits for completion. Memory to memory decode operations work in a similar manner. The encoded data address is written to the BCH_ENCODEPTR and the data and meta pointers are written to buffers that correspond to the desired decoded data addresses. To initiate a decode, software must set the M2M_ENCODE bit to 0 while writing the M2M_ENABLE bit. Note that the addresses written to the BCH_DATAPTR, BCH_METAPTR and BCH_ENCODEPTR registers should always be aligned on a 4 byte boundary. In other words, the 2 lower bits of the address should always be written with zeros. 16.4 Programming the BCH/GPMI Interfaces Programming the BCH for NAND operations consists largely of disabling the soft reset and clock bits (SFTRST and CLKGATE) from the BCH_CTRL register and then programming the flash layout registers to correspond to the format of the attached NAND device(s). The BCH_LAYOUTSELECT register should also be programmed to map the chip select of each attached device into one of the four layout registers. The bulk of the programming is actually applied to the GPMI through PIO operations embedded in DMA command structures. The DMA will perform all the requisite handshaking with the GPMI interface to negotiate the address portion of the transfer, then the BCH will handle all the movement of data from memory to the GPMI (writes) or the GPMI to memory (reads). The BCH will direct all data blocks to the buffer pointed to by the PAYLOAD_BUFFER and the metadata will be written to the AUXILIARY_BUFFER. Both of these registers are located in the GPMI PIO data space and are communicated to the BCH hardware at the beginning of the transfer. Thus, the normal multi-NAND DMA based device interleaving is preserved, that is, four NANDs on four separate chip selects can be scheduled for read or write operations using the BCH. Whichever channel finishes its ready wait first and enters the DMA arbiter with its lock bit set owns the GPMI command interface and through it owns the BCH resources for the duration of its processing. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1370 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 16.4.1 BCH Encoding for NAND Writes The BCH encoder flowchart in Figure 16-6 shows the detailed steps involved in programming and using the BCH encoder. This flowchart shows how to use the BCH block with the GPMI. To use the BCH encoder with the GPMI's DMA, create a DMA command chain containing ten descriptor structures, as shown in Figure 16-8 and detailed in the DMA structure code example that follows it in DMA Structure Code Example. The ten descriptors perform the following tasks: 1. Disable the BCH block (in case it was enabled) and issue NAND write setup command byte (under CLE) and address bytes (under ALE). 2. Configure and enable the BCH and GPMI blocks to perform the NAND write. 3. Disable the BCH block and issue NAND write execute command byte (under CLE). 4. Wait for the NAND device to finish writing the data by watching the ready signal. 5. Check for NAND timeout through PSENSE. 6. Issue NAND status command byte (under CLE). 7. Read the status and compare against expected. 8. If status is incorrect or incomplete, branch to error handling descriptor chain. 9. Otherwise, write is complete and emit GPMI interrupt. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1371 Programming the BCH/GPMI Interfaces BCH ENCODE & WRITE NAND Run the prescribe initialization sequence. Point the GPMI DMA channel 4 (or 5 or 6 or 7) at the prescribed static DMA sequence. Start the DMA. Return and wait for DMA channel 4 (or 5 or 6 or 7) command complete interrupt. STOP APBH DMA CH4 Command Complete ISR Must use SCT clear HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ = 0 Start GPMI DMA chain for next write or read transfer. STOP Figure 16-6. BCH Encode Flowchart Descriptor Legend NEXT CMD ADDR CMD <= xfer_count cmdwords wait4endcmd semaphore nandwait4ready nandlock address address_increment irqoncmplt chain command BUFFER ADDR HW_GPMI_CTRL0 <= command_mode HW_GPMI_COMPARE <= HW_GPMI_ECCCTRL <= word_length lock_cs CS mask xfer_count reference ecc_cmd enable_ecc buffer_mask HW_GPMI_ECCCOUNT HW_GPMI_PAYLOAD HW_GPMI_AUXILIARY Figure 16-7. BCH DMA Descriptor Legend i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1372 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) Descriptor 1: Disable BCH engine and issue NAND write set-up command and address (CLE/ALE). NEXT CMD ADDR CMD <= 1+5 3 1 0 0 1 0 1 DMA_READ BUFFER ADDR HW_GPMI_CTRL0 <= write HW_GPMI_COMPARE <= 8_bit enabled 2 NAND_CLE 1 null 1 Byte NAND CMD 1+5 5 Byte ADDR null HW_GPMI_ECCCTRL <= disable NOTE: No DMA data transferred to GPMI when using BCH Descriptor 2: Enable the BCH engine and write the data payload. NEXT CMD ADDR CMD <= 0 4 1 0 0 1 0 1 NO_DMA_XFER BUFFER ADDR HW_GPMI_CTRL0 <= write HW_GPMI_COMPARE <= 8_bit enabled 2 NAND_DATA 0 null HW_GPMI_ECCCTRL <= 0 null encode_8_bit HW_GPMI_ECCCOUNT<= enable 0x1FF 8*512 Byte Data Payload Buffer 4096+218 (flash page size) HW_GPMI_PAYLOAD HW_GPMI_AUXILIARY Auxiliary Payload Buffer Descriptor 3: Disable BCH engine and issue NAND write execute command (CLE). NEXT CMD ADDR CMD <= 1 3 1 0 0 1 0 1 DMA_READ BUFFER ADDR HW_GPMI_CTRL0 <= write HW_GPMI_COMPARE <= 8_bit enabled 2 NAND_CLE 0 null HW_GPMI_ECCCTRL <= 1 1 Byte NAND CMD null ---- disable ---- Descriptor 4: Wait for NAND ready. NEXT CMD ADDR CMD <= HW_GPMI_CTRL0 <= 0 1 1 BUFFER ADDR wait_for_ready 0 1 0 0 1 NO_DMA_XFER 8_bit disabled 2 NAND_DATA 0 0 Descriptor 5: PSENSE compare for time-out. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 0 0 1 DMA_SENSE DMA Error Descriptor Chain Descriptor 6: Disable BCH engine (if enabled by another thread) and issue NAND status command (CLE). NEXT CMD ADDR CMD <= 1 3 1 0 0 1 0 1 DMA_READ BUFFER ADDR HW_GPMI_CTRL0 <= write HW_GPMI_COMPARE <= 8_bit enabled 2 NAND_CLE 0 null HW_GPMI_ECCCTRL <= 1 1 Byte NAND CMD null ---- disable ---- Descriptor 7: Read the NAND status and compare against expected value. NEXT CMD ADDR CMD <= 0 2 1 0 0 1 0 1 NO_DMA_XFER BUFFER ADDR HW_GPMI_CTRL0 <= read_and_compare HW_GPMI_COMPARE <= 8_bit disabled 2 NAND_DATA 0 1 Descriptor 8: PSENSE compare for status comparison check. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 0 0 1 DMA_SENSE Descriptor 9: Emit GPMI DMA interrupt. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 0 1 0 NO_DMA_XFER Figure 16-8. BCH Encode DMA Descriptor Chain i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1373 Programming the BCH/GPMI Interfaces 16.4.1.1 DMA Structure Code Example The following code sample illustrates the coding for one write transaction involving 4096 bytes of data payload (eight 512-byte blocks) and 10 bytes of auxiliary payload (also referred to as metadata) to a 4K NAND page sitting on GPMI CS2. //---------------------------------------------------------------------------// generic DMA/GPMI/ECC descriptor struct, order sensitive! //---------------------------------------------------------------------------typedef struct { // DMA related fields unsigned int dma_nxtcmdar; unsigned int dma_cmd; unsigned int dma_bar; // GPMI related fields unsigned int gpmi_ctrl0; unsigned int gpmi_compare; unsigned int gpmi_eccctrl; unsigned int gpmi_ecccount; unsigned int gpmi_data_ptr; unsigned int gpmi_aux_ptr; } GENERIC_DESCRIPTOR; //---------------------------------------------------------------------------// allocate 10 descriptors for doing a NAND ECC Write //---------------------------------------------------------------------------GENERIC_DESCRIPTOR write[10]; //---------------------------------------------------------------------------// DMA descriptor pointer to handle error conditions from psense checks //---------------------------------------------------------------------------unsigned int * dma_error_handler; //---------------------------------------------------------------------------// 8 byte NAND command and address buffer // any alignment is ok, it is read by the GPMI DMA // byte 0 is write setup command // bytes 1-5 is the NAND address // byte 6 is write execute command // byte 7 is status command //---------------------------------------------------------------------------unsigned char nand_cmd_addr_buffer[8]; //---------------------------------------------------------------------------// 4096 byte payload buffer used for reads or writes // needs to be word aligned //---------------------------------------------------------------------------unsigned int write_payload_buffer[(4096/4)]; //---------------------------------------------------------------------------// 65 byte meta-data to be written to NAND // needs to be word aligned //---------------------------------------------------------------------------unsigned int write_aux_buffer[65]; //---------------------------------------------------------------------------// Descriptor 1: issue NAND write setup command (CLE/ALE) //---------------------------------------------------------------------------write[0].dma_nxtcmdar = &write[1]; // point to the next descriptor write[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1 + 5)| // 1 byte command, 5 byte address BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to the GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before // continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels from // taking over BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1374 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // read data from DMA, write to NAND write[0].dma_bar = &nand_cmd_addr_buffer; // byte 0 write setup, bytes 1 - 5 NAND address // 3 words sent to the GPMI write[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, ENABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_CLE) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (1) | // send command and address BF_GPMI_CTRL0_XFER_COUNT (1 + 5); // 1 byte command, 5 byte address write[0].gpmi_compare = NULL; // field not used but necessary to set eccctrl write[0].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block //---------------------------------------------------------------------------// Descriptor 2: write the data payload (DATA) //---------------------------------------------------------------------------write[1].dma_nxtcmdar = &write[2]; // point to the next descriptor write[1].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0)| // NOTE: No DMA data transfer BF_APBH_CHn_CMD_CMDWORDS (4)| // send 4 words to the GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1)| // Wait to end BF_APBH_CHn_CMD_SEMAPHORE (0)| BF_APBH_CHn_CMD_NANDWAIT4READY (0)| BF_APBH_CHn_CMD_NANDLOCK (1)| // maintain resource lock BF_APBH_CHn_CMD_IRQONCMPLT (0)| BF_APBH_CHn_CMD_CHAIN (1)| // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, DMA_NO_XFER); // No data transferred write[1].dma_bar = &write_payload_buffer; // pointer for the 4K byte data area // 4 words sent to the GPMI write[1].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, ENABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA)| BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (0); // NOTE: this field contains // the total amount // DMA transferred to GPMI via DMA (0)! write[1].gpmi_compare = NULL; // field not used but necessary to set eccctrl write[1].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD, ENCODE_8_BIT) | // specify t = 8 mode BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE) | // enable ECC module BF_GPMI_ECCCTRL_BUFFER_MASK (0x1FF); // write all 8 data blocks // and 1 aux block write[1].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(4096+218); // specify number of bytes // written to NAND write[1].gpmi_data_pointer = &write_payload_pointer; // data buffer address write[1].gpmi_aux_pointer = &write_aux_pointer; // metadata pointer //---------------------------------------------------------------------------// Descriptor 3: issue NAND write execute command (CLE) //---------------------------------------------------------------------------write[2].dma_nxtcmdar = &write[3]; // point to the next descriptor write[2].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // 1 byte command BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to the GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before // continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // maintain resource lock i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1375 Programming the BCH/GPMI Interfaces BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // follow chain to next command // read data from DMA, write to NAND write[2].dma_bar = &nand_cmd_addr_buffer[6]; // point to byte 6, write execute command // 3 words sent to the GPMI write[2].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, ENABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_CLE) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (1); // 1 byte command write[2].gpmi_compare = NULL; // field not used but necessary to set eccctrl write[2].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block //---------------------------------------------------------------------------// Descriptor 4: wait for ready (CLE) //---------------------------------------------------------------------------write[3].dma_nxtcmdar = &write[4]; // point to the next descriptor write[3].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT BF_APBH_CHn_CMD_CMDWORDS BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | (1) | (1) | // no dma transfer // send 1 word to the GPMI // wait for command to finish before // continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(1) | // wait for nand to be ready BF_APBH_CHn_CMD_NANDLOCK (0) | // relinquish nand lock BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer write[3].dma_bar = NULL; // field not used // 1 word sent to the GPMI write[3].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WAIT_FOR_READY) | // wait for NAND ready BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, DISABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (0); //---------------------------------------------------------------------------// Descriptor 5: psense compare (time out check) //---------------------------------------------------------------------------write[4].dma_nxtcmdar = &write[5]; // point to the next descriptor write[4].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (0) | // no words sent to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | // do not wait to continue BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); // perform a sense check write[4].dma_bar = dma_error_handler; // if sense check fails, branch to error handler //---------------------------------------------------------------------------// Descriptor 6: issue NAND status command (CLE) //---------------------------------------------------------------------------write[5].dma_nxtcmdar = &write[6]; // point to the next descriptor write[5].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // 1 byte command BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to the GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1376 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) taking over BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels from BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // read data from DMA, write to NAND write[5].dma_bar = &nand_cmd_addr_buffer[7]; // point to byte 7, status command write[5].gpmi_compare = NULL; // field not used but necessary to set eccctrl write[5].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block // 3 words sent to the GPMI write[5].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, ENABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_CLE) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (1); // 1 byte command //---------------------------------------------------------------------------// Descriptor 7: read status and compare (DATA) //---------------------------------------------------------------------------write[6].dma_nxtcmdar = &write[7]; // point to the next descriptor write[6].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (2) | // send 2 words to the GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before // continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // maintain resource lock BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer write[6].dma_bar = NULL; // field not used // 2 word sent to the GPMI write[6].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ_AND_COMPARE) | // read from the // NAND and // // compare to expect BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, DISABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (1); write[6].gpmi_compare = ; // NOTE: mask and reference values are NAND // SPECIFIC to evaluate the NAND status //---------------------------------------------------------------------------// Descriptor 8: psense compare (time out check) //---------------------------------------------------------------------------write[7].dma_nxtcmdar = &write[8]; // point to the next descriptor write[7].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (0) | // no words sent to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | // do not wait to continue BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | // relinquish nand lock BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); // perform a sense check write[7].dma_bar = dma_error_handler; // if sense check fails, branch to error handler //---------------------------------------------------------------------------// Descriptor 9: emit GPMI interrupt //---------------------------------------------------------------------------write[8].dma_nxtcmdar = NULL; // not used since this is i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1377 Programming the BCH/GPMI Interfaces last descriptor write[8].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | BF_APBH_CHn_CMD_CMDWORDS (0) | BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (1) | BF_APBH_CHn_CMD_CHAIN (0) | processing BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer // no words sent to GPMI // do not wait to continue // emit GPMI interrupt // terminate DMA chain // no dma transfer 16.4.1.2 Using the BCH Encoder To use the BCH encoder, first turn off the module-wide soft reset bit in both the GPMI and BCH blocks before starting any DMA activity. Turning off the soft reset must take place by itself, prior to programming the rest of the control registers. Turn off the BCH bus master soft reset bit (bit 29). Turn off the clock gate bits. Program the remainder of the GPMI, BCH and APBH DMA as follows: // bring APBH out of reset APBH_CTRL0_CLR(BM_APBH_CTRL0_SFRST); APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE); // bring BCH out of reset BCH_CTRL_CLR(BM_BCH_CTRL_SFTRST); BCH_CTRL_CLR(BM_BCH_CTRL_CLKGATE); // bring gpmi out of reset GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST); GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE); GPMI_CTRL1_SET(BM_GPMI_CTRL1_DEV_RESET | // deassert reset BM_GPMI_CTRL1_BCH_MODE ); // enable BCH mode // enable pinctrl PINCTRL_CTRL_WR(0x00000000); // enable GPMI through alt pin wiring PINCTRL_MUXSEL0_CLR(0xff000000); PINCTRL_MUXSEL0_SET(0xaa000000); // to use the primary pins do the following // PINCTRL_MUXSEL4_CLR(0xff000000); // PINCTRL_MUXSEL4_SET(0x55000000); // enable gpmi pins PINCTRL_MUXSEL0_CLR(0x0000ffff); // data bits PINCTRL_MUXSEL1_CLR(0x000fffff); // control bits Note that for writing NANDs (ECC encoding), only GPMI DMA command complete interrupts are used. The BCH engine is used for writing to the NAND but may optionally produces an interrupt. From the sample code in DMA Structure Code Example: * DMA descriptor 1 prepares the NAND for data write by using the GPMI to issue a write setup command byte under CLE, then sends a 5-byte address under ALE. The BCH engine is disabled and not used for these commands. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1378 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) * DMA descriptor 2 enables the BCH engine for encoding to begin the initial writing of the NAND data by specifying where the data and auxiliary payload are coming from in system memory. * DMA descriptor 3 issues the write commit command byte under CLE to the NAND. * DMA descriptor 4 waits for the NAND to complete the write commit/transfer by watching the NAND's ready line status. This descriptor relinquishes the NANDLOCK on the GPMI to enable the other DMA channels to initiate NAND transactions on different NAND CS lines. * DMA descriptor 6 issues a NAND status command byte under "CLE" to check the status of the NAND device following the page write. * DMA descriptor 7 reads back the NAND status and compares the status with an expected value. If there are differences, then the DMA processing engine follows an error-handling DMA descriptor path. * DMA descriptor 8 disables the BCH engine and emits a GPMI interrupt to indicate that the NAND write has been completed. 16.4.2 BCH Decoding for NAND Reads When a page is read from NAND flash, BCH syndromes will be computed and, if correctable errors are found, they will be corrected on a per block basis within the NAND page. This decoding process is fully overlapped with other NAND data reads and with CPU execution. The BCH decoder flowchart in the figure below shows the steps involved in programming the decoder. The hardware flow of reading and decoding a 4096-byte page is shown in Figure 16-10. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1379 Programming the BCH/GPMI Interfaces Read NAND & BCH Decode Run the prescribe initialization Sequence Point the GPMI DMA channel 4 (or 5 or 6 or 7) at the prescribed static DMA sequence Start the DMA Return and wait for DMA channel 4 (or 5 or 6 or 7) command complete interrupt. STOP APBH DMA CH4 Command Complete ISR Must use SCT clear HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ = 0 Start GPMI DMA chain for next write or read transfer STOP BCH Complete ISR Read status regs and store for processing Must use SCT clear HW_BCH_CTRL_COMPLETE_IRQ = 0 STOP Figure 16-9. BCH Decode Flowchart Conceptually, an APHB DMA Channel (0,1,2,3,4,5,6,7,8,9,10 or11) command chain with seven command structures linked together is used to perform the BCH decode operation (as shown in Figure 16-10). Note The GPMI's DMA command structures controls the BCH decode operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1380 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) To use the BCH decoder with the GPMI's DMA, create a DMA command chain containing seven descriptor structures, as shown in the figure below and detailed in the DMA structure code example that follows it in DMA Structure Code Example. The seven DMA descriptors perform the following tasks: 1. Issue NAND read setup command byte (under "CLE") and address bytes (under "ALE"). 2. Issue NAND read execute command byte (under "CLE"). 3. Wait for the NAND device to complete accessing the block data by watching the ready signal. 4. Check for NAND timeout through "PSENSE". 5. Configure and enable the BCH block and read the NAND block data. 6. Disable the BCH block. 7. Descriptor NOP to allow NANDLOCK in the previous descriptor to the thread-safe. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1381 Programming the BCH/GPMI Interfaces Descriptor 1: Disable BCH engine and issue NAND read set-up command and address (CLE/ALE). NEXT CMD ADDR CMD <= 1+5 3 1 0 0 1 0 1 DMA_READ BUFFER ADDR HW_GPMI_CTRL0 <= write 8_bit enabled 2 HW_GPMI_COMPARE <= NAND_CLE 1 null HW_GPMI_ECCCTRL <= 1+5 5 Byte ADDR null ---- disable 1 Byte NAND CMD ---- Descriptor 2: NAND read execute command (CLE). NEXT CMD ADDR CMD <= 1 1 1 0 0 1 0 1 DMA_READ BUFFER ADDR HW_GPMI_CTRL0 <= write 8_bit disabled 2 NAND_CLE 0 1 Byte NAND CMD 1 Descriptor 3: Wait for NAND ready. NEXT CMD ADDR CMD <= 0 1 1 0 1 0 0 1 NO_DMA_XFER BUFFER ADDR HW_GPMI_CTRL0 <= wait_for_ready 8_bit disabled 2 NAND_DATA 0 0 Descriptor 4: PSENSE compare for time-out. NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 0 0 1 DMA_SENSE DMA Error Descriptor Chain Descriptor 5: Enable BCH engine and read NAND data. NEXT CMD ADDR CMD <= 0 6 1 0 0 1 0 1 NO_DMA_XFER BUFFER ADDR HW_GPMI_CTRL0 <= read 8_bit disabled 2 NAND_DATA 0 HW_GPMI_COMPARE <= null HW_GPMI_ECCCTRL <= 4096+218 null decode_8_bit HW_GPMI_ECCCOUNT<= enable 0x1FF 8*512 Byte Data Payload Buffer 4096+218 (flash page size) HW_GPMI_PAYLOAD HW_GPMI_AUXILIARY 412 Byte Auxiliary Payload Buffer Descriptor 6: Disable BCH engine (wait for ready is a NOP here). NEXT CMD ADDR CMD <= 0 3 1 0 1 1 0 1 NO_DMA_XFER BUFFER ADDR HW_GPMI_CTRL0 <= wait_for_ready HW_GPMI_COMPARE <= 8_bit _ disabled 0 NAND_DATA 0 null HW_GPMI_ECCCTRL <= 0 null ---- disable ---- Descriptor 7: NOP to ensure NANDLOCK in previous descriptor . NEXT CMD ADDR CMD <= 0 0 0 BUFFER ADDR 0 0 0 0 0 NO_DMA_XFER Figure 16-10. BCH Decode DMA Descriptor Chain i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1382 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 16.4.2.1 DMA Structure Code Example The following sample code illustrates the coding for one read transaction, consisting of a seven DMA command structure chain for reading all 4096 bytes of payload data (eight 512-byte blocks) and 65 bytes of metadata with the associative parity bytes (8 * (18) + 9) from a 4K NAND page sitting on GPMI CS2. //---------------------------------------------------------------------------// generic DMA/GPMI/ECC descriptor struct, order sensitive! //---------------------------------------------------------------------------typedef struct { // DMA related fields unsigned int dma_nxtcmdar; unsigned int dma_cmd; unsigned int dma_bar; // GPMI related fields unsigned int gpmi_ctrl0; unsigned int gpmi_compare; unsigned int gpmi_eccctrl; unsigned int gpmi_ecccount; unsigned int gpmi_data_ptr; unsigned int gpmi_aux_ptr; } GENERIC_DESCRIPTOR; //---------------------------------------------------------------------------// allocate 7 descriptors for doing a NAND ECC Read //---------------------------------------------------------------------------GENERIC_DESCRIPTOR read[7]; //---------------------------------------------------------------------------// DMA descriptor pointer to handle error conditions from psense checks //---------------------------------------------------------------------------unsigned int * dma_error_handler; //---------------------------------------------------------------------------// 7 byte NAND command and address buffer // any alignment is ok, it is read by the GPMI DMA // byte 0 is read setup command // bytes 1-5 is the NAND address // byte 6 is read execute command //---------------------------------------------------------------------------unsigned char nand_cmd_addr_buffer[7]; //---------------------------------------------------------------------------// 4096 byte payload buffer used for reads or writes // needs to be word aligned //---------------------------------------------------------------------------unsigned int read_payload_buffer[(4096/4)]; //---------------------------------------------------------------------------// 412 byte auxiliary buffer used for reads // needs to be word aligned //---------------------------------------------------------------------------unsigned int read_aux_buffer[(412/4)]; //---------------------------------------------------------------------------// Descriptor 1: issue NAND read setup command (CLE/ALE) //---------------------------------------------------------------------------read[0].dma_nxtcmdar = &read[1]; // point to the next descriptor read[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1 + 5) | // 1 byte command, 5 byte address BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to the GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish // before continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels from // taking over BF_APBH_CHn_CMD_IRQONCMPLT (0) | i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1383 Programming the BCH/GPMI Interfaces BF_APBH_CHn_CMD_CHAIN (1) | BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // follow chain to next command // read data from DMA, write to NAND read[0].dma_bar = &nand_cmd_addr_buffer; // byte 0 read setup, bytes 1 - 5 NAND address // 3 words sent to the GPMI read[0].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, ENABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_CLE) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (1) | // send command and address BF_GPMI_CTRL0_XFER_COUNT (1 + 5); // 1 byte command, 5 byte address read[0].gpmi_compare = NULL; // field not used but necessary to set eccctrl read[0].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block //---------------------------------------------------------------------------// Descriptor 2: issue NAND read execute command (CLE) //---------------------------------------------------------------------------read[1].dma_nxtcmdar = &read[2]; // point to the next descriptor read[1].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (1) | // 1 byte read command BF_APBH_CHn_CMD_CMDWORDS (1) | // send 1 word to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before // continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels from // taking over BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, DMA_READ); // read data from DMA, write to NAND read[1].dma_bar = &nand_cmd_addr_buffer[6]; // point to byte 6, read execute command // 1 word sent to the GPMI read[1].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WRITE) | // write to the NAND BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, DISABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_CLE) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (1); // 1 byte command //---------------------------------------------------------------------------// Descriptor 3: wait for ready (DATA) //---------------------------------------------------------------------------read[2].dma_nxtcmdar = &read[3]; // point to the next descriptor read[2].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (1) | // send 1 word to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before // continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(1) | // wait for nand to be ready BF_APBH_CHn_CMD_NANDLOCK (0) | // relinquish nand lock BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer read[2].dma_bar = NULL; // field not used // 1 word sent to the GPMI read[2].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, WAIT_FOR_READY) | // wait for NAND ready BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, DISABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1384 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (0); //---------------------------------------------------------------------------// Descriptor 4: psense compare (time out check) //---------------------------------------------------------------------------read[3].dma_nxtcmdar = &read[4]; // point to the next descriptor read[3].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (0) | // no words sent to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | // do not wait to continue BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, DMA_SENSE); // perform a sense check read[3].dma_bar = dma_error_handler; // if sense check fails, branch to error handler //---------------------------------------------------------------------------// Descriptor 5: read 4K page plus 65 byte meta-data Nand data // and send it to ECC block (DATA) //---------------------------------------------------------------------------read[4].dma_nxtcmdar = &read[5]; // point to the next descriptor read[4].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (6) | // send 6 words to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before // continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (1) | // prevent other DMA channels from taking over BF_APBH_CHn_CMD_IRQONCMPLT (0) | // ECC block generates BCH interrupt // on completion BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no DMA transfer, // ECC block handles transfer read[4].dma_bar = NULL; // field not used // 6 words sent to the GPMI read[4].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ) | // read from the NAND BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, DISABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (4096+218); // eight 512 byte data blocks // metadata, and parity read[4].gpmi_compare = NULL; // field not used but necessary to set eccctrl // GPMI ECCCTRL PIO This launches the 4K byte transfer through BCH's // bus master. Setting the ECC_ENABLE bit redirects the data flow // within the GPMI so that read data flows to the BCH engine instead // of flowing to the GPMI's DMA channel. read[4].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ECC_CMD, DECODE_8_BIT) | // specify t = 8 mode BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, ENABLE) | // enable ECC module BF_GPMI_ECCCTRL_BUFFER_MASK (0X1FF); // read all 8 data blocks and 1 aux block read[4].gpmi_ecccount = BF_GPMI_ECCCOUNT_COUNT(4096+218); // specify number of bytes // read from NAND read[4].gpmi_data_ptr = &read_payload_buffer; // pointer for the 4K byte // data area read[4].gpmi_aux_ptr = &read_aux_buffer; // pointer for the 65 byte aux area + // parity and syndrome i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1385 Programming the BCH/GPMI Interfaces bytes for both // data and aux blocks. //---------------------------------------------------------------------------// Descriptor 6: disable ECC block //---------------------------------------------------------------------------read[5].dma_nxtcmdar = &read[6]; // point to the next descriptor read[5].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (3) | // send 3 words to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (1) | // wait for command to finish before // continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(1) | // wait for nand to be ready BF_APBH_CHn_CMD_NANDLOCK (1) | // need nand lock to be // thread safe while turn-off BCH BF_APBH_CHn_CMD_IRQONCMPLT (0) | BF_APBH_CHn_CMD_CHAIN (1) | // follow chain to next command BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer read[5].dma_bar = NULL; // field not used // 3 words sent to the GPMI read[5].gpmi_ctrl0 = BV_FLD(GPMI_CTRL0, COMMAND_MODE, READ) | BV_FLD(GPMI_CTRL0, WORD_LENGTH, 8_BIT) | BV_FLD(GPMI_CTRL0, LOCK_CS, DISABLED) | BF_GPMI_CTRL0_CS (2) | // must correspond to NAND CS used BV_FLD(GPMI_CTRL0, ADDRESS, NAND_DATA) | BF_GPMI_CTRL0_ADDRESS_INCREMENT (0) | BF_GPMI_CTRL0_XFER_COUNT (0); read[5].gpmi_compare = NULL; // field not used but necessary to set eccctrl read[5].gpmi_eccctrl = BV_FLD(GPMI_ECCCTRL, ENABLE_ECC, DISABLE); // disable the ECC block //---------------------------------------------------------------------------// Descriptor 7: deassert nand lock //---------------------------------------------------------------------------read[6].dma_nxtcmdar = NULL; // not used since this is last descriptor read[6].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT (0) | // no dma transfer BF_APBH_CHn_CMD_CMDWORDS (0) | // no words sent to GPMI BF_APBH_CHn_CMD_WAIT4ENDCMD (0) | // wait for command to finish before // continuing BF_APBH_CHn_CMD_SEMAPHORE (0) | BF_APBH_CHn_CMD_NANDWAIT4READY(0) | BF_APBH_CHn_CMD_NANDLOCK (0) | // relinquish nand lock BF_APBH_CHn_CMD_IRQONCMPLT (0) | // BCH engine generates interrupt BF_APBH_CHn_CMD_CHAIN (0) | // terminate DMA chain processing BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER); // no dma transfer read[6].dma_bar = NULL; // field not used 16.4.2.2 Using the Decoder As illustrated in Figure 16-10 and the sample code in DMA Structure Code Example : * DMA descriptor 1 prepares the NAND for data read by using the GPMI to issue a NAND read setup command byte under CLE, then sends a 5-byte address under ALE. The BCH engine is not used for these commands. * DMA descriptor 2 issues a one-byte read execute command to the NAND device that triggers its read access. The NAND then goes not ready. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1386 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) * DMA descriptor 3 performs a wait for ready operation allowing the DMA chain to remain dormant until the NAND device completes its read access time. * DMA descriptor 5 handles the reading and error correction of the NAND data. This command's PIOs activate the BCH engine to write the read NAND data to system memory and to process it for any errors that need to be corrected. This DMA descriptor contains two PIO values that are system memory addresses pointing to the PAYLOAD data area and to the AUXILIARY data area. These addresses are used by the BCH engine's AHB master to move data into system memory and to correct it. While this example is reading an entire 4K page--payload plus metadata--it is equally possible to read just one 512-byte payload block or just the uniquely protected metadata block in a single 7 DMA structure transfer. * DMA descriptor 6 disables the BCH engine with the NANDLOCK asserted. This is necessary to ensure that the GPMI resource is not arbitrated to another DMA channel when multiple DMA channels are active concurrently. * DMA descriptor 7 deasserts the NANDLOCK to free up the GPMI resource to another channel. As the BCH block receives data from the GPMI: * The decoder transforms the read NAND data block into a BCH code word and computes the codeword syndrome. * If no errors are present, then the BCH block can immediately report back to firmware. This report is passed as the BCH_CTRL_COMPLETE_IRQ interrupt status bit and the associated status registers in BCH_STATUS0/1 registers. * If an error is present, then the BCH block corrects the necessary data block or parity block bytes, if possible (not all errors are correctable). As the BCH decoder reads the data and parity blocks, it records a special condition, i.e., that all of the bits of a payload data block or metadata block are one, including any associated parity bytes. The all-ones case for both parity and data indicates an erased block in the NAND device. The BCH_STATUS0 register contains a 4-bit field that indicates the final status of the auxiliary block. A value of 0x0 indicates no errors found for a block. * A value of 1 to 20 inclusive indicates that many correctable errors were found and fixed. * A value of 0xFE indicates uncorrectable errors detected on the block. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1387 Programming the BCH/GPMI Interfaces * A value of 0xFF indicates that the block was in the special ALL ONES state and is therefore considered to be an ERASED block. * All other values are disallowed by the hardware design. Recall that up to four NAND devices can have DMA chains in-flight at once, i.e. they can all be contending for access to the GPMI data bus. It is impossible to predict which NAND device will enter the BCH engine with a transfer first, because each chain includes a wait4ready command structure. As a result, firmware should look at the BCH_STATUS0_COMPLETED_CE bit field to determine which block is being reported in the status register. There is also a 16-bit HANDLE field in the GPMI_ECCCTRL register that is passed down the pipeline with each transaction. This handle field can be used to speed firmware's detection of which transaction is being reported. These examples of reading and writing have focused on full page transfers of 4K page NAND devices. Other device configurations can be specified by changing the ECCOUNT field in the GPMI registers and reprogramming the BCH's FLASHnLAYOUTm registers. The BCH and GPMI blocks are designed to be very efficient at reading single 512-byte pages in one transaction. With no errors, the transaction takes less than 20 HCLKs longer than the time to read the raw data from the NAND. To summarize, the APBH DMA command chain for a BCH decode operation is shown in Figure 16-10. Seven DMA command structures must be present for each NAND read transaction decoded by the BCH. The seven DMA command structures for multiple NAND read transaction blocks can be chained together to make larger units of work for the BCH, and each will produce an appropriate error report in the BCH PIO space. Multiple NAND devices can have such multiple chains scheduled. The results can come back out of order with respect to the multiple chains. 16.4.3 Interrupts There are two interrupt sources used in processing BCH protected NAND read and write transfers. Since all BCH operations are initiated by GPMI DMA command structures, the DMA completion interrupt for the GPMI is an important ISR. Both of the flow charts of Figure 16-6 and Figure 16-9 show the GPMI DMA complete ISR skeleton. In both reads and writes, the GPMI DMA completion interrupt is used to schedule work INTO the error correction pipeline. As the front end processing completes, the DMA interrupt is i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1388 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) generated and additional work, such as DMA chains, are passed to the GPMI DMA to keep it fed. For write operations, this is the only interrupt that is generated for processing the NAND write transfer. For reads, however, two interrupts are needed. Every read is started by a GPMI DMA command chain and the front end queue is fed as described above. The back end of the read pipeline is drained by monitoring the BCH completion interrupt found int HW_BCH_CTRL_COMPLETE_IRQ. An BCH transaction consists of reading or writing all of the blocks requested in the HW_GPMI_ECCCTRL_BUFFER_MASK bit field. As every read transaction completes, it posts the status of all of the blocks to the HW_BCH_STATUS0 and HW_BCH_STATUS1 registers and sets the completion interrupt. The five stages of the BCH read pipeline completes, one in the GPMI and four in the BCH, are independently stalled as they complete and try to deliver to the next stage in the data flow. Several of these stages can be skipped if no-errors are found or once an uncorrectable error is found in a block. In any case, the final stage will stall if the status register is busy waiting for the CPU to take status register results. The hardware monitors the state of the HW_BCH_CTRL_COMPLETE_IRQ bit. If it is still set when the last pipeline stage is ready to post data, then the stage will stall. It follows that the next previous stage will stall when it is ready to hand off work to the final stage, and so on up the pipeline. CAUTION It is important that firmware read the STATUS0/1 results and save them before clearing the interrupt request bit. Otherwise, a transaction and its results could be completely lost. 16.5 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. 16.6 BCH Memory Map/Register Definition BCH Hardware Register Format Summary i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1389 BCH Memory Map/Register Definition BCH memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 0 Hardware BCH ECC Accelerator Control Register (BCH_CTRL) 32 R/W 10 Hardware ECC Accelerator Status Register 0 (BCH_STATUS0) 32 R 0000_0010h 16.6.2/1393 20 Hardware ECC Accelerator Mode Register (BCH_MODE) 32 R/W 0000_0000h 16.6.3/1394 30 Hardware BCH ECC Loopback Encode Buffer Register (BCH_ENCODEPTR) 32 R/W 0000_0000h 16.6.4/1395 40 Hardware BCH ECC Loopback Data Buffer Register (BCH_DATAPTR) 32 R/W 0000_0000h 16.6.5/1395 50 Hardware BCH ECC Loopback Metadata Buffer Register (BCH_METAPTR) 32 R/W 0000_0000h 16.6.6/1396 70 Hardware ECC Accelerator Layout Select Register (BCH_LAYOUTSELECT) 32 R/W E4E4_E4E4h 16.6.7/1396 80 Hardware BCH ECC Flash 0 Layout 0 Register (BCH_FLASH0LAYOUT0) 32 R/W 070A_8200h 16.6.8/1397 90 Hardware BCH ECC Flash 0 Layout 1 Register (BCH_FLASH0LAYOUT1) 32 R/W 10DA_8200h 16.6.9/1399 A0 Hardware BCH ECC Flash 1 Layout 0 Register (BCH_FLASH1LAYOUT0) 32 R/W 070A_8200h 16.6.10/ 1399 B0 Hardware BCH ECC Flash 1 Layout 1 Register (BCH_FLASH1LAYOUT1) 32 R/W 10DA_8200h 16.6.11/ 1401 C0 Hardware BCH ECC Flash 2 Layout 0 Register (BCH_FLASH2LAYOUT0) 32 R/W 070A_8200h 16.6.12/ 1401 D0 Hardware BCH ECC Flash 2 Layout 1 Register (BCH_FLASH2LAYOUT1) 32 R/W 10DA_8200h 16.6.13/ 1403 E0 Hardware BCH ECC Flash 3 Layout 0 Register (BCH_FLASH3LAYOUT0) 32 R/W 070A_8200h 16.6.14/ 1403 F0 Hardware BCH ECC Flash 3 Layout 1 Register (BCH_FLASH3LAYOUT1) 32 R/W 10DA_8200h 16.6.15/ 1405 100 Hardware BCH ECC Debug Register0 (BCH_DEBUG0) 32 R/W 0000_0000h 16.6.16/ 1405 110 KES Debug Read Register (BCH_DBGKESREAD) 32 R 0000_0000h 16.6.17/ 1407 120 Chien Search Debug Read Register (BCH_DBGCSFEREAD) 32 R 0000_0000h 16.6.18/ 1408 130 Syndrome Generator Debug Read Register (BCH_DBGSYNDGENREAD) 32 R 0000_0000h 16.6.19/ 1408 140 Bus Master and ECC Controller Debug Read Register (BCH_DBGAHBMREAD) 32 R 0000_0000h 16.6.20/ 1409 150 Block Name Register (BCH_BLOCKNAME) 32 R 2048_4342h 16.6.21/ 1409 160 BCH Version Register (BCH_VERSION) 32 R 0100_0000h 16.6.22/ 1410 E000_0000h 16.6.1/1391 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1390 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 16.6.1 Hardware BCH ECC Accelerator Control Register (BCH_CTRL) The BCH CTRL provides overall control of the hardware ECC accelerator Address: 0h base + 0h offset = 0h 31 30 29 28 27 26 25 24 23 RSVD5 19 18 17 16 M2M_ LAYOUT M2M_ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEBUG_STALL_IRQ 0 0 RSVD2 0 0 RSVD1 COMPLETE_IRQ_EN DEBUG_STALL_IRQ_EN RSVD3 R COMPLETE_IRQ M2M_ENCODE 1 RSVD0 1 BM_ERROR_IRQ RSVD4 CLKGATE Bit 20 1 W Reset 21 SFTRST R 22 DEBUGSYNDROME Bit W Reset 0 0 0 0 0 0 0 0 0 0 0 0 BCH_CTRL field descriptions Field 31 SFTRST Description Set this bit to zero to enable normal BCH operation. Set this bit to one (default) to disable clocking with the BCH and hold it in its reset (lowest power) state. This bit can be turned on and then off to Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1391 BCH Memory Map/Register Definition BCH_CTRL field descriptions (continued) Field Description reset the BCH block to its default state. This bit resets all state machines except for the AHB master state machine 0x0 0x1 30 CLKGATE 29-23 RSVD5 RUN -- Allow BCH to operate normally. RESET -- Hold BCH in reset. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. 0x0 0x1 RUN -- Allow BCH to operate normally. NO_CLKS -- Do not clock BCH gates in order to minimize power consumption. Reserved, always set this bit to zero. 22 (For debug purposes only). Enable write of computed syndromes to memory on BCH decode DEBUGSYNDROME operations. Computed syndromes will be written to the auxiliary buffer after the status block. Syndromes will be written as padded 16-bit values. 21-20 RSVD4 Reserved, always set these bits to zero. 19-18 M2M_LAYOUT Selects the flash page format for memory-to-memory operations. 17 M2M_ENCODE Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations. 16 M2M_ENABLE NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION. The BCH module must be inactive (not processing data from the GPMI) when this bit is set. The M2M_ENCODE and M2M_LAYOUT bits as well as the ENCODEPTR, DATAPTR, and METAPTR registers are used for memory-to-memory operations and must be correctly programmed before writing this bit. 15-11 RSVD3 10 DEBUG_STALL_ IRQ_EN 9 RSVD2 8 COMPLETE_IRQ_ EN 7-4 RSVD1 3 BM_ERROR_IRQ Reserved, always set these bits to zero. 1 = interrupt on debug stall mode is enabled. The irq is raised on every block Reserved, always set these bits to zero. 1 = interrupt on completion of correction is enabled. Reserved, always set these bits to zero. AHB Bus interface Error Interrupt Status. Write a one to the SCT clear address to clear the interrupt status bit. 2 DEBUG STALL Interrupt Status. Write a one to the SCT clear address to clear the interrupt status bit. DEBUG_STALL_IRQ 1 RSVD0 0 COMPLETE_IRQ Reserved, always set these bits to zero. This bit indicates the state of the external interrupt line. Write a one to the SCT clear address to clear the interrupt status bit. NOTE: subsequent ECC completions will be held off as long as this bit is set. Be sure to read the data from BCH_STATUS0,1 before clearing this interrupt bit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1392 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 16.6.2 Hardware ECC Accelerator Status Register 0 (BCH_STATUS0) The BCH STAT register provides visibility into the run-time status of the BCH and status information when processing is complete. Address: 0h base + 10h offset = 10h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 HANDLE R 18 17 16 COMPLETED_CE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNCORRECTABLE Bit 0 CORRECTED Reset ALLONES W 1 0 0 STATUS_BLK0 R RSVD1 RSVD0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1393 BCH Memory Map/Register Definition BCH_STATUS0 field descriptions Field Description 31-20 HANDLE Software supplies a 12 bit handle for this transfer as part of the GPMI DMA PIO operation that started the transaction. That handle passes down the pipeline and ends up here at the time the BCH interrupt is signaled. 19-16 This is the chip enable number corresponding to the NAND device from which this data came. COMPLETED_CE 15-8 STATUS_BLK0 Count of symbols in error during processing of first block of flash (metadata block). The number of errors reported will be in the range of 0 to the ECC correction level for block 0. ZERO -- No errors found on block. ERROR1 -- One error found on block. ERROR2 -- One errors found on block. ERROR3 -- One errors found on block. ERROR4 -- One errors found on block. UNCORRECTABLE -- Block exhibited uncorrectable errors. ERASED -- Page is erased. 0x00 0x01 0x02 0x03 0x04 0xFE 0xFF 7-5 RSVD1 Reserved, always set these bits to zero. 4 ALLONES 1 = All data bits of this transaction are ONE. 3 CORRECTED 1 = At least one correctable error encountered during last processing cycle. 2 1 = Uncorrectable error encountered during last processing cycle. UNCORRECTABLE RSVD0 Reserved, always set these bits to zero. 16.6.3 Hardware ECC Accelerator Mode Register (BCH_MODE) The BCH MODE register provides additional mode controls. Contains additional global mode controls for the BCH engine. Address: 0h base + 20h offset = 20h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSVD R 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 ERASE_THRESHOLD W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCH_MODE field descriptions Field 31-8 RSVD Description Reserved, always set these bits to zero. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1394 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) BCH_MODE field descriptions (continued) Field Description ERASE_ THRESHOLD This value indicates the maximum number of zero bits on a flash page for it to be considered erased. For SLC NAND devices, this value should be programmed to 0 (meaning that the entire page should consist of bytes of 0xFF. For MLC NAND devices, bit errors may occur on reads (even on blank pages), so this threshold can be used to tune the erased page checking algorithm. 16.6.4 Hardware BCH ECC Loopback Encode Buffer Register (BCH_ENCODEPTR) When performing memory to memory operations, indicates the address of the encode buffer. This register should be programmed before writing a 1 to the M2M_ENABLE bit in the CTRL register. For memory to memory operations, this register is used as the pointer to the encoded data, which is an output when encoding and an input while decoding. Address: 0h base + 30h offset = 30h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCH_ENCODEPTR field descriptions Field Description ADDR Address pointer to encode buffer. This is the source for decode operations and the destination for encode operations. This value must be aligned on a 4 byte boundary. 16.6.5 Hardware BCH ECC Loopback Data Buffer Register (BCH_DATAPTR) When performing memory to memory operations, indicates the address of the data buffer. For memory to memory operations, this register is used as the pointer to the data to encode or the destination buffer for decode operations. Address: 0h base + 40h offset = 40h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1395 BCH Memory Map/Register Definition BCH_DATAPTR field descriptions Field Description ADDR Address pointer to data buffer. This is the source for encode operations and the destination for decode operations. This register should be programmed before writing a 1 to the M2M_ENABLE bit in the CTRL register. This value must be aligned on a 4 byte boundary. 16.6.6 Hardware BCH ECC Loopback Metadata Buffer Register (BCH_METAPTR) When performing memory to memory operations, indicates the address of the metadata buffer. For memory to memory operations, this register is used as the pointer to the metadata to encode or the extracted metadata for decode operations. Address: 0h base + 50h offset = 50h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCH_METAPTR field descriptions Field Description ADDR Address pointer to metadata buffer. This is the source for encode metadata read operations and the destination for metadata decode operations. This register should be programmed before writing a 1 to the M2M_ENABLE bit in the CTRL register. This value must be aligned on a 4 byte boundary. 16.6.7 Hardware ECC Accelerator Layout Select Register (BCH_LAYOUTSELECT) The BCH LAYOUTSELECT register provides a mapping of chip selects to layout registers. When the BCH engine receives a request to process a data block from the GPMI interface, it will use this register to map the incoming chip select to one of the four possible flash layout registers Address: 0h base + 70h offset = 70h Bit 31 R W Reset 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CS15_ SELECT CS14_ SELECT CS13_ SELECT CS12_ SELECT CS11_ SELECT CS10_ SELECT CS9_ SELECT CS8_ SELECT 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1396 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 15 Bit R W Reset 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CS7_ SELECT CS6_ SELECT CS5_ SELECT CS4_ SELECT CS3_ SELECT CS2_ SELECT CS1_ SELECT CS0_ SELECT 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 BCH_LAYOUTSELECT field descriptions Field Description 31-30 Selects which layout is used for chip select 15. CS15_SELECT 29-28 Selects which layout is used for chip select 14. CS14_SELECT 27-26 Selects which layout is used for chip select 13. CS13_SELECT 25-24 Selects which layout is used for chip select 12. CS12_SELECT 23-22 Selects which layout is used for chip select 11. CS11_SELECT 21-20 Selects which layout is used for chip select 10. CS10_SELECT 19-18 CS9_SELECT Selects which layout is used for chip select 9. 17-16 CS8_SELECT Selects which layout is used for chip select 8. 15-14 CS7_SELECT Selects which layout is used for chip select 7. 13-12 CS6_SELECT Selects which layout is used for chip select 6. 11-10 CS5_SELECT Selects which layout is used for chip select 5. 9-8 CS4_SELECT Selects which layout is used for chip select 4. 7-6 CS3_SELECT Selects which layout is used for chip select 3. 5-4 CS2_SELECT Selects which layout is used for chip select 2. 3-2 CS1_SELECT Selects which layout is used for chip select 1. CS0_SELECT Selects which layout is used for chip select 0. 16.6.8 Hardware BCH ECC Flash 0 Layout 0 Register (BCH_FLASH0LAYOUT0) The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjunction with the FLASH0LAYOUT1 register to control the format for the devices selecting layout 0 in the LAYOUTSELECT register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1397 BCH Memory Map/Register Definition Each pair of layout registers describes one of four supported flash configurations. Software should program the LAYOUTSELECT register for each supported GPMI chip select to select from one of the four layout values. Each pair of registers contains settings that are used by the BCH block while reading/writing the flash page to control data, metadata, and flash page sizes as well as the ECC correction level. The first block written to flash can be programmed to have different ECC, metadata, and data sizes from subsequent data blocks on the device. In addition, the number of blocks stored on a page of flash is not fixed, but instead is determined by the number of bytes consumed by the initial (block 0) and subsequent data blocks. See the BCH programming reference manual for more information on setting up the flash layout registers. Address: 0h base + 80h offset = 80h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 NBLOCKS 0 0 0 0 1 21 20 19 18 17 16 15 META_SIZE 1 1 0 0 0 0 1 0 14 13 12 11 10 9 8 ECC0 1 0 1 0 0 7 6 5 4 3 2 1 0 0 0 0 0 DATA0_SIZE 0 0 0 1 0 0 0 0 0 BCH_FLASH0LAYOUT0 field descriptions Field Description 31-24 NBLOCKS Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that only the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total of 9 blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the hardware. 23-16 META_SIZE Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0 to 255 bytes for metadata -- if set to zero, no metadata will be stored. Metadata is stored before the associated data in block 0. If the DATA0_SIZE field is programmed to a zero, then metadata effectively be stored with its own parity. When both the metadata and data0 fields are programmed with non-zero values, the first block will contain both portions of data and will be covered by a single parity block. 15-12 ECC0 Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the associated data from the DATA0_SIZE field. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA DATA0_SIZE NONE -- No ECC to be performed ECC2 -- ECC 2 to be performed ECC4 -- ECC 4 to be performed ECC6 -- ECC 6 to be performed ECC8 -- ECC 8 to be performed ECC10 -- ECC 10 to be performed ECC12 -- ECC 12 to be performed ECC14 -- ECC 14 to be performed ECC16 -- ECC 16 to be performed ECC18 -- ECC 18 to be performed ECC20 -- ECC 20 to be performed Indicates the size of the data 0 block (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. If set to zero, the first block will only contain metadata. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1398 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 16.6.9 Hardware BCH ECC Flash 0 Layout 1 Register (BCH_FLASH0LAYOUT1) The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjunction with the FLASH0LAYOUT0 register to control the format for the device selecting layout 0 in the LAYOUTSELECT register. Address: 0h base + 90h offset = 90h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PAGE_SIZE 0 0 1 0 0 0 0 1 1 14 13 12 11 10 9 8 ECCN 0 1 1 0 1 0 1 0 0 7 6 5 4 3 2 1 0 0 0 0 0 DATAN_SIZE 0 0 0 1 0 0 0 0 0 BCH_FLASH0LAYOUT1 field descriptions Field Description 31-16 PAGE_SIZE Indicates the total size of the flash page (in bytes). This should be set to the page size including spare area. The page size is programmable to accomodate different flash configurations that may be available in the future. 15-12 ECCN Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n). Subsequent blocks only contain data (no metadata). 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA DATAN_SIZE NONE -- No ECC to be performed ECC2 -- ECC 2 to be performed ECC4 -- ECC 4 to be performed ECC6 -- ECC 6 to be performed ECC8 -- ECC 8 to be performed ECC10 -- ECC 10 to be performed ECC12 -- ECC 12 to be performed ECC14 -- ECC 14 to be performed ECC16 -- ECC 16 to be performed ECC18 -- ECC 18 to be performed ECC20 -- ECC 20 to be performed Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. The size of subsequent data blocks does not have to match the data size for block 0, which is important when metadata is stored separately or for balancing the amount of data stored in each block. 16.6.10 Hardware BCH ECC Flash 1 Layout 0 Register (BCH_FLASH1LAYOUT0) The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjunction with the FLASH1LAYOUT1 register to control the format for the devices selecting layout 1 in the LAYOUTSELECT register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1399 BCH Memory Map/Register Definition Each pair of layout registers describes one of four supported flash configurations. Software should program the LAYOUTSELECT register for each supported GPMI chip select to select from one of the four layout values. Each pair of registers contains settings that are used by the BCH block while reading/writing the flash page to control data, metadata, and flash page sizes as well as the ECC correction level. The first block written to flash can be programmed to have different ECC, metadata, and data sizes from subsequent data blocks on the device. In addition, the number of blocks stored on a page of flash is not fixed, but instead is determined by the number of bytes consumed by the initial (block 0) and subsequent data blocks. See the BCH programming reference manual for more information on setting up the flash layout registers. Address: 0h base + A0h offset = A0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 NBLOCKS 0 0 0 0 1 21 20 19 18 17 16 15 META_SIZE 1 1 0 0 0 0 1 0 14 13 12 11 10 9 8 ECC0 1 0 1 0 0 7 6 5 4 3 2 1 0 0 0 0 0 DATA0_SIZE 0 0 0 1 0 0 0 0 0 BCH_FLASH1LAYOUT0 field descriptions Field Description 31-24 NBLOCKS Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that only the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total of 9 blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the hardware. 23-16 META_SIZE Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0 to 255 bytes for metadata -- if set to zero, no metadata will be stored. Metadata is stored before the associated data in block 0. If the DATA0_SIZE field is programmed to a zero, then metadata effectively be stored with its own parity. When both the metadata and data0 fields are programmed with non-zero values, the first block will contain both portions of data and will be covered by a single parity block. 15-12 ECC0 Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the associated data from the DATA0_SIZE field. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA DATA0_SIZE NONE -- No ECC to be performed ECC2 -- ECC 2 to be performed ECC4 -- ECC 4 to be performed ECC6 -- ECC 6 to be performed ECC8 -- ECC 8 to be performed ECC10 -- ECC 10 to be performed ECC12 -- ECC 12 to be performed ECC14 -- ECC 14 to be performed ECC16 -- ECC 16 to be performed ECC18 -- ECC 18 to be performed ECC20 -- ECC 20 to be performed Indicates the size of the data 0 block (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. If set to zero, the first block will only contain metadata. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1400 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 16.6.11 Hardware BCH ECC Flash 1 Layout 1 Register (BCH_FLASH1LAYOUT1) The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjunction with the FLASH1LAYOUT0 register to control the format for the device selecting layout 1 in the LAYOUTSELECT register. Address: 0h base + B0h offset = B0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PAGE_SIZE 0 0 1 0 0 0 0 1 1 14 13 12 11 10 9 8 ECCN 0 1 1 0 1 0 1 0 0 7 6 5 4 3 2 1 0 0 0 0 0 DATAN_SIZE 0 0 0 1 0 0 0 0 0 BCH_FLASH1LAYOUT1 field descriptions Field Description 31-16 PAGE_SIZE Indicates the total size of the flash page (in bytes). This should be set to the page size including spare area. The page size is programmable to accomodate different flash configurations that may be available in the future. 15-12 ECCN Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n). Subsequent blocks only contain data (no metadata). 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA DATAN_SIZE NONE -- No ECC to be performed ECC2 -- ECC 2 to be performed ECC4 -- ECC 4 to be performed ECC6 -- ECC 6 to be performed ECC8 -- ECC 8 to be performed ECC10 -- ECC 10 to be performed ECC12 -- ECC 12 to be performed ECC14 -- ECC 14 to be performed ECC16 -- ECC 16 to be performed ECC18 -- ECC 18 to be performed ECC20 -- ECC 20 to be performed Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. The size of subsequent data blocks does not have to match the data size for block 0, which is important when metadata is stored separately or for balancing the amount of data stored in each block. 16.6.12 Hardware BCH ECC Flash 2 Layout 0 Register (BCH_FLASH2LAYOUT0) The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjunction with the FLASH2LAYOUT1 register to control the format for the devices selecting layout 2 in the LAYOUTSELECT register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1401 BCH Memory Map/Register Definition Each pair of layout registers describes one of four supported flash configurations. Software should program the LAYOUTSELECT register for each supported GPMI chip select to select from one of the four layout values. Each pair of registers contains settings that are used by the BCH block while reading/writing the flash page to control data, metadata, and flash page sizes as well as the ECC correction level. The first block written to flash can be programmed to have different ECC, metadata, and data sizes from subsequent data blocks on the device. In addition, the number of blocks stored on a page of flash is not fixed, but instead is determined by the number of bytes consumed by the initial (block 0) and subsequent data blocks. See the BCH programming reference manual for more information on setting up the flash layout registers. Address: 0h base + C0h offset = C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 NBLOCKS 0 0 0 0 1 21 20 19 18 17 16 15 META_SIZE 1 1 0 0 0 0 1 0 14 13 12 11 10 9 8 ECC0 1 0 1 0 0 7 6 5 4 3 2 1 0 0 0 0 0 DATA0_SIZE 0 0 0 1 0 0 0 0 0 BCH_FLASH2LAYOUT0 field descriptions Field Description 31-24 NBLOCKS Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that only the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total of 9 blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the hardware. 23-16 META_SIZE Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0 to 255 bytes for metadata -- if set to zero, no metadata will be stored. Metadata is stored before the associated data in block 0. If the DATA0_SIZE field is programmed to a zero, then metadata effectively be stored with its own parity. When both the metadata and data0 fields are programmed with non-zero values, the first block will contain both portions of data and will be covered by a single parity block. 15-12 ECC0 Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the associated data from the DATA0_SIZE field. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA DATA0_SIZE NONE -- No ECC to be performed ECC2 -- ECC 2 to be performed ECC4 -- ECC 4 to be performed ECC6 -- ECC 6 to be performed ECC8 -- ECC 8 to be performed ECC10 -- ECC 10 to be performed ECC12 -- ECC 12 to be performed ECC14 -- ECC 14 to be performed ECC16 -- ECC 16 to be performed ECC18 -- ECC 18 to be performed ECC20 -- ECC 20 to be performed Indicates the size of the data 0 block (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. If set to zero, the first block will only contain metadata. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1402 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 16.6.13 Hardware BCH ECC Flash 2 Layout 1 Register (BCH_FLASH2LAYOUT1) The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjunction with the FLASH2LAYOUT0 register to control the format for the device selecting layout 2 in the LAYOUTSELECT register. Address: 0h base + D0h offset = D0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PAGE_SIZE 0 0 1 0 0 0 0 1 1 14 13 12 11 10 9 8 ECCN 0 1 1 0 1 0 1 0 0 7 6 5 4 3 2 1 0 0 0 0 0 DATAN_SIZE 0 0 0 1 0 0 0 0 0 BCH_FLASH2LAYOUT1 field descriptions Field Description 31-16 PAGE_SIZE Indicates the total size of the flash page (in bytes). This should be set to the page size including spare area. The page size is programmable to accomodate different flash configurations that may be available in the future. 15-12 ECCN Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n). Subsequent blocks only contain data (no metadata). 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA DATAN_SIZE NONE -- No ECC to be performed ECC2 -- ECC 2 to be performed ECC4 -- ECC 4 to be performed ECC6 -- ECC 6 to be performed ECC8 -- ECC 8 to be performed ECC10 -- ECC 10 to be performed ECC12 -- ECC 12 to be performed ECC14 -- ECC 14 to be performed ECC16 -- ECC 16 to be performed ECC18 -- ECC 18 to be performed ECC20 -- ECC 20 to be performed Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. The size of subsequent data blocks does not have to match the data size for block 0, which is important when metadata is stored separately or for balancing the amount of data stored in each block. 16.6.14 Hardware BCH ECC Flash 3 Layout 0 Register (BCH_FLASH3LAYOUT0) The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjunction with the FLASH3LAYOUT1 register to control the format for the devices selecting layout 3 in the LAYOUTSELECT register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1403 BCH Memory Map/Register Definition Each pair of layout registers describes one of four supported flash configurations. Software should program the LAYOUTSELECT register for each supported GPMI chip select to select from one of the four layout values. Each pair of registers contains settings that are used by the BCH block while reading/writing the flash page to control data, metadata, and flash page sizes as well as the ECC correction level. The first block written to flash can be programmed to have different ECC, metadata, and data sizes from subsequent data blocks on the device. In addition, the number of blocks stored on a page of flash is not fixed, but instead is determined by the number of bytes consumed by the initial (block 0) and subsequent data blocks. See the BCH programming reference manual for more information on setting up the flash layout registers. Address: 0h base + E0h offset = E0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 NBLOCKS 0 0 0 0 1 21 20 19 18 17 16 15 META_SIZE 1 1 0 0 0 0 1 0 14 13 12 11 10 9 8 ECC0 1 0 1 0 0 7 6 5 4 3 2 1 0 0 0 0 0 DATA0_SIZE 0 0 0 1 0 0 0 0 0 BCH_FLASH3LAYOUT0 field descriptions Field Description 31-24 NBLOCKS Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that only the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total of 9 blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the hardware. 23-16 META_SIZE Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0 to 255 bytes for metadata -- if set to zero, no metadata will be stored. Metadata is stored before the associated data in block 0. If the DATA0_SIZE field is programmed to a zero, then metadata effectively be stored with its own parity. When both the metadata and data0 fields are programmed with non-zero values, the first block will contain both portions of data and will be covered by a single parity block. 15-12 ECC0 Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the associated data from the DATA0_SIZE field. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA DATA0_SIZE NONE -- No ECC to be performed ECC2 -- ECC 2 to be performed ECC4 -- ECC 4 to be performed ECC6 -- ECC 6 to be performed ECC8 -- ECC 8 to be performed ECC10 -- ECC 10 to be performed ECC12 -- ECC 12 to be performed ECC14 -- ECC 14 to be performed ECC16 -- ECC 16 to be performed ECC18 -- ECC 18 to be performed ECC20 -- ECC 20 to be performed Indicates the size of the data 0 block (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. If set to zero, the first block will only contain metadata. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1404 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) 16.6.15 Hardware BCH ECC Flash 3 Layout 1 Register (BCH_FLASH3LAYOUT1) The flash format register contains a description of the logical layout of data on the flash device. This register is used in conjucction with the FLASH3LAYOUT0 register to control the format for the device selecting layout 3 in the LAYOUTSELECT register. Address: 0h base + F0h offset = F0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PAGE_SIZE 0 0 1 0 0 0 0 1 1 14 13 12 11 10 9 8 ECCN 0 1 1 0 1 0 1 0 0 7 6 5 4 3 2 1 0 0 0 0 0 DATAN_SIZE 0 0 0 1 0 0 0 0 0 BCH_FLASH3LAYOUT1 field descriptions Field Description 31-16 PAGE_SIZE Indicates the total size of the flash page (in bytes). This should be set to the page size including spare area. The page size is programmable to accomodate different flash configurations that may be available in the future. 15-12 ECCN Indicates the ECC level for the subsequent blocks on the flash page (blocks 1-n). Subsequent blocks only contain data (no metadata). 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA DATAN_SIZE NONE -- No ECC to be performed ECC2 -- ECC 2 to be performed ECC4 -- ECC 4 to be performed ECC6 -- ECC 6 to be performed ECC8 -- ECC 8 to be performed ECC10 -- ECC 10 to be performed ECC12 -- ECC 12 to be performed ECC14 -- ECC 14 to be performed ECC16 -- ECC 16 to be performed ECC18 -- ECC 18 to be performed ECC20 -- ECC 20 to be performed Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page. The data size MUST be a multiple of four bytes. The size of subsequent data blocks does not have to match the data size for block 0, which is important when metadata is stored separately or for balancing the amount of data stored in each block. 16.6.16 Hardware BCH ECC Debug Register0 (BCH_DEBUG0) The hardware BCH accelerator internal state machines and signals can be seen in the ECC debug register. The BCH_DEBUG0 register provides access to various internal state information which might prove useful during hardware debug and validation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1405 BCH Memory Map/Register Definition Address: 0h base + 100h offset = 100h Bit 31 30 29 28 27 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BM_KES_TEST_BYPASS 16 ROM_BIST_COMPLETE 17 KES_DEBUG_STALL 18 ROM_BIST_ENABLE 19 KES_DEBUG_STEP 20 KES_STANDALONE Reset 21 KES_DEBUG_KICK W 22 KES_DEBUG_MODE4K R 23 KES_DEBUG_PAYLOAD_FLAG Bit 24 0 0 0 0 0 0 0 0 0 W Reset 25 KES_DEBUG_SHIFT_SYND R 26 KES_DEBUG_SYNDROME_SYMBOL RSVD0 DEBUG_REG_SELECT 0 0 0 0 0 0 0 0 BCH_DEBUG0 field descriptions Field 31-27 RSVD1 Description Reserved, always set these bits to zero. 26 ROM_BIST_ ENABLE Software may initiate a ROM BIST operation by toggling this bit from a zero to a one. When the operation is complete, the ROM_BIST_COMPLETE bit will be set and the ROM's CRC value will be available in the DEBUG data register. 25 ROM_BIST_ COMPLETE This bit will be set after a BIST operation completes, at which time the ROM CRC is available in the DBGKESREAD register. The CRC value will be cleared after the BIST_ENABLE bit is cleared. 24-16 KES_DEBUG_ SYNDROME_ SYMBOL The 9 bit value in this bit field will be shifted into the syndrome register array at the input of the KES engine whenever BCH_DEBUG0_KES_DEBUG_SHIFT_SYND is toggled. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1406 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) BCH_DEBUG0 field descriptions (continued) Field Description 0x0 0x1 15 KES_DEBUG_ SHIFT_SYND NORMAL -- Bus master address generator for synd_gen writes operates normally. TEST_MODE -- Bus master address generator always addresses last four bytes in Auxilliary block. Toggling this bit causes the value in BCH_DEBUG0_KES_SYNDROME_SYMBOL to be shift into the syndrome register array at the input to the KES engine. After shifting in 16 symbols, one can kick off both KES and CF cycles by toggling BCH_DEBUG0_KES_DEBUG_KICK. Be sure to set KES_BCH_DEBUG0_KES_STANDALONE mode to 1 before kicking. 14 When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES_DEBUG_ KES engine as the input payload flag. PAYLOAD_FLAG 0x1 DATA -- Payload is set for 512 byte data block. 0x1 AUX -- Payload is set for 65 or 19 byte auxilliary block. 13 KES_DEBUG_ MODE4K When running the stand alone debug mode on the error calculator, the state of this bit is presented to the KES engine as the input mode (4K or 2K pages). 12 KES_DEBUG_ KICK Toggling causes KES engine FSM to start as if kick by the Bus Master. This allows stand alone testing of the KES and Chien Search engines. Be sure to set KES_BCH_DEBUG0_KES_STANDALONE mode to 1 before kicking. 11 KES_ STANDALONE Set to one to cause the KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine. 10 KES_DEBUG_ STEP Toggling this bit causes the KES FSM to skip passed the stall state if it is in DEBUG_STALL mode and it has completed processing a block. 9 KES_DEBUG_ STALL Set to one to cause KES FSM to stall after notifying Chien search engine to start processing its block but before notifying the bus master that the KES computation is complete. This allows a diagnostic to stall the FSM after each blocks key equations are solved. This also has the effect of stalling the CSFE search engine so it's state can be examined after it finishes processing the KES stalled block. 0x1 0x1 0x0 0x1 0x0 0x1 4k -- Mode is set for 4K NAND pages. 2k -- Mode is set for 2K NAND pages. NORMAL -- Bus master address generator for synd_gen writes operates normally. TEST_MODE -- Bus master address generator always addresses last four bytes in Auxilliary block. NORMAL -- KES FSM proceeds to next block supplied by bus master. WAIT -- KES FSM waits after current equations are solved and the search engine is started. 8 1 = Point all synd_gen writes to dummy area at the end of the AUXILLIARY block so that diagnostics can BM_KES_TEST_ preload all payload, parity bytes and computed syndrome bytes for test the KES engine. BYPASS 0x0 NORMAL -- Bus master address generator for synd_gen writes operates normally. 0x1 TEST_MODE -- Bus master address generator always addresses last four bytes in Auxilliary block. 7-6 RSVD0 DEBUG_REG_ SELECT Reserved, always set these bits to zero. The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine. 16.6.17 KES Debug Read Register (BCH_DBGKESREAD) The hardware BCH ECC accelerator key equation solver internal state machines and signals can be seen in the ECC debug registers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1407 BCH Memory Map/Register Definition Address: 0h base + 110h offset = 110h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUES R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCH_DBGKESREAD field descriptions Field Description VALUES This register will return the ROM BIST CRC value after a BIST test. 16.6.18 Chien Search Debug Read Register (BCH_DBGCSFEREAD) The hardware BCH ECC accelerator Chien Search internal state machines and signals can be seen in the ECC debug registers. Address: 0h base + 120h offset = 120h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUES R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCH_DBGCSFEREAD field descriptions Field Description VALUES Reserved 16.6.19 Syndrome Generator Debug Read Register (BCH_DBGSYNDGENREAD) The hardware BCH ECC accelerator syndrome generator internal state machines and signals can be seen in the ECC debug registers. Address: 0h base + 130h offset = 130h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUES R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1408 Freescale Semiconductor, Inc. Chapter 16 20-BIT Correcting ECC Accelerator (BCH) BCH_DBGSYNDGENREAD field descriptions Field Description VALUES Reserved 16.6.20 Bus Master and ECC Controller Debug Read Register (BCH_DBGAHBMREAD) The hardware BCH ECC accelerator bus master and ecc controller internal state machines and signals can be seen in the ECC debug registers. Address: 0h base + 140h offset = 140h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUES R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCH_DBGAHBMREAD field descriptions Field Description VALUES Reserved 16.6.21 Block Name Register (BCH_BLOCKNAME) Read only view of the block name string BCH. Fixed pattern read only value for test purposes. Can be read as an ASCII string with the zero termination coming from the first byte of the BLOCKVERSION register. Address: 0h base + 150h offset = 150h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0 NAME R W Reset 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 BCH_BLOCKNAME field descriptions Field NAME Description Should be the ASCII characters BCH (0x20, H, C, B). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1409 BCH Memory Map/Register Definition 16.6.22 BCH Version Register (BCH_VERSION) This register always returns a known read value for debug purposes and indicates the version of the block. Address: 0h base + 160h offset = 160h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCH_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1410 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 17.1 Overview The Synchronous Serial Port is a host controller which provides a flexible interface for inter-IC and removable media control and communication. The SSP supports MMC/SD/ SDIO 1-bit, 4-bit, and 8-bit modes; SPI master and slave modes; and Texas Instruments SSI mode. The SSP is fully compliant with the eMMC 4.4 standard. Specifically, it supports Power-on and alternate boot mode and is designed to perform both SDR and DDR operations at the maxinum speed of 52 MHz. In SPI mode, the SSP has enhancements to support 1-bit legacy MMC cards, and SPI master dual (2-bit) and quad (4-bit) read modes are also supported. The SSP has a dedicated DMA channel in the bridge and can also be controlled directly by the CPU through PIO registers.Figure 17-1 illustrates one of the four SSP ports included on the i.MX28. Each SSP is independent of the other and can have separate SSPCLK frequencies. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1411 External Pins ARM Core SRAM System Clock Generator AHB AHB Slave AHB Master AHB-to-APBH Bridge APBH SPI TI SSI SSPCLK APBH Master HCLK DMA Request DMA Controller 8-Bit SD/SDIO/MMC Modes Synchronous Serial Port GPIO SSP/GPIO Pin MUX Pins Figure 17-1. Synchronous Serial Port Block Diagram 17.2 External Pins The following table lists the SSP pin placements for all supported modes. Table 17-1. SSP Pin Matrix Pin Name MOTOROLASPI Mode WinBONDSPI Mode TI SSIMode SD/SDIO/MMC/ Modes SSP_SCK SCK CLK CLK CLK SSP_CMD MOSI DI (IO0) MOSI CMD SSP_DATA0 MISO DO (IO1) MISO DATA0 SSP_DATA1 WPn (IO2) DATA1/IRQ SSP_DATA2 HOLDn (IO3) DATA2 SSP_DATA3 SSn0 SSn0 SSn DATA3 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1412 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) Table 17-1. SSP Pin Matrix (continued) Pin Name MOTOROLASPI Mode WinBONDSPI Mode TI SSIMode SSP_DATA4 SSn1 SSn1 DATA4 SSP_DATA5 SSn2 SSn2 DATA5 SD/SDIO/MMC/ Modes SSP_DATA6 DATA6 SSP_DATA7 DATA7 SSP_DETECT CARD_DETECT The pin control interface on the i.MX28 provides all digital pins with selectable output drive strengths. In addition, all SSP data pins have selectable 47-K pullup resistors, and SSP command pins have 10-K pullups. Configuring the SSP_CMD pad to connect to the internal 10-K pullup is recommended for SD/SDIO/MMC modes during the Card_ID phase. After the Card_ID phase, the 10-K pullup should be disabled, and the weaker external 47-K pullup takes over. The SSP_DATA pads also can be configured to connect to an internal 47-K pullup, which is required for SD/SDIO/MMC modes. 17.3 Bit Rate Generation The serial bit rate is derived by dividing down the internal clock SSPCLK. The clock is first divided by an even prescale value, CLOCK_DIVIDE, from 2 to 254, which is programmed in HW_SSP_TIMING. The clock is further divided by a value from 1 to 256, which is 1 + CLOCK_RATE, where CLOCK_RATE is the value programmed in HW_SSP_TIMING. The frequency of the output signal bit clock SSP_SCK is defined as follows: SSP _ SCK = SSPCLK CLOCK DIVIDE x (1 + CLOCK _ RATE) For example, if SSPCLK is 3.6864 MHz, and CLOCK_DIVIDE = 2, then SSP_SCK has a frequency range from 7.2 KHz to 1.8432 MHz. See Clock Generation and Control (CLKCTRL) Overview for more clock details. 17.4 Frame Format for SPI and SSI Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. Two basic frame types can be selected: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1413 Motorola SPI Mode * Motorola SPI * Texas Instruments Synchronous Serial Interface (SSI) For both formats, the serial clock (SSP_SCK) is held inactive while the SSP is idle and transitions at the programmed frequency only during active transmissions or reception of data. The idle state of SSP_SCK is used to provide a receive time-out indication, which occurs when FIFO still contains data after a time-out period. For Motorola SPI frame format, the serial frame (SSn) pin is active low and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial interface (SSI) frame format, the SSn pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSP and the off-chip slave device drive their output on data on the rising edge of SSP_SCK, and latch data from the other device on the falling edge. The SSP master supports up to three combinations of SPI and SSI slave devices connected. Three SSn pins are provided but only one can be active at a time. 17.5 Motorola SPI Mode The SPI mode is used for general inter-component communication and legacy 1-bit MMC cards. 17.5.1 SPI DMA Mode The SPI bus is inherently a full-duplex bidirectional interface. However, as most applications only require half-duplex data transmission, the i.MX28 has a single DMA channel for the SSP. It can be configured for either transmit or receive. In DMA receive mode, the SPI continuously repeats the word written to its data register. In DMA transmit mode, the SPI ignores the incoming data. 17.5.2 Motorola SPI Frame Format The Motorola SPI interface is a four-wire interface where the SSn signal behaves as a slave select. The main feature of the Motorola SPI format is that the inactive state and phase of SSP_SCK signal are programmable through the polarity and phase bits within the HW_SSP_CTRL1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1414 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 17.5.2.1 Clock Polarity * When the clock polarity control bit is low, it produces a steady-state low value on the SSP_SCK pin. * When the clock polarity control bit is high, a steady-state high value is placed on the SSP_SCK pin when data is not being transferred. 17.5.2.2 Clock Phase The phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted, by either allowing or not allowing a clock transition before the first data-capture edge. * When the phase control bit is low, data is captured on the first clock-edge transition. * When the clock phase control bit is high, data is captured on the second clock-edge transition. 17.5.3 Motorola SPI Format with Polarity=0, Phase=0 Single and continuous transmission signal sequences for Motorola SPI format with POLARITY=0, PHASE=0 are shown in Figure 17-2 and Figure 17-3. SSP_SCK SSn MISO LSB MSB Q 4 to 16 bits MSB MOSI LSB Figure 17-2. Motorola SPI Frame Format (Single Transfer) with POLARITY=0 and PHASE=0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1415 Motorola SPI Mode SSP_SCK SSn MOSI/MISO LSB MSB LSB MSB 4 to 16 bits Figure 17-3. Motorola SPI Frame Format with POLARITY=0 and PHASE=0 In this configuration, during idle periods: * The SSP_SCK signal is forced low. * SSn is forced high. * The Transmit data line MOSI is arbitrarily forced low. * When the SSP is configured as a master, SSP_SCK is an output. * When the SSP is configured as a slave, SSP_SCK is an input. If the SSP is enabled and there is valid data within the FIFO, the start of the transmission is signified by the SSn master signal being low. This causes slave data to be enabled onto the MISO input line of the master, and enables the master MOSI output pad. One-half SSP_SCK period later, valid master data is transferred to the MOSI pin. Now that both the master and slave data have been set, the SSP_SCK master clock pin goes high after one further half SSP_SCK period. The data is now captured on the rising and propagated on the falling edges of the SSP_SCK signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSn line is returned to its idle high state one SSP_SCK period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSn signal must be pulsed high between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the PHASE bit is logic 0. Therefore, the master device must raise the SSn pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSn pin is returned to its idle state one SSP_SCK period after the last bit has been captured. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1416 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 17.5.4 Motorola SPI Format with Polarity=0, Phase=1 The transfer signal sequence for Motorola SPI format with POLARITY=0 and PHASE=1 is shown in Figure 17-4, which covers both single and continuous transfers. SSP_SCK SSn MISO Q LSB MSB Q 4 to 16 bits MSB MOSI LSB Figure 17-4. Motorola SPI Frame Format (Continuous Transfer) with POLARITY=0 and PHASE=1 In this configuration, during idle periods: * The SSP_SCK signal is forced low. * SSn is forced high. * The Transmit data line MOSI is arbitrarily forced low. * When the SSP is configured as a master, the SSP_SCK pad is an output. * When the SSP is configured as a slave, the SSP_SCK is an input. If the SSP is enabled and there is valid data within the FIFO, the start of the transmission is signified by the SSn master signal being low. After a further one-half SSP_SCK period, both master and slave valid data are enabled with a rising-edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSP_SCK signal. In the case of a single word transfer, after all bits have been transferred, the SSn line is returned to its idle high state one SSP_SCK period after the last bit has been captured. For continuous back-to-back transfers, SSPFSOUT (the SSn pin in master mode) is held low between successive data words and termination is the same as that of a single word transfer. 17.5.5 Motorola SPI Format with Polarity=1, Phase=0 Single and continuous transmission signal sequences for Motorola SPI format with POLARITY=1 and PHASE=0 are shown in Figure 17-5 and Figure 17-6. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1417 Motorola SPI Mode SSP_SCK SSn MISO MSB LSB Q 4 to 16 bits MSB MOSI LSB Figure 17-5. Motorola SPI Frame Format (Single Transfer) with POLARITY=1 and PHASE=0 Note In Figure 17-5, Q is an undefined signal. SSP_SCK SSn MOSI/MISO LSB LSB MSB MSB 4 to 16 bits Figure 17-6. Motorola SPI Frame Format (Continuous Transfer) with POLARITY=1 and PHASE=0 In this configuration, during idle periods: * The SSP_SCK signal is forced high. * SSn is forced high. * The Transmit data line MOSI is arbitrarily forced low. * When the SSP is configured as a master, the SSP_SCK pad is an output. * When the SSP is configured as a slave, the SSP_SCK is an input. If the SSP is enabled and there is valid data within the FIFO, the start of transmission is signified by the SSn master signal being driven low, which causes slave data to be immediately transferred onto the MISO line of the master, and enabling the master MOSI output pad. One half-period later, valid master data is transferred to the MOSI line. Now that both master and slave data have been set, the SSP_SCK master clock pin becomes low after one further half SSP_SCK period. This means that data is captured on the falling edges and propagated on the rising edges of the SSP_SCK signal. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1418 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) In the case of a single word transmission, after all bits of the data word are transferred, the SSn line is returned to its idle high state one SSP_SCK period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSn signal must be pulsed high between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the PHASE bit is logic 0. Therefore, the master device must raise SSPSFSSIN (the SSn pin in slave mode) of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSn pin is returned to its idle state one SSP_SCK period after the last bit has been captured. 17.5.6 Motorola SPI Format with Polarity=1, Phase=1 The transfer signal sequence for Motorola SPI format with POLARITY=1 and PHASE=1 is shown in Figure 17-7, which covers both single and continuous transfers. SSP_SCK SSn MISO Q MOSI MSB LSB Q 4 to 16 bits MSB LSB Figure 17-7. Motorola SPI Frame Format with POLARITY=1 and PHASE=1 Note In Figure 17-7, Q is an undefined signal. In this configuration, during idle periods: * The SSP_SCK signal is forced high. * SSn is forced high. * The Transmit data line MOSI is arbitrarily forced low. * When the SSP is configured as a master, the SSP_SCK pad is an output. * When the SSP is configured as a slave, the SSP_SCK is an input. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1419 Winbond SPI Mode If the SSP is enabled and there is valid data within the FIFO, the start of transmission is signified by the SSn master signal being driven low, and MOSI output is enabled. After a further one-half SSP_SCK period, both master and slave are enabled onto their respective transmission lines. At the same time, the SSP_SCK is enabled with a falling edge transition. Data is then captured on the rising edge and propagated on the falling edges of the SSP_SCK signal. After all bits have been transferred, in the case of a single word transmission, the SSn line is returned to its idle high state one SSP_SCK period after the last bit has been captured. For continuous back-to-back transmissions, the SSn pin remains in its active low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSn pin is held low between successive data words and termination is same as that of a single word transfer. 17.6 Winbond SPI Mode The Winbond SPI mode is similar to Motorola's SPI mode when POLARITY = PHASE, where data is sampled on the rising edge. In addition to serial 1-bit reads and writes, 2-bit (dual) and 4-bit (quad) reads are supported. Only 8-bit word length is supported for dual and quad read modes. See Figure 17-8. The numbers in the IO signal waveform correspond to the bit position in the byte being transferred. CLK CLK IO0 SwitchesfromInput to Out IO0 Switches from Input to Output IO0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 IO1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 * Data Out 1 Data Out 2 * Data Out 3 Data Out 4 IO0 4 0 4 0 4 0 4 0 IO1 5 1 5 1 5 1 5 1 IO2 6 2 6 2 6 2 6 2 IO3 7 3 7 3 7 3 7 3 Byte 1 Byte 2 Byte 3 Byte 4 Figure 17-8. Fast Read Dual and Quad Output Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1420 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 17.7 Texas Instruments Synchronous Serial Interface (SSI) Mode Figure 17-9 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. SSP_SCK SSn MSB MOSI/MISO LSB 4 to 16 bits Figure 17-9. Texas Instruments Synchronous Serial Frame Format (Single Transfer) In this mode, SSP_SCK and SSn are forced low, and the transmit data line MOSI is three-stated whenever the SSP is idle. Once the bottom entry of the FIFO contains data, SSn is pulsed high for one SSP_SCK period. The value to be transmitted is also transferred from the FIFO to the serial shift register of the transmit logic. On the next rising edge of SSP_SCK, the MSB of the 4-to-16-bit data frame is shifted out on the SSPRXD pin by the off-chip serial slave device. Both the SSP and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSP_SCK. The received data is transferred from the serial shifter to the FIFO on the first rising edge of SSP_SCK after the LSB has been latched. Figure 17-10 shows the Texas Instrument synchronous serial frame format when back-toback frames are transmitted. SSP_SCK SSn MOSI/MISO MSB LSB 4 to 16 bits Figure 17-10. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1421 SD/SDIO/MMC Mode 17.8 SD/SDIO/MMC Mode This mode is used to provide high performance with SD, SDIO, MMC, and high-speed (4-bit and 8-bit) MMC cards. When running 4-bit and 8-bit modes, the SSP has the capability of SDR and DDR operations. Power-on and alternate boot operations are also supported. SD/MMC mode supports simultaneous command and data transfers. Commands are sent to the card and responses are returned to the host on the CMD line. Register data, such as card information, is sent as a command response and is therefore on the CMD line. Block data read from or written to the card's flash is transferred on the DAT line(s). The SSP also supports the SDIO IRQ. The SSP's SD/MMC controller can automatically perform a single block read/write or card register operation with a single PIO setup and RUN. For example, the SD/MMC controller can perform these steps with a single write to the PIO registers: * Send command to the card. * Receive response from the card. * Check response for errors (and assert a CPU IRQ if there is an error). * Wait for the DAT line(s) to be ready to transfer data (while counting for time-out). * Transfer multiple blocks of data to/from the card. * Check the CRC or CRC status of received/sent data (and assert IRQ if there is an error). The SD/MMC controller is generally used with the DMA. Each DMA descriptor is set up the SD/MMC controller to perform a single complex operation as exemplified above. Multiple DMA descriptors can be chained to perform multiple card block transfers without CPU intervention. A single DMA descriptor can also perform multiple card block transfers. 17.8.1 SD/MMC Command/Response Transfer SD/MMC commands are written to the HW_SSP_CMDn registers and sent on the CMD line. Command tokens consist of a start bit (0), a source bit (1), the actual command, which is padded to 38 bits, a 7-bit CRC and a stop bit (1). The command token format is shown in Table 17-2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1422 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) Table 17-2. SD/MMC Command/Response Transfer Line Start Source Data CRC End CMD 0 1 (Host) 38-bit Command CRC7 1 SD/MMC cards transmit command words with the most significant bit first. After the card receives the command, it checks for CRC errors or invalid commands. If an error occurs, the card withholds the usual response to the command. After transmitting the end bit, the SSP releases the CMD line to the high-impedance state. A pullup resistor on the CMD node keeps it at the 1 state until the response packet is received. The slave waits to issue a reply until the SCK line is clocking again. After the SSP sends an SD/MMC command, it optionally starts looking for a response from the card. It waits for the CMD line to go low, indicating the start of the response token. Once the SSP has received the Start and Source bits, it begins shifting the response content into the receive shift register. The SSP calculates the CRC7 of the incoming data. If the card fails to start sending an expected response packet within 64 SCK cycles, then an error occurrs; the command may be invalid or have a bad CRC. After the SSP detects a time-out, it stops any DMA request activity and sets the RESP_TIMEOUT flag. If RESP_TIMEOUT_IRQ_EN is set, then a CPU IRQ is asserted. The SSP calculates the CRC of the received response and compares it to the CRC received from the card. If they do not match, then the SSP sets the RESP_ERR status flag. If RESP_ERR_IRQ_EN is set, then a CPU IRQ is asserted on a command response CRC mismatch. The SSP can also compare the 32-bit card status word, known as response R1, against a reference to check for errors. If CHECK_RESP in HW_SSP_CTRL0 is set, then the SSP XORs the response with the XOR field in the HW_SSP_COMPREF register. It then masks the results with the MASK field in the HW_SSP_COMPMASK register. If there are any differences between the masked response and the reference, then an error will occur. The CPU asserts the RESP_ERR status flag. If RESP_ERR_IRQ_EN is set, then the RESP_ERR_IRQ is asserted. In the ISR, the CPU can read the status word to see which error flags are set. The regular and long response tokens are shown in Table 17-3 and Table 17-4 : Table 17-3. SD/MMC Command Regular Response Token Line Start Source Data CRC End CMD 0 0 (Card) 38-bit Response CRC7 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1423 SD/SDIO/MMC Mode Table 17-4. SD/MMC Command Regular Long Response Token Line Start Source Data CRC End CMD 0 0 (Card) 117-bit response CRC16 1 17.8.2 SD/MMC Data Block Transfer Block data is transferred on the DATA0 pin. In 1-bit I/O mode, the block data is formatted as shown in Table 17-5. Block data transfers typically have 512 bytes of payload, plus a 16-bit CRC, a Start bit, and an End bit. The block size is programmable with the XFER_COUNT field in the HW_SSP_XFER_SIZE register. In SD/MMC mode, WORD_LENGTH in the HW_SSP_CTRL1 register field should always be set to 8 bits. Data is always sent Most Significant Bit of the Least Significant Byte first. The SSP is designed to support block transfer modes only. Streaming modes may not be supported. Figure 17-11 shows a flowchart of SD/MMC block read and write transfers. In block write mode, the card holds the DATA0 line low while it is busy. SSP must wait for the DATA0 line to be high for one clock cycle before starting to write to a block. In block read mode, the card begins sending the data when it is ready. The first bit transmitted by the card is a Start bit 0. Prior to the 0 Start Bit, the DATA0 bus is high. After the Start bit is received, data is shifted in. The SSP bus width is set using the BUS_WIDTH bit in the HW_SSP_CTRL0 register. In 1-bit bus mode, the block data is formatted as shown in Table 17-5. Table 17-5. SD/MMC Data Block Transfer 1-Bit Bus Mode Line Start Data Data Data CRC End DATA0 0 Data Bit 7 Byte 0 ... Data Bit 0 Byte 511 CRC16 1 In 4-bit I/O mode, the block data is formatted as shown in Table 17-6. Table 17-6. SD/MMC Data Block Transfer 4-Bit Bus Mode Line Start Data Data Data CRC End DATA3 0 Data Bit 7 Byte 0 ... Data Bit 3 Byte 511 CRC16 1 DATA2 0 Data Bit 6 Byte 0 ... Data Bit 2 Byte 511 CRC16 1 DATA1 0 Data Bit 5 Byte 0 ... Data Bit 1 Byte 511 CRC16 1 DATA0 0 Data Bit 4 Byte 0 ... Data Bit 0 Byte 511 CRC16 1 In 8-bit bus mode, the block data is formatted as shown in Table 17-7. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1424 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) Table 17-7. SD/MMC Data Block Transfer 8-Bit Bus Mode Line Start Data Data Data CRC End DATA7 0 Data Bit 7 Byte 0 ... Data Bit 7 Byte 511 CRC16 1 DATA6 0 Data Bit 6 Byte 0 ... Data Bit 6 Byte 511 CRC16 1 DATA5 0 Data Bit 5 Byte 0 ... Data Bit 5 Byte 511 CRC16 1 DATA4 0 Data Bit 4 Byte 0 ... Data Bit 4 Byte 511 CRC16 1 DATA3 0 Data Bit 3 Byte 0 ... Data Bit 3 Byte 511 CRC16 1 DATA2 0 Data Bit 2Byte 0 ... Data Bit 2 Byte 511 CRC16 1 DATA1 0 Data Bit 1 Byte 0 ... Data Bit 1 Byte 511 CRC16 1 DATA0 0 Data Bit 0 Byte 0 ... Data Bit 0 Byte 511 CRC16 1 17.8.2.1 SD/MMC Multiple Block Transfers The SSP supports SD/MMC multiple block transfers. The CPU or DMA will configure the SD/MMC controller to issue a Multi-Block Read or Write command. If DMA is used, then the first descriptor issues the multi-block read/write command and receives/sends the first block (512 bytes) of data. Subsequent DMA descriptors only receive/send blocks of data and do not issue new SD/MMC commands. If the card is configured for an openended multi-block transfer, then the last DMA descriptor needs to issue a STOP command to the card. Multiple blocks can also be transferred with a single DMA descriptor. After each block of data has been transferred, the SSP sends/receives the CRC and checks the CRC or the CRC token. If the CRC is correct, then the SSP signals the DMA that it is completed. The SSP supports transferring multiple SD/MMC blocks per DMA descriptor. The SSP state machine needs to know the number of blocks and the size of a block. When HW_SSP_BLOCK_SIZE_BLOCK_COUNT is non-zero, the actual block size is: 0x1 shiftleft BLOCK_SIZE For example, setting a value of 9 will result in a block size of 512 bytes. When BLOCK_COUNT is 0, BLOCK_SIZE is ignored and the bit field HW_SSP_XFER_SIZE_XFER_COUNT represents the single block size or the number of byte to transfer. This must satisfy the equation: HW_SSP_XFER_SIZE_XFER_COUNT = (0x1 shiftleft BLOCK_SIZE) x (BLOCK_COUNT+1) for BLOCK_COUNT greater than 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1425 SD/SDIO/MMC Mode 17.8.2.2 eMMC DDR operation When performing a single block or multiple block transfer, the SSP has an option of using DDR operation by setting DBL_DATA_RATE_EN bit in HW_SSP_CMD0 register. When performing a DDR operation, the timing relationship between SCK and DATA can be programmed to suit different needs. The highly recommended settings are in the following (but not necessary): * To set TXCLK_DELAY_TYPE of HW_SSP_DDR_CTRL register allows SCK to have a 1/4 SCK delay and to switch approximately at the center of each TX DATA period. * Turn on the DLL by setting ENABLE bit of HW_SSP_DLL_CTRL registerr. This generates a precisive clock delay relative to SCK (input version), which is used to sample RX DATA. Program the value of 4'd7 to DLV_DLY_TARGET field of HW_SSP_DLL_CTRL register, and this specifies the clock delay to be 1/4 of SCK period. To boost the performance of SSP running in DDR mode and at the maximum frequency, the DMA interface allows a burst of 4 or 8 32-bit APB transfers per DMA request. 17.8.2.3 SD/MMC Block Transfer CRC Protection The block of data transferred over the data bus is protected by CRC16. For reads, the SSP calculates the CRC of the incoming data and compares it to the CRC16 reference that is provided by the card at the end of the block. In DDR mode, two sets of CRC16s are calculated for both the rising edge sampled data and the falling edge sampled data. If any CRC mismatch occurs, then the block asserts the DATA_CRC_ERR status flag. If DATA_CRC_IRQ_EN is set, then a CPU IRQ is asserted. For block write operations, the card determines if a CRC error has occurred. After the SSP has sent a block of data, it transmits the reference CRC16. In DDR mode, two sets of reference CRC16s are transmitted. The card compares that(those) to its calculated CRC16(s). The card then sends a CRC status token on the DATA bus. It sends a positive status ('010') if the transfer was good, and a negative status ('101') if the CRC16(s) did not match. If the SSP receives a CRC bad token, it sets the DATA_CRC_ERROR in the HW_SSP_STATUS register, and then it indicates it to the CPU if DATA_CRC_IRQ_EN is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1426 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 17.8.3 eMMC Boot Operation In boot operation mode, the SSP can read boot data from the slave (MMC device) by keeping SSP_CMD line low using PRIM_BOOT_OP_EN bit, or sending CMD0 with argument = 0xFFFFFFFA, before issuing CMD1. User can terminate the boot operation by setting SOFT_TERMINATE bit in HW_SSP_CMD0 register when using primary boot method, or send a CMD0 command when using the alternate boot method. Boot acknowledge is also supported by setting BOOT_ACK_EN bit in HW_SSP_CMD0 register. The boot mode supports DDR operations as specified in eMMC 4.4 standard. 17.8.4 SDIO Interrupts The SSP supports SDIO interrupts. When the SSP is in SD/MMC mode and the SDIO_IRQ bit in the HW_SSP_CTRL0 register is set, the SSP looks for interrupts on DATA1 during the valid IRQ periods. The valid IRQ periods are defined in the SDIO specification. If the card asserts an interrupt and SDIO_IRQ_EN is set, then the SSP sets the SDIO_IRQ status bit and asserts a CPU IRQ. Other than detecting when card IRQs are valid, the SDIO IRQ function operates independently from the rest of the SSP. After the CPU receives an IRQ, it should monitor the SSP and DMA status to determine when it should send commands to the SDIO card to handle the interrupt. 17.8.5 SD/MMC Mode Error Handling There are several errors that can occur during the SD/MMC operation. These errors can be caused by normal unexpected events, such as having a card removed or unusual events such as a card failure. The detected error cases are listed below. Please note that in all the cases below, a CPU IRQ is only asserted if DATA_CRC_IRQ_EN is set in HW_SSP_CTRL1 register. * Data Receive CRC Error--Detected by the SSP after a block receive. If this occurs, the SSP will not indicate to DMA that the transfer is complete. It will set the DATA_CRC_ERR status flag and assert a CPU IRQ. The ISR should reset the SSP DMA channel and instruct the DMA to re-try the block read operation. * Data Transmit CRC Error--Transmit CRC error token is received from the SD/ MMC card on the DAT line after a block transmit. If this occurs, the SSP will not indicate to DMA that the transfer is complete. It will set the DATA_CRC_ERR status flag and assert a CPU IRQ. The ISR should reset the SSP DMA channel and instruct the DMA to re-try the block write operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1427 SD/SDIO/MMC Mode SD/MMC Block Read Example SD/MMC Block Write Example DMA PIO cycle: SD/MMC mode Read Mode XFER_COUNT=512 Write the BLOCK_READ command to SDCTRLx. DMA sets SSP Run bit. DMA PIO cycle: SD/MMC mode Write Mode XFER_COUNT=512 Write the BLOCK_WRITE command to SDCTRLx. DMA sets SSP Run bit. SSP sends out the MMC Block Read Command and begins looking at the DAT line for a Start Bit. After the Block Read command is sent, SSP looks at the CMD line for a Response. SSP sends out the MMC Block Write Command and begins looking at the DAT line for Busy Condition. SSP will start issuing DMA requests to fill the transmit FIFO. After the Block Write command is sent, SSP looks at the CMD line for a Response. When the response is sent by the MMC card, the SSP will place the response in the RESP register. The SSP will check the CRC7 of the response packet against the received CRC7. If there is an error, it will assert a CPU IRQ. When the response is sent by the MMC card, the SSP will place the response in the RESP register. The SSP will check the CRC7 of the response packet against the received CRC7. If there is an error, it will assert a CPU IRQ. When the Data is ready, the MMC will send the start bit and the SSP will put the data into the receive FIFO and start asserting DMA request. The received data will also be checked for CRC16. If there is a CRC error, the SSP will assert a CPU IRQ. When the Data line is no longer busy, the SSP will start sending data. The transmitted data will also have CRC16 calculated and transmitted after the data. If the card indicates a CRC error, the SSP will assert a CPU IRQ. After the block has been read and the CRC checked, the SSP will indicate to the DMA that it is done. The DMA can then issue a new command sequence, or tell the CPU that it is done. After the block has been sent and the CRC checked, the SSP will indicate to the DMA that it is done. The DMA can then issue a new command sequence or tell the CPU that it is done. Figure 17-11. SD/MMC Block Transfer Flowchart * Data Time-Out Error--The SSP TIMEOUT counter is used to detect a time-out condition during data write or read operations. The time-out counts any time that the SSP is waiting on a busy DAT bus. For read operations, the DAT line(s) indicate busy before the card sends the start bit. For write operations, the DAT line(s) may indicate busy after the block has been sent to the card. If the time-out counter expires i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1428 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) before the DAT line(s) become ready, the SSP stops any DMA requests, sets the DATA_TIMEOUT status flag, and asserts a CPU IRQ. The ISR should check the status register to see that a data time-out has occurred. It can then reset the DMA channel and the SSP to re-try the operation. * DMA Overflow/Underflow--The SSP should stop SCK if the FIFO is full or the FIFO is empty during data transfer. So, a DMA underflow or overflow should not occur. However, if it does due to some unforeseen problem, the FIFO_OVRFLW or FIFO_UNDRFLW status bit is set in the SSP Status Register and asserts a CPU IRQ. * Command Response Error--The SD/MMC card returns a R1 status response after most commands. The SSP can compare the R1 response against a mask/reference pair. If any of the enabled bits are set, then an error will occur. The SSP stops requesting any DMAs, sets the RESP_ERR status flag, and asserts a CPU IRQ. The CPU can read the SSP Status Register to see the RESP_ERR flag and read the HW_SSP_SDRESP0 register to get the actual response from the SD/MMC card. That response contains the specific error information. Once the error is understood, the CPU can reset the DMA channel and the SSP and re-try the operation or take some other action to recover or inform the user of a non-recoverable error. * Command Response Time-Out--If an expected response is not received within 64 SCK cycles, then the command response has timed out. If this occurs, the SSP stops any DMA requests, stops transferring data to the card, sets the RESP_TIME-OUT status flag, and asserts the RESP_TIME-OUT_IRQ. The ISR should read the status register to find that a command response time-out has occurred. It can then decide to reset the DMA channel and SSP and re-try the operation. 17.8.6 SD/MMC Clock Control * When SD/MMC block is idle, the serial clock (SCK) toggling will be based on the value of CONT_CLKING_EN and SLOW_CLKING_EN. See HW_SSP_CMD0 register description. * SCK runs any time that RUN is set and a data or command is active or pending. If a command has been sent and a response is expected, then SCK continues to run until the response is received. If a data operation is active or if the DAT line is busy, then SCK runs. * If CONT_CLKING_EN=0, SCK stops running if received command response status R1 indicates an error. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1429 Behavior During Reset * If CONT_CLKING_EN=0, SCK stops running if a data operation has timed out or a CRC error has occurred. * If CONT_CLKING_EN=0, SCK stops running after all pending commands and data operations have completed. SCK restarts when a new command or data operation has been requested. 17.9 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. 17.10 Programmable Registers SSP Hardware Register Format Summary SSP0 base address is 0x80010000; SSP1 base address is 0x80012000; SSP2 base address is 0x80014000; SSP3 base address is 0x80016000 HW_SSP memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8001_0000 SSP Control Register 0 (HW_SSP_CTRL0) 32 R/W C000_0000h 17.10.1/ 1431 8001_0010 SD/MMC Command Register 0 (HW_SSP_CMD0) 32 R/W 0000_0000h 17.10.2/ 1434 8001_0020 SD/MMC Command Register 1 (HW_SSP_CMD1) 32 R/W 0000_0000h 17.10.3/ 1437 8001_0030 Transfer Count Register (HW_SSP_XFER_SIZE) 32 R/W 0000_0001h 17.10.4/ 1438 8001_0040 SD/MMC BLOCK SIZE and COUNT Register (HW_SSP_BLOCK_SIZE) 32 R/W 0000_0000h 17.10.5/ 1438 8001_0050 SD/MMC Compare Reference (HW_SSP_COMPREF) 32 R/W 0000_0000h 17.10.6/ 1439 8001_0060 SD/MMC compare mask (HW_SSP_COMPMASK) 32 R/W 0000_0000h 17.10.7/ 1439 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1430 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) HW_SSP memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8001_0070 SSP Timing Register (HW_SSP_TIMING) 32 R/W 0000_0000h 17.10.8/ 1439 8001_0080 SSP Control Register 1 (HW_SSP_CTRL1) 32 R/W 0000_0080h 17.10.9/ 1440 8001_0090 SSP Data Register (HW_SSP_DATA) 32 R/W 0000_0000h 17.10.10/ 1443 8001_00A0 SD/MMC Card Response Register 0 (HW_SSP_SDRESP0) 32 R 0000_0000h 17.10.11/ 1444 8001_00B0 SD/MMC Card Response Register 1 (HW_SSP_SDRESP1) 32 R 0000_0000h 17.10.12/ 1444 8001_00C0 SD/MMC Card Response Register 2 (HW_SSP_SDRESP2) 32 R 0000_0000h 17.10.13/ 1445 8001_00D0 SD/MMC Card Response Register 3 (HW_SSP_SDRESP3) 32 R 0000_0000h 17.10.14/ 1445 8001_00E0 SD/MMC Double Data Rate Control Register (HW_SSP_DDR_CTRL) 32 R/W 0000_0000h 17.10.15/ 1445 8001_00F0 SD/MMC DLL Control Register (HW_SSP_DLL_CTRL) 32 R 0000_0000h 17.10.16/ 1447 8001_0100 SSP Status Register (HW_SSP_STATUS) 32 R E000_0020h 17.10.17/ 1448 8001_0110 SD/MMC DLL Status Register (HW_SSP_DLL_STS) 32 R 0000_0000h 17.10.18/ 1451 8001_0120 SSP Debug Register (HW_SSP_DEBUG) 32 R 0000_0000h 17.10.19/ 1452 8001_0130 SSP Version Register (HW_SSP_VERSION) 32 R 0400_0000h 17.10.20/ 1455 17.10.1 SSP Control Register 0 (HW_SSP_CTRL0) SSP Control Register 0 HW_SSP_CTRL0: 0x000 HW_SSP_CTRL0_SET: 0x004 HW_SSP_CTRL0_CLR: 0x008 HW_SSP_CTRL0_TOG: 0x00C This is the most frequently changed fields. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1431 Programmable Registers 31 30 29 28 27 26 25 24 DATA_XFER WAIT_FOR_IRQ WAIT_FOR_CMD LONG_RESP CHECK_RESP 16 READ 17 IGNORE_CRC 18 LOCK_CS 19 SDIO_IRQ_CHECK 20 CLKGATE Bit 21 RUN GET_ RESP 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset 22 SFTRST R 23 BUS_WIDTH Bit ENABLE Address: 8001_0000h base + 0h offset = 8001_0000h RSVD0 R W Reset 0 0 0 0 0 0 0 0 0 HW_SSP_CTRL0 field descriptions Field 31 SFTRST Description SSP Reset - 0: SSP is not Reset. 1: SSP Held in Reset. After Reset, all registers are returned to their reset state. This will not work if the CLKGATE bit is already set to \'1\'. CLKGATE must be cleared to \'0\' before issuing a soft reset. Also the SSPCLK must be running for this to work properly. 30 CLKGATE 29 RUN 28 SDIO_IRQ_ CHECK 27 LOCK_CS Gate SSP Clocks - 0: SSP Clocks not gated. 1: SSP Clocks are gated. Set this to save power while the SSP is not actively being used. Configuration state is kept while the clock is gated. SSP Run. 0: SSP is not running. 1: SSP is running. Automatically set during DMA operation. In SD/MMC mode: SDIO IRQ: 1= Enable checking for SDIO Card IRQ. In SPI mode: This affects the SSn output. When set to 1, SSn will be asserted throughout the current command. SSn will remain asserted after the command if IGNORE_CRC = 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1432 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) HW_SSP_CTRL0 field descriptions (continued) Field Description SSn will deassert at the end of the next command that has IGNORE_CRC = 1. In SD/MMC mode: 0= Look for a CRC status token from the card on DATA0 after a block write. 1= Ignore the CRC status response on DATA0 after a write operation. Note that the SD/MMC function should be used when performing MMC BUSTEST_W operation. 26 IGNORE_CRC 25 READ Ignore CRC - In SD/MMC. In SPI/SSI modes: When set to 1, deassert the chip select (SSn) pin after the command is executed. Read Mode - When this and DATA_XFER are set, the SSP will read data from the device. If this is not set, then the SSP will write data to the device. 24 DATA_XFER Data Transfer Mode - When set, transfer XFER_COUNT bytes of data. When not set, the SSP will not transfer any data (command or Wait for IRQ only). 23-22 BUS_WIDTH Data Bus Width - SD/MMC modes supports all widths, SSI mode supports only 1-bit bus width. In SPI mode 1, 2, and 4-bit bus widths are supported. In SPI mode the Data Bus Width field is redefined: 0 means 1-bit; 1 means 2-bit; 2 means 4-bit. 0x0 0x1 0x2 ONE_BIT -- SD/MMC data bus is 1-bit wide FOUR_BIT -- SD/MMC data bus is 4-bits wide EIGHT_BIT -- SD/MMC data bus is 8-bits wide 21 Wait for IRQ WAIT_FOR_IRQ In SD/MMC mode this signal means wait for MMC ready before sending command. (MMC is busy when databit0 is low.) In SPI/SSI mode this bit and WAIT_FOR_CMD bit select which SSn output to assert: (WAIT_FOR_IRQ,WAIT_FOR_CMD) = b00: SSn0 will assert during access (SSn2, SSn1 inactive); b01: SSn1 will assert during access (SSn2, SSn0 inactive); b10: SSn2 will assert during access (SSn1, SSn0 inactive). 20 WAIT_FOR_ CMD Wait for Data Done - SD/MMC - 0: Send commands immediately after they are written. 1: Wait to send command until after the CRC-checking phase of a data transfer has completed successfully. This delays sending a command until a block of data is transferred. This can be used to send a STOP command during an SD/MMC multi-block read. In SD/MMC mode this signal means wait for MMC ready before sending command. (MMC is busy when databit0 is low.) In SPI/SSI mode this bit and WAIT_FOR_IRQ bit select which SSn output to assert: (WAIT_FOR_IRQ,WAIT_FOR_CMD) = b00: SSn0 will assert during access (SSn2, SSn1 inactive); b01: SSn1 will assert during access (SSn2, SSn0 inactive); b10: SSn2 will assert during access (SSn1, SSn0 inactive). 19 LONG_RESP Get Long Response - SD/MMC - 0: The card response will be short. 1: The card will provide a 136-bit response. Only valid if GET_RESP is set. A long response cannot be checked using CHECK_RESP. 18 CHECK_RESP Check Response - SD/MMC. If this bit is set, the SSP will XOR the result with the REFERENCE field and then mask the incoming status word with the MASK field in the COMPARE register. If there is a mismatch, then the SSP will set the RESP_ERR status bit, and, if enabled, the RESP_ERR_IRQ. This should not be used with LONG_RESP. 17 GET_RESP Get Response - SD/MMC - 0: Do not wait for a response from the card. 1: This command should receive a response from the card. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1433 Programmable Registers HW_SSP_CTRL0 field descriptions (continued) Field Description 16 ENABLE Command Transmit Enable - SD/MMC - 0: Commands are not enabled. 1: Data in Command registers will be sent. This is normally enabled in SD/MMC. RSVD0 Reserved 17.10.2 SD/MMC Command Register 0 (HW_SSP_CMD0) SD/MMC Command Index and control register HW_SSP_CMD0: 0x010 HW_SSP_CMD0_SET: 0x014 HW_SSP_CMD0_CLR: 0x018 HW_SSP_CMD0_TOG: 0x01C This is the command code for the SD/MMC devices. See device specification for details. For eMMC Alternate boot operation, Command and RX data phases must be executed together (HW_SSP_CTRL0_ENABLE=1 and HW_SSP_CTRL0_DATA_XFER=1) so that SSP does not miss the boot ack or boot data phases. RSVD0 R W Reset 0 0 0 0 0 26 25 APPEND_8CYC 27 CONT_CLKING_EN 28 SLOW_CLKING_EN 29 BOOT_ACK_EN 30 PRIM_BOOT_OP_EN 31 DBL_DATA_RATE_EN Bit SOFT_TERMINATE Address: 8001_0000h base + 10h offset = 8001_0010h 24 23 22 21 20 0 0 0 0 0 0 0 19 18 17 16 RSVD1 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1434 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 RSVD1 R CMD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_CMD0 field descriptions Field 31-27 RSVD0 Description Reserved 26 SOFT_ TERMINATE Setting this bit to 1 causes the current operation to terminate itself under normal condition. This signal is used as edge-sensitive, so in order to create a subsequent termanation, SOFT_TERMINATE must be taken low and then asserted again. 25 DBL_DATA_ RATE_EN This bit enables the Double Data Rate operation. The DDR operation only applies in 4-bit or 8-bit data transfers. 24 PRIM_BOOT_ OP_EN Enable the primary method of Boot Operation where the SSP_CMD output is driven low for the entire boot operation. In primary Boot Operation mode, program the SSP to read one or more 512 byte blocks of data, and ensure command is dissabled (HW_SSP_CTRL0_ENABLE=0). Do not set this bit for the Alternate Boot Operation mode; instead, program the SSP to send command zero (with no response) and read one or more 512 byte blocks of boot data. Enabling the BOOT_ACK is optional. 23 Enable Boot Acknowledge reception from the slave during primary or alternate boot operation. BOOT_ACK_EN For eMMC Alternate boot operation, Command and RX data phases must be executed together (HW_SSP_CTRL0_ENABLE=1 and HW_SSP_CTRL0_DATA_XFER=1) so that SSP does not miss the boot ack or boot data phases. This bit must be zero for non-boot operations. 22 Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively SLOW_CLKING_ transferring command and data. This field is ignored when CONT_CLKING is zero. EN 21 Set this bit to enable Continous clocking of SCK when no SD/MMC command/reaponse or data transfer is CONT_CLKING_ active. This is used in SD/MMC mode. When set to zero, SCK is idle when no transfer is taking place. EN 20 Append 8 SCK cycles. This is used in SD/MMC mode. When set to one, the SCK will toggle for 8 more APPEND_8CYC cycles before going idle. When set to zero SCK will toggle up to 4 cycles before going idle. This should be set to one at the end of a single or multiple block transfer. 19-8 RSVD1 Reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1435 Programmable Registers HW_SSP_CMD0 field descriptions (continued) Field CMD Description SD/MMC Command Index (uses 5:0) to be sent to card. This is also SPI/SSI control word[7:0] for RX transfers. 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x23 0x24 0x26 0x27 0x28 0x2A 0x37 0x38 0x00 0x02 0x03 0x04 0x05 0x07 0x09 0x0A MMC_GO_IDLE_STATE -- MMC_SEND_OP_COND -- MMC_ALL_SEND_CID -- MMC_SET_RELATIVE_ADDR -- MMC_SET_DSR -- MMC_RESERVED_5 -- MMC_SWITCH -- MMC_SELECT_DESELECT_CARD -- MMC_SEND_EXT_CSD -- MMC_SEND_CSD -- MMC_SEND_CID -- MMC_READ_DAT_UNTIL_STOP -- MMC_STOP_TRANSMISSION -- MMC_SEND_STATUS -- MMC_BUSTEST_R -- MMC_GO_INACTIVE_STATE -- MMC_SET_BLOCKLEN -- MMC_READ_SINGLE_BLOCK -- MMC_READ_MULTIPLE_BLOCK -- MMC_BUSTEST_W -- MMC_WRITE_DAT_UNTIL_STOP -- MMC_SET_BLOCK_COUNT -- MMC_WRITE_BLOCK -- MMC_WRITE_MULTIPLE_BLOCK -- MMC_PROGRAM_CID -- MMC_PROGRAM_CSD -- MMC_SET_WRITE_PROT -- MMC_CLR_WRITE_PROT -- MMC_SEND_WRITE_PROT -- MMC_ERASE_GROUP_START -- MMC_ERASE_GROUP_END -- MMC_ERASE -- MMC_FAST_IO -- MMC_GO_IRQ_STATE -- MMC_LOCK_UNLOCK -- MMC_APP_CMD -- MMC_GEN_CMD -- SD_GO_IDLE_STATE -- SD_ALL_SEND_CID -- SD_SEND_RELATIVE_ADDR -- SD_SET_DSR -- SD_IO_SEND_OP_COND -- SD_SELECT_DESELECT_CARD -- SD_SEND_CSD -- SD_SEND_CID -- i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1436 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) HW_SSP_CMD0 field descriptions (continued) Field Description 0x0C 0x0D 0x0F 0x10 0x11 0x12 0x18 0x19 0x1B 0x1C 0x1D 0x1E 0x20 0x21 0x23 0x24 0x26 0x2A 0x34 0x35 0x37 0x38 SD_STOP_TRANSMISSION -- SD_SEND_STATUS -- SD_GO_INACTIVE_STATE -- SD_SET_BLOCKLEN -- SD_READ_SINGLE_BLOCK -- SD_READ_MULTIPLE_BLOCK -- SD_WRITE_BLOCK -- SD_WRITE_MULTIPLE_BLOCK -- SD_PROGRAM_CSD -- SD_SET_WRITE_PROT -- SD_CLR_WRITE_PROT -- SD_SEND_WRITE_PROT -- SD_ERASE_WR_BLK_START -- SD_ERASE_WR_BLK_END -- SD_ERASE_GROUP_START -- SD_ERASE_GROUP_END -- SD_ERASE -- SD_LOCK_UNLOCK -- SD_IO_RW_DIRECT -- SD_IO_RW_EXTENDED -- SD_APP_CMD -- SD_GEN_CMD -- 17.10.3 SD/MMC Command Register 1 (HW_SSP_CMD1) SD/MMC Command Argument Register Address: 8001_0000h base + 20h offset = 8001_0020h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_ARG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_CMD1 field descriptions Field CMD_ARG Description SD/MMC Command Argument. See SSP_CTRL0_DATA_XFER bit description. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1437 Programmable Registers 17.10.4 Transfer Count Register (HW_SSP_XFER_SIZE) Transfer Count Register. Address: 8001_0000h base + 30h offset = 8001_0030h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 XFER_COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_XFER_SIZE field descriptions Field Description XFER_COUNT Number of words to transfer, as referenced in WORD_LENGTH in HW_SSP_CTRL1. The run bit and DMA request will clear after this many words have been transferred. In SD/MMC, this should be a multiple of the block size. 17.10.5 SD/MMC BLOCK SIZE and COUNT Register (HW_SSP_BLOCK_SIZE) SD/SDIO/MMC Multiple Block Size and Count Register. Address: 8001_0000h base + 40h offset = 8001_0040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RSVD0 R 0 0 0 16 15 14 13 12 11 10 9 8 7 6 5 4 BLOCK_COUNT W Reset 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 BLOCK_SIZE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_BLOCK_SIZE field descriptions Field 31-28 RSVD0 Description Reserved 27-4 SD/MMC block count. This value one less than the number of blocks to transfer. For example setting a BLOCK_COUNT value of one will transfer two blocks. This must satisfy equation HW_SSP_XFER_SIZE_XFER_COUNT = (1 shiftleft BLOCK_SIZE) x (BLOCK_COUNT+1) for BLOCK_COUNT greater than zero. This is also SPI/ SSI control word[15:8] for RX transfers. BLOCK_SIZE SD/MMC block size encode. When BLOCK_COUNT is nonzero, the actual block size is (1 shiftleft BLOCK_SIZE). For example setting a value of 9 will result in a block size of 512 bytes. When BLOCK_COUNT is zero, BLOCK_SIZE is ignored and HW_SSP_XFER_SIZE_XFER_COUNT represents the single block size or the number of byte to transfer. This must satisfy equation HW_SSP_XFER_SIZE_XFER_COUNT = (1 shiftleft BLOCK_SIZE) x (BLOCK_COUNT+1) for BLOCK_COUNT greater than zero. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1438 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 17.10.6 SD/MMC Compare Reference (HW_SSP_COMPREF) SD/MMC status can be compared with a reference value. Address: 8001_0000h base + 50h offset = 8001_0050h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFERENCE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_COMPREF field descriptions Field Description REFERENCE SD/MMC Compare mode reference. If CHECK_RESP is set, the response will be XOR'd with this value. The results will be masked by the MASK bitfield. If there are any differences, then the SSP will indicate an error state to the DMA. 17.10.7 SD/MMC compare mask (HW_SSP_COMPMASK) A mask allows the comparison of one or more bit fields in the reference value. Address: 8001_0000h base + 60h offset = 8001_0060h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_COMPMASK field descriptions Field MASK Description SD/MMC Compare mode Mask. If CHECK_RESP is set, the response is compared to REFERENCE, and the results are masked by this bitfield. 17.10.8 SSP Timing Register (HW_SSP_TIMING) SSP Timing Config Register The Timeout field and the clock dividers are contained in this register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1439 Programmable Registers Address: 8001_0000h base + 70h offset = 8001_0070h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 TIMEOUT 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 CLOCK_DIVIDE 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 CLOCK_RATE 0 0 0 0 0 0 0 0 HW_SSP_TIMING field descriptions Field 31-16 TIMEOUT Description Timeout counter. This specifies the number of SCK cycles multiplied by 4096, to wait before asserting the DATA TIMEOUT IRQ. It is used during timeout is used for data transfer/write operations in SD/MMC modes. 15-8 Clock Pre-Divider. CLOCK_DIVIDE must be an even value from 2 to 254. CLOCK_DIVIDE CLOCK_RATE Serial Clock Rate. The value CLOCK_RATE is used to generate the transmit and receive bit rate of the SSP. The bit rate is SSPCLK / (CLOCK_DIVIDE x (1+ CLOCK_RATE)). CLOCK_RATE is a value from 0 to 255. 17.10.9 SSP Control Register 1 (HW_SSP_CTRL1) Control Register 1. HW_SSP_CTRL1: 0x080 HW_SSP_CTRL1_SET: 0x084 HW_SSP_CTRL1_CLR: 0x088 HW_SSP_CTRL1_TOG: 0x08C This contains interrupt status and enable fields. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1440 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) Address: 8001_0000h base + 80h offset = 8001_0080h DATA_CRC_IRQ_EN FIFO_UNDERRUN_IRQ FIFO_UNDERRUN_EN RSVD2 RSVD1 RECV_TIMEOUT_IRQ RECV_TIMEOUT_IRQ_EN 16 DATA_CRC_IRQ 17 DATA_TIMEOUT_IRQ_EN 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLAVE_MODE 19 DATA_TIMEOUT_IRQ 20 POLARITY 21 RESP_TIMEOUT_IRQ_EN 22 PHASE 23 RESP_TIMEOUT_IRQ 24 SLAVE_OUT_DISABLE 25 RESP_ERR_IRQ_EN 26 RESP_ERR_IRQ 27 DMA_ENABLE 28 SDIO_IRQ_EN 29 FIFO_OVERRUN_IRQ_EN 30 SDIO_IRQ 31 FIFO_OVERRUN_IRQ Bit 0 0 0 0 0 0 0 R Reset Bit R RSVD0 W WORD_LENGTH SSP_MODE W Reset 0 1 0 0 0 0 0 0 0 HW_SSP_CTRL1 field descriptions Field 31 SDIO_IRQ Description If this is set, an SDIO card interrupt has occurred and an IRQ, if enabled, has been sent to the ICOLL. Write a one to the SCT Clear address to reset this interrupt request status bit. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1441 Programmable Registers HW_SSP_CTRL1 field descriptions (continued) Field 30 SDIO_IRQ_EN Description SDIO Card Interrupt IRQ Enable. 0: SDIO card IRQs masked. 1: SDIO card IRQs will be sent to the ICOLL. 29 When the CHECK_RESP bit in CTRL0 is set, if an unexpected response (or response CRC) is received RESP_ERR_IRQ from the card, this bit will be set. Write a one to the SCT Clear address to reset this interrupt request status bit. 28 RESP_ERR_ IRQ_EN SD/MMC Card Error IRQ Enable. 0: Card Error IRQ is Masked. 1: Card Error IRQ is enabled. When set to 1, if an SD/MMC card indicates a card error (bit is set in both the SD/MMC Error Mask and R1 Card Status response), then a CPU IRQ will be asserted. 27 RESP_ TIMEOUT_IRQ If this is set, a command response timeout has occurred, and an IRQ, if enabled, has been sent to the IRQ Collector. This is used for SD/MMC response timeout. Write a one to the SCT Clear address to reset this interrupt request status bit. 26 SD/MMC Card Command Respone Timeout Error IRQ Enable. 0: Response Timeout IRQ is Masked. 1: RESP_ Response Timeout IRQ is enabled. When set to 1, if an SD/MMC card does not respond to a command TIMEOUT_IRQ_ within 64 cycles, then this CPU IRQ will be asserted. EN 25 DATA_ TIMEOUT_IRQ Data Transmit/Receive Timeout Error IRQ. If the timeout counter expires before the DAT bus is ready for write or sends read data, then a data timeout has occurred. Only Valid For SD/MMC Modes. Write a one to the SCT Clear address to reset this interrupt request status bit. 24 Data Transmit/Receive Timeout Error IRQ Enable. If the timeout counter expires before the DAT bus is DATA_ ready for write or sends read data, then a data timeout has occurred. Only Valid For SD/MMC Modes. TIMEOUT_IRQ_ EN 23 Data Transmit/Receive CRC Error IRQ. Only valid for SD/MMC Modes. Write a one to the SCT Clear DATA_CRC_IRQ address to reset this interrupt request status bit. 22 DATA_CRC_ IRQ_EN Data Transmit/Receive CRC Error IRQ Enable. Only valid for SD/MMC Modes. 21 FIFO_ UNDERRUN_ IRQ FIFO Underrun Interrupt. If the FIFO is read when it is empty this bit will be set. Write a one to the SCT Clear address to reset this interrupt request status bit. 20 FIFO Underrun IRQ Enable. If set and the FIFO_UNDERRUN_IRQ bit is asserted, an IRQ will be FIFO_ generated. UNDERRUN_EN 19 RSVD2 Reserved 18 RSVD1 Reserved 17 RECV_ TIMEOUT_IRQ Data Timeout Interrupt. If enabled and the FIFO is not empty, an IRQ will be generated if 128 HCLK Cycles Pass before the DATA register is read. This is supported for SPI modes only (Modes 0,1,2). Write a one to the SCT Clear address to reset this interrupt request status bit. 16 Receive Timeout. If set and the FIFO is not empty, an IRQ will be generated if 128 HCLK Cycles Pass RECV_ before the DATA register is read. TIMEOUT_IRQ_ EN 15 FIFO Overrun Interrupt. Indicated that the FIFO has been written to while full. Write a one to the SCT FIFO_ Clear address to reset this interrupt request status bit. OVERRUN_IRQ Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1442 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) HW_SSP_CTRL1 field descriptions (continued) Field Description 14 FIFO Overrun Interrupt Enable. If set, an IRQ will be generated if the FIFO is written to while full. FIFO_ OVERRUN_IRQ_ EN 13 DMA_ENABLE 12 RSVD0 DMA Enable. This signal enables DMA request and DMA Command End signals to be asserted. Reserved 11 SLAVE_OUT_ DISABLE 10 PHASE Slave Output Disable. 0: SSP can drive MISO in Slave Mode. 1: SSP does not drive MISO in slave mode. Serial Clock Phase. For SPI mode only. 9 POLARITY Serial Clock Polarity. In SD/MMC mode, 0: Command and TX data change after rising edge of SCK. In SPI mode, 0: Steady-state '0' on SCK when data is not being transferred. 1: Steady-state '1' on SCK when data is not being transferred. 8 SLAVE_MODE Slave Mode. 0: SSP is in Master Mode. 1: SSP is in Slave Mode. Set to zero for SD/MMC modes. 7-4 Word Length in bits per word. 0x0 to 0x2 are Reserved and Undefined. 0x3 is 4-bits per word...0xF is 16WORD_LENGTH bits per word. Always use 8 bits per word in SD/MMC Modes. FOUR_BITS -- use 4-bits per word EIGHT_BITS -- use 8-bits per word SIXTEEN_BITS -- use 16-bits per word Other values -- Reserved and Undefined 0x3 0x7 0xF SSP_MODE Operating Mode. 0x0 = Motorola and Winbond SPI Mode, 0x1 = TI syncronous serial mode, 0x3 = SD/ MMC Card. All other values are undefined. Before changing ssp_mode, a softreset must be issued to clear the FIFO. SPI -- Motorola and Winbond SPI mode SSI -- Texas Instruments SSI mode SD_MMC -- SD/MMC mode -- 0x0 0x1 0x3 17.10.10 SSP Data Register (HW_SSP_DATA) The HW_SSP_DATA register allows user access to the SSP FIFO. This register is the gateway for data transfer to and from the attached device. Address: 8001_0000h base + 90h offset = 8001_0090h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1443 Programmable Registers HW_SSP_DATA field descriptions Field Description DATA Data Register. Holds one, two, three, or four words, depending on the WORD_LENGTH. If WORD_LENGTH is not 8, 16, or 32, the words are padded to those lengths. Data is right justified. When the run bit is set reads will cause the FIFO read pointer to increment and writes will cause the FIFO write pointer to increment. 17.10.11 SD/MMC Card Response Register 0 (HW_SSP_SDRESP0) SD/SDIO/MMC Card Response Register 0. Address: 8001_0000h base + A0h offset = 8001_00A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESP0 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_SDRESP0 field descriptions Field Description RESP0 SD/MMC Response Status Bits[31:0]. See SSP_CTRL0_DATA_XFER bit description. 17.10.12 SD/MMC Card Response Register 1 (HW_SSP_SDRESP1) SD/SDIO/MMC Card Response Register 1. Address: 8001_0000h base + B0h offset = 8001_00B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESP1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_SDRESP1 field descriptions Field RESP1 Description SD/MMC Long Response [63:32] i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1444 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 17.10.13 SD/MMC Card Response Register 2 (HW_SSP_SDRESP2) SD/SDIO/MMC Card Response Register 2. Address: 8001_0000h base + C0h offset = 8001_00C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESP2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_SDRESP2 field descriptions Field Description RESP2 SD/MMC Long Response [95:64] 17.10.14 SD/MMC Card Response Register 3 (HW_SSP_SDRESP3) SD/SDIO/MMC Card Response Register 3. Address: 8001_0000h base + D0h offset = 8001_00D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESP3 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_SDRESP3 field descriptions Field RESP3 Description SD/MMC Long Response [127:96] 17.10.15 SD/MMC Double Data Rate Control Register (HW_SSP_DDR_CTRL) SD/MMC Double Data Rate Control Register. This register provides programmability in DDR mode for data output timing and data formats. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1445 Programmable Registers Address: 8001_0000h base + E0h offset = 8001_00E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD0 R DMA_ BURST_ TYPE Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCLK_DELAY_TYPE Reset NIBBLE_POS W 0 0 0 0 0 0 0 0 RSVD0 R W Reset 0 0 0 0 0 0 0 0 HW_SSP_DDR_CTRL field descriptions Field 31-30 DMA_BURST_ TYPE 29-2 RSVD0 1 NIBBLE_POS Description The field controls the number of APB transfers per DMA request. 2'b00: select one APB transfer per DMA request 2'b01: select 4 APB transfers per DMA request. 2'b10: select 8 APB transfers per DMA request. 2'b11: reserved Reserved This bit only applies in MMC 4-bit DDR transfers. 0: The two high nibbles of two odd and even bytes are sent/received on a cycle(both edges), then the low nibbles of the odd and even bytes are sent/received on the next cycle. 1: Two nibbles of every bytes are sent/received on a cycle. 0 This field specifies two delay methods of delaying SCK related to SSP TX data to serve the purpose of TXCLK_DELAY_ obtaining better TX data setup time. Set this bit to 0 to choose the pre-set gate delay, which is TYPE approximately 5ns; set this bit to 1 to choose the SCK-coupled delay, which is 1/4 of SCK period. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1446 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 17.10.16 SD/MMC DLL Control Register (HW_SSP_DLL_CTRL) SD/MMC Delay Loop Lock Control Register. This register provides programmability in DDR mode for data input timing and data formats. Address: 8001_0000h base + F0h offset = 8001_00F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD1 R REF_UPDATE_INT SLV_UPDATE_INT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET ENABLE 0 0 0 SLV_OVERRIDE R SLV_OVERRIDE_VAL GATE_UPDATE Bit 0 RSVD0 Reset SLV_FORCE_UPD W SLV_DLY_TARGET W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_DLL_CTRL field descriptions Field Description 31-28 This field allows the user to add additional delay cycles to the DLL control loop (reference delay line REF_UPDATE_ control). By default, the DLL control loop shall update every two SSPCLK cycles. Programming this field INT results in a DLL control loop update interval of (2 + REF_UPDATE_INT) * SSPCLK. It should be noted Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1447 Programmable Registers HW_SSP_DLL_CTRL field descriptions (continued) Field Description that increasing the reference delay-line update interval reduces the ability of the DLL to adjust to fast changes in conditions that may effect the delay (such as voltage and temperature) 27-20 Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256 SLV_UPDATE_ SSPCLK cycles. A value of 0 results in an update interval of 256 SSPCLK cycles (default setting). A value INT of 0x0f results in 15 cycles and so on. Note that software can always cause an update of the slave-delay line using the SLV_FORCE_UPDATE register. Note that the slave delay line will also update automatically when the reference DLL transitions to a locked state (from an un-locked state). 19-16 RSVD1 Reserved 15-10 When SLV_OVERRIDE=1 This field is used to select 1 of 64 physical taps manually. A value of 0 selects SLV_ tap 1, and a value of 0x3f selects tap 64. OVERRIDE_VAL 9 Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to SLV_OVERRIDE disable manual override. This feature does not require the DLL to tbe enabled using the ENABLE bit. In fact to reduce power, if SLV_OVERRIDE is used, it is recommended to disable the DLL with ENABLE=0 8 RSVD0 Reserved 7 Setting this bit to 1, forces the slave delay line not update GATE_UPDATE 6-3 SLV_DLY_ TARGET The delay target for the SSP read clock is can be programmed in 1/16th increments of an SSPCLK halfperiod. So the input read-clock can be delayed relative input data from (SSPCLK/2)/16 to SSPCLK/2. 2 SLV_FORCE_ UPD Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately. The slave delay line shall update automatically based on the SLV_UPDATE_INT interval or when a DLL lock condition is sensed. Subsequent forcing of the slave-line update can only occur if SLV_FORCE_UP is set back to 0 and then asserted again (edge triggered). 1 RESET Setting this bit to 1 force a reset on DLL. This will cause the DLL to lose lock and re-calibrate to detect an SSPCLK half period phase shift. This signal is used by the DLL as edge-sensitive, so in order to create a subsequent reset, RESET must be taken low and then asserted again. 0 ENABLE Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL. Note that using the slave delay line override feature with SLV_OVERRIDE and SLV_OVERRIDE VAL, the DLL does not need to be enabled. 17.10.17 SSP Status Register (HW_SSP_STATUS) SSP Read Only Status Registers. Various SSP status fields are provided in this register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1448 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 23 0 0 RSVD3 22 21 20 19 18 17 16 RESP_CRC_ERR 0 24 SDIO_IRQ 1 25 DMAEND 1 26 DMAREQ CARD_DETECT 1 27 DMATERM 28 DMASENSE 29 DMABURST 30 SD_PRESENT R 31 RSVD4 Bit PRESENT Address: 8001_0000h base + 100h offset = 8001_0100h 0 0 0 0 0 0 0 W Reset 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1449 8 TIMEOUT RECV_TIMEOUT_STAT RSVD2 FIFO_OVRFLW FIFO_FULL 0 0 0 0 0 0 0 0 7 6 RSVD1 5 4 3 2 1 0 BUSY 9 RSVD0 10 DATA_BUSY 11 CMD_BUSY 12 FIFO_UNDRFLW 13 FIFO_EMPTY 14 DATA_CRC_ERR R 15 RESP_TIMEOUT Bit RESP_ERR Programmable Registers 1 0 0 0 0 0 W Reset 0 0 HW_SSP_STATUS field descriptions Field 31 PRESENT 30 RSVD4 29 SD_PRESENT Description SSP Present Bit. 0: SSP is not present in this product. 1: SSP is present. Reserved SD/MMC Controller Present bit. 0: SD/MMC controller is not present in this product. 1: SD/MMC controller is present. 28 Reflects the state of the SSP_DETECT input pin. CARD_DETECT 27-23 RSVD3 Reserved 22 DMABURST Reflects the state of the ssp_dmaburst output port. 21 DMASENSE Reflects the state of the ssp_dmasense output port. It indicates a DMA error (Timeout or CRC) when asserted high at the end of a DMA command. 20 DMATERM Reflects the state of the ssp_dmaterm output port. This is a toggle signal. 19 DMAREQ Reflects the state of the ssp_dmareq output port. This is a toggle signal. 18 DMAEND Reflects the state of the ssp_dmaend output port. This is a toggle signal. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1450 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) HW_SSP_STATUS field descriptions (continued) Field 17 SDIO_IRQ 16 RESP_CRC_ ERR 15 RESP_ERR Description SDIO IRQ has been detected. SD/MMC Response failed CRC check. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN. SD/MMC Card Responsed to Command with an Error Condition. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN. 14 SD/MMC Card Expected Command Response not received within 64 CLK cycles. This indicates a card RESP_TIMEOUT error, bad command, or command that failed CRC check. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN. 13 DATA_CRC_ ERR 12 TIMEOUT Data CRC Error. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN. SD/MMC - timeout counter expired before data bus was ready. This bit is cleared with soft reset or the rising edge of HW_SSP_CTRL0_RUN. 11 Raw Receive Timeout Status. Indicates that no read has occurred to non-empty receive data FIFO for 128 RECV_ cycles TIMEOUT_STAT 10 RSVD2 Reserved 9 FIFO Overflow Interrupt. FIFO_OVRFLW 8 FIFO_FULL 7-6 RSVD1 5 FIFO_EMPTY FIFO FULL Reserved FIFO Empty. 4 FIFO Underflow has occurred. FIFO_UNDRFLW 3 CMD_BUSY SD/MMC command controller is busy sending a command or receiving a response 2 DATA_BUSY SD/MMC command controller is busy transferring data. 1 RSVD0 0 BUSY Reserved SSP State Machines are Busy. 17.10.18 SD/MMC DLL Status Register (HW_SSP_DLL_STS) SSP Read Only Status Registers. SSP DLL status fields are provided in this register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1451 Programmable Registers Address: 8001_0000h base + 110h offset = 8001_0110h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD0 R Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLV_LOCK Reset REF_LOCK W 0 0 0 0 RSVD0 REF_SEL SLV_SEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_DLL_STS field descriptions Field 31-14 RSVD0 Description Reserved 13-8 REF_SEL Reference delay line select status. 7-2 SLV_SEL Slave delay line select status 1 REF_LOCK Reference DLL lock status. This signifies that the DLL has detected and locked to a half-phase SSPCLK shift, allowing the slave delay-line to perform programmed clock delays. 0 SLV_LOCK Slave delay-line lock status. This signifies that a valid calibration has been set to the slave-delay line and that the slave-delay line is implementing the programmed delay value. 17.10.19 SSP Debug Register (HW_SSP_DEBUG) SSP Read Only Debug Registers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1452 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) Debug Register provide access to State machines. Address: 8001_0000h base + 120h offset = 8001_0120h 30 29 28 DATACRC_ERR R 27 26 25 24 23 DAT_SM 22 21 20 19 18 CMD_OE 31 DATA_STALL Bit RSVD1 17 16 DMA_SM Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSP_RESP Reset SSP_CMD W 0 0 0 0 0 MMC_SM R CMD_SM SSP_RXD W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_DEBUG field descriptions Field Description 31-28 Data CRC error DATACRC_ERR 27 DATA_STALL MMC mode: FIFO transfer not ready Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1453 Programmable Registers HW_SSP_DEBUG field descriptions (continued) Field 26-24 DAT_SM 23-20 RSVD1 Description MMC dataxfer state machine 0x0 0x2 0x3 0x4 0x5 DSM_IDLE -- DSM_WORD -- DSM_CRC1 -- DSM_CRC2 -- DSM_END -- Reserved 19 CMD_OE Enable for SSP_CMD 18-16 DMA_SM DMA state machine 15-12 MMC_SM MMC_state machine 11-10 CMD_SM MMC command_state machine 9 SSP_CMD SSP_CMD 8 SSP_RESP SSP_RESP SSP_RXD SSP_RXD. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0x0 0x1 0x2 0x3 DMA_IDLE -- DMA_DMAREQ -- DMA_DMAACK -- DMA_STALL -- DMA_BUSY -- DMA_DONE -- DMA_COUNT -- MMC_IDLE -- MMC_CMD -- MMC_TRC -- MMC_RESP -- MMC_RPRX -- MMC_TX -- MMC_CTOK -- MMC_RX -- MMC_CCS -- MMC_PUP -- MMC_WAIT -- CSM_IDLE -- CSM_INDEX -- CSM_ARG -- CSM_CRC -- i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1454 Freescale Semiconductor, Inc. Chapter 17 Synchronous Serial Ports (SSP) 17.10.20 SSP Version Register (HW_SSP_VERSION) This register reflects the version number for the SSP. Address: 8001_0000h base + 130h offset = 8001_0130h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SSP_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1455 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1456 Freescale Semiconductor, Inc. Chapter 18 Boundary Scan Interface 18.1 Boundary Scan Interface This chapter describes the boundary scan feature that has been implemented on the i.MX28. This feature is provided to enable board level testing. There are five pins on the device which are used to implement the IEEE 1149.1 boundary scan protocol. In order to make use of the boundary scan functionality, an extra pin called DEBUG must be tied to low. The following table shows the pin information that is used to implement boundary scan. Table 18-1. Boundary Scan Pin Functions Name of Pin Function Direction TCK This is the clock that is used to serially shift data in to the part. Input TMS This signal is used to select the test mode. Input TDI This is the serial data that is used to shift in data into the boundary scan Input register. It is also be used to shift in instructions into the instruction register and data into the I/O configuration register. TRST_N This is the reset signal for the block. Input TDO This is the output of the boundary scan chain. Output DEBUG This is the selection for the JTAG interface. Input DEBUG=0: JTAG interface works for boundary scan. DEBUG=1: JTAG interface works for ARM debugging. This chapter does not cover ARM Debugging. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1457 Boundary Scan Interface There are six instructions implemented in the boundary scan design. The following table describes these instructions: Table 18-2. Boundary Scan Instruction Set Instruction Code Description EXTEST 0000 This instruction places the IC into an external boundary-test mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundaryscan register is accessed to drive test data off-chip through the boundary outputs and receive test data off-chip through the boundary inputs. SAMPLE/PRELOAD 0001 This instruction takes the data on the I/O pad and latches it into the boundary scan register. BYPASS 1111 This instruction is used to bypass the chip during board testing. IDCODE 0010 This instruction allows a code to be serially read from the component. The Chip level JTAG ID Code of i.MX28 is 0x0882401D. HIGHZ 0011 This instruction places the component in a state, in which all of its system logic outputs are placed in an inactive drive state. IOCFG 0101 This user-defined instruction is used to program the voltage level of pins. There is a special instruction which is called IOCFG that is implemented to load the I/O configuration register. The I/O configuration register is used to program the voltage levels of pins. It has 126 bits, corresponding to the 126 GPIO pins in the device. If there is a 0 in a certain bit location, then the GPIO corresponding to that location will be programmed to a 1.8 V level. The default value, which is 1, corresponds to a pin being programmed to a 3.3 V level. This register is provided so that the pins that are connected to 1.8 V peripherals can be programmed to the correct voltage level before running the board level tests. The customer will be provided a BSDL file which is in a format that is used by the board tester. This file will detail the sequence of the pad connection in the boundary scan chain, and the properties of the pads. This is used by the board level tester to develop the tests for connectivity of the chip. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1458 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM 19.1 Overview The digital control block provides overall control of various items within the top digital block of the chip, including: * Default first-level page table (DFLPT) controls * HCLK performance counter * Free-running microseconds counter * Entropy control * BIST controls for ARM Core and On-Chip RAM * Chip Revision register * USB loop back congtrol * Other miscellaneous controls The detailed diagram is shown below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1459 SRAM Controls ARM Core SRAM EMI AXIS AHB Bridge AHB APB Bridge Shared APBX DMA AHB-to-APBH Bridge APBH APBH Master Revision On-Chip OTP Controller PIO Programmable Registers Performance Monitos AHB Arbiter Entropy DIGCTL PSWITCH Default FirstLevel Page Table OCRAM_CTRL Figure 19-1. Digital Control (DIGCTL) Block Diagram 19.2 SRAM Controls The on-chip 128 KB RAM is comprised of four physical banks of 8Kx32-bit each. The architecture requires a 4-port, word interleaved topology to maximize the performance in a multi-layer bus system. A diagrammatic representation of the word-interleaving is shown below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1460 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM 31 0 0x0000_0000 0x0000_0010 . . . . Bank 3 0x0000_0004 0x0000_0014 . . . . Bank 2 0x0000_0008 0x0000_0018 . . . . Bank 1 0x0000_000C 0x0000_001C . . . . Bank 0 Figure 19-2. On-Chip RAM Partitioning A 32-bit AHB address is arranged as shown below. Table 19-1. On-Chip RAM Address Bits AHB ADDR BITS USAGE DESCRIPTION 16:4 Address Selects one of 8 K words in a bank. 3:2 Bank Address Selects 1 of 4 physical 32 KB banks. 1:0 Byte Address Selects/masks out specific bytes within a word. The on-chip RAM and controller work at full CLK_H frequency without additional wait states. There is no memory repair for the SRAM. 19.3 Miscellaneous Controls The digital control block also contains a number of other miscellaneous functions, as detailed in this section. 19.3.1 Performance Monitoring The digital control block contains several registers for system bus performance monitoring, including HW_DIGCTL_HCLKCOUNT, which counts HCLK rising edges. This register counts at a variable rate as HW_CLKCTRL_HBUS_AUTO_SLOW_ MODE is enabled. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1461 Programmable Registers In addition, there exists a performance monitoring register for each AHB layer (L0-L3). The HW_DIGCTL_L(n)_AHB_DATA_STALLED and HW_DIGCTL_L(n)_AHB_ACTIVE_CYCLES registers can be used to measure AHB bus utilization. The Stalled register counts all cycles in which any device has an outstanding and unfulfilled bus operation in flight. The Active Cycles register counts the number of data transfer cycles. Subtract cycles from stalls to determine under utilized bus cycles. These counters can be used to tune the performance of the HCLK frequency for specific activities. In addition, these monitors can be forced to focus on specific masters (which connect to that layer). See the HW_DIGCTL_AHB_STATS_SELECT bit description for details. 19.3.2 High-Entropy PRN Seed A 32-bit entropy register begins running a pseudo-random number algorithm from the time reset is removed until the PSWITCH is released by the user. This high-entropy value can be used as the seed for other pseudo-random number generators. 19.3.3 Write-Once Register A 32-bit write-once register holds a runtime-derived locked seed. Once written, it cannot be changed until the next chip wide reset event. The contents of this register are frequently derived from the entropy register. 19.3.4 Microseconds Counter A 32-bit free-running microseconds counter provides fine-grain real-time control. Its period is determined by dividing the 24.0-MHz crystal oscillator by 24. Therefore, its frequency does not change as HCLK, XCLK, and the processor clock frequency are changed. 19.4 Programmable Registers DIGCTL Register Format Summary i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1462 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 0001_0004h 19.4.1/1465 8001_C000 DIGCTL Control Register (HW_DIGCTL_CTRL) 32 R/W 8001_C010 DIGCTL Status Register (HW_DIGCTL_STATUS) 32 R FF00_0000h 19.4.2/1469 8001_C020 Free-Running HCLK Counter Register (HW_DIGCTL_HCLKCOUNT) 32 R 0000_0000h 19.4.3/1472 8001_C030 On-Chip RAM Control Register (HW_DIGCTL_RAMCTRL) 32 R/W 0000_0000h 19.4.4/1473 8001_C040 EMI Status Register (HW_DIGCTL_EMI_STATUS) 32 R 0000_0000h 19.4.5/1474 8001_C050 On-Chip Memories Read Margin Register (HW_DIGCTL_READ_MARGIN) 32 R/W 0000_0002h 19.4.6/1475 8001_C060 Software Write-Once Register (HW_DIGCTL_WRITEONCE) 32 R/W A5A5_A5A5h 19.4.7/1476 8001_C070 BIST Control Register (HW_DIGCTL_BIST_CTL) 32 R/W 4000_0000h 19.4.8/1476 8001_C080 DIGCTL Status Register (HW_DIGCTL_BIST_STATUS) 32 R 0000_0000h 19.4.9/1479 8001_C090 Entropy Register (HW_DIGCTL_ENTROPY) 32 R 0000_0000h 19.4.10/ 1483 8001_C0A0 Entropy Latched Register (HW_DIGCTL_ENTROPY_LATCHED) 32 R 0000_0000h 19.4.11/ 1484 8001_C0C0 Digital Control Microseconds Counter Register (HW_DIGCTL_MICROSECONDS) 32 R/W 0000_0000h 19.4.12/ 1484 8001_C0D0 Digital Control Debug Read Test Register (HW_DIGCTL_DBGRD) 32 R 789A _BCDEh 19.4.13/ 1485 8001_C0E0 Digital Control Debug Register (HW_DIGCTL_DBG) 32 R 8765_4321h 19.4.14/ 1485 8001_C100 USB LOOP BACK (HW_DIGCTL_USB_LOOPBACK) 32 R/W 0000_0000h 19.4.15/ 1486 8001_C110 SRAM Status Register 0 (HW_DIGCTL_OCRAM_STATUS0) 32 R 0000_0000h 19.4.16/ 1488 8001_C120 SRAM Status Register 1 (HW_DIGCTL_OCRAM_STATUS1) 32 R 0000_0000h 19.4.17/ 1489 8001_C130 SRAM Status Register 2 (HW_DIGCTL_OCRAM_STATUS2) 32 R 0000_0000h 19.4.18/ 1489 8001_C140 SRAM Status Register 3 (HW_DIGCTL_OCRAM_STATUS3) 32 R 0000_0000h 19.4.19/ 1490 8001_C150 SRAM Status Register 4 (HW_DIGCTL_OCRAM_STATUS4) 32 R 0000_0000h 19.4.20/ 1491 8001_C160 SRAM Status Register 5 (HW_DIGCTL_OCRAM_STATUS5) 32 R 0000_0000h 19.4.21/ 1491 8001_C170 SRAM Status Register 6 (HW_DIGCTL_OCRAM_STATUS6) 32 R 0000_0000h 19.4.22/ 1492 8001_C180 SRAM Status Register 7 (HW_DIGCTL_OCRAM_STATUS7) 32 R 0000_0000h 19.4.23/ 1493 8001_C190 SRAM Status Register 8 (HW_DIGCTL_OCRAM_STATUS8) 32 R 0000_0000h 19.4.24/ 1493 8001_C1A0 SRAM Status Register 9 (HW_DIGCTL_OCRAM_STATUS9) 32 R 0000_0000h 19.4.25/ 1494 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1463 Programmable Registers HW_DIGCTL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8001_C1B0 SRAM Status Register 10 (HW_DIGCTL_OCRAM_STATUS10) 32 R 0000_0000h 19.4.26/ 1495 8001_C1C0 SRAM Status Register 11 (HW_DIGCTL_OCRAM_STATUS11) 32 R 0000_0000h 19.4.27/ 1496 8001_C1D0 SRAM Status Register 12 (HW_DIGCTL_OCRAM_STATUS12) 32 R 0000_0000h 19.4.28/ 1496 8001_C1E0 SRAM Status Register 13 (HW_DIGCTL_OCRAM_STATUS13) 32 R 0000_0000h 19.4.29/ 1498 8001_C280 Digital Control Scratch Register 0 (HW_DIGCTL_SCRATCH0) 32 R/W 0000_0000h 19.4.30/ 1499 8001_C290 Digital Control Scratch Register 1 (HW_DIGCTL_SCRATCH1) 32 R/W 0000_0000h 19.4.31/ 1499 8001_C2A0 Digital Control ARM Cache Register (HW_DIGCTL_ARMCACHE) 32 R/W 0000_0000h 19.4.32/ 1500 8001_C2B0 Debug Trap Control and Status for AHB Layer 0 and 3 (HW_DIGCTL_DEBUG_TRAP) 32 R/W 0000_0000h 19.4.33/ 1501 8001_C2C0 Debug Trap Range Low Address for AHB Layer 0 (HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW) 32 R/W 0000_0000h 19.4.34/ 1503 8001_C2D0 Debug Trap Range High Address for AHB Layer 0 (HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH) 32 R/W 0000_0000h 19.4.35/ 1504 8001_C2E0 Debug Trap Range Low Address for AHB Layer 3 (HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW) 32 R/W 0000_0000h 19.4.36/ 1504 8001_C2F0 Debug Trap Range High Address for AHB Layer 3 (HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH) 32 R/W 0000_0000h 19.4.37/ 1505 8001_C300 Freescale Copyright Identifier Register (HW_DIGCTL_FSL) 32 R 6565_7246h 19.4.38/ 1505 8001_C310 Digital Control Chip Revision Register (HW_DIGCTL_CHIPID) 32 R 2800_0000h 19.4.39/ 1506 8001_C330 AHB Statistics Control Register (HW_DIGCTL_AHB_STATS_SELECT) 32 R/W 0000_0000h 19.4.40/ 1507 8001_C370 AHB Layer 1 Transfer Count Register (HW_DIGCTL_L1_AHB_ACTIVE_CYCLES) 32 R/W 0000_0000h 19.4.41/ 1508 8001_C380 AHB Layer 1 Performance Metric for Stalled Bus Cycles Register (HW_DIGCTL_L1_AHB_DATA_STALLED) 32 R/W 0000_0000h 19.4.42/ 1508 8001_C390 AHB Layer 1 Performance Metric for Valid Bus Cycles Register (HW_DIGCTL_L1_AHB_DATA_CYCLES) 32 R/W 0000_0000h 19.4.43/ 1509 8001_C3A0 AHB Layer 2 Transfer Count Register (HW_DIGCTL_L2_AHB_ACTIVE_CYCLES) 32 R/W 0000_0000h 19.4.44/ 1510 8001_C3B0 AHB Layer 2 Performance Metric for Stalled Bus Cycles Register (HW_DIGCTL_L2_AHB_DATA_STALLED) 32 R/W 0000_0000h 19.4.45/ 1510 8001_C3C0 AHB Layer 2 Performance Metric for Valid Bus Cycles Register (HW_DIGCTL_L2_AHB_DATA_CYCLES) 32 R/W 0000_0000h 19.4.46/ 1511 8001_C3D0 AHB Layer 3 Transfer Count Register (HW_DIGCTL_L3_AHB_ACTIVE_CYCLES) 32 R/W 0000_0000h 19.4.47/ 1512 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1464 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8001_C3E0 AHB Layer 3 Performance Metric for Stalled Bus Cycles Register (HW_DIGCTL_L3_AHB_DATA_STALLED) 32 R/W 0000_0000h 19.4.48/ 1512 8001_C3F0 AHB Layer 3 Performance Metric for Valid Bus Cycles Register (HW_DIGCTL_L3_AHB_DATA_CYCLES) 32 R/W 0000_0000h 19.4.49/ 1513 8001_C500 Default First Level Page Table Movable PTE Locator 0 (HW_DIGCTL_MPTE0_LOC) 32 R/W 0000_0000h 19.4.50/ 1513 8001_C510 Default First-Level Page Table Movable PTE Locator 1 (HW_DIGCTL_MPTE1_LOC) 32 R/W 0000_0001h 19.4.51/ 1514 8001_C520 Default First-Level Page Table Movable PTE Locator 2 (HW_DIGCTL_MPTE2_LOC) 32 R/W 0000_0002h 19.4.52/ 1515 8001_C530 Default First-Level Page Table Movable PTE Locator 3 (HW_DIGCTL_MPTE3_LOC) 32 R/W 0000_0003h 19.4.53/ 1516 8001_C540 Default First-Level Page Table Movable PTE Locator 4 (HW_DIGCTL_MPTE4_LOC) 32 R/W 0000_0004h 19.4.54/ 1517 8001_C550 Default First-Level Page Table Movable PTE Locator 5 (HW_DIGCTL_MPTE5_LOC) 32 R/W 0000_0005h 19.4.55/ 1518 8001_C560 Default First-Level Page Table Movable PTE Locator 6 (HW_DIGCTL_MPTE6_LOC) 32 R/W 0000_0006h 19.4.56/ 1519 8001_C570 Default First-Level Page Table Movable PTE Locator 7 (HW_DIGCTL_MPTE7_LOC) 32 R/W 0000_0007h 19.4.57/ 1520 8001_C580 Default First-Level Page Table Movable PTE Locator 8 (HW_DIGCTL_MPTE8_LOC) 32 R/W 0000_0008h 19.4.58/ 1521 8001_C590 Default First-Level Page Table Movable PTE Locator 9 (HW_DIGCTL_MPTE9_LOC) 32 R/W 0000_0009h 19.4.59/ 1522 8001_C5A0 Default First-Level Page Table Movable PTE Locator 10 (HW_DIGCTL_MPTE10_LOC) 32 R/W 0000_000Ah 19.4.60/ 1522 8001_C5B0 Default First-Level Page Table Movable PTE Locator 11 (HW_DIGCTL_MPTE11_LOC) 32 R/W 0000_000Bh 19.4.61/ 1523 8001_C5C0 Default First-Level Page Table Movable PTE Locator 12 (HW_DIGCTL_MPTE12_LOC) 32 R/W 0000_000Ch 19.4.62/ 1524 8001_C5D0 Default First-Level Page Table Movable PTE Locator 13 (HW_DIGCTL_MPTE13_LOC) 32 R/W 0000_000Dh 19.4.63/ 1525 8001_C5E0 Default First-Level Page Table Movable PTE Locator 14 (HW_DIGCTL_MPTE14_LOC) 32 R/W 0000_000Eh 19.4.64/ 1526 8001_C5F0 Default First-Level Page Table Movable PTE Locator 15 (HW_DIGCTL_MPTE15_LOC) 32 R/W 0000_000Fh 19.4.65/ 1527 19.4.1 DIGCTL Control Register (HW_DIGCTL_CTRL) The DIGCTL Control Register provides overall control of various functions throughout the digital portion of the chip. HW_DIGCTL_CTRL: 0x000 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1465 Programmable Registers HW_DIGCTL_CTRL_SET: 0x004 HW_DIGCTL_CTRL_CLR: 0x008 HW_DIGCTL_CTRL_TOG: 0x00C EXAMPLE HW_DIGCTL_CTRL_CLR(BM_DIGCTL_CTRL_USB_CLKGATE); // enable USB clock 22 21 20 19 18 17 16 USB1_CLKGATE 0 23 DIGITAL_TESTMODE 0 RSVD2 24 ANALOG_TESTMODE 25 USB0_TESTMODE 26 USB1_TESTMODE 27 USB0_OVERCURRENT_POL 28 USB1_OVERCURRENT_POL 29 USB0_OVERCURRENT_ENABLE R 30 XTAL24M_GATE 31 RSVD3 Bit USB1_OVERCURRENT_ENABLE Address: 8001_C000h base + 0h offset = 8001_C000h 0 0 0 0 0 0 0 0 1 W Reset 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1466 Freescale Semiconductor, Inc. 0 10 9 8 7 6 5 4 0 0 3 2 1 0 LATCH_ENTROPY 0 11 JTAG_SHIELD AUART01_LOOPBACK 0 12 USB0_CLKGATE DUART_LOOPBACK 13 SAIF_LOOPBACK R 14 RSVD1 15 Bit DEBUG_DISABLE Chapter 19 Digital Control (DIGCTL) and On-Chip RAM 0 1 0 0 RSVD0 SAIF_ CLKMUX_ SEL W Reset 0 0 0 0 0 0 0 HW_DIGCTL_CTRL field descriptions Field 31 RSVD3 Description Reserved. 30 If set to 1, disable the Digital Control Microseconds counter, STRB1MHZ. If set to 0, enable the Digital XTAL24M_GATE Control Microseconds counter.. 29-25 RSVD2 Reserved. 24 0 - Disable the overcurrent detection logic (default) USB1_ 1 - Enable the overcurrent detection logic OVERCURRENT_ ENABLE 23 0 - Disable the overcurrent detection logic (default) USB0_ 1 - Enable the overcurrent detection logic OVERCURRENT_ ENABLE 22 0 - The external Over Current indicator signal is high active.(default) USB1_ 1 - The external Over Current indicator signal is low active. OVERCURRENT_ POL 21 0 - The external Over Current indicator signal is high active.(default) USB0_ 1 - The external Over Current indicator signal is low active. OVERCURRENT_ POL Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1467 Programmable Registers HW_DIGCTL_CTRL field descriptions (continued) Field Description 20 USB1_ TESTMODE Set this bit to get into USB1 test mode 19 USB0_ TESTMODE Set this bit to get into USB0 test mode 18 ANALOG_ TESTMODE Set this bit to get into analog test mode 17 DIGITAL_ TESTMODE Set this bit to get into digital test mode 16 This bit must be cleared to 0 for normal operation of the USB controller. When set to 1, it gates off the USB1_CLKGATE clocks to the USB controller. USB_CLKGATE can be set during suspend to gate the USB clock during suspend. If this is gated, then the USB controller Reset Received bit (HW_USBCTRL_USBSTS_URI) should be not be polled for reset during suspend; use the HW_USBPHY_CTRL_RESUME_IRQ bit instead. This bit can be hardware auto cleared when wakeup from suspend happens 0x0 0x1 RUN -- Allow USB to operate normally. NO_CLKS -- Do not clock USB gates in order to minimize power consumption. 15 Set this bit to one to loop SAIF0 to SAIF1 and SAIF1 to SAIF0. To use SAIF loopback the user must SAIF_LOOPBACK configure one SAIF for transmit and the other for receive. Because this bit connects SAIF0's output to SAIF1's input, and SAIF1's output to SAIF0's input it doesn't matter which of the two ports is configured for TX and the other for RX, either configuration will produce an internal TX to RX loopback. 0x0 0x1 NORMAL -- No loopback. LOOPIT -- Loop SAIF0 and SAIF1 back to each other. 14 DUART_ LOOPBACK Set this bit to one to loop the debug UART's RX and TX signals back on themselves in a null modem configuration. 13 AUART01_ LOOPBACK Set this bit to one to loop application UARTs 0 and 1 back on themselves in a null modem configuration. 12 RSVD1 0x0 0x1 0x0 0x1 NORMAL -- No loopback. LOOPIT -- Loop debug UART TX and RX together. NORMAL -- No loopback. LOOPIT -- Loop application UART 0 and 1 together. Reserved. 11-10 Selects the source of the SAIF0 and SAIF1 input bit clock (BITCLK), and input left/right sample clock SAIF_CLKMUX_ (LRCLK). SEL 0x0 DIRECT -- SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1 clock pins selected for SAIF1 input clocks. 0x1 CROSSINPUT -- SAIF1 clock inputs selected for SAIF0 input clocks, and SAIF0 clock inputs selected for SAIF1 input clocks. This is the cross input mode. 0x2 CLKSRCSAIF0PIN -- SAIF0 clock pin selected for both SAIF0 and SAIF1 input clocks. 0x3 CLKSRCSAIF1PIN -- SAIF1 clock pin selected for both SAIF0 and SAIF1 input clocks. 9-4 RSVD0 Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1468 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_CTRL field descriptions (continued) Field Description 3 Set this bit to disable the ARM core's debug logic (for power savings). This bit must remain 0 following DEBUG_DISABLE power-on reset for normal JTAG debugger operation of the ARM core. When set to 1, it gates off the clocks to the ARM core's debug logic. Once this bit is set, the part must undergo a power-on reset to reenable debug operation. Manually clearing this bit through a write after it has been set produces unknown results. 2 This bit must be cleared to 0 for normal operation of the USB controller. When set to 1, it gates off the USB0_CLKGATE clocks to the USB controller. USB_CLKGATE can be set during suspend to gate the USB clock during suspend. If this is gated, then the USB controller Reset Received bit (HW_USBCTRL_USBSTS_URI) should be not be polled for reset during suspend; use the HW_USBPHY_CTRL_RESUME_IRQ bit instead. This bit can be hardware auto cleared when wakeup from suspend happens 0x0 0x1 1 JTAG_SHIELD 0 = The JTAG debugger is enabled. 1 = The JTAG debugger is disabled. 0x0 0x1 0 LATCH_ ENTROPY RUN -- Allow USB to operate normally. NO_CLKS -- Do not clock USB gates in order to minimize power consumption. NORMAL -- JTAG debugger enabled. SHIELDS_UP -- JTAG debugger disabled. Setting this bit latches the current value of the entropy register into HW_DIGCTL_ENTROPY_VALUE. This can be used get a stable value on players that do not deassert the PSWITCH while powered up. 19.4.2 DIGCTL Status Register (HW_DIGCTL_STATUS) The DIGCTL Status Register provides a read-only view to various input conditions and internal states. HW_DIGCTL_STATUS: 0x010 HW_DIGCTL_STATUS_SET: 0x014 HW_DIGCTL_STATUS_CLR: 0x018 HW_DIGCTL_STATUS_TOG: 0x01C EXAMPLE if(HW_DIGCTL_STATUS.PACKAGE_TYPE) { // do 100-pin package things } i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1469 Programmable Registers 30 29 28 27 26 25 24 USB0_HOST_PRESENT USB0_DEVICE_PRESENT USB1_HS_PRESENT USB1_OTG_PRESENT USB1_HOST_PRESENT USB1_DEVICE_PRESENT R 31 USB0_OTG_PRESENT Bit USB0_HS_PRESENT Address: 8001_C000h base + 10h offset = 8001_C010h 1 1 1 1 1 1 1 1 23 22 21 20 19 18 17 16 0 0 0 RSVD0 W Reset 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1470 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM 13 12 11 10 9 8 7 6 5 RSVD0 R 4 3 2 1 PACKAGE_TYPE 0 WRITTEN 14 JTAG_IN_USE 15 Bit W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_STATUS field descriptions Field 31 USB0_HS_ PRESENT 30 USB0_OTG_ PRESENT 29 USB0_HOST_ PRESENT Description This read-only bit returns a 1 when USB high-speed mode is present. This read-only bit returns a 1 when USB on-the-go (OTG) functionality is present. This read-only bit returns a 1 when USB host functionality is present. 28 This read-only bit returns a 1 when USB device functionality is present. USB0_DEVICE_ PRESENT 27 USB1_HS_ PRESENT 26 USB1_OTG_ PRESENT This read-only bit returns a 1 when USB high-speed mode is present. This read-only bit returns a 1 when USB on-the-go (OTG) functionality is present. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1471 Programmable Registers HW_DIGCTL_STATUS field descriptions (continued) Field Description 25 USB1_HOST_ PRESENT This read-only bit returns a 1 when USB host functionality is present. 24 This read-only bit returns a 1 when USB device functionality is present. USB1_DEVICE_ PRESENT 23-5 RSVD0 Reserved. 4 JTAG_IN_USE 3-1 PACKAGE_ TYPE This read-only bit is a 1 if JTAG debugger usage has been detected. This read-only bit field returns the pin count and package type. 000=289BGA, 001-111=Reserved. 0 WRITTEN Set to 1 by any successful write to the HW_DIGCTL_WRITEONCE register. 19.4.3 Free-Running HCLK Counter Register (HW_DIGCTL_HCLKCOUNT) The Free-Running HCLK Counter Register is available for performance metrics. This counter increments once per HCLK rising edge. HW_DIGCTL_HCLKCOUNT: 0x020 HW_DIGCTL_HCLKCOUNT_SET: 0x024 HW_DIGCTL_HCLKCOUNT_CLR: 0x028 HW_DIGCTL_HCLKCOUNT_TOG: 0x02C EXAMPLE StartTime = HW_DIGCTL_HCLKCOUNT; // Do something you want timed here EndTime = HW_DIGCTL_HCLKCOUNT; Duration = EndTime - StartTime; // make sure to handle rollover in a real application Address: 8001_C000h base + 20h offset = 8001_C020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1472 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_HCLKCOUNT field descriptions Field Description COUNT This counter counts up from reset using HCLK. The count is valid for HCLK frequencies greater than 2 MHz. 19.4.4 On-Chip RAM Control Register (HW_DIGCTL_RAMCTRL) The On-Chip RAM Control Register holds on-chip SRAM control bit fields. This register controls various parts of the on-chip RAM, including the speed select configuration. HW_DIGCTL_RAMCTRL: 0x030 HW_DIGCTL_RAMCTRL_SET: 0x034 HW_DIGCTL_RAMCTRL_CLR: 0x038 HW_DIGCTL_RAMCTRL_TOG: 0x03C EXAMPLE HW_DIGCTL_RAMCTRL_SET(BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT); state machine // Start the efuse Address: 8001_C000h base + 30h offset = 8001_C030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSVD2 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1473 Programmable Registers 15 RSVD 2 0 0 W Reset 13 DEBUG_ENABLE R 14 RSVD1 Bit 0 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD0 DEBUG_CODE 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_RAMCTRL field descriptions Field Description 31-15 RSVD2 Reserved. 14 RSVD1 Reserved, always set to zero. 13 DEBUG_ ENABLE Debug enable for on chip sram. Set DEBUG_CODE field for different debug mode. 12-8 Debug code for 8x32 OCRAM instances. Recommended value is 0x0. Used to change different data DEBUG_CODE access time. These bits are ignored if debug enable is low. 0x0 0x4 0x5 0x6 0x7 RSVD0 NORMAL -- Normal functional mode. DELAY1 -- Normal functional mode. DELAY2 -- Normal functional mode. DELAY3 -- Normal functional mode. DELAY4 -- Normal functional mode. Reserved. 19.4.5 EMI Status Register (HW_DIGCTL_EMI_STATUS) The EMI Status Register indicates the low power mode of the EMI and provides state data that is not available in the EMI controller. HW_DIGCTL_EMI_STATUS: 0x040 HW_DIGCTL_EMI_STATUS_SET: 0x044 HW_DIGCTL_EMI_STATUS_CLR: 0x048 HW_DIGCTL_EMI_STATUS_TOG: 0x04C EXAMPLE NA i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1474 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM Address: 8001_C000h base + 40h offset = 8001_C040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 RSVD0 R 4 3 2 1 0 POWER_MODE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_EMI_STATUS field descriptions Field Description 31-5 RSVD0 Reserved. POWER_MODE A detail description of the low power modes can be found in the EMI documentation. This register provides a port with which to read the power mode status since this capability is not inherent in the block itself. 0x2 0x4 0x8 0x10 0x0 PM4 -- Power mode 4 is active. PM3 -- Power mode 3 is active. PM2 -- Power mode 2 is active. PM1 -- Power mode 1 is active. NORMAL -- Normal operation, low power modes are not active. 19.4.6 On-Chip Memories Read Margin Register (HW_DIGCTL_READ_MARGIN) The On-Chip Memories Read Margin Register provide speed select settings for numerous memories. HW_DIGCTL_READ_MARGIN: 0x050 HW_DIGCTL_READ_MARGIN_SET: 0x054 HW_DIGCTL_READ_MARGIN_CLR: 0x058 HW_DIGCTL_READ_MARGIN_TOG: 0x05C This register controls various parts of the on-chip RAM and ROM, including the sense amp configuration. Address: 8001_C000h base + 50h offset = 8001_C050h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 RSVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ROM W Reset 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1475 Programmable Registers HW_DIGCTL_READ_MARGIN field descriptions Field Description 31-4 RSVD0 Reserved. ROM This field is used for setting the read margin for the On-Chip ROM. It programs the sense amp differential setting and allows the trade off between speed and robustness. This field should not be changed unless instructed by Freescale. 19.4.7 Software Write-Once Register (HW_DIGCTL_WRITEONCE) The Software Write-Once Register hold the value used in software certification management. This register is used to hold a portion of a certificate that is not mutable after software initialization. EXAMPLE HW_DIGCTL_WRITEONCE.U = my_certificate; Address: 8001_C000h base + 60h offset = 8001_C060h Bit R W 31 Reset 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 BITS 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 HW_DIGCTL_WRITEONCE field descriptions Field BITS Description This field can be written only one time. The contents are not used by hardware. 19.4.8 BIST Control Register (HW_DIGCTL_BIST_CTL) The BIST Control Register provides the BIST control of all the blocks. HW_DIGCTL_BIST_CTL: 0x070 HW_DIGCTL_BIST_CTL_SET: 0x074 HW_DIGCTL_BIST_CTL_CLR: 0x078 HW_DIGCTL_BIST_CTL_TOG: 0x07C EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1476 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_BIST_CTL(); // Address: 8001_C000h base + 70h offset = 8001_C070h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD0 BIST_TESTMODE BIST_RESETN BIST_DEBUGZ BIST_CHECKB BIST_RESUME 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD 0 OCRAM_BIST_RETENTION OCRAM_BIST_PASS OCRAM_BIST_FAIL OCRAM_BIST_DONE OCRAM_BIST_START PXP_BIST_START LCDIF_BIST_START DCP_BIST_START ENET_BIST_START USB1_BIST_START USB0_BIST_START DMA1_BIST_START DMA0_BIST_START CACHE_BIST_START CAN_BIST_START R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Bit R W Reset i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1477 Programmable Registers HW_DIGCTL_BIST_CTL field descriptions Field 31 BIST_ TESTMODE 30 BIST_RESETN Description bist test mode, open clock gatings bist reset. 29 enable bist debug BIST_DEBUGZ 28 use checkboard algorithm with retention BIST_CHECKB 27 resume with bist for retention test BIST_RESUME 26-15 RSVD0 Reserved. 14 This read-only bit is a 1 if the OCRAM BIST test has been enabled waiting for a resume. OCRAM_BIST_ RETENTION 13 This read-only bit is a 1 if the OCRAM BIST pass. OCRAM_BIST_ PASS 12 This read-only bit is a 1 if the OCRAM BIST test returns a failure. OCRAM_BIST_ FAIL 11 This read-only bit is a 1 if the OCRAM BIST test has completed. OCRAM_BIST_ DONE 10 Set this bit to start the OCRAM BIST. OCRAM_BIST_ START 9 PXP_BIST_ START 8 LCDIF_BIST_ START Set this bit to start the PXP BIST. Set this bit to start the LCDIF BIST. 7 DCP_BIST_ START Set this bit to start the DCP BIST. 6 ENET_BIST_ START Set this bit to start the ENET BIST. 5 USB1_BIST_ START Set this bit to start the USB1 BIST. 4 USB0_BIST_ START Set this bit to start the USB0 BIST. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1478 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_BIST_CTL field descriptions (continued) Field Description 3 DMA1_BIST_ START Set this bit to start the DMA1 BIST. 2 DMA0_BIST_ START Set this bit to start the DMA0 BIST. 1 CACHE_BIST_ START 0 CAN_BIST_ START Set this bit to start the CACHE BIST. Set this bit to start the CAN BIST. 19.4.9 DIGCTL Status Register (HW_DIGCTL_BIST_STATUS) The DIGCTL Status Register reports status for the digital control block. HW_DIGCTL_BIST_STATUS: 0x080 HW_DIGCTL_BIST_STATUS_SET: 0x084 HW_DIGCTL_BIST_STATUS_CLR: 0x088 HW_DIGCTL_BIST_STATUS_TOG: 0x08C EXAMPLE HW_DIGCTL_BIST_STATUS(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1479 Bit 31 R Reset 1480 0 26 25 24 23 22 21 20 19 18 17 16 USB1_BIST_RETENTION USB0_BIST_RETENTION DMA1_BIST_RETENTION DMA0_BIST_RETENTION CACHE_BIST_RETENTION CAN_BIST_RETENTION PXP_BIST_FAIL LCDIF_BIST_FAIL DCP_BIST_FAIL ENET_BIST_FAIL 0 27 ENET_BIST_RETENTION W 28 DCP_BIST_RETENTION RSVD0 29 LCDIF_BIST_RETENTION 30 PXP_BIST_RETENTION Programmable Registers Address: 8001_C000h base + 80h offset = 8001_C080h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMA1_BIST_FAIL DMA0_BIST_FAIL CACHE_BIST_FAIL CAN_BIST_FAIL PXP_BIST_DONE LCDIF_BIST_DONE DCP_BIST_DONE ENET_BIST_DONE USB1_BIST_DONE USB0_BIST_DONE DMA1_BIST_DONE DMA0_BIST_DONE CACHE_BIST_DONE CAN_BIST_DONE R 15 USB0_BIST_FAIL Bit USB1_BIST_FAIL Chapter 19 Digital Control (DIGCTL) and On-Chip RAM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset HW_DIGCTL_BIST_STATUS field descriptions Field 31-30 RSVD0 Description Reserved. 29 PXP_BIST_ RETENTION This read-only bit is a 1 if the PXP BIST test has been enabled waiting for a resume. 28 LCDIF_BIST_ RETENTION This read-only bit is a 1 if the LCDIF BIST test has been enabled waiting for a resume. 27 DCP_BIST_ RETENTION This read-only bit is a 1 if the DCP BIST test has been enabled waiting for a resume. 26 ENET_BIST_ RETENTION This read-only bit is a 1 if the ENET BIST test has been enabled waiting for a resume. 25 USB1_BIST_ RETENTION This read-only bit is a 1 if the USB1 BIST test has been enabled waiting for a resume. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1481 Programmable Registers HW_DIGCTL_BIST_STATUS field descriptions (continued) Field Description 24 USB0_BIST_ RETENTION This read-only bit is a 1 if the USB0 BIST test has been enabled waiting for a resume. 23 DMA1_BIST_ RETENTION This read-only bit is a 1 if the DMA1 BIST test has been enabled waiting for a resume. 22 DMA0_BIST_ RETENTION This read-only bit is a 1 if the DMA0 BIST test has been enabled waiting for a resume. 21 CACHE_BIST_ RETENTION 20 CAN_BIST_ RETENTION This read-only bit is a 1 if the CACHE BIST test has been enabled waiting for a resume. This read-only bit is a 1 if the CAN BIST test has been enabled waiting for a resume. 19 This read-only bit is a 1 if the PXP BIST test returns a failure. PXP_BIST_FAIL 18 LCDIF_BIST_ FAIL This read-only bit is a 1 if the LCDIF BIST test returns a failure. 17 This read-only bit is a 1 if the DCP BIST test returns a failure. DCP_BIST_FAIL 16 ENET_BIST_ FAIL This read-only bit is a 1 if the ENET BIST test returns a failure. 15 USB1_BIST_ FAIL This read-only bit is a 1 if the USB1 BIST test returns a failure. 14 USB0_BIST_ FAIL This read-only bit is a 1 if the USB0 BIST test returns a failure. 13 DMA1_BIST_ FAIL This read-only bit is a 1 if the DMA1 BIST test returns a failure. 12 DMA0_BIST_ FAIL This read-only bit is a 1 if the DMA0 BIST test returns a failure. 11 CACHE_BIST_ FAIL This read-only bit is a 1 if the CACHE BIST test returns a failure. 10 This read-only bit is a 1 if the CAN BIST test returns a failure. CAN_BIST_FAIL 9 PXP_BIST_ DONE 8 LCDIF_BIST_ DONE This read-only bit is a 1 if the PXP BIST test has completed. This read-only bit is a 1 if the LCDIF BIST test has completed. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1482 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_BIST_STATUS field descriptions (continued) Field Description 7 DCP_BIST_ DONE This read-only bit is a 1 if the DCP BIST test has completed. 6 ENET_BIST_ DONE This read-only bit is a 1 if the ENET BIST test has completed. 5 USB1_BIST_ DONE This read-only bit is a 1 if the USB1 BIST test has completed. 4 USB0_BIST_ DONE This read-only bit is a 1 if the USB0 BIST test has completed. 3 DMA1_BIST_ DONE This read-only bit is a 1 if the DMA1 BIST test has completed. 2 DMA0_BIST_ DONE This read-only bit is a 1 if the DMA0 BIST test has completed. 1 CACHE_BIST_ DONE 0 CAN_BIST_ DONE This read-only bit is a 1 if the CACHE BIST test has completed. This read-only bit is a 1 if the CAN BIST test has completed. 19.4.10 Entropy Register (HW_DIGCTL_ENTROPY) The Entropy register is a read-only test value register. EXAMPLE while(HW_DIGCTL_STATUS.PSWITCH != 0) { //wait for pswitch to go away } HW_DIGCTL_WRITEONCE.BITS = rand(HW_DIGCTL_ENTROPY.VALUE); Address: 8001_C000h base + 90h offset = 8001_C090h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1483 Programmable Registers HW_DIGCTL_ENTROPY field descriptions Field Description VALUE This read-only bit field always reads back the results of an entropy calculation. It is used to randomize the seeds for random number generators. 19.4.11 Entropy Latched Register (HW_DIGCTL_ENTROPY_LATCHED) The Entropy Latched Register is a read-only test value register. Address: 8001_C000h base + A0h offset = 8001_C0A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_ENTROPY_LATCHED field descriptions Field VALUE Description When the LATCH_ENTROPY bit in the HW_DIGCTL_CTRL register is set to 1, the value of the HW_DIGCTL_ENTROPY register is latched into this register. This can be used to latch a stable random value on players where the PSWITCH is not deasserted after power-up. 19.4.12 Digital Control Microseconds Counter Register (HW_DIGCTL_MICROSECONDS) The Digital Control Microseconds Counter Register is a read-only test value register. HW_DIGCTL_MICROSECONDS: 0x0C0 HW_DIGCTL_MICROSECONDS_SET: 0x0C4 HW_DIGCTL_MICROSECONDS_CLR: 0x0C8 HW_DIGCTL_MICROSECONDS_TOG: 0x0CC This fixed-rate timer always increments at 24.0 MHz divided by 24 or 1.0 MHz. It does not generate an interrupt. EXAMPLE StartTime = HW_DIGCTL_MICROSECONDS_RD(); EndTime = HW_DIGCTL_MICROSECONDS_RD(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1484 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM ElapsedTime = StartTime - EndTime; // WARNING, handle rollover in real software Address: 8001_C000h base + C0h offset = 8001_C0C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MICROSECONDS field descriptions Field Description VALUE This register maintains a 32-bit counter that increments at a 1-microsecond rate. The 1-MHz clock driving this counter is derived from the 24.0-MHz crystal oscillator. The count value is not preserved over powerdowns. The 32-bit value wraps in less than two hours. 19.4.13 Digital Control Debug Read Test Register (HW_DIGCTL_DBGRD) The Digital Control Debug Read Test Register is a read-only test value register. This register is used for debugging purposes. EXAMPLE debug_value = HW_DIGCTL_DBGRD_RD(); Address: 8001_C000h base + D0h offset = 8001_C0D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 COMPLEMENT R W Reset 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 HW_DIGCTL_DBGRD field descriptions Field Description COMPLEMENT This read-only bit field always reads back the one's complement of the value in HW_DIGCTL_DBG. 19.4.14 Digital Control Debug Register (HW_DIGCTL_DBG) The Digital Control Debug Register is a read-only test value register. This register is used for debugging purposes. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1485 Programmable Registers debug_value = HW_DIGCTL_DBG_RD(); Address: 8001_C000h base + E0h offset = 8001_C0E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 VALUE R W 1 Reset 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 HW_DIGCTL_DBG field descriptions Field Description VALUE This read-only bit field always reads back the fixed value 0x87654321. 19.4.15 USB LOOP BACK (HW_DIGCTL_USB_LOOPBACK) This register used to control the USB test mode for loopback tests. HW_DIGCTL_USB_LOOPBACK: 0x100 HW_DIGCTL_USB_LOOPBACK_SET: 0x104 HW_DIGCTL_USB_LOOPBACK_CLR: 0x108 HW_DIGCTL_USB_LOOPBACK_TOG: 0x10C This register contains controls for the USB loop back 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 0 0 0 0 0 RSVD0 R W Reset 0 0 0 0 0 0 0 0 17 16 TSTI1_TX_LS Bit USB1_TST_START Address: 8001_C000h base + 100h offset = 8001_C100h 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1486 Freescale Semiconductor, Inc. 11 10 9 8 7 6 5 4 TSTI1_TX_HIZ UTMI1_DIG_TST1 UTMI1_DIG_TST0 USB0_TST_START TSTI0_TX_LS TSTI0_TX_HS TSTI0_TX_EN TSTI0_TX_HIZ UTMI0_DIG_TST1 UTMI0_DIG_TST0 0 0 0 0 0 0 0 0 0 0 0 0 R 3 2 1 0 UTMO0_DIG_TST0 12 UTMO0_DIG_TST1 13 UTMO1_DIG_TST0 14 UTMO1_DIG_TST1 15 TSTI1_TX_EN Bit TSTI1_TX_HS Chapter 19 Digital Control (DIGCTL) and On-Chip RAM 0 0 0 0 W Reset HW_DIGCTL_USB_LOOPBACK field descriptions Field 31-18 RSVD0 17 USB1_TST_ START Description Always write zeroes to this bit field. This bit enables the USB loopback test. 16 TSTI1_TX_LS Set to 1 to choose LS, set to 0 to choose HS or FS mode which defined by TSTI1_TX_HS. 15 TSTI1_TX_HS chooses HS or FS mode. 14 TSTI1_TX_EN eanbles TX 13 TSTI1_TX_HIZ makes TX HIZ 12 UTMI1_DIG_ TST1 control for mode 11 UTMI1_DIG_ TST0 control for mode 10 USB0_TST_ START This bit enables the USB loopback test. 9 TSTI0_TX_LS Set to 1 to choose LS, set to 0 to choose HS or FS mode which defined by TSTI1_TX_HS. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1487 Programmable Registers HW_DIGCTL_USB_LOOPBACK field descriptions (continued) Field Description 8 TSTI0_TX_HS chooses HS or FS mode. 7 TSTI0_TX_EN enables TX 6 TSTI0_TX_HIZ makes TX HIZ 5 UTMI0_DIG_ TST1 control for mode 4 UTMI0_DIG_ TST0 control for mode 3 UTMO1_DIG_ TST1 This read-only bit is a status bit for USB1 LB = 1 is pass 2 UTMO1_DIG_ TST0 This read-only bit is a status bit for USB1 LB = 0 is pass 1 UTMO0_DIG_ TST1 This read-only bit is a status bit for USB0 LB = 1 is pass 0 UTMO0_DIG_ TST0 This read-only bit is a status bit for USB0 LB = 0 is pass 19.4.16 SRAM Status Register 0 (HW_DIGCTL_OCRAM_STATUS0) The SRAM Status Register 0 is a read-only fail data register. HW_DIGCTL_OCRAM_STATUS0: 0x110 HW_DIGCTL_OCRAM_STATUS0_SET: 0x114 HW_DIGCTL_OCRAM_STATUS0_CLR: 0x118 HW_DIGCTL_OCRAM_STATUS0_TOG: 0x11C This register contains fail data for the first fail . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS0_RD(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1488 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM Address: 8001_C000h base + 110h offset = 8001_C110h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAILDATA00 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS0 field descriptions Field Description FAILDATA00 This read-only bit field contains the fail data for the first fail . 19.4.17 SRAM Status Register 1 (HW_DIGCTL_OCRAM_STATUS1) The SRAM Status Register 1 is a read-only fail data register. HW_DIGCTL_OCRAM_STATUS1: 0x120 HW_DIGCTL_OCRAM_STATUS1_SET: 0x124 HW_DIGCTL_OCRAM_STATUS1_CLR: 0x128 HW_DIGCTL_OCRAM_STATUS1_TOG: 0x12C This register contains fail data for the second fail . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS1_RD(); Address: 8001_C000h base + 120h offset = 8001_C120h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAILDATA01 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS1 field descriptions Field FAILDATA01 Description This read-only bit field contains the fail data for the second fail . 19.4.18 SRAM Status Register 2 (HW_DIGCTL_OCRAM_STATUS2) SRAM Status Register 2 is a read-only fail data register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1489 Programmable Registers HW_DIGCTL_OCRAM_STATUS2: 0x130 HW_DIGCTL_OCRAM_STATUS2_SET: 0x134 HW_DIGCTL_OCRAM_STATUS2_CLR: 0x138 HW_DIGCTL_OCRAM_STATUS2_TOG: 0x13C This register contains fail data for the third fail . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS2_RD(); Address: 8001_C000h base + 130h offset = 8001_C130h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAILDATA10 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS2 field descriptions Field FAILDATA10 Description This read-only bit field contains the fail data for the third fail . 19.4.19 SRAM Status Register 3 (HW_DIGCTL_OCRAM_STATUS3) RAM Status Register 3 is a read-only fail data register. HW_DIGCTL_OCRAM_STATUS3: 0x140 HW_DIGCTL_OCRAM_STATUS3_SET: 0x144 HW_DIGCTL_OCRAM_STATUS3_CLR: 0x148 HW_DIGCTL_OCRAM_STATUS3_TOG: 0x14C This register contains fail data for the 4th fail . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS3_RD(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1490 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM Address: 8001_C000h base + 140h offset = 8001_C140h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAILDATA11 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS3 field descriptions Field Description FAILDATA11 This read-only bit field contains the fail data for the 4th fail . 19.4.20 SRAM Status Register 4 (HW_DIGCTL_OCRAM_STATUS4) SRAM Status Register 4 is a read-only fail data register. HW_DIGCTL_OCRAM_STATUS4: 0x150 HW_DIGCTL_OCRAM_STATUS4_SET: 0x154 HW_DIGCTL_OCRAM_STATUS4_CLR: 0x158 HW_DIGCTL_OCRAM_STATUS4_TOG: 0x15C This register contains fail data for the 5th fail . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS4_RD(); Address: 8001_C000h base + 150h offset = 8001_C150h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAILDATA20 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS4 field descriptions Field FAILDATA20 Description This read-only bit field contains the fail data for the 5th fail . 19.4.21 SRAM Status Register 5 (HW_DIGCTL_OCRAM_STATUS5) SRAM Status Register 5 is a read-only fail data register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1491 Programmable Registers HW_DIGCTL_OCRAM_STATUS5: 0x160 HW_DIGCTL_OCRAM_STATUS5_SET: 0x164 HW_DIGCTL_OCRAM_STATUS5_CLR: 0x168 HW_DIGCTL_OCRAM_STATUS5_TOG: 0x16C This register contains fail data for the 6th fail . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS5_RD(); Address: 8001_C000h base + 160h offset = 8001_C160h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAILDATA21 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS5 field descriptions Field FAILDATA21 Description This read-only bit field contains the fail data for the 6th fail . 19.4.22 SRAM Status Register 6 (HW_DIGCTL_OCRAM_STATUS6) SRAM Status Register 6 is a read-only fail data register. HW_DIGCTL_OCRAM_STATUS6: 0x170 HW_DIGCTL_OCRAM_STATUS6_SET: 0x174 HW_DIGCTL_OCRAM_STATUS6_CLR: 0x178 HW_DIGCTL_OCRAM_STATUS6_TOG: 0x17C This register contains fail data for the 7th fail . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS6_RD(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1492 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM Address: 8001_C000h base + 170h offset = 8001_C170h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAILDATA30 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS6 field descriptions Field Description FAILDATA30 This read-only bit field contains the fail data for the 7th fail . 19.4.23 SRAM Status Register 7 (HW_DIGCTL_OCRAM_STATUS7) SRAM Status Register 7 is a read-only fail data register. HW_DIGCTL_OCRAM_STATUS7: 0x180 HW_DIGCTL_OCRAM_STATUS7_SET: 0x184 HW_DIGCTL_OCRAM_STATUS7_CLR: 0x188 HW_DIGCTL_OCRAM_STATUS7_TOG: 0x18C This register contains fail data for the 8th fail . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS7_RD(); Address: 8001_C000h base + 180h offset = 8001_C180h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAILDATA31 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS7 field descriptions Field FAILDATA31 Description This read-only bit field contains the fail data for the 8th fail . 19.4.24 SRAM Status Register 8 (HW_DIGCTL_OCRAM_STATUS8) SRAM Status Register 8 is a read-only fail address register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1493 Programmable Registers HW_DIGCTL_OCRAM_STATUS8: 0x190 HW_DIGCTL_OCRAM_STATUS8_SET: 0x194 HW_DIGCTL_OCRAM_STATUS8_CLR: 0x198 HW_DIGCTL_OCRAM_STATUS8_TOG: 0x19C This register contains fail address for the first and second failures . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS8_RD(); Address: 8001_C000h base + 190h offset = 8001_C190h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FAILADDR01 R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FAILADDR00 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS8 field descriptions Field Description 31-16 FAILADDR01 This read-only bit field contains the failing address for the second fail . FAILADDR00 This read-only bit field contains the failing address for the first fail . 19.4.25 SRAM Status Register 9 (HW_DIGCTL_OCRAM_STATUS9) SRAM Status Register 9 is a read-only fail address register. HW_DIGCTL_OCRAM_STATUS9: 0x1A0 HW_DIGCTL_OCRAM_STATUS9_SET: 0x1A4 HW_DIGCTL_OCRAM_STATUS9_CLR: 0x1A8 HW_DIGCTL_OCRAM_STATUS9_TOG: 0x1AC This register contains fail address for the third and 4th failures . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS9_RD(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1494 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM Address: 8001_C000h base + 1A0h offset = 8001_C1A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FAILADDR11 R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FAILADDR10 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS9 field descriptions Field Description 31-16 FAILADDR11 This read-only bit field contains the failing address for the 4th fail . FAILADDR10 This read-only bit field contains the failing address for the third fail . 19.4.26 SRAM Status Register 10 (HW_DIGCTL_OCRAM_STATUS10) SRAM Status Register 10 is a read-only fail address register. HW_DIGCTL_OCRAM_STATUS10: 0x1B0 HW_DIGCTL_OCRAM_STATUS10_SET: 0x1B4 HW_DIGCTL_OCRAM_STATUS10_CLR: 0x1B8 HW_DIGCTL_OCRAM_STATUS10_TOG: 0x1BC This register contains fail address for the 5th and 6th failures . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS10_RD(); Address: 8001_C000h base + 1B0h offset = 8001_C1B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FAILADDR21 R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FAILADDR20 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS10 field descriptions Field Description 31-16 FAILADDR21 This read-only bit field contains the failing address for the 6th fail . FAILADDR20 This read-only bit field contains the failing address for the 5th fail . i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1495 Programmable Registers 19.4.27 SRAM Status Register 11 (HW_DIGCTL_OCRAM_STATUS11) SRAM Status Register 11 is a read-only fail address register. HW_DIGCTL_OCRAM_STATUS11: 0x1C0 HW_DIGCTL_OCRAM_STATUS11_SET: 0x1C4 HW_DIGCTL_OCRAM_STATUS11_CLR: 0x1C8 HW_DIGCTL_OCRAM_STATUS11_TOG: 0x1CC This register contains fail address for the 7th and 8th failures . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS11_RD(); Address: 8001_C000h base + 1C0h offset = 8001_C1C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FAILADDR31 R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 FAILADDR30 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS11 field descriptions Field Description 31-16 FAILADDR31 This read-only bit field contains the failing address for the 8th fail . FAILADDR30 This read-only bit field contains the failing address for the 7th fail . 19.4.28 SRAM Status Register 12 (HW_DIGCTL_OCRAM_STATUS12) SRAM Status Register 12 is a read-only fail state register. HW_DIGCTL_OCRAM_STATUS12: 0x1D0 HW_DIGCTL_OCRAM_STATUS12_SET: 0x1D4 HW_DIGCTL_OCRAM_STATUS12_CLR: 0x1D8 HW_DIGCTL_OCRAM_STATUS12_TOG: 0x1DC This register contains fail state for the first, second, third and 4th failures . EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1496 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM fail_data = HW_DIGCTL_OCRAM_STATUS12_RD(); Address: 8001_C000h base + 1D0h offset = 8001_C1D0h R 30 29 28 27 26 25 24 23 22 21 RSVD2 31 RSVD3 Bit FAILSTATE11 20 19 18 17 16 FAILSTATE10 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSVD0 Bit 0 RSVD1 Reset FAILSTATE01 FAILSTATE00 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_OCRAM_STATUS12 field descriptions Field 31 RSVD3 30-24 FAILSTATE11 23 RSVD2 22-16 FAILSTATE10 15 RSVD1 14-8 FAILSTATE01 7 RSVD0 FAILSTATE00 Description This field is unused. This read-only bit field contains the failing state for the 4th fail . This field is unused. This read-only bit field contains the failing state for the 3th fail . This field is unused. This read-only bit field contains the failing state for the second fail . This field is unused. This read-only bit field contains the failing state for the first fail . i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1497 Programmable Registers 19.4.29 SRAM Status Register 13 (HW_DIGCTL_OCRAM_STATUS13) SRAM Status Register 13 is a read-only fail state register. HW_DIGCTL_OCRAM_STATUS13: 0x1E0 HW_DIGCTL_OCRAM_STATUS13_SET: 0x1E4 HW_DIGCTL_OCRAM_STATUS13_CLR: 0x1E8 HW_DIGCTL_OCRAM_STATUS13_TOG: 0x1EC This register contains fail state for the 5th, 6th, 7th, and 8th failures . EXAMPLE fail_data = HW_DIGCTL_OCRAM_STATUS13_RD(); Address: 8001_C000h base + 1E0h offset = 8001_C1E0h R 30 29 28 27 26 25 24 23 22 21 RSVD2 31 RSVD3 Bit FAILSTATE31 20 19 18 17 16 FAILSTATE30 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSVD0 Bit 0 RSVD1 Reset FAILSTATE21 FAILSTATE20 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1498 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_OCRAM_STATUS13 field descriptions Field Description 31 RSVD3 This field is unused. 30-24 FAILSTATE31 23 RSVD2 This read-only bit field contains the failing state for the 8th fail . This field is unused. 22-16 FAILSTATE30 15 RSVD1 This read-only bit field contains the failing state for the 7th fail . This field is unused. 14-8 FAILSTATE21 7 RSVD0 This read-only bit field contains the failing state for the 6th fail . This field is unused. FAILSTATE20 This read-only bit field contains the failing state for the 5th fail . 19.4.30 Digital Control Scratch Register 0 (HW_DIGCTL_SCRATCH0) Digital control scratch pad Scratch Pad Register 0. EXAMPLE scratch_pad = (*void)HW_DIGCTL_SCRATCH0.PTR; Address: 8001_C000h base + 280h offset = 8001_C280h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_SCRATCH0 field descriptions Field PTR Description Digital control scratch pad 19.4.31 Digital Control Scratch Register 1 (HW_DIGCTL_SCRATCH1) Scratch Pad Register 1. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1499 Programmable Registers scratch_pad = (*void)HW_DIGCTL_SCRATCH1.PTR; Address: 8001_C000h base + 290h offset = 8001_C290h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_SCRATCH1 field descriptions Field Description PTR Digital control scratch pad 19.4.32 Digital Control ARM Cache Register (HW_DIGCTL_ARMCACHE) This register provides the ARM cache RAM controls. ARM Cache Control Register. EXAMPLE cache_timing = HW_DIGCTL_ARMCACHE.CACHE_SS; Address: 8001_C000h base + 2A0h offset = 8001_C2A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 RSVD4 R Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD3 W Reset 16 VALID_SS W Reset 17 0 0 DRTY_SS 0 0 RSVD2 0 0 CACHE_SS 0 0 RSVD1 0 0 RSVD0 DTAG_SS 0 0 0 0 ITAG_SS 0 0 HW_DIGCTL_ARMCACHE field descriptions Field 31-18 RSVD4 17-16 VALID_SS 15-14 RSVD3 Description Reserved. Timing control for 64x24x1 RAMs (both instruction and data cache_valid arrays). Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1500 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_ARMCACHE field descriptions (continued) Field 13-12 DRTY_SS 11-10 RSVD2 9-8 CACHE_SS 7-6 RSVD1 5-4 DTAG_SS 3-2 RSVD0 ITAG_SS Description Timing control for 128x8x1 RAM (DDRTY). Reserved. Timing Control for 1024x32x4 RAMs (both instruction and data cache arrays). Reserved. Timing Control for 256x22x4 RAM (DTAG). Reserved. Timing Control for 128x22x4 RAM (ITAG). 19.4.33 Debug Trap Control and Status for AHB Layer 0 and 3 (HW_DIGCTL_DEBUG_TRAP) The Debug Trap Register provides control and status information for the trap functionality. HW_DIGCTL_DEBUG_TRAP: 0x2B0 HW_DIGCTL_DEBUG_TRAP_SET: 0x2B4 HW_DIGCTL_DEBUG_TRAP_CLR: 0x2B8 HW_DIGCTL_DEBUG_TRAP_TOG: 0x2BC This register sets the lower address that defines the debug trap function. When this function is enabled, any active AHB cycle on either Layer 0 or Layer 0 which accesses this range will trigger an interrupt to the ARM core. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1501 Programmable Registers Address: 8001_C000h base + 2B0h offset = 8001_C2B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRAP_L0_IRQ TRAP_IN_RANGE TRAP_ENABLE Bit 0 0 0 0 0 RSVD2 R RSVD1 TRAP_L0_ MASTER_ID RSVD0 Reset TRAP_L3_IRQ W TRAP_L3_ MASTER_ID W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_DEBUG_TRAP field descriptions Field Description 31-12 RSVD2 Reserved. 11-10 RSVD1 Reserved. 9-8 TRAP_L0_ MASTER_ID ID of master on AHB Layer 0 that triggered the TRAP_L0_IRQ. The value in this bitfield is updated when TRAP_L0_IRQ is set. 0x0 0x1 0x2 0x3 PXP -- PXP LCDIF -- LCDIF BCH -- BCH DCP -- DCP Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1502 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_DEBUG_TRAP field descriptions (continued) Field Description 7 RSVD0 Reserved. 6-4 TRAP_L3_ MASTER_ID ID of master on AHB Layer 3 that triggered the TRAP_L3_IRQ. The value in this bitfield is updated when TRAP_L3_IRQ is set. 3 TRAP_L3_IRQ This bit is set when an AHB access occurs to the range defined by the TRAP_ADDR registers below and the trap function is enabled with the TRAP_ENABLE bit. 2 TRAP_L0_IRQ This bit is set when an AHB access occurs to the range defined by the TRAP_ADDR registers below and the trap function is enabled with the TRAP_ENABLE bit. APBH_BRIDE_DMA -- APBH Bridge DMA APBX_BRIDE_DMA -- APBX Bridge DMA USB0 -- USB0 USB1 -- USB1 ENET_M0 -- ENET_M0 ENET_M1 -- ENET_M1 0x0 0x1 0x2 0x3 0x4 0x5 1 TRAP_IN_ RANGE Determines whether the debug trap function causes a match when the master address is inside (lowaddress <= current-address <= high-address) the specified range. 0 = The trap occurs when the master address falls outside of the range. 1 = The check is inside the range. 0 Enables the AHB arbiter debug trap functions. When a trap occurs and this bit is set, an interrupt is sent to TRAP_ENABLE the ARM core. 19.4.34 Debug Trap Range Low Address for AHB Layer 0 (HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW) The Debug Trap Range Low Address Register defines the lower bound for an address range that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs within this range. This register applies only to AHB Layer 0. This register sets the lower address that defines the debug trap function. When this function is enabled, any active AHB cycle on Layer 0 which accesses this range will trigger an interrupt to the ARM core. EXAMPLE Address: 8001_C000h base + 2C0h offset = 8001_C2C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1503 Programmable Registers HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW field descriptions Field Description ADDR This field contains the 32-bit lower address for the debug trap range. 19.4.35 Debug Trap Range High Address for AHB Layer 0 (HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH) The Debug Trap Range High Address Register defines the upper bound for an address range that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs within this range. This register applies only to AHB Layer 0. This register sets the upper address that defines the debug trap function. When this function is enabled, any active AHB cycle on Layer 0 which accesses this range will trigger an interrupt to the ARM core. EXAMPLE Address: 8001_C000h base + 2D0h offset = 8001_C2D0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH field descriptions Field ADDR Description This field contains the 32-bit upper address for the debug trap range. 19.4.36 Debug Trap Range Low Address for AHB Layer 3 (HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW) The Debug Trap Range Low Address Register defines the lower bound for an address range that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs within this range. This register applies only to AHB Layer 3. This register sets the lower address that defines the debug trap function. When this function is enabled, any active AHB cycle on Layer 3 which accesses this range will trigger an interrupt to the ARM core. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1504 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM Address: 8001_C000h base + 2E0h offset = 8001_C2E0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW field descriptions Field Description ADDR This field contains the 32-bit lower address for the debug trap range. 19.4.37 Debug Trap Range High Address for AHB Layer 3 (HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH) The Debug Trap Range High Address Register defines the upper bound for an address range that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs within this range. This register applies only to AHB Layer 3. This register sets the upper address that defines the debug trap function. When this function is enabled, any active AHB cycle on Layer 3 which accesses this range will trigger an interrupt to the ARM core. EXAMPLE Address: 8001_C000h base + 2F0h offset = 8001_C2F0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH field descriptions Field ADDR Description This field contains the 32-bit upper address for the debug trap range. 19.4.38 Freescale Copyright Identifier Register (HW_DIGCTL_FSL) Read-only Freescale Copyright Identifier Register. This register provides read-only access to the zero-terminated twelve-byte Freescale copyright identification string. This register behaves somewhat differently from all other APB registers in that it provides different read-back values at its three successive SCT bus addresses. The following binary values are read back at 0x300, 0x304, and 0x308 respectively: 0x65657246 e,e,r,F at 0x300 0x6c616373 l,a,c,e at 0x304 0xAEA92d65 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1505 Programmable Registers 0x00, Registered Trademark ((R)), Copyright ((c)), hyphen (-), e at 0x308 The debugger does a string compare on these 12 successive little endian bytes. Any chip that reads back these values is either a Freescale chip or it is a competitors chip that is violating Freescale registered trademarks and or copyrights. EXAMPLE printf("%s", (char *)HW_DIGCTL_SGTL_ADDR); Address: 8001_C000h base + 300h offset = 8001_C300h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 COPYRIGHT R W 0 Reset 1 1 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 HW_DIGCTL_FSL field descriptions Field Description COPYRIGHT This read-only bit field contains the four bytes of the Freescale Copyright Identification String. 19.4.39 Digital Control Chip Revision Register (HW_DIGCTL_CHIPID) Read-only chip revision register. This register is for Chip Revision EXAMPLE FormatAndPrintChipID(HW_DIGCTL_CHIPID_PRODUCT_CODE,HW_DIGCTL_CHIPID_REVISION ); Address: 8001_C000h base + 310h offset = 8001_C310h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 PRODUCT_CODE R 12 11 10 9 8 7 6 RSVD0 5 4 3 2 1 0 0 0 REVISION W Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_CHIPID field descriptions Field 31-16 PRODUCT_ CODE Description This read-only bit field returns 0x2800, which identifies the generation from which the part is derived. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1506 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_CHIPID field descriptions (continued) Field Description 15-8 RSVD0 Reserved. REVISION This read-only bit field always reads back the mask revision level of the chip. 19.4.40 AHB Statistics Control Register (HW_DIGCTL_AHB_STATS_SELECT) The AHB Statistics Control Register selects which AHB Masters on each Layer of the AHB subsystem are enabled to contribute to the statistics calculations. This register is to enable performance monitoring for the corresponding AHB master in layers EXAMPLE Address: 8001_C000h base + 330h offset = 8001_C330h Bit 31 30 29 28 27 26 25 24 23 RSVD0 R 0 0 0 0 0 21 20 19 18 17 16 15 L3_MASTER_SELECT W Reset 22 0 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 7 L2_MASTER_SELECT 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 L1_MASTER_SELECT 0 0 0 0 0 0 0 0 0 HW_DIGCTL_AHB_STATS_SELECT field descriptions Field 31-24 RSVD0 Description Reserved. 23-16 L3_MASTER_ SELECT Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 3 arbiter for the corresponding AHB master. Bits [7:6] are currently reserved and should not be set 15-8 L2_MASTER_ SELECT Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 2 arbiter for the corresponding AHB master. Bits [7:1] are currently reserved and should not be set L1_MASTER_ SELECT Set various bits of this bit field to one to enable performance monitoring in the AHB Layer 1 arbiter for the corresponding AHB master. Bits [7:1] are currently reserved and should not be set 0x1 0x2 0x4 0x8 0x10 0x20 0x1 0x1 APBHDMA -- Select APBH DMA Master. APBXDMA -- Select APBX DMA Master. USB0 -- Select USB0 Master. USB1 -- Select USB1 Master. UDMA0 -- Select UDMA0 Master. UDMA1 -- Select UDMA1 Master. ARMD -- Select ARM DATA Master. ARMI -- Select ARM Instruction Master. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1507 Programmable Registers 19.4.41 AHB Layer 1 Transfer Count Register (HW_DIGCTL_L1_AHB_ACTIVE_CYCLES) The AHB Layer 1 Transfer Count Register counts the number of AHB bus cycles during which a transfer is active on AHB Layer 0. This field counts the number of AHB cycles in which a master was requesting a transfer, and the slave had not responded. This includes cycles in which it was requesting transfers but was not granted them, as well as cycles in which it was granted and driving the bus but the targeted slave was not ready. The master selects in HW_DIGCTL_CTRL_MASTER_SELECT are used in the arbiter to mask which master \'s cycles are actually recorded here. EXAMPLE NumberCycles = HW_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT_RD(); Address: 8001_C000h base + 370h offset = 8001_C370h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_L1_AHB_ACTIVE_CYCLES field descriptions Field COUNT Description This field contains the count of AHB bus cycles during which a master was active on the AHB Layer 1. 19.4.42 AHB Layer 1 Performance Metric for Stalled Bus Cycles Register (HW_DIGCTL_L1_AHB_DATA_STALLED) Used for AHB bus utilization measurements, the AHB Performance Metric for Stalled Bus Cycles Register counts the number of stalled AHB cycles. This counter increments on a data-phase of the AHB in which the HREADY signal is low, indicating a stalled data transfer. EXAMPLE NumberStalledCycles = HW_DIGCTL_L1_AHB_DATA_STALLED_COUNT_RD(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1508 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM Address: 8001_C000h base + 380h offset = 8001_C380h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_L1_AHB_DATA_STALLED field descriptions Field Description COUNT This field counts the number of AHB cycles in which a master was stalled. 19.4.43 AHB Layer 1 Performance Metric for Valid Bus Cycles Register (HW_DIGCTL_L1_AHB_DATA_CYCLES) Used for AHB bus utilization measurements, the AHB Performance Metric for Valid Bus Cycles Register counts the number of actual AHB cycles in which a data transfer is completed. This field counts the number of AHB cycles in which a master completed a data transfer (a data-phase in which HREADY is high). EXAMPLE StartTime = HW_DIGCTL_HCLKCOUNT_RD(); while(HW_DIGCTL_L1_AHB_DATA_CYCLES.COUNT less than 1000000) { // wait for a specific number of xfers } ElapsedTime = HW_DIGCTL_HCLKCOUNT_RD() - StartTime; Address: 8001_C000h base + 390h offset = 8001_C390h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_L1_AHB_DATA_CYCLES field descriptions Field COUNT Description This field contains the count of AHB bus cycles during which data was actually transferred from a master to a slave or from a slave to a master. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1509 Programmable Registers 19.4.44 AHB Layer 2 Transfer Count Register (HW_DIGCTL_L2_AHB_ACTIVE_CYCLES) The AHB Layer 2 Transfer Count Register counts the number of AHB bus cycles during which a transfer is active on AHB Layer 2. This field counts the number of AHB cycles in which a master was requesting a transfer, and the slave had not responded. This includes cycles in which it was requesting transfers but was not granted them, as well as cycles in which it was granted and driving the bus but the targeted slave was not ready. The master selects in HW_DIGCTL_CTRL_MASTER_SELECT are used in the arbiter to mask which master \'s cycles are actually recorded here. EXAMPLE NumberCycles = HW_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_RD(); Address: 8001_C000h base + 3A0h offset = 8001_C3A0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_L2_AHB_ACTIVE_CYCLES field descriptions Field COUNT Description This field contains the count of AHB bus cycles during which a master was active on the AHB Layer 2. 19.4.45 AHB Layer 2 Performance Metric for Stalled Bus Cycles Register (HW_DIGCTL_L2_AHB_DATA_STALLED) Used for AHB bus utilization measurements, the AHB Performance Metric for Stalled Bus Cycles Register counts the number of stalled AHB cycles. This counter increments on a data-phase of the AHB in which the HREADY signal is low, indicating a stalled data transfer. EXAMPLE NumberStalledCycles = HW_DIGCTL_L2_AHB_DATA_STALLED_COUNT_RD(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1510 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM Address: 8001_C000h base + 3B0h offset = 8001_C3B0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_L2_AHB_DATA_STALLED field descriptions Field Description COUNT This field counts the number of AHB cycles in which a master was stalled. 19.4.46 AHB Layer 2 Performance Metric for Valid Bus Cycles Register (HW_DIGCTL_L2_AHB_DATA_CYCLES) Used for AHB bus utilization measurements, the AHB Performance Metric for Valid Bus Cycles Register counts the number of actual AHB cycles in which a data transfer is completed. This field counts the number of AHB cycles in which a master completed a data transfer (a data-phase in which HREADY is high). EXAMPLE StartTime = HW_DIGCTL_HCLKCOUNT_RD(); while(HW_DIGCTL_L2_AHB_DATA_CYCLES.COUNT less than 1000000) { // wait for a specific number of xfers } ElapsedTime = HW_DIGCTL_HCLKCOUNT_RD() - StartTime; Address: 8001_C000h base + 3C0h offset = 8001_C3C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_L2_AHB_DATA_CYCLES field descriptions Field COUNT Description This field contains the count of AHB bus cycles during which data was actually transferred from a master to a slave or from a slave to a master. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1511 Programmable Registers 19.4.47 AHB Layer 3 Transfer Count Register (HW_DIGCTL_L3_AHB_ACTIVE_CYCLES) The AHB Layer 3 Transfer Count Register counts the number of AHB bus cycles during which a transfer is active on AHB Layer 3. This field counts the number of AHB cycles in which a master was requesting a transfer, and the slave had not responded. This includes cycles in which it was requesting transfers but was not granted them, as well as cycles in which it was granted and driving the bus but the targeted slave was not ready. The master selects in HW_DIGCTL_CTRL_MASTER_SELECT are used in the arbiter to mask which master \'s cycles are actually recorded here. EXAMPLE NumberCycles = HW_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT_RD(); Address: 8001_C000h base + 3D0h offset = 8001_C3D0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_L3_AHB_ACTIVE_CYCLES field descriptions Field COUNT Description This field contains the count of AHB bus cycles during which a master was active on the AHB Layer 3. 19.4.48 AHB Layer 3 Performance Metric for Stalled Bus Cycles Register (HW_DIGCTL_L3_AHB_DATA_STALLED) Used for AHB bus utilization measurements, the AHB Performance Metric for Stalled Bus Cycles Register counts the number of stalled AHB cycles. This counter increments on a data-phase of the AHB in which the HREADY signal is low, indicating a stalled data transfer. EXAMPLE NumberStalledCycles = HW_DIGCTL_L3_AHB_DATA_STALLED_COUNT_RD(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1512 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM Address: 8001_C000h base + 3E0h offset = 8001_C3E0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_L3_AHB_DATA_STALLED field descriptions Field Description COUNT This field counts the number of AHB cycles in which a master was stalled. 19.4.49 AHB Layer 3 Performance Metric for Valid Bus Cycles Register (HW_DIGCTL_L3_AHB_DATA_CYCLES) Used for AHB bus utilization measurements, the AHB Performance Metric for Valid Bus Cycles Register counts the number of actual AHB cycles in which a data transfer is completed. This field counts the number of AHB cycles in which a master completed a data transfer (a data-phase in which HREADY is high). EXAMPLE StartTime = HW_DIGCTL_HCLKCOUNT_RD(); while(HW_DIGCTL_L3_AHB_DATA_CYCLES.COUNT less than 1000000) { // wait for a specific number of xfers } ElapsedTime = HW_DIGCTL_HCLKCOUNT_RD() - StartTime; Address: 8001_C000h base + 3F0h offset = 8001_C3F0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_L3_AHB_DATA_CYCLES field descriptions Field COUNT Description This field contains the count of AHB bus cycles during which data was actually transferred from a master to a slave or from a slave to a master. 19.4.50 Default First Level Page Table Movable PTE Locator 0 (HW_DIGCTL_MPTE0_LOC) This register is used by the DFLPT to set the location for MPTE0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1513 Programmable Registers When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE0) to any of the 4096 sections. Address: 8001_C000h base + 500h offset = 8001_C500h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE0_LOC field descriptions Field 31 DIS Description Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the 4-values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.51 Default First-Level Page Table Movable PTE Locator 1 (HW_DIGCTL_MPTE1_LOC) This register is used by the DFLPT to set the location for MPTE1. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE1) to any of the 4096 sections. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1514 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM Address: 8001_C000h base + 510h offset = 8001_C510h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE1_LOC field descriptions Field Description 31 DIS Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the 4-values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.52 Default First-Level Page Table Movable PTE Locator 2 (HW_DIGCTL_MPTE2_LOC) This register is used by the DFLPT to set the location for MPTE2. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE2) to any of the 4096 sections. Address: 8001_C000h base + 520h offset = 8001_C520h Bit 31 R W Reset 30 28 27 26 RSVD1 DIS 0 29 0 0 0 25 24 23 22 21 0 0 19 18 17 16 0 0 0 RSVD0 SPAN 0 20 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1515 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 RSVD0 R 0 0 0 4 3 2 1 0 0 0 0 0 1 0 LOC W Reset 5 0 0 0 0 0 0 0 HW_DIGCTL_MPTE2_LOC field descriptions Field Description 31 DIS Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1MB addression within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the 4-values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.53 Default First-Level Page Table Movable PTE Locator 3 (HW_DIGCTL_MPTE3_LOC) This register is used by the DFLPT to set the location for MPTE3. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE3) to any of the 4096 sections. Address: 8001_C000h base + 530h offset = 8001_C530h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1516 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_MPTE3_LOC field descriptions Field Description 31 DIS Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the 4-values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.54 Default First-Level Page Table Movable PTE Locator 4 (HW_DIGCTL_MPTE4_LOC) This register is used by the DFLPT to set the location for MPTE4. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE4) to any of the 4096 sections. Address: 8001_C000h base + 540h offset = 8001_C540h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE4_LOC field descriptions Field 31 DIS 30-27 RSVD1 Description Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1517 Programmable Registers HW_DIGCTL_MPTE4_LOC field descriptions (continued) Field Description 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the 4-values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.55 Default First-Level Page Table Movable PTE Locator 5 (HW_DIGCTL_MPTE5_LOC) This register is used by the DFLPT to set the location for MPTE5. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE5) to any of the 4096 sections. Address: 8001_C000h base + 550h offset = 8001_C550h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 1 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE5_LOC field descriptions Field 31 DIS Description Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1518 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_MPTE5_LOC field descriptions (continued) Field Description a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.56 Default First-Level Page Table Movable PTE Locator 6 (HW_DIGCTL_MPTE6_LOC) This register is used by the DFLPT to set the location for MPTE6. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE6) to any of the 4096 sections. Address: 8001_C000h base + 560h offset = 8001_C560h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE6_LOC field descriptions Field 31 DIS Description Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1519 Programmable Registers HW_DIGCTL_MPTE6_LOC field descriptions (continued) Field Description 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.57 Default First-Level Page Table Movable PTE Locator 7 (HW_DIGCTL_MPTE7_LOC) This register is used by the DFLPT to set the location for MPTE7. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE7) to any of the 4096 sections. Address: 8001_C000h base + 570h offset = 8001_C570h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 1 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE7_LOC field descriptions Field 31 DIS Description Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1520 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_MPTE7_LOC field descriptions (continued) Field Description HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.58 Default First-Level Page Table Movable PTE Locator 8 (HW_DIGCTL_MPTE8_LOC) This register is used by the DFLPT to set the location for MPTE8. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE8) to any of the 4096 sections. Address: 8001_C000h base + 580h offset = 8001_C580h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE8_LOC field descriptions Field 31 DIS Description Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1521 Programmable Registers 19.4.59 Default First-Level Page Table Movable PTE Locator 9 (HW_DIGCTL_MPTE9_LOC) This register is used by the DFLPT to set the location for MPTE9. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE9) to any of the 4096 sections. Address: 8001_C000h base + 590h offset = 8001_C590h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE9_LOC field descriptions Field 31 DIS Description Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.60 Default First-Level Page Table Movable PTE Locator 10 (HW_DIGCTL_MPTE10_LOC) This register is used by the DFLPT to set the location for MPTE10. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1522 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE10) to any of the 4096 sections. Address: 8001_C000h base + 5A0h offset = 8001_C5A0h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 0 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE10_LOC field descriptions Field 31 DIS Description Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.61 Default First-Level Page Table Movable PTE Locator 11 (HW_DIGCTL_MPTE11_LOC) This register is used by the DFLPT to set the location for MPTE11. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE11) to any of the 4096 sections. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1523 Programmable Registers Address: 8001_C000h base + 5B0h offset = 8001_C5B0h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 1 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE11_LOC field descriptions Field Description 31 DIS Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.62 Default First-Level Page Table Movable PTE Locator 12 (HW_DIGCTL_MPTE12_LOC) This register is used by the DFLPT to set the location for MPTE12. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE12) to any of the 4096 sections. Address: 8001_C000h base + 5C0h offset = 8001_C5C0h Bit 31 R W Reset 30 28 27 26 RSVD1 DIS 0 29 0 0 0 25 24 23 22 21 0 0 19 18 17 16 0 0 0 RSVD0 SPAN 0 20 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1524 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM 15 Bit 14 13 12 11 10 9 8 7 6 RSVD0 R 0 0 0 4 3 2 1 0 0 0 1 1 0 0 LOC W Reset 5 0 0 0 0 0 0 0 HW_DIGCTL_MPTE12_LOC field descriptions Field Description 31 DIS Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.63 Default First-Level Page Table Movable PTE Locator 13 (HW_DIGCTL_MPTE13_LOC) This register is used by the DFLPT to set the location for MPTE13. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE13) to any of the 4096 sections. Address: 8001_C000h base + 5D0h offset = 8001_C5D0h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1525 Programmable Registers HW_DIGCTL_MPTE13_LOC field descriptions Field Description 31 DIS Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.64 Default First-Level Page Table Movable PTE Locator 14 (HW_DIGCTL_MPTE14_LOC) This register is used by the DFLPT to set the location for MPTE14. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE14) to any of the 4096 sections. Address: 8001_C000h base + 5E0h offset = 8001_C5E0h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE14_LOC field descriptions Field 31 DIS 30-27 RSVD1 Description Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1526 Freescale Semiconductor, Inc. Chapter 19 Digital Control (DIGCTL) and On-Chip RAM HW_DIGCTL_MPTE14_LOC field descriptions (continued) Field Description 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 Reserved. LOC Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. 19.4.65 Default First-Level Page Table Movable PTE Locator 15 (HW_DIGCTL_MPTE15_LOC) This register is used by the DFLPT to set the location for MPTE15. When using the hardware-based Default First-Level Page Table (DFLPT), program this value to set the location for Movable PTE (MPTE15) to any of the 4096 sections. Address: 8001_C000h base + 5F0h offset = 8001_C5F0h Bit 31 R W Reset Bit 30 29 28 27 26 RSVD1 DIS 25 24 23 22 20 19 18 17 16 RSVD0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 RSVD0 R LOC W Reset 21 0 0 0 0 0 0 0 0 0 0 HW_DIGCTL_MPTE15_LOC field descriptions Field 31 DIS Description Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be modified. 30-27 RSVD1 Reserved. 26-24 SPAN This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN). Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT does not provide any correction mechanism in an overlapped scenario. Because only one value can be set for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1527 Programmable Registers HW_DIGCTL_MPTE15_LOC field descriptions (continued) Field Description a SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC, LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span are contiguous. 23-12 RSVD0 LOC Reserved. Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1528 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller 20.1 OCOTP Overview The on-chip OTP controller (OCOTP) provides the following functions: * Full memory-mapped (restricted) read access of 1.25 Kbit of on-chip OTP ROM. * Data-register programming interface for the 1.25 Kbit of OTP. * Generation of the chip hardware capability bus. * Sources of two security keys that are supplied automatically to the DCP block through private internal busses. * Chip-level pin access to nonrestricted portions of OTP. The OCOTP is connected to the APBH system peripheral bus and is accessible through the ARM core. Read accesses can be performed at the maximum HCLK frequency. Programming/writes can be performed at 24 MHz. There are two security encription keys that are supplied to the DCP block. The first is the Crypto key which is made up of the 128 bits from registers HW_OCOTP_CRYPTO0 through HW_OCOTP_CRYPTO3. The least significant bits are in register 0. The second one is the UNIQUE_KEY. For details of UNIQUE_KEY, see AES OTP Key. The system diagram for the OCOTP is shown below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1529 Operation OCOTP APBH APB Interface HW_OCOTP_CTRL S HW_OCOTP_DATA _ HW/SW / Capability, LOCK and ROM Shadow Regs HW Capability Bus All Blocks Crypto Keys To DCP OTP Controller/State Machine 256x1 OTP 256x1 OTP 256x1 OTP 256x1 OTP 256x1 OTP Test /Pin Interface Figure 20-1. On-Chip OTP (OCOTP) Controller Block Diagram 20.2 Operation The APB interface of the OCOTP provides two functions: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1530 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller * Programmer-model access to registers (see OCOTP Memory Map/Register Definition for register details). These operations require a bank opening sequence through HW_OCOTP_CTRL_RD_BANK_OPEN. * Restricted 32-bit word write/program access to the 1.25 Kbit OTP. The OTP is divided into 32-bit words (40 in total). All of the 40 words are memorymapped to APBH addresses (for reads only). Writes require the use of HW_OCOTP_CTRL_ADDR. The high-level OTP allocation for i.MX28 is shown below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1531 Operation HW_OCOTP_CTRL_ADDR Shadow Regs Pin Access Shadow Regs 0x27 SRK 0x26 SRK 0x25 SRK 0x24 SRK 0x23 SRK 0x22 SRK 0x21 SRK 0x20 SRK 0x1F ROM Use 0x1E ROM Use 0x1D ROM Use 0x1C ROM Use 0x1B ROM Use 0x1A ROM Use 0x19 ROM Use 0x18 ROM Use 0x17 OPS6 0x16 OPS5 0x15 OPS4 0x14 OPS3 0x13 OPS2 0x12 OPS1 0x11 OPS0 0x10 LOCK 0x0F CUSTCap 0x0E SWCap 0x0D HWCap5 0x0C HWCap4 0x0B HWCap3 0x0A HWCap2 0x09 HWCap1 0x08 HWCap0 0x07 CRYPTO KEY 0x06 CRYPTO KEY 0x05 CRYPTO KEY 0x04 CRYPTO KEY 0x03 Customer 0x02 Customer OTP Bank 4 OTP Bank 3 OTP Bank 2 OTP Bank 1 OTP Bank 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Customer 0x01 1532 0x00 Customer Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller OTP reads and writes can be performed on 32-bit words only. For writes, the 32-bit word reflects the write mask, such that bit fields with 0 will not be programmed and bit fields with 1 will be programmed. For OTP random access, the programming interface consists of: * HW_OCOTP_DATA--Data register (32- bit) for OTP programming (writes). * HW_OCOTP_CTRL_ADDR--Address register (6-bit) for OTP programming (writes). * HW_OCOTP_CTRL_BUSY--Programming/write request/status handshake bit. * HW_OCOTP_CTRL_ERROR--Read/write access error status. * HW_OCOTP_CTRL_RD_BANK_OPEN--Status of OTP read availability (reads). 20.2.1 Software Read Sequence Reading OTP contents is relatively simple, because all OTP words are memory-mapped on the APB space (see OCOTP Memory Map/Register Definition for details). These registers are read-only, except for the HW/SW capability, CUSTCAP, ROM and SRK shadow registers, which are writable until the appropriate LOCK bit in OTP is set. Due to the fuse-read architecture, the OTP banks must be open before they can be read. This is accomplished as follows (the following does not apply to shadow registers, which can be read at any time). 1. Program the HCLK to a frequency up to the maximum allowable HCLK frequency. Note that this cannot exceed 200 MHz. 2. Check that HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_ERROR are clear. 3. Set HW_OCOTP_CTRL_RD_BANK_OPEN. This will kick the controller to put the fuses into read mode. The controller will set HW_OCOTP_CTRL_BUSY until the OTP contents are readable. Note that if there was a pending write (holding HW_OCOTP_CTRL_BUSY) and HW_OCOTP_CTRL_RD_BANK_OPEN was set, the controller would complete the write and immediately move into read operation (keeping HW_OCOTP_CTRL_BUSY set while the banks are being opened). 4. Poll for HW_OCOTP_CTRL_BUSY clear. When HW_OCOTP_CTRL_BUSY is clear and HW_OCOTP_CTRL_RD_BANK_OPEN is set, read the data from the appropriate memory-mapped address. Note that this is not necessary for registers that are shadowed. Reading before HW_OCOTP_CTRL_BUSY is cleared by the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1533 Operation controller, will return 0xBADA_BADA and will result in the setting of HW_OCOTP_CTRL_ERROR. Because opening banks takes approximately 33 HCLK cycles, immediate polling for BUSY is not recommended. 5. Once accesses are complete, clear HW_OCOTP_CTRL_RD_BANK_OPEN. Leaving the banks open will cause current drain. If data is accessed from a protected region (such as the crypto key, once a read LOCK bit has been set), the controller returns 0xBADA_BADA. In addition HW_OCOTP_CTRL_ERROR is set. It must be cleared by the software before any new write access can be issued. Subsequent reads to unrestricted mapped OTP locations will still work successfully assuming that HW_OCOTP_CTRL_RD_BANK_OPEN is set and HW_OCOTP_CTRL_BUSY is clear. It should be noted that after opening the banks, read latencies to OTP are instant (meaning they behave like regular reads from hardware registers), since parallel loading is used. It should also be noted that setting HW_OCOTP_CTRL_RELOAD_SHADOWS to reload shadow registers does not set HW_OCOTP_CTRL_RD_BANK_OPEN. HW_OCOTP_CTRL_RD_BANK_OPEN can only be set and cleared by software. Forced reloading of shadows is covered in Shadow Registers and Hardware Capability Bus. 20.2.2 Software Write Sequence In order to avoid erroneous code performing erroneous writes to OTP, a special unlocking sequence is required for writes. 1. Program HCLK to 24 MHz. OTP writes do not work at frequencies above 24 MHz. 2. Set the VDDIO voltage to 2.8 V (using HW_POWER_VDDIOCTRL_TRG). The VDDIO voltage is used to program OTP. Incorrect voltage and frequency settings will result in the OTP being programmed with incorrect values. 3. Check that HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_ERROR are clear. Overlapped accesses are not supported by the controller. Any pending write must be completed before a write access can be requested. In addition, the banks cannot be open for reading, so HW_OCOTP_CTRL_RD_BANK_OPEN must also be clear. If the write is done following a previous write, the postamble wait period of 2 s must be followed after clearing the HW_OCOTP_CTRL_BUSY (see Write Postamble). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1534 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller 4. Write the requested address to HW_OCOTP_CTRL_ADDR and program the unlock code into HW_OCOTP_CTRL_WR_UNLOCK. This must be programmed for each write access. The lock code is documented in the register description. Both the unlock code and address can be written in the same operation. 5. Write the data to HW_OCOTP_DATA. This automatically sets HW_OCOTP_CTRL_BUSY and clears HW_OCOTP_CTRL_WR_UNLOCK. In this case, the data is a programming mask. Bit fields with ones will result in that OTP bit being set. Only the controller can clear HW_OCOTP_CTRL_BUSY. The controller will use the mask to program a 32-bit word in the OTP per the address in ADDR. At the same time that the write is accepted, the controller makes an internal copy of HW_OCOTP_CTRL_ADDR that cannot be updated until the next write sequence is initiated. This copy guarantees that erroneous writes to HW_OCOTP_CTRL_ADDR will not affect an active write operation. It should also be noted that, during programming, HW_OCOTP_DATA will shift right (with zero fill). This shifting is required to program the OTP serially. During the write operation, HW_OCOTP_DATA cannot be modified. 6. Once complete, the controller clears BUSY. Beyond this, the 2-s postamble requirement must be met before submitting any further OTP operations (see Write Postamble). A write request to a protected region will result in no OTP access and no setting of HW_OCOTP_CTRL_BUSY. In addition, HW_OCOTP_CTRL_ERROR will be set. It must be cleared by software before any new write access can be issued. It should be noted that write latencies to OTP are in the order of 10s to 100s of microseconds per word. Write latencies will vary based on the location of the word within the OTP bank. Once a write is initiated, HW_OCOTP_DATA is shifted one bit per every 32 HCLK cycles. Given: 8 words per OTP bank 32 bits per word tHCLK is the HCLK clock period n word locations (where 0 n 7) Then, the approximate write latency for a given word is: tHCLK * 32 * 32 * n In addition to this latency, software must allow for the 2-s postamble (using HW_DIGCTL_MICROSECONDS), as described in Write Postamble i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1535 Operation 20.2.3 Write Postamble Due to internal electrical characteristics of the OTP during writes, all OTP operations following a write must be separated by 2 s after the clearing of HW_OCOTP_CTRL_BUSY following the write. This guarantees programming voltages on-chip to reach a steady state when exiting a write sequence. This includes reads, shadow reloads, or other writes. A recommended software sequence to meet the postamble requirements is as follows: 1. Issue the write and poll for BUSY (as per Software Write Sequence). 2. Once BUSY is clear, use HW_DIGCTL_MICROSECONDS to wait 2 s. 3. Perform the next OTP operation. 20.2.4 Shadow Registers and Hardware Capability Bus The on-chip hardware capability bus is generated using a direct connection to the shadow registers HW_OCOTP_HWCAP0-5 and HW_OCOTP_HWSWCAP. The bits are copied from the OTP on reset. They can be modified until either HW_OCOTP_LOCK_HWSW_SHADOW or HW_OCOTP_LOCK_HWSW_SHADOW_ALT is set. In addition, HW_OCOTP_SWCAP and HW_OCOTP_LOCK are also shadowed into physical registers immediately after reset. The user can force a reload of the shadow registers (including HW_OCOTP_LOCK) without having to reset the device, which is useful for debugging code. To force a reload: * Set HW_OCOTP_CTRL_RELOAD_SHADOWS. * Wait for HW_OCOTP_CTRL_BUSY and HW_OCOTP_CTRL_RELOAD_SHADOWS to be cleared by the controller. * Attempting to write to the shadow registers while the shadows are being reloaded will result in the setting of HW_OCOTP_CTRL_ERROR. In addition, the register will not take the attempted write (yielding to the reload instead). * Attempting to write to a shadow register that is locked will result in the setting of HW_OCOTP_CTRL_ERROR. HW_OCOTP_CTRL_RELOAD_SHADOWS can be set at any time. There is no need to wait for HW_OCOTP_CTRL_BUSY or HW_OCOTP_CTRL_ERROR to be clear. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1536 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller * In the case of HW_OCOTP_CTRL_BUSY being set due to an active write, the controller will perform the bank opening and shadow reloading immediately after the completion of the write. * In the case where HW_OCOTP_CTRL_RD_BANK_OPEN is set, the shadow reload will be performed immediately after the banks are closed by the software (by clearing HW_OCOTP_CTRL_RD_BANK_OPEN). It should be noted that BUSY will take approximately 33 HCLK cycles to clear, so polling for HW_OCOTP_CTRL_BUSY immediately after clearing HW_OCOTP_CTRL_RD_BANK_OPEN is not recommended. * In all cases, the controller will clear HW_OCOTP_CTRL_RELOAD_SHADOWS after the successful completion of the operation. 20.3 Behavior During Reset The OCOTP is always active. The shadow registers described in OCOTP Memory Map/ Register Definition automatically load the appropriate OTP contents after reset is deasserted. During this load-time HW_OCOTP_CTRL_BUSY is set. The load time is approximately 32 HCLK cycles after the deassertion of reset. These shadow registers can be reloaded as described in Shadow Registers and Hardware Capability Bus. 20.4 OCOTP Memory Map/Register Definition OCOTP Hardware Register Format Summary HW_OCOTP memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8002_C000 OTP Controller Control Register (HW_OCOTP_CTRL) 32 R/W 0000_0000h 20.4.1/1539 8002_C010 OTP Controller Write Data Register (HW_OCOTP_DATA) 32 R/W 0000_0000h 20.4.2/1541 8002_C020 Value of OTP Bank0 Word0 (Customer) (HW_OCOTP_CUST0) 32 R 0000_0000h 20.4.3/1542 8002_C030 Value of OTP Bank0 Word1 (Customer) (HW_OCOTP_CUST1) 32 R 0000_0000h 20.4.4/1542 8002_C040 Value of OTP Bank0 Word2 (Customer) (HW_OCOTP_CUST2) 32 R 0000_0000h 20.4.5/1543 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1537 OCOTP Memory Map/Register Definition HW_OCOTP memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8002_C050 Value of OTP Bank0 Word3 (Customer) (HW_OCOTP_CUST3) 32 R 0000_0000h 20.4.6/1543 8002_C060 Value of OTP Bank0 Word4 (Crypto Key) (HW_OCOTP_CRYPTO0) 32 R 0000_0000h 20.4.7/1544 8002_C070 Value of OTP Bank0 Word5 (Crypto Key) (HW_OCOTP_CRYPTO1) 32 R 0000_0000h 20.4.8/1544 8002_C080 Value of OTP Bank0 Word6 (Crypto Key) (HW_OCOTP_CRYPTO2) 32 R 0000_0000h 20.4.9/1545 8002_C090 Value of OTP Bank0 Word7 (Crypto Key) (HW_OCOTP_CRYPTO3) 32 R 0000_0000h 20.4.10/ 1546 8002_C0A0 HW Capability Shadow Register 0 (HW_OCOTP_HWCAP0) 32 R/W 0000_0000h 20.4.11/ 1546 8002_C0B0 HW Capability Shadow Register 1 (HW_OCOTP_HWCAP1) 32 R/W 0000_0000h 20.4.12/ 1547 8002_C0C0 HW Capability Shadow Register 2 (HW_OCOTP_HWCAP2) 32 R/W 0000_0000h 20.4.13/ 1547 8002_C0D0 HW Capability Shadow Register 3 (HW_OCOTP_HWCAP3) 32 R/W 0000_0000h 20.4.14/ 1547 8002_C0E0 HW Capability Shadow Register 4 (HW_OCOTP_HWCAP4) 32 R/W 0000_0000h 20.4.15/ 1548 8002_C0F0 HW Capability Shadow Register 5 (HW_OCOTP_HWCAP5) 32 R/W 0000_0000h 20.4.16/ 1548 8002_C100 SW Capability Shadow Register (HW_OCOTP_SWCAP) 32 R/W 0000_0000h 20.4.17/ 1549 8002_C110 Customer Capability Shadow Register (HW_OCOTP_CUSTCAP) 32 R/W 0000_0000h 20.4.18/ 1549 8002_C120 LOCK Shadow Register OTP Bank 2 Word 0 (HW_OCOTP_LOCK) 32 R 0000_0000h 20.4.19/ 1551 8002_C130 Value of OTP Bank2 Word1 (Freescale OPS0) (HW_OCOTP_OPS0) 32 R 0000_0000h 20.4.20/ 1555 8002_C140 Value of OTP Bank2 Word2 (Freescale OPS1) (HW_OCOTP_OPS1) 32 R 0000_0000h 20.4.21/ 1555 8002_C150 Value of OTP Bank2 Word3 (Freescale OPS2) (HW_OCOTP_OPS2) 32 R 0000_0000h 20.4.22/ 1556 8002_C160 Value of OTP Bank2 Word4 (Freescale OPS3) (HW_OCOTP_OPS3) 32 R 0000_0000h 20.4.23/ 1556 8002_C170 Value of OTP Bank2 Word5 Freescale OPS4 (HW_OCOTP_OPS4) 32 R 0000_0000h 20.4.24/ 1557 8002_C180 Value of OTP Bank2 Word6 Freescale OPS5 (HW_OCOTP_OPS5) 32 R 0000_0000h 20.4.25/ 1557 8002_C190 Value of OTP Bank2 Word7 Freescale OPS6 (HW_OCOTP_OPS6) 32 R 0000_0000h 20.4.26/ 1558 8002_C1A0 Shadow Register for OTP Bank3 Word0 (ROM Use 0) (HW_OCOTP_ROM0) 32 R/W 0000_0000h 20.4.27/ 1558 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1538 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller HW_OCOTP memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8002_C1B0 Shadow Register for OTP Bank3 Word1 (ROM Use 1) (HW_OCOTP_ROM1) 32 R/W 0000_0000h 20.4.28/ 1561 8002_C1C0 Shadow Register for OTP Bank3 Word2 (ROM Use 2) (HW_OCOTP_ROM2) 32 R/W 0000_0000h 20.4.29/ 1564 8002_C1D0 Shadow Register for OTP Bank3 Word3 (ROM Use 3) (HW_OCOTP_ROM3) 32 R/W 0000_0000h 20.4.30/ 1564 8002_C1E0 Shadow Register for OTP Bank3 Word4 (ROM Use 4) (HW_OCOTP_ROM4) 32 R/W 0000_0000h 20.4.31/ 1565 8002_C1F0 Shadow Register for OTP Bank3 Word5 (ROM Use 5) (HW_OCOTP_ROM5) 32 R/W 0000_0000h 20.4.32/ 1567 8002_C200 Shadow Register for OTP Bank3 Word6 (ROM Use 6) (HW_OCOTP_ROM6) 32 R/W 0000_0000h 20.4.33/ 1567 8002_C210 Shadow Register for OTP Bank3 Word7 (ROM Use 7) (HW_OCOTP_ROM7) 32 R/W 0000_0000h 20.4.34/ 1568 8002_C220 Shadow Register for OTP Bank4 Word0 (Data Use 0) (HW_OCOTP_SRK0) 32 R/W 0000_0000h 20.4.35/ 1570 8002_C230 Shadow Register for OTP Bank4 Word1 (Data Use 1) (HW_OCOTP_SRK1) 32 R/W 0000_0000h 20.4.36/ 1571 8002_C240 Shadow Register for OTP Bank4 Word2 (Data Use 2) (HW_OCOTP_SRK2) 32 R/W 0000_0000h 20.4.37/ 1571 8002_C250 Shadow Register for OTP Bank4 Word3 (Data Use 3) (HW_OCOTP_SRK3) 32 R/W 0000_0000h 20.4.38/ 1572 8002_C260 Shadow Register for OTP Bank4 Word4 (Data Use 4) (HW_OCOTP_SRK4) 32 R/W 0000_0000h 20.4.39/ 1572 8002_C270 Shadow Register for OTP Bank4 Word5 (Data Use 5) (HW_OCOTP_SRK5) 32 R/W 0000_0000h 20.4.40/ 1573 8002_C280 Shadow Register for OTP Bank4 Word6 (Data Use 6) (HW_OCOTP_SRK6) 32 R/W 0000_0000h 20.4.41/ 1573 8002_C290 Shadow Register for OTP Bank4 Word7 (Data Use 7) (HW_OCOTP_SRK7) 32 R/W 0000_0000h 20.4.42/ 1574 32 R 0105_0000h 20.4.43/ 1574 8002_C2A0 OTP Controller Version Register (HW_OCOTP_VERSION) 20.4.1 OTP Controller Control Register (HW_OCOTP_CTRL) The OCOTP Control and Status Register specifies the copy state, as well as the control required for random access of the OTP memory HW_OCOTP_CTRL: 0x000 HW_OCOTP_CTRL_SET: 0x004 HW_OCOTP_CTRL_CLR: 0x008 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1539 OCOTP Memory Map/Register Definition HW_OCOTP_CTRL_TOG: 0x00C The OCOTP Control and Status Register provides the necessary software interface for performing read and write operations to the On-Chip OTP (One-Time Programmable ROM). The control fields such as WR_UNLOCK, ADDR and BUSY/ERROR may be used in conjunction with the HW_OCOTP_DATA register to perform write operations. Read operations are performed through the direct memory mapped registers. In the cases where OTP values are shadowed into local memory storage, the memory mapped location can be read directly. In the cases where the OTP values are not shadowed into local memory, the read-preparation sequence involving RD_BANK_OPEN and BUSY/ ERROR fields must be used before performing the read. Address: 8002_C000h base + 0h offset = 8002_C000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R WR_UNLOCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD2 0 0 0 0 0 BUSY R 0 RSRVD1 RSRVD0 ERROR Bit 0 RD_BANK_OPEN Reset RELOAD_SHADOWS W ADDR W Reset 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1540 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller HW_OCOTP_CTRL field descriptions Field Description 31-16 WR_UNLOCK Write 0x3E77 to enable OTP write accesses. NOTE: This register must be unlocked on a write-by-write basis (a write is initiated when HW_OCOTP_DATA is written), so the UNLOCK bitfield must contain the correct key value during all writes to HW_OCOTP_DATA, otherwise a write shall not be initiated. This field is automatically cleared after a successful write completion (clearing of BUSY). 0x3E77 15-14 RSRVD2 KEY -- Key needed to unlock HW_OCOTP_DATA register. These bits always read back zero. 13 RELOAD_ SHADOWS Set to force re-loading the shadow registers (HW/SW capability and LOCK). This operation will automatically open banks (but will not set RD_BANK_OPEN) and set BUSY. Once the shadow registers have been re-loaded, BUSY and RELOAD_SHADOWS are automatically cleared by the controller. There is no need to set RD_BANK_OPEN to force the reload. If RD_BANK_OPEN is already set, its still possible to set RELOAD_SHADOWS. In this case, the shadow registers will only be updated upon the clearing of RD_BANK_OPEN. 12 RD_BANK_ OPEN Set to open the all the OTP banks for reading. When set, the controller sets BUSY to allow time for the banks to become available (approximately 32 HCLK cycles later at which time the controller will clear BUSY). Once BUSY is clear, the various OTP words are accessible through their memory mapped address. Note that OTP words which are shadowed, can be read at anytime and will not be affected by RD_BANK_OPEN. This bit must be cleared after reading is complete. Keeping the OTP banks open causes additional current draw. BUSY must be clear before this setting will take affect. If there is a write transaction pending (holding BUSY), then the bank opening sequence will begin automatically upon the previous transaction clears BUSY. Note that if a read is performed from non-shadowed locations without RD_BANK_OPEN, ERROR will be set 11-10 RSRVD1 These bits always read back zero. 9 ERROR Set by the controller when either an access to a locked region is requested or a read is requested from non-shadowed efuse locations without the banks being open. Must be cleared before any further write access can be performed. This bit can only be set by the controller. This bit is also set if the Pin interface is active and software requests an access to the OTP. In this instance, the ERROR bit cannot be cleared until the Pin interface access has completed. Reset this bit by writing a one to the SCT clear address space and not by a general write. 8 BUSY 7-6 RSRVD0 ADDR OTP controller status bit. When active, no new write access or bank open operations (including RELOAD_SHADOWS) can be performed. Cleared by controller when access complete (for writes), or the banks are open (for reads). After reset (or after setting RELOAD_SHADOWS), this bit is set by the controller until the HW/SW and LOCK registers are successfully copied, after which time it is automatically cleared by the controller. These bits always read back zero. OTP write access address register. Specifies one of 40 word address locations (0x00 - 0x27). If a valid write is accepted by the controller (see HW_OCOTP_DATA for details on what constitutes a valid write), the controller makes an internal copy of this value (to avoid the OTP programming being corrupted). This internal copy will not update until the write access is complete. 20.4.2 OTP Controller Write Data Register (HW_OCOTP_DATA) The OCOTP Data Register is used for OTP Programming This register is used in conjunction with HW_OCOTP_CTRL to perform one-time writes to the OTP. See the Software Write Sequence section for operating details. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1541 OCOTP Memory Map/Register Definition Address: 8002_C000h base + 10h offset = 8002_C010h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_DATA field descriptions Field Description DATA Used to initiate a write to OTP. To blow a fuse bit, the "1" shall be written through this data register 20.4.3 Value of OTP Bank0 Word0 (Customer) (HW_OCOTP_CUST0) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Non-shadowed memory mapped access to OTP Bank 0, word 0 (ADDR = 0x00). Address: 8002_C000h base + 20h offset = 8002_C020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_CUST0 field descriptions Field BITS Description Reflects value of OTP Bank 0, word 0 (ADDR = 0x00) 20.4.4 Value of OTP Bank0 Word1 (Customer) (HW_OCOTP_CUST1) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Non-shadowed memory mapped access to OTP Bank 0, word 1 (ADDR = 0x01). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1542 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller Address: 8002_C000h base + 30h offset = 8002_C030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_CUST1 field descriptions Field Description BITS Reflects value of OTP Bank 0, word 1 (ADDR = 0x01) 20.4.5 Value of OTP Bank0 Word2 (Customer) (HW_OCOTP_CUST2) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Non-shadowed memory mapped access to OTP Bank 0, word 2 (ADDR = 0x02). Address: 8002_C000h base + 40h offset = 8002_C040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_CUST2 field descriptions Field BITS Description Reflects value of OTP Bank 0, word 2 (ADDR = 0x02) 20.4.6 Value of OTP Bank0 Word3 (Customer) (HW_OCOTP_CUST3) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Non-shadowed memory mapped access to OTP Bank 0, word 3 (ADDR = 0x03). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1543 OCOTP Memory Map/Register Definition Address: 8002_C000h base + 50h offset = 8002_C050h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_CUST3 field descriptions Field Description BITS Reflects value of OTP Bank 0, word 3 (ADDR = 0x03) 20.4.7 Value of OTP Bank0 Word4 (Crypto Key) (HW_OCOTP_CRYPTO0) OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Non-shadowed memory mapped access to OTP Bank 0, word 4 (ADDR = 0x04). Address: 8002_C000h base + 60h offset = 8002_C060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_CRYPTO0 field descriptions Field BITS Description Reflects value of OTP Bank 0, word 4 (ADDR = 0x04). If HW_OCOTP_LOCK[CRYPTOKEY] is set, returns 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR] 20.4.8 Value of OTP Bank0 Word5 (Crypto Key) (HW_OCOTP_CRYPTO1) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1544 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller Non-shadowed memory mapped access to OTP Bank 0, word 5 (ADDR = 0x05). Address: 8002_C000h base + 70h offset = 8002_C070h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_CRYPTO1 field descriptions Field Description BITS Reflects value of OTP Bank 0, word 5 (ADDR = 0x05). If HW_OCOTP_LOCK[CRYPTOKEY] is set, returns 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR] 20.4.9 Value of OTP Bank0 Word6 (Crypto Key) (HW_OCOTP_CRYPTO2) OTP banks must be open via HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Non-shadowed memory mapped access to OTP Bank 0, word 6 (ADDR = 0x06). Address: 8002_C000h base + 80h offset = 8002_C080h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_CRYPTO2 field descriptions Field BITS Description Reflects value of OTP Bank 0, word 6 (ADDR = 0x06). If HW_OCOTP_LOCK[CRYPTOKEY] is set, returns 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR] i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1545 OCOTP Memory Map/Register Definition 20.4.10 Value of OTP Bank0 Word7 (Crypto Key) (HW_OCOTP_CRYPTO3) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Non-shadowed memory mapped access to OTP Bank 0, word 7 (ADDR = 0x07). Address: 8002_C000h base + 90h offset = 8002_C090h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_CRYPTO3 field descriptions Field Description BITS Reflects value of OTP Bank 0, word 7 (ADDR = 0x07). If HW_OCOTP_LOCK[CRYPTOKEY] is set, returns 0xBADA_BADA and sets HW_OCOTP_CTRL[ERROR] 20.4.11 HW Capability Shadow Register 0 (HW_OCOTP_HWCAP0) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 0 (ADDR = 0x08). Address: 8002_C000h base + A0h offset = 8002_C0A0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_HWCAP0 field descriptions Field BITS Description Shadow register for HW capability bits 31:0 (copy of OTP bank 1, word 0 (ADDR = 0x08)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1546 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller 20.4.12 HW Capability Shadow Register 1 (HW_OCOTP_HWCAP1) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 1 (ADDR = 0x09). Address: 8002_C000h base + B0h offset = 8002_C0B0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_HWCAP1 field descriptions Field Description BITS Shadow register for HW capability bits 63:32 (copy of OTP bank 1, word 1 (ADDR = 0x09)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. 20.4.13 HW Capability Shadow Register 2 (HW_OCOTP_HWCAP2) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 2 (ADDR = 0x0A). Address: 8002_C000h base + C0h offset = 8002_C0C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_HWCAP2 field descriptions Field BITS Description Shadow register for HW capability bits 95:64 (copy of OTP bank 1, word 2 (ADDR = 0x0A)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. 20.4.14 HW Capability Shadow Register 3 (HW_OCOTP_HWCAP3) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1547 OCOTP Memory Map/Register Definition Shadowed memory mapped access to OTP bank 1, word 3 (ADDR = 0x0B). Address: 8002_C000h base + D0h offset = 8002_C0D0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_HWCAP3 field descriptions Field Description BITS Shadow register for HW capability bits 127:96 (copy of OTP bank 1, word 3 (ADDR = 0x0B)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. 20.4.15 HW Capability Shadow Register 4 (HW_OCOTP_HWCAP4) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 4 (ADDR = 0x0C). Address: 8002_C000h base + E0h offset = 8002_C0E0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_HWCAP4 field descriptions Field Description BITS Shadow register for HW capability bits 159:128 (copy of OTP bank 1, word 4 (ADDR = 0x0C)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. 20.4.16 HW Capability Shadow Register 5 (HW_OCOTP_HWCAP5) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 5 (ADDR = 0x0D). Address: 8002_C000h base + F0h offset = 8002_C0F0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1548 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller HW_OCOTP_HWCAP5 field descriptions Field Description BITS Shadow register for HW capability bits 191:160 (copy of OTP bank 1, word 5 (ADDR = 0x0D)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. 20.4.17 SW Capability Shadow Register (HW_OCOTP_SWCAP) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 6 (ADDR = 0x0E). Address: 8002_C000h base + 100h offset = 8002_C100h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_SWCAP field descriptions Field BITS Description Shadow register for SW capability bits 31:0 (copy of OTP bank 1, word 6 (ADDR = 0x0E)). These bits become read-only after the HW_OCOTP_LOCK[HWSW_SHADOW] or HW_OCOTP_LOCK[HWSW_SHADOW_ALT] bit is set. 20.4.18 Customer Capability Shadow Register (HW_OCOTP_CUSTCAP) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 1, word 7 (ADDR = 0x0F). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1549 OCOTP Memory Map/Register Definition Address: 8002_C000h base + 110h offset = 8002_C110h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 Bit 0 RTC_XTAL_32000_PRESENT Reset RTC_XTAL_32768_PRESENT W 0 0 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 HW_OCOTP_CUSTCAP field descriptions Field 31-3 RSRVD1 Description Reserved - do not blow these bits. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1550 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller HW_OCOTP_CUSTCAP field descriptions (continued) Field Description 2 RTC_XTAL_ 32768_ PRESENT Blow to indicate the presence of an optional 32.768KHz off-chip oscillator. 1 RTC_XTAL_ 32000_ PRESENT Blow to indicate the presence of an optional 32.000KHz off-chip oscillator. 0 RSRVD0 Reserved - do not blow these bits. 20.4.19 LOCK Shadow Register OTP Bank 2 Word 0 (HW_OCOTP_LOCK) Shadow register for OCOTP Lock Status Value (ADDR = 0x10). Copy of the state of the OTP lock regions. Copied from the OTP upon reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS] Shadowed memory mapped access to OTP bank 2, word 0 (ADDR = 0x10). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1551 OCOTP Memory Map/Register Definition 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ROM5 ROM4 ROM3 ROM2 ROM1 ROM0 HWSW_SHADOW_ALT CRYPTODCP_ALT CRYPTOKEY_ALT PIN OPS UN2 UN1 UN0 R 31 ROM6 Bit ROM7 Address: 8002_C000h base + 120h offset = 8002_C120h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1552 Freescale Semiconductor, Inc. 10 9 8 7 6 5 4 3 2 1 0 UNALLOCATED HWSW CUSTCAP_SHADOW HWSW_SHADOW CRYPTODCP CRYPTOKEY CUST3 CUST2 CUST1 CUST0 SRK 11 CUSTCAP R 12 ROM_SHADOW 15 Bit SRK_SHADOW Chapter 20 On-Chip OTP (OCOTP) Controller 14 13 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 HW_OCOTP_LOCK field descriptions Field Description 31 ROM7 Status of ROM use region write lock bits (ADDR = 0x1F). When set, word 0x1F in the ROM region is locked. 30 ROM6 Status of ROM use region write lock bits (ADDR = 0x1E). When set, word 0x1E in the ROM region is locked. 29 ROM5 Status of ROM use region write lock bits (ADDR = 0x1D). When set, word 0x1D in the ROM region is locked. 28 ROM4 Status of ROM use region write lock bits (ADDR = 0x1C). When set, word 0x1C in the ROM region is locked. 27 ROM3 Status of ROM use region write lock bits (ADDR = 0x1B). When set, word 0x1B in the ROM region is locked. 26 ROM2 Status of ROM use region write lock bits (ADDR = 0x1A). When set, word 0x1A in the ROM region is locked. 25 ROM1 Status of ROM use region write lock bits (ADDR = 0x19). When set, word 0x19 in the ROM region is locked. 24 ROM0 Status of ROM use region write lock bits (ADDR = 0x18). When set, word 0x18 in the ROM region is locked. 23 HWSW_ SHADOW_ALT Status of alternate bit for HWSW_SHADOW lock Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1553 OCOTP Memory Map/Register Definition HW_OCOTP_LOCK field descriptions (continued) Field Description 22 CRYPTODCP_ ALT Status of alternate bit for CRYPTODCP lock 21 CRYPTOKEY_ ALT Status of alternate bit for CRYPTOKEY lock 20 PIN Status of Pin access lock bit. When set, pin access is disabled. 19 OPS Status of OPS region (ADDR = 0x11-0x14) write lock bit. When set, region is locked. 18 UN2 Status of un-assigned (ADDR = 0x17) write-lock bit. When set, un-asigned word at OTP address 0x17 is locked. 17 UN1 Status of un-assigned (ADDR = 0x16) write-lock bit. When set, un-asigned word at OTP address 0x16 is locked. 16 UN0 Status of un-assigned (ADDR = 0x15) write-lock bit. When set, un-asigned word at OTP address 0x15 is locked. 15 SRK Status of SRK bank (ADDR = 0x20-0x27) write-lock bit. When set, the 8 words (bank4) at OTP addresses 0x20-0x27 are locked. 14-12 Value of un-used portion of LOCK word UNALLOCATED 11 Status of SRK region shadow register lock. When set, over-ride of DATA-region shadow bits is blocked. SRK_SHADOW 10 Status of ROM region shadow register lock. When set, over-ride of ROM-region shadow bits is blocked. ROM_SHADOW 9 CUSTCAP 8 HWSW Status of Customer Capability region (ADDR = 0x0F) write lock bit. When set, region is locked. Status of HW/SW region (ADDR = 0x08-0x0E) write lock bit. When set, region is locked. 7 CUSTCAP_ SHADOW Status of Customer Capability shadow register lock. When set, over-ride of customer capabality shadow bits is blocked. 6 HWSW_ SHADOW Status of HW/SW Capability shadow register lock. When set, over-ride of HW/SW capabality shadow bits is blocked. 5 CRYPTODCP Status of read lock bit for DCP APB crypto access. When set, the DCP will disallow reads of its crypto keys through its APB interface. 4 CRYPTOKEY Status of crypto key region (ADDR = 0x04-0x07) read/write lock bit. When set, region is locked. 3 CUST3 Status of customer region word (ADDR = 0x03) write lock bit. When set, the region is locked. 2 CUST2 Status of customer region word (ADDR = 0x02) write lock bit. When set, the region is locked. 1 CUST1 Status of customer region word (ADDR = 0x01) write lock bit. When set, the region is locked. 0 CUST0 Status of customer region word (ADDR = 0x00) write lock bit. When set, the region is locked. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1554 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller 20.4.20 Value of OTP Bank2 Word1 (Freescale OPS0) (HW_OCOTP_OPS0) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Shadowed memory mapped access to OTP Bank 2, word 1 (ADDR = 0x11). Address: 8002_C000h base + 130h offset = 8002_C130h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_OPS0 field descriptions Field Description BITS Reflects value of OTP Bank 2, word 1 (ADDR = 0x11). OPS0 is not used on i.MX28. 20.4.21 Value of OTP Bank2 Word2 (Freescale OPS1) (HW_OCOTP_OPS1) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Shadowed memory mapped access to OTP Bank 2, word 2 (ADDR = 0x12). Address: 8002_C000h base + 140h offset = 8002_C140h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1555 OCOTP Memory Map/Register Definition HW_OCOTP_OPS1 field descriptions Field Description BITS Reflects value of OTP Bank 2, word 2 (ADDR = 0x12). OPS1 is reserved for Freescale internal use. 20.4.22 Value of OTP Bank2 Word3 (Freescale OPS2) (HW_OCOTP_OPS2) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Shadowed memory mapped access to OTP Bank 2, word 3 (ADDR = 0x13). Address: 8002_C000h base + 150h offset = 8002_C150h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_OPS2 field descriptions Field Description BITS Reflects value of OTP Bank 2, word 3 (ADDR = 0x13). It contains the most significant 32 bits of the unique id for every chip. It is used to form the UNIQUE_KEY. 20.4.23 Value of OTP Bank2 Word4 (Freescale OPS3) (HW_OCOTP_OPS3) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Shadowed memory mapped access to OTP Bank 2, word 4 (ADDR = 0x14). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1556 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller Address: 8002_C000h base + 160h offset = 8002_C160h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_OPS3 field descriptions Field Description BITS Reflects value of OTP Bank 2, word 4 (ADDR = 0x14). It contains the least significant 32 bits of the unique id for every chip. 20.4.24 Value of OTP Bank2 Word5 Freescale OPS4 (HW_OCOTP_OPS4) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Non-shadowed memory mapped access to OTP Bank 2, word 5 (ADDR = 0x15). Address: 8002_C000h base + 170h offset = 8002_C170h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_OPS4 field descriptions Field BITS Description Reflects value of OTP Bank 2, word 5 (ADDR = 0x15). OPS4 is not used in i.MX28. 20.4.25 Value of OTP Bank2 Word6 Freescale OPS5 (HW_OCOTP_OPS5) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1557 OCOTP Memory Map/Register Definition Non-shadowed memory mapped access to OTP Bank 2, word 6 (ADDR = 0x16). Address: 8002_C000h base + 180h offset = 8002_C180h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_OPS5 field descriptions Field Description BITS Reflects value of OTP Bank 2, word 6 (ADDR = 0x16). OPS5 is not used in i.MX28. 20.4.26 Value of OTP Bank2 Word7 Freescale OPS6 (HW_OCOTP_OPS6) OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN] set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR] being set and 0xBADA_BADA being returned. Non-shadowed memory mapped access to OTP Bank 2, word 7 (ADDR = 0x17). Address: 8002_C000h base + 190h offset = 8002_C190h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_OPS6 field descriptions Field BITS Description Reflects value of OTP Bank 2, word 7 (ADDR = 0x17). OPS6 value is duplicate of that of OPS3. It is used to form the UNIQUE_KEY. 20.4.27 Shadow Register for OTP Bank3 Word0 (ROM Use 0) (HW_OCOTP_ROM0) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 0 (ADDR = 0x18). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1558 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller Address: 8002_C000h base + 1A0h offset = 8002_C1A0h 31 30 29 28 27 26 25 24 23 22 21 SD_POWER_GATE_GPIO R SD_MMC_ MODE BOOT_MODE 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENABLE_USB_BOOT_SERIAL_NUM ENABLE_UNENCRYPTED_BOOT RSRVD0 SD_POWER_UP_DELAY DISABLE_SPI_NOR_FAST_READ Bit 19 EMMC_USE_DDR W Reset 20 0 0 0 0 0 R SD_ POWER_ UP_DELAY SD_BUS_ WIDTH SSP_SCK_INDEX DISABLE_RECOVERY_MODE Bit USE_ALT_ DEBUG_ UART_PINS W Reset 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1559 OCOTP Memory Map/Register Definition HW_OCOTP_ROM0 field descriptions Field 31-24 BOOT_MODE Description Encoded boot mode. 23-22 SD/MMC BOOT MODE SD_MMC_MODE 00 MBR BOOT 01 Reserved 10 eMMC 4.3 Fast Boot 11 eSD2.1 Fast Boot 21-20 SD_POWER_ GATE_GPIO SD card power gate GPIO pin select: 00 - PWM3, 01 - PWM4, 10 - LCD_DOTCLK, 11 - NO_GATE. 19-14 SD card power up delay required after enabling GPIO power gate: 000000 - 0 ms, 000001 - 10 ms, SD_POWER_UP_ 000010 - 20 ms, 111111 - 630 ms. DELAY 13-12 SD card bus width: 00 - 4-bit, 01 - 1-bit, 10 - 8-bit, 11 - reserved. SD_BUS_WIDTH 11-8 Index to the SSP clock speed SSP_SCK_INDEX 0000 - invalid 0001 - 240kHz 0010 - 1Mhz 0011 - 2Mhz 0100 - 4Mhz 0101 - 6Mhz 0110 - 8Mhz 0111 - 10Mhz 1000 - 12Mhz 1001 - 16Mhz 1010 - 20Mhz 1011 - 30Mhz 1100 - 40Mhz 1101 - 48Mhz 1110 - 51.4Mhz (Max Frequency) 1111 - invalid 7 Blow to operate eMMC4.4 card in DDR mode. EMMC_USE_DDR 6 DISABLE_SPI_ NOR_FAST_ READ Blow to disable SPI NOR fast reads which are used by default. 5 Blow to enable USB boot serial number. ENABLE_USB_ BOOT_SERIAL_ NUM Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1560 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller HW_OCOTP_ROM0 field descriptions (continued) Field Description 4 Blow to enable unencrypted boot modes. ENABLE_ UNENCRYPTED_ BOOT 3 RSRVD0 Reserved - do not blow this bit. 2 DISABLE_ RECOVERY_ MODE Blow to disable recovery boot mode. USE_ALT_ DEBUG_UART_ PINS 00-PWM; 01-AUART0; 10-I2C0; 11-Reserved; 20.4.28 Shadow Register for OTP Bank3 Word1 (ROM Use 1) (HW_OCOTP_ROM1) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 1 (ADDR = 0x19). 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ENABLE_NAND6_CE_RDY_PULLUP ENABLE_NAND5_CE_RDY_PULLUP ENABLE_NAND4_CE_RDY_PULLUP ENABLE_NAND3_CE_RDY_PULLUP ENABLE_NAND2_CE_RDY_PULLUP ENABLE_NAND1_CE_RDY_PULLUP ENABLE_NAND0_CE_RDY_PULLUP UNTOUCH_INTERNAL_SSP_PULLUP SSP1_EXT_PULLUP SSP0_EXT_PULLUP SD_INCREASE_INIT_SEQ_TIME R 30 ENABLE_NAND7_CE_RDY_PULLUP 31 SSP2_EXT_PULLUP Bit SSP3_EXT_PULLUP Address: 8002_C000h base + 1B0h offset = 8002_C1B0h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSRVD2 W Reset 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1561 0 0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 13 RSRVD1 14 SD_INIT_SEQ_1_DISABLE R 15 SD_CMD0_DISABLE Bit SD_INIT_SEQ_2_ENABLE OCOTP Memory Map/Register Definition BOOT_SEARCH_COUNT NUMBER_OF_ NANDS BOOT_SEARCH_STRIDE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_ROM1 field descriptions Field 31-30 RSRVD2 Description Reserved - do not blow this bit. 29 SSP3_EXT_ PULLUP Blow to indicate external pull-ups implemented for SSP3. 28 SSP2_EXT_ PULLUP Blow to indicate external pull-ups implemented for SSP2. 27 ENABLE_ NAND7_CE_ RDY_PULLUP If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE7 and GPMI_RDY7 pins. 26 ENABLE_ NAND6_CE_ RDY_PULLUP If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE6 and GPMI_RDY6 pins. 25 ENABLE_ NAND5_CE_ RDY_PULLUP If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE5 and GPMI_RDY5 pins. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1562 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller HW_OCOTP_ROM1 field descriptions (continued) Field Description 24 ENABLE_ NAND4_CE_ RDY_PULLUP If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE4 and GPMI_RDY4 pins. 23 ENABLE_ NAND3_CE_ RDY_PULLUP If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE3 and GPMI_RDY3 pins. 22 ENABLE_ NAND2_CE_ RDY_PULLUP If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE2 and GPMI_RDY2 pins. 21 ENABLE_ NAND1_CE_ RDY_PULLUP If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE1 and GPMI_RDY1 pins. 20 ENABLE_ NAND0_CE_ RDY_PULLUP If the bit is blown then ROM NAND driver will enable internal pull-up for GPMI_CE0 and GPMI_RDY0 pins. 19 UNTOUCH_ INTERNAL_ SSP_PULLUP If this bit is blown then internal pull-ups for SSP are neither enabled nor disabled. This bit is used only if external pull-ups are implemented and ROM1:18 and/or ROM1:17 are blown. 18 SSP1_EXT_ PULLUP Blow to indicate external pull-ups implemented for SSP1. 17 SSP0_EXT_ PULLUP Blow to indicate external pull-ups implemented for SSP0. 16 Blow to increase the SD card initialization sequence time from 1ms (default) to 4ms. SD_INCREASE_ INIT_SEQ_TIME 15 Blow to enable the second initialization sequence for SD boot. SD_INIT_SEQ_ 2_ENABLE 14 SD_CMD0_ DISABLE Cmd0 (reset cmd) is called by default to reset the SD card during startup. Blow this bit to not reset the card during SD boot. 13 Blow to disable the first initialization sequence for SD. SD_INIT_SEQ_ 1_DISABLE 12 RSRVD1 11-8 BOOT_ SEARCH_ COUNT Reserved - do not blow these bits. Number of 64 page blocks that should be read by the boot loader. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1563 OCOTP Memory Map/Register Definition HW_OCOTP_ROM1 field descriptions (continued) Field Description 7-4 BOOT_ SEARCH_ STRIDE the value of these bits is multiplied by 64 to get boot search stride. The default is 1 boot search stride, i.e. 64 pages. 3 RSRVD0 Reserved - do not blow these bits. NUMBER_OF_ NANDS Encoded value indicates number of external NAND devices (0 to 7). Zero indicates ROM will probe for the number of NAND devices connected in the system. 20.4.29 Shadow Register for OTP Bank3 Word2 (ROM Use 2) (HW_OCOTP_ROM2) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 2 (ADDR = 0x1A). Address: 8002_C000h base + 1C0h offset = 8002_C1C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 USB_VID 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 USB_PID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_ROM2 field descriptions Field Description 31-16 USB_VID USB Vendor ID. USB_PID USB Product ID 20.4.30 Shadow Register for OTP Bank3 Word3 (ROM Use 3) (HW_OCOTP_ROM3) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 3 (ADDR = 0x1B). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1564 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller Address: 8002_C000h base + 1D0h offset = 8002_C1D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 ALT_FAST_BOOT Bit 0 FAST_BOOT_ACK Reset 0 0 RSRVD0 0 0 0 0 0 0 HW_OCOTP_ROM3 field descriptions Field Description 31-12 RSRVD1 Reserved - do not blow these bits. 11 FAST_BOOT_ ACK Enable the fast boot acknowledge. 10 ALT_FAST_ BOOT RSRVD0 Enable the alternative fast boot mode. Reserved - do not blow these bits. 20.4.31 Shadow Register for OTP Bank3 Word4 (ROM Use 4) (HW_OCOTP_ROM4) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1565 OCOTP Memory Map/Register Definition Shadowed memory mapped access to OTP Bank 3, word 4 (ADDR = 0x1C). Address: 8002_C000h base + 1E0h offset = 8002_C1E0h 31 R W Reset Bit 30 29 28 NAND_BADBLOCK_MARKER_RESERVE Bit 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 NAND_READ_CMD_CODE2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NAND_COLUMN_ ADDRESS_BYTES NAND_READ_CMD_CODE1 NAND_ROW_ADDRESS_ BYTES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_ROM4 field descriptions Field 31 NAND_ BADBLOCK_ MARKER_ RESERVE Description If this bit is blown, the factory bad block marker preservation will be disabled. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1566 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller HW_OCOTP_ROM4 field descriptions (continued) Field Description 30-24 RSRVD0 Reserved - do not blow these bits. 23-16 NAND_READ_ CMD_CODE2 NAND flash read command confirm code. 15-8 NAND_READ_ CMD_CODE1 NAND flash read command setup code. 7-4 NAND_ COLUMN_ ADDRESS_ BYTES NAND flash column address cycles. NAND_ROW_ ADDRESS_ BYTES NAND flash row address cycles. 20.4.32 Shadow Register for OTP Bank3 Word5 (ROM Use 5) (HW_OCOTP_ROM5) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 5 (ADDR = 0x1D). Address: 8002_C000h base + 1F0h offset = 8002_C1F0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_ROM5 field descriptions Field BITS Description Shadow register for ROM-use word5 (Copy of OTP Bank 3, word 5 (ADDR = 0x1D)). These bits become read-only after the HW_OCOTP_LOCK[ROM_SHADOW] bit is set. 20.4.33 Shadow Register for OTP Bank3 Word6 (ROM Use 6) (HW_OCOTP_ROM6) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 6 (ADDR = 0x1E). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1567 OCOTP Memory Map/Register Definition Address: 8002_C000h base + 200h offset = 8002_C200h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_ROM6 field descriptions Field Description BITS Shadow register for ROM-use word6 (Copy of OTP Bank 3, word 6 (ADDR = 0x1E)). These bits become read-only after the HW_OCOTP_LOCK[ROM_SHADOW] bit is set. 20.4.34 Shadow Register for OTP Bank3 Word7 (ROM Use 7) (HW_OCOTP_ROM7) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 3, word 7 (ADDR = 0x1F). 31 30 29 28 27 26 25 24 RSRVD2 R W Reset 0 0 0 0 0 0 0 0 23 22 ARM_PLL_DISABLE Bit FORCE_RECOVERY_DISABLE Address: 8002_C000h base + 210h offset = 8002_C210h 0 0 21 20 HAB_ CONFIG 0 0 19 18 17 16 RECOVERY_BOOT_MODE 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1568 Freescale Semiconductor, Inc. RECOVERY_BOOT_MODE HAB_DISABLE R 9 8 0 0 7 6 5 4 3 2 1 0 ENABLE_PIN_BOOT_CHECK 10 MMU_DISABLE 11 ENABLE_ARM_ICACHE 12 I2C_USE_400KHZ 13 ENABLE_SSP_12MA_DRIVE 14 RSRVD1 15 Bit RESET_USB_PHY_AT_STARTUP Chapter 20 On-Chip OTP (OCOTP) Controller 0 0 0 0 RSRVD0 W Reset 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_ROM7 field descriptions Field 31-24 RSRVD2 23 FORCE_ RECOVERY_ DISABLE 22 ARM_PLL_ DISABLE 21-20 HAB_CONFIG Description Reserved - do not blow these bits. 0 - Force Recovery Enable 1 - Force Recovery Disable 0 - Not disabled : ARM core will run at 240MHz for high speed boot 1 - Disabled : ARM core will run at xtal 24MHz for boot 00 - HAB_FAB : Blank out of FAB 01 - HAB_OPEN : For non-secure shipping products, or secure products under development., the ROM will boot the image even if the HAB authentication fails. Other - HAB_CLOSED : For the end product, the ROM will not boot unless the image passes the HAB authentication. 19-12 RECOVERY_ BOOT_MODE If USB is not desirable for recovery boot mode then these bits can be blown to have the ROM boot from a non-USB device in recovery mode. 11 HAB_DISABLE 0 - HAB is enabled in default 10 RSRVD1 1 - HAB is disabled Reserved - do not blow these bits. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1569 OCOTP Memory Map/Register Definition HW_OCOTP_ROM7 field descriptions (continued) Field Description 9 RESET_USB_ PHY_AT_ STARTUP Blow to reset the USBPHY at startup This bit will be listed as Reserved in the Data Sheet. 8 Blow to force SSP pins to drive 12mA, default is 4mA. ENABLE_SSP_ 12MA_DRIVE 7-4 RSRVD0 Reserved - do not blow these bits. 3 I2C_USE_ 400KHZ Blow to force the I2C to be programmed by the boot loader to run at 400KHz, 100KHz is the default. 2 Blow to enable the ARM 926 ICache during boot. ENABLE_ARM_ ICACHE 1 0 - MMU and D-Cache are enabled during boot. MMU_DISABLE 1 - MMU and D-Cache are disabled during boot. 0 ENABLE_PIN_ BOOT_CHECK Blow to enable boot loader to first test the LCD_RS pin to determine if pin boot mode is enabled. If this bit is blown, and LCD_RS is pulled high, then boot mode is determined by the state of LCD_D[5:0] pins. If this bit is not blown, skip testing the LCD_RS pin and go directly to determining boot mode by reading the state of LCD_D[5:0]. 20.4.35 Shadow Register for OTP Bank4 Word0 (Data Use 0) (HW_OCOTP_SRK0) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 4, word 0 (ADDR = 0x20). Address: 8002_C000h base + 220h offset = 8002_C220h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_SRK0 field descriptions Field Description BITS Shadow register for the hash of the Super Root Key word0. If HAB is not required, these fuses can be used for other purposes (Copy of OTP Bank 4, word 0 (ADDR = 0x20)). These bits become read-only after the HW_OCOTP_LOCK[SRK_SHADOW] bit is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1570 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller 20.4.36 Shadow Register for OTP Bank4 Word1 (Data Use 1) (HW_OCOTP_SRK1) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 4, word 1 (ADDR = 0x21). Address: 8002_C000h base + 230h offset = 8002_C230h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_SRK1 field descriptions Field Description BITS Shadow register for the hash of the Super Root Key word1. If HAB is not required, these fuses can be used for other purposes (Copy of OTP Bank 4, word 1 (ADDR = 0x21)). These bits become read-only after the HW_OCOTP_LOCK[SRK_SHADOW] bit is set. 20.4.37 Shadow Register for OTP Bank4 Word2 (Data Use 2) (HW_OCOTP_SRK2) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 4, word 2 (ADDR = 0x22). Address: 8002_C000h base + 240h offset = 8002_C240h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_SRK2 field descriptions Field Description BITS Shadow register for the hash of the Super Root Key word2. If HAB is not required, these fuses can be used for other purposes (Copy of OTP Bank 4, word 2 (ADDR = 0x22)). These bits become read-only after the HW_OCOTP_LOCK[SRK_SHADOW] bit is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1571 OCOTP Memory Map/Register Definition 20.4.38 Shadow Register for OTP Bank4 Word3 (Data Use 3) (HW_OCOTP_SRK3) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 4, word 3 (ADDR = 0x23). Address: 8002_C000h base + 250h offset = 8002_C250h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_SRK3 field descriptions Field Description BITS Shadow register for the hash of the Super Root Key word3. If HAB is not required, these fuses can be used for other purposes (Copy of OTP Bank 4, word 3 (ADDR = 0x23)). These bits become read-only after the HW_OCOTP_LOCK[SRK_SHADOW] bit is set. 20.4.39 Shadow Register for OTP Bank4 Word4 (Data Use 4) (HW_OCOTP_SRK4) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 4, word 4 (ADDR = 0x24). Address: 8002_C000h base + 260h offset = 8002_C260h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_SRK4 field descriptions Field Description BITS Shadow register for the hash of the Super Root Key word4. If HAB is not required, these fuses can be used for other purposes (Copy of OTP Bank 4, word 4 (ADDR = 0x24)). These bits become read-only after the HW_OCOTP_LOCK[SRK_SHADOW] bit is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1572 Freescale Semiconductor, Inc. Chapter 20 On-Chip OTP (OCOTP) Controller 20.4.40 Shadow Register for OTP Bank4 Word5 (Data Use 5) (HW_OCOTP_SRK5) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 4, word 5 (ADDR = 0x25). Address: 8002_C000h base + 270h offset = 8002_C270h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_SRK5 field descriptions Field Description BITS Shadow register for the hash of the Super Root Key word5. If HAB is not required, these fuses can be used for other purposes (Copy of OTP Bank 4, word 5 (ADDR = 0x25)). These bits become read-only after the HW_OCOTP_LOCK[SRK_SHADOW] bit is set. 20.4.41 Shadow Register for OTP Bank4 Word6 (Data Use 6) (HW_OCOTP_SRK6) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 4, word 6 (ADDR = 0x26). Address: 8002_C000h base + 280h offset = 8002_C280h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_SRK6 field descriptions Field Description BITS Shadow register for the hash of the Super Root Key word6. If HAB is not required, these fuses can be used for other purposes (Copy of OTP Bank 4, word 6 (ADDR = 0x26)). These bits become read-only after the HW_OCOTP_LOCK[SRK_SHADOW] bit is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1573 OCOTP Memory Map/Register Definition 20.4.42 Shadow Register for OTP Bank4 Word7 (Data Use 7) (HW_OCOTP_SRK7) Copied from the OTP automatically after reset. Can be re-loaded by setting HW_OCOTP_CTRL[RELOAD_SHADOWS]. Shadowed memory mapped access to OTP Bank 4, word 7 (ADDR = 0x27). Address: 8002_C000h base + 290h offset = 8002_C290h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BITS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_OCOTP_SRK7 field descriptions Field Description BITS Shadow register for the hash of the Super Root Key word7. If HAB is not required, these fuses can be used for other purposes (Copy of OTP Bank 4, word 7 (ADDR = 0x27)). These bits become read-only after the HW_OCOTP_LOCK[SRK_SHADOW] bit is set. 20.4.43 OTP Controller Version Register (HW_OCOTP_VERSION) This register always returns a known read value for debug purposes it indicates the version of the block. This register indicates the RTL version in use. Address: 8002_C000h base + 2A0h offset = 8002_C2A0h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 HW_OCOTP_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1574 Freescale Semiconductor, Inc. Chapter 21 Performance Monitor (PERFMON) 21.1 Overview The i.MX28 implements a real time systerm performance monitor, it provides the following functions: * Real-time performance statistics collection on AXI buses. * Single or multiple master transactions monitoring. * Various interrupts support: address trap, latency threshold, and so on. * AXI protocol and out-of-order sequence support. The performance monitor is illustrated in Figure 21-1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1575 Operation M Ax i0 - 200MHz (PL301) AHB_ARB3 AHB_ARB2 AHB_ARB1 Performance Monitor 64 LCDIF M 64 M 64 M 64 PXP DCP BCH SYNC/ ASYNC EMI - DDR2-400, LV-DDR2-400, LP-DDR1-400 Figure 21-1. Block diagram of PerfMon 21.2 Operation The role of the performance monitor in an AXI system is to collect real time bus transaction statistics, including transaction average and maximum latency, total data bandwidth, and total active cycles. The statistics collection can be configured for single master or multiple masters on the same AXI bus, and can be enabled for either read or write transactions. There is one AXI bus in the i.MX28 system which has DCP, PXP, LCDIF and BCH. AXI protocol supports out-of-order transaction completion. In i.MX28, out-of-order transaction is programmable in EMI. Tag ID is used to trace each transaction and match the data phase with the correct address phase. Performance Monitor supports out-of-order transactions. AXI protocol separates the address/control phase and data phase, and has the ability to issue multiple outstanding addresses. It gives an ID tag to every transaction across the interface, which consists 4-bit master ID and 4-bit subID. Every master has its own unique master ID, and each master could have up to 16 sub IDs, which means up to 16 outstanding address phases. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1576 Freescale Semiconductor, Inc. Chapter 21 Performance Monitor (PERFMON) PerfMon collects the accumulated latency on cycle counts and number of transfers, the average latency can be calculated by dividing the total latency over number of transfers. Since the AXI protocol separates the address and data phases, the address and data phases could be overlapped, and individual data phase could overlap with multiple address phase. Statistics on total cycles, total data transfer in bytes will be collected as well. All statistics are collected for either read or write transactions, which could be switched by the enable bit in the control register. To calculate the maximum latency and support out-of-order transaction, PerfMon needs to cache the tag ID for all the outstanding requests. The potential number of outstanding requests depends on how deep the command queue in the memory controller(EMI) which includes two level of command queues. A scoreboard will be implemented to match the tag ID of the ongoing data phase with the ID from the outstanding requests. PerfMon snapshots the master ID(8 bits), burst length(4 bits), burst type(2 bits), burst size(3 bits) for the content register of maximum latency, but no transfer address(32 bits). Registers in PerfMon are accessible through APBH bridge, and PerfMon registers sits on APBH clock domain. Shade registers are added for the coherence among statistics/status registers, and the snapshot bit in PerfMon control register will trigger the shade register being filled at the same cycle for these registers: total transfers, total latency, maximum latency, content register for max_latency, total data bytes, total active cycles, and total cycles. Various interrupts supported in this module are as follows: 1. Address trap IRQ. IRQ will be asserted if any transaction address hit within the preconfigured address range. 2. Address range inversion IRQ. IRQ will be asserted if any transaction address hit outside the pre-configured address range. 3. Max latency threshold IRQ: IRQ will be asserted if maximum latency is above the value defined in the threshold register. 4. Bus error IRQ: IRQ will be asserted if any AXI transaction triggers an error response. 21.3 Programmable Registers PERFMON Hardware Register Format Summary i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1577 Programmable Registers HW_PERFMON memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_6000 PerfMon Control Register (HW_PERFMON_CTRL) 32 R/W C000_0000h 21.3.1/1578 8000_6010 PerfMon Master Enable Register (HW_PERFMON_MASTER_EN) 32 R/W 0000_0000h 21.3.2/1580 8000_6020 PerfMon Trap Range Low Address Register (HW_PERFMON_TRAP_ADDR_LOW) 32 R/W 0000_0000h 21.3.3/1582 8000_6030 PerfMon Trap Range High Address Register (HW_PERFMON_TRAP_ADDR_HIGH) 32 R/W 0000_0000h 21.3.4/1582 8000_6040 PerfMon Latency Threshold Register (HW_PERFMON_LAT_THRESHOLD) 32 R/W 0000_0000h 21.3.5/1583 8000_6050 PerfMon AXI Active Cycle Count Register (HW_PERFMON_ACTIVE_CYCLE) 32 R 0000_0000h 21.3.6/1583 8000_6060 PerfMon Transfer Count Register (HW_PERFMON_TRANSFER_COUNT) 32 R 0000_0000h 21.3.7/1584 8000_6070 PerfMon Total Latency Count Register (HW_PERFMON_TOTAL_LATENCY) 32 R 0000_0000h 21.3.8/1584 8000_6080 PerfMon Total Data Count Register (HW_PERFMON_DATA_COUNT) 32 R 0000_0000h 21.3.9/1585 8000_6090 PerfMon Maximum Latency Register (HW_PERFMON_MAX_LATENCY) 32 R 0000_0000h 21.3.10/ 1585 8000_60A0 PerfMon Debug Register (HW_PERFMON_DEBUG) 32 R/W 0000_0001h 21.3.11/ 1586 8000_60B0 PerfMon Version Register (HW_PERFMON_VERSION) 32 R 0100_0000h 21.3.12/ 1587 21.3.1 PerfMon Control Register (HW_PERFMON_CTRL) The PerfMon Control Register specifies the reset state and the interrupt controls for the Performance Monitor. HW_PERFMON_CTRL: 0x000 HW_PERFMON_CTRL_SET: 0x004 HW_PERFMON_CTRL_CLR: 0x008 HW_PERFMON_CTRL_TOG: 0x00C This register controls various funcitons of the systerm performance monitor. EXAMPLE // turn off soft reset and clock gating HW_PERFMON_CTRL_CLR(BM_PERFMON_CTRL_SFTRST| BM_PERFMON_CTRL_CLKGATE); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1578 Freescale Semiconductor, Inc. Chapter 21 Performance Monitor (PERFMON) Address: 8000_6000h base + 0h offset = 8000_6000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 RSVD2 18 17 16 CLKGATE 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS_ ERR_ IRQ LATENCY_IRQ TRAP_IRQ BUS_ERR_IRQ_EN LATENCY_IRQ_EN TRAP_IRQ_EN LATENCY_ENABLE TRAP_IN_RANGE TRAP_ENABLE READ_EN CLR SNAP IRQ_MID SFTRST R 19 RUN 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset Bit RSVD1 R W Reset 0 0 0 HW_PERFMON_CTRL field descriptions Field 31 SFTRST Description Set to zero for normal operation. When this bit is set to one (default), then the entire block is held in its reset state. 0x0 0x1 30 CLKGATE 29-24 RSVD2 23-16 IRQ_MID 15-13 RSVD1 RUN -- Allow PerfMon to operate normally. RESET -- Hold PerfMon in reset. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. 0x0 0x1 RUN -- Allow PerfMon to operate normally. NO_CLKS -- Do not clock PerfMon gates in order to minimize power consumption. Always set this bit field to zero. This field contains the master ID and sub ID associated with the interrupt. If multiple IRQs, it is the ID associated the first IRQ transaction, and will not update until the IRQ being cleared. Always set this bit field to zero. 12 This bit is set if there is error on any AXI transaction and the BUS_ERR_IRQ_EN bit is set. BUS_ERR_IRQ Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1579 Programmable Registers HW_PERFMON_CTRL field descriptions (continued) Field 11 LATENCY_IRQ 10 TRAP_IRQ Description This status bit is set if maximum latency is above the value defined in the latency threshold register and the LATENCY_ENABLE bit is set. Writing a one to its SCT clear address to clear it. This status bit is set to indicate that an address trap occurs. This bit is cleared by software by writing a one to its SCT clear address. This bit is set if axi address is within the pre-configured address range and the trap function is enabled with TRAP_ENABLE bit. 9 Enables the PerfMon AXI BUS ERROR IRQ. When an error occurs and this bit is set, an interrupt is sent BUS_ERR_IRQ_ to the ARM core. EN 8 Enables the PerfMon Latency threshold IRQ. When an error occurs and this bit is set, an interrupt is sent LATENCY_IRQ_ to the ARM core. EN 7 TRAP_IRQ_EN Enables the PerfMon Address Trap IRQ. When an trap occurs and this bit is set, an interrupt is sent to the ARM core. 6 LATENCY_ ENABLE Enables the PerfMon AXI latency threshold functions. When a transfer latency larger than the threshold and this bit is set, the LATENCY_IRQ status bit will be set. 5 TRAP_IN_ RANGE Determines whether the debug trap function causes a match when the master address is inside (lowaddress <= current-address <= high-address) the specified range. 0 = The trap occurs when the master address falls outside of the range. 1 = The check is inside the range. 4 Enables the PerfMon AXI address trap functions. When a trap occurs and this bit is set, the TRAP_IRQ TRAP_ENABLE status bit will be set. 3 READ_EN Set this bit to One to monitor all Read transactions, set to zero to monitor all Write transactions. 0 = performance monitoring on all WRITE activities. 1 = performance monitoring on all READ activities. 2 CLR Set this bit to clear all the PerfMon's statistics registers. This bit will be reset to 0 once the clear process is done. 1 SNAP Set this bit to snap shot PerfMon's statistics registers into the shadow registers for reads. PerfMon will continue collecting and updating statistics registers. This bit will be reset to 0 once the snapshot processing is done. 0 RUN Set this bit to one to enable the PerfMon operation. 0x0 0x1 HALT -- No PerfMon command in progress. RUN -- Process Performance monitoring. 21.3.2 PerfMon Master Enable Register (HW_PERFMON_MASTER_EN) The Master Enable register defines single or multiple MasterIDs to be monitored by Perfmon. The master ID of PXP is 0, LCDIF is 1, BCH is 2 and DCP is 3. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1580 Freescale Semiconductor, Inc. Chapter 21 Performance Monitor (PERFMON) Address: 8000_6000h base + 10h offset = 8000_6010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MID13 MID12 MID11 MID10 Bit 0 MID14 Reset MID15 W 0 0 0 0 0 0 R MID9 MID8 MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID0 W Reset 0 0 0 0 0 0 0 0 0 0 HW_PERFMON_MASTER_EN field descriptions Field Description 31-16 RSVD0 Always set this bit field to zero. 15 MID15 Set to 1 to enable performancce monitoring and statistics collection on MasterID 15. 14 MID14 Set to 1 to enable performancce monitoring and statistics collection on MasterID 14. 13 MID13 Set to 1 to enable performancce monitoring and statistics collection on MasterID 13. 12 MID12 Set to 1 to enable performancce monitoring and statistics collection on MasterID 12. 11 MID11 Set to 1 to enable performancce monitoring and statistics collection on MasterID 11. 10 MID10 Set to 1 to enable performancce monitoring and statistics collection on MasterID 10. 9 MID9 Set to 1 to enable performancce monitoring and statistics collection on MasterID 9. 8 MID8 Set to 1 to enable performancce monitoring and statistics collection on MasterID 8. 7 MID7 Set to 1 to enable performancce monitoring and statistics collection on MasterID 7. 6 MID6 Set to 1 to enable performancce monitoring and statistics collection on MasterID 6. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1581 Programmable Registers HW_PERFMON_MASTER_EN field descriptions (continued) Field Description 5 MID5 Set to 1 to enable performancce monitoring and statistics collection on MasterID 5. 4 MID4 Set to 1 to enable performancce monitoring and statistics collection on MasterID 4. 3 MID3 Set to 1 to enable performancce monitoring and statistics collection on MasterID 3. 2 MID2 Set to 1 to enable performancce monitoring and statistics collection on MasterID 2. 1 MID1 Set to 1 to enable performancce monitoring and statistics collection on MasterID 1. 0 MID0 Set to 1 to enable performancce monitoring and statistics collection on MasterID 0. 21.3.3 PerfMon Trap Range Low Address Register (HW_PERFMON_TRAP_ADDR_LOW) The Debug Trap Range Low Address Register defines the lower bound for an address range that can be enabled to trigger an interrupt to the ARM core when an AXI cycle occurs within this range. Address: 8000_6000h base + 20h offset = 8000_6020h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PERFMON_TRAP_ADDR_LOW field descriptions Field ADDR Description This field contains the 32-bit lower address for the debug trap range. 21.3.4 PerfMon Trap Range High Address Register (HW_PERFMON_TRAP_ADDR_HIGH) The Trap Range High Address Register defines the upper bound for an address range that can be enabled to trigger an interrupt to the ARM core when an AXI cycle occurs within this range. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1582 Freescale Semiconductor, Inc. Chapter 21 Performance Monitor (PERFMON) Address: 8000_6000h base + 30h offset = 8000_6030h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PERFMON_TRAP_ADDR_HIGH field descriptions Field Description ADDR This field contains the 32-bit upper address for the debug trap range. 21.3.5 PerfMon Latency Threshold Register (HW_PERFMON_LAT_THRESHOLD) The latency threshold Register defines the threshold for AXI transaction latency that can be enabled to trigger an interrupt to the ARM core when an AXI transaction latency is above this value. Address: 8000_6000h base + 40h offset = 8000_6040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSVD0 R 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 0 0 0 VALUE W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PERFMON_LAT_THRESHOLD field descriptions Field Description 31-12 RSVD0 Always set this bit field to zero. VALUE This field contains the 12-bit transaction latency threshold. 21.3.6 PerfMon AXI Active Cycle Count Register (HW_PERFMON_ACTIVE_CYCLE) The active cycle count register counts the number of AXI cycles during which a transaction is active on AXI bus. This register counts the number of AXI cycles in which a master was requesting a transfer, and the slave had not responded. This is including cycles in which it was requesting transfers but was not accepted by slave yet. The master enable register HW_PERFMON_MASTER_EN are used to mask which master(s) cycles are actually recorded here. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1583 Programmable Registers Address: 8000_6000h base + 50h offset = 8000_6050h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PERFMON_ACTIVE_CYCLE field descriptions Field Description COUNT This field contains the total active AXI cycle counts. If overflow, the value will be 0xFFFFFFFF. 21.3.7 PerfMon Transfer Count Register (HW_PERFMON_TRANSFER_COUNT) The transfer count register defines the total number of transfers has been completed during the whole monitoring period. Divide the register HW_PERFMON_LATENCY_CYCLE value over this value of this register will give the average latency for each transfer. Address: 8000_6000h base + 60h offset = 8000_6060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PERFMON_TRANSFER_COUNT field descriptions Field VALUE Description This field contains the total amount transfers. If overflow, the value will be 0xFFFFFFFF. 21.3.8 PerfMon Total Latency Count Register (HW_PERFMON_TOTAL_LATENCY) The transfer count register defines the total number of latency in cycles during the monitoring period. Divide the register value over value of register HW_PERFMON_TRANSFER_COUNT will give the average latency for each transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1584 Freescale Semiconductor, Inc. Chapter 21 Performance Monitor (PERFMON) Address: 8000_6000h base + 70h offset = 8000_6070h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PERFMON_TOTAL_LATENCY field descriptions Field Description COUNT This field contains the total latency in cycle counts. If overflow, the value will be 0xFFFFFFFF. 21.3.9 PerfMon Total Data Count Register (HW_PERFMON_DATA_COUNT) The data count register defines the total number of data transfered in bytes during the monitoring period. Address: 8000_6000h base + 80h offset = 8000_6080h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PERFMON_DATA_COUNT field descriptions Field Description COUNT This field contains the total bytes of data transfered. If overflow, the value will be 0xFFFFFFFF. 21.3.10 PerfMon Maximum Latency Register (HW_PERFMON_MAX_LATENCY) The maximum latency register contains the maximum latency in cycles and control signals for this transaction during the monitoring period. Address: 8000_6000h base + 90h offset = 8000_6090h Bit 31 R 30 29 28 ABURST 27 26 25 ALEN 24 23 22 21 20 ASIZE 19 18 17 16 0 0 0 TAGID W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1585 Programmable Registers 15 Bit R 14 TAGI D 13 12 11 10 9 8 7 RSVD0 6 5 4 3 2 1 0 0 0 0 0 0 COUNT W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_PERFMON_MAX_LATENCY field descriptions Field Description 31-30 ABURST This field contains axi_aburst signal associated with the worst latency transaction. 29-26 ALEN This field contains axi_alen signal associated with the worst latency transaction. 25-23 ASIZE This field contains axi_asize signal associated with the worst latency transaction. 22-15 TAGID This field contains the master id and sub id associated with the worst latency transaction. 14-12 RSVD0 Always set this bit field to zero. COUNT This field contains the worst transfer latency. If overflow, the value will be 0xFFF. 21.3.11 PerfMon Debug Register (HW_PERFMON_DEBUG) The debug register is for internal use only. Divide the register HW_PERFMON_LATENCY_CYCLE value over this value of this register will give the average latency for each transfer. Address: 8000_6000h base + A0h offset = 8000_60A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSVD R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1586 Freescale Semiconductor, Inc. 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 RSVD R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 TOTAL_CYCLE_CLR_EN Chapter 21 Performance Monitor (PERFMON) ERR_ MID 0 1 HW_PERFMON_DEBUG field descriptions Field Description 31-2 RSVD Always set this bit field to zero. 1 This field is for debug purpose. Set to 1 to clear the internal total cycle register no matter there is pending TOTAL_CYCLE_ request or not when the clear bit in control register is set. CLR_EN 0 ERR_MID This field is for debug purpose. Set to 0 will not record the MID for bus error irq. 21.3.12 PerfMon Version Register (HW_PERFMON_VERSION) This register always returns a known read value for debug purposes. It indicates the version of the block. EXAMPLE if (HW_PERFMON_VERSION.B.MAJOR != 1) Error(); Address: 8000_6000h base + B0h offset = 8000_60B0h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1587 Programmable Registers HW_PERFMON_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1588 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits 22.1 RTC Overview The real-time clock (RTC) and alarm share a one-second pulse time domain. The watchdog reset and millisecond counter run on a one-millisecond time domain. The RTC, alarm, and persistent bits use persistent storage and reside in a special power domain (crystal domain) that remains powered up even when the rest of the chip is in its powered-down state. Figure 22-1 illustrates this block. Note The term power-down, as used here, refers to a state in which the DC-DC converter and various parts of the crystal power domain are still powered up, but the rest of the chip is powered down. If the battery is removed, then the persistent bits, the alarm value, and the second counter value will be lost. The crystal power domain powers both the 32-KHz and 24-MHz crystals. Upon battery insertion, the crystals (32-KHz and 24-MHz) are in a quiescent state. The activation of these crystals is under software control through the RTC persistent bits, as described later in this chapter. * The XTAL32KHZ_PWRUP bit in the Persistent Register 0 controls the activity of the 32-KHz crystal at all times (chip power on or off). * The XTAL24MHZ_PWRUP bit in the Persistent Register 0 controls the behavior of the 24-MHz crystal during the power-off state. (The 24-MHz crystal is always on when the chip is powered up.) The one-second time base is derived either from the 24.0-MHz crystal oscillator or a 32KHz crystal oscillator (which can be either exactly 32.0 KHz or 32.768 KHz), as controlled by bits in Persistent Register 0. The time base thus generated is used to i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1589 RTC Overview increment the value of the persistent seconds count register. Like the values of the other persistent registers, the value of the persistent seconds count register is not lost across a power-down state and will continue to count seconds during that time. Contrary to the one-second time base, no record or count is made of the one-millisecond time base in the crystal power domain. The one-millisecond time base is always derived from the 24.0-MHz crystal oscillator, but is not available when the chip is powered down. The real-time clock seconds counter, alarm functions, and persistent bit storage are kept in the (always on) crystal power domain. Shadow versions of these values are maintained in the CPU's power and APBX clock domain when the chip is in the power-up state. When the chip transitions from power-off to power-on, the master values are copied to shadow registers by the copy controller. Whenever software writes to a shadow register, then the copy controller copies the new value into the master register in the crystal oscillator power domain. Some of the persistent bits are used to control features that can continue to operate after power-down, such as the second counter and the alarm function and bits in the HW_RTC_PERSISTENT0 register. The bits in registers HW_RTC_PERSISTENT1 through HW_RTC_PERSISTENT5 are available to store application state information over power-downs and are completely software-defined. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1590 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits ARM Core SRAM AHB 24-MHz XTAL Osc. Divide by n AHB Master Shared DMA AHB-to-APBX Bridge 32.768 or 32.000 kHz XTAL Osc.1 APBX APBX Master RTC/Watchdog/Alarm/ Persistent I/O Copy controller 32-Bit Shadow Persistent 0 1/768 = 31250Hz AHB Slave 32-Bit Master Persistent 0 32-Bit Shadow Persistent 1 32-Bit Master Persistent 1 32-Bit Shadow Persistent 2 32-Bit Master Persistent 2 32-Bit Shadow Persistent 3 32-Bit Master Persistent 3 32-Bit Shadow Persistent 4 32-Bit Master Persistent 4 32-Bit Shadow Persistent 5 32-Bit Master Persistent 5 32-Bit Alarm Shadow 32-Bit Alarm Master == 32-Bit RTC Shadow Counter Alarm Event 32-Bit RTC Seconds 1 Hz 1 Hz Divide by appropriate value Crystal Power and Clock Domain 1 kHz fixed divide by 24000 Figure 22-1. RTC, Watchdog, Alarm, and Persistent Bits Block Diagram Immediately after reset, it will take approximately three milliseconds for the copy controller to complete the copy process from the analog domain to the digital domain. Software cannot rely on the contents of the seconds counter, alarm, or persistent bits until this copy is complete. Therefore, software must wait until all bits of interest in the HW_RTC_STAT_STALE_REGS field have been reset to 0 by the copy controller before reading the initial state of these values (see Figure 22-2). The order in which registers are updated is Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds. (This list is in bitfield order, from LSB to MSB, as they would appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT register. For example, the Seconds register corresponds to STALE_REGS or NEW_REGS containing 0x80.) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1591 Programming and Enabling the RTC Clock rtc_init Call during initialization HW_RTC_CTRL_SFTRST_WRITE (BM_RTC_CTRL_SFTRST); HW_RTC_CTRL_CLKGATE_WRITE (BM_RTC_CTRL_CLKGATE); Return Remove soft reset and clock gate. This releases the copy controller. Figure 22-2. RTC Initialization Sequence 22.2 Programming and Enabling the RTC Clock The RTC functions implemented in the crystal power domain are referred to as RTC analog functions. The clock frequency and clock source for the RTC analog functions are programmable. There are three possible clock options. * If the HW_RTC_PERSISTENT0_CLOCKSOURCE bit is set to 0, these functions operate on a clock domain derived from the 24.0-MHz crystal oscillator divided by 768 to yield 31.250 KHz. * If the HW_RTC_PERSISTENT0_CLOCKSOURCE bit is 1 and the HW_RTC_PERSISTENT0_XTAL32_FREQ bit is 0, then the optional external driving crystal clock will be used and its frequency should be 32.768 KHz. * However, if the HW_RTC_PERSISTENT0_CLOCKSOURCE is 1 and the HW_RTC_PERSISTENT0_XTAL32_FREQ bit is also 1, then the external crystal generated clock should be 32.000 KHz for correct operation. Thus, the HW_RTC_PERSISTENT0_XTAL32_FREQ bit gives the systems designer some flexibility as to which external crystal to use on the board. Switching between these two clock domains is handled by a glitch-free clock mux and can be done on the fly. The 1-Hz time base is derived by dividing either 32.768 KHz by 32768 or by dividing 31.250 KHz by 31,250, or by dividing 32.000 KHz by 32000. By reading and examining the HW_RTC_STAT_XTAL32000_PRESENT and HW_RTC_STAT_XTAL32768_PRESENT bits, software can discover if there is an optional crystal clock present and the frequency at which it runs (32.768 KHz or 32.000 KHz). Only one of these fuse bits will be asserted if there is such a crystal attached. If there is no crystal present, both bits will be deasserted. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1592 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits 22.3 RTC Persistent Register Copy Control The copying of a persistent shadow register (digital) to persistent master storage (analog) occurs automatically. This automatic write-back that occurs for each register as the copy controller services writes to the shadow registers can lead to some very long timing loops if efficient write procedures are not used. Writing all eight shadow registers can take several milliseconds to complete. Do not attempt to write to more than one shadow register immediately before power down. Whenever possible, software should ensure that the HW_RTC_STAT_NEW_REGS field is 0 before powering down the chip or setting the HW_RTC_CTRL_SFTRST bit. Otherwise, some of the write data could be lost because the shadow registers could be powered down/reset before the new values can be copied to the persistent master storage. Registers are copied between the digital and analog sides one by one and in 32-bit words. There are no hardwired uses for any of the bits of Persistent registers 1 through 5. Therefore, the bits in these registers can be defined and set by the software. Persistent Register 0 is reserved for hardware programming and configuration. Before a new value is written to a shadow register by the CPU, software must first confirm that the corresponding bit of HW_RTC_STAT_NEW_REGS is 0. This ensures that a value previously written to the register has been completely handled by the copy state machine. Failure to obey this constraint could cause a newer updated value to be lost. NOTE: The HW_RTC_CTRL_SUPPRESS_COPY2ANALOG diagnostic bit is never set while any copy or update operation is underway. Doing so will result in undefined operation of the copy controller. Figure 22-3 shows the copy and test procedure for a single register. However, software can write to any register whose HW_RTC_STAT_NEW_REGS bit is 0 even if the copy controller is currently busy copying a different register. For example, if the copy controller is busy copying Persistent Register 1 from a previous write, software can simultaneously write to Persistent Register 0 during this copy. After the copy controller has finished copying register 1, it will then, in turn, begin the copy process for the new value of Register 0. Therefore, registers can thus be written in any order. Again, the main important rule that must be followed is that the HW_RTC_STAT_NEW_REGS bit for a particular register must be 0 before it can be written and is independent of the state of the HW_RTC_STAT_NEW_REGS bits for the other registers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1593 Real-Time Clock Function How to write a master register. rtc_write2master TestValue = HW_RTC_STAT _NEW_REGS Extract corresponding bit. NO TestValue == 0 YES HW_RTC_PERSISTENT2_WR(0xdeadbeef); TestValue =HW_RTC_STAT_NEW_REGS NO Wait for previous write to this register to complete. Write new value to shadow that will be automatically copied to analog side. Use this same technique for milliseconds, alarm, or other persistent registers. TestValue == 0 Return Figure 22-3. RTC Writing to a Master Register from CPU The digital shadow registers will be updated (copied from analog to digital) with values from their analog persistent counterparts under two conditions: first, whenever the chip is powered on, and second, whenever the HW_RTC_CTRL_FORCE_UPDATE bit is set by the software. Then, an update occurs, and all persistent registers are updated. Persistent registers cannot be updated singly. 22.4 Real-Time Clock Function The real-time clock is a CPU-accessible, continuously-running 32-bit counter that increments every second and that can be derived from either the 24-MHz clock or the 32KHz clock, as determined by writable bit values in the RTC Persistent Register 0. A 32-bit second counter has enough resolution to count up to 136 years with one-second increments. The RTC can continue to count time as long as a voltage is applied to the BATT pin, irrespective of whether the rest of the chip is powered up. The normal digital reset has no effect on the master RTC registers located in the crystal power and clock domain. A special first-power-on reset establishes the default value of the master RTC registers when a voltage is first applied to the BATT pin (battery insertion). For consistency across applications, it is recommended that the seconds timer should be referenced to January 1, 1980 at a 32-bit value of 0 (same epoch reference as PC) in applications that use it as a time-of-day clock. If the real-time clock function is not i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1594 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits present on a specific chip, as indicated in the control and status register (HW_RTC_STAT_RTC_PRESENT), then no real-time epoch is maintained over powerdown cycles. 22.4.1 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. 22.5 Millisecond Resolution Timing Function A millisecond counter facility is provided based on a 1-KHz signal derived from the 24MHz clock. The count value is neither maintained nor incremented during power-down cycles. At each power-up, this register is set to its reset state. On each tick of the 1-KHz source, the milliseconds counter increments. With a 32-bit counter, a kernel can run up to 4,294,967,294 milliseconds or 49.7 days before it must deal with a counter wrap. The programmer can change the resolution of the millisecond counter to be 1, 2, 4, 8, or 16 milliseconds. This is programmed through bits in Persistent Register 0. CAUTION: When the 32.768-KHz or 32.000-KHz crystal oscillator is selected as the source for the seconds counter, an anomaly is created between the time intervals of the millisecond counter and the seconds counter. That is, the manufacturing tolerance of the two crystals are such that 1000 millisecond counter increments are not exactly one second as measured by the real-time clock seconds counter. 22.6 Alarm Clock Function The alarm clock function allows an application to specify a future instant at which the chip should be awakened, that is, if powered down, it can be powered up. The alarm clock setting is a CPU-accessible, 32-bit value that is continuously matched against the 32-bit real-time clock seconds counter. When the two values are equal, an alarm event is triggered. Persistent bits indicate whether an alarm event should power up the chip from its powered-down state. In addition to or instead of powering up the chip, the alarm event can also cause a CPU interrupt. Although these two functions can be enabled at the same time, one should remember that the CPU will only be interrupted if the chip is powered up at the time of the alarm event. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1595 Watchdog Reset Function NOTE: If the alarm is set to power up the chip in the event of an alarm and such an event occurs, then the only record of the cause of the wake-up is located in the analog side. At power-up, the analog side registers are copied to the digital shadow registers and the ALARM_WAKE bit in the Persistent register 0 is visible in the digital shadow register. If an alarm wake event occurs while the chip is powered up, the ALARM_WAKE bit will not be set in the persistent register because the chip was not woken up. The alarm must be present on an actual chip to perform this function (see the HW_RTC_STAT_ALARM_PRESENT bit description). 22.7 Watchdog Reset Function The watchdog reset is a CPU-configurable device. It is programmed by software to generate a chip-wide reset after HW_RTC_WATCHDOG milliseconds. The watchdog generates this reset if software does not rewrite this register before this time elapses. The watchdog timer decrements the register value once for every tick of the 1-KHz clock supplied from the RTC analog section (see Figure 22-1). The reset generated by the watchdog timer has no effect on the values retained in the master registers of the realtime clock seconds counter, alarm, or persistent registers (analog persistent storage). The watchdog timer is initially disabled and set to count 4,294,967,295 milliseconds before generating a watchdog reset. The watchdog timer does not run when the chip is in its powered-down state. Therefore, there is no master/shadow register pairing for the watchdog timer, and it must be reprogrammed after cycling power or resetting the block. The watchdog timer must be "present" on an actual chip to perform this function (see the HW_RTC_STAT_WATCHDOG_PRESENT bit description). 22.8 Programmable Registers RTC Hardware Register Format Summary HW_RTC memory map Absolute address (hex) 8005_6000 Register name Real-Time Clock Control Register (HW_RTC_CTRL) Width Access (in bits) 32 R/W Reset value Section/ page C000_0020h 22.8.1/1597 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1596 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits HW_RTC memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8005_6010 Real-Time Clock Status Register (HW_RTC_STAT) 32 R E0FF_0000h 22.8.2/1599 8005_6020 Real-Time Clock Milliseconds Counter (HW_RTC_MILLISECONDS) 32 R/W 0000_0000h 22.8.3/1601 8005_6030 Real-Time Clock Seconds Counter (HW_RTC_SECONDS) 32 R/W 0000_0000h 22.8.4/1602 8005_6040 Real-Time Clock Alarm Register (HW_RTC_ALARM) 32 R/W 0000_0000h 22.8.5/1603 8005_6050 Watchdog Timer Register (HW_RTC_WATCHDOG) 32 R/W FFFF_FFFFh 22.8.6/1604 8005_6060 Persistent State Register 0 (HW_RTC_PERSISTENT0) 32 R/W 0000_0100h 22.8.7/1604 8005_6070 Persistent State Register 1 (HW_RTC_PERSISTENT1) 32 R/W 0000_0000h 22.8.8/1607 8005_6080 Persistent State Register 2 (HW_RTC_PERSISTENT2) 32 R/W 0000_0000h 22.8.9/1608 8005_6090 Persistent State Register 3 (HW_RTC_PERSISTENT3) 32 R/W 0000_0000h 22.8.10/ 1608 8005_60A0 Persistent State Register 4 (HW_RTC_PERSISTENT4) 32 R/W 0000_0000h 22.8.11/ 1609 8005_60B0 Persistent State Register 5 (HW_RTC_PERSISTENT5) 32 R/W 0000_0000h 22.8.12/ 1610 8005_60C0 Real-Time Clock Debug Register (HW_RTC_DEBUG) 32 R/W 0000_0000h 22.8.13/ 1610 8005_60D0 Real-Time Clock Version Register (HW_RTC_VERSION) 32 R 0203_0000h 22.8.14/ 1612 22.8.1 Real-Time Clock Control Register (HW_RTC_CTRL) HW_RTC_CTRL is the control register for the RTC. HW_RTC_CTRL: 0x000 HW_RTC_CTRL_SET: 0x004 HW_RTC_CTRL_CLR: 0x008 HW_RTC_CTRL_TOG: 0x00C The contents of this register control the operation of the RTC portions implemented as an APBX peripheral running in the APBX clock domain. These functions only operate when the chip is in its full power up state. EXAMPLE HW_RTC_CTRL_CLR(BM_RTC_CTRL_SFTRST); // remove the soft reset condition HW_RTC_CTRL_CLR(BM_RTC_CTRL_CLKGATE); // enable clocks within the RTC HW_RTC_CTRL_CLR(BM_RTC_CTRL_ALARM_IRQ); // reset the alarm interrupt by clearing its status bit i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1597 Programmable Registers Address: 8005_6000h base + 0h offset = 8005_6000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD0 SFTRST CLKGATE 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SUPPRESS_COPY2ANALOG FORCE_UPDATE WATCHDOGEN ONEMSEC_IRQ ALARM_IRQ ONEMSEC_IRQ_EN ALARM_IRQ_EN R 0 0 0 0 0 1 0 0 0 0 0 W Reset Bit RSVD0 R W Reset 0 0 0 0 0 HW_RTC_CTRL field descriptions Field 31 SFTRST 30 CLKGATE 29-7 RSVD0 Description 1= Hold real time clock digital side in soft reset state. This bit has no effect on the RTC analog. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. This bit has no effect on RTC analog. Reserved, write only zeroes. 6 This bit is used for diagnostic purposes. 1= suppress the automatic copy that normally occurs to the SUPPRESS_ analog side, whenever a shadow register is written. 0= Normal operation. Use SCT writes to set, clear, or COPY2ANALOG toggle. 5 FORCE_ UPDATE This bit is how the software requests the update of the shadow registers from values in RTC analog. When software sets this bit, all eight of the shadow registers are updated from the corresponding values in the persistent registers in RTC analog. The state of this update operation is reflected on the STALEREGS bits on the STAT register, which are set to all ones upon an update request and are cleared by hardware as the update proceeds. Hardware clears this bit immediately after detecting it has been set. Software does not need to clear. Software must NOT look to the state of this bit to determine the status of Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1598 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits HW_RTC_CTRL field descriptions (continued) Field Description the update operation, it must look to the STALEREG bits in the STAT register to determine when any given register has been updated and/or when the update operation is complete. Notice that the default value of this bit is 1, so that that a reset (either chip-wide or soft) always results in an update. 4 1= Enable Watchdog Timer to force chip wide resets. Use SCT writes to set, clear, or toggle. WATCHDOGEN 3 1= one millisecond interrupt request status. Use SCT writes to clear this interrupt status bit. ONEMSEC_IRQ 2 ALARM_IRQ 1= Alarm Interrupt Status. Use SCT writes to clear this interrupt status bit. 1 1= Enable one millisecond interrupt. Use SCT writes to set, clear, or toggle. ONEMSEC_IRQ_ EN 0 1= Enable Alarm Interrupt. Use SCT writes to set, clear, or toggle. ALARM_IRQ_EN 22.8.2 Real-Time Clock Status Register (HW_RTC_STAT) HW_RTC_STAT is the status register for the RTC. HW_RTC_STAT: 0x010 HW_RTC_STAT_SET: 0x014 HW_RTC_STAT_CLR: 0x018 HW_RTC_STAT_TOG: 0x01C This register reflects the current state of the RTC in terms of its enabled capabilities and the state of the persistent registers. EXAMPLE required, on this chip while(HW_RTC_STAT.STALE_REGS !=0) { printf(" something is stale in one of the digital side registers\n"); // the copy controller will copy analog registers to digtial registers as // turning off staleregs bits as it goes about its business. } if(HW_RTC_STAT.WATCHDOG_PRESENT != 0) // then you can use the watchdog timer i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1599 Programmable Registers Address: 8005_6000h base + 10h offset = 8005_6010h 27 26 25 24 23 22 21 20 19 18 17 16 XTAL32768_PRESENT 28 XTAL32000_PRESENT 29 WATCHDOG_PRESENT 30 ALARM_PRESENT R 31 RTC_PRESENT Bit 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSVD1 STALE_REGS W Reset Bit NEW_REGS R RSVD0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_RTC_STAT field descriptions Field Description 31 This read-only bit reads back a one if the RTC is present in the device. RTC_PRESENT Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1600 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits HW_RTC_STAT field descriptions (continued) Field 30 ALARM_ PRESENT 29 WATCHDOG_ PRESENT Description This read-only bit reads back a one if the Alarm function is present in the device. This read-only bit reads back a one if the Watchdog Timer function is present in the device. 28 XTAL32000_ PRESENT This read-only bit reads back a one if the 32.000-kHz crystal oscillator function is present in the device. 27 XTAL32768_ PRESENT This read-only bit reads back a one if the 32.768-kHz crystal oscillator function is present in the device. 26-24 RSVD1 Reserved, write only zeroes. 23-16 STALE_REGS These read-only bits are set to one whenever the corresponding shadow register contents are older than the analog side contents. These bits are set by reset and cleared by the copy controller. They are also set by writing a one to the FORCE_UPDATE bit. 15-8 NEW_REGS These read-only bits are set to one whenever the corresponding shadow register contents are newer than the analog side contents. These bits are set by writing to the corresponding register and cleared by the copy controller. RSVD0 Reserved, write only zeroes. 22.8.3 Real-Time Clock Milliseconds Counter (HW_RTC_MILLISECONDS) The millisecond count register provides a reliable elapsed time reference to the kernel with millisecond resolution. HW_RTC_MILLISECONDS: 0x020 HW_RTC_MILLISECONDS_SET: 0x024 HW_RTC_MILLISECONDS_CLR: 0x028 HW_RTC_MILLISECONDS_TOG: 0x02C HW_RTC_MILLISECONDS provides access to the 32-bit millisecond counter. This counter is not a shadow register, i.e., the contents of this register are not preserved over power-down states. This counter increments once per millisecond based on a pulse from RTC analog which is derived from the 24.0-MHz crystal clock. This 1-kHz source hence does not vary as the APBX clock frequency is changed. The millisecond counter wraps at 4,294,967,294 milliseconds or 49.7 days. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1601 Programmable Registers HW_RTC_MILLISECONDS_WR(0); // write an initial starting value to the milliseconds counter Count = HW_RTC_MILLISECONDS_RD(); // read the current value of the milliseconds counter. Address: 8005_6000h base + 20h offset = 8005_6020h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_RTC_MILLISECONDS field descriptions Field COUNT Description 32 bit milliseconds counter. 22.8.4 Real-Time Clock Seconds Counter (HW_RTC_SECONDS) The real-time clock seconds counter is used to maintain real time for applications, even across certain chip power-down states. HW_RTC_SECONDS: 0x030 HW_RTC_SECONDS_SET: 0x034 HW_RTC_SECONDS_CLR: 0x038 HW_RTC_SECONDS_TOG: 0x03C HW_RTC_SECONDS provides access to the 32-bit real-time seconds counter. Both the shadow register on the digital side and the analog side register update every second. When the chip enters the power-down state, the shadow register is powered down and loses its state value. When the chip powers up, the analog side register contents are automatically copied to the shadow register. The reset value of 0x0 for the digital side register is only visible until the copy controller overwrites with the value from the analog side. The analog side register resets to zero only upon power-on reset (POR), i.e., when the battery is first inserted or whenever a battery-less part is plugged into USB power or into a wall transformer. Note that if a low frequency (32.000khz or 32.768khz) crystal is available in the system, then the seconds count and the milliseconds count will be derived from different clocks. Namely, the msec count is derived from the 24MHz crystal and the seconds count from the low-frequency crystal. This limits the precision of the relation between these two clocks. EXAMPLE HW_RTC_SECONDS_WR(0); // write an initial value to the digital side. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1602 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits This value will // be automatically copied to the analog side rt_clock = HW_RTC_SECONDS_RD(); // read the 32 seconds counter value Address: 8005_6000h base + 30h offset = 8005_6030h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_RTC_SECONDS field descriptions Field Description COUNT Increments once per second. 22.8.5 Real-Time Clock Alarm Register (HW_RTC_ALARM) The 32-bit alarm value is matched against the 32-bit seconds counter to detect an alarm condition. HW_RTC_ALARM: 0x040 HW_RTC_ALARM_SET: 0x044 HW_RTC_ALARM_CLR: 0x048 HW_RTC_ALARM_TOG: 0x04C The 32-bit alarm value can be used to awaken the chip from a power-down state or simply to cause an interrupt at a specific time. When the chip enters the power-down state, the shadow register is powered down and loses its state value. When the chip powers up, the analog side register contents are automatically copied to the shadow register. The reset value of 0x0 for the digital side register is only visible until the copy controller overwrites with the value from the analog side. The analog side register resets to zero only upon power-on reset (POR), i.e., when the battery is first inserted or whenever a battery-less part is plugged into a power USB or into a wall transformer. EXAMPLE HW_RTC_ALARM_WR(60); // generate rtc alarm after 60 seconds Address: 8005_6000h base + 40h offset = 8005_6040h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1603 Programmable Registers HW_RTC_ALARM field descriptions Field Description VALUE Seconds match-value used to trigger assertion of the RTC alarm. 22.8.6 Watchdog Timer Register (HW_RTC_WATCHDOG) The 32-bit watch dog timer can be used to reset the chip if enabled and not adequately serviced. HW_RTC_WATCHDOG: 0x050 HW_RTC_WATCHDOG_SET: 0x054 HW_RTC_WATCHDOG_CLR: 0x058 HW_RTC_WATCHDOG_TOG: 0x05C The 32-bit watchdog timer will reset the chip upon decrementing to zero, if this function is enabled and present on the chip. The 1-kHz source is based on a msec pulse from RTC analog which is derived from the 24-MHz crystal oscillator and hence does not vary when the APBX clock is changed. EXAMPLE HW_RTC_WATCHDOG_WR(10000); the chip // reload the watchdog and keep it from resetting Address: 8005_6000h base + 50h offset = 8005_6050h Bit R W 31 Reset 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 COUNT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_RTC_WATCHDOG field descriptions Field COUNT Description If the watchdog timer decrements to zero and the watchdog timer reset is enabled, then the chip will be reset. The watchdog timer decrements once per millisecond, when enabled. 22.8.7 Persistent State Register 0 (HW_RTC_PERSISTENT0) The 32-bit persistent registers are used to retain certain control states during chip wide power-down states. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1604 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits HW_RTC_PERSISTENT0: 0x060 HW_RTC_PERSISTENT0_SET: 0x064 HW_RTC_PERSISTENT0_CLR: 0x068 HW_RTC_PERSISTENT0_TOG: 0x06C The general persistent bits are available for software use. The register initalizes to a known reset pattern. The copy controller overwrites the digital reset values very soon after power on, but not in zero time. EXAMPLE HW_RTC_PERSISTENT0_SET(BM_RTC_PERSISTENT0_ALARM_WAKE_EN); // wake up the chip if the alarm event occurs HW_RTC_PERSISTENT0_SET(BM_RTC_PERSISTENT0_CLOCKSOURCE); // select the 32KHz oscillator as the source for the RTC analog clock Address: 8005_6000h base + 60h offset = 8005_6060h DISABLE_ PSWITCH 16 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLOCKSOURCE 17 AUTO_ RESTART 18 0 0 1 0 0 0 0 0 0 0 0 RSVD1 R LOWERBIAS W 0 0 DISABLE_ XTALOK W Reset 19 0 ADJ_POSLIMITBUCK Bit 20 0 R Reset 21 ALARM_WAKE_ EN 22 RSVD2 23 ALARM_EN 24 RSVD0 25 LCK_SECS 26 THERMAL_ RESET 27 XTAL24MHZ_ PWRUP 28 EXTERNAL_ RESET 29 XTAL32KHZ_ PWRUP 30 XTAL32_FREQ 31 ALARM_WAKE Bit 0 MSEC_RES 0 0 0 HW_RTC_PERSISTENT0 field descriptions Field Description 31-28 This field can be used to allow dcdc startup with lower Liion battery voltages. With the default value of 0x0, ADJ_ the dcdc converter will not startup below 2.83V, and increasing this value will lower the Liion startup POSLIMITBUCK voltage. It is not recommended to set a value higher than 0x6. The value of this field effects the minimum startup voltage as follows: 0x0=2.83V, 0x1=2.78V, 0x2=2.73V, 0x3=2.68V, 0x4=2.62V, 0x5=2.57V, 0x6=2.52V, 0x7-0xF=2.48V. 27-22 RSVD1 21 EXTERNAL_ RESET Reserved for special uses. This bit is set by the analog hardware. On powerup, it indicate to software that that the chip had previously been powered down due to a reset event on the reset pin by an external source. This bit must be cleared Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1605 Programmable Registers HW_RTC_PERSISTENT0 field descriptions (continued) Field Description by software. Note this bit is only valid when 32K XTAL is selected as the clock source of RTC, otherwise the external reset event might not be correctly captured when the reset happens. 20 THERMAL_ RESET This bit is set by the analog hardware. On powerup, it indicate to software that that the chip had previously been powered down due to overheating. This bit must be cleared by software. This bit is analogous to the HW_POWER_STS_THERMAL_WARNING bit only in persistent storage. Note this bit is only valid when 32K XTAL is selected as the clock source of RTC, otherwise the thermal reset event might not be correctly captured when the reset happens. 19 RSVD0 Reserved for special uses. 18 RSVD2 Reserved. 17 AUTO_ RESTART Set to one to enable the chip to automatically power up approximately 180 ms after powering down. 16 DISABLE_ PSWITCH Disables the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL pin voltage by a threshold voltage. Typically, this voltage is created by pulling pswitch up with a current limiting resistor to a higher voltage, such as the Liion battery voltage. 15-14 LOWERBIAS Reduce bias current of 24mhz crystal. b00: nominal, b01: -25%, b10: -25%, b11: -50%, 13 DISABLE_ XTALOK 12-8 MSEC_RES Set to one to disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz. The circuit defaults to enabled and will power down the device if the 24-MHz stop oscillating for any reason. This bit field encodes the value of the millisecond count resolution in a one-hot format. Resolutions supported are: 1, 2, 4, 8, and 16 msec. The bitfield directly gives the resolution without need for decode. 7 Set when the chip is powered up by an alarm event from rtc_ana. Can then be cleared by software as ALARM_WAKE desired. 6 If CLOCKSOURCE (bit 0 of this register) is one, then this bit gives the exact frequency of the 32kHz XTAL32_FREQ crystal. If this bit is zero, the frequency is 32.768kHZ, if it is one, the frequency is 32.000kHz. If CLOCKSOURCE is zero, the value of this bit is immaterial. 5 XTAL32KHZ_ PWRUP Set to one to power up the 32kHz crystal oscillator. Set to zero to disable the oscillator. This bit controls the oscillator at all times (chip powered on or not). 4 XTAL24MHZ_ PWRUP Set to one to keep the 24.0-MHz crystal oscillator powered up while the chip is powered down. Set to zero to disable during chip power down. Note: The oscillator is always on while the chip is powered on. 3 LCK_SECS Set to one to lock down the seconds count. Once this bit is written with a 1, the user will not be able to either write to the seconds register or to change this bit back to a zero -- except by removing the battery. 2 ALARM_EN Set this bit to one to enable the detection of an alarm event. This bit must be turned on before an alarm event can awaken a powered-down device, or before it can generate an alarm interrupt to a powered-up CPU. When the alarm is not present in the device (as indicated by the fuse bits) the copy of shadow0 to persistent0 will not allow bit[2] to be written and persistent bit[2] will always read back 0, regardless of the values in the shadow register. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1606 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits HW_RTC_PERSISTENT0 field descriptions (continued) Field Description 1 This bit is set to one to upon the arrival of an alarm event that powers up the chip. ALARM_EN must be ALARM_WAKE_ set to one to enable the detection of an alarm event. EN This bit is reset by writing a zero directly to the shadow register, which causes the copy controller to move it across to the analog domain. 0 Set to one to select the 32-kHz crystal oscillator as the source for the 32-kHz clock domain used by the CLOCKSOURCE RTC analog domain circuits. Set to zero to select the 24-MHz crystal oscillator as the source for generating the 32-kHz clock domain used by the RTC analog domain circuits. 22.8.8 Persistent State Register 1 (HW_RTC_PERSISTENT1) The 32-bit persistent registers are used to retain certain control states during chip wide power-down states. HW_RTC_PERSISTENT1: 0x070 HW_RTC_PERSISTENT1_SET: 0x074 HW_RTC_PERSISTENT1_CLR: 0x078 HW_RTC_PERSISTENT1_TOG: 0x07C The register initalizes to a known reset pattern. The copy controller overwrites this digital reset value very soon after power on but not in zero time. EXAMPLE HW_RTC_PERSISTENT1_WR(0x12345678); // this write will ultimately push data to the analog side via the copy controller Address: 8005_6000h base + 70h offset = 8005_6070h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GENERAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_RTC_PERSISTENT1 field descriptions Field GENERAL Description Firmware use, defined as follows: 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 ENUMERATE_500MA_TWICE -- Enumerate at 500mA twice before dropping back to 100mA. USB_BOOT_PLAYER_MODE -- Boot to player when connected to USB. SKIP_CHECKDISK -- Run Checkdisk flag. USB_LOW_POWER_MODE -- USB Hi/Lo Current select. OTG_HNP_BIT -- HNP has been required if set to one. OTG_ATL_ROLE_BIT -- USB role. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1607 Programmable Registers 22.8.9 Persistent State Register 2 (HW_RTC_PERSISTENT2) The 32-bit persistent registers are used to retain certain control states during chip-wide power-down states. HW_RTC_PERSISTENT2: 0x080 HW_RTC_PERSISTENT2_SET: 0x084 HW_RTC_PERSISTENT2_CLR: 0x088 HW_RTC_PERSISTENT2_TOG: 0x08C The register initalizes to a known reset pattern. The copy controller overwrites this digital reset value very soon after power on but not in zero time. EXAMPLE HW_RTC_PERSISTENT2_WR(0x12345678); // this write will ultimately push data to the analog side via the copy controller Address: 8005_6000h base + 80h offset = 8005_6080h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GENERAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_RTC_PERSISTENT2 field descriptions Field GENERAL Description FIRMWARE/SOFTWARE 22.8.10 Persistent State Register 3 (HW_RTC_PERSISTENT3) The 32-bit persistent registers are used to retain certain control states during chip-wide power-down states. HW_RTC_PERSISTENT3: 0x090 HW_RTC_PERSISTENT3_SET: 0x094 HW_RTC_PERSISTENT3_CLR: 0x098 HW_RTC_PERSISTENT3_TOG: 0x09C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1608 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits The register initalizes to a known reset pattern. The copy controller overwrites this digital reset value very soon after power on but not in zero time. EXAMPLE HW_RTC_PERSISTENT3_WR(0x12345678); // this write will ultimately push data to the analog side via the copy controller Address: 8005_6000h base + 90h offset = 8005_6090h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GENERAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_RTC_PERSISTENT3 field descriptions Field Description GENERAL FIRMWARE/SOFTWARE 22.8.11 Persistent State Register 4 (HW_RTC_PERSISTENT4) The 32-bit persistent registers are used to retain certain control states during chip-wide power-down states. HW_RTC_PERSISTENT4: 0x0A0 HW_RTC_PERSISTENT4_SET: 0x0A4 HW_RTC_PERSISTENT4_CLR: 0x0A8 HW_RTC_PERSISTENT4_TOG: 0x0AC The register initalizes to a known reset pattern. The copy controller overwrites this digital reset value very soon after power on but not in zero time. EXAMPLE HW_RTC_PERSISTENT4_WR(0x12345678); // this write will ultimately push data to the analog side via the copy controller Address: 8005_6000h base + A0h offset = 8005_60A0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GENERAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1609 Programmable Registers HW_RTC_PERSISTENT4 field descriptions Field Description GENERAL FIRMWARE/SOFTWARE 22.8.12 Persistent State Register 5 (HW_RTC_PERSISTENT5) The 32-bit persistent registers are used to retain certain control states during chip-wide power-down states. HW_RTC_PERSISTENT5: 0x0B0 HW_RTC_PERSISTENT5_SET: 0x0B4 HW_RTC_PERSISTENT5_CLR: 0x0B8 HW_RTC_PERSISTENT5_TOG: 0x0BC The register initalizes to a known reset pattern. The copy controller overwrites this digital reset value very soon after power on but not in zero time. EXAMPLE HW_RTC_PERSISTENT5_WR(0x12345678); // this write will ultimately push data to the analog side via the copy controller Address: 8005_6000h base + B0h offset = 8005_60B0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GENERAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_RTC_PERSISTENT5 field descriptions Field GENERAL Description FIRMWARE/SOFTWARE 22.8.13 Real-Time Clock Debug Register (HW_RTC_DEBUG) This 32-bit register provides debug read access to various internal states for diagnostic purposes. HW_RTC_DEBUG: 0x0C0 HW_RTC_DEBUG_SET: 0x0C4 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1610 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits HW_RTC_DEBUG_CLR: 0x0C8 HW_RTC_DEBUG_TOG: 0x0CC Read-only view into the internals of the digital side of the RTC for diagnostic purposes. EXAMPLE DebugValue = HW_RTC_DEBUG_RD(); // read debug register value Address: 8005_6000h base + C0h offset = 8005_60C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1611 Programmable Registers 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 RSVD0 R 1 0 WATCHDOG_RESET 14 WATCHDOG_RESET_MASK 15 Bit W Reset 0 0 0 0 0 0 0 0 0 0 HW_RTC_DEBUG field descriptions Field 31-2 RSVD0 Description Debug read-only view of various state machine bits. 1 WATCHDOG_ RESET_MASK When set, mask the reset generation by the watchdog timer for testing purposes. 0 WATCHDOG_ RESET Reflects the state of the watchdog reset. Used for testing purposes so the watchdog can be tested without resetting part. When set, Watchdog reset is asserted. 22.8.14 Real-Time Clock Version Register (HW_RTC_VERSION) Version register. EXAMPLE VersionValue = HW_RTC_VERSION_RD(); // read debug register value i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1612 Freescale Semiconductor, Inc. Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits Address: 8005_6000h base + D0h offset = 8005_60D0h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 HW_RTC_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1613 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1614 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) 23.1 Timers and Rotary Decoder (TIMROT) Overview The device implements four timers and a rotary decoder, as shown in Figure 23-1. The timers and decoder can take their inputs from any of the pins defined for PWM, rotary encoders, or certain divisions from the 32-KHz clock input. Therefore, the PWM pins can be inputs or outputs, depending on the application. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1615 Timer ARM Core SRAM 24-MHz XTAL Osc. AHB AHB Slave Divide by n AHB Master Shared DMA AHB-to-APBX Bridge APBX APBX Master PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] PWM[5] PWM[6] PWM[7] ROTARY_B ROTARY_A 32-kHz Osc. Timer/Rotary Decoder Programmable Registers Timer 0 1/1, 1/ 2, 1/4, 1/8 Timer 1 1/1, 1/ 2, 1/4, 1/8 Timer 2 1/1, 1/ 2, 1/4, 1/8 Timer 3 1/1, 1/ 2, 1/4, 1/8 Rotary Up/Down Counter Timers and Rotary Decoder Figure 23-1. Timers and Rotary Decoder Block Diagram The timer/rotary decoder block is a programmed I/O interface connected to the APBX bus. Recall that the APBX typically runs at a divided clock rate from the 24-MHz crystal clock. Each timer and rotary channel can sample at a rate that is further subdivided from the APBX clock. Each timer can select a different pre-scaler value. 23.2 Timer There are two running mode for each timer. One is fixed count mode and the other is match count mode. By default Timer works in fixed count mode, and match count mode can be enabled by writing 1'b1 to bit MATCH_MODE of register TIMERx Control and Status Register (x = 0-3). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1616 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) 23.2.1 Fixed count mode In this mode, the timer consists of a 32-bit fixed count value and a 32-bit free-running count value. The free running count decrements until it reaches 0 where it sets an interrupt status bit associated with the counter. * If the RELOAD bit is set to 1, then the fixed count is automatically copied to the free-running counter and the count continues. * If the RELOAD bit is not set, the timer stalls when it reaches 0. Figure 23-2 shows a detailed view of each timer in fixed count mode. ? == match & match_mode Timer I/O 32-Bit Running Count 32-Bit Match Count match_mode == 1 Mode Controller Edge Detect Tick Divide byy 1, 4, 8, 32 ALWAYS TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] PWM[5] PWM[6] PWM[7] ROTARY_A ROTARY_B NEVER TICK 32-kHz Input 24-MHz XTAL Osc. Divide APBX clk by n Divide by 1, 2, 4, 8 Gated clk Figure 23-2. Timer 0, Timer 1, Timer 2 or Timer 3 Detail Each timer has an UPDATE bit that controls whether the free-running counter is loaded at the same time the fixed-count register is written from the CPU. The output of each timer's source select has a polarity control that allows the timer to operate on either edge. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1617 Timer Table 23-1 lists the timer state machine transitions. Table 23-1. Timer State Machine Transitions UPDATE RELOAD RUNNING 0 0 PIO writes to the fixed-count bit field have no effect on the running count. 0 1 The value written to the fixed count is used to reload the running count the next time it reaches 0. When the fixed count has been written with a value of 0 and the running count reaches 0, it continuously copies the fixed count value to the running count. Therefore, writing a non-zero value to the fixed count register kicks off a continuous count and update operation. 1 0 The value written to the fixed count bit field is copied, immediately to the running count, restarting any existing running count operation. When the new running count reaches 0, it freezes. 1 1 The value written to the fixed count bit field is copied, immediately to the running count, restarting any existing running count operation. When the new running count reaches 0, it is reloaded from the value in the fixed count bit field, therefore running continuously using the newly supplied fixed count. When generating a periodic timer interrupt using the RELOAD bit, the user must compute proper fixed-count value (count_value) based on clock speeds and clock divider settings. Note that, in this case, the actual value written to the FIXED_COUNT register field should be count_value - 1. For one-shot interrupts (RELOAD bit not set), the value written should be count_value. Any timer interrupt can be programmed as an FIQ or as a regular IRQ. See Interrupt Collector (ICOLL) Overview for programming details. For proper detection of the input source signal, it should be much slower than the prescaled APBX clock (not greater than one-third the frequency of the pre-scaled APBX clock). Selecting the ALWAYS tick causes the timer to decrement continuously at the rate established by the pre-scaled APBX clock. The NEVER TICK selection causes the timer to stall. Setting the fixed-count to 0xFFFFFFFF and setting the RELOAD bit causes the timer to operate continuously with a 4,294,967,296 count. The state of the 32-bit free-running count can be read by the CPU for each timer. 23.2.2 Match count mode In this mode, the timer consists of a 32-bit match count value and a 32-bit free-running count value. This mode is enabled once MATCH MODE of Register TIMERx Control and Status Register (x = 0-3) is written to 1. At the same time, the free-running count returns to its default start value 0xFFFF_FFFF, then starts decrementing from 0xFFFF_FFFF to 0. Every time it decreases to 0, it restores to 0xFFFF_FFFF and keeps decreasing repeatedly. During this ceaseless decrement, interrupt is triggered every time free running count equals match count. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1618 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) Figure 23-3 shows a detailed view of each timer in match mode. ? == match & match_mode Timer I/O 32-Bit Running Count 32-Bit Match Count match_mode == 1 Mode Controller Edge Detect Tick Divide byy 1, 4, 8, 32 ALWAYS TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] PWM[5] PWM[6] PWM[7] ROTARY_A ROTARY_B NEVER TICK 32-kHz Input 24-MHz XTAL Osc. Divide APBX clk by n Divide by 1, 2, 4, 8 Gated clk Figure 23-3. Timer 0, Timer 1, Timer 2 or Timer 3 Detail In match mode, period timer interrupt can be triggered by modifying the match register to a proper value adequately smaller than the current value of the match register in every interrupt service routine, which is usually calculated by subtracting a delta from the current value of the match register. To get a group of interrupts with fixed interval, constant delta is used, and to get interrupts with variable interval, variable delta is used. Any timer interrupt can be programmed as a FIQ or as a regular IRQ. See Interrupt Collector (ICOLL) Overview for programming details. For proper detection of the input source signal, it should be much slower than the prescaled APBX clock (not greater than one-third the frequency of the pre-scaled APBX clock). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1619 Timer Selecting the ALWAYS tick causes the timer to decrement continuously at the rate established by the pre-scaled APBX clock. The NEVER TICK selection causes the timer to stall. The state of the 32-bit free-running count can be read by the CPU for each timer. 23.2.3 Using External Signals as Inputs External signals can be used as inputs to the block. They can be used as either the test signal or sampling input signals (duty cycle or normal timer mode). This can be accomplished by using the rotary input pins or any unused PWM pins. If PWM pins are being used for this purpose, conflicts with the PWM or other blocks that could drive the pins as outputs must be avoided. In this case, the PWM pins being used should be programmed as GPIO inputs. (See Pin Control and GPIO Overview for details.) Then, the external signal can be wired to the pin, and the PWM number selected in the appropriate TIMROT registers. 23.2.4 Timer 3 and Duty Cycle Mode Timer 3 can operate in the same modes as Timer 0, Timer 1, and Timer 2. However, it has an additional duty cycle measurement mode. Figure 23-4 shows a detailed view of Timer 3 in duty cycle mode. This mode can be enabled by writing 1 to bit DUTY_CYCLE of Register TIMER3 Control and Status Register. When this bit is set, no matter what value MATCH MODE of Register TIMER3 Control and Status Register is, Timer 3 works in duty cycle mode. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1620 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) Timer I/O 32-Bit Low Count 32-Bit Fixed count 32-Bit Running Count Hold, load, copy Hold, down, load, copy Mode Controller ALWAYS TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] PWM[5] PWM[6] PWM[7] ROTARY_A ROTARY_B NEVER TICK Tick LVL Divide byy 1, 4, 8, 32 Edge Detect 32-kHz Input 24-MHz XTAL Osc. Divide by n APBX clk Divide by 1, 2, 4, 8 Gated clk Figure 23-4. Timer 3 Detail In the duty cycle mode, Timer 3 samples the free-running counter at the rising and falling edges of the input test signal, resetting the free-running counter on the same clock that is sampled. * On the rising edge of the test signal, the free-running count is copied to the LOW_RUNNING_COUNT bit field of the HW_TIMROT_TIMCOUNT3 register. * On the falling edge of the source clock, the free-running count is copied to the HIGH_FIXED_COUNT bit field (as shown in Figure 23-5). Low Count High Count Input Figure 23-5. Pulse-Width Measurement Mode i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1621 Rotary Decoder * Once duty cycle mode is programmed and the input signal is stable, software should poll the DUTY_VALID bit in the HW_TIMROT_TIMCTRL3 register. * This bit is automatically set and cleared by the hardware. When this bit is set, count values in the HW_TIMROT_TIMCOUNT3 register are stable and ready to be read. Refer to the Timer 3 control and status register, HW_TIMROT_TIMCTRL3, where the DUTY_CYCLE bit controls whether HW_TIMROT_TIMCOUNT3 register's LOW_RUNNING_COUNT bit field reads back the running count or the low count of a duty cycle measurement. The DUTY_CYCLE bit also controls whether the HIGH_FIXED_COUNT bit field reads back the fixed-count value used in normal timer operations or the duty cycle high-time measurement. It should be noted that for duty cycle mode to function properly, the timer tick source selected (SELECT field of the HW_TIMROT_TIMCTRL3 register) should be an appropriate frequency to sample the test signal. The NEVER_TICK value should never be used in this mode, as it yields incorrect count results. 23.3 Rotary Decoder The rotary decoder uses two input selectors and edge detectors, as shown in Figure 23-6. It includes a debounce circuit for each input, as shown in Figure 23-7. This figure shows the debounce circuit for input A, though the circuit is identical for input B. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1622 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) Timer I/O Signed 16-Bit Up/Down Count 32-kHz Input Hold, load, inc/dec NEVER TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] PWM[5] PWM[6] PWM[7] Mode Controller and Debounce Circuit ROT SELA Edge Detect ROTARY_A ROTARY_B NEVER TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] PWM[5] PWM[6] PWM[7] ROTARY_A ROTARY_B ROT SELB Edge Detect APBX Clock Figure 23-6. Detail of Rotary Decoder i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1623 Rotary Decoder ~oversamp_by_8 Adebounce J Q DQ DQ DQ DQ DQ DQ DQ DQ *Q *Q *Q *Q *Q *Q *Q *Q K Q* ~oversamp_by_8 Flip-flops sample and advance at a divided 32-kHz rate NEVER TICK PWM[0] PWM[1] PWM[2] PWM[3] PWM[4] PWM[5] PWM[6] PWM[7] ROTARY_A ROTARY_B Figure 23-7. Rotary Decoding Mode-Debouncing Rotary A and B Inputs A state machine following rotary decoder transition is provided to detect the direction of rotation and the time at which to increment or decrement the 16-bit signed counter in HW_TIMROT_ROTCOUNT. The updown counter can be treated as either a relative count or an absolute count, depending on the state of the HW_TIMROT_ROTCTRL_RELATIVE bit. When set to the relative mode, each read of the counter has the side effect of resetting it. The edge detectors respond to both edges of each input to determine the self-timed transition inputs to the state machine (see Figure 23-8). 11 00 inc Input A Input B 10 01 10 11 00 dec 01 Figure 23-8. Rotary Decoding Mode-Input Transitions i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1624 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) Figure 23-8 shows that each detected edge causes a transition in the decoder state machine. Not all transitions are legal (see Table 23-2). For example, there is no legal way to transition directly from state 11 to 00 using normal inputs. In the cases where this occurs, the state machine goes to an alternate set of states and follows the input sequence until a valid sequence leading to state 00 is detected. No increment or decrement action is taken from the alternate state sequence. Table 23-2. Rotary Decoder State Machine Transitions CURRENT STATE INPUT BA=00 INPUT BA=01 INPUT BA=10 INPUT BA=11 00 00 01 00, dec 01 10 error 01 error 11 10 00, inc error 10 11 11 error 01 10 11 23.3.1 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. 23.4 Programmable Registers i.MX28 TIMROT Hardware Register Format Summary HW_TIMROT memory map Absolute address (hex) Register name 8006_8000 Rotary Decoder Control Register (HW_TIMROT_ROTCTRL) 32 R/W 8006_8010 Rotary Decoder Up/Down Counter Register (HW_TIMROT_ROTCOUNT) 32 R 0000_0000h 23.4.2/1629 8006_8020 Timer 0 Control and Status Register (HW_TIMROT_TIMCTRL0) 32 R/W 0000_0000h 23.4.3/1630 8006_8030 Timer 0 Runing Count Register (HW_TIMROT_RUNNING_COUNT0) 32 R 0000_0000h 23.4.4/1632 8006_8040 Timer 0 Fixed Count Register (HW_TIMROT_FIXED_COUNT0) 32 R/W 0000_0000h 23.4.5/1632 Width Access (in bits) Reset value Section/ page FE00_0000h 23.4.1/1626 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1625 Programmable Registers HW_TIMROT memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8006_8050 Timer 0 Match Count Register (HW_TIMROT_MATCH_COUNT0) 32 R/W 0000_0000h 23.4.6/1633 8006_8060 Timer 1 Control and Status Register (HW_TIMROT_TIMCTRL1) 32 R/W 0000_0000h 23.4.7/1633 8006_8070 Timer 1 Runing Count Register (HW_TIMROT_RUNNING_COUNT1) 32 R 0000_0000h 23.4.8/1635 8006_8080 Timer 1 Fixed Count Register (HW_TIMROT_FIXED_COUNT1) 32 R/W 0000_0000h 23.4.9/1636 8006_8090 Timer 1 Match Count Register (HW_TIMROT_MATCH_COUNT1) 32 R/W 0000_0000h 23.4.10/ 1636 8006_80A0 Timer 2 Control and Status Register (HW_TIMROT_TIMCTRL2) 32 R/W 0000_0000h 23.4.11/ 1637 8006_80B0 Timer 2 Runing Count Register (HW_TIMROT_RUNNING_COUNT2) 32 R 0000_0000h 23.4.12/ 1639 8006_80C0 Timer 2 Fixed Count Register (HW_TIMROT_FIXED_COUNT2) 32 R/W 0000_0000h 23.4.13/ 1639 8006_80D0 Timer 2 Match Count Register (HW_TIMROT_MATCH_COUNT2) 32 R/W 0000_0000h 23.4.14/ 1640 8006_80E0 Timer 3 Control and Status Register (HW_TIMROT_TIMCTRL3) 32 R/W 0000_0000h 23.4.15/ 1640 8006_80F0 Timer 3 Running Count Register (HW_TIMROT_RUNNING_COUNT3) 32 R 0000_0000h 23.4.16/ 1643 8006_8100 Timer 3 Count Register (HW_TIMROT_FIXED_COUNT3) 32 R/W 0000_0000h 23.4.17/ 1644 8006_8110 Timer 3 Match Count Register (HW_TIMROT_MATCH_COUNT3) 32 R/W 0000_0000h 23.4.18/ 1644 8006_8120 TIMROT Version Register (HW_TIMROT_VERSION) 32 R 0200_0000h 23.4.19/ 1645 23.4.1 Rotary Decoder Control Register (HW_TIMROT_ROTCTRL) The Rotary Decoder Control Register specifies the reset state and the source selection for the rotary decoder. In addition, it specifies the polarity of any external input source that is used. This register also contains some general block controls including soft reset, clock gate, and present bits. HW_TIMROT_ROTCTRL: 0x000 HW_TIMROT_ROTCTRL_SET: 0x004 HW_TIMROT_ROTCTRL_CLR: 0x008 HW_TIMROT_ROTCTRL_TOG: 0x00C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1626 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) EXAMPLE HW_TIMROT_ROTCTRL_WR(0x00000076); // Set up rotary control fields. 26 25 TIM1_PRESENT TIM0_PRESENT 24 23 22 21 20 19 18 17 16 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POLARITY_A 27 POLARITY_B 28 TIM3_PRESENT 29 ROTARY_PRESENT 30 CLKGATE 31 SFTRST Bit TIM2_PRESENT Address: 8006_8000h base + 0h offset = 8006_8000h 0 0 R STATE DIVIDER W Bit RSRVD3 RELATIVE R OVERSAMPLE Reset SELECT_B SELECT_A W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_ROTCTRL field descriptions Field 31 SFTRST Description This bit must be set to zero to enable operation of any timer or the rotary decoder. When set to one, it forces a block-level reset and gates off the clocks to the block. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1627 Programmable Registers HW_TIMROT_ROTCTRL field descriptions (continued) Field 30 CLKGATE 29 ROTARY_ PRESENT Description This bit must be set to zero for normal operation. When set to one, it gates off the clocks to the block. 0= Rotary decoder is not present in this product. 1= Rotary decoder is present is in this product. 28 0= TIMER3 is not present in this product. TIM3_PRESENT 1= TIMER3 is present is in this product. 27 0= TIMER2 is not present in this product. TIM2_PRESENT 1= TIMER2 is present is in this product. 26 0= TIMER1 is not present in this product. TIM1_PRESENT 1= TIMER1 is present is in this product. 25 0= TIMER0 is not present in this product. TIM0_PRESENT 1= TIMER0 is present is in this product. 24-22 STATE Read-only view of the rotary decoder transition detecting state machine. 21-16 DIVIDER This bit field determines the divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing) the rotary A and B inputs. Note that the divider value is actually the (value of this field+1). 15-13 RSRVD3 Always write zeroes to this bit field. 12 RELATIVE 11-10 OVERSAMPLE Set this bit to one to cause the rotary decoders updown counter to be reset to zero whenever it is read. This bit field determines the oversample rate to use in debouncing Rotary A and B inputs. 0x0 0x1 0x2 0x3 8X -- 8x Oversample: 8 successive ones or zeroes to transition. 4X -- 4x Oversample: 4 successive ones or zeroes to transition. 2X -- 2x Oversample: 2 successive ones or zeroes to transition. 1X -- 1x Oversample: Transition on each first input change. 9 POLARITY_B Set this bit to one to invert the input to the edge detector. 8 POLARITY_A Set this bit to one to invert the input to the edge detector. 7-4 SELECT_B Selects the source for the timer tick that increments the free-running counter that measures the A2B and B2A overlap counts. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA NEVER_TICK -- SelectB: Never tick. PWM0 -- SelectB: Input from PWM0. PWM1 -- SelectB: Input from PWM1. PWM2 -- SelectB: Input from PWM2. PWM3 -- SelectB: Input from PWM3. PWM4 -- SelectB: Input from PWM4. PWM5 -- SelectB: Input from PWM5. PWM6 -- SelectB: Input from PWM6. PWM7 -- SelectB: Input from PWM7. ROTARYA -- SelectB: Input from Rotary A. ROTARYB -- SelectB: Input from Rotary B. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1628 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) HW_TIMROT_ROTCTRL field descriptions (continued) Field Description SELECT_A Selects the source for the timer tick that increments the free-running counter that measures the A2B and B2A overlap counts. NEVER_TICK -- SelectA: Never tick. PWM0 -- SelectA: Input from PWM0. PWM1 -- SelectA: Input from PWM1. PWM2 -- SelectA: Input from PWM2. PWM3 -- SelectA: Input from PWM3. PWM4 -- SelectA: Input from PWM4. PWM5 -- SelectB: Input from PWM5. PWM6 -- SelectB: Input from PWM6. PWM7 -- SelectB: Input from PWM7. ROTARYA -- SelectB: Input from Rotary A. ROTARYB -- SelectB: Input from Rotary B. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 23.4.2 Rotary Decoder Up/Down Counter Register (HW_TIMROT_ROTCOUNT) The Rotary Decoder Up/Down Counter Register contains the timer counter value that counts up or down as the rotary encoder is rotated. This register contains the read-only current count for the rotary decoder. EXAMPLE count = HW_TIMROT_ROTCTRL_RD(); // Read count Address: 8006_8000h base + 10h offset = 8006_8010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSRVD1 R 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 UPDOWN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_ROTCOUNT field descriptions Field Description 31-16 RSRVD1 Always write zeroes to this bit field. UPDOWN At each edge of the Rotary A input, the Rotary B value is sampled, similarly at each edge of the Rotary B input, the Rotary A input is sampled. These values drive a rotary decoder state machine that determines when this counter is incremented or decremetned. When set in the RELATIVE mode, reads from this register clear this register as a side effect. Counter values in this register are signed 16-bit values. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1629 Programmable Registers 23.4.3 Timer 0 Control and Status Register (HW_TIMROT_TIMCTRL0) The Timer 0 Control and Status Register specifies timer control parameters, as well as interrupt status and the enable for Timer 0. HW_TIMROT_TIMCTRL0: 0x020 HW_TIMROT_TIMCTRL0_SET: 0x024 HW_TIMROT_TIMCTRL0_CLR: 0x028 HW_TIMROT_TIMCTRL0_TOG: 0x02C EXAMPLE HW_TIMROT_TIMCTRLn_WR(0, 0x00000008); // Set up control fields for timer0 Address: 8006_8000h base + 20h offset = 8006_8020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD3 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UPDATE RELOAD Bit 0 0 0 0 RSRVD2 IRQ IRQ_EN R 0 0 W Reset 0 0 MATCH_MODE Reset POLARITY W 0 RSRVD1 0 0 PRESCALE 0 0 SELECT 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1630 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) HW_TIMROT_TIMCTRL0 field descriptions Field 31-16 RSRVD3 15 IRQ Description Always write zeroes to this bit field. This bit is set to one when Timer 0 decrements to zero. Write a zero to clear it or use Clear SCT mode. 14 IRQ_EN Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter mode. 13-12 RSRVD2 Always write zeroes to this bit field. 11 Set this bit to one to enable timer match mode MATCH_MODE 10-9 RSRVD1 8 POLARITY Always write zeroes to this bit field. Set this bit to one to invert the input to the edge detector. 0: Positive edge detection. 1: Negative edge detection. 7 UPDATE Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count register value is written. 6 RELOAD Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of zero. When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. 5-4 PRESCALE Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency. 0x0 0x1 0x2 0x3 SELECT DIV_BY_1 -- PreScale: Divide the APBX clock by 1. DIV_BY_2 -- PreScale: Divide the APBX clock by 2. DIV_BY_4 -- PreScale: Divide the APBX clock by 4. DIV_BY_8 -- PreScale: Divide the APBX clock by 8. Selects the source for the timer tick that decrements the free running counter. Note: programming an undefined value will result in "always tick" behavior. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF NEVER_TICK -- Never tick. PWM0 -- Input from PWM0. PWM1 -- Input from PWM1. PWM2 -- Input from PWM2. PWM3 -- Input from PWM3. PWM4 -- Input from PWM4. PWM5 -- Input from PWM5. PWM6 -- Input from PWM6. PWM7 -- Input from PWM7. ROTARYA -- Input from Rotary A. ROTARYB -- Input from Rotary B. 32KHZ_XTAL -- Input from 32-kHz crystal. 8KHZ_XTAL -- Input from 8-kHz (divided from 32-kHz crystal). 4KHZ_XTAL -- Input from 4-kHz (divided from 32-kHz crystal). 1KHZ_XTAL -- Input from 1-kHz (divided from 32-kHz crystal). TICK_ALWAYS -- Always tick. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1631 Programmable Registers 23.4.4 Timer 0 Runing Count Register (HW_TIMROT_RUNNING_COUNT0) The Timer 0 Running Count Register contains the timer running counter values for Timer 0. Address: 8006_8000h base + 30h offset = 8006_8030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUNNING_COUNT R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_RUNNING_COUNT0 field descriptions Field Description RUNNING_ COUNT This bit field shows the current state of the running count as it decrements. 23.4.5 Timer 0 Fixed Count Register (HW_TIMROT_FIXED_COUNT0) The Timer 0 Fixed Count Register contains the fixed timer counter values for Timer 0. EXAMPLE HW_TIMROT_FIXED_COUNTn_WR(0, 0x0000f0dd); // Set up timer fixed count Address: 8006_8000h base + 40h offset = 8006_8040h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIXED_COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_FIXED_COUNT0 field descriptions Field Description FIXED_COUNT Software loads the fixed count bit field with the value to down count. If the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. If the update bit is set to one, then the new value is also copied into the running count, immediately. If both the reload and update bits are set to zero, then the new value is never picked up by the running count. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1632 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) 23.4.6 Timer 0 Match Count Register (HW_TIMROT_MATCH_COUNT0) The Timer 0 Match Count Register contains the match timer counter values for Timer 0. EXAMPLE HW_TIMROT_MATCH_COUNTn_WR(0, 0x0000f0dd); // Set up timer match count Address: 8006_8000h base + 50h offset = 8006_8050h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH_COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_MATCH_COUNT0 field descriptions Field Description MATCH_COUNT Software compares the match count bit field with the value to down count. If they equal to each other, interrupt is trigger. 23.4.7 Timer 1 Control and Status Register (HW_TIMROT_TIMCTRL1) The Timer 1 Control and Status Register specifies timer control parameters, as well as interrupt status and the enable for Timer 1. HW_TIMROT_TIMCTRL1: 0x060 HW_TIMROT_TIMCTRL1_SET: 0x064 HW_TIMROT_TIMCTRL1_CLR: 0x068 HW_TIMROT_TIMCTRL1_TOG: 0x06C EXAMPLE HW_TIMROT_TIMCTRLn_WR(1, 0x00000008); // Set up control fields for timer1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1633 Programmable Registers Address: 8006_8000h base + 60h offset = 8006_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD3 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UPDATE RELOAD Bit 0 0 0 0 RSRVD2 IRQ IRQ_EN R 0 0 W Reset 0 0 RSRVD1 MATCH_MODE Reset POLARITY W 0 0 0 PRESCALE 0 0 SELECT 0 0 0 0 HW_TIMROT_TIMCTRL1 field descriptions Field 31-16 RSRVD3 15 IRQ Description Always write zeroes to this bit field. This bit is set to one when Timer 1 decrements to zero. Write a zero to clear it or use Clear SCT mode. 14 IRQ_EN Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter mode. 13-12 RSRVD2 Always write zeroes to this bit field. 11 Set this bit to one to enable timer match mode MATCH_MODE 10-9 RSRVD1 8 POLARITY Always write zeroes to this bit field. Set this bit to one to invert the input to the edge detector. 0: Positive edge detection. 1: Invert to negative edge detection. 7 UPDATE Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count register value is written. 6 RELOAD Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1634 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) HW_TIMROT_TIMCTRL1 field descriptions (continued) Field Description zero. When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. 5-4 PRESCALE Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency. DIV_BY_1 -- PreScale: Divide the APBX clock by 1. DIV_BY_2 -- PreScale: Divide the APBX clock by 2. DIV_BY_4 -- PreScale: Divide the APBX clock by 4. DIV_BY_8 -- PreScale: Divide the APBX clock by 8. 0x0 0x1 0x2 0x3 SELECT Selects the source for the timer tick that decrements the free running counter. Note: programming an undefined value will result in "always tick" behavior. NEVER_TICK -- Never tick. PWM0 -- Input from PWM0. PWM1 -- Input from PWM1. PWM2 -- Input from PWM2. PWM3 -- Input from PWM3. PWM4 -- Input from PWM4. PWM5 -- Input from PWM5. PWM6 -- Input from PWM6. PWM7 -- Input from PWM7. ROTARYA -- Input from Rotary A. ROTARYB -- Input from Rotary B. 32KHZ_XTAL -- Input from 32-kHz crystal. 8KHZ_XTAL -- Input from 8-kHz (divided from 32-kHz crystal). 4KHZ_XTAL -- Input from 4-kHz (divided from 32-kHz crystal). 1KHZ_XTAL -- Input from 1-kHz (divided from 32-kHz crystal). TICK_ALWAYS -- Always tick. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 23.4.8 Timer 1 Runing Count Register (HW_TIMROT_RUNNING_COUNT1) The Timer 1 Running Count Register contains the timer running counter values for Timer 1. Address: 8006_8000h base + 70h offset = 8006_8070h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUNNING_COUNT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1635 Programmable Registers HW_TIMROT_RUNNING_COUNT1 field descriptions Field Description RUNNING_ COUNT This bit field shows the current state of the running count as it decrements. 23.4.9 Timer 1 Fixed Count Register (HW_TIMROT_FIXED_COUNT1) The Timer 1 Fixed Count Register contains the fixed timer counter values for Timer 1. EXAMPLE HW_TIMROT_FIXED_COUNTn_WR(1, 0x0000f0dd); // Set up timer fixed count Address: 8006_8000h base + 80h offset = 8006_8080h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIXED_COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_FIXED_COUNT1 field descriptions Field Description FIXED_COUNT Software loads the fixed count bit field with the value to down count. If the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. If the update bit is set to one, then the new value is also copied into the running count, immediately. If both the reload and update bits are set to zero, then the new value is never picked up by the running count. 23.4.10 Timer 1 Match Count Register (HW_TIMROT_MATCH_COUNT1) The Timer 1 Match Count Register contains the match timer counter values for Timer 1. EXAMPLE HW_TIMROT_MATCH_COUNTn_WR(1, 0x0000f0dd); // Set up timer match count Address: 8006_8000h base + 90h offset = 8006_8090h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH_COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1636 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) HW_TIMROT_MATCH_COUNT1 field descriptions Field Description MATCH_COUNT Software compares the match count bit field with the value to down count. If they equal to each other, interrupt is trigger. 23.4.11 Timer 2 Control and Status Register (HW_TIMROT_TIMCTRL2) The Timer 2 Control and Status Register specifies timer control parameters, as well as interrupt status and the enable for Timer 2. HW_TIMROT_TIMCTRL2: 0x0a0 HW_TIMROT_TIMCTRL2_SET: 0x0a4 HW_TIMROT_TIMCTRL2_CLR: 0x0a8 HW_TIMROT_TIMCTRL2_TOG: 0x0aC EXAMPLE HW_TIMROT_TIMCTRLn_WR(2, 0x00000008); // Set up control fields for timer2 Address: 8006_8000h base + A0h offset = 8006_80A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD3 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1637 12 RSRVD2 IRQ IRQ_EN R 0 0 W Reset 0 0 11 10 9 8 7 6 RELOAD 13 UPDATE 14 0 0 0 5 4 3 2 1 0 RSRVD1 MATCH_MODE 15 Bit POLARITY Programmable Registers 0 0 0 PRESCALE 0 0 SELECT 0 0 0 0 HW_TIMROT_TIMCTRL2 field descriptions Field 31-16 RSRVD3 15 IRQ Description Always write zeroes to this bit field. This bit is set to one when Timer 2 decrements to zero. Write a zero to clear it or use Clear SCT mode. 14 IRQ_EN Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter mode. 13-12 RSRVD2 Always write zeroes to this bit field. 11 Set this bit to one to enable timer match mode MATCH_MODE 10-9 RSRVD1 8 POLARITY Always write zeroes to this bit field. Set this bit to one to invert the input to the edge detector. 0: Positive edge detection. 1: Invert to negative edge detection. 7 UPDATE Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count register value is written. 6 RELOAD Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of zero. When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. 5-4 PRESCALE Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency. 0x0 0x1 0x2 0x3 SELECT DIV_BY_1 -- PreScale: Divide the APBX clock by 1. DIV_BY_2 -- PreScale: Divide the APBX clock by 2. DIV_BY_4 -- PreScale: Divide the APBX clock by 4. DIV_BY_8 -- PreScale: Divide the APBX clock by 8. Selects the source for the timer tick that decrements the free running counter. Note: programming an undefined value will result in "always tick" behavior. 0x0 0x1 NEVER_TICK -- Never tick. PWM0 -- Input from PWM0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1638 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) HW_TIMROT_TIMCTRL2 field descriptions (continued) Field Description PWM1 -- Input from PWM1. PWM2 -- Input from PWM2. PWM3 -- Input from PWM3. PWM4 -- Input from PWM4. PWM5 -- Input from PWM5. PWM6 -- Input from PWM6. PWM7 -- Input from PWM7. ROTARYA -- Input from Rotary A. ROTARYB -- Input from Rotary B. 32KHZ_XTAL -- Input from 32-kHz crystal. 8KHZ_XTAL -- Input from 8-kHz (divided from 32-kHz crystal). 4KHZ_XTAL -- Input from 4-kHz (divided from 32-kHz crystal). 1KHZ_XTAL -- Input from 1-kHz (divided from 32-kHz crystal). TICK_ALWAYS -- Always tick. 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 23.4.12 Timer 2 Runing Count Register (HW_TIMROT_RUNNING_COUNT2) The Timer 2 Running Count Register contains the timer running counter values for Timer 2. Address: 8006_8000h base + B0h offset = 8006_80B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUNNING_COUNT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_RUNNING_COUNT2 field descriptions Field RUNNING_ COUNT Description This bit field shows the current state of the running count as it decrements. 23.4.13 Timer 2 Fixed Count Register (HW_TIMROT_FIXED_COUNT2) The Timer 2 Fixed Count Register contains the fixed timer counter values for Timer 2. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1639 Programmable Registers HW_TIMROT_FIXED_COUNTn_WR(2, 0x0000f0dd); // Set up timer fixed count Address: 8006_8000h base + C0h offset = 8006_80C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIXED_COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_FIXED_COUNT2 field descriptions Field Description FIXED_COUNT Software loads the fixed count bit field with the value to down count. If the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. If the update bit is set to one, then the new value is also copied into the running count, immediately. If both the reload and update bits are set to zero, then the new value is never picked up by the running count. 23.4.14 Timer 2 Match Count Register (HW_TIMROT_MATCH_COUNT2) The Timer 2 Match Count Register contains the match timer counter values for Timer 2. EXAMPLE HW_TIMROT_MATCH_COUNTn_WR(2, 0x0000f0dd); // Set up timer match count Address: 8006_8000h base + D0h offset = 8006_80D0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH_COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_MATCH_COUNT2 field descriptions Field Description MATCH_COUNT Software compares the match count bit field with the value to down count. If they equal to each other, interrupt is trigger. 23.4.15 Timer 3 Control and Status Register (HW_TIMROT_TIMCTRL3) The Timer 3 Control and Status Register specifies timer control parameters, as well as interrupt status and the enable for Timer 3. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1640 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) HW_TIMROT_TIMCTRL3: 0x0e0 HW_TIMROT_TIMCTRL3_SET: 0x0e4 HW_TIMROT_TIMCTRL3_CLR: 0x0e8 HW_TIMROT_TIMCTRL3_TOG: 0x0eC EXAMPLE HW_TIMROT_TIMCTRLn_WR(3, 0x00000008); // Set up control fields for timer3 Address: 8006_8000h base + E0h offset = 8006_80E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD2 R TEST_SIGNAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POLARITY UPDATE RELOAD 0 0 0 0 RSRVD1 IRQ IRQ_EN R 0 0 DUTY_VALID Bit 0 MATCH_MODE Reset DUTY_CYCLE W PRESCALE SELECT W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1641 Programmable Registers HW_TIMROT_TIMCTRL3 field descriptions Field 31-20 RSRVD2 19-16 TEST_SIGNAL 15 IRQ Description Always write zeroes to this bit field. Selects the source of the signal to be measured in duty cycle mode. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF NEVER_TICK -- Never tick. Freeze the count. PWM0 -- Input from PWM0. PWM1 -- Input from PWM1. PWM2 -- Input from PWM2. PWM3 -- Input from PWM3. PWM4 -- Input from PWM4. PWM5 -- Input from PWM5. PWM6 -- Input from PWM6. PWM7 -- Input from PWM7. ROTARYA -- Input from Rotary A. ROTARYB -- Input from Rotary B. 32KHZ_XTAL -- Input from 32-kHz crystal. 8KHZ_XTAL -- Input from 8-kHz (divided from 32-kHz crystal). 4KHZ_XTAL -- Input from 4-kHz (divided from 32-kHz crystal). 1KHZ_XTAL -- Input from 1-kHz (divided from 32-kHz crystal). TICK_ALWAYS -- Always tick. This bit is set to one when Timer 3 decrements to zero. Write a zero to clear it or use Clear SCT mode. 14 IRQ_EN Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter mode. 13-12 RSRVD1 Always write zeroes to this bit field. 11 Set this bit to one to enable timer match mode MATCH_MODE 10 DUTY_VALID This bit is set and cleared by the hardware. It is set only when in duty cycle measuring mode and the HW_TIMROT_TIMCOUNT3 has valid duty cycle data to be read. This register will be cleared if not in duty cycle mode or on writes to this register. In the case that it is written while in duty cycle mode, this bit will clear but will again be set at the appropriate time for reading the count register. 9 DUTY_CYCLE Set this bit to one to cause the timer to operate in duty cycle measuring mode. 8 POLARITY Set this bit to one to invert the input to the edge detector. 0: Positive edge detection. 1: Invert to negative edge detection. 7 UPDATE Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count register value is written. 6 RELOAD Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of zero. When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register so that writting a non-zero value will start the timer. 5-4 PRESCALE Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency. 0x0 DIV_BY_1 -- PreScale: Divide the APBX clock by 1. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1642 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) HW_TIMROT_TIMCTRL3 field descriptions (continued) Field Description DIV_BY_2 -- PreScale: Divide the APBX clock by 2. DIV_BY_4 -- PreScale: Divide the APBX clock by 4. DIV_BY_8 -- PreScale: Divide the APBX clock by 8. 0x1 0x2 0x3 SELECT Selects the source for the timer tick that decrements the free running counter. Note: programming an undefined value will result in "always tick" behavior. In duty cycle mode it increments the counter used to calculate the high and low cycle counts. NEVER_TICK -- Never tick. Freeze the count. PWM0 -- Input from PWM0. PWM1 -- Input from PWM1. PWM2 -- Input from PWM2. PWM3 -- Input from PWM3. PWM4 -- Input from PWM4. PWM5 -- Input from PWM5. PWM6 -- Input from PWM6. PWM7 -- Input from PWM7. ROTARYA -- Input from Rotary A. ROTARYB -- Input from Rotary B. 32KHZ_XTAL -- Input from 32-kHz crystal. 8KHZ_XTAL -- Input from 8-kHz (divided from 32-kHz crystal). 4KHZ_XTAL -- Input from 4-kHz (divided from 32-kHz crystal). 1KHZ_XTAL -- Input from 1-kHz (divided from 32-kHz crystal). TICK_ALWAYS -- Always tick. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 23.4.16 Timer 3 Running Count Register (HW_TIMROT_RUNNING_COUNT3) The Timer 3 Running Count Register contains the timer runningcounter values for Timer 3. NOTE: This timer can be put in a special duty cycle mode that will measure the duty cycle of an input test signal. The definitions of the fields change depending whether the timer is in normal or duty cycle mode. Address: 8006_8000h base + F0h offset = 8006_80F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 LOW_RUNNING_COUNT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1643 Programmable Registers HW_TIMROT_RUNNING_COUNT3 field descriptions Field Description LOW_ RUNNING_ COUNT In duty cycle mode, this bit field is loaded from the running counter when it has just finished measuring the low portion of the duty cycle. In normal timer mode, it shows the running count as a read-only value. 23.4.17 Timer 3 Count Register (HW_TIMROT_FIXED_COUNT3) The Timer 3 fixed Count Register contains the timer fixed counter values for Timer 3. NOTE: This timer can be put in a special duty cycle mode that will measure the duty cycle of an input test signal. The definitions of the fields change depending whether the timer is in normal or duty cycle mode. EXAMPLE HW_TIMROT_FIXED_COUNTn_WR(3, 0x0000f0dd); // Set up timer fixed count Address: 8006_8000h base + 100h offset = 8006_8100h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIGH_FIXED_COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_FIXED_COUNT3 field descriptions Field HIGH_FIXED_ COUNT Description Software loads the fixed count bit field with the value to down count. If the reload bit is set to one, then the new value will be loaded into the running count the next time it reaches zero. If the update bit is set to one, then the new value is also copied into the running count, immediately. If both the reload and update bits are set to zero, then the new value is never picked up by the running count. In duty cycle mode, this bit field is loaded from the running counter when it has finished measuring the high portion of the duty cycle. 23.4.18 Timer 3 Match Count Register (HW_TIMROT_MATCH_COUNT3) The Timer 3 Match Count Register contains the match timer counter values for Timer 3. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1644 Freescale Semiconductor, Inc. Chapter 23 Timers and Rotary Decoder (TIMROT) HW_TIMROT_MATCH_COUNTn_WR(0, 0x0000f0dd); // Set up timer match count Address: 8006_8000h base + 110h offset = 8006_8110h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH_COUNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_MATCH_COUNT3 field descriptions Field Description MATCH_COUNT Software compares the match count bit field with the value to down count. If they equal to each other, interrupt is trigger. 23.4.19 TIMROT Version Register (HW_TIMROT_VERSION) This register always returns a known read value for debug purposes it indicates the version of the block. EXAMPLE if (HW_TIMROT_VERSION.B.MAJOR != 1) Error(); Address: 8006_8000h base + 120h offset = 8006_8120h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_TIMROT_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1645 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1646 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) 24.1 Debug UART Overview The Debug UART performs: * Serial-to-parallel conversion on data received from a peripheral device * Parallel-to-serial conversion on data transmitted to the peripheral device The CPU reads and writes data and control/status information through the APBX interface. The transmit and receive paths are buffered with internal FIFO memories, enabling up to 32 bytes to be stored independently in both transmit and receive modes. The Debug UART includes a programmable baud rate generator that creates a transmit and receive internal clock from the 24-MHz UART internal reference clock input UARTCLK. XCLK is not tied to the UARTCLK in the i.MX28. It offers similar functionality to the industry-standard 16C550 UART device and supports baud rates of up to 115 Kb/s. Figure 24-1 shows a block diagram of the Debug UART. The Debug UART operation and baud rate values are controlled by the line control register (HW_UARTDBGLCR_H, HW_UARTDBGIBRD, and HW_UARTDBGFBRD). The Debug UART can generate a single combined interrupt, so output is asserted if any individual interrupt is asserted and unmasked. Interrupt sources include the receive (including timeout), transmit, modem status, and error conditions. If a framing, parity, or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately, and FIFO data is prevented from being overwritten. You can program the FIFOs to be one-byte deep, providing a conventional double-buffered UART interface. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1647 Debug UART Overview The modem status input signal Clear To Send (CTS) and output modem control line Request To Send (RTS) are supported. A programmable hardware flow control feature uses the nUARTCTS input and the nUARTRTS output to automatically control the serial data flow. Note Names for the external pins used by the Debug UART begin with "UART1". Pin names beginning with "UART2" are used by the Application UART. ARM Core SRAM AHB XCLK 24-MHz XTAL Osc. APBX APBX Master UART1RXD UART2RTS UART2CTS UART1TXD XCLK AHB-to-APBX Bridge UARTCLK Divide by n AHB Slave UART Programmable Registers and FIFOs RX FSM BAUDRATE TX FSM UART Figure 24-1. Debug UART Block Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1648 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) 24.2 Operation Control data is written to the Debug UART line control register. This register defines: * Transmission parameters * Word length * Buffer mode * Number of transmitted stop bits * Parity mode * Break generation * Baud rate divisor 24.2.1 Fractional Baud Rate Divider The baud rate divisor is calculated from the frequency of UARTCLK and the desired baud rate by using the following formula: divisor = (UARTCLK * 4) / baud rate, rounded to the nearest integer The divisor must be between 0x00000040 and 0x003FFFC0, inclusive. Program the lowest 6 bits of the divisor into BAUD_DIVFRAC, and the next 16 bits of the divisor into BAUD_DIVINT. In the debug UART, HW_UARTDBGLCR_H, HW_UARTDBGIBRD, and HW_UARTDBGFBRD form a single 30-bit wide register (UARTLCR) that is updated on a single write strobe generated by an HW_UARTDBGLCR_H write. So, in order to internally update the contents of HW_UARTDBGIBRD or HW_UARTDBGFBRD, a write to HW_UARTDBGLCR_H must always be performed at the end. 24.2.2 UART Character Frame Figure 24-2 illustrates the UART character frame. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1649 Operation UARTTXD lsb 1 0 msb 1-2 stop bits 5-8 data bits n Start Parity bit if enabled Figure 24-2. Debug UART Character Frame 24.2.3 Data Transmission or Reception Data received or transmitted is stored in two 32-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the Debug UART is enabled, it causes a data frame to start transmitting with the parameters indicated in UARTLCR_H. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY signal goes HIGH as soon as data is written to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted HIGH while data is being transmitted. BUSY is negated only when the transmit FIFO is empty and the last character has been transmitted from the shift register, including the stop bits. BUSY can be asserted HIGH even though the Debug UART might no longer be enabled. For each sample of data, three readings are taken and the majority value is kept. In the following paragraphs, the middle sampling point is defined and one sample is taken either side of it. * When the receiver is idle (UARTRXD continuously 1, in the marking state) and a LOW is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by Baud16, begins running and data is sampled on the eighth cycle of that counter in normal UART mode to allow for the shorter logic 0 pulses (half way through a bit period). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1650 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) * The start bit is valid if UARTRXD is still LOW on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked, if parity mode was enabled. * Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word (see Table 24-1). 24.2.4 Error Bits Three error bits are stored in bits [10:8] of the receive FIFO and are associated with a particular character. An additional error indicating an overrun error is stored in bit 11 of the receive FIFO. 24.2.5 Overrun Bit The overrun bit is not associated with the character in the receive FIFO. The overrun error is set when the FIFO is full, and the next character is completely received in the shift register. The data in the shift register is overwritten, but it is not written into the FIFO. When an empty location is available in the receive FIFO, and another character is received, the state of the overrun bit is copied into the receive FIFO along with the received character. The overrun state is then cleared. Table 24-1 shows the bit functions of the receive FIFO. Table 24-1. Receive FIFO Bit Functions FIFO bit Function 11 Overrun indicator 10 Break error 9 Parity error 8 Framing error 7:0 Received data i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1651 Programmable Registers 24.2.6 Disabling the FIFOs FIFOs can be disabled. In this case, the transmit and receive sides of the UART have onebyte holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word has been received and the previous one was not yet read. In this implementation, the FIFOs are not physically disabled, but the flags are manipulated to give the illusion of a one-byte register. 24.3 Programmable Registers UARTDBG Hardware Register Format Summary HW_UARTDBG memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8007_4000 UART Data Register (HW_UARTDBG_DR) 32 R/W 0000_0000h 24.3.1/1653 8007_4004 UART Receive Status Register (Read) / Error Clear Register (Write) (HW_UARTDBG_ECR) 32 R/W 0000_0000h 24.3.2/1654 8007_4018 UART Flag Register (HW_UARTDBG_FR) 32 R 0000_0090h 24.3.3/1655 8007_4020 UART IrDA Low-Power Counter Register (HW_UARTDBG_ILPR) 32 R/W 0000_0000h 24.3.4/1656 8007_4024 UART Integer Baud Rate Divisor Register (HW_UARTDBG_IBRD) 32 R/W 0000_0000h 24.3.5/1657 8007_4028 UART Fractional Baud Rate Divisor Register (HW_UARTDBG_FBRD) 32 R/W 0000_0000h 24.3.6/1657 8007_402C UART Line Control Register, HIGH Byte (HW_UARTDBG_H) 32 R/W 0000_0000h 24.3.7/1658 8007_4030 UART Control Register (HW_UARTDBG_CR) 32 R/W 0000_0300h 24.3.8/1659 8007_4034 UART Interrupt FIFO Level Select Register (HW_UARTDBG_IFLS) 32 R/W 0000_0012h 24.3.9/1661 8007_4038 UART Interrupt Mask Set/Clear Register (HW_UARTDBG_IMSC) 32 R/W 0000_0000h 24.3.10/ 1662 8007_403C UART Raw Interrupt Status Register (HW_UARTDBG_RIS) 32 R 0000_0000h 24.3.11/ 1664 8007_4040 UART Masked Interrupt Status Register (HW_UARTDBG_MIS) 32 R 0000_0000h 24.3.12/ 1666 8007_4044 UART Interrupt Clear Register (HW_UARTDBG_ICR) 32 R/W 0000_0000h 24.3.13/ 1668 8007_4048 UART DMA Control Register (HW_UARTDBG_DMACR) 32 R/W 0000_0000h 24.3.14/ 1669 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1652 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) 24.3.1 UART Data Register (HW_UARTDBG_DR) Debug Uart Data Register. For words to be transmitted: 1) If the FIFOs are enabled, data written to this location is pushed onto the transmit FIFO 2) If the FIFOs are not enabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the PrimeCell UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: 1) If the FIFOs are enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) are pushed onto the 12-bit wide receive FIFO 2) If the FIFOs are not enabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from the DR register along with the corresponding status information. The status information can also be read by a read of the RSR_ECR register. Address: 8007_4000h base + 0h offset = 8007_4000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OE BE PE FE 0 0 0 0 0 0 0 0 RESERVED R DATA W Reset 0 0 0 0 0 0 0 0 HW_UARTDBG_DR field descriptions Field 31-16 UNAVAILABLE 15-12 RESERVED Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. This field is reserved. Reserved. 11 OE Overrun Error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. 10 BE Break Error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1653 Programmable Registers HW_UARTDBG_DR field descriptions (continued) Field Description 9 PE Parity Error. When this bit is set to 1, it indicates that the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the LCR_H register. In FIFO mode, this error is associated with the character at the top of the FIFO. 8 FE Framing Error. When this bit is set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. DATA Receive (read) data character. Transmit (write) data character. 24.3.2 UART Receive Status Register (Read) / Error Clear Register (Write) (HW_UARTDBG_ECR) The RSR_ECR register is the receive status register/error clear register. Receive status can also be read from RSR_ECR. If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from DR prior to reading RSR_ECR. The status information for overrun is set immediately when an overrun condition occurs. A write to RSR_ECR clears the framing, parity, break, and overrun errors. Address: 8007_4000h base + 4h offset = 8007_4004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OE BE PE FE 0 0 0 0 UNAVAILABLE R EC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_UARTDBG_ECR field descriptions Field 31-8 UNAVAILABLE Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. 7-4 EC Error Clear. Any write to this bitfield clears the framing, parity, break, and overrun errors. The value is unpredictable when read. 3 OE Overrun Error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by any write to RSR_ECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1654 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) HW_UARTDBG_ECR field descriptions (continued) Field Description 2 BE Break Error. 1 PE Parity Error. 0 FE Framing Error. 24.3.3 UART Flag Register (HW_UARTDBG_FR) The FR register is the flag register. Address: 8007_4000h base + 18h offset = 8007_4018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSR CTS 0 0 RESERVED R RI TXFE RXFF TXFF RXFE BUSY DCD W Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 HW_UARTDBG_FR field descriptions Field 31-16 UNAVAILABLE 15-9 RESERVED Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. This field is reserved. Reserved, do not modify, read as zero. 8 RI Ring Indicator. This bit is the complement of the UART ring indicator (nUARTRI) modem status input. That is, the bit is 1 when the modem status input is 0. 7 TXFE Transmit FIFO Empty. The meaning of this bit depends on the state of the FEN bit in the LCR_H register. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. 6 RXFF Receive FIFO Full. 5 TXFF Transmit FIFO Full. 4 RXFE Receive FIFO Empty. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1655 Programmable Registers HW_UARTDBG_FR field descriptions (continued) Field Description 3 BUSY UART Busy. 2 DCD Data Carrier Detect. 1 DSR Data Set Ready. 0 CTS Clear To Send. 24.3.4 UART IrDA Low-Power Counter Register (HW_UARTDBG_ILPR) The ILPR register is the IrDA Low-Power Counter Register. This is an 8-bit read/write register which stores a low-power counter divisor value used to divde down the UARTCLK to generate the IrLPBaud16 signal. Address: 8007_4000h base + 20h offset = 8007_4020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 UNAVAILABLE R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 0 0 0 ILPDVSR W Reset 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_UARTDBG_ILPR field descriptions Field 31-8 UNAVAILABLE ILPDVSR Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. IrDA Low Power Divisor [7:0]. 8-bit low-power divisor value. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1656 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) 24.3.5 UART Integer Baud Rate Divisor Register (HW_UARTDBG_IBRD) The IBRD register is the integer part of the baud rate divisor value. Address: 8007_4000h base + 24h offset = 8007_4024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 UNAVAILABLE R 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 BAUD_DIVINT W Reset 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_UARTDBG_IBRD field descriptions Field Description 31-16 UNAVAILABLE The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. BAUD_DIVINT Baud Rate Integer [15:0]. The integer baud rate divisor. 24.3.6 UART Fractional Baud Rate Divisor Register (HW_UARTDBG_FBRD) The FBRD register is the fractional part of the baud rate divisor value. Address: 8007_4000h base + 28h offset = 8007_4028h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 UNAVAILABLE R RESERVED BAUD_DIVFRAC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_UARTDBG_FBRD field descriptions Field 31-8 UNAVAILABLE Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1657 Programmable Registers HW_UARTDBG_FBRD field descriptions (continued) Field Description 7-6 RESERVED This field is reserved. Not documented. BAUD_DIVFRAC Baud Rate Fraction [5:0]. The fractional baud rate divisor. 24.3.7 UART Line Control Register, HIGH Byte (HW_UARTDBG_H) The LCR_H is the Line Control Register. Address: 8007_4000h base + 2Ch offset = 8007_402Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FEN STP2 EPS PEN BRK 0 0 0 0 0 RESERVED R SPS W Reset 0 0 0 0 0 0 0 0 0 WLEN 0 0 HW_UARTDBG_H field descriptions Field 31-16 UNAVAILABLE 15-8 RESERVED 7 SPS Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. This field is reserved. Reserved, do not modify, read as zero. Stick Parity Select. When bits 1, 2, and 7 of the LCR_H register are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this bit is cleared stick parity is disabled. 6-5 WLEN Word length [1:0]. The select bits indicate the number of data bits transmitted or received in a frame as follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits. 4 FEN Enable FIFOs. If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, the FIFOs are disabled (character mode); that is, the FIFOs become 1-byte-deep holding registers. 3 STP2 Two Stop Bits Select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. 2 EPS Even Parity Select. If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed which checks for an odd number of 1s. This bit has no effect when parity is disabled by Parity Enable (PEN, bit 1) being cleared to 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1658 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) HW_UARTDBG_H field descriptions (continued) Field Description 1 PEN Parity Enable. If this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no parity bit added to the data frame. 0 BRK Send Break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. 24.3.8 UART Control Register (HW_UARTDBG_CR) The CR is the Control Register. Address: 8007_4000h base + 30h offset = 8007_4030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UARTEN Bit 0 SIREN Reset SIRLP W 0 0 0 RESERVED CTSEN RTSEN OUT2 OUT1 R RTS 0 0 0 0 0 DTR RXE TXE LBE 0 1 1 0 W Reset 0 0 0 0 HW_UARTDBG_CR field descriptions Field 31-16 UNAVAILABLE Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. 15 CTSEN CTS Hardware Flow Control Enable. 14 RTSEN RTS Hardware Flow Control Enable. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1659 Programmable Registers HW_UARTDBG_CR field descriptions (continued) Field Description 13 OUT2 This bit is the complement of the UART Out2 (nUARTOut2) modem status output. Not Implemented. 12 OUT1 This bit is the complement of the UART Out1 (nUARTOut1) modem status output. Not Implemented. 11 RTS Request To Send. 10 DTR Data Transmit Ready. Not Implemented. 9 RXE Receive Enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for the UART signals. When the UART is disabled in the middle of reception, it completes the current character before stopping. 8 TXE Transmit Enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for the UART signals. When the UART is disabled in the middle of transmission, it completes the current character before stopping. 7 LBE Loop Back Enable. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, the UARTTXD path is fed through to the UARTRXD path. When this bit is set, the modem outputs are also fed through to the modem inputs. 6-3 RESERVED This field is reserved. Reserved, do not modify, read as zero. 2 SIRLP IrDA SIR low-power mode. Not Supported. 1 SIREN SIR Enable. Not Supported. 0 UARTEN UART Enable. If this bit is set to 1, the UART is enabled. Data transmission and reception occurs for the UART signals. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1660 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) 24.3.9 UART Interrupt FIFO Level Select Register (HW_UARTDBG_IFLS) The IFLS register is the Interrupt FIFO Level Select Register. You can use the IFLS register to define the FIFO level at which the UARTTXINTR and UARTRXINTR are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the design is such that the interrupts are generated when the fill level progresses through the trigger level. The bits are reset so that the trigger level is when the FIFOs are at the half-way mark. Address: 8007_4000h base + 34h offset = 8007_4034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 UNAVAILABLE R 12 11 10 9 8 7 6 RESERVED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 RXIFLSE TXIFLSE L L W Reset 5 0 0 0 0 1 0 0 1 0 HW_UARTDBG_IFLS field descriptions Field 31-16 UNAVAILABLE 15-6 RESERVED Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. This field is reserved. Reserved, do not modify, read as zero. 5-3 RXIFLSEL Receive Interrupt FIFO Level Select. The trigger points for the receive interrupt are as follows: TXIFLSEL Transmit Interrupt FIFO Level Select. The trigger points for the transmit interrupt are as follows: 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 ONE_EIGHT -- Trigger when FIFO becomes at least one-eight full. ONE_QUARTER -- Trigger when FIFO becomes at least one-quarter full. ONE_HALF -- Trigger when FIFO becomes at least one-half full. THREE_QUARTERS -- Trigger when FIFO becomes at least three-quarters full. SEVEN_EIGHTHS -- Trigger when FIFO becomes at least seven-eights full. INVALID5 -- Reserved. INVALID6 -- Reserved. INVALID7 -- Reserved. ONE_EIGHT -- Trigger when FIFO becomes equal or less than one-eight full. ONE_QUARTER -- Trigger when FIFO becomes equal or less than one-quarter full. ONE_HALF -- Trigger when FIFO becomes equal or less than one-half full. THREE_QUARTERS -- Trigger when FIFO becomes equal or less than three-quarters full. SEVEN_EIGHTHS -- Trigger when FIFO becomes equal or less than seven-eights full. INVALID5 -- Reserved. INVALID6 -- Reserved. INVALID7 -- Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1661 Programmable Registers 24.3.10 UART Interrupt Mask Set/Clear Register (HW_UARTDBG_IMSC) The IMSC register is the Interrupt Mask Set/Clear Register. On a read, this register gives the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit, it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask. Special Note: Here Mask means Enable.Mask=1 means that bit interrupt is enabled Address: 8007_4000h base + 38h offset = 8007_4038h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTSMIM RIMIM Bit 0 DCDMIM Reset DSRMIM W 0 0 0 0 RESERVED R OEIM BEIM PEIM FEIM RTIM TXIM RXIM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_UARTDBG_IMSC field descriptions Field 31-16 UNAVAILABLE 15-11 RESERVED Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. This field is reserved. Reserved, do not modify, read as zero. 10 OEIM Overrun Error Interrupt Mask. On a read, the current mask for the OEIM interrupt is returned. On a write of 1, the mask of the OEIM interrupt is set. A write of 0 clears the mask. 9 BEIM Break Error Interrupt Mask. 8 PEIM Parity Error Interrupt Mask. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1662 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) HW_UARTDBG_IMSC field descriptions (continued) Field Description 7 FEIM Framing Error Interrupt Mask. 6 RTIM Receive Timeout Interrupt Mask. 5 TXIM Transmit Interrupt Mask. 4 RXIM Receive Interrupt Mask. 3 DSRMIM nUARTDSR Modem Interrupt Mask. 2 DCDMIM nUARTDCD Modem Interrupt Mask. 1 CTSMIM nUARTCTS Modem Interrupt Mask. 0 RIMIM nUARTRI Modem Interrupt Mask. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1663 Programmable Registers 24.3.11 UART Raw Interrupt Status Register (HW_UARTDBG_RIS) The RIS register is the Raw Interrupt Status Register. It is a read-only register. On a read this register gives the current raw status value of the corresponding interrupt. A write has no effect. All the bits, except for the modem status interrupt bits (bits 3 to 0), are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. Address: 8007_4000h base + 3Ch offset = 8007_403Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PERIS FERIS RTRIS TXRIS RXRIS DSRRMIS DCDRMIS CTSRMIS RIRMIS Bit 0 BERIS Reset OERIS W 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED R W Reset 0 0 0 HW_UARTDBG_RIS field descriptions Field 31-16 UNAVAILABLE 15-11 RESERVED 10 OERIS Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. This field is reserved. Reserved, read as zero, do not modify. Overrun Error Interrupt Status. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1664 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) HW_UARTDBG_RIS field descriptions (continued) Field Description 9 BERIS Break Error Interrupt Status. 8 PERIS Parity Error Interrupt Status. 7 FERIS Framing Error Interrupt Status. 6 RTRIS Receive Timeout Interrupt Status. 5 TXRIS Transmit Interrupt Status. 4 RXRIS Receive Interrupt Status. 3 DSRRMIS nUARTDSR Modem Interrupt Status. 2 DCDRMIS nUARTDCD Modem Interrupt Status. 1 CTSRMIS nUARTCTS Modem Interrupt Status. 0 RIRMIS nUARTRI Modem Interrupt Status. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1665 Programmable Registers 24.3.12 UART Masked Interrupt Status Register (HW_UARTDBG_MIS) The MIS register is the Masked Interrupt Status Register. It is a read-only register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. All the bits except for the modem status interrupt bits (bits 3 to 0) are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. Address: 8007_4000h base + 40h offset = 8007_4040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEMIS FEMIS RTMIS TXMIS RXMIS DSRMMIS DCDMMIS CTSMMIS RIMMIS Bit 0 BEMIS Reset OEMIS W 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED R W Reset 0 0 0 HW_UARTDBG_MIS field descriptions Field 31-16 UNAVAILABLE Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. 15-11 RESERVED This field is reserved. Reserved, read as zero, do not modify. 10 OEMIS Overrun Error Masked Interrupt Status. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1666 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) HW_UARTDBG_MIS field descriptions (continued) Field Description 9 BEMIS Break Error Masked Interrupt Status. 8 PEMIS Parity Error Masked Interrupt Status. 7 FEMIS Framing Error Masked Interrupt Status. 6 RTMIS Receive Timeout Masked Interrupt Status. 5 TXMIS Transmit Masked Interrupt Status. 4 RXMIS Receive Masked Interrupt Status. 3 DSRMMIS nUARTDSR Modem Masked Interrupt Status. 2 DCDMMIS nUARTDCD Modem Masked Interrupt Status. 1 CTSMMIS nUARTCTS Modem Masked Interrupt Status. 0 RIMMIS nUARTRI Modem Masked Interrupt Status. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1667 Programmable Registers 24.3.13 UART Interrupt Clear Register (HW_UARTDBG_ICR) The ICR register is the Interrupt Clear Register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. Address: 8007_4000h base + 44h offset = 8007_4044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEIC FEIC RTIC TXIC RXIC DSRMIC DCDMIC CTSMIC RIMIC Bit 0 BEIC Reset OEIC W 0 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED R W Reset 0 0 0 HW_UARTDBG_ICR field descriptions Field 31-16 UNAVAILABLE 15-11 RESERVED Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. This field is reserved. Reserved, read as zero, do not modify. 10 OEIC Overrun Error Interrupt Clear. 9 BEIC Break Error Interrupt Clear. 8 PEIC Parity Error Interrupt Clear. 7 FEIC Framing Error Interrupt Clear. 6 RTIC Receive Timeout Interrupt Clear. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1668 Freescale Semiconductor, Inc. Chapter 24 Debug UART (DUART) HW_UARTDBG_ICR field descriptions (continued) Field Description 5 TXIC Transmit Interrupt Clear. 4 RXIC Receive Interrupt Clear. 3 DSRMIC nUARTDSR Modem Interrupt Clear. 2 DCDMIC nUARTDCD Modem Interrupt Clear. 1 CTSMIC nUARTCTS Modem Interrupt Clear. 0 RIMIC nUARTRI Modem Interrupt Clear. 24.3.14 UART DMA Control Register (HW_UARTDBG_DMACR) This register is reserved in this system. Address: 8007_4000h base + 48h offset = 8007_4048h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNAVAILABLE R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXDMAE Bit 0 TXDMAE Reset DMAONERR W 0 0 0 0 0 0 0 0 0 RESERVED R W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1669 Programmable Registers HW_UARTDBG_DMACR field descriptions Field 31-16 UNAVAILABLE Description The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are always unavailable. 15-3 RESERVED This field is reserved. Reserved. 2 DMAONERR Reserved. 1 TXDMAE Reserved. 0 RXDMAE Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1670 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) 25.1 FlexCAN Introduction The FlexCAN module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification. A general block diagram is shown in Figure 25-1, which describes the main sub-blocks implemented in the FlexCAN module, including two embedded memories, one for storing Message Buffers (MB) and another one for storing Rx Individual Mask Registers. The functions of the sub-modules are described in subsequent sections. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1671 Overview MB63 RXIMR63 RXIMR62 Message Buffer Management CAN MB62 CAN Tx ID Mask Storage Message Buffer Storage 256byte RAM 1056byte RAM CAN Rx RXIMR1 RXIMR0 MB1 MB0 Bus Interface Unit APB Bus Interface Clocks, Address & Data buses, Interrupt and Test Signals Figure 25-1. FlexCAN Block Diagram 25.2 Overview The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames. The Message Buffers are stored in an embedded RAM dedicated to the FlexCAN module. The CAN Protocol Interface (CPI) sub-module manages the serial communication on the CAN bus, requesting RAM access for receiving and transmitting message frames, validating received messages and performing error handling. The Message Buffer Management (MBM) sub-module handles Message Buffer selection for reception and transmission, taking care of arbitration and ID matching algorithms. The Bus Interface i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1672 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) Unit (BIU) sub-module controls the access to and from the internal interface bus, in order to establish connection to the CPU and other blocks. Clocks, address and data buses, interrupt outputs and test signals are accessed through the Bus Interface Unit, which is compliant to APB Bus Specification. 25.2.1 Features The FlexCAN module includes the following distinctive Features: * Full Implementation of the CAN protocol specification, Version 2.0B * Standard data and remote frames * Extended data and remote frames * Zero to eight bytes data length * Programmable bit rate up to 1 Mb/sec * Content-related addressing * 64 Message Buffers of zero to eight bytes data length * Each MB configurable as Rx or Tx, all supporting standard and extended messages * Individual Rx Mask Registers per Message Buffer * Includes either 1056 bytes (64 MBs) of RAM used for MB storage * Includes either 256 bytes (64 MBs) of RAM used for individual Rx Mask Registers * Full featured Rx FIFO with storage capacity for six frames and internal pointer handling * Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 8 extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability * Selectable backward compatibility with previous FlexCAN version * CAN Protocol Interface with clock only from crystal oscillator * Unused MB and Rx Mask Register space can be used as general purpose RAM space * Listen only mode capability * Programmable loop-back mode supporting self-test operation * Programmable transmission priority scheme: lowest ID, lowest buffer number or highest priority i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1673 Overview * Time Stamp based on 16-bit free-running timer * Global network time, synchronized by a specific message * Maskable interrupts * Independent of the transmission medium (an external transceiver is assumed) * Short latency time due to an arbitration scheme for high-priority messages * Low power modes, with programmable wake up on bus activity * Configurable Glitch filter width to filter the noise on CAN bus when waking up 25.2.2 Modes of Operation The FlexCAN module has four functional modes: Normal Mode, Freeze Mode, ListenOnly Mode and Loop-Back Mode. There are also two low power modes: Disable Mode, Stop Mode. * Normal Mode : In Normal Mode, the module operates receiving and/or transmitting message frames, errors are handled normally and all the CAN Protocol functions are enabled. * Freeze Mode: It is enabled when the FRZ bit in the MCR Register is asserted. If enabled, Freeze Mode is entered when the HALT bit in MCR is set or when Debug Mode is requested. In this mode, no transmission or reception of frames is done and synchronicity to the CAN bus is lost. See Freeze Mode for more information. * Listen-Only Mode: The module enters this mode when the LOM bit in the Control Register is asserted. In this mode, transmission is disabled, all error counters are frozen and the module operates in a CAN Error Passive mode. Only messages acknowledged by another CAN station will be received. If FlexCAN detects a message that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the message. * Loop-Back Mode: The module enters this mode when the LPB bit in the Control Register is asserted. In this mode, FlexCAN performs an internal loop back that can be used for self test operation. The bit stream output of the transmitter is internally fed back to the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1674 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive state (logic '1'). FlexCAN behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated. * Module Disable Mode: This low power mode is entered when the MDIS bit in the MCR Register is asserted. When disabled, the module shuts down the clocks to the CAN Protocol Interface and Message Buffer Management sub-modules. Exit from this mode is done by negating the MDIS bit in the MCR Register. See Module Disable Mode for more information. * Stop Mode: This low power mode is entered when Stop Mode is requested at ARM chip level.When in Stop Mode, the module puts itself in an inactive state and then informs the ARM that the clocks can be shut down globally. Exit from this mode happens when the Stop Mode request is removed or when activity is detected on the CAN bus and the Self Wake Up mechanism is enabled. See Stop Mode for more information. 25.3 Message Buffer Structure The Message Buffer structure used by the FlexCAN module is represented in Table 25-1. Both Extended and Standard Frames (29-bit Identifier and 11-bit Identifier, respectively) used in the CAN specification (Version 2.0 Part B) are represented. Table 25-1. Message Buffer Structure 31 $0 $4 28 27 24 CODE PRIO 22 21 20 19 S R ID R T E R R 16 15 8 LENGTH 7 0 TIME STAMP ID (Standard/Extended) ID (Extended) $8 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 $ C Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 = Unimplemented or Reserved CODE--Message Buffer Code i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1675 Message Buffer Structure This 4-bit field can be accessed (read or write) by the CPU and by the Flexcan module itself, as part of the message buffer matching and arbitration process. The encoding is shown in Table 25-2 and Table 25-3. See Overview for additional information. Table 25-2. Message Buffer Code for Rx buffers Rx Code BEFORE Rx Code AFTER Description Rx New Frame 0000 INACTIVE: MB is not active. 0100 EMPTY: MB is active and empty. 0010 0110 0XY1a a Comment Rx New Frame -- MB does not participate in the matching process. 0010 MB participates in the matching process. When a frame is received successfully, the code is automatically updated to FULL. 0010 The act of reading the C/S word followed by unlocking the MB does not make the code return to EMPTY. It remains FULL. If a new frame is written to the MB after the C/S word was read and the MB was unlocked, the code still remains FULL. 0110 If the MB is FULL and a new frame is overwritten to this MB before the CPU had time to read it, the code is automatically updated to OVERRUN. Refer to Matching Process for details about overrun behavior. 0010 If the code indicates OVERRUN but the CPU reads the C/S word and then unlocks the MB, when a new frame is written to the MB the code returns to FULL. 0110 If the code already indicates OVERRUN, and yet another new frame must be written, the MB will be overwritten again, and the code will remain OVERRUN. Refer to Matching Process for details about overrun behavior. 0010 An EMPTY buffer was written with a new frame (XY was 01). 0110 A FULL/OVERRUN buffer was overwritten (XY was 11). FULL: MB is full. OVERRUN: a frame was overwritten into a full buffer. BUSY: Flexcan is updating the contents of the MB. The CPU must not access the MB. For Tx MBs (see Table 3), the BUSY bit should be ignored upon read, except when the AEN bit is set in the MCR register. Table 25-3. Message Buffer Code for Tx buffers Code after successful Description transmission RTR Initial Tx code X 1000 -- INACTIVE: MB does not participate in the arbitration process. X 1001 -- ABORT: MB was configured as Tx and CPU aborted the transmission. This code is only valid when AEN bit in MCR is asserted. MB does not participate in the arbitration process. 0 1100 1000 Transmit data frame unconditionally once. After transmission, the MB automatically returns to the INACTIVE state. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1676 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) Table 25-3. Message Buffer Code for Tx buffers (continued) RTR Initial Tx code 1 1100 0 0 Code after successful Description transmission 1010 1110 0100 Transmit remote frame unconditionally once. After transmission, the MB automatically becomes an Rx MB with the same ID. 1010 Transmit a data frame whenever a remote request frame with the same ID is received. This MB participates simultaneously in both the matching and arbitration processes. The matching process compares the ID of the incoming remote request frame with the ID of the MB. If a match occurs this MB is allowed to participate in the current arbitration process and the Code field is automatically updated to '1110' to allow the MB to participate in future arbitration runs. When the frame is eventually transmitted successfully, the Code automatically returns to '1010' to restart the process again. 1010 This is an intermediate code that is automatically written to the MB by the MBM as a result of match to a remote request frame. The data frame will be transmitted unconditionally once and then the code will automatically return to '1010'. The CPU can also write this code with the same effect. SRR--Substitute Remote Request Fixed recessive bit, used only in extended format. It must be set to '1' by the user for transmission (Tx Buffers) and will be stored with the value received on the CAN bus for Rx receiving buffers. It can be received as either recessive or dominant. If FlexCAN receives this bit as dominant, then it is interpreted as arbitration loss. 1 = Recessive value is compulsory for transmission in Extended Format frames 0 = Dominant is not a valid value for transmission in Extended Format frames IDE--ID Extended Bit This bit identifies whether the frame format is standard or extended. 1 = Frame format is extended 0 = Frame format is standard RTR--Remote Transmission Request This bit is used for requesting transmissions of a data frame. If FlexCAN transmits this bit as '1' (recessive) and receives it as '0' (dominant), it is interpreted as arbitration loss. If this bit is transmitted as '0' (dominant), then if it is received as '1' (recessive), the FlexCAN module treats it as bit error. If the value received matches the value transmitted, it is considered as a successful bit transmission. 1 = Indicates the current MB has a Remote Frame to be transmitted 0 = Indicates the current MB has a Data Frame to be transmitted i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1677 Message Buffer Structure LENGTH--Length of Data in Bytes This 4-bit field is the length (in bytes) of the Rx or Tx data, which is located in offset $8 through $F of the MB space (see Table 25-1). In reception, this field is written by the FlexCAN module, copied from the DLC (Data Length Code) field of the received frame. In transmission, this field is written by the CPU and corresponds to the DLC field value of the frame to be transmitted. When RTR=1, the Frame to be transmitted is a Remote Frame and does not include the data field, regardless of the Length field. TIME STAMP--Free-Running Counter Time Stamp This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. PRIO--Local priority This 3-bit field is only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. See Arbitration Process. ID--Frame Identifier In Standard Frame format, only the eleven most significant bits (28 to 18) are used for frame identification in both receive and transmit cases. The 18 least significant bits are ignored. In Extended Frame format, all bits are used for frame identification in both receive and transmit cases. DATA--Data Field Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from the CAN bus. For Tx frames, the CPU prepares the data field to be transmitted within the frame. 25.3.1 Rx FIFO Structure When the FEN bit is set in the MCR, the memory area from $80 to $FF (which is normally occupied by MBs 0 to 7) is used by the reception FIFO engine. Table 25-4 shows the Rx FIFO data structure. The region $0-$C contains a MB structure which is the port through which the CPU reads data from the FIFO (the oldest frame received and not read yet). The region $10-$DF is reserved for internal use of the FIFO engine. The region $E0-$FF contains an 8-entry ID table that specifies filtering criteria for accepting frames into the FIFO. Table 25-5 shows the three different formats that the elements of the ID table can assume, depending on the IDAM field of the MCR. Note that all elements of the table must have the same format. See Rx FIFO for more information. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1678 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) Table 25-4. Rx FIFO Structure 31 28 27 24 22 21 20 19 S R ID R T E R R $0 $4 16 15 8 LENGTH 7 0 TIME STAMP ID (Standard/Extended) ID (Extended) $8 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 $ C Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 $1 0 to Reserved $ D F $ E 0 ID Table 0 $ E 4 ID Table 1 $ E 8 ID Table 2 $ E C ID Table 3 $F 0 ID Table 4 $F 4 ID Table 5 $F 8 ID Table 6 $F C ID Table 7 = Unimplemented or Reserved Table 25-5. ID Table 0 - 7 Fo rm 31 at A R E E X M T B R E E X M T 28 27 24 22 21 20 19 16 15 8 7 0 RXIDA (Standard = 29-19, Extended = 29-1) RXIDB_0 (Standard = 29-19, Extended = 29-16) R E E X M T RXIDB_1 (Standard = 13-3, Extended = 13-0) Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1679 Message Buffer Structure Table 25-5. ID Table 0 - 7 (continued) C RXIDC_0 RXIDC_1 RXIDC_2 RXIDC_3 (Std/Ext = 31-24) (Std/Ext = 23-16) (Std/Ext = 15-8) (Std/Ext = 7-0) = Unimplemented or Reserved REM -- Remote Frame This bit specifies if Remote Frames are accepted into the FIFO if they match the target ID. 1 = Remote Frames can be accepted and data frames are rejected 0 = Remote Frames are rejected and data frames can be accepted EXT -- Extended Frame Specifies whether extended or standard frames are accepted into the FIFO if they match the target ID. 1 = Extended frames can be accepted and standard frames are rejected 0 = Extended frames are rejected and standard frames can be accepted RXIDA -- Rx Frame Identifier (Format A) Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format, only the eleven most significant bits are used for frame identification. In the extended frame format, all bits are used. RXIDB_0, RXIDB_1 -- Rx Frame Identifier (Format B) Specifies an ID to be used as acceptance criteria for the FIFO. In the standard frame format, the eleven most significant bits (a full standard ID) are used for frame identification. In the extended frame format, all 14 bits of the field are compared to the 14 most significant bits of the received ID. RXIDC_0, RXIDC_1, RXIDC_2, RXIDC_3 -- Rx Frame Identifier (Format C) Specifies an ID to be used as acceptance criteria for the FIFO. In both standard and extended frame formats, all eight bits of the field are compared to the eight most significant bits of the received ID. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1680 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) 25.4 Functional Description 25.4.1 Overview The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and receiving CAN frames. The mailbox system is composed by a set of 64 Message Buffers (MB) that store configuration and control data, time stamp, message ID and data (see Message Buffer Structure). The memory corresponding to the first 8 MBs can be configured to support a FIFO reception scheme with a powerful ID filtering mechanism, capable of checking incoming frames against a table of IDs (up to 8 extended IDs or 16 standard IDs or 32 8-bit ID slices), each one with its own individual mask register. Simultaneous reception through FIFO and mailbox is supported. For mailbox reception, a matching algorithm makes it possible to store received frames only into MBs that have the same ID programmed on its ID field. A masking scheme makes it possible to match the ID programmed on the MB with a range of IDs on received CAN frames. For transmission, an arbitration algorithm decides the prioritization of MBs to be transmitted based on the message ID (optionally augmented by three local priority bits) or the MB ordering. Before proceeding with the functional description, an important concept must be explained. A Message Buffer is said to be active at a given time if it can participate in the matching and arbitration algorithms that are happening at that time. An Rx MB with a 0000 code is inactive (refer to Table 25-2). Similarly, a Tx MB with a 1000 or 1001 code is also inactive (refer to Table 25-3). An MB not programmed with 0000, 1000 or 1001 is temporarily deactivated (does not participate in the current arbitration or matching run) when the ARM writes to the C/S field of that MB (see Message Buffer Deactivation). The FlexCAN also provide a glitch filter which can filter the noises on CAN bus when the FlexCAN is in the STOP mode. The glitch filter width is configurable by the register HW_CAN_GFWR. 25.4.2 Transmit Process In order to transmit a CAN frame, the ARM must prepare a Message Buffer for transmission by executing the following procedure: * If the MB is active (transmission pending), write an ABORT code ('1001') to the Code field of the Control and Status word to request an abortion of the transmission, then read back the Code field and the IFLAG register to check if the transmission was aborted (see Transmission Abort Mechanism). If backwards compatibility is i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1681 Functional Description desired (AEN in MCR negated), just write '1000' to the Code field to inactivate the MB but then the pending frame may be transmitted without notification (see Message Buffer Deactivation). * Write the ID word. * Write the data bytes. * Write the Length, Control and Code fields of the Control and Status word to activate the MB. Once the MB is activated in the fourth step, it will participate in the arbitration process and eventually be transmitted according to its priority. At the end of the successful transmission, the value of the Free Running Timer is written into the Time Stamp field, the Code field in the Control and Status word is updated, a status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the corresponding Interrupt Mask Register bit. The new Code field after transmission depends on the code that was used to activate the MB in step four (see Table 25-2 and Table 25-3 in Section Message Buffer Structure). When the Abort feature is enabled (AEN in MCR is asserted), after the Interrupt Flag is asserted for a MB configured as transmit buffer, the MB is blocked, therefore the ARM is not able to update it until the Interrupt Flag be negated by ARM. It means that the ARM must clear the corresponding IFLAG before starting to prepare this MB for a new transmission or reception. 25.4.3 Arbitration Process The arbitration process is an algorithm executed by the MBM that scans the whole MB memory looking for the highest priority message to be transmitted. All MBs programmed as transmit buffers will be scanned to find the lowest ID1 or the lowest MB number or the highest priority, depending on the LBUF and LPRIO_EN bits on the Control Register. The arbitration process is triggered in the following events: * During the CRC field of the CAN frame * During the error delimiter field of the CAN frame * During Intermission, if the winner MB defined in a previous arbitration was deactivated, or if there was no MB to transmit, but the ARM wrote to the C/S word of any MB after the previous arbitration finished 1. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the same positions they are transmitted in the CAN frame. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1682 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) * When MBM is in Idle or Bus Off state and the ARM writes to the C/S word of any MB * Upon leaving Freeze Mode When LBUF is asserted, the LPRIO_EN bit has no effect and the lowest number buffer is transmitted first. When LBUF and LPRIO_EN are both negated, the MB with the lowest ID is transmitted first. But, if LBUF is negated and LPRIO_EN is asserted, the PRIO bits augment the ID used during the arbitration process. With this extended ID concept, arbitration is performed based on the full 32-bit ID and the PRIO bits define which MB should be transmitted first, therefore MBs with PRIO = 000 have higher priority. If two or more MBs have the same priority, the regular ID will determine the priority of transmission. If two or more MBs have the same priority (3 extra bits) and the same regular ID, the lowest MB will be transmitted first. Once the highest priority MB is selected, it is transferred to a temporary storage space called Serial Message Buffer (SMB), which has the same structure as a normal MB but is not user accessible. This operation is called move-out and after it is done, write access to the corresponding MB is blocked (if the AEN bit in MCR is asserted). The write access is released in the following events: * After the MB is transmitted * FlexCAN enters in HALT or BUS OFF * FlexCAN loses the bus arbitration or there is an error during the transmission At the first opportunity window on the CAN bus, the message on the SMB is transmitted according to the CAN protocol rules. FlexCAN transmits up to eight data bytes, even if the DLC (Data Length Code) value is bigger. 25.4.4 Receive Process To be able to receive CAN frames into the mailbox MBs, the ARM must prepare one or more Message Buffers for reception by executing the following steps: * If the MB has a pending transmission, write an ABORT code ('1001') to the Code field of the Control and Status word to request an abortion of the transmission, then read back the Code field and the IFLAG register to check if the transmission was aborted (see Transmission Abort Mechanism). If backwards compatibility is desired (AEN in MCR negated), just write '1000' to the Code field to inactivate the MB, but i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1683 Functional Description then the pending frame may be transmitted without notification (see Message Buffer Deactivation). If the MB already programmed as a receiver, just write '0000' to the Code field of the Control and Status word to keep the MB inactive. * Write the ID word * Write '0100' to the Code field of the Control and Status word to activate the MB Once the MB is activated in the third step, it will be able to receive frames that match the programmed ID. At the end of a successful reception, the MB is updated by the MBM as follows: * The value of the Free Running Timer is written into the Time Stamp field * The received ID, Data (8 bytes at most) and Length fields are stored * The Code field in the Control and Status word is updated (see Table 25-2 and Table 25-3 in Section Message Buffer Structure) * A status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the corresponding Interrupt Mask Register bit Upon receiving the MB interrupt, the ARM should service the received frame using the following procedure: * Read the Control and Status word (mandatory - activates an internal lock for this buffer) * Read the ID field (optional - needed only if a mask was used) * Read the Data field * Read the Free Running Timer (optional - releases the internal lock) Upon reading the Control and Status word, if the BUSY bit is set in the Code field, then the ARM should defer the access to the MB until this bit is negated. Reading the Free Running Timer is not mandatory. If not executed the MB remains locked, unless the ARM reads the C/S word of another MB. Note that only a single MB is locked at a time. The only mandatory ARM read operation is the one on the Control and Status word to assure data coherency (see Data Coherence). The ARM should synchronize to frame reception by the status flag bit for the specific MB in one of the IFLAG Registers and not by the Code field of that MB. Polling the Code field does not work because once a frame was received and the ARM services the MB (by reading the C/S word followed by unlocking the MB), the Code field will not return to EMPTY. It will remain FULL, as explained in Table 25-2. If the ARM tries to i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1684 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) workaround this behavior by writing to the C/S word to force an EMPTY code after reading the MB, the MB is actually deactivated from any currently ongoing matching process. As a result, a newly received frame matching the ID of that MB may be lost. In summary: never do polling by reading directly the C/S word of the MBs. Instead, read the IFLAG registers. Note that the received ID field is always stored in the matching MB, therefore the contents of the ID field in an MB may change if the match was due to masking. Note also that FlexCAN does receive frames transmitted by itself if there exists an Rx matching MB, provided the SRX_DIS bit in the MCR is not asserted. If SRX_DIS is asserted, FlexCAN will not store frames transmitted by itself in any MB, even if it contains a matching MB, and no interrupt flag or interrupt signal will be generated due to the frame reception. To be able to receive CAN frames through the FIFO, the ARM must enable and configure the FIFO during Freeze Mode (see Rx FIFO). Upon receiving the frames available interrupt from FIFO, the ARM should service the received frame using the following procedure: * Read the Control and Status word (optional - needed only if a mask was used for IDE and RTR bits) * Read the ID field (optional - needed only if a mask was used) * Read the Data field * Clear the frames available interrupt (mandatory - release the buffer and allow the ARM to read the next FIFO entry) 25.4.5 Matching Process The matching process is an algorithm executed by the MBM that scans the MB memory looking for Rx MBs programmed with the same ID as the one received from the CAN bus. If the FIFO is enabled, the 8-entry ID table from FIFO is scanned first and then, if a match is not found within the FIFO table, the other MBs are scanned. In the event that the FIFO is full, the matching algorithm will always look for a matching MB outside the FIFO region. When the frame is received, it is temporarily stored in a hidden auxiliary MB called Serial Message Buffer (SMB). The matching process takes place during the CRC field of the received frame. If a matching ID is found in the FIFO table or in one of the regular MBs, the contents of the SMB will be transferred to the FIFO or to the matched MB i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1685 Functional Description during the sixth bit of the End-Of-Frame field of the CAN protocol. This operation is called move-in. If any protocol error (CRC, ACK, and so on) is detected, than the movein operation does not happen. For the regular mailbox MBs, an MB is said to be free to receive a new frame if the following conditions are satisfied: * The MB is not locked (see Message Buffer Lock Mechanism) * The Code field is either EMPTY or it is FULL or OVERRUN but the ARM has already serviced the MB (read the C/S word and then unlocked the MB) If the first MB with a matching ID is not free to receive the new frame, then the matching algorithm keeps looking for another free MB until it finds one. If it can not find one that is free, then it will overwrite the last matching MB (unless it is locked) and set the Code field to OVERRUN (see Table 25-2 and Table 25-3). If the last matching MB is locked, then the new message remains in the SMB, waiting for the MB to be unlocked (see Message Buffer Lock Mechanism). Suppose, for example, the FIFO is disabled and there are two MBs with the same ID, and FlexCAN starts receiving messages with that ID. Let us say that these MBs are the second and the fifth in the array. When the first message arrives, the matching algorithm will find the first match in MB number 2. The code of this MB is EMPTY, so the message is stored there. When the second message arrives, the matching algorithm will find MB number 2 again, but it is not free to receive, so it will keep looking and find MB number 5 and store the message there. If yet another message with the same ID arrives, the matching algorithm finds out that there are no matching MBs that are free to receive, so it decides to overwrite the last matched MB, which is number 5. In doing so, it sets the Code field of the MB to indicate OVERRUN. The ability to match the same ID in more than one MB can be exploited to implement a reception queue (in addition to the full featured FIFO) to allow more time for the ARM to service the MBs. By programming more than one MB with the same ID, received messages will be queued into the MBs. The ARM can examine the Time Stamp field of the MBs to determine the order in which the messages are arrived. The matching algorithm described above can be changed to be the same one used in previous versions of the FlexCAN module. When the BCC bit in MCR is negated, the matching algorithm stops at the first MB with a matching ID that it founds, whether this MB is free or not. As a result, the message queueing feature does not work if the BCC bit is negated. Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN supports individual masking per MB. During the matching algorithm, if a mask bit is asserted, then the corresponding ID bit is compared. If the mask bit is negated, the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1686 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) corresponding ID bit is "don't care". The Individual Mask Registers are implemented in RAM, so they are not initialized out of reset. Also, they can only be programmed if the BCC bit is asserted and while the module is in Freeze Mode. FlexCAN also supports an alternate masking scheme with only three mask registers (RGXMASK, RX14MASK and RX15MASK) for backwards compatibility. This alternate masking scheme is enabled when the BCC bit in the MCR Register is negated. 25.4.6 Data Coherence In order to maintain data coherency and FlexCAN proper operation, the ARM must obey the rules described in Transmit Process and Receive Process. Any form of ARM accessing a MB structure within FlexCAN other than those specified may cause FlexCAN to behave in an unpredictable way. 25.4.6.1 Transmission Abort Mechanism The abort mechanism provides a safe way to request the abortion of a pending transmission. A feedback mechanism is provided to inform the ARM if the transmission was aborted or if the frame could not be aborted and was transmitted instead. In order to maintain backwards compatibility, the abort mechanism must be explicitly enabled by asserting the AEN bit in the MCR. In order to abort a transmission, the ARM must write a specific abort code (1001) to the Code field of the Control and Status word. When the abort mechanism is enabled, the active MBs configured as transmission must be aborted first and then they may be updated. If the abort code is written to a MB that is currently being transmitted, or to an MB that was already loaded into the SMB for transmission, the write operation is blocked and the MB is not deactivated, but the abort request is captured and kept pending until one of the following conditions is satisfied: * The module loses the bus arbitration * There is an error during the transmission * The module is put into Freeze Mode If none of conditions above are reached, the MB is transmitted correctly, the interrupt flag is set in the IFLAG register and an interrupt to the ARM is generated (if enabled). The abort request is automatically cleared when the interrupt flag is set. In the other hand, i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1687 Functional Description if one of the above conditions is reached, the frame is not transmitted, therefore the abort code is written into the Code field, the interrupt flag is set in the IFLAG and an interrupt is (optionally) generated to the ARM. If the ARM writes the abort code before the transmission begins internally, then the write operation is not blocked, therefore the MB is updated and no interrupt flag is set. In this way the ARM just needs to read the abort code to make sure the active MB was deactivated. Although the AEN bit is asserted and the ARM wrote the abort code, in this case the MB is deactivated and not aborted, because the transmission did not start yet. One MB is only aborted when the abort request is captured and kept pending until one of the previous conditions are satisfied. The abort procedure can be summarized as follows: * ARM writes 1001 into the code field of the C/S word * ARM reads the CODE field and compares it to the value that was written * If the CODE field that was read is different from the value that was written, the ARM must read the corresponding IFLAG to check if the frame was transmitted or it is being currently transmitted. If the corresponding IFLAG is set, the frame was transmitted. If the corresponding IFLAG is reset, the ARM must wait for it to be set, and then the ARM must read the CODE field to check if the MB was aborted (CODE=1001) or it was transmitted (CODE=1000). 25.4.7 Message Buffer Deactivation Deactivation is a mechanism provided to maintain data coherence when the ARM writes to the Control and Status word of active MBs out of Freeze Mode. Any ARM write access to the Control and Status word of a MB causes that MB to be excluded from the transmit or receive processes during the current matching or arbitration round. The deactivation is temporary, affecting only for the current match/arbitration round. The purpose of deactivation is data coherency. The match/arbitration process scans the MBs to decide which MB to transmit or receive. If the ARM updates the MB in the middle of a match or arbitration process, the data of that MB may no longer be coherent, therefore deactivation of that MB is done. Even with the coherence mechanism described above, writing to the Control and Status word of active MBs when not in Freeze Mode may produce undesirable results. Examples are: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1688 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) * Matching and arbitration are one-pass processes. If MBs are deactivated after they are scanned, no re-evaluation is done to determine a new match/winner. If a Rx MB with a matching ID is deactivated during the matching process after it was scanned, then this MB is marked as invalid to receive the frame, and FlexCAN will keep looking for another matching MB within the ones it has not scanned yet. If it can not find one, then the message will be lost. Suppose, for example, that two MBs have a matching ID to a received frame, and the user deactivated the first matching MB after FlexCAN has scanned the second. The received frame is lost even if the second matching MB was free to receive. * If a Tx MB containing the lowest ID is deactivated after FlexCAN has scanned it, then FlexCAN will look for another winner within the MBs that it has not scanned yet. Therefore, it may transmit a MB with ID that may not be the lowest at the time because a lower ID might be present in one of the MBs that it had already scanned before the deactivation. * There is a point in time until which the deactivation of a Tx MB causes it not to be transmitted (end of move-out). After this point, it is transmitted but no interrupt is issued and the Code field is not updated. In order to avoid this situation, the abort procedures described in Transmission Abort Mechanism should be used. 25.4.8 Message Buffer Lock Mechanism Besides MB deactivation, FlexCAN has another data coherence mechanism for the receive process. When the ARM reads the Control and Status word of an "active not empty" Rx MB, FlexCAN assumes that the ARM wants to read the whole MB in an atomic operation, and therefore it sets an internal lock flag for that MB. The lock is released when the ARM reads the Free Running Timer (global unlock operation), or when it reads the Control and Status word of another MB. The MB locking is done to prevent a new frame to be written into the MB while the ARM is reading it. Note The locking mechanism only applies to Rx MBs which have a code different than INACTIVE ('0000') or EMPTY1('0100'). Also, Tx MBs can not be locked. Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the array are programmed with the same ID, and FlexCAN has already received and stored messages into these two MBs. Suppose now that the ARM decides to read MB number 5 1. In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior will be honoured when the BCC bit is negated. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1689 Functional Description and at the same time another message with the same ID is arriving. When the ARM reads the Control and Status word of MB number 5, this MB is locked. The new message arrives and the matching algorithm finds out that there are no MBs that are free to receive, so it decides to override MB number 5. However, this MB is locked, so the new message can not be written there. It will remain in the SMB waiting for the MB to be unlocked, and only then will be written to the MB. If the MB is not unlocked in time and yet another new message with the same ID arrives, then the new message overwrites the one on the SMB and there will be no indication of lost messages either in the Code field of the MB or in the Error and Status Register. While the message is being moved-in from the SMB to the MB, the BUSY bit on the Code field is asserted. If the ARM reads the Control and Status word and finds out that the BUSY bit is set, it should defer accessing the MB until the BUSY bit is negated. Note If the BUSY bit is asserted or if the MB is empty, then reading the Control and Status word does not lock the MB. Deactivation takes precedence over locking. If the ARM deactivates a locked Rx MB, then its lock status is negated and the MB is marked as invalid for the current matching round. Any pending message on the SMB will not be transferred anymore to the MB. 25.4.9 Rx FIFO The receive-only FIFO is enabled by asserting the FEN bit in the MCR. The reset value of this bit is zero to maintain software backwards compatibility with previous versions of the module that did not have the FIFO feature. When the FIFO is enabled, the memory region normally occupied by the first 8 MBs ($80-$FF) is now reserved for use of the FIFO engine (see Rx FIFO Structure). Management of read and write pointers is done internally by the FIFO engine. The ARM can read the received frames sequentially, in the order they were received, by repeatedly accessing a Message Buffer structure at the beginning of the memory. The FIFO can store up to 6 frames pending service by the ARM. An interrupt is sent to the ARM when new frames are available in the FIFO. Upon receiving the interrupt, the ARM must read the frame (accessing an MB in the $80 address) and then clear the interrupt. The act of clearing the interrupt triggers the FIFO engine to replace the MB in $80 with the next frame in the queue, and then issue another interrupt to the ARM. If the FIFO is full and more frames continue to be received, an OVERFLOW interrupt is issued to the ARM and subsequent frames are not accepted until the ARM creates space in the FIFO by reading one or more frames. A warning interrupt is also generated when 4frames are accumulated in the FIFO. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1690 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) A powerful filtering scheme is provided to accept only frames intended for the target application, thus reducing the interrupt servicing work load. The filtering criteria is specified by programming a table of 8 32-bit registers that can be configured to one of the following formats (see also Rx FIFO Structure): * Format A: 8 extended or standard IDs (including IDE and RTR) * Format B: 16 standard IDs or 16 extended 14-bit ID slices (including IDE and RTR) * Format C: 32 standard or extended 8-bit ID slices Note A chosen format is applied to all 8 registers of the filter table. It is not possible to mix formats within the table. The eight elements of the filter table are individually affected by the first eight Individual Mask Registers (RXIMR0 - RXIMR7), allowing very powerful filtering criteria to be defined. The rest of the RXIMR, starting from RXIM8, continue to affect the regular MBs, starting from MB8. If the BCC bit is negated (or if the RXIMR are not available for the particular MCU), then the FIFO filter table is affected by the legacy mask registers as follows: element 6 is affected by RX14MASK, element 7 is affected by RX15MASK and the other elements (0 to 5) are affected by RXGMASK. 25.4.10 CAN Protocol Related Features 25.4.10.1 Remote Frames Remote frame is a special kind of frame. The user can program a MB to be a Request Remote Frame by writing the MB as Transmit with the RTR bit set to '1'. After the Remote Request frame is transmitted successfully, the MB becomes a Receive Message Buffer, with the same ID as before. When a Remote Request frame is received by FlexCAN, its ID is compared to the IDs of the transmit message buffers with the Code field '1010'. If there is a matching ID, then this MB frame will be transmitted. Note that if the matching MB has the RTR bit set, then FlexCAN will transmit a Remote Frame as a response. A received Remote Request Frame is not stored in a receive buffer. It is only used to trigger a transmission of a frame in response. The mask registers are not used in remote frame matching, and all ID bits (except RTR) of the incoming received frame should match. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1691 CAN Protocol Related Features In the case that a Remote Request Frame was received and matched an MB, this message buffer immediately enters the internal arbitration process, but is considered as normal Tx MB, with no higher priority. The data length of this frame is independent of the DLC field in the remote frame that initiated its transmission. If the Rx FIFO is enabled (bit FEN set in MCR), FlexCAN will not generate an automatic response for Remote Request Frames that match the FIFO filtering criteria. If the remote frame matches one of the target IDs, it will be stored in the FIFO and presented to the ARM. Note that for filtering formats A and B, it is possible to select whether remote frames are accepted or not. For format C, remote frames are always accepted (if they match the ID). 25.4.10.2 Overload Frames FlexCAN does transmit overload frames due to detection of the following conditions on CAN bus: * Detection of a dominant bit in the first/second bit of Intermission * Detection of a dominant bit at the seventh bit (last) of End of Frame field (Rx frames) * Detection of a dominant bit at the eighth bit (last) of Error Frame Delimiter or Overload Frame Delimiter 25.4.10.3 Time Stamp The value of the Free Running Timer is sampled at the beginning of the Identifier field on the CAN bus, and is stored at the end of move-in in the TIME STAMP field, providing network behavior with respect to time. The Free Running Timer can be reset upon a specific frame reception, enabling network time synchronization. 25.4.10.4 Protocol Timing The FlexCAN only supports the crystal oscillator clock as the CPI clock. The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required in the CAN bus timing. The crystal oscillator clock has better jitter performance than PLL generated clocks. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1692 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) The FlexCAN module supports a variety of means to setup bit timing parameters that are required by the CAN protocol. The Control Register has various fields used to control bit timing parameters: PRESDIV, PROPSEG, PSEG1, PSEG2 and RJW. The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose period defines the 'time quantum' used to compose the CAN waveform. A time quantum is the atomic unit of time handled by the CAN engine. f Tq = f CANCLK (PrescalerValue) A bit time is subdivided into three segments1 (reference Figure 25-2 and Table 25-6): * SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section * Time Segment 1: This segment includes the Propagation Segment and the Phase Segment 1 of the CAN standard. It can be programmed by setting the PROPSEG and the PSEG1 fields of the CTRL Register so that their sum (plus 2) is in the range of 4 to 16 time quanta * Time Segment 2: This segment represents the Phase Segment 2 of the CAN standard. It can be programmed by setting the PSEG2 field of the CTRL Register (plus 1) to be 2 to 8 time quanta long BitRate = 1. f Tq (number of Time Quanta) For further explanation of the underlying concepts please refer to ISO/DIS 11519-1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1693 CAN Protocol Related Features NRZ Signal SYN C _SEG Time Segment 1 (PROP_SEG + PSEG1 + 2) Time Segment 2 (PSEG2 + 1) 1 4 ... 16 2 ... 8 8 ... 25 Time Quanta = 1 Bit Time Transmit Point Sample Point (single or triple sampling) Figure 25-2. Segments within the Bit Time Table 25-6. Time Segment Syntax Syntax Description SYNC_SEG System expects transitions to occur on the bus during this period. Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node samples the bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample. Table 25-7 gives an overview of the CAN compliant segment settings and the related parameter values. Table 25-7. CAN Standard Compliant Bit Time Segment Settings Time Segment 1 Time Segment 2 Re-synchronization Jump Width 5 .. 10 2 1 .. 2 4 .. 11 3 1 .. 3 5 .. 12 4 1 .. 4 6 .. 13 5 1 .. 4 7 .. 14 6 1 .. 4 8 .. 15 7 1 .. 4 9 .. 16 8 1 .. 4 NOTE It is the user's responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit time calculations, use an IPT (Information Processing Time) of 2, which is the value implemented in the FlexCAN module. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1694 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) 25.4.10.5 Arbitration and Matching Timing During normal transmission or reception of frames, the arbitration, matching, move-in and move-out processes are executed during certain time windows inside the CAN frame, as shown in Figure 25-3. Start Move (bit 6) CRC (15) Interm EOF (7) Move Window Matching/Arbitration Window (24 bits) Figure 25-3. Arbitration, Match and Move Time Windows When doing matching and arbitration, FlexCAN needs to scan the whole Message Buffer memory during the available time slot. In order to have sufficient time to do that, the following requirements must be observed: * A valid CAN bit timing must be programmed, as indicated in Table 25-7 * The peripheral clock frequency can not be smaller than the oscillator clock frequency, that is the PLL can not be programmed to divide down the oscillator clock * There must be a minimum ratio between the peripheral clock frequency and the CAN bit rate, as specified in Table 25-8 Table 25-8. Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate Number of Message Buffers Minimum Ratio 16 8 32 8 64 16 A direct consequence of the first requirement is that the minimum number of time quanta per CAN bit must be 8, so the oscillator clock frequency should be at least eight times the CAN bit rate. The minimum frequency ratio specified in Table 25-8 can be achieved by choosing a high enough peripheral clock frequency when compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters (PRESDIV, PROPSEG, PSEG1, PSEG2). As an example, taking the case of 64 MBs, if the oscillator and peripheral clock frequencies are equal and the CAN bit timing is programmed to i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1695 Modes of Operation Details have 8 time quanta per bit, then the prescaler factor (PRESDIV + 1) should be at least 2. For prescaler factor equal to one and CAN bit timing with 8 time quanta per bit, the ratio between peripheral and oscillator clock frequencies should be at least 2. 25.4.11 Modes of Operation Details 25.4.11.1 Freeze Mode This mode is entered by asserting the HALT bit in the MCR Register or when the i.MX28 is put into Debug Mode. In both cases, it is also necessary that the FRZ bit is asserted in the MCR Register and the module is not in any of the low power modes (Disable, Stop). When Freeze Mode is requested during transmission or reception, FlexCAN does the following: * Waits to be in either Intermission, Passive Error, Bus Off or Idle state * Waits for all internal activities like arbitration, matching, move-in and move-out to finish * Ignores the Rx input pin and drives the Tx pin as recessive * Stops the prescaler, therefore halting all CAN protocol activities * Grants write access to the Error Counters Register, which is read-only in other modes * Sets the NOT_RDY and FRZ_ACK bits in MCR After requesting Freeze Mode, the user must wait for the FRZ_ACK bit to be asserted in MCR before executing any other action, otherwise FlexCAN may operate in an unpredictable way. In Freeze mode, all memory mapped registers are accessible. Exiting Freeze Mode is done in one of the following ways: * ARM negates the FRZ bit in the MCR Register * The MCU is removed from Debug Mode (negating ipg_debug) and/or the HALT bit is negated Once out of Freeze Mode, FlexCAN tries to re-synchronize to the CAN bus by waiting for 11 consecutive recessive bits. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1696 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) 25.4.11.2 Module Disable Mode This low power mode is entered when the MDIS bit in the MCR Register is asserted. If the module is disabled during Freeze Mode, it shuts down the clocks to the CPI and MBM sub-modules, sets the LPM_ACK bit and negates the FRZ_ACK bit. If the module is disabled during transmission or reception, FlexCAN does the following: * Waits to be in either Idle or Bus Off state, or otherwise waits for the third bit of Intermission and then checks it to be recessive * Waits for all internal activities like arbitration, matching, move-in and move-out to finish * Ignores its Rx input pin and drives its Tx pin as recessive * Shuts down the clocks to the CPI and MBM sub-modules * Sets the NOT_RDY and LPM_ACK bits in MCR The Bus Interface Unit continues to operate, enabling the ARM to access memory mapped registers, except the Free Running Timer, the Error Counter Register and the Message Buffers, which cannot be accessed when the module is in Disable Mode. Exiting from this mode is done by negating the MDIS bit, which will resume the clocks and negate the LPM_ACK bit. 25.4.11.3 Stop Mode This is a system low power mode in which all i.MX28 clocks are stopped for maximum power savings. If FlexCAN receives the global Stop Mode request (through ipg_stop) during Freeze Mode, it sets the LPM_ACK bit, negates the FRZ_ACK bit and then sends a Stop Acknowledge signal to the ARM, in order to shut down the clocks globally. If Stop Mode is requested during transmission or reception, FlexCAN does the following: * Waits to be in either Idle or Bus Off state, or otherwise waits for the third bit of Intermission and checks it to be recessive * Waits for all internal activities like arbitration, matching, move-in and move-out to finish * Ignores its Rx input pin and drives its Tx pin as recessive i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1697 Modes of Operation Details * Sets the NOT_RDY and LPM_ACK bits in MCR * Sends a Stop Acknowledge signal to the ARM, so that it can shut down the clocks globally Exiting Stop Mode is done in one of the following ways: * ARM resuming the clocks and removing the Stop Mode request * ARM resuming the clocks and Stop Mode request as a result of the Self Wake mechanism In the Self Wake mechanism, if the SLF_WAK bit in MCR Register was set at the time FlexCAN entered Stop Mode, then upon detection of a recessive to dominant transition on the CAN bus, FlexCAN sets the WAK_INT bit in the ESR Register and, if enabled by the WAK_MSK bit in MCR, generates a Wake Up interrupt to the ARM. Upon receiving the interrupt, the ARM should resume the clocks and remove the Stop Mode request. FlexCAN will then wait for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, it will not receive the frame that woke it up. Table 25-9 details the effect of SLF_WAK and WAK_MSK upon wake-up from Stop Mode. Note that wake-up from Stop Mode only works when both bits are asserted. Table 25-9. Wake-up from Stop Mode i.MX28 Clocks Enabled Wake-up Interrupt Generated 0 No No 0 1 No No 1 0 No No 1 1 Yes Yes SLF_WAK WAK_MSK 0 The sensitivity to CAN bus activity can be modified by applying a low-pass filter function to the Rx CAN input line while in Stop Mode. This feature can be used to protect FlexCAN from waking up due to short glitches on the CAN bus lines. Such glitches can result from electromagnetic interference within noisy environments. 25.4.11.4 Interrupts The module can generate up to 70 interrupt sources (64 interrupts due to message buffers and 6 interrupts due to ORed interrupts from MBs, Bus Off, Error, Tx Warning, Rx Warning and Wake Up). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1698 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) Each one of the message buffers can be an interrupt source, if its corresponding IMASK bit is set. There is no distinction between Tx and Rx interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission or reception. Each of the buffers has assigned a flag bit in the IFLAG Registers. The bit is set when the corresponding buffer completes a successful transmission/reception and is cleared when the ARM writes it to 1 (unless another interrupt is generated at the same time). If the Rx FIFO is enabled (bit FEN on MCR set), the interrupts corresponding to MBs 0 to 7 have a different behavior. Bit 7 of the IFLAG1 becomes the FIFO Overflow flag; bit 6 becomes the FIFO Warning flag, bit 5 becomes the Frames Available in FIFO flag and bits 4-0 are unused. A combined interrupt for all MBs is also generated by an OR of all the interrupt sources from MBs. This interrupt gets generated when any of the MBs generates an interrupt. In this case the ARM must read the IFLAG Registers to determine which MB caused the interrupt. The other 5 interrupt sources (Bus Off, Error, Tx Warning, Rx Warning and Wake Up) generate interrupts like the MB ones, and can be read from the Error and Status Register. The Bus Off, Error, Tx Warning and Rx Warning interrupt mask bits are located in the Control Register, and the Wake-Up interrupt mask bit is located in the MCR. 25.5 Initialization/Application Information This section provide instructions for initializing the FlexCAN module. 25.5.1 FlexCAN Initialization Sequence The FlexCAN module may be reset in three ways: * i.MX28 level hard reset using ipg_hard_async_reset_b, which resets all memory mapped registers asynchronously * i.MX28 level soft reset, which resets some of the memory mapped registers synchronously * SOFT_RST bit in MCR, which has the same effect as the i.MX28 level soft reset Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. Therefore, it may take some time to fully propagate its effects. The SOFT_RST bit remains asserted while soft reset is pending, so software can poll this bit i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1699 Initialization/Application Information to know when the reset has completed. Also, soft reset can not be applied while clocks are shut down in any of the low power modes. The low power mode should be exited and the clocks resumed before applying soft reset. The clock source (CLK_SRC bit) should be selected while the module is in Disable Mode. After the clock source is selected and the module is enabled (MDIS bit negated), FlexCAN automatically goes to Freeze Mode. In Freeze Mode, FlexCAN is unsynchronized to the CAN bus, the HALT and FRZ bits in MCR Register are set, the internal state machines are disabled and the FRZ_ACK and NOT_RDY bits in the MCR Register are set. The Tx pin is in recessive state and FlexCAN does not initiate any transmission or reception of CAN frames. Note that the Message Buffers and the Rx Individual Mask Registers are not affected by reset, so they are not automatically initialized. For any configuration change/initialization it is required that FlexCAN is put into Freeze Mode (see Freeze Mode). The following is a generic initialization sequence applicable to the FlexCAN module: * Initialize the Module Configuration Register * Enable the individual filtering per MB and reception queue features by setting the BCC bit * Enable the warning interrupts by setting the WRN_EN bit * If required, disable frame self reception by setting the SRX_DIS bit * Enable the FIFO by setting the FEN bit * Enable the abort mechanism by setting the AEN bit * Enable the local priority feature by setting the LPRIO_EN bit * Initialize the Control Register * Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW * Determine the bit rate by programming the PRESDIV field * Determine the internal arbitration mode (LBUF bit) * Initialize the Message Buffers * The Control and Status word of all Message Buffers must be initialized * If FIFO was enabled, the 8-entry ID table must be initialized * Other entries in each Message Buffer should be initialized as required i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1700 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) * Initialize the Rx Individual Mask Registers * Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in CTRL Register (for Bus Off and Error interrupts) and in MCR Register for Wake-Up interrupt * Negate the HALT bit in MCR Starting with the last event, FlexCAN attempts to synchronize to the CAN bus. 25.6 Programmable Registers CAN Hardware Register Format Summary There are Two CAN in chip. CAN0 base address is 0x80032000 and CAN1 base address is 0x80034000 HW_CAN memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8003_2000 Module Configuration Register (HW_CAN_MCR) 32 R/W 5890_000Fh 25.6.1/1702 8003_2004 Control Register (HW_CAN_CTRL) 32 R/W 0000_0000h 25.6.2/1704 8003_2008 Free Running Timer (HW_CAN_TIMER) 32 R/W 0000_0000h 25.6.3/1707 8003_2010 Rx Global Mask (HW_CAN_RXGMASK) 32 R/W FFFF_FFFFh 25.6.4/1707 8003_2014 Rx 14 Mask (HW_CAN_RX14MASK) 32 R/W FFFF_FFFFh 25.6.5/1708 8003_2018 Rx 15 Mask (HW_CAN_RX15MASK) 32 R/W FFFF_FFFFh 25.6.6/1709 8003_201C Error Counter Register (HW_CAN_ECR) 32 R/W 0000_0000h 25.6.7/1709 8003_2020 Error and Status Register (HW_CAN_ESR) 32 R/W 0000_0000h 25.6.8/1711 8003_2024 Interrupt Masks 2 Register (HW_CAN_IMASK2) 32 R/W 0000_0000h 25.6.9/1713 8003_2028 Interrupt Masks 1 Register (HW_CAN_IMASK1) 32 R/W 0000_0000h 25.6.10/ 1714 8003_202C Interrupt Flags 2 Register (HW_CAN_IFLAG2) 32 R/W 0000_0000h 25.6.11/ 1714 8003_2030 Interrupt Flags 1 Register (HW_CAN_IFLAG1) 32 R/W 0000_0000h 25.6.12/ 1715 8003_2034 Glitch Filter Width Register (HW_CAN_GFWR) 32 R/W 0000_007Fh 25.6.13/ 1715 8003_2080 CAN Messager Buffer Registers (HW_CAN_MBn) 32 R/W 0000_0000h 25.6.14/ 1716 8003_2880 Rx Individual Mask Registers (HW_CAN_RXIMRn) 32 R/W 0000_0000h 25.6.15/ 1716 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1701 Programmable Registers 25.6.1 Module Configuration Register (HW_CAN_MCR) This register defines global system configurations, such as the module operation mode (e.g., low power)and maximum message buffer configuration.Most of the fields in this register can be accessed at any time, except the MAXMB field, which should only be changed while the module is in Freeze Mode. The default value of this register is 0x5890000f. The MCR defines global system configurations such as the module operation mode (for example, low-power mode) and maximum message buffer configuration. The MAXMB field must only be changed while the module is in freeze mode: all other fields in this register can be accessed at any time. 30 29 28 24 23 22 21 16 MDIS FRZ FEN SLF_ WAK SRX_DIS 17 RSVD3 18 WAK_SRC 19 SUPV FRZ_ ACK 20 SOFT_RST 25 WAK_MSK 26 HALT R 27 LPM_ACK 31 NOT_RDY Bit WRN_EN Address: 8003_2000h base + 0h offset = 8003_2000h BCC 0 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 W Bit R RSVD2 RSVD1 LPRIO_EN Reset AEN 0 0 RSVD0 IDAM MAXMB W Reset 0 0 0 0 0 0 0 0 0 0 1 1 HW_CAN_MCR field descriptions Field Description 31 MDIS Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1702 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) HW_CAN_MCR field descriptions (continued) Field Description This bit controls whether CAN is enabled or not.When disabled, CAN shuts down the clocks to the CAN Protocol Interface and Message Buffer Management sub-modules. This is the only bit in MCR not affected by soft reset. 1 Disable the FlexCAN module 0 Enable the FlexCAN module 30 FRZ 29 FEN 28 HALT 27 NOT_RDY 26 WAK_MSK 25 SOFT_RST 24 FRZ_ACK 23 SUPV 22 SLF_WAK The FRZ bit specifies the CAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at MCU level (through assertion of the ipg_debug signal on the IP Interface). When FRZ is asserted, CAN is enabled to enter Freeze Mode. Negation of this bit field causes CAN to exit from Freeze Mode. This bit controls whether the FIFO feature is enabled or not. When FEN is set, MBs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory region ($80-$FF) is used by the FIFO engine. Assertion of this bit puts the CAN module into Freeze Mode. The ARM should clear it after initializing the Message Buffers and Control Register. No reception or transmission is performed by CAN before this bit is cleared. While in Freeze Mode, the ARM has write access to the Error Counter Register, that is otherwise read-only. Freeze Mode can not be entered while CAN is in any of the low power modes. This read-only bit indicates that CAN is either in DisableMode, StopMode or Freeze Mode. It is negated once CAN has exited these modes. This bit enables the Wake Up Interrupt generation. When this bit is asserted, CAN resets its internal state machines and some of the memory mapped registers. The following registers are reset: MCR (except the MDIS bit), TIMER, TCR, ECR, ESR, IMASK1, IMASK2, IFLAG1, IFLAG2. Configuration registers that control the interface to the CAN bus are not affected by soft reset. This read-only bit indicates that CAN is in Freeze Mode and its prescaler is stopped. This bit configures some of the CAN registers to be either in Supervisor or Unrestricted memory space. This bit enables the Self Wake Up feature when CAN is in Stop Mode. If this bit had been asserted by the time CAN entered StopMode, then CAN will look for a recessive to dominant transition on the bus during these modes. 21 WRN_EN Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1703 Programmable Registers HW_CAN_MCR field descriptions (continued) Field Description When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register. If WRN_EN is negated, the TWRN_INT and RWRN_INT flags will always be zero, independent of the values of the error counters, and no warning interrupt will ever be generated. 20 LPM_ACK 19 WAK_SRC 18 RSVD3 17 SRX_DIS 16 BCC 15-14 RSVD2 13 LPRIO_EN 12 AEN 11-10 RSVD1 9-8 IDAM 7-6 RSVD0 This read-only bit indicates that CAN is either in Disable Mode or Stop Mode. This bit defines whether the integrated low-pass filter is applied to protect the Rx CAN input from spurious wake up. This bit field is reserved. This bit defines whether CAN is allowed to receive frames transmitted by itself. This bit is provided to support Backwards Compatibility with previous CAN versions. Reserved. This bit is provided for backwards compatibility reasons. It controls whether the local priority feature is enabled or not. This bit is supplied for backwards compatibility reasons. Reserved. This 2-bit field identifies the format of the elements of the Rx FIFO filter table Reserved. MAXMB This 6-bit field defines the maximum number of message buffers that will take part in the matching and arbitration processes. 25.6.2 Control Register (HW_CAN_CTRL) This register is defined for specific CAN control features related to the CAN bus. The default value of this register is 0x00000000. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1704 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) This register is defined for specific FlexCAN control features related to the CAN bus, such as bit rate, programmable sampling point within an Rx bit, loopback mode, listenonly mode, bus-off recovery behavior and interrupt enabling (bus-off, error, warning). It also determines the division factor for the clock prescaler. Most of the fields in this register can only be changed while the module is in disable mode or in freeze mode. Exceptions are the BOFF_MSK, ERR_MSK, TWRN_MSK, RWRN_MSK and BOFF_REC bits, that can be accessed at any time. Address: 8003_2000h base + 4h offset = 8003_2004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PRESDIV RJW PSEG1 PSEG2 Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMP BOFF_REC W 0 0 RSVD 0 RWRN_MSK 0 LPB TWRN_MSK ERR_ MSK CLK_SRC BOFF_MSK R 0 0 0 0 TSYN LBUF LOM PROP_SEG W Reset 0 0 0 0 0 0 0 0 HW_CAN_CTRL field descriptions Field 31-24 PRESDIV 23-22 RJW 21-19 PSEG1 Description This 8-bit field defines the ratio between the CPI clock frequency and the serial clock (SCLK) frequency. This 2-bit field defines the maximum number of time quanta that a bit time can be changed by one RJW re-synchronization. This 3-bit field defines the length of phase buffer segment 1 in the bit time. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1705 Programmable Registers HW_CAN_CTRL field descriptions (continued) Field 18-16 PSEG2 15 BOFF_MSK 14 ERR_MSK 13 CLK_SRC Description This 3-bit field defines the length of phase buffer segment 2 in the bit time. This bit provides a mask for the bus-off interrupt. This bit provides a mask for the error interrupt. This bit selects the clock source to the CAN Protocol Interface (CPI) to be either the peripheral clock (driven by the PLL) or the crystal oscillator clock. In i.MX28, the clock source is just from the crystal oscillator clock. Setting this bit has no effects. 12 LPB 11 TWRN_MSK 10 RWRN_MSK 9-8 RSVD 7 SMP 6 BOFF_REC 5 TSYN 4 LBUF 3 LOM This bit configures CAN to operate in Loop-Back Mode. This bit provides a mask for the TxWarning Interrupt associated with the TWRN_INT flag in the Error and Status Register. This bit provides amask for the RxWarning Interrupt associated with the RWRN_INT flag in the Error and Status Register. Reserved. This bit defines the sampling mode of CAN bits at the Rx input. This bit defines how CAN recovers from the bus-off state. This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0. This bit defines the ordering mechanism for Message Buffer transmission. This bit configures CAN to operate in Listen Only Mode. PROP_SEG This 3-bit field defines the length of the propagation segment in the bit time. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1706 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) 25.6.3 Free Running Timer (HW_CAN_TIMER) This register represents a 16-bit free-running counter that can be read and written by the ARM. The timer starts at 0x0000 upon reset, counts linearly to 0xFFFF, then wraps back to 0x0000. The default value of this register is 0x00000000. This register represents a 16-bit free-running counter that can be read and written by the ARM. The timer starts at 0x0000 upon reset, counts linearly to 0xFFFF, then wraps back to 0x0000. The timer is clocked by the FlexCAN bit-clock (which defines the baud rate on the CAN bus). During a message transmission/reception, it increments each time a bit is received or transmitted. When there is no message on the bus, it counts using the previously-programmed baud rate. During freeze mode, the timer is not incremented. The timer value is captured at the beginning of the identifier field of any frame on the CAN bus. This captured value is written into the time stamp entry in a message buffer after a successful reception or transmission of a message. Writing to the timer is an indirect operation. The data is first written to an auxiliary register and then an internal request/ acknowledge procedure across clock domains is executed. All this is transparent to the user, except for the fact that the data takes some time to actually be written to the register. If desired, software can poll the register to discover when the data was actually written. Address: 8003_2000h base + 8h offset = 8003_2008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RSVD R 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 TIMER W Reset 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_CAN_TIMER field descriptions Field 31-16 RSVD Description Reserved . TIMER each time a message is received in Message Buffer 25.6.4 Rx Global Mask (HW_CAN_RXGMASK) The default value of this register is 0xffffffff. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1707 Programmable Registers This register is provided for legacy support and for low cost MCUs that do not have the individual masking per message buffer feature. For MCUs supporting individual masks per message buffer, setting the BCC bit in the MCR causes the RXGMASK register to have no effect on the module operation. For MCUs not supporting individual masks per message buffer, this register is always effective. RXGMASK is used as acceptance mask for all Rx message buffers, excluding message buffers 14C15, which have individual mask registers. When the FEN bit in the MCR is set (FIFO enabled), the RXGMASK also applies to all elements of the ID filter table, except elements 6-7, which have individual masks. Setting the BCC bit in MCR causes the RXGMASK register to have no effect on the modules operation. The contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is transmitting or receiving frames. Address: 8003_2000h base + 10h offset = 8003_2010h Bit R W 31 Reset 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MI 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_CAN_RXGMASK field descriptions Field Description MI This register is provided for legacy support and for low cost MCUs that do not have the individual masking per message buffer feature. 25.6.5 Rx 14 Mask (HW_CAN_RX14MASK) The default value of this register is 0xffffffff. RX14MASK is used as acceptance mask for the identifier in message buffer 14. When the FEN bit in the MCR is set (FIFO enabled), the RXG14MASK also applies to element 6 of the ID filter table. Setting the BCC bit in the MCR causes the RX14MASK register to have no effect on the module operation. This register has the same structure as RXGMASK. It must be programmed while the module is in freeze mode, and must not be modified when the module is transmitting or receiving frames. Address: 8003_2000h base + 14h offset = 8003_2014h Bit R W 31 Reset 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MI 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1708 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) HW_CAN_RX14MASK field descriptions Field Description MI This register is provided for legacy support and for low cost MCUs that do not have the individual masking per message buffer feature. 25.6.6 Rx 15 Mask (HW_CAN_RX15MASK) The default value of this register is 0xffffffff. When the BCC bit is cleared, RX15MASK is used as acceptance mask for the identifier in message buffer 15. When the FEN bit in the MCR is set (FIFO enabled), the RXG14MASK also applies to element 7 of the ID filter table. Setting the BCC bit in the MCR causes the RX15MASK register to have no effect on the module operation. This register has the same structure as the RXGMASK. It must be programmed while the module is in freeze mode, and must not be modified when the module is transmitting or receiving frames. Address: 8003_2000h base + 18h offset = 8003_2018h Bit R W 31 Reset 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 MI 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_CAN_RX15MASK field descriptions Field Description MI This register is provided for legacy support and for low cost MCUs that do not have the individual masking per message buffer feature. 25.6.7 Error Counter Register (HW_CAN_ECR) This register has two 8-bit fields which reflect the value of the transmit error counter (tx_err_counter field) and receive error counter (rx_err_counter field). This register has two 8-bit fields which reflect the value of the transmit error counter (tx_err_counter field) and receive error counter (rx_err_counter field). The rules for increasing and decreasing these counters are described in the CAN protocol and are completely implemented in the FlexCAN module. Both counters are read only except in freeze mode, where they can be written by the ARM. Writing to the error counter register while in freeze mode is an indirect operation. The data is first written to an auxiliary i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1709 Programmable Registers register, and then an internal request/acknowledge procedure across clock domains is executed. All this is transparent to the user, except for the fact that the data takes some time to actually be written to the register. If desired, software can poll the register to discover when the data was actually written. FlexCAN responds to any bus state as described in the protocol, for example, by transmitting an error active or error passive flag, delaying its transmission start time (error passive), and avoiding any influence on the bus when in the bus-off state. The following are the basic rules for FlexCAN bus state transitions: If the value of tx_err_counter or rx_err_counter increases to exceed 127, the FLT_CONF field in the error and status register is updated to reflect error passive state. If the FlexCAN state is error passive, and either tx_err_counter or rx_err_counter decrements to a value less than or equal to 127 while the other already satisfies this condition, the FLT_CONF field in the error and status register is updated to reflect error active state. If the value of tx_err_counter increases to be greater than 255, the FLT_CONF field in the error and status register is updated to reflect the bus-off state, and an interrupt is issued. The value of tx_err_counter is then reset to zero. If FlexCAN is in the bus-off state, then tx_err_counter is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence, tx_err_counter is reset to zero and counts in a manner where the internal counter counts 11 such bits and then wraps around while incrementing the tx_err_counter. when tx_err_counter reaches the value of 128, the FLT_CONF field in the error and status register is updated to be error active and both error counters are reset to zero. at any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without affecting the tx_err_counter value. If during system start-up, only one node is operating, then its tx_err_counter increases in each message it is trying to transmit, as a result of acknowledge errors (indicated by the ACK_ERR bit in the error and status register). After the transition to error passive state, the tx_err_counter does not increment anymore by acknowledge errors. Therefore the device never goes to the bus-off state. If the rx_err_counter increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. At the next successful message reception, the counter is set to a value between 119 and 127 to resume to error active state. Address: 8003_2000h base + 1Ch offset = 8003_201Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RSVD R 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 RX_ERR_COUNTER W Reset 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 TX_ERR_COUNTER 0 0 0 0 0 0 0 0 0 HW_CAN_ECR field descriptions Field Description 31-16 RSVD Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1710 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) HW_CAN_ECR field descriptions (continued) Field Description Reserved . 15-8 RX_ERR_ COUNTER Receive error counter TX_ERR_ COUNTER Transmit error counter 25.6.8 Error and Status Register (HW_CAN_ESR) This register reflects various error conditions, some general status of the device and it is the source of four interrupts to the ARM. This register reflects various error conditions, some general status of the device and it is the source of four interrupts to the ARM. The reported error conditions are those that occurred since the last time the ARM read this register. The ARM read action clears bits. Bits are status bits. Most bits in this register are read-only, except TWRN_INT, RWRN_INT, BOFF_INT, WAK_INT and ERR_INT, which are interrupt flags that can be cleared by writing 1 to them (writing 0 has no effect). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 0 0 0 0 0 16 0 0 RSVD1 R W Reset 17 RWRN_INT Bit TWRN_INT Address: 8003_2000h base + 20h offset = 8003_2020h 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1711 10 9 8 7 6 CRC_ERR FRM_ERR STF_ ERR TX_WRN RX_WRN IDLE TXRX 0 0 0 0 0 0 0 0 0 0 5 4 FLT_CONF 2 1 0 WAK_INT 11 ERR_INT 12 BOFF_INT 13 3 RSVD0 14 ACK_ERR R 15 BIT0_ERR Bit BIT1_ERR Programmable Registers 0 0 0 W Reset 0 0 0 HW_CAN_ESR field descriptions Field 31-18 RSVD1 17 TWRN_INT 16 RWRN_INT 15 BIT1_ERR 14 BIT0_ERR 13 ACK_ERR 12 CRC_ERR 11 FRM_ERR 10 STF_ERR Description Reserved . If theWRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from 0 to 1, meaning that the Tx error counter reached If theWRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from 0 to 1, meaning that the Rx error counters reached This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. This bit indicates that an Acknowledge Error has been detected by the transmitter node This bit indicates that a CRC Error has been detected by the receiver node This bit indicates that a Form Error has been detected by the receiver node This bit indicates that a Stuffing Error has been detected. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1712 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) HW_CAN_ESR field descriptions (continued) Field Description 9 TX_WRN This bit indicates when repetitive errors are occurring during message transmission. 8 RX_WRN This bit indicates when repetitive errors are occurring during message reception. 7 IDLE This bit indicates when CAN bus is in IDLE state. 6 TXRX This bit indicates if CAN is transmitting or receiving a message when the CAN bus is not in IDLE state. 5-4 FLT_CONF This 2-bit field indicates the Confinement State of the CAN module 3 RSVD0 Reserved. 2 BOFF_INT This bit is set when CAN enters Bus Off state 1 ERR_INT This bit indicates that at least one of the Error Bits (bits 15-10) is set. 0 WAK_INT When CAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the ARM. 25.6.9 Interrupt Masks 2 Register (HW_CAN_IMASK2) The default value of this register is 0x00000000. This register allows any number of a range of 32 message buffer interrupts to be enabled or disabled. It contains one interrupt mask bit per buffer, enabling the ARM to determine which buffer generates an interrupt after a successful transmission or reception (that is, when the corresponding IFLAG2 bit is set). Address: 8003_2000h base + 24h offset = 8003_2024h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1713 Programmable Registers HW_CAN_IMASK2 field descriptions Field Description BUFM Each bit enables or disables the respective FlexCAN message buffer interrupt (message buffers 32~63). 25.6.10 Interrupt Masks 1 Register (HW_CAN_IMASK1) The default value of this register is 0x00000000. This register enables or disables any number of a range of 32 message buffer interrupts. It contains one interrupt mask bit per buffer, enabling the ARM to determine which buffer generates an interrupt after a successful transmission or reception (that is, when the corresponding IFLAG1 bit is set) Address: 8003_2000h base + 28h offset = 8003_2028h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_CAN_IMASK1 field descriptions Field Description BUFM This register allows any number of a range of 32 message buffer interrupts to be enabled or disabled. 25.6.11 Interrupt Flags 2 Register (HW_CAN_IFLAG2) The default value of this register is 0x00000000. This register defines the flags for 32 message buffer interrupts. It contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding IFLAG2 bit. If the corresponding IMASK2 bit is set, an interrupt is generated. The interrupt flag must be cleared by writing a 1; writing 0 has no effect. When the AEN bit in the MCR is set (abort enabled), while the IFLAG2 bit is set for a message buffer configured as Tx, ARM write access to the corresponding message buffer is blocked. Address: 8003_2000h base + 2Ch offset = 8003_202Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1714 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) HW_CAN_IFLAG2 field descriptions Field Description BUFI This register defines the flags for 32Message Buffer interrupts. 25.6.12 Interrupt Flags 1 Register (HW_CAN_IFLAG1) The default value of this register is 0x00000000. This register defines the flags for 32 message buffer interrupts and FIFO interrupts. It contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt is generated. The interrupt flag must be cleared by writing a 1 to it. Writing 0 has no effect. Setting the abort enabled (AEN) bit in the MCR while the IFLAG1 bit is set for a message buffer configured as Tx blocks the ARMs write access to the corresponding message buffer. Setting the FIFO enable (FEN) bit in the MCR changes the function of the 8 least significant interrupt flags (BUF7ICBUF0I) to support the FIFOs operation. BUF7I, BUF6I, and BUF5I indicate operating conditions of the FIFO; BUF4ICBUF0I are not used. Address: 8003_2000h base + 30h offset = 8003_2030h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_CAN_IFLAG1 field descriptions Field Description BUFI This register defines the flags for 32 Message Buffer interrupts. 25.6.13 Glitch Filter Width Register (HW_CAN_GFWR) The default value of this register is 0x0000007f. The Glitch Filter just takes effects when the FlexCAN enters the STOP mode. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1715 Programmable Registers Address: 8003_2000h base + 34h offset = 8003_2034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 RSVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 3 2 1 0 GFWR W Reset 4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 HW_CAN_GFWR field descriptions Field Description 31-8 RSVD0 Reserved GFWR The Glitch Filter Width Register defines the glitch width which will be filtered. 25.6.14 CAN Messager Buffer Registers (HW_CAN_MBn) The default value of this register is 0x00000000. There are 64 MB registers ( MB0~MB63) n denotes the number from 0 to 63. See the Messager Buffer structure in previous section. Address: 8003_2000h base + 80h offset = 8003_2080h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_CAN_MBn field descriptions Field Description MBn These registers are used as acceptance storage for messages. 25.6.15 Rx Individual Mask Registers (HW_CAN_RXIMRn) The default value of this register is 0x00000000. There are 64 Rx Individual Mask registers ( RXIMR0RXIMR63) n denotes the number from 0 to 63. These registers are used as acceptance masks for ID filtering in Rx message buffers and the FIFO. If the FIFO is not enabled, one mask register is provided for each available message buffer, providing ID masking capability on a per message buffer basis. When the FIFO is enabled (FEN bit in the MCR is set), the first 8 mask registers apply to the 8 elements of the FIFO filter table (on a one-to-one correspondence), while the rest of the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1716 Freescale Semiconductor, Inc. Chapter 25 Controller Area Network (FlexCAN) registers apply to the regular message buffers, starting from message buffer 8. The individual Rx mask registers are implemented in RAM, so they are not affected by reset and must be explicitly initialized prior to any reception. Furthermore, they can only be accessed by the ARM while the module is in freeze mode. Outside of freeze mode, write accesses are blocked and read accesses return all zeros. Furthermore, if the BCC bit in the MCR is cleared, any read or write operation to these registers results in an access error. Address: 8003_2000h base + 880h offset = 8003_2880h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_CAN_RXIMRn field descriptions Field MI Description These registers are used as acceptance masks for ID filtering in Rx message buffers and the FIFO. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1717 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1718 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.1 Overview The ethernet controller (ENET) consists of two MACs (media access controllers), each with it's own dedicated uDMA (unified DMA) module. The MAC module is third party IP from "More Than IP" (MTIP). The MACs interface to 10 Mbps and 100 Mbps Ethernet/IEEE 802.3TM networks. For Ethernet, an external PHY or SerDes device is required to complete the interface to the media. Each MAC supports multiple standard media-independent interfaces. An integrated 3-Port Switch allows the macs to filter and forward traffic at wire-speed to each other or the core, or operate as two independent ports. The ENET assembly provides two master ports on the AHB Bus. IP provides interface for connecting various FIFOs for data storage (for MAC and Switch). The ENET MAC is backward compatible with the Freescale FEC controller (Such as the FEC used in i.MX25). 26.1.1 Block Diagram SOC Pad uDMA0 APB Mux MAC0 APB Bus AHB Bus Switch MAC1 uDMA1 Figure 26-1. SOCENET Pad Overview Block Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1719 Unified DMA Block Guide 26.1.2 Features * MAC supports full 802.3 specification with preamble/SFD generation, frame padding generation, CRC generation and checking * Dynamically configurable to support 10/100 Mbps * Supports full duplex and configurable half duplex operations * Supports AMD magic packet detection with interrupt for node remote power management * Supports interface to Fast Ethernet Phy devices through Medium independent interface (MII) working at 25 MHz and Reduced Medium independent interface (RMII) working at 50 MHz * Provides 64 bit FIFO interface (transmit and receive) * When operating in Full Duplex mode, implements automated Pause Frame (802.3 x 31A) generation and termination providing flow control without user application intervention * Implements standard flow control mechanism in full duplex operation mode * In half duplex mode, provides full collision support, including jamming, backoff and automatic retransmission * Support for VLAN tagged frames as per IEEE 802.1Q * Programmable MAC address * Multicast and unicast address filtering on receive based on 64 entries hash table thus reducing higher layer processing load * Programmable frame maximum length providing support for any standard or proprietary frame length * Statistic indicators for frame traffic as well as errors (alignment, CRC error and so on) and pause frames providing for IEEE 802.3 basic and mandatory management information database (MIB) package and Remote network monitoring (RFC 2819) * Multiple internal loopback options * MDIO master interface for PHY device configuration * Support for all IEEE 1588 frames * Reference clock can be chosen independently of network speed * Software programmable precise time stamping of Ingress frames and Egress frames * Hardware and software controllable timer synchronization 26.2 Unified DMA Block Guide This section includes an introduction, descriptions of signals, a description of the control interface, and a functional description. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1720 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.2.1 Introduction This section includes an overview, description of features, and a description of the modes of operation. 26.2.1.1 Overview The Unified DMA (uDMA) block is connected with the ENET-MAC and through the 3PSWITCH. This is NOT a general purpose DMA but is highly specific to support Ethernet traffic. Fundamentally, there are two basic modes of operation. The uDMA supports a legacy mode which enables data to be transferred in a format significantly consistent with the legacy FEC device that exists on several parts through the Legacy Buffer Descriptor (LBD). Additionally the uDMA supports an Enhanced Buffer Descriptor (EBD) which in turn provides the ability to make use of several new features including (but not limited to) IEEE-1588 support, Gigabit Ethernet, transmit error checking and various off loading features. The uDMA blocks are highlighted Figure 26-2. SOCinPad 1 2 APB Mux MAC0 APB Bus uDMA0 3 AHB Bus Switch MAC1 2 uDMA1 3 1 Figure 26-2. SOCTypical Pad uDMA SoC Connection In reference to the figure: 1 - The interface between the MAC-NET and the SoC Pad Logic. All pin multiplexing takes place outside the ENET-MAC, including RMII and MII. 2 - The ENET-MAC communicates with the Unified DMA through two FIFO interfaces. One of the FIFO interfaces is for RX the other is for TX. These interfaces also contain a set of sideband signals. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1721 Unified DMA Block Guide 3 - The Unified DMA communicates with the SoC Platform through this interface. 26.2.1.2 Features The primary features of the uDMA are listed below: * Only Surport big-endian. * Separate TX and RX interfaces to allow for minimum space or maximum data throughput. * Supports Legacy Buffer Descriptor programming models and functionality. * Enables an Enhanced Buffer Descriptor programming model to support new Ethernet functionality. 26.2.1.3 Modes of Operation The primary modes of operation of the uDMA are described in this section: * Legacy mode * Enhanced mode 26.2.1.3.1 Legacy Mode While in legacy mode, the uDMA reads and generates Legacy Buffer Descriptors (LBD). Additionally, great effort is made to ensure that support signals such as interrupts behave consistently with the legacy programming model used with the FEC. This is the default mode of operation. 26.2.1.3.2 Enhanced Mode While in enhanced mode, the uDMA reads and generates Enhanced Buffer Descriptors (EBD). The descriptors are based on the LBD but allow for the support of additional features such as IEEE-1588 support, additional interrupts and error checking among other features. While in this mode, there is no hard requirement that the programming model is consistent with the legacy programming model; however where reasonable the same look and feel is accomplished. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1722 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.2.2 Functional Description This section provides the detailed functional description of the uDMA. The uDMA is a data mover between the FIFO interface and the bus master and vice-versa. Additionally, the uDMA is responsible for formatting the data being transferred into and out of buffer descriptors. Further, the uDMA is responsible for the generation of various control signals (that is, interrupts) that may occur during the process. The uDMA is the key link for enabling the legacy programming format of the FEC module to work with the ENETMAC. This section provides the technical details for the uDMA. Additional details required for legacy mode compatibility is provided in the FEC specification (FEC_BlockGuide.pdf). There are two FIFO interfaces, one for transmit and one for receive. Please refer to the documentation in the reference section for the detailed specification for these FIFO interfaces. 26.2.2.1 Legacy Buffer Descriptor Models Table 26-1 and Table 26-2 show the legacy buffer descriptor (LBD) models. 26.2.2.1.1 Legacy FEC Receive Buffer Descriptor This section discusses the legacy FEC receive buffer descriptors. Table 26-1. Legacy FEC Receive Buffer Descriptor Offset + 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E RO1 W RO2 L -- -- M BC MC LG NO -- CR OV TR Offset + 2 Data length Offset + 4 RX Data Buffer Pointer - A[31:16] Offset + 6 RX Data buffer Pointer - A[15:0] The following sections reference Table 26-1. 26.2.2.1.1.1 Bit-15 E Empty. Written by the uDMA (=0) and user (=1). The functionality and operation of this bit does not change from the FEC. The uDMA clears this bit to indicate that the buffer descriptor is complete and ready for the driver to process. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1723 Unified DMA Block Guide 26.2.2.1.1.2 Bit-14 RO1 26.2.2.1.1.3 Bit-13 W 26.2.2.1.1.4 Bit-12 RO2 26.2.2.1.1.5 Bit-11 L 26.2.2.1.1.6 Bit-10 and Bit 9 -- 26.2.2.1.1.7 Bit-8 M 26.2.2.1.1.8 Bit-7 BC 26.2.2.1.1.9 Bit-6 MC Receive software ownership. This field is reserved for use by software. This read/write bit will not be modified by hardware, nor will its value affect hardware. Wrap. Written by user. The functionality and operation of this bit does not change from the FEC. It indicates the next buffer descriptor the uDMA is supposed to use. If 0 the next buffer descriptor is found in the consecutive location, and if 1 the next buffer descriptor is found at the location defined in ERDSR. Receive software ownership.This field is reserved for use by software. This read/write bit will not be modified by hardware, nor will its value affect hardware. Last in frame. Written by the uDMA. Setting this bit to '1' indicates that the buffer descriptor is the last buffer descriptor in the frame. These bits are reserved and must not be modified. Miss. Written by the uDMA. This bit is set by the uDMA for frames accepted in promiscuous mode, but flagged as a miss by the internal address recognition. Therefore, while in promiscuous mode, the user can use the M-bit to quickly determine whether the frame was destined to this station. This bit is only valid if the L-bit is set and the PROM bit is set inside the ENET-MAC. If 0,the frame was received because of an address recognition hit. If 1, the frame was received because of promiscuous mode. This field is only valid if the BD is the last in the frame, that is, L-bit is set. Set if the DA is broadcast (FF-FF-FF-FF-FF-FF). Set if the DA is multicast and not BC. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1724 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.2.2.1.1.10 Bit-5 LG 26.2.2.1.1.11 Bit-4 NO 26.2.2.1.1.12 Bit-3 -- 26.2.2.1.1.13 Bit-2 CR 26.2.2.1.1.14 Bit-1 OV 26.2.2.1.1.15 Bit-0 TR 26.2.2.1.1.16 Data Length 26.2.2.1.1.17 RX Data Buffer Pointer - A[31:16] Rx frame length violation, written by the uDMA. A frame length greater than MAX_FL was recognized. This bit is valid only if the L-bit is set. The receive data is not altered in any way unless the length exceeds TRUNC_FL bytes. Receive non-octet aligned frame, written by the uDMA. A frame that contained a number of bits not divisible by 8 was received, and the CRC check that occurred at the preceding byte boundary generated an error or Phy error occurred. This bit is valid only if the L-bit is set. If this bit is set the CR bit will not be set. Reserved. Rx CRC or Rx Frame error, written by the uDMA. This frame contains a Frame with Phy error or CRC error and is an integral number of octets in length. This bit is valid only if the L-bit is set. Overrun, written by the uDMA. A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M, LG, NO, SH, CR, and CL lose their normal meaning and will be zero. This bit is valid only if the L-bit is set. Will be set if the receive frame is truncated (frame length > TRUNC_FL). If the TR bit is set, the frame should be discarded and the other error bits should be ignored as they may be incorrect. Data length. Written by the uDMA. Data length is the number of octets written by the uDMA into this BD's data section. If L equals 0, the value written will be equal to EMRBR. If L equals 1, complete length of the frame including the CRC. It is written by the uDMA once as the BD is closed. RX data buffer pointer, bits [31:16]. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1725 Unified DMA Block Guide 26.2.2.1.1.18 RX Data Buffer Pointer - A[15:0] RX data buffer pointer, bits [15:0]. The receive buffer pointer, which always points to the first location of the associated data buffer, must always be evenly divisible by 16. 26.2.2.1.2 Legacy FEC Transmit Buffer Descriptor This section discusses the legacy FEC transmit buffer descriptors. Table 26-2. Legacy FEC Transmit Buffer Descriptor Offset + 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TO1 W TO2 L TC ABC -- -- -- -- -- -- -- -- -- Offset + 2 Data length Offset + 4 TX Data Buffer Pointer A[31:16] Offset + 6 TX Data buffer Pointer A[15:0] The following sections reference Table 26-2. 26.2.2.1.2.1 Bit-15 R 26.2.2.1.2.2 Bit-14 TO1 26.2.2.1.2.3 Bit-13 W 26.2.2.1.2.4 Bit-12 TO2 26.2.2.1.2.5 Bit-11 L Ready. Written by the uDMA (=0) and the user (=1). It is set by the user to indicate the buffer descriptor is ready for transmission. The uDMA clears this bit at the start of data transmission. Transmit software ownership. This field is reserved for software use. This read/write bit will not be modified by hardware, nor will its value affect the hardware. Wrap. Written by user. The functionality and operation of this bit does not change from the FEC. * 0 The next buffer descriptor is found in the consecutive location. * 1 The next buffer descriptor is found at the location defined in ETDSR. Transmit software ownership. This field is reserved for software use. This read/write bit will not be modified by hardware, nor will its value affect hardware. Last in frame. Written by the user. The functionality and operation of this bit does not change from the FEC. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1726 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) * 0 The buffer descriptor is not the last in the transmit frame. * 1 The buffer descriptor is the last in the transmit frame. 26.2.2.1.2.6 Bit-10 TC Tx CRC. This bit is written by the user. If '0' this indicates that the frame is sent as-is and it is up to the software to provide a valid frame with CRC field. If '1' the MAC will calculate and append the CRC field to the frame. 26.2.2.1.2.7 Bit-9 ABC 26.2.2.1.2.8 Bit 8-0 -- 26.2.2.1.2.9 Data Length Append bad CRC. This bit is not supported in the uDMA legacy or enhanced modes and is ignored. These values are reserved and should not be modified. Datalength. Written by the user. The functionality and operation of this field does not change from the FEC. 26.2.2.1.2.10 TX Data Buffer Pointer A[31:16] 26.2.2.1.2.11 TX Data Buffer Pointer A[15:0] TX data buffer pointer. A[31:0] contains the address of the associated data buffer and must always be evenly divisible by 4. The functionality and operation of this field does not change from the FEC. TX data buffer pointer. The functionality and operation of this field does not change from the FEC. 26.2.2.2 Enhanced Buffer Descriptor Models In order to support various new functionality now available in the ENET-MAC the uDMA also supports an enhanced buffer descriptor model (EBD). Table 26-3 and Table 26-4 shows what is being referred to as the EBD models. To promote the maximum reuse of driver software where possible the LBD fields were reused. 26.2.2.2.1 Enhanced uDMA Receive Buffer Descriptor This section discusses the enhanced uDMA receive buffer descriptors. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1727 Unified DMA Block Guide Table 26-3. Enhanced uDMA Receive Buffer Descriptor Offset + 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E RO1 W RO2 L -- -- M BC MC LG NO -- CR OV TR -- -- -- -- -- Offset + 2 Data length Offset + 4 RX Data Buffer Pointer A[31:16] Offset + 6 RX Data buffer Pointer A[15:0] Offset + 8 ME -- -- -- -- PE CE UC INT -- Offset + A -- -- -- -- -- -- -- -- -- -- -- -- -- Offset + C Header Length Offset + E -- ICE PCR -- VLA FRA IPV6 N G Protocol Type Payload Checksum Offset + 10 BDU -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Offset + 12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Offset + 14 1588 Timestamp[31:16] Offset + 16 1588 Timestamp[15:0 Offset + 18 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Offset + 1A -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Offset + 1C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Offset + 1E -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 26.2.2.2.1.1 Offset + 0 Bit 15:0 26.2.2.2.1.2 Data Length 26.2.2.2.1.3 RX Data Buffer Pointer A[31:16] 26.2.2.2.1.4 RX Data Buffer Pointer A[15:0] This set of bits behaves exactly as in legacy mode with the exception of bit 15 E. See Legacy FEC Receive Buffer Descriptor. The Last Buffer Descriptor is already updated when bit E=0 and bit BDU=1. This field behaves exactly the same as in legacy mode. See Legacy FEC Receive Buffer Descriptor . This field behaves exactly the same as in legacy mode. See Legacy FEC Receive Buffer Descriptor. This field behaves exactly the same as in legacy mode. See Legacy FEC Receive Buffer Descriptor. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1728 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.2.2.2.1.5 Offset + 8 Bit 15 ME MAC error. This bit is written by the uDMA. This bit means that the frame stored in the system memory was received with an error. This bit is only valid when the L-bit is set. 26.2.2.2.1.6 Offset + 8 Bit 14 -- 26.2.2.2.1.7 Offset + 8 Bit 10 PE This bit is not used (reserved) since the uDMA aborts the operation when a DMA detects an error during the data transfer. PHY Error. This bit is written by the uDMA. Set to 1 when the frame was received with an Error character on the PHY interface. The frame is invalid. This bit is valid only when the L-bit is set. 26.2.2.2.1.8 Offset + 8 - Bit 9 CE Collision. This bit is written by the uDMA. Set to 1 when the frame was received with a collision detected during reception. The frame is invalid and sent to the user application. This bit is valid only when the L-bit is set. 26.2.2.2.1.9 Offset + 8 - Bit 8 UC Unicast. This bit is written by the uDMA. This bit means that the frame is unicast. This bit is valid regardless of if the L-bit is set. 26.2.2.2.1.10 Offset + 8 - Bit 7 INT 26.2.2.2.1.11 Offset + A - Bit 5 ICE Generate RXB/RXF interrupt. This bit is set by the user. This bit indicates that the uDMA is to generate an interrupt on the dma_int_rxb / dma_int_rxf event. IP header checksum error. This is an accelerator option. This bit is written by the uDMA. Set to 1 when either not an IP frame is received, or the IP header checksum was invalid. This bit is only valid if the L-bit is set. 26.2.2.2.1.12 Offset + A - Bit 4 PCR Protocol checksum error. This is an accelerator option. This bit is written by the uDMA. Set to 1 when the checksum of the protocol is invalid, or an unknown protocol is found and checksumming could not be performed. This bit is only valid if the L-bit is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1729 Unified DMA Block Guide 26.2.2.2.1.13 Offset + A - Bit 3 -- Type removed. This is an accelerator option. This bit is written by the uDMA. If set, this bit indicates that the frame's type feld has been removed: The frames payload starts immediately after the MAC source address within the frame, or after the VLAN tag if present. This bit is only valid if the L-bit is set. The date for this bit comes from the MTIP sideband signal ff_rx_ip_stat[7]. 26.2.2.2.1.14 Offset + A - Bit 2 VLAN VLAN. This is an accelerator option. This bit is written by the uDMA. This bit means that the frame has a VLAN tag. This bit is valid only if the L-bit is set. 26.2.2.2.1.15 Offset + A - Bit 1 IPV6 IPV6 Frame. This bit is written by the uDMA. This bit indicates that the frame has a IPv6 frame type. If this bit is not set, it means that an IPv4 or other protocol frame was received. This bit is valid only if the L-bit is set. 26.2.2.2.1.16 Offset + A - Bit 0 FRAG Pv4 Fragment.This is an accelerator option.This bit is written by the uDMA.This bit indicates that the frame is an IPv4 fragment frame. This bit is only valid when the L-bit is set. 26.2.2.2.1.17 Offset + C - Bit [15:11] Header Length Header length. This is an accelerator option. This field is written by the uDMA. This field is the sum of 32 bit words found within the IP and its following protocol headers. If an IP datagram with an unknown protocol is found, the value is the length of the IP header. If no IP frame or an erroneous IP header is found, the value is 0. The following values are minimum values if no header options exist in the respective headers: * ICMP/IP: 6 (5 IP header, 1 ICMP header) * UDP/IP: 7 (5 IP header, 2 UDP header) * TCP/IP: 10 (5 IP header, 5 TCP header) This field is only valid if the L-bit is set. 26.2.2.2.1.18 Offset + C - Bit [7:0] Protocol Type Protocol type. This is an accelerator option. The 8-Bit protocol field found within the IP header of the frame. Only valid if "ICE" bit is 0. This bit is only valid if the L-bit is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1730 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.2.2.2.1.19 Offset + E - Bit [15:0] Payload Checksum Internet payload checksum. This is an accelerator option. The one's complement sum of the payload section of the IP frame. The sum is calculated over all data following the IP header until the end of the IP payload. This field is valid only when the L-bit is set. 26.2.2.2.1.20 Offset + 0x10 - Bit 15 BDU 26.2.2.2.1.21 1588 Timestamp [31:0] Last Buffer Descriptor Update Done. This bit indicates that all the last BD data has been updated by uDMA. This bit is written by the user (=0) and uDMA (=1). It is only valid if the L-bit is set. 26.2.2.2.2 Enhanced uDMA Transmit Buffer Descriptor This section discusses the enhanced uDMA transmit buffer descriptors. Table 26-4. Enhanced uDMA Transmit Buffer Descriptor Offset + 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TO1 W TO2 L TC - - - - - - - - - - Offset + 2 Data length Offset + 4 TX Data Buffer Pointer - A[31:16] TX Data buffer Pointer - A[15:0] Offset + 6 Offset + 8 - Offset + A TXE INT TS PIN S IINS - UE EE - - - - - - - - - - - FE LCE OE TSE - - - - - - - - Offset + C - - - - - - - - - - - - - - - - Offset + E - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Offset + 10 BDU Offset + 12 - Offset + 14 1588 Timestamp [31:16] Offset + 16 1588 Timestamp [15:0] Offset + 18 - - - - - - - - - - - - - - - - Offset + 1A - - - - - - - - - - - - - - - - Offset + 1C - - - - - - - - - - - - - - - - Offset + 1E - - - - - - - - - - - - - - - - The following sections reference Table 26-4. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1731 Unified DMA Block Guide 26.2.2.2.2.1 Offset + 0 - Bit 15:0 26.2.2.2.2.2 Offset + 2 - Data Length 26.2.2.2.2.3 Offset + 4 and Offset + 6 - TX Data Buffer Pointer 26.2.2.2.2.4 Offset + 8 Bit 15 "-" 26.2.2.2.2.5 Offset + 8 Bit 14 "INT" 26.2.2.2.2.6 Offset + 8 Bit 13 "TS" This functionality does not change from the legacy programming model with the exception of bit 9 "ABC" which has been explicitly removed and bit 15 "R". See Legacy FEC Transmit Buffer Descriptor. This functionality does not change from the legacy programming model. See Legacy FEC Transmit Buffer Descriptor . This functionality does not change from the legacy programming model. See Legacy FEC Transmit Buffer Descriptor. Error Indication. This bit is written by the user. This bit is used by the application software to indicate that the frame stored in the system memory contains an error. This bit is valid regardless of if the L-bit is set and must be the same for all EBD for a given frame. The uDMA does not update this value. Generate interrupt. This bit is written by the user. This indicates that the uDMA is to generate a dma_int_txb / dma_int_txf interrupt in relation to this frame / buffer descriptor. This bit is valid regardless of if the L-bit is set and must be the same for all EBD for a given frame. The uDMA does not update this value. Timestamp. This bit is written by the user. This indicates that the uDMA is to generate a timestamp frame. This bit is valid regardless of if the L-bit is set and must be the same for all EBD for the given frame. The uDMA does not update this value. 26.2.2.2.2.7 Offset + 8 Bit 12 "PINS" Insert protocol specifc checksum. This bit is written by the user. If '1' the MAC's IP accelerator calculates the protocol checksum and overwrites the corresponding checksum feld with the calculated value. The checksum feld must be set to 0 by the application generating the frame. The uDMA does not update this value. This bit is valid regardless of if the L-bit is set and must be the same for all EBD for a given frame. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1732 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.2.2.2.2.8 Offset + 8 Bit 11 "IINS" Insert IP header checksum. This bit is written by the user. If '1' the MAC's IP accelerator calculates the IP header checksum and overwrites the corresponding header feld with the calculated value. The checksum feld must be set to 0 by the application generating the frame. The uDMA does not update this value. This bit is valid regardless of if the L-bit is set and must be the same for all EBD for a given frame. 26.2.2.2.2.9 Offset + A Bit 15 "TXE" 26.2.2.2.2.10 Offset + A Bit 14 "-" 26.2.2.2.2.11 Offset + A Bit 13 "UE" Transmit error occurred. This bit is written by the uDMA. This bit indicates that there was a transmit error reported with the frame. Effectively this bit is the "or" of all other error bits including UE, EE, FE, LCE, OE, and TSE. This bit is only valid when the L-bit is set. This bit is not used (reserved) since the uDMA will abort the operation when a DMA detects an error during the data transfer. Underflow error. This bit is written by the uDMA. This bit indicates that the MAC reported an underfow error on transmit. 26.2.2.2.2.12 Offset + A Bit 12 "EE" Excess Collision error. This bit is written by the uDMA. This bit indicates that the MAC reported an excess collision error on transmit. This bit is only valid when the L-bit is set. 26.2.2.2.2.13 Offset + A Bit 11 "FE" Frame with error. This bit is written by the uDMA. This bit indicates that the MAC reported that the uDMA reported an error when providing the packet. This bit is only valid when the L-bit is set. 26.2.2.2.2.14 Offset + A Bit 10 "LCE" Late collision error. This bit is written by the uDMA. This bit indicates that the MAC reported that there was a Late Collision on transmit. This bit is only valid when the L-bit is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1733 Ethernet ENET-MAC Core 26.2.2.2.2.15 Offset + A Bit 9 "OE" Overfow error. This bit is written by the uDMA. This bit indicates that the MAC reported that there was a FIFO overfow condition on transmit. This bit is only valid when the L-bit is set. 26.2.2.2.2.16 Offset + A Bit 8 "TSE" Timestamp error. This bit is written by the uDMA. This bit indicates that the MAC reported a different frame type then a timestamp frame. This bit is only valid when the Lbit is set. 26.2.2.2.2.17 Offset + 0x10 - Bit 15 "BDU" 26.2.2.2.2.18 1588 Timestamp [31:0] Last Buffer Descriptor Update Done. This bit indicates that all the last BD data has been updated by uDMA. This bit is written by the user (=0) and uDMA (=1). This value is written by the uDMA when switch is in Bypass mode. It is only valid if the L-bit is set. 26.3 Ethernet ENET-MAC Core This section describes the ENET-MAC core, including the block diagram and formats. 26.3.1 Introduction Ethernet is available in different speeds (10/100 Mbps) and provides connectivity to meet a wide range of needs and from desktop to switches. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1734 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 10GbEth 1GbEth Access switch Backone switch 1GbEth Work group Switch 100MbEth 1GbEth Work group Switch 100MbEth 100MbEth 10MbEth Desktop (Wiring Closet) Figure 26-3. Enterprise LAN Topology Example The ENET-MAC Core implements, in conjunction with a dual-speed 10/100 MAC, Layer 3 network acceleration functions, which are designed to accelerate the processing of various common networking protocols such as IP, TCP, UDP and ICMP providing wire speed services to Client applications. The Core implements a dual speed 10/100 Mbps Ethernet MAC compliant with the IEEE802.3-2002 standard. The MAC layer provides compatibility with Half or Full Duplex 10/100 Mbps Ethernet and Fast Ethernet LANs. The MAC operation is fully programmable and can be used in NIC (Network Interface Card), bridging or switching applications. The Core implements the Remote Network Monitoring (RMON) counters according to IETF RFC 2819. All registers are accessible through a 32-Bit APB interface. The Core also implements a Hardware acceleration block to optimize the performance of network controllers providing IP and TCP, UDP, ICMP protocol services. The acceleration block performs, in hardware, critical functions, which are typically implemented with large software overhead. The Core implements programmable embedded FIFOs that can provide, on the Receive path, buffering for loss-less flow control. Advanced Power Management features are available with Magic Packet detection and programmable power down modes. For industrial automation application, the IEEE 1588 standard is becoming the main technology for precise time synchronization on Ethernet networks providing accurate clock synchronization for distributed control nodes to overcome one of the drawbacks of Ethernet. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1735 10 100Mbps Ethernet ENET-MAC Core Features The programmable 10/100 Ethernet MAC with IEEE 1588 support integrates a standard IEEE 802.3 Ethernet MAC with a time stamping module to support Ethernet applications requiring precise timing references for incoming and outgoing frames to implement a distributed time synchronization protocol such as the IEEE 1588. 26.3.2 10 100Mbps Ethernet ENET-MAC Core Features 26.3.2.1 Ethernet MAC Features * Implements the full 802.3 specification with preamble / SFD generation, frame padding generation, CRC generation and checking * Dynamically configurable to support 10 Mbps and 100 Mbps operation * Supports full duplex and configurable half duplex operation * Supports AMD Magic Packet detection with interrupt for node remote power management * Seamless interface to commercial Fast Ethernet PHY device through a 4-Bit Media Independent Interface (MII) operating at 25MHz * Simple 64-Bit FIFO interface to user application * CRC-32 checking at full speed with optional forwarding of the FCS field to client * CRC-32 generation and append on transmit or forwarding of user application provided FCS selectable on a per-frame basis * When operating in Full Duplex mode, implements automated Pause Frame (802.3 x31A) generation and termination providing flow control without user application intervention * When operating in full duplex mode, pause quanta used to form Pause frames, dynamically programmable * Pause frame generation additionally controllable by user application offering flexible traffic flow control * Optional forwarding of received pause frames to the user application when operating in Full Duplex mode * Implements standard flow-control mechanism in full-duplex operation mode * In half-duplex mode, provides full collision support, including jamming, backoff, and automatic retransmission i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1736 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) * Support for VLAN tagged frames according to IEEE 802.1Q * Programmable MAC address: Insertion on transmit; discards frames with mismatching destination address on receive (except broadcast and pause frames) * Programmable group of four supplemental MAC addresses that can be used to filter Unicast traffic * Programmable Promiscuous mode support to omit MAC destination address checking on receive * Multicast and Unicast address filtering on receive based on 64 entries hash table reducing higher layer processing load * Programmable frame maximum length providing support for any standard or proprietary frame length * Statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames providing for IEEE 802.3 basic and mandatory Management Information Database (MIB) package and Remote Network Monitoring (RFC 2819) * Simple handshake user application FIFO interface with fully programmable depth and threshold levels ensuring data rates of 1Gbps * 64-Bit Client FIFO interface * Separate status word available for each received frame on the user interface providing information such as frame length, frame type, VLAN tag and error information * Multiple internal loopback options * MDIO Master interface for PHY device configuration and management with two programmable MDIO base addresses 26.3.2.2 IP Protocol Performance Optimization Features * Operates on TCP/IP and UDP/IP and ICMP/IP protocol data or IP header only * Enables wire-speed processing * IPv4 and IPv6 support * Transparent passing of frames of other types and protocols * Support for VLAN tagged frames according to IEEE 802.1q with transparent forwarding of VLAN tag and control field i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1737 10 100Mbps Ethernet ENET-MAC Core Features * Automatic IP-header and payload (protocol specific) checksum calculation and verification on receive * Automatic IP-header and payload (protocol specific) checksum generation and automatic insertion on transmit configurable on a per-frame basis * Support for IP and TCP, UDP, ICMP data for checksum generation and checking * Full header options support for IPv4 and TCP protocol headers * IPv6 support limited to datagrams with base header only. Datagrams with extension headers are passed transparently unmodifed/unchecked * Statistics information for received IP and protocol errors * Configurable automatic discard of erroneous frames * Configurable automatic Host-to-Network (RX) and Network-to-Host (TX) byte order conversion for IP and TCP/UDP/ICMP headers within the frame * Configurable padding remove for short IP datagrams on receive * Configurable Ethernet Payload alignment to allow for 32-bit word aligned header and payload processing * Programmable Store & Forward operation with clock and rate decoupling FIFOs 26.3.2.3 IEEE 1588 Functions * Support for all IEEE 1588 Frames * Reference Clock can be chosen independently of the Network speed * Software Programmable Precise Time-Stamping of Ingress Frames and Egress Frames * Timer monitoring capabilities for System calibration and timing accuracy management * Precise time stamping of external events with programmable interrupt generation * Programmable event and interrupt generation for external system control * Hardware and Software controllable timer synchronization i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1738 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.3 ENET-MAC Core Block Diagram Receive Application Interface Receive FIFO RX Control TCP-IP Performance Optimization Transmit Application Interface CRC Check Transmit FIFO Pause Frame Terminate TX Control TCP-IP Performance Optimization CRC Gen MDIO Master PHY Management Interface Configuration Satistics Pause Frame Generate GMII/SERDES GMII/SERDES MII/SERDES MII/SERDES Receve Interface Receve Interface Transmit Interface Transmit Interface MAC TOE Functions Register Interface Figure 26-4. ENET-MAC Core Overview 26.3.4 Ethernet MAC Frame Formats 26.3.4.1 Overview The IEEE 802.3 Standard defines the Ethernet frame format as follows: An Ethernet frame has a minimum length of 64 bytes and a maximum length of 1518 bytes or more if jumbo frames are supported, excluding the preamble and the start frame delimiter bytes. An Ethernet frame consists of the following fields: * Seven bytes preamble * Start frame delimiter (SFD) * Two address fields * Length or type field i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1739 Ethernet MAC Frame Formats * Data field * Frame check sequence (CRC value) * An EXTENSION field is defined only for gigabit Ethernet half-duplex implementations and is not supported by the MAC core Frame length 7 octets PREAMBLE 1 octet SFD 6 octets DESTINATION ADDRESS 6 octets SOURCE ADDRESS 2 octets LENGTH/TYPE 0..1500/9000 octets 0..46 octets Payload length PAYLOAD DATA PAD FRAME CHECK SEQUENCE 4 octets EXTENSION (half dup only) Figure 26-5. MAC Frame Format Overview Optionally MAC frames can be VLAN-tagged with an additional 4-byte field (VLAN Tag and VLAN Info) inserted between the MAC source address and the Type/Length Field. VLAN tagging is defined by the IEEE P802.1q specification. VLAN tagged frames have a maximum length of 1522 bytes, excluding the preamble and the SFD bytes. Frame length 7 octets 1 octet 6 octets 6 octets 2 octets 2 octets 2 octets PREAMBLE SFD DESTINATION ADDRESS SOURCE ADDRESS VLAN Tag (0x8100) VLAN info LENGTH/TYPE 0..1500/9000 octets 0..42 octets 4 octets lengthtype field Payload length PAYLOAD DATA PAD FRAME CHECK SEQUENCE EXTENSION (half dup only) Figure 26-6. VLAN Tagged MAC Frame Format Overview Table 26-5. MAC Frame Definition Term Description Frame length The length, in octets, defines the length of the complete Frame without preamble and SFD. A frame has a valid length if it contains at least 64 octets and does not exceed the programmed maximum length (typical 1518). Payload Length The length / type field indicates the length of the frame's payload section. The most significant byte is sent/received first. If the Length/type field is set to a value lower than 46, the payload is padded so that the minimum frame length requirement (64 Bytes) is met. For VLAN tagged frames, a value less than 42 indicates a padded frame. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1740 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) Table 26-5. MAC Frame Definition (continued) Term Description If the Length/type field is set to a value larger than the programmed frame maximum length (e.g. 1518) it is interpreted as a type field. Destination and Source 48-bit MAC addresses. The least significant byte is sent/received first and the two first bits (two least Address significant bits) of the MAC address are used to distinguish MAC frames. Note Although the IEEE specification defines a maximum frame length, the MAC core provides the flexibility to program any value for the frame maximum length. 26.3.4.2 Pause Frames A Pause Frame is generated by the receiving device to indicate a congestion to the emitting device which should stop sending data. Pause Frames are indicated by the Length/Type set to 0x8808. The two first bytes of a Pause Frame following the type, defines a 16-Bit opcode field set to 0x0001 always. A 16-Bit Pause Quanta is defined in the Frame payload Bytes 2 (Byte P1) and 3 (Byte P2) as defined in Table 26-6. The pause quanta byte P1 is the most significant. Table 26-6. Pause Frame Format (values in hex) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 55 55 55 55 55 55 55 D5 01 80 C2 00 00 01 15 16 17 18 19 20 21 22 23 24 25 26 27-68 00 00 00 00 00 00 88 08 00 01 hi lo 00 P1 P2 pad (42) Preamble Source Address 69 70 71 72 26 6B AE 0A SFD Type Multicast Destination Address Opcode CRC-32 There is no Payload Length field found within a Pause Frame and a Pause Frame is always padded with 42 bytes (0x00). If a pause frame with a pause value greater zero (XOFF Condition) is received, the MAC stops transmitting data as soon the current Frame transfer is completed. The MAC stops transmitting data for the value defined in pause quanta. One pause quanta fraction refers to 512 bit times. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1741 IP and Higher Layers Frame Format If a pause frame with a pause value of zero (XON Condition) is received, the transmitter is allowed to send data immediately (See chapter 10 for details). 26.3.4.3 Magic Packets A Magic Packet can be a Unicast, Multicast or Broadcast packet, which carries a defined sequence in the payload section. Magic Packet are received and inspected only under specific conditions as described in Magic Packet Detection The defined sequence used to decode a Magic Packet is formed with a synchronization stream (Six consecutive 0xFF bytes) followed by a sequence of six consecutive Unicast MAC addresses (The Unicast Address of the Node to be awakened). The sequence can be located anywhere in the Magic Packet payload and the Magic Packet is formed with standard Ethernet header optional padding and CRC. 26.3.5 IP and Higher Layers Frame Format 26.3.5.1 Definitions The following chapters use the term datagram to describe the protocol specific data unit, which is found within the payload section of its container entity. For example, an IP datagram specifies the payload section of an Ethernet frame. A TCP datagram specifies the payload section within an IP datagram. 26.3.5.2 Ethernet Types IP datagrams are carried in the payload section of an Ethernet frame. The Ethernet frame type/length field is used to discriminate several datagram types. The following table lists the types of interest: Table 26-7. Ethernet Type Value Examples Type Description 0x8100 VLAN tagged frame. The actual type is found 4 octets later in the frame 0x0800 IP 0x0806 ARP 0x86dd IPv6 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1742 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.5.3 IPv4 Datagram Format The following Figure 6 shows the IP Version 4 (IPv4) header, which is located at the beginning of an IP datagram. It is organized in 32-bit words. The most significant bit is bit 31 in the following figure. The first byte sent/received is the leftmost byte of the first word (that is, Version/IHL field). The IP Header can contain further options, which are always padded if necessary, to guarantee the payload following the header is aligned to a 32-bit boundary. The IP header is followed by the payload immediately, which can contain further protocol headers like for example, TCP or UDP as indicated by the protocol field value. The complete IP datagram is transported in the payload section of an Ethernet frame. 3 1 2 7 Vers 2 3 IHL 1 9 1 5 TOS 7 3 0 length fragment ID TTL 1 1 flags protocol fragment offset header checksum source address destination address options Figure 26-7. IPv4 Header Format Table 26-8. IPv4 Header Fields Field Name Description Vers 4-bit IP version information. It is 4 for IPv4 frames IHL 4-bit internet header length information. Determines number of 32-bit words found within the IP header. The default value, if no options are present is 5 TOS Type of Service / DiffServ field length Total length of the datagram in bytes. It includes all octets of header and payload fragment ID, flags, fragment offset Fields used for IP fragmentation TTL Time-to-live. If zero, datagram must be discarded protocol Protocol Identifier of protocol that follows in the datagram header checksum Checksum over all IP header fields source address Source IP address destination address Destination IP address i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1743 IP and Higher Layers Frame Format 26.3.5.4 IPv6 Datagram Format Figure 26-8 shows the IP Version 6 (IPv6) header, which is located at the beginning of an IP datagram. It is organized in 32-bit words and has a fixed length of 10 words (40 byte). The next header field identifies the type of the header to follow the IPv6 header. It is defined identical to the protocol identifier within IPv4 with new definitions for identifying so-called extension headers, which can be inserted between the IPv6 header and the protocol header, shifting the protocol header accordingly. The accelerator currently only supports IPv6 without extension headers (that is, next header identifies TCP or UDP or ICMP protocol). The most significant bit is bit 31 in the following figure. The first byte sent/received is the leftmost byte of the first word (that is, Version/Traffic class fields). 3 1 2 7 Vers TrafficClass 2 3 1 9 payload length 1 5 1 1 7 3 0 folowlable next header hop limit source address destination address start of next header / payload Figure 26-8. IPv6 Header Format Table 26-9. IPv6 Header Fields Field Name Description Vers 4-bit IP version information. It is 6 for all IPv6 frames Traffic Class 8-bit field defining the traffic class flow label 20-bit flow label identifying frames of the same flow payload length 16-Bit Length of the datagram payload (!) in bytes. It includes all octets following the IPv6 header. next header Identifies the header that follows the IPv6 header. This can be the protocol header or any IPv6 defined extension header. hop limit Hop counter, decremented by 1 by each station that forwards the frame. If hop limit is 0 the frame must be discarded. source address 128-bit IPv6 source address destination address 128-bit IPv6 destination address i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1744 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.5.5 ICMP Datagram Format Following the IP Header, an Internet Control Message Protocol (ICMP) datagram is found when the protocol identifier has a decimal value of 1. The ICMP datagram has 4 octets header followed by the additional message data. 3 1 2 7 2 3 type 1 9 1 5 code 1 1 7 3 0 checksum icmp message data Figure 26-9. ICMP Header Format Table 26-10. IP Header Fields Field Name Description type 8-bit type information code 8-bit code that is related to the message type checksum 16-bit one's complement checksum over the complete ICMP datagram 26.3.5.6 UDP Datagram Format Following the IP Header, a user datagram protocol header is found when the protocol identifier has a decimal value of 17. Following the UDP header is the payload of the datagram. The header byte order follows the conventions given for the IP header above. 3 1 2 7 2 3 1 9 1 5 1 1 7 3 source port destination port length checksum 0 Figure 26-10. UDP Header Format Table 26-11. UDP Header Fields Field Name Description source port Source application port destination port Destination application port length Length of user data which follows immediately the header including the UDP header. That is, the minimum value is 8. checksum Checksum over the complete datagram and some IP header information i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1745 IP and Higher Layers Frame Format 26.3.5.7 TCP Datagram Format Following the IP Header, a TCP header is found when the protocol identifier has a decimal value of 6. The TCP payload follows immediately the TCP header. 2 7 3 1 2 3 1 9 1 5 1 1 7 3 0 destination port source port sequence number acknowledgment number offs reserved flags window checksum urgent pointer options Figure 26-11. TCP Header Format Table 26-12. TCP Header Fields Field Name Description source port Source application port destination port Destination application port sequence number Transmit sequence number ack. number Receive sequence number offs Data offset. Number of 32-bit words within the TCP header. If no options, a value of 5. flags URG, ACK, PSH, RST, SYN, FIN flags window TCP receive window size information checksum Checksum over the complete datagram (TCP Header and data) and IP header information options Additional 32-bit words for protocol options i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1746 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.6 IEEE 1588 Message Formats 26.3.6.1 Transport Encapsulation The Precision-Time-Protocol (PTP) datagrams are encapsulated in Ethernet frames using the UDP/IP transport mechanism, or, optionally, with the newer 1588v2 directly in Ethernet frames (Layer 2). Typically multicast addresses are used to allow efficient distribution of the synchronization messages. 26.3.6.1.1 UDP/IP The 1588 messages (v1 and v2) can be transported using UDP/IP multicast messages. The following IP multicast groups are defined for PTP. The table also shows their respective MAC layer multicast address mapping according to RFC 1112 (last 3 octets of IP follow the fixed value of 01-00-5e). Table 26-13. UDP/IP Multicast Domains Name IP Address MAC Address mapping DefaultPTPdomain 224.0.1.129 01-00-5e-00-01-81 AlternatePTPdomain1 224.0.1.130 01-00-5e-00-01-82 AlternatePTPdomain2 224.0.1.131 01-00-5e-00-01-83 AlternatePTPdomain3 224.0.1.132 01-00-5e-00-01-84 Table 26-14. UDP Portnumbers Message Type UDP Port Note event 319 Used for SYNC and DELAY_REQUEST messages general 320 All other messages (for example, follow-up, delay-response) 26.3.6.1.2 Native Ethernet (PTPv2) In addition to the usage of UDP/IP frames, IEEE 1588v2 defines a native Ethernet frame format that uses ethertype=0x88f7. The payload of the Ethernet frame immediately contains the PTP datagram, starting with the PTPv2 header. Beside others, version 2 adds a peer delay mechanism to allow delay measurements between individual point-to-point links along a path over multiple nodes. The following multicast domains are additionally defined in PTPv2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1747 IEEE 1588 Message Formats Table 26-15. PTPv2 Multicast Domains Name MAC Address Normal messages 01-1b-19-00-00-00 peer delay messages 01-80-c2-00-00-0e 26.3.6.2 PTP Header All PTP frames contain a common header, which is used to determine the protocol version as well as the type of message, which defines the further content of the message. All multi-octet fields are transmitted in big-endian order meaning, the most significant byte is transmitted/received first. The version field's (versionPTP) last four bits are at the same position (that is, 2nd byte) for both PTPv1 and PTPv2 headers, allowing a correct identification by inspecting the first two bytes of the message. 26.3.6.2.1 PTPv1 Header Table 26-16. Common PTPv1 message header Bits 7 6 5 Octets Offset versionPTP = 0x0001 2 0 versionNetwork 2 2 subdomain 16 4 4 3 2 1 0 messageType 1 20 sourceCommunicationTechnology 1 21 sourceUuid 6 22 sourcePortId 2 28 sequenceId 2 30 control 1 32 0x00 1 33 flags 2 34 reserved 4 36 The type of message is encoded in the fields messageType and control as follows: Table 26-17. PTPv1 Message Type Identification messageType control Message Name Message 0x01 0 SYNC event message Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1748 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) Table 26-17. PTPv1 Message Type Identification (continued) messageType control Message Name Message 0x01 1 DELAY_REQ event message 0x02 2 FOLLOW_UP general message 0x02 3 DELAY_RESP general message 0x02 4 MANAGEMENT general message other other reserved The field sequenceId is used to non-ambiguously identify a message. 26.3.6.2.2 PTPv2 Header Table 26-18. Common PTPv2 message Header Bits 7 6 5 4 3 2 1 Octets Offset 0 transportSpecific messageId 1 0 reserved versionPTP = 0x2 1 1 messageLength 2 2 domainNumber 1 4 reserved 1 5 flags 2 6 correctionField 8 8 reserved 4 16 sourcePortIdentity 10 20 sequenceId 2 30 control 1 32 logMeanMessageInterval 1 33 The type of message is encoded in the field messageId which is as follows: Table 26-19. PTPv2 Message Type Identification messageId Message Name Message 0x0 SYNC event message 0x1 DELAY_REQ event message 0x2 PATH_DELAY_REQ event message 0x3 PATH_DELAY_RESP event message 0x8 FOLLOW_UP general message 0x9 DELAY_RESP general message 0xa PATH_DELAY_FOLLOW_UP general message 0x4 - 0x7 reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1749 MAC Receive Table 26-19. PTPv2 Message Type Identification (continued) messageId Message Name Message 0xb ANNOUNCE general message 0xc SIGNALING general message 0xd MANAGEMENT general message The PTPv2 flags field contains further details on the type of message, especially if onestep or two-step implementations are used. The flags field consists of two octets with the following meanings for the bits. Reserved bits are set to 0 (false). Table 26-20. PTPv2 Message Flags Field Definitions Octet Offset bit Name Description 6 (first) 0 ALTERNATE_MASTER See IEEE 1588 Clause 17.4 1 TWO_STEP True (1) for two-step clock False (0) for one-step clock 2 UNICAST 3 reserved 4 reserved 5 profile specific 6 profile specific 7 reserved True (1) if transport layer address uses a unicast destination address, false (0) if multicast is used. 26.3.7 MAC Receive 26.3.7.1 Overview The MAC receive engine performs the following tasks: * Check Frame Framing * Remove Frame preamble and Frame SFD field * Frame Discarding based on Frame Destination address field * Terminate Pause Frames * Check Frame Length * Remove payload padding if it exists i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1750 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) * Calculate and verify CRC-32 * Write received Frames in the Core receive FIFO In the MAC is programmed to operate in half duplex mode, the MAC performed the following additional action: * Check if the frame is received with a collision discard Detect Preamble discard Collision Half Duplex only discard Compare Destination Address with locol/multicast/broadcast discard discriminate length/type information receive payload remove padding verify CRC verify frame length write data FIFO and frame status Figure 26-12. MAC Receive Flow 26.3.7.2 Collision Detection in Half Duplex Mode If the packet is received with a collision detected during the reception of the first 64 bytes, the packet is discarded (if frame size was less than ~14 octets) or transmitted to the user application with an error and status bit ff_rx_err_stat(24) set to '1'. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1751 MAC Address Check 26.3.7.3 Preamble Processing The IEEE 802.3 Standard allows a maximum size of 56 bits (7 bytes) for the preamble, while the MAC Core allows any arbitrary preamble length. The MAC Core checks for the start frame delimiter (SFD) byte. If the next byte of the preamble, which is different from 0x55, is not 0xD5, the frame will be discarded. Although the IEEE specification specifies that Frames should be separated at least by 96 bit (Inter Packet Gap or IPG), the MAC Core is designed to accept frames only separated by 64 MII (10/100Mbps operation) bits. The MAC Core removes all the preamble bytes and the SFD byte. 26.3.7.4 MAC Address Check 26.3.7.4.1 Overview The destination address bit 0 is used to differentiate Multicast and Unicast Addresses: * If bit 0 is set '0' the MAC address is an individual (Unicast) address. * If bit 0 is set '1' the MAC address defines a group address (Multicast Address). * If all 48 bits of the MAC address are set to '1' it indicates a Broadcast address. 26.3.7.4.2 Unicast Address Check If a Unicast address is received, the destination MAC address is compared to the Node MAC address programmed by the host in the registers PADDR1/PADDR2. In addition, it is compared to the supplemental MAC addresses programmed in the registers SMAC_0_0/SMAC_0_1, SMAC_1_0/SMAC_1_1, SMAC_2_0/SMAC_2_1 and SMAC_3_0/SMAC_3_1. If the destination address matches any of the programmed MAC addresses, the frame is accepted. If only one MAC address is required, all the supplemental MAC addresses should be programmed with the Node MAC address. If promiscuous mode is enabled (configuration register RCR(PROM) set to '1' ) no address checking is performed and all Unicast frames are accepted. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1752 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.7.4.3 Multicast and Unicast Address Resolution The hash table algorithm used in the group and individual hash filtering operates as follows. The 48-bit destination address is mapped into one of 64 bits, represented by 64 bits stored in GAUR, GALR (group address hash match), or IAUR, IALR (individual address hash match). This mapping is performed by passing the 48-bit address through the on-chip 32 bit CRC generator and selecting the six most significant bits of the CRCencoded result to generate a number between 0 and 63. The msb of the CRC result selects GAUR (msb equals 1) or GALR (msb equals 0). The least significant five bits of the hash result select the bit within the selected register. If the CRC generator selects a bit set in the hash table, the frame is accepted; otherwise, it is rejected. For example, if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from reaching memory. Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. The effectiveness of the hash table declines as the number of addresses increases. The user must initialize the hash table registers. Use this CRC32 polynomial to compute the hash: * FCS(X) = X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X 4 +X 2 +X 1 +1 If promiscuous mode is enabled (Configuration register bit PROM set to '1'), all Unicast and all Multicast frames are accepted regardless of GAUR / GALR and IAUR / IALR settings. 26.3.7.4.4 Broadcast Address Reject All Broadcast Frames are accepted if the register bit BC_REJ is set to '0' or if the register bit PROM is set to '1'. If PROM is set to '0' when BC_REJ set to '1', all Broadcast Frames are rejected. Table 26-21. Broadcast Address Reject Programming PROM BC_REJ Broadcast Frames 0 0 Accepted 0 1 Rejected 1 0 Accepted 1 1 Accepted i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1753 Frame Length Type Verification 26.3.7.4.5 Miss-Bit Implementation For higher layer filtering purposes, the receive FIFO interface provides a status bit (ff_rx_err_stat[26]) indicating an address miss when the MAC operates in promiscuous mode and accepted a frame that would otherwise be rejected. If neither a hash match (group or individual) nor an exact match (group or individual) occur, and if promiscuous mode is enabled (RCR[PROM] equals 1), the frame is accepted and the MISS bit is set; otherwise, the frame is rejected. This means the status bit is set in any of the following conditions during promiscuous mode: * BC_REJ=1. A broadcast frame is received in promiscuous mode while broadcast reject is set. * A unicast is received that does not match with any of the following: * PADDR1/ 2 (Node address, PALR/PAUR) * SMAC_0/1/2/3 (supplemental unicast addresses) * IADDR1/2 hash table entries (hash table for unicast, IALR/IAUR) * A multicast is received that does not match the GADDR1/2 hash table entries (GALR/IAUR) 26.3.7.5 Frame Length Type Verification 26.3.7.5.1 Payload Length Check If the Length / Type has a value lower than 0x600 and if the register bit NO_LGTH_CHECK is configured to perform the check, the MAC checks the payload length and reports any error in the frame status word (Bit 1 of Core signal ff_rx_err_stat(0) and interrupt bit PLR). If the Length / Type field has a value greater or equal 0x600, the MAC interprets the field as a type and no payload length check is performed. The length check is performed on VLAN and stacked VLAN frames. If a padded frame is received, no length check can be performed due to the extended frame payload (that is, padded frames never can have a payload length error). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1754 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.7.5.2 Frame Length Check When the receive frame length exceeds MAX_FL bytes, the BABR interrupt bit is generated. The LG register bit and ff_rx_err_stat(1) are set to '1'. The frame is not truncated unless the frame length exceeds the value programmed in TRUNC_FL. If the frame is truncated, ff_rx_err_stat(2) is set to '1'. In addition, a truncated frame will always have the CRC error indication set (ff_rx_err_stat(3)). 26.3.7.6 VLAN Frames Processing VLAN frames have a Length / Type field set to 0x8100 immediately followed by a 16Bit VLAN Control Information field. VLAN tagged frames are received as normal frames (VLAN Tag not interpreted by the MAC function) and are completely (Including the VLAN tag) pushed to the user application. If the length/type field of the VLAN tagged frame, which is found four octets later in the frame is less than 42, padding will be removed. In addition, the frame status word (Core signal ff_rx_err_stat(7)) indicates that the current frame is VLAN tagged. 26.3.7.7 Pause Frame Termination Pause frames are terminated within the receive engine and not transferred to the receive FIFO. The Quanta is extracted and sent to the MAC Transmit path through a small internal Clock Rate decoupling asynchronous FIFO. The Quanta is written only if a correct CRC and a correct frame length are detected by the control state machine. If not, the Quanta is discarded and the MAC Transmit path is not paused. Good Pause Frames are ignored if the register bit FCE is set to '0' and are forwarded to the Client interface when register bit PAUSE_FWD is set to '1'. 26.3.7.8 CRC Check The CRC-32 field is checked and is forwarded to the Core FIFO interface if the Core configuration registers CRC_FWD and PAD_EN are set to '0' and '1' respectively. When the Core register CRC_FWD is set to '1' (Regardless of PAD_EN register value), the CRC-32 field is checked and terminated (Not transmitted to the Core FIFO). The CRC polynomial, as specified in the 802.3 Standard, is as follows: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1755 MAC Transmit * FCS(X) = X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X 4 +X 2 +X 1 +1 The 32 bits of the CRC value are placed in the FCS field so that the X31 term is the rightmost bit of the first octet. The CRC bits are thus received in the following order: X31, X30,..., X1, X0. If a CRC error is detected, the frame is marked invalid and ff_rx_err_stat(3) is set AE1O. 26.3.7.9 Frame Padding Remove When a frame is received with a Payload length field set to lower than 46 (42 for VLAN tagged and 38 for frames with stacked VLANs) the '0' padding can be optionally removed before the Frame is written into the data FIFO as configured by the configuration bit PAD_EN. Note If a frame is received with excess padding (that is, length field as mentioned above, but frame has more than 64 octets) and padding removal is enabled, the padding is removed as normal and no error is caused if the frame is otherwise correct (for example, good CRC and less maximum length and no other error). 26.3.8 MAC Transmit 26.3.8.1 Overview Frame transmission starts when the Transmit FIFO holds enough data. Once a transfer has started, the MAC transmit function performs the following tasks: * Generate Preamble and SFD field before Frame transmission. * Generate XOFF pause frames if the Receive FIFO reports a congestion or if register TFC_PAUSE signal is asserted with PAUSE_DUR set to a non zero value. * Generate XON pause frames if the Receive FIFO congestion condition is cleared or if register TFC_PAUSE signal is asserted with PAUSE_DUR set to 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1756 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) * Suspend Ethernet Frame transfer (XOFF) if a non zero Pause Quanta is received from the MAC receive path. * Add padding to the frame if required. * Calculate and append CRC-32 to the transmitted frame. * Send Frame with correct Inter Packet Gap (IPG) (Deferring). When the MAC is configured to operate in Half Duplex mode, the following additional tasks are performed: * Collision detection * Frame retransmit after back-off timer has expired Send Preamble Send Destination Address send local MAC address (overwrite FIFO data) send payload send padding (if necessary) send CRC Figure 26-13. Frame Transmit Overview 26.3.8.2 Frame Payload Padding The IEEE specification defines a minimum frame length of 64 bytes. If the frame sent to the MAC from the user application has a size smaller than 60 bytes, the MAC automatically adds padding bytes (0x00) so that frames transmitted to the Ethernet link do not violate the Ethernet minimum frame length specification. Transmit padding is always performed and cannot be disabled. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1757 MAC Transmit If the MAC is not allowed to append a CRC (ff_tx_crc_fwd=1) the user application is responsible for providing frames with a minimum length of 64 octets. 26.3.8.3 MAC Address Insertion On each frame received from the Core transmit FIFO interface, the source MAC address is optionally replaced by the address programmed on the configuration registers PADDR1 and PADDR2 (Core Configuration register TX_ADDR_INS set to '1') or is transparently forwarded to the Ethernet line (Core Configuration register TX_ADDR_INS set to '0'). 26.3.8.4 CRC-32 generation The CRC-32 field is optionally generated and appended at the end of a Frame if the Frame is transmitted to the Core with the Frame status bit ff_tx_crc_fwd set to '0' when ff_tx_eop is asserted. The CRC polynomial, as specified in the 802.3 Standard, is as follows: * FCS(X) = X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X 4 +X 2 +X 1 +1 The 32 bits of the CRC value are placed in the FCS field so that the X31 term is the rightmost bit of the first octet. The CRC bits are thus transmitted in the following order: X31, X30,..., X1, X0. 26.3.8.5 Inter Packet Gap In full duplex mode, after frame transmission and before transmission of a new frame, an Inter Packet Gap (IPG), programmed with register TX_IPG_LENGTH, is maintained. The minimum IPG can be programmed to any value between 8 and 27 byte-times (64 and 216 bit-times). In half duplex mode, the core constantly monitors the line. Actual transmission of the data onto the network occurs only if it has been idle for a 96-bit time period and any backoff time requirements have been satisfied. In accordance with the standard, the Core begins to measure the IPG from mii_crs / gmii_crs de-assertion. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1758 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.8.6 Collision Detection and Handling - Half Duplex Operation Only A collision occurs on a half-duplex network when concurrent transmissions from two or more nodes take place. During transmission, the Core monitors the line condition and detects a collision when the PHY device asserts the MII mii_col signal. When the Core detects a collision while transmitting, it stops the transmission of data and transmits a 32-bit jam pattern. If the collision is detected during the preamble or the SFD transmission, the jam pattern is transmitted after completing the SFD, which results in a minimum 96-bit fragment. The jam pattern is a fixed pattern that is not compared to the actual frame CRC and has a very low probability (0.532) of having a jam pattern identical to the CRC. If a collision occurs before the transmission of 64 bytes (Including preamble and SFD), the MAC Core waits for the backoff period and retransmits the packet data (Stored in a 64-Bytes re-transmit buffer) already sent on the line. The backoff period is generated from a pseudo random process (Truncated binary exponential backoff). If a collision occurs after the transmission of 64 bytes (Including preamble and SFD), the MAC discards the remaining of the Frame, optionally sets the interrupt bit LC and sets the transmit status bit tx_ts_stat(1). LFSR Core Tx Engine col PHY Control Back off Period Core FIFO rden MAC Transmit Control Retransmit Buffer Control raddr Waddr Frame Discard MAC Transmit Datapath PHY Interface Transmit FIFO Interface 64x5 Retransmit Buffer Figure 26-14. Packet Re-Transmit Overview The backoff time is represented by an integer multiple of slot times (1 slot is equal to a 512-bit time period). The number of delay slot times, before the nth retransmission attempt, is chosen as a uniformly distributed random integer in the range: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1759 Full Duplex Flow Control Operation * 0 < r < 2^k * k = min(n, N) where n is the number of retransmissions and N = 10 For example, after the first collision, the backoff period (in slot time) is 0 or 1, if a collision occurs on the 1st retransmission, the backoff period (in slot time) is 0, 1, 2 or 3 and so on. The maximum backoff time (in 512-Bit time slots) is limited by N set to 10 as specified in the IEEE 802.3 Standard. If a collision occurs after 16 consecutive retransmissions, the Core reports an excessive collision condition (Interrupt bit RL and transmit status bit tx_ts_stat(2)) and discards the current packet from the FIFO. In networks violating the standard requirements, a collision may occur after the transmission of first 64 bytes. In this case, the Core stops the current packet transmission and discards the rest of the packet from the transmit FIFO. The Core resumes transmission with the next packet available in the Core transmit FIFO. 26.3.9 Full Duplex Flow Control Operation 26.3.9.1 Overview Three conditions are handled by the Core's Flow Control engine: * Remote Device Congestion: The Remote device connected to the same Ethernet segment as the Core reports a Congestion requesting the Core to stop sending Data. * Core FIFO Congestion: When the Core's receive FIFO reaches a user programmable threshold (rx section empty), the Core sends a Pause Frame back to the Remote device requesting data transfer to be stopped. * Local Device Congestion: Any device connected to the Core can request (Typically through the Host Processor) the remote device to stop transmitting data. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1760 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.9.2 Remote Device Congestion When the MAC Transmit control gets a valid Pause Quanta from the receive path and if the bit FCE is set to '1', the MAC Transmit logic completes the transfer of the current Frame, stops sending data for the amount of time specified by the Pause Quanta in 512 bit time increments and asserts the bit RFC_PAUSE. Frame transfer resumes when the time specified by the Quanta has expired and if no new Quanta value has been received or if a new Pause Frame with a Quanta value set to 0x0000 is received. The MAC also resets the bit RFC_PAUSE to '0'. If the register bit FCE is set to '0', Pause Frames received by the MAC are ignored. Optionally and independently of the FCE register bit setting, Pause Frame are forwarded to the Client interface if the register bit PAUSE_FWD is set to '1'. 26.3.9.3 Local Device / FIFO Congestion Pause Frames are generated by the MAC transmit engine, when the local receive FIFO is not able to receive more than a pre-defined number of words (FIFO programmable threshold) or when a Pause Frame generation is requested by the Local Host Processor: * To generate a Pause Frame, the Host Processor asserts the register TFC_PAUSE. A single pause frame is generated when the current Frame transfer is completed and the register bit TFC_PAUSE is automatically cleared. Optionally, an interrupt () is generated. * A XOFF Pause Frame is generated when the Receive FIFO asserts its section empty flag (internal). A XOFF Pause Frame is generated automatically, when the current Frame transfer is completed. * A XON Pause Frame is generated when the Receive FIFO de-asserts its section empty flag (internal). A XON Pause Frame is generated automatically, when the current Frame transfer is completed. When a XOFF Pause Frame is generated, the Pause Quanta (Payload Byte P1 and P2) is filled with the value programmed in the Core register PAUSE_DUR. The Source Address is set to the MAC address programmed in the Core configuration registers PADDR1 and PADDR2 and the destination address is set to the fixed Multicast address 01-80-C2-00-00-01 (0x010000c28001). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1761 Full Duplex Flow Control Operation When a XON Pause Frame is generated, the Pause Quanta (Payload Byte P1 and P2) is filled with 0x0000 (Zero Quanta). The Source Address is set to the MAC address programmed in the Core configuration registers PADDR1 and PADDR2 and the destination address is set to the fixed Multicast address 01-80-C2-00-00-01 (0x010000c28001). Pause Frames generated are compliant to the IEEE 802.3 annex 31A&B. From Ethernet Line Programmable Thereshold TFC_PAUSE Pause Frame Generation PAUSE_DUR To Ethernet Line Figure 26-15. Pause Frame Generation Overview Note Although the flow control mechanism should prevent any FIFO overflow on the MAC Core receive path, the Core receive FIFO is protected. When an overflow is detected on the receive FIFO, the current frame is truncated with an error indication set in the frame status word. The frame should subsequently be discarded by the user application. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1762 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.10 Magic Packet Detection 26.3.10.1 Overview Magic Packet detection is used to wake up a node that is put in the power down mode by the node management agent. Magic Packet detection is supported only if the MAC is configured in sleep mode. 26.3.10.2 Sleep Mode To put the MAC in sleep mode, the configuration ECR(SLEEP) should be set to AE1O. At the same time, ECR(MAGIC_ENA) should be set to 1, to enable magic packet detection. In addition, when the external input pin ipg_stop is asserted, sleep mode is entered also, without affecting the ECR register bits. When the Core is in sleep mode: * The MAC transmit logic is disabled. * The Core FIFO receive / transmit functions are disabled. The MAC receive logic is kept in normal mode but it ignores all traffic from the line except Magic Packets, which are detected so that a remote agent can wake up the node. 26.3.10.3 Magic Packet Detection The Core is designed to detect Magic Packets (see 5.3 page 30) with the destination address set to: * Any Multicast address. * The Broadcast address. * The Unicast address programmed in the Core registers PADDR1 / PADDR2. * If enabled, to any of the Unicast addresses programmed in the Core supplemental MAC address registers SMAC_0.. to SMAC_3.. . i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1763 IP Accelerator Functions When a Magic Packets is detected, the interrupt bit EIR(WAKEUP) is asserted and none of the statistic registers is incremented. In addition, the external pin magic_det is asserted and held asserted until the magic packet detection is disabled or the sleep mode is cancelled. 26.3.10.4 Wakeup When a Magic Packet was detected, indicated by an asserted EIR(WAKEUP), the configuration bit ECR(SLEEP) should be cleared to resume normal operation of the MAC. Clearing the SLEEP bit will automatically mask the MAGIC_ENA bit, disabling magic packet detection. This will also deassert the external pin magic_det. 26.3.11 IP Accelerator Functions 26.3.11.1 Checksum Calculation The IP and ICMP, TCP, UDP checksums are calculated with one's complement arithmetic summing up 16-bit values. For ICMP, the checksum is calculated over the complete ICMP datagram (that is, without IP header). For TCP and UDP, the checksums contain the header and data sections and in addition the values from the IP header, which can be seen as a pseudo header that is not actually present as such in the datastream. 3 1 2 7 2 3 1 9 1 5 1 1 7 3 0 source address destination address zero protocol TCP/UDP length Figure 26-16. IPv4 Pseudo Header for Checksum calculation i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1764 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 3 1 2 7 2 3 1 9 1 5 1 1 7 3 0 source address destination address TCP/UDP length zero next header Figure 26-17. IPv6 Pseudo Header for Checksum Calculation The TCP/UDP length value is the length of the TCP or UDP datagram, which is equal to the payload of an IP datagram. It is derived by subtracting the IP header length from the complete IP datagram length that is given in the IP header (IPv4) or directly taken from the IP header (IPv6). The protocol field is the corresponding value from the IP header and 'zero' is filled with zeroes. For IPv6, the complete 128 bit addresses are considered. The next header value identifies the upper layer protocol (TCP or UDP) and may differ from the IPv6 header's actual next header value. if the extension headers are inserted before the protocol header. The checksum calculation uses 16-bit words in network byte order: The first byte sent/ received is the most significant byte and the second byte sent/received is the least significant byte of the 16-bit value to add to the checksum. If the frame ends on an odd number of bytes, a zero byte is appended for checksum calculation only (not actually transmitted). 26.3.11.2 Additional Padding Processing Any Ethernet frame according to IEEE 802.3 must have a minimum length of 64 octets. The MAC usually removes padding on receive, when a frame with length information is received. As IP frames have a type value instead of the length, the MAC will not remove padding for short IP frames, as it is not aware of the frame contents. The IP Accelerator function can be configured to remove the Ethernet padding bytes that might follow the IP datagram. On transmit, the MAC automatically ensures to add padding as necessary to fill any frame to a length of 64. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1765 IP Accelerator Functions 26.3.11.3 32-bit Ethernet Payload Alignment The data FIFOs allow inserting two additional arbitrary bytes in front of a frame. This extends the 14-byte Ethernet header to a 16-byte header, which leads to the alignment of the Ethernet payload, following the Ethernet header, on a 32-bit boundary. This function can be enabled for transmit and receive independently with the corresponding SHIFT16 bits in the ipaccTxConf register and ipaccRxConf register respectively. When enabled, the valid frame data is arranged as shown in the table below. Table 26-22. 64-Bit Interface Data Structure with SHIFT16 option enabled 63 56 55 48 47 40 39 32 31 24 23 16 15 8 70 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Any value Any value Byte 13 Byte 12 Byte 11 Byte 10 Byte 9 Byte 8 Byte 7 Byte 6 ... Receive Processing When the SHIFT16 bit in ipaccRxConf register is enabled, each frame is received with two additional bytes in front of the frame. The user application has to ignore these first two bytes and has to find the first byte of the frame in bits 23:16 of the first word from the RX FIFO. Note that the SHIFT16 bit must be set during initialization and kept asserted during the complete operation as it influences the FIFO write behavior. Transmit Processing When the SHIFT16 bit in ipaccTxConf register is enabled, the first two bytes of the first word written (that is, bits 15:0) will be discarded immediately by the FIFO write logic. The SHIFT16 bit can be enabled/disabled for each frame individually if required, but can be changed only in-between frames. 26.3.11.4 Received Frame Discard As the Receive FIFO must be operated in store and forward mode (Register RX_SECTION_FULL must be set 0), received Frames can be discarded based on the following errors: 1. The MAC function receives the frame with an error: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1766 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) * The Frame has an invalid payload length. * Frame length is greater than MAX_FL. * Frame received with a CRC-32 error. * Frame truncated due to receive FIFO overflow. * Frame is corrupted as PHY signaled an error (mii_rx_err asserted during reception). 2. An IP frame is detected and the IP header checksum is wrong 3. An IP frame with a valid IP header and a valid IP header checksum is detected, the protocol is known but the protocol specific checksum is wrong If one of the errors occurs and the IP Accelerator function is configured to discard frames (Register ipaccRxConf), the frame is automatically discarded. Statistics are maintained normally and are not affected by this discard function. 26.3.11.5 IPv4 Fragments When an IP (IPv4) fragment frame is received, only the IP header is inspected and its checksum is verified. The 32-bit alignment operates on fragments as on normal IP frames, as specified above. The IP fragment frame payload is not inspected for any protocol headers, as such a protocol header would only exist in the very first fragment. To assist in the protocol specific checksum verification, the one's-complement sum is calculated on the IP payload (that is, all bytes following the IP header) and provided with the frame status word. Note The application software can take advantage of the payload checksum delivered with the frame's status word to calculate the protocol specific checksum of the datagram after all the fragments have been received and reassembled. For example, if a TCP payload is delivered by multiple IP fragments, the application software can calculate the pseudo header checksum value from the first fragment and add the payload checksums delivered with the status for all fragments to verify the TCP datagram checksum. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1767 IP Version 6 IPv6 Support 26.3.11.6 IP Version 6 IPv6 Support 26.3.11.6.1 Receive Processing An Ethernet frame of type 0x86dd identifies an IP Version 6 frame (IPv6) Frame. If an IPv6 frame is received, the first IP header is inspected (first 10 words) which is available in every IPv6 frame. If the receive SHIFT16 function is enabled, the IP header is aligned on a 32-bit boundary allowing more efficient processing (see 12.3 page 54). For TCP and UDP datagrams, the pseudo-header checksum calculation is performed and verified. To assist in protocol specific checksum verification, the one's-complement sum is always calculated on the IP payload (that is, all bytes following the IP header) and provided with the frame status word. For example, if extension headers were present, their sum(s) can be subtracted in software from the checksum to isolate the TCP/UDP datagram checksum if required. 26.3.11.6.2 Transmit Processing For IPv6 transmission, the SHIFT16 function is supported to process 32-bit aligned datagrams. IPv6 has no IP header checksum therefore, the IP checksum insertion configuration is ignored. The protocol checksum will be inserted only if the next header of the IP header is a known protocol (that is, TCP, UDP or ICMP). If a known protocol is detected, the checksum over all bytes following the IP header is calculated and inserted in the correct position. The pseudo-header checksum calculation is performed for TCP and UDP datagrams accordingly. 26.3.12 Resets and Stop Controls 26.3.12.1 Hardware Reset Setting the ECR(RESET) bit, resets the Ethernet controller and initializes all registers and logic. This bit is self-clare. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1768 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.12.2 Soft Reset When ECR(ETHER_EN) is cleared, during operation, the following happens: * DMA, buffer descriptor and FIFO control logic are reset, including the buffer descriptor and FIFO pointers. * Transmission is terminated by asserting mii_tx_err to the PHY. * The current FIFO write is terminated and all further data from the application is ignored. All subsequent writes are ignored until re-enabled. * The current FIFO read is terminated. 26.3.12.3 Graceful Stop The following conditions lead to a graceful stop of the MAC transmit or receive datapaths. A graceful stop means that any currently ongoing transactions are completed normally and no further frames after that will be accepted. The MAC can resume from a graceful stop without the need for a reset (for example, ECR(ETHER_EN) bit deassertion is not required). 26.3.12.4 Graceful Transmit Stop (GTS) When gracefully stopped, the MAC is no longer reading frame data from the transmit FIFO and has completed any ongoing transmission. In any of the following conditions, the transmit datapath will stop after an ongoing frame transmission has been completed normally. * Register bit TCR(GTS) is set by software. * Register bit TCR(TFC_PAUSE) is set by software requesting a pause frame transmission. The status (and register bit) is cleared after the pause frame has been sent. * A pause frame was received stopping the transmitter. The stopped situation is terminated when the pause timer expired or a pause frame with zero quanta is received. * MAC is placed in Sleep mode by set SLEEP or SLEEP bit (see Sleep Mode). When the transmitter has reached its stopped state, the following events occur: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1769 Resets and Stop Controls * The GRA interrupt is asserted (once, when transitioned into stopped). 26.3.12.5 Graceful Receive Stop (GRS) When gracefully stopped, the MAC is no longer writing frames into the receive FIFO. If any of the following conditions occur, the receive datapath will stop after any ongoing frame reception has been completed normally. * MAC is placed in sleep mode (by set SLEEP or SLEEP ). The MAC will continue to receive frames and hunt for magic packets if enabled (see Sleep Mode). However, no frames will be written into the receive FIFO and therefore will not be forwarded to the application. When the receive datapath is stopped, the following events will occur: * The RCR(GRS) bit is set as long as the RX is in the stopped state. * The GRA interrupt is asserted when the transmitter is also stopped (both TX and RX are stopped). * Any ongoing receive transaction to the application (RX FIFO read) will continue normally until the frame is completed (eop). After this, the following happens: * When sleep mode is active, all further frames will be discarded, flushing the rx FIFO. Note The assertion of GRS will not wait for an ongoing transaction on the application side of the FIFO (FIFO read). If necessary, the signal can be ANDed with the ff_rx_dval (considering proper clock domains). 26.3.12.6 Graceful Stop Interrupt (GRA) The graceful stopped interrupt (GRA) is asserted for the following conditions: * If sleep mode is active, the interrupt asserts only after both TX and RX datapaths are stopped. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1770 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) * * The MAC transmit datapath is stopped for any other condition (GTS, TFC_PAUSE, pause received). The GRA interrupt is triggered only once when the stopped state is entered. If the interrupt is cleared while the stop condition persists, no further interrupt will be triggered. 26.3.13 IEEE 1588 Functions 26.3.13.1 Overview To allow for IEEE 1588 or similar time synchronization protocol implementations, the MAC is combined with a time-stamping module to support precise time stamping of incoming and outgoing frames. 1588 Support is enabled when the register bit ENA_1588 is set to '1'. MAC with 1588 Frame Data 10/100 MAC (mac) PHY Timing Control/ Status Adjustable Timer Module (tsm) Events gen 1PPS Control/ Status Data Control User Application Figure 26-18. IEEE 1588 Functions Overview 26.3.13.2 Adjustable Timer Module 26.3.13.2.1 Overview The Adjustable Timer Module (TSM) implements the Free Running Counter (FRC), the timer, which is used to generate the timestamps. The FRC operates with the clock CLK_ENET_TIME, which can be set to any value depending on the system requirements. However, it is recommended to choose a period, which is an integer value (for example, 5 ns, 6 ns, 8 ns, but not 7.5 ns) to implement a precise timer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1771 Adjustable Timer Module The current value of the FRC is available on the Core toplevel pins frc(). Through dedicated correction logic (see below), the timer can be adjusted allowing synchronization to a remote master and provide a synchronized timing reference to the local system. The timer can be configured to cause an interrupt after a fixed period of time to allow synchronization of software timers or perform other synchronized system functions. The timer is usually used to implement a period of 1 second, hence, its value would range from 0 to (1*109)-1. The period event can trigger an interrupt and software then can maintain the seconds and hours time values and so on as necessary. 26.3.13.2.2 Adjustable Timer Implementation The adjustable timer consists of a programmable counter/accumulator and a correction counter. The periods of both counters and its increment rate are freely configurable allowing very fine tuning of the timer. frc_in(31:0) frc(31:0) Adjustable Timer Counter current time ATIME_EVT_PERICD Correction Counter ATIME_CORR mod to intemal modules (MAC,capture/ compare) Inc by normal correction FRC_SLAVE ATIME_INC(14:8) correction Increment ATIME_INC(6:0) normal Increment Figure 26-19. Adjustable Timer Implementation Detail The counter is producing the current time. Each clock cycle (CLK_ENET_TIME), a constant value is added to the current time as programmed in the ATIME_INC(4:0) register. The value depends on the chosen clock frequency of CLK_ENET_TIME. For example, if the CLK_ENET_TIME operates at 125 MHz, the increment would be set to 8 representing 8 ns. The period, configured in register ATIME_EVT_PERIOD, defines the modulo when the counter has to wrap around. In a typical implementation, the period is set to 1*109, so the counter wraps every 1 second and hence, all timestamps represent the absolute nanoseconds within the 1 second period. When the period is reached, the counter wraps to start again respecting the period modulo. This means it will not necessarily start from 0 but instead the counter will be loaded with the value (current + inc - (1*109)) assuming the period was set to 1*109. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1772 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) The correction counter operates fully independently and increments by 1 with each clock cycle (CLK_ENET_TIME). When it reaches the value configured in ATIME_CORR, it restarts and instructs the timer once to increment by the correction value, instead of the normal value. The normal and correction increments are configured in register ATIME_INC. To speed up the timer, the correction increment would be larger than the normal increment value. To slow down the timer, the correction increment would be smaller than the normal increment value. Note that the correction counter only defines the distance of the corrective actions, not the amount. This allows very fine corrections (and hence low jitter) happening in the range of 1ns independently from the chosen clock frequency. By enabling the slave mode (ATIME_CTRL(FRC_SLAVE)), the timer is ignored and the current time is the externally provided time from pins frc_in(). This is useful if multiple modules within the system need to operate from a single timer (see below). When slave mode is enabled, it is still required to set the ATIME_INC(6:0) increment value to the value of the master as it is used for internal comparisons. 26.3.13.3 Timer Synchronization for Multi-Port Implementations An additional timer input is available on the Core toplevel pins frc_in() to allow to use an externally provided timer value for all time stamping functions. This is necessary if multiple instances (ports) of the MAC should be synchronized to a single reference timer in the system. In i.MX28, ENET-MAC0 is used as master, so the timer input (frc_in) of ENET_MAC0 is unused and wired to all 0. The FRC value of ENET_MAC0 is wired to frc_in of ENET_MAC1 (acting as slave). To operate the MAC in Slave mode, the timer module configuration ATIME_CTRL(FRC_SLAVE) is used to disable the internal adjustable timer and use only the externally provided time value. Timing Slave Timing Master MAC with 1588 MAC with 1588 10/100 MAC (mac0 as master) frc frc_in Timing Adjustable Timer Module (tsm) Events gen. 10/100 MAC (mac1 as slave) frc_in Timing Events gen. Figure 26-20. 1588 Multiple MAC implementation i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1773 Adjustable Timer Module 26.3.13.4 Transmit Timestamping On transmit, only 1588 event frames need to be time-stamped. The Client application (for example, the MAC driver) should detect 1588 event frames and set 'TS' bit in Enhanced uDMA Transmit Buffer Descriptor. For every transmitted frame, the MAC returns the captured timestamp in '1588 Timestamp' and the transmit status TSE in Enhanced uDMA Transmit Buffer Descriptor. The transmit status bit indicates that the application had the TS bit asserted for the frame. If TS is set to '1', the MAC additionally memorizes the timestamp for the frame in the register TS_TIMESTAMP. The interrupt bit EIR(TS_AVAIL) is set to indicate that a new timestamp is available. Software would implement a handshaking procedure by setting the TS bit when it transmits the frame it needs a timestamp for and then waits on the EIR(TS_AVAIL) interrupt bit to know when the timestamp is available. It then can read the timestamp from the TS_TIMESTAMP register. This is done for all event frames, other frames will not use the TS indicator and hence will not interfere with the timestamp capture. 26.3.13.5 Receive Timestamping When a frame is received, the MAC latches the value of the timer when the frame SFD field is detected and provides the captured timestamp '1588 Timestamp' in Enhanced uDMA Receive Buffer Descriptor. This is done for all received frames. The DMA controller has to ensure that it transfers the timestamp provided for the frame into the corresponding field within the receive descriptor for software access. 26.3.13.6 Time Synchronization To synchronize the local clock of a node to a remote master, the adjustable timer module is available. It implements a free running 32-bit counter, which has an additional correction counter connected to it. The correction counter is used to increase or decrease the rate of the free running counter, enabling very fine granular changes of the timer for synchronization, yet adding only very low jitter when performing corrections. The application (software) implements, in a slave scenario, the required control algorithm setting the correction to compensate for local oscillator drifts and locking the timer to the remote master clock on the network. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1774 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) The timer and all timestamp related information should be configured to show the true nanoseconds value of a second (that is, the timer is configured to have a period of 1 second). Hence, the values range from 0 to (1*109)-1. In this application, the seconds counter is implemented in software using an interrupt function that is executed whenever the nanoseconds counter wraps at 1*109. Note Implementing the seconds counter in software is not a strict requirement. 26.3.13.7 Capture/Compare Block The Capture / Compare block can provide precise hardware timing for four input events and four output events. The capture registers (CAPT_REG..) latch the time value when the corresponding external event occurs (evt_in()). If the corresponding interrupt bit is enabled in the CCB_INT register, an interrupt can be generated. The compare registers (COMP_REG_..) are loaded with the time at which the corresponding event should occur. The timer reached the value, the corresponding output pin (evt_out()) is asserted. If the corresponding interrupt bit is enabled in the EIMR register, an interrupt can be generated. 26.3.14 FIFO Thresholds 26.3.14.1 Overview The Core FIFO thresholds are all fully programmable to provide the possibility to dynamically change the FIFO operation. For example, store and forward transfer can be enabled by a simple change in the FIFO threshold registers. The thresholds are defined in 64-bit words. 26.3.14.2 Receive FIFO Four programmable thresholds are available which are programmed with the registers RX_ALMOST_EMPTY, RX_ALMOST_FULL, RX_SECTION_EMPTY and RX_SECTION_FULL which can be set to any value to control operation as follows table. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1775 FIFO Thresholds Table 26-23. Receive FIFO Thresholds Definition Register Description RX_ALMOST_EMPTY When the FIFO level reaches the value programmed in the register RX_ALMOST_EMPTY, and the end-of-frame has not been received for the frame yet, the Core receive read control stops FIFO read (and subsequently stops transferring data to the MAC client application). It continues to deliver the frame, if again more data than the threshold or the end-of-frame is available in the FIFO. A minimum value of 6 should be set. RX_ALMOST_FULL When the FIFO level comes close to the maximum, so that there is no more space for at least RX_ALMOST_FULL number of words, the MAC control logic stops writing data in the FIFO and truncates the received frame to avoid FIFO overflow. The corresponding error status will be set when the frame is delivered to the application. A minimum value of 4 should be set. RX_SECTION_EMPTY When the FIFO level reaches the value programmed in the register RX_SECTION_EMPTY, an indication is provided to the MAC transmit logic, which generates a XOFF Pause frame to indicate FIFO congestion to the remote Ethernet client. When the FIFO level goes below the value programmed in the register RX_SECTION_EMPTY, an indication is provided to the MAC transmit logic, which generates a XON Pause frame to indicate the FIFO congestion is cleared to the remote Ethernet client. A value of 0 disables any pause frame generation. RX_SECTION_FULL When the FIFO level reaches the value programmed in the register RX_SECTION_FULL, the MAC will indicate uDMA that data is available in the Receive FIFO (cut-through operation) by asserted a internal signal. MAC will deassert the siganl again after asserted, if the fifo empties below the threshold set with RX_ALMOST_EMPTY, and if the end-of-frame is not yet stored in the fifo (Hysteresis). If a Frame has a size smaller than the threshold (i.e. an end-of-frame is available for the frame), the status is also asserted. To enable store and forward on the receive path, set the register RX_SECTION_FULL to 0. In this case, The signal is asserted only when a complete frame is stored in the receive FIFO. When programming a value>0 (cut-through operation) it should be greater than RX_ALMOST_EMPTY. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1776 Freescale Semiconductor, Inc. Almost Empty (FIFO Read Control) Section Full (Core FIFO Status) MAC Receive Almost Full (FIFO White Proctection FIFO Read Control Chapter 26 Ethernet Controller (ENET) Section Empty (Pause Frame Generation) Figure 26-21. Receive FIFO Overview 26.3.14.3 Transmit FIFO Four programmable thresholds are available which are programmed with registers TX_ALMOST_EMPTY, TX_ALMOST_FULL, TX_SECTION_EMPTY and TFWR / STR_FWD. Table 26-24. Transmit FIFO Thresholds Definition Register Description TX_ALMOST_EMPTY When the FIFO level reaches the value programmed in the register TX_ALMOST_EMPTY, and no end-of-frame is available for the frame, the MAC transmit logic, to avoid FIFO underflow, stops reading the FIFO and transmits the Ethernet frame with a MII error indication. A minimum value of 4 should be set. TX_ALMOST_FULL When the FIFO level comes close to the maximum, so that there is no more space for at least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the application does not react on this signal, the FIFO write control logic, to avoid FIFO overflow, truncates the current frame and sets the error status. As a result the frame will be transmitted with an MII error indication. A minimum value of 4 should be set. Larger values allow more latency for the application to react on ff_tx_rdy deassertion, before the frame is being truncated. A typical setting is 8, which offers 3-4 clock cycles of latency to the application to react on ff_tx_rdy deassertion. TX_SECTION_EMPTY When the FIFO level reaches the value programmed in the register TX_SECTION_EMPTY, the Core status ff_tx_septy is deasserted to indicate that the Transmit FIFO is getting full. This gives the application an indication to slow down or stop its write transaction to avoid a buffer overflow. This is a pure indication function to the application. It has no effect within the MAC. When a value of 0 is set, the signal is never deasserted. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1777 Loopback Options Table 26-24. Transmit FIFO Thresholds Definition (continued) Register Description TFWR / STR_FWD When the FIFO level reaches the value coded in the register TFWR and when the register bit STR_FWD is set to '0', the MAC transmit control logic starts frame transmission even before the end-of-frame is available in the FIFO (cut-through operation). If a complete frame has a size smaller than the threshold programmed with TFWR, the MAC also transmits the Frame to the line. Almost Full (FIFO White Control) MAC Transmit Section Full (MAC Transmit Start) Section Empty (Core FIFO Status) Almost Empty (MAC Read Control) FIFO Write Control To enable store and forward on the Transmit path, set the register bit STR_FWD to '1'. In this case, the MAC starts to transmit data only when a complete frame is stored in the Transmit FIFO. Figure 26-22. Transmit FIFO Overview 26.3.15 Loopback Options 26.3.15.1 Overview The Core implements external and internal loopback options with are controlled by the RCR register bits LOOP. Table 26-25. Loopback Options Register Bit Description LOOP Internal MII Loopback The MAC transmit is returned to the MAC receive. No data is transmitted to the external interfaces. RMII_LOOP External RMII Near End Loopback. Not surpport now. RMII_ECHO External RMII Far End Loopback. Not surpport now. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1778 Freescale Semiconductor, Inc. Line Interface MAC Interface Chapter 26 Ethernet Controller (ENET) LOOP ena_loop RMII_ECHO ena_rmii_loop RMII_LOOP ena_rmii_echo Figure 26-23. Loopback Options 26.3.16 FIFO Protection 26.3.16.1 Transmit FIFO Underflow When the Transmit FIFO, during a frame transfer, reaches the almost empty threshold with no End of Frame indication stored in the FIFO, the MAC logic stops reading data from the FIFO, sets the MII error signal (mii_tx_err) to '1' to indicate that the fragment already transferred is not valid and deasserts the MII transmit enable signal (mii_tx_en) to terminate the frame transfer . When after an underflow, the application completes the frame transfer , the MAC transmit logic discards any new data available in the FIFO until the end of packet is reached and sets bit UE of Enhanced uDMA Transmit Buffer Descriptor. The MAC starts to transfer data on the MII interface when the application sends a new frame with a start of frame indication . i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1779 FIFO Protection 26.3.16.2 Transmit FIFO Overflow On the transmit path, when the FIFO reaches the programmable almost full threshold, if the application keeps sending new data, the transmit FIFO will overflow, corrupting previously stored contents. ENET-MAC will set bit OE of Enhanced uDMA Transmit Buffer Descriptor for the next frame transmitted to indicate this overflow occurrence. Note that overflow is a fatal error and must be addressed by resetting the core or deasserting the ECR(ETHER_EN) bit to clear the FIFOs and prepare for normal operation again. 26.3.16.3 Receive FIFO Overflow If, during a frame reception the client application is not able to receive data , the MAC receive control, when the FIFO reaches the programmable almost full threshold truncates the incoming frame (To avoid a overflow). The frame is subsequently received on the FIFO interface with an error indication (ME of Enhanced uDMA Receive Buffer Descriptor ) with the truncation error status bit (TR of Legacy FEC Receive Buffer Descriptor) set to '1'. GMII /MII Receive rx_clk gmii/mii_rx_en gmii/mii_rx_data gmii/mii_rx_err Receive FIFO ff_rx_clk ff_rx_rdy ff_rx_dsav ff_rx_dval ff_rx_sop ff_rx_eop ff_rx_data ff_rx_err ff_rx_err_stat 1 2 3 Figure 26-24. Receive FIFO Overflow Protection i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1780 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.3.17 PHY Management Interface 26.3.17.1 Overview The MDIO interface is a two-wire Management Interface. The MDIO management interface implements a standardized method to access the PHY device management registers. This is a Master MDIO interface, which can be connected to up to 32 PHY devices. 26.3.17.2 MDIO Frame Format The MDIO Master controller communicates with the Slave (PHY device) using Frames, which are defined in Table 26-26. A complete frame has a length of 64 bits (Optional 32 bit preamble, 14 bit command, 2 bit bus direction change, 16 bit data). Each bit is transferred with the rising edge of the MDIO clock (MDC signal). The PHY Management interface supports the standard MDIO specification (IEEE803.2 Clause 22). Table 26-26. MDIO Frame Formats (Read / Write) Type Command PRE ST OP Addr1 Addr2 MSB LSB MSB LSB MSB LSB MSB LSB TA Data Idle MSB LSB Read 1...1 01 10 xxxxx xxxxx Z0 xxxxxxxxxxxxxxxx Z Write 1...1 01 01 xxxxx xxxxx 10 xxxxxxxxxxxxxxxx Z Table 26-27. MDIO Frame Fields Description Name Description PRE Preamble: 32 Bits of logical '1' sent prior to every transaction when the register bit DIS_PRE is set to '0. If DIS_PRE is set to '1', the preamble is not generated. ST Start indication, programmed with the register bits ST: Standard MDIO (Clause 22): '01' OP The opcode, programmed with the register bits OP, defines whether a read or write operation is performed: If '10' a read operation is performed. If '01' a write operation is performed. Addr1 The PHY device address, programmed with the register bits PA. Up to 32 devices can be addressed. Addr2 Register Address, programmed with the register bits RA. Each PHY can implement up to 32 registers. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1781 PHY Management Interface Table 26-27. MDIO Frame Fields Description (continued) Name Description TA Turnaround time, programmed with register bits TA. Two bit-times are reserved for read operations to switch the data bus from write to read for read operations. The PHY device will present its register contents in the data phase and drives the bus from the second bit of the turnaround phase. Data 16 bits of data written, set to register bits DATA, to the PHY or read from the PHY on register bits DATA. Idle Between frames, the MDIO data signal is tri-stated. 26.3.17.3 MDIO Clock Generation The MDC clock is generated from the register interface clock pclk divided by the value programmed in the Core register MII_SPEED. 26.3.17.4 MDIO Operation To perform a MDIO access, the MDIO Command register (Register MMFR) should be set according to the description provided in ENET MAC MII Management Frame Register (HW_ENET_MAC_MMFR). To check when the programmed access is completed, the EIR status register should be read and the register bit MII checked. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1782 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) Start Load MMFR Register Read EIR No MII='1' Yes Figure 26-25. MDIO Access Overview 26.3.17.5 MDIO Buffer Connection mdio_in MDIO mdio_out mdio_oeN Figure 26-26. MDIO Buffer Connection i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1783 MII Interface 26.3.18 MII Interface 26.3.18.1 Transmit On Transmit, all data transfers are synchronous to tx_clk rising edge. The MII data enable signal mii_tx_en is asserted to indicate the start of a new frame and remains asserted until the last byte of the frame is present on mii_tx_d(3:0) bus. Between frames, mii_tx_en remains de-asserted. CRC-32 SFD Preamble tx_dk 5 mii_tx_d(3:0) mii_tx_en mii_tx_err Figure 26-27. MII Transmit Operation If a frame is received on the FIFO interface with an error (for example, Signal ff_rx_err asserted) the frame is subsequently transmitted with the MII mii_tx_err error signal for one clock cycle at any time during the packet transfer. CRC-32 Preamble SFD tx_clk mii_tx_d(3:0) 5 mii_tx_en mii_tx_err Figure 26-28. MII Transmit Operation - Errored Frame 26.3.18.2 Transmit with Collision - Half Duplex When a collision is detected during a frame transmission (MII signal mii_col asserted), the MAC stops the current transmission, sends a 32-Bit jam pattern and re-transmits the current frame (See section Collision Detection in Half Duplex Mode for detail). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1784 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) Jam tx_clk 5 mii_tx_d(3:0) mii_tx_en mii_tx_err mii_crs mii_col Figure 26-29. MII Transmit Operation - Transmission with Collision 26.3.18.3 Receive On Receive, all signals are sampled on the rx_clk rising edge. The MII data enable signal mii_rx_dv is asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the frame is present on mii_rx_d(3:0) bus. Between frames, mii_rx_dv remains de-asserted. CRC-32 SFD Preamble rx_clk 5 mii_rx_d(3:0) mii_rx_dv mii_rx_err Figure 26-30. MII Receive Operation If the PHY detects an error on the frame received from the line, the PHY asserts the MII error signal, mii_rx_err, for at least one clock cycle at any time during the packet transfer. CRC-32 Preamble SFD rx_clk 5 mii_rx_d(3:0) mii_rx_dv mii_rx_err Figure 26-31. MII Receive Operation - Errored Frame i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1785 MII Interface 26.3.19 MII Interface Timing Characteristics rx_clk tx_clk 1/F max rx_clk mii_rx_d(3:0) mii_rx_dv mii_rx_err thold tsu tx_clk mii_tx_d(3:0) mii_tx_en mii_tx_err too Table 26-28. MII Timing Characteristics Symbol Description Value Min Max Fmax MII Maximum Frequency 2.5 MHz 25 MHz tsu MII Inputs Setup Time 2 ns - thold MII Inputs Hold Time 0 ns - tco MII Outputs Clock to Out - 5 ns i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1786 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4 Programmable Registers Each ENET-MAC with its corresponding management counters implements a register space of 512 32-bit registers. All reads and writes must be 32 bits wide. Reserved bits should be written with 0 and ignored on read to allow future extension. Unused registers read back 0 and a write has no effect. ENET-MAC0 base address is 0x800F0000; ENET-MAC1 base address is 0x800F4000. HW_ENET memory map Absolute address (hex) Register name 800F_0004 ENET MAC Interrupt Event Register (HW_ENET_MAC_EIR) 32 800F_0008 ENET MAC Interrupt Mask Register (HW_ENET_MAC_EIMR) 800F_0010 Width Access (in bits) Reset value Section/ page R/W 0000_0000h 26.4.1/1793 32 R/W 0000_0000h 26.4.2/1794 ENET MAC Receive Descriptor Active Register (HW_ENET_MAC_RDAR) 32 R/W 0000_0000h 26.4.3/1795 800F_0014 ENET MAC Transmit Descriptor Active Register (HW_ENET_MAC_TDAR) 32 R/W 0000_0000h 26.4.4/1796 800F_0024 ENET MAC Control Register (HW_ENET_MAC_ECR) 32 R/W F000_0000h 26.4.5/1798 800F_0040 ENET MAC MII Management Frame Register (HW_ENET_MAC_MMFR) 32 R/W 0000_0000h 26.4.6/1799 800F_0044 ENET MAC MII Speed Control Register (HW_ENET_MAC_MSCR) 32 R/W 0000_0000h 26.4.7/1801 800F_0064 ENET MAC MIB Control/Status Register (HW_ENET_MAC_MIBC) 32 R/W C000_0000h 26.4.8/1802 800F_0084 ENET MAC Receive Control Register (HW_ENET_MAC_RCR) 32 R/W 05EE_0001h 26.4.9/1803 800F_00C4 ENET MAC Transmit Control Register (HW_ENET_MAC_TCR) 32 R/W 0000_0000h 26.4.10/ 1805 800F_00E4 ENET MAC Physical Address Lower Register (HW_ENET_MAC_PALR) 32 R/W 0000_0000h 26.4.11/ 1806 800F_00E8 ENET MAC Physical Address Upper Register (HW_ENET_MAC_PAUR) 32 R/W 0000_8808h 26.4.12/ 1807 800F_00EC ENET MAC Opcode/Pause Duration Register (HW_ENET_MAC_OPD) 32 R/W 0001_0000h 26.4.13/ 1807 800F_0118 ENET MAC Descriptor Individual Upper Address Register (HW_ENET_MAC_IAUR) 32 R/W 0000_0000h 26.4.14/ 1807 800F_011C ENET MAC Descriptor Individual Lower Address Register (HW_ENET_MAC_IALR) 32 R/W 0000_0000h 26.4.15/ 1808 800F_0120 ENET MAC Descriptor Group Upper Address Register (HW_ENET_MAC_GAUR) 32 R/W 0000_0000h 26.4.16/ 1808 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1787 Programmable Registers HW_ENET memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800F_0124 ENET MAC Descriptor Group Lower Address Register (HW_ENET_MAC_GALR) 32 R/W 0000_0000h 26.4.17/ 1809 800F_0144 ENET MAC Transmit FIFO Watermark and Store and Forward Control Register (HW_ENET_MAC_TFW_SFCR) 32 R/W 0000_0000h 26.4.18/ 1809 800F_014C ENET MAC FIFO Receive Bound Register (HW_ENET_MAC_FRBR) 32 R/W 0000_0600h 26.4.19/ 1810 800F_0150 ENET MAC FIFO Receive FIFO Start Register (HW_ENET_MAC_FRSR) 32 R/W 0000_0500h 26.4.20/ 1811 800F_0180 ENET MAC Pointer to Receive Descriptor Ring Register (HW_ENET_MAC_ERDSR) 32 R/W 0000_0000h 26.4.21/ 1812 800F_0184 ENET MAC Pointer to Transmit Descriptor Ring Register (HW_ENET_MAC_ETDSR) 32 R/W 0000_0000h 26.4.22/ 1813 800F_0188 ENET MAC Maximum Receive Buffer Size Register (HW_ENET_MAC_EMRBR) 32 R/W 0000_0000h 26.4.23/ 1814 800F_0190 ENET MAC Receive FIFO Section Full Threshold Register (HW_ENET_MAC_RX_SECTION_FULL) 32 R/W 0000_0000h 26.4.24/ 1814 800F_0194 ENET MAC Receive FIFO Section Empty Threshold Register (HW_ENET_MAC_RX_SECTION_EMPTY) 32 R/W 0000_0000h 26.4.25/ 1815 800F_0198 ENET MAC Receive FIFO Almost Empty Threshold Register (HW_ENET_MAC_RX_ALMOST_EMPTY) 32 R/W 0000_0004h 26.4.26/ 1815 800F_019C ENET MAC Receive FIFO Almost Full Thresholdt Register (HW_ENET_MAC_RX_ALMOST_FULL) 32 R/W 0000_0004h 26.4.27/ 1816 800F_01A0 ENET MAC Transmit FIFO Section Empty Threshold Register (HW_ENET_MAC_TX_SECTION_EMPTY) 32 R/W 0000_0000h 26.4.28/ 1816 800F_01A4 ENET MAC Transmit FIFO Almost Empty Threshold Register (HW_ENET_MAC_TX_ALMOST_EMPTY) 32 R/W 0000_0004h 26.4.29/ 1817 800F_01A8 ENET MAC Transmit FIFO Almost Full Threshold Register (HW_ENET_MAC_TX_ALMOST_FULL) 32 R/W 0000_0008h 26.4.30/ 1817 800F_01AC ENET MAC Transmit Inter-Packet Gap Register (HW_ENET_MAC_TX_IPG_LENGTH) 32 R/W 0000_000Ch 26.4.31/ 1818 800F_01B0 ENET MAC Frame Truncation Length Register (HW_ENET_MAC_TRUNC_FL) 32 R/W 0000_07FFh 26.4.32/ 1818 800F_01C0 ENET MAC Accelerator Transmit Function Configuration Register (HW_ENET_MAC_IPACCTXCONF) 32 R/W 0000_0000h 26.4.33/ 1819 800F_01C4 ENET MAC Accelerator Receive Function Configuration Register (HW_ENET_MAC_IPACCRXCONF) 32 R/W 0000_0000h 26.4.34/ 1821 800F_0200 ENET MAC RMON Tx packet drop (HW_ENET_MAC_RMON_T_DROP) 32 R 0000_0000h 26.4.35/ 1822 800F_0204 ENET MAC RMON Tx packet count (HW_ENET_MAC_RMON_T_PACKETS) 32 R 0000_0000h 26.4.36/ 1823 800F_0208 ENET MAC RMON Tx Broadcast Packets (HW_ENET_MAC_RMON_T_BC_PKT) 32 R 0000_0000h 26.4.37/ 1823 800F_020C ENET MAC RMON Tx Multicast Packets (HW_ENET_MAC_RMON_T_MC_PKT) 32 R 0000_0000h 26.4.38/ 1823 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1788 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) HW_ENET memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800F_0210 ENET MAC RMON Tx Packets w CRC/Align error (HW_ENET_MAC_RMON_T_CRC_ALIGN) 32 R 0000_0000h 26.4.39/ 1824 800F_0214 ENET MAC RMON Tx Packets < 64 bytes, good CRC (HW_ENET_MAC_RMON_T_UNDERSIZE) 32 R 0000_0000h 26.4.40/ 1824 800F_0218 ENET MAC RMON Tx Packets > MAX_FL bytes, good CRC (HW_ENET_MAC_RMON_T_OVERSIZE) 32 R 0000_0000h 26.4.41/ 1825 800F_021C ENET MAC RMON Tx Packets < 64 bytes, bad CRC (HW_ENET_MAC_RMON_T_FRAG) 32 R 0000_0000h 26.4.42/ 1825 800F_0220 ENET MAC RMON Tx Packets > MAX_FL bytes, bad CRC (HW_ENET_MAC_RMON_T_JAB) 32 R 0000_0000h 26.4.43/ 1825 800F_0224 ENET MAC RMON Tx collision count (HW_ENET_MAC_RMON_T_COL) 32 R 0000_0000h 26.4.44/ 1826 800F_0228 ENET MAC RMON Tx 64 byte packets (HW_ENET_MAC_RMON_T_P64) 32 R 0000_0000h 26.4.45/ 1826 800F_022C ENET MAC RMON Tx 65 to 127 byte packets (HW_ENET_MAC_RMON_T_P65TO127N) 32 R 0000_0000h 26.4.46/ 1827 800F_0230 ENET MAC RMON Tx 128 to 255 byte packets (HW_ENET_MAC_RMON_T_P128TO255N) 32 R 0000_0000h 26.4.47/ 1827 800F_0234 ENET MAC RMON Tx 256 to 511 byte packets (HW_ENET_MAC_RMON_T_P256TO511) 32 R 0000_0000h 26.4.48/ 1827 800F_0238 ENET MAC RMON Tx 512 to 1023 byte packets (HW_ENET_MAC_RMON_T_P512TO1023) 32 R 0000_0000h 26.4.49/ 1828 800F_023C ENET MAC RMON Tx 1024 to 2047 byte packets (HW_ENET_MAC_RMON_T_P1024TO2047) 32 R 0000_0000h 26.4.50/ 1828 800F_0240 ENET MAC RMON Tx packets w > 2048 bytes (HW_ENET_MAC_RMON_T_P_GTE2048) 32 R 0000_0000h 26.4.51/ 1829 800F_0244 ENET MAC RMON Tx Octets (HW_ENET_MAC_RMON_T_OCTETS) 32 R 0000_0000h 26.4.52/ 1829 800F_0248 ENET MAC Frames Transmitted count drop (HW_ENET_MAC_IEEE_T_DROP) 32 R 0000_0000h 26.4.53/ 1829 800F_024C ENET MAC Frames Transmitted OK (HW_ENET_MAC_IEEE_T_FRAME_OK) 32 R 0000_0000h 26.4.54/ 1830 800F_0250 ENET MAC Frames Transmitted with Single Collision (HW_ENET_MAC_IEEE_T_1COL) 32 R 0000_0000h 26.4.55/ 1830 800F_0254 ENET MAC Frames Transmitted with Multiple Collisions (HW_ENET_MAC_IEEE_T_MCOL) 32 R 0000_0000h 26.4.56/ 1831 800F_0258 ENET MAC Frames Transmitted after Deferral Delay (HW_ENET_MAC_IEEE_T_DEF) 32 R 0000_0000h 26.4.57/ 1831 800F_025C ENET MAC Frames Transmitted with Late Collision (HW_ENET_MAC_IEEE_T_LCOL) 32 R 0000_0000h 26.4.58/ 1831 800F_0260 ENET MAC Frames Transmitted with Excessive Collisions (HW_ENET_MAC_IEEE_T_EXCOL) 32 R 0000_0000h 26.4.59/ 1832 800F_0264 ENET MAC Frames Transmitted with Tx FIFO Underrun (HW_ENET_MAC_IEEE_T_MACERR) 32 R 0000_0000h 26.4.60/ 1832 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1789 Programmable Registers HW_ENET memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800F_0268 ENET MAC Frames Transmitted with Carrier Sense Error (HW_ENET_MAC_IEEE_T_CSERR) 32 R 0000_0000h 26.4.61/ 1833 800F_026C ENET MAC Frames Transmitted with SQE Error (HW_ENET_MAC_IEEE_T_SQE) 32 R 0000_0000h 26.4.62/ 1833 800F_0270 ENET MAC Frames Transmitted flow control (HW_ENET_MAC_IEEE_T_FDXFC) 32 R 0000_0000h 26.4.63/ 1834 800F_0274 ENET MAC Frames Transmitted error (HW_ENET_MAC_IEEE_T_OCTETS_OK) 32 R 0000_0000h 26.4.64/ 1834 800F_0284 ENET MAC RMON Rx packet count (HW_ENET_MAC_RMON_R_PACKETS) 32 R 0000_0000h 26.4.65/ 1835 800F_0288 ENET MAC RMON Rx Broadcast Packets (HW_ENET_MAC_RMON_R_BC_PKT) 32 R 0000_0000h 26.4.66/ 1835 800F_028C ENET MAC RMON Rx Multicast Packets (HW_ENET_MAC_RMON_R_MC_PKT) 32 R 0000_0000h 26.4.67/ 1835 800F_0290 ENET MAC RMON Rx Packets w CRC/Align error (HW_ENET_MAC_RMON_R_CRC_ALIGN) 32 R 0000_0000h 26.4.68/ 1836 800F_0294 ENET MAC RMON Rx Packets < 64 bytes, good CRC (HW_ENET_MAC_RMON_R_UNDERSIZE) 32 R 0000_0000h 26.4.69/ 1836 800F_0298 ENET MAC RMON Rx Packets > MAX_FL, good CRC (HW_ENET_MAC_RMON_R_OVERSIZE) 32 R 0000_0000h 26.4.70/ 1837 800F_029C ENET MAC RMON Rx Packets < 64 bytes, bad CRC (HW_ENET_MAC_RMON_R_FRAG) 32 R 0000_0000h 26.4.71/ 1837 800F_02A0 ENET MAC RMON Rx Packets > MAX_FL bytes, bad CRC (HW_ENET_MAC_RMON_R_JAB) 32 R 0000_0000h 26.4.72/ 1838 800F_02A8 ENET MAC RMON Rx 64 byte packets (HW_ENET_MAC_RMON_R_P64) 32 R 0000_0000h 26.4.73/ 1838 800F_02AC ENET MAC RMON Rx 65 to 127 byte packets (HW_ENET_MAC_RMON_R_P65TO127) 32 R 0000_0000h 26.4.74/ 1839 800F_02B0 ENET MAC RMON Rx 128 to 255 byte packets (HW_ENET_MAC_RMON_R_P128TO255) 32 R 0000_0000h 26.4.75/ 1839 800F_02B4 ENET MAC RMON Rx 256 to 511 byte packets (HW_ENET_MAC_RMON_R_P256TO511) 32 R 0000_0000h 26.4.76/ 1840 800F_02B8 ENET MAC RMON Rx 512 to 1023 byte packets (HW_ENET_MAC_RMON_R_P512TO1023) 32 R 0000_0000h 26.4.77/ 1840 800F_02BC ENET MAC RMON Rx 1024 to 2047 byte packets (HW_ENET_MAC_RMON_R_P1024TO2047) 32 R 0000_0000h 26.4.78/ 1841 800F_02C0 ENET MAC RMON Rx packets w > 2048 bytes (HW_ENET_MAC_RMON_R_P_GTE2048) 32 R 0000_0000h 26.4.79/ 1841 800F_02C4 ENET MAC RMON Rx Octets (HW_ENET_MAC_RMON_R_OCTETS) 32 R 0000_0000h 26.4.80/ 1842 800F_02C8 ENET MAC Frames Received count drop (HW_ENET_MAC_IEEE_R_DROP) 32 R 0000_0000h 26.4.81/ 1842 800F_02CC ENET MAC Frames Received OK (HW_ENET_MAC_IEEE_R_FRAME_OK) 32 R 0000_0000h 26.4.82/ 1843 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1790 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) HW_ENET memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800F_02D0 ENET MAC Frames Received with CRC Error (HW_ENET_MAC_IEEE_R_CRC) 32 R 0000_0000h 26.4.83/ 1843 800F_02D4 ENET MAC Frames Received with Alignment Error (HW_ENET_MAC_IEEE_R_ALIGN) 32 R 0000_0000h 26.4.84/ 1844 800F_02D8 ENET MAC Frames Received overflow (HW_ENET_MAC_IEEE_R_MACERR) 32 R 0000_0000h 26.4.85/ 1844 800F_02DC ENET MAC Frames Received flow control (HW_ENET_MAC_IEEE_R_FDXFC) 32 R 0000_0000h 26.4.86/ 1845 800F_02E0 ENET MAC Frames Received error (HW_ENET_MAC_IEEE_R_OCTETS_OK) 32 R 0000_0000h 26.4.87/ 1845 800F_0400 ENET MAC IEEE1588 Timer Control Register (HW_ENET_MAC_ATIME_CTRL) 32 R/W 0000_0000h 26.4.88/ 1846 800F_0404 ENET MAC IEEE1588 Timer value Register (HW_ENET_MAC_ATIME) 32 R/W 0000_0000h 26.4.89/ 1848 800F_0408 ENET MAC IEEE1588 Offsetvalue for one-shot event generation Register (HW_ENET_MAC_ATIME_EVT_OFFSET) 32 R/W 0000_0000h 26.4.90/ 1848 800F_040C ENET MAC IEEE1588 Timer Period Register (HW_ENET_MAC_ATIME_EVT_PERIOD) 32 R/W 3B9A_CA00h 26.4.91/ 1849 800F_0410 ENET MAC IEEE1588 Correction counter wrap around value Register (HW_ENET_MAC_ATIME_CORR) 32 R/W 0000_0000h 26.4.92/ 1850 800F_0414 ENET MAC IEEE1588 Clock period of the timestamping clock (ts_clk) in nanoseconds and correction increment Register (HW_ENET_MAC_ATIME_INC) 32 R/W 0000_0000h 26.4.93/ 1851 800F_0418 ENET MAC IEEE1588 Timestamp of the last Frame Register (HW_ENET_MAC_TS_TIMESTAMP) 32 R 0000_0000h 26.4.94/ 1852 800F_0500 ENET MAC Supplemental MAC Address 0 (HW_ENET_MAC_SMAC_0_0) 32 R/W 0000_0000h 26.4.95/ 1852 800F_0504 ENET MAC Supplemental MAC Address 0 (HW_ENET_MAC_SMAC_0_1) 32 R/W 0000_0000h 26.4.96/ 1853 800F_0508 ENET MAC Supplemental MAC Address 1 (HW_ENET_MAC_SMAC_1_0) 32 R/W 0000_0000h 26.4.97/ 1853 800F_050C ENET MAC Supplemental MAC Address 1 (HW_ENET_MAC_SMAC_1_1) 32 R/W 0000_0000h 26.4.98/ 1854 800F_0510 ENET MAC Supplemental MAC Address 2 (HW_ENET_MAC_SMAC_2_0) 32 R/W 0000_0000h 26.4.99/ 1854 800F_0514 ENET MAC Supplemental MAC Address 2 (HW_ENET_MAC_SMAC_2_1) 32 R/W 0000_0000h 26.4.100/ 1855 800F_0518 ENET MAC Supplemental MAC Address 3 (HW_ENET_MAC_SMAC_3_0) 32 R/W 0000_0000h 26.4.101/ 1855 800F_051C ENET MAC Supplemental MAC Address 3 (HW_ENET_MAC_SMAC_3_1) 32 R/W 0000_0000h 26.4.102/ 1856 800F_0600 ENET MAC Compare register 0 (HW_ENET_MAC_COMP_REG_0) 32 R/W 0000_0000h 26.4.103/ 1856 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1791 Programmable Registers HW_ENET memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800F_0604 ENET MAC Compare register 1 (HW_ENET_MAC_COMP_REG_1) 32 R/W 0000_0000h 26.4.104/ 1857 800F_0608 ENET MAC Compare register 2 (HW_ENET_MAC_COMP_REG_2) 32 R/W 0000_0000h 26.4.105/ 1857 800F_060C ENET MAC Compare register 3 (HW_ENET_MAC_COMP_REG_3) 32 R/W 0000_0000h 26.4.106/ 1858 800F_0640 ENET MAC Capture register 0 (HW_ENET_MAC_CAPT_REG_0) 32 R 0000_0000h 26.4.107/ 1858 800F_0644 ENET MAC Capture register 1 (HW_ENET_MAC_CAPT_REG_1) 32 R 0000_0000h 26.4.108/ 1859 800F_0648 ENET MAC Capture register 2 (HW_ENET_MAC_CAPT_REG_2) 32 R 0000_0000h 26.4.109/ 1859 800F_064C ENET MAC Capture register 3 (HW_ENET_MAC_CAPT_REG_3) 32 R 0000_0000h 26.4.110/ 1860 800F_0680 ENET MAC IEEE1588 Interrupt register. (HW_ENET_MAC_CCB_INT) 32 R/W 0000_0000h 26.4.111/ 1860 800F_0684 ENET MAC IEEE1588 Interrupt enable mask register (HW_ENET_MAC_CCB_INT_MASK) 32 R/W 0000_0000h 26.4.112/ 1862 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1792 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.1 ENET MAC Interrupt Event Register (HW_ENET_MAC_EIR) When an event occurs that sets a bit in HW_ENET_MAC_EIR, an interrupt occurs if the corresponding bit in the interrupt mask register (HW_ENET_MAC_EIMR) is also set. Writing a 1 to an HW_ENET_MAC_EIR bit clears it; writing 0 has no effect. This register is cleared upon hardware reset. Address: 800F_0000h base + 4h offset = 800F_0004h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXF TXB RXF RXB MII RL UN PLR LC WAKEUP TS_AVAIL R EBERR RSRVD0 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 BABR BABT GRA W Reset Bit RSRVD1 TS_TIMER R W Reset 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_EIR field descriptions Field 31 RSRVD0 Description Reserved bits. Write as 0. 30 BABR Babbling receive error. This bit indicates a frame was received with length in excess of MAX_FL bytes. 29 BABT Babbling transmit error. This bit indicates the transmitted frame length exceeds MAX_FL bytes. This condition usually caused by a frame that is too long placed into the transmit data buffer(s). Truncation does not occur. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1793 Programmable Registers HW_ENET_MAC_EIR field descriptions (continued) Field Description 28 GRA Graceful stop complete. This interrupt is asserted after the transmitter is put into a pause state after completion of the frame currently being transmitted. See Graceful Transmit Stop (GTS) for conditions that lead to graceful stop. Note: The GRA interrupt is asserted only when the TX transitions into the stopped state. If this bit is cleared (by writing 1) and the TX is still stopped, the bit will not become set again. 27 TXF Transmit frame interrupt. This bit indicates a frame has been transmitted and the last corresponding buffer descriptor has been updated (Signal dma_txf_int asserted). 26 TXB Transmit buffer interrupt. This bit indicates a transmit buffer descriptor has been updated (Signal dma_txb_int asserted). 25 RXF Receive frame interrupt. This bit indicates a frame has been received and the last corresponding buffer descriptor has been updated (Signal dma_rxf_int asserted). 24 RXB Receive buffer interrupt. This bit indicates a receive buffer descriptor not the last in the frame has been updated (Signal dma_rxb_int asserted). 23 MII MII interrupt. This bit indicates the MII has completed the data transfer requested. 22 EBERR Ethernet bus error. This bit indicates a system bus error occurs when a DMA transaction is underway (Signal dma_eberr_int asserted). When the EBERR bit is set, ETHER_EN is cleared, halting frame processing by the MAC. When this occurs, software needs to insure proper actions (possibly resetting the system) to resume normal operation. 21 LC Late collision. This bit indicates a collision occurs beyond the collision window (slot time) in half duplex mode. The frame truncates with a bad CRC and the remainder of the frame is discarded. 20 RL Collision retry limit. This bit indicates a collision occurs on each of 16 successive attempts to transmit the frame. The frame is discarded without being transmitted and transmission of the next frame commences. This error can only occur in half duplex mode. 19 UN Transmit FIFO underrun. This bit indicates the transmit FIFO became empty before the complete frame was transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is discarded. 18 PLR Payload receive error. This bit indicates a frame was received with a payload length error. 17 WAKEUP Node Wake Up Request Indication. Read only status bit to indicate that a Magic Packet has been detected. Will act only if ECR(MAGIC_ENA) is 1. 16 TS_AVAIL Transmit Timestamp Available. Indicates that the timestamp of the last transmitted Timing Frame is available in the register TS_TIMESTAMP. 15 TS_TIMER The adjustable timer reached the period or offset events. RSRVD1 Reserved bits. Write as 0. 26.4.2 ENET MAC Interrupt Mask Register (HW_ENET_MAC_EIMR) Address: 800F_0000h base + 8h offset = 800F_0008h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 EIMR (bit define is same with EIR register) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1794 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) HW_ENET_MAC_EIMR field descriptions Field Description EIMR (bit define is same with EIR register) Each bit corresponds to an interrupt source defined by the EIR register. The corresponding EIMR bit determines whether an interrupt condition can generate an interrupt. At every processor clock, the EIR samples the signal generated by the interrupting source. The corresponding EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit is not set. * 0 The corresponding interrupt source is masked. * 1 The corresponding interrupt source is not masked (i.e. interrupt is enabled). 26.4.3 ENET MAC Receive Descriptor Active Register (HW_ENET_MAC_RDAR) The Receive Descriptor Active Register (RDAR) is a command register, written by the user, indicating the receive descriptor ring is updated (empty receive buffers have been produced by the driver with the empty bit set) Whenever the register is written, the RDAR bit is set. This is independent of the data actually written by the user. When set, the uDMA polls the receive descriptor ring and processes receive frames (provided ether_en is also set). Once the uDMA polls a receive descriptor whose empty bit is not set, the uDMA clears the RDAR bit and ceases receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors are placed into the receive descriptor ring. The RDAR registers are cleared at reset and when ether_en transitions from asserted to de-asserted or when the ecr_reset is set. Address: 800F_0000h base + 10h offset = 800F_0010h Bit 31 30 29 28 27 26 25 24 23 22 21 RSRVD0 19 18 17 16 0 0 0 RSRVD1 RDAR R 20 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1795 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RDAR field descriptions Field 31-25 RSRVD0 24 RDAR RSRVD1 Description Reserved bits. Write as 0. Set to 1 when this register is written, regardless of the value written. Cleared by the uDMA when no additional empty descriptors remain in the receive ring. Also cleared when ether_en transitions from asserted to de-asserted. Reserved bits. Write as 0. 26.4.4 ENET MAC Transmit Descriptor Active Register (HW_ENET_MAC_TDAR) The Transmit Descriptor Active Register (TDAR) is a command register which the user writes to indicate the transmit descriptor ring has been updated (transmit buffers have been produced by the driver with the ready bit set in the buffer descriptor) When the register is written, the TDAR bit is set. This value is independent of the data actually written by the user. When set, the uDMA polls the transmit descriptor ring and processes transmit frames (provided ether_en is also set). Once the uDMA polls a transmit descriptor that has a ready bit not set, the uDMA clears the TDAR bit and ceases transmit descriptor ring polling until the user sets the bit again to signify additional descriptors have been placed into the transmit descriptor ring. The TDAR register is cleared at reset, when ether_en transitions from asserted to de-asserted, or when the ecr_reset is set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1796 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) Address: 800F_0000h base + 14h offset = 800F_0014h Bit 31 30 29 28 27 26 25 24 23 22 21 RSRVD0 19 18 17 16 RSRVD1 TDAR R 20 W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_TDAR field descriptions Field 31-25 RSRVD0 24 TDAR RSRVD1 Description Reserved bits. Write as 0. Set to 1 when this register is written, regardless of the value written. Cleared by the uDMA when no additional ready descriptors remain in the transmit ring. Also cleared when ether_en transitions from asserted to de-asserted. Reserved bits. Write as 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1797 Programmable Registers 26.4.5 ENET MAC Control Register (HW_ENET_MAC_ECR) To clear any of the event bits within the Interrupt Event Register (EIR), the register must be written with a '1' in the corresponding bit position. Address: 800F_0000h base + 24h offset = 800F_0024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLEEP MAGIC_ENA ETHER_EN RESET Bit 1 0 0 0 0 0 0 0 0 0 RSRVD0 DBG_EN R RSRVD0 Reset ENA_1588 W W Reset 0 0 0 0 0 0 0 HW_ENET_MAC_ECR field descriptions Field Description 31-7 RSRVD0 Reserved bits. Write as 0. 6 DBG_EN Enables the debug input pin mac_freeze. When set, the input has an effect. When cleared (0, reset value) the input pin has no effect. 5 RSRVD0 Reserved bits. Write as 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1798 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) HW_ENET_MAC_ECR field descriptions (continued) Field Description 4 ENA_1588 IEEE1588 Enable. Should be set to '1' to enable the Frame Time Stamping functions. Also drives the DMA control bit ena_1588. 3 SLEEP Put controller in Sleep Mode. When asserted (Set to 1) the controller is configured in sleep mode. When set to 0 (Reset value) the controller is in normal operating mode. 2 MAGIC_ENA Enable Magic Packet Detection. When set to 1, the controller detects Magic Packets and will assert the EIR (WAKEUP) bit when a frame is detected. When set to 0 (Reset value) the Magic Detection logic is disabled. Note: MAGIC_ENA is relevant only if the SLEEP bit is 1. If set to 1, changing the SLEEP bit will enable or disable both sleep mode and magic packet detection. 1 ETHER_EN When this bit is set, MAC is enabled, and reception and transmission are possible. When this bit is cleared, reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. When ETHER_EN is cleared, the DMA, buffer descriptor, and FIFO control logic are reset, including the buffer descriptor and FIFO pointers. Hardware alters the ETHER_EN bit under the following conditions: RESET is set by software, in which case ETHER_EN is cleared An error condition causes the EBERR bit to set, in which case ETHER_EN is cleared 0 RESET The behavior of ENET-MAC when set this bit is depend on Switch mode. If disable switch, assert this bit will reset MAC and UDMA. If enable switch, assert this bit will only reset MAC. UDMA will be reset by software reset of switch. 26.4.6 ENET MAC MII Management Frame Register (HW_ENET_MAC_MMFR) MDIO Management Register Performing a write to the MMFR register triggers a management frame transaction to the PHY device unless the MSCR is programmed to 0. If the MSCR register is written to a non-zero value in the case of writing to MMFR when MSCR equals 0, an MII frame is generated with the data previously written to the MMFR. This allows MMFR and MSCR to be programmed in either order if MSCR is currently zero. If the MMFR register is written while frame generation is in progress, the frame contents are altered. Software must use the EIR(MII) interrupt indication to avoid writing to the MMFR register while frame generation is in progress. Address: 800F_0000h base + 40h offset = 800F_0040h Bit R W 31 Reset 0 30 ST 0 29 28 27 26 OP 0 0 25 24 23 22 21 PA 0 0 0 20 19 18 RA 0 0 0 0 0 17 16 15 14 13 12 11 10 9 TA 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DATA 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1799 Programmable Registers HW_ENET_MAC_MMFR field descriptions Field Description 31-30 ST Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII management frame. 29-28 OP Operation code: 00 Write frame operation, but not MII compliant. 01 Write frame operation for a valid MII management frame. 10 Read frame operation for a valid MII management frame. 11 Read frame operation, but not MII compliant. 27-23 PA PHY address. This field specifies one of up to 32 attached PHY devices. 22-18 RA Register address. This field specifies one of up to 32 registers within the specified PHY device. 17-16 TA Turn around. This field must be programmed to '10' to generate a valid MII management frame. DATA Management frame data. This is the field for data to be written to or read from the PHY register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1800 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.7 ENET MAC MII Speed Control Register (HW_ENET_MAC_MSCR) Address: 800F_0000h base + 44h offset = 800F_0044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSRVD1 Reset RSRVD0 R DIS_ PRE HOLDTIME MII_SPEED W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_MSCR field descriptions Field 31-11 RSRVD0 10-8 HOLDTIME Description Reserved bits. Write as 0. The IEEE802.3 Clause 22 defines a minimum of 10ns for the holdtime on the MDIO output. Depending on the host bus frequency the setting may need to be increased. The following Bit 10:8: MDIO hold time setting: 000 : 1 pclk cycle (default) 001 : 2 pclk cycles 010 : 3 pclk cycles 011 : 4 pclk cycles 100 : 5 pclk cycles 101 : 6 pclk cycles 110 : 7 pclk cycles 111 : 8 pclk cycles 7 DIS_PRE 6-1 MII_SPEED 0 RSRVD1 Asserting this bit causes preamble (32 1s) not to be prepended to the MII management frame. The MII standard allows the preamble to be dropped if the attached PHY device(s) does not require it. MII_SPEED controls the frequency of the MII management interface clock (Signal mdc) relative to the internal bus clock (pclk). A value of 0 in this field turns off the mdc and leaves it in low voltage state. Any non-zero value results in the mdc frequency of 1/(MII_SPEED x 2) of the internal bus frequency (Clock pclk). Reserved bits. Write as 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1801 Programmable Registers 26.4.8 ENET MAC MIB Control/Status Register (HW_ENET_MAC_MIBC) Address: 800F_0000h base + 64h offset = 800F_0064h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 MIB_DIS MIB_ IDLE MIB_CLEAR R 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset Bit RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_MIBC field descriptions Field Description 31 MIB_DIS A read/write control bit. If set, the MIB logic halts and does not update any MIB counters. 30 MIB_IDLE A read-only status bit. If set the MIB block is not currently updating any MIB counters. 29 MIB_CLEAR RSRVD0 A read/write control bit. If set all statistics counters are reset to 0. Reserved bits. Write as 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1802 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.9 ENET MAC Receive Control Register (HW_ENET_MAC_RCR) 0 0 0 0 1 0 1 1 15 14 13 12 11 10 9 8 PAD_EN RSRVD0 RSRVD0 RMII_10T RMII_MODE R 25 24 21 20 19 18 17 16 1 1 0 1 1 1 0 7 6 5 4 3 2 1 0 FCE BC_ REJ DRT LOOP 0 PAUSE_FWD Bit 26 MII_MODE NO_LGTH_CHECK Reset 27 PROM GRS 0 0 0 0 0 0 W 28 RSRVD0 30 R 29 RSRVD0 31 CRC_FWD Bit CNTL_FRM_ENA Address: 800F_0000h base + 84h offset = 800F_0084h 23 22 0 0 0 0 0 1 MAX_FL W Reset 0 0 0 0 HW_ENET_MAC_RCR field descriptions Field 31 GRS 30 NO_LGTH_ CHECK 29-16 MAX_FL Description Graceful receive stopped. Read-only status indicating that the MAC receive datapath is stopped Payload Length Check Disable. When set to 1, the controller checks the frame's payload length with the Frame Length/Type field. When set to 0 (Reset value) the payload length check is disabled Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt to occur. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1803 Programmable Registers HW_ENET_MAC_RCR field descriptions (continued) Field Description Receive frames longer than MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame receive buffer descriptor. Set to 1518 (Decimal) after reset. 15 CNTL_FRM_ ENA 14 CRC_FWD MAC Control Frame Enable. When set to 1, MAC Control frames with any Opcode other than 0x01 (Pause Frame) are silently discarded. When set to 0 (Reset value), MAC Control frames with any Opcode other than 0x01 are accepted and forwarded to the Client interface. Terminate / Forward Received CRC. If cleared (Reset value 0) the CRC field of received frames is transmitted to the user application. If set to 1 the CRC field is stripped from the frame. Note: If padding function is enabled (Bit PAD_EN set to 1), CRC_FWD is ignored and the CRC field is checked and always terminated and removed. 13 PAUSE_FWD Terminate / Forward Pause Frames. If enabled (Set to 1) pause frames are forwarded to the user application. In normal mode (Set to reset value 0) pause frames are terminated and discarded in the MAC. 12 PAD_EN Enable / Disable Frame Padding Remove on receive. If enabled (Set to 1) padding is removed from received frames. If disabled (set to reset value 0) no padding is removed on receive by the MAC. 11 RSRVD0 Reserved bits. Write as 0. 10 RSRVD0 Reserved bits. Write as 0. 9 RMII_10T RMII 10-Base T. Enables 10Mbps mode of the RMII. When set to 1, the controller signal set_10 is set to 1, when set to 0 set_10 is set to 0. 8 RMII_MODE RMII Mode Enable. Indicates, when ECR(ETH_SPEED) is set to 0, if the MAC is in RMII or MII. 0 MAC configured for MII mode. 1 MAC configured for RMII operation. When set to 1, the controller signal ena_rmii is set to 1, when set to 0, ena_rmii is set to 0. 7 RSRVD0 Reserved bits. Write as 0. 6 RSRVD0 Reserved bits. Write as 0. 5 FCE Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame detection, the transmitter will stop transmitting data frames for a given duration. 4 BC_REJ Broadcast frame reject. If asserted, frames with DA (destination address) equals 0xFFFFFFFFFFFF are rejected unless the PROM bit is set. If both BC_REJ and PROM equals 1, frames with broadcast DA are accepted and the M (MISS) is set in the receive buffer descriptor. 3 PROM 2 MII_MODE 1 DRT Promiscuous mode. All frames are accepted regardless of address matching. Media independent interface mode. Should always be set to 1, setting MII_MODE to 0 has no effect. Disable receive on transmit. 0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode). 1 Disable reception of frames while transmitting (normally used for half duplex mode). 0 LOOP Internal loopback. If set, transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. When asserted the controller signal ena_loop is set to 1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1804 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.10 ENET MAC Transmit Control Register (HW_ENET_MAC_TCR) Address: 800F_0000h base + C4h offset = 800F_00C4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TFC_PAUSE FEDN 0 0 0 0 0 RSRVD0 R TX_ADDR_SEL RSRVD0 0 RFC_PAUSE Bit 0 TX_ADDR_INS Reset TX_CRC_FWD W GTS W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_TCR field descriptions Field 31-10 RSRVD0 9 TX_CRC_FWD Description Reserved bits. Write as 0. Forward frame from application with CRC. When set (1) the transmitter will not append any CRC to transmitted frames as it is expecting a frame with crc from the application. When cleared (0, default) the toplevel input pin ff_tx_crc_fwd controls if the frame has a crc from the application (1) or not (0) (i.e. the register bit is OR'ed with ff_tx_crc_fwd input). 8 TX_ADDR_INS Set MAC address on transmit. If enabled (Set to 1) the MAC overwrites the source MAC address with the programmed MAC address according to TX_ADDR_SEL. If disabled (Set to reset value 0), the source MAC address is not modified by the MAC. 7-5 Source MAC address select on transmit. If register TX_ADDR_INS is set to 1 the MAC address that is TX_ADDR_SEL used to overwrite the source MAC address: Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1805 Programmable Registers HW_ENET_MAC_TCR field descriptions (continued) Field Description 000: Node MAC Address programmed on PADDR1/2 registers is used as the source address. 100: Supplemental MAC Address 0 programmed on SMAC_0_0 and SMAC_0_1 registers is used as the source address. 101: Supplemental MAC Address 1 programmed on SMAC_1_0 and SMAC_1_1 registers is used as the source address. 110: Supplemental MAC Address 2 programmed on SMAC_2_0 and SMAC_2_1 registers is used as the source address. other (any value other than above): Supplemental MAC Address 3 programmed on SMAC_3_0 and SMAC_3_1 registers is used as the source address. 4 RFC_PAUSE Receive frame control pause. This read-only status bit is asserted when a full duplex flow control pause frame is received and the transmitter pauses for the duration defined in this pause frame. This bit automatically clears when the pause duration is complete. 3 TFC_PAUSE Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC stops transmission of data frames after the current transmission is complete. At this time, GRA interrupt in the EIR register is asserted. With transmission of data frames stopped, MAC transmits a MAC Control PAUSE frame. Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data frames. If the transmitter pauses due to user assertion of GTS or reception of a PAUSE frame, the MAC may continue transmitting a MAC Control PAUSE frame. 2 FEDN Full duplex enable. If set, frames transmit independent of carrier sense and collision inputs. This bit should only be modified when ETHER_EN is cleared. 1 RSRVD0 Reserved bits. Write as 0. 0 GTS Graceful transmit stop. When this bit is set, MAC stops transmission after any frame currently transmitted is complete and GRA interrupt in the EIR register is asserted. If frame transmission is not currently underway, the GRA interrupt will be asserted immediately. Once transmission has completed, a restart can accomplish by clearing the GTS bit. The next frame in the transmit FIFO is then transmitted. If an early collision occurs during transmission when GTS equals 1, transmission stops after the collision. The frame is transmitted again once GTS is cleared. There may be old frames in the transmit FIFO that transmit when GTS is reasserted. To avoid this, clear the ECR register bit ETHER_EN following the GRA interrupt. 26.4.11 ENET MAC Physical Address Lower Register (HW_ENET_MAC_PALR) Address: 800F_0000h base + E4h offset = 800F_00E4h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PADDR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_PALR field descriptions Field PADDR1 Description Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact match and the source address field in PAUSE frames. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1806 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.12 ENET MAC Physical Address Upper Register (HW_ENET_MAC_PAUR) Address: 800F_0000h base + E8h offset = 800F_00E8h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PADDR2 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 TYPE 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 HW_ENET_MAC_PAUR field descriptions Field Description 31-16 PADDR2 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames. TYPE Type field in PAUSE frames. These 16-bits are a constant value of 0x8808 (not writeable). 26.4.13 ENET MAC Opcode/Pause Duration Register (HW_ENET_MAC_OPD) Address: 800F_0000h base + ECh offset = 800F_00ECh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 OPCODE R 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PAUSE_DUR W Reset 9 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_OPD field descriptions Field Description 31-16 OPCODE Opcode field used in PAUSE frames. These bits are a constant, 0x01 (not writeable). PAUSE_DUR Pause Duration field used in PAUSE frames. 26.4.14 ENET MAC Descriptor Individual Upper Address Register (HW_ENET_MAC_IAUR) Address: 800F_0000h base + 118h offset = 800F_0118h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADDR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1807 Programmable Registers HW_ENET_MAC_IAUR field descriptions Field Description IADDR1 The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32. 26.4.15 ENET MAC Descriptor Individual Lower Address Register (HW_ENET_MAC_IALR) Address: 800F_0000h base + 11Ch offset = 800F_011Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADDR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IALR field descriptions Field Description IADDR2 The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0. 26.4.16 ENET MAC Descriptor Group Upper Address Register (HW_ENET_MAC_GAUR) Address: 800F_0000h base + 120h offset = 800F_0120h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GADDR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_GAUR field descriptions Field Description GADDR1 The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1808 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.17 ENET MAC Descriptor Group Lower Address Register (HW_ENET_MAC_GALR) Address: 800F_0000h base + 124h offset = 800F_0124h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GADDR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_GALR field descriptions Field Description GADDR2 The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0. 26.4.18 ENET MAC Transmit FIFO Watermark and Store and Forward Control Register (HW_ENET_MAC_TFW_SFCR) Address: 800F_0000h base + 144h offset = 800F_0144h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSRVD0 R STR_ FWD W Reset 0 0 0 0 0 0 0 0 RSRVD1 0 0 TFWR 0 0 0 0 HW_ENET_MAC_TFW_SFCR field descriptions Field 31-9 RSRVD0 8 STR_FWD 7-6 RSRVD1 TFWR Description Reserved bits. Write as 0. Store and Forward Enable. When set to 1, Store and Forward is enabled, when set to 0 (Reset value), the transmission start threshold is programmed with the TFWR bits. Reserved bits. Write as 0. When STR_FWD is set to 0, number of bytes, in steps of 64 Bytes, written to transmit FIFO before transmission of a frame begins: 000000 64 bytes written 000001 64 bytes written Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1809 Programmable Registers HW_ENET_MAC_TFW_SFCR field descriptions (continued) Field Description 000010 128 bytes written 000011 192 bytes written 000100 256 bytes written 000101 320 bytes written 000110 384 bytes written ...... 111110 3968 bytes written 111111 4032 bytes written Note: if a frame with less than the threshold is written it will still be sent, independently of this threshold setting. The threshold is only relevant if the frame is larger than the threshold given. 26.4.19 ENET MAC FIFO Receive Bound Register (HW_ENET_MAC_FRBR) Address: 800F_0000h base + 14Ch offset = 800F_014Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 1 0 RSRVD0 R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RSRVD0 R R_BOUND W Reset 0 0 0 0 RSRVD1 0 1 1 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_FRBR field descriptions Field 31-10 RSRVD0 9-2 R_BOUND RSRVD1 Description Reserved bits. Write as 0. Read-only. Highest valid FIFO RAM address. Set to 01100000 to provide software compatibility with existing devices. Reserved bits. Write as 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1810 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.20 ENET MAC FIFO Receive FIFO Start Register (HW_ENET_MAC_FRSR) Address: 800F_0000h base + 150h offset = 800F_0150h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD1 Reset RSRVD0 R RSRVD2 R_FSTART W Reset 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 HW_ENET_MAC_FRSR field descriptions Field Description 31-11 RSRVD0 Reserved bits. Write as 0. 10 RSRVD1 Must be set. Not used, implemented for software compatibility. 9-2 R_FSTART Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. For proper operation, ensure that R_FSTART is set to 0x48 or greater. Read/write: Not used, implemented for software compatibility. RSRVD2 Reserved bits. Write as 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1811 Programmable Registers 26.4.21 ENET MAC Pointer to Receive Descriptor Ring Register (HW_ENET_MAC_ERDSR) The user writes the ERDSR. It provides a pointer to the start of the circular receive buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however it is recommended it be made 128-bit aligned (evenly divisible by 16).The user should write bits 1 and 0 to 0. Hardware ignores non-zero values in these two bit positions. Address: 800F_0000h base + 180h offset = 800F_0180h Bit 31 30 29 28 27 26 25 R Bit 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RSRVD0 R_DES_START W Reset 23 R_DES_START W Reset 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_ERDSR field descriptions Field Description 31-2 Pointer to start of receive buffer descriptor queue. R_DES_START RSRVD0 Reserved bits. Write as 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1812 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.22 ENET MAC Pointer to Transmit Descriptor Ring Register (HW_ENET_MAC_ETDSR) The user writes the ETDSR. It provides a pointer to the start of the circular transmit buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16). The user should write bits 1 and 0 to 0. Hardware ignores non-zero values in these two bit positions. Address: 800F_0000h base + 184h offset = 800F_0184h Bit 31 30 29 28 27 26 25 R Bit 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RSRVD0 X_DES_START W Reset 23 X_DES_START W Reset 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_ETDSR field descriptions Field Description 31-2 Pointer to start of transmit buffer descriptor queue. X_DES_START RSRVD0 Reserved bits. Write as 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1813 Programmable Registers 26.4.23 ENET MAC Maximum Receive Buffer Size Register (HW_ENET_MAC_EMRBR) The EMRBR is a user-programmable register that dictates the maximum size of all receive buffers. Note that because receive frames are truncated at 2k-15bytes, only bits 10-4 are used. This value should take into consideration that the receive CRC is always written into the last receive buffer. To allow on maximum size frame per buffer, EMRBR must be set to RCR[MAX_FL] or larger. The EMRBR must be evenly divisible by 16. To ensure this, bits 3-0 are forced low. To minimize bus utilization (descriptor fetches), it is recommended that EMRBR be greater than or equal to 256 bytes. Address: 800F_0000h base + 188h offset = 800F_0188h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 RSRVD1 R_BUF_SIZE W Reset 8 0 0 0 0 0 0 1 0 HW_ENET_MAC_EMRBR field descriptions Field Description 31-11 RSRVD0 Reserved bits. Write as 0. 10-4 R_BUF_SIZE Receive buffer size in bytes. 0x00 0 bytes 0x01 16 bytes 0x02 32 bytes ... 0x7F 2032 bytes RSRVD1 Reserved bits. Write as 0. 26.4.24 ENET MAC Receive FIFO Section Full Threshold Register (HW_ENET_MAC_RX_SECTION_FULL) Address: 800F_0000h base + 190h offset = 800F_0190h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 RX_SECTION_FULL W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1814 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) HW_ENET_MAC_RX_SECTION_FULL field descriptions Field Description 31-8 RSRVD0 Reserved bits. Write as 0. RX_SECTION_ Value, in 64-Bit words, of the Receive FIFO section full threshold. FULL 26.4.25 ENET MAC Receive FIFO Section Empty Threshold Register (HW_ENET_MAC_RX_SECTION_EMPTY) Address: 800F_0000h base + 194h offset = 800F_0194h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 RX_SECTION_EMPTY W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RX_SECTION_EMPTY field descriptions Field Description 31-8 RSRVD0 Reserved bits. Write as 0. RX_SECTION_ Value, in 64-Bit words, of the Receive FIFO section empty threshold. EMPTY 26.4.26 ENET MAC Receive FIFO Almost Empty Threshold Register (HW_ENET_MAC_RX_ALMOST_EMPTY) Address: 800F_0000h base + 198h offset = 800F_0198h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 RX_ALMOST_EMPTY W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 HW_ENET_MAC_RX_ALMOST_EMPTY field descriptions Field 31-8 RSRVD0 RX_ALMOST_ EMPTY Description Reserved bits. Write as 0. Value, in 64-Bit words, of the Receive FIFO almost empty threshold. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1815 Programmable Registers 26.4.27 ENET MAC Receive FIFO Almost Full Thresholdt Register (HW_ENET_MAC_RX_ALMOST_FULL) Address: 800F_0000h base + 19Ch offset = 800F_019Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 RX_ALMOST_FULL W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 HW_ENET_MAC_RX_ALMOST_FULL field descriptions Field Description 31-8 RSRVD0 Reserved bits. Write as 0. RX_ALMOST_ FULL Value, in 64-Bit words, of the Receive FIFO almost full threshold. 26.4.28 ENET MAC Transmit FIFO Section Empty Threshold Register (HW_ENET_MAC_TX_SECTION_EMPTY) Address: 800F_0000h base + 1A0h offset = 800F_01A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 TX_SECTION_EMPTY W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_TX_SECTION_EMPTY field descriptions Field 31-8 RSRVD0 TX_SECTION_ EMPTY Description Reserved bits. Write as 0. Value, in 64-Bit words, of the Transmit FIFO section empty threshold. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1816 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.29 ENET MAC Transmit FIFO Almost Empty Threshold Register (HW_ENET_MAC_TX_ALMOST_EMPTY) Address: 800F_0000h base + 1A4h offset = 800F_01A4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 TX_ALMOST_EMPTY W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 HW_ENET_MAC_TX_ALMOST_EMPTY field descriptions Field Description 31-8 RSRVD0 Reserved bits. Write as 0. TX_ALMOST_ EMPTY Value, in 64-Bit words, of the Transmit FIFO almost empty threshold. 26.4.30 ENET MAC Transmit FIFO Almost Full Threshold Register (HW_ENET_MAC_TX_ALMOST_FULL) Address: 800F_0000h base + 1A8h offset = 800F_01A8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 TX_ALMOST_FULL W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 HW_ENET_MAC_TX_ALMOST_FULL field descriptions Field 31-8 RSRVD0 TX_ALMOST_ FULL Description Reserved bits. Write as 0. Value, in 64-Bit words, of the Transmit FIFO almost full threshold. The number of bits, K, is Log2 of the Transmit FIFO depth. A minimum value of 6 is required to have correct ff_tx_rdy deassertion before the fifo overflows. If a lower value is set, the FIFO will overflow when ff_tx_rdy is deasserted, hence there would be no time for the application to react properly. A recommended value of at least 8 should be set allowing a latency of 2 clock cycles to the application. If more latency is required the value can be increased as necessary (latency=TX_ALMOST_FULL-5). Note that a FIFO overflow is a fatal error and requires a global reset on the transmit datapath or at least deassertion of ETHER_EN. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1817 Programmable Registers 26.4.31 ENET MAC Transmit Inter-Packet Gap Register (HW_ENET_MAC_TX_IPG_LENGTH) Address: 800F_0000h base + 1ACh offset = 800F_01ACh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 TX_IPG_ LENGTH W Reset 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 HW_ENET_MAC_TX_IPG_LENGTH field descriptions Field Description 31-5 RSRVD0 Reserved bits. Write as 0. TX_IPG_ LENGTH Transmit Inter Packet Gap. Set, in Bytes, the IPG between transmitted Frames. Can be set to any value between 8 and 27. If set to a Value below 8, the IPG is 8, if set to any value above 27, the IPG is 27. 26.4.32 ENET MAC Frame Truncation Length Register (HW_ENET_MAC_TRUNC_FL) Address: 800F_0000h base + 1B0h offset = 800F_01B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 1 1 1 1 1 TRUNC_FL W Reset 8 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 HW_ENET_MAC_TRUNC_FL field descriptions Field 31-14 RSRVD0 TRUNC_FL Description Reserved bits. Write as 0. Frame Truncation Length. Set the value from which a receive Frame is truncated (if greater than this value). Should be a value greater or equal to RCR(MAX_FL). Note: Truncation happens at TRUNC_FL, however when truncation occured, the application (FIFO) may receive less data, guaranteeing that it will never receive more than the set limit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1818 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.33 ENET MAC Accelerator Transmit Function Configuration Register (HW_ENET_MAC_IPACCTXCONF) Transmit Accelerator function configuration. Control accelerator actions to be performed when sending frames. The register can be changed before or after each frame, but must stay unmodified during frame write into the transmit FIFO. Address: 800F_0000h base + 1C0h offset = 800F_01C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 RSRVD1 0 0 SHIFT16 RSRVD0 R TX_IPCHK_INS Bit 0 TX_PROTCHK_INS Reset 0 0 0 HW_ENET_MAC_IPACCTXCONF field descriptions Field 31-5 RSRVD0 Description Reserved bits. Write as 0. 4 Enable insertion of protocol checksum. If enabled (1) and an IP frame with a known protocol is TX_PROTCHK_ transmitted, the checksum will be inserted automatically into the frame. The checksum field should be all INS zero. Other frames are not modified. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1819 Programmable Registers HW_ENET_MAC_IPACCTXCONF field descriptions (continued) Field Description The setting is OR'ed with the pin ff_tx_protchk_ins. 3 Enable insertion of IP header checksum. If enabled (1) and an IP frame is transmitted, its checksum will TX_IPCHK_INS be inserted automatically. The IP header checksum field should be all zero. If a non-IP frame is transmitted the frame will not be modified. The setting is OR'ed with the pin ff_tx_ipchk_ins. 2-1 RSRVD1 Reserved bits. Write as 0. 0 SHIFT16 Enable TX FIFO Shift16 function. Indicates to the transmit data FIFO, that the frame will be written with 2 additional octets before the frame data. This means the actual Frame starts at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory as the 14-byte Ethernet header is extended to a 16 byte header. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1820 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.34 ENET MAC Accelerator Receive Function Configuration Register (HW_ENET_MAC_IPACCRXCONF) Address: 800F_0000h base + 1C4h offset = 800F_01C4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RX_IPERR_DISCARD RX_IP_PAD_REMOVE 0 0 0 RSRVD0 R RX_LINEERR_DISC Bit 0 SHIFT16 Reset RX_PROTERR_DISCARD W 0 0 W Reset 0 0 0 0 0 0 0 0 RSRVD1 0 0 0 HW_ENET_MAC_IPACCRXCONF field descriptions Field Description 31-8 RSRVD0 Reserved bits. Write as 0. 7 SHIFT16 If set 1, instructs the MAC to write 2 additional bytes in front of each frame received into the RX FIFO. The actual frame data then starts at bit 16 of the first word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary. Note: If this function only affects the FIFO storage and has no influence on the statistics, which still use the actual length of the frame received. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1821 Programmable Registers HW_ENET_MAC_IPACCRXCONF field descriptions (continued) Field Description 6 RX_LINEERR_ DISC 5-3 RSRVD1 Enable discard of frames with MAC layer errors. If set any frame received with a CRC, length or PHY error is automatically discarded and not forwarded to the user application interface. See 12.4 page 55. Reserved bits. Write as 0. 2 Enable discard of frames with wrong protocol checksum. RX_PROTERR_ If set and TCP/IP, UDP/IP or ICMP/IP frame is received that has a wrong TCP or UDP or ICMP checksum DISCARD the frame is discarded. Discarding is only available when the RX FIFO operates in Store and Forward mode. 1 RX_IPERR_ DISCARD Enable discard of frames with wrong IPv4 header checksum. If set and an IPv4 frame is received with a mismatching header checksum, the frame will be discarded. IPv6 has no header checksum and will therefore not be affected by this setting. Discarding is only available when the RX FIFO operates in Store and Forward mode. 0 RX_IP_PAD_ REMOVE Enable padding removal for short IP frames. If set any bytes following the IP payload section of the frame are removed from the frame. 26.4.35 ENET MAC RMON Tx packet drop (HW_ENET_MAC_RMON_T_DROP) Count of frames not counted correctly Note: Counter not implemented (read 0 always) as not applicable Address: 800F_0000h base + 200h offset = 800F_0200h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_DROP R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_DROP field descriptions Field Description RMON_T_DROP Reserved (this counter not implemented) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1822 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.36 ENET MAC RMON Tx packet count (HW_ENET_MAC_RMON_T_PACKETS) Address: 800F_0000h base + 204h offset = 800F_0204h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_PACKETS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_PACKETS field descriptions Field Description RMON_T_ PACKETS ENET MAC RMON Tx packet count 26.4.37 ENET MAC RMON Tx Broadcast Packets (HW_ENET_MAC_RMON_T_BC_PKT) Address: 800F_0000h base + 208h offset = 800F_0208h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_BC_PKT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_BC_PKT field descriptions Field Description RMON_T_BC_ PKT ENET MAC RMON Tx Broadcast Packets count 26.4.38 ENET MAC RMON Tx Multicast Packets (HW_ENET_MAC_RMON_T_MC_PKT) Address: 800F_0000h base + 20Ch offset = 800F_020Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_MC_PKT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1823 Programmable Registers HW_ENET_MAC_RMON_T_MC_PKT field descriptions Field Description RMON_T_MC_ PKT Count of ENET MAC RMON Tx Multicast Packets 26.4.39 ENET MAC RMON Tx Packets w CRC/Align error (HW_ENET_MAC_RMON_T_CRC_ALIGN) Address: 800F_0000h base + 210h offset = 800F_0210h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_CRC_ALIGN R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_CRC_ALIGN field descriptions Field Description RMON_T_CRC_ Count of ENET MAC RMON Tx Packets w CRC/Align error ALIGN 26.4.40 ENET MAC RMON Tx Packets < 64 bytes, good CRC (HW_ENET_MAC_RMON_T_UNDERSIZE) Address: 800F_0000h base + 214h offset = 800F_0214h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_UNDERSIZE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_UNDERSIZE field descriptions Field RMON_T_ UNDERSIZE Description Count of ENET MAC RMON Tx Packets < 64 bytes, good CRC i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1824 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.41 ENET MAC RMON Tx Packets > MAX_FL bytes, good CRC (HW_ENET_MAC_RMON_T_OVERSIZE) Address: 800F_0000h base + 218h offset = 800F_0218h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_OVERSIZE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_OVERSIZE field descriptions Field Description RMON_T_ OVERSIZE Count of ENET MAC RMON Tx Packets > MAX_FL bytes, good CRC 26.4.42 ENET MAC RMON Tx Packets < 64 bytes, bad CRC (HW_ENET_MAC_RMON_T_FRAG) Address: 800F_0000h base + 21Ch offset = 800F_021Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_FRAG R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_FRAG field descriptions Field Description RMON_T_FRAG Count of ENET MAC RMON Tx Packets < 64 bytes, bad CRC 26.4.43 ENET MAC RMON Tx Packets > MAX_FL bytes, bad CRC (HW_ENET_MAC_RMON_T_JAB) Address: 800F_0000h base + 220h offset = 800F_0220h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_JAB R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1825 Programmable Registers HW_ENET_MAC_RMON_T_JAB field descriptions Field Description RMON_T_JAB Count of ENET MAC RMON Tx Packets > MAX_FL bytes, bad CRC 26.4.44 ENET MAC RMON Tx collision count (HW_ENET_MAC_RMON_T_COL) Address: 800F_0000h base + 224h offset = 800F_0224h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_COL R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_COL field descriptions Field Description RMON_T_COL ENET MAC RMON Tx collision count 26.4.45 ENET MAC RMON Tx 64 byte packets (HW_ENET_MAC_RMON_T_P64) Address: 800F_0000h base + 228h offset = 800F_0228h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_P64 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_P64 field descriptions Field RMON_T_P64 Description Count of ENET MAC RMON Tx 64 byte packets i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1826 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.46 ENET MAC RMON Tx 65 to 127 byte packets (HW_ENET_MAC_RMON_T_P65TO127N) Address: 800F_0000h base + 22Ch offset = 800F_022Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_P65TO127N R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_P65TO127N field descriptions Field Description RMON_T_ P65TO127N Count of ENET MAC RMON Tx 65 to 127 byte packets 26.4.47 ENET MAC RMON Tx 128 to 255 byte packets (HW_ENET_MAC_RMON_T_P128TO255N) ENET MAC RMON Tx 128 to 255 byte packets Address: 800F_0000h base + 230h offset = 800F_0230h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_P128TO255N R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_P128TO255N field descriptions Field Description RMON_T_ P128TO255N Count of ENET MAC RMON Tx 128 to 255 byte packets 26.4.48 ENET MAC RMON Tx 256 to 511 byte packets (HW_ENET_MAC_RMON_T_P256TO511) Address: 800F_0000h base + 234h offset = 800F_0234h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_P256TO511 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1827 Programmable Registers HW_ENET_MAC_RMON_T_P256TO511 field descriptions Field Description RMON_T_ P256TO511 Count of ENET MAC RMON Tx 256 to 511 byte packets 26.4.49 ENET MAC RMON Tx 512 to 1023 byte packets (HW_ENET_MAC_RMON_T_P512TO1023) Address: 800F_0000h base + 238h offset = 800F_0238h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_P512TO1023 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_P512TO1023 field descriptions Field Description RMON_T_ P512TO1023 Count of ENET MAC RMON Tx 512 to 1023 byte packets 26.4.50 ENET MAC RMON Tx 1024 to 2047 byte packets (HW_ENET_MAC_RMON_T_P1024TO2047) Address: 800F_0000h base + 23Ch offset = 800F_023Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_P1024TO2047 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_P1024TO2047 field descriptions Field RMON_T_ P1024TO2047 Description Count of ENET MAC RMON Tx 1024 to 2047 byte packets i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1828 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.51 ENET MAC RMON Tx packets w > 2048 bytes (HW_ENET_MAC_RMON_T_P_GTE2048) Address: 800F_0000h base + 240h offset = 800F_0240h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_P_GTE2048 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_P_GTE2048 field descriptions Field Description RMON_T_P_ GTE2048 Count of ENET MAC RMON Tx packets w > 2048 bytes 26.4.52 ENET MAC RMON Tx Octets (HW_ENET_MAC_RMON_T_OCTETS) Address: 800F_0000h base + 244h offset = 800F_0244h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_T_OCTETS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_T_OCTETS field descriptions Field RMON_T_ OCTETS Description Count of ENET MAC RMON Tx Octets 26.4.53 ENET MAC Frames Transmitted count drop (HW_ENET_MAC_IEEE_T_DROP) Count of frames not counted correctly Note: Counter not implemented (read 0 always) as not appl i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1829 Programmable Registers Address: 800F_0000h base + 248h offset = 800F_0248h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_DROP R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_DROP field descriptions Field Description IEEE_T_DROP Reserved (this counter not implemented) 26.4.54 ENET MAC Frames Transmitted OK (HW_ENET_MAC_IEEE_T_FRAME_OK) Address: 800F_0000h base + 24Ch offset = 800F_024Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_FRAME_OK R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_FRAME_OK field descriptions Field Description IEEE_T_ FRAME_OK Count of ENET MAC Frames Transmitted OK 26.4.55 ENET MAC Frames Transmitted with Single Collision (HW_ENET_MAC_IEEE_T_1COL) Address: 800F_0000h base + 250h offset = 800F_0250h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_1COL R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_1COL field descriptions Field IEEE_T_1COL Description Count of ENET MAC Frames Transmitted with Single Collision i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1830 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.56 ENET MAC Frames Transmitted with Multiple Collisions (HW_ENET_MAC_IEEE_T_MCOL) Address: 800F_0000h base + 254h offset = 800F_0254h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_MCOL R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_MCOL field descriptions Field Description IEEE_T_MCOL Count of ENET MAC Frames Transmitted with Multiple Collisions 26.4.57 ENET MAC Frames Transmitted after Deferral Delay (HW_ENET_MAC_IEEE_T_DEF) Address: 800F_0000h base + 258h offset = 800F_0258h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_DEF R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_DEF field descriptions Field Description IEEE_T_DEF ENET MAC Frame count Transmitted after Deferral Delay 26.4.58 ENET MAC Frames Transmitted with Late Collision (HW_ENET_MAC_IEEE_T_LCOL) Address: 800F_0000h base + 25Ch offset = 800F_025Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_LCOL R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1831 Programmable Registers HW_ENET_MAC_IEEE_T_LCOL field descriptions Field Description IEEE_T_LCOL Count of ENET MAC Frames Transmitted with Late Collision 26.4.59 ENET MAC Frames Transmitted with Excessive Collisions (HW_ENET_MAC_IEEE_T_EXCOL) Address: 800F_0000h base + 260h offset = 800F_0260h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_EXCOL R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_EXCOL field descriptions Field Description IEEE_T_EXCOL Count of ENET MAC Frames Transmitted with Excessive Collisions 26.4.60 ENET MAC Frames Transmitted with Tx FIFO Underrun (HW_ENET_MAC_IEEE_T_MACERR) Address: 800F_0000h base + 264h offset = 800F_0264h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_MACERR R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_MACERR field descriptions Field IEEE_T_ MACERR Description Count of ENET MAC Frames Transmitted with Tx FIFO Underrun i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1832 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.61 ENET MAC Frames Transmitted with Carrier Sense Error (HW_ENET_MAC_IEEE_T_CSERR) Address: 800F_0000h base + 268h offset = 800F_0268h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_CSERR R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_CSERR field descriptions Field Description IEEE_T_CSERR Count of ENET MAC Frames Transmitted with Carrier Sense Error 26.4.62 ENET MAC Frames Transmitted with SQE Error (HW_ENET_MAC_IEEE_T_SQE) Note: Counter not implemented (read 0 always) as no SQE information is available Address: 800F_0000h base + 26Ch offset = 800F_026Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_SQE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_SQE field descriptions Field IEEE_T_SQE Description Count of ENET MAC Frames Transmitted with SQE Error i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1833 Programmable Registers 26.4.63 ENET MAC Frames Transmitted flow control (HW_ENET_MAC_IEEE_T_FDXFC) Flow Control Pause frames transmitted Address: 800F_0000h base + 270h offset = 800F_0270h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_FDXFC R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_FDXFC field descriptions Field Description IEEE_T_FDXFC Count of ENET MAC Frames Transmitted flow control 26.4.64 ENET MAC Frames Transmitted error (HW_ENET_MAC_IEEE_T_OCTETS_OK) Octet count for Frames Transmitted w/o Error Note: counts total octets (includes header and FCS fiel Address: 800F_0000h base + 274h offset = 800F_0274h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_T_OCTETS_OK R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_T_OCTETS_OK field descriptions Field IEEE_T_ OCTETS_OK Description Octet count for Frames Transmitted w/o Error i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1834 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.65 ENET MAC RMON Rx packet count (HW_ENET_MAC_RMON_R_PACKETS) Address: 800F_0000h base + 284h offset = 800F_0284h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_PACKETS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_PACKETS field descriptions Field Description RMON_R_ PACKETS ENET MAC RMON Rx packet count 26.4.66 ENET MAC RMON Rx Broadcast Packets (HW_ENET_MAC_RMON_R_BC_PKT) Address: 800F_0000h base + 288h offset = 800F_0288h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_BC_PKT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_BC_PKT field descriptions Field Description RMON_R_BC_ PKT Count of ENET MAC RMON Rx Broadcast Packets 26.4.67 ENET MAC RMON Rx Multicast Packets (HW_ENET_MAC_RMON_R_MC_PKT) Address: 800F_0000h base + 28Ch offset = 800F_028Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_MC_PKT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1835 Programmable Registers HW_ENET_MAC_RMON_R_MC_PKT field descriptions Field Description RMON_R_MC_ Count of ENET MAC RMON Rx Multicast Packets PKT 26.4.68 ENET MAC RMON Rx Packets w CRC/Align error (HW_ENET_MAC_RMON_R_CRC_ALIGN) Address: 800F_0000h base + 290h offset = 800F_0290h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_CRC_ALIGN R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_CRC_ALIGN field descriptions Field Description RMON_R_CRC_ Count of ENET MAC RMON Rx Packets w CRC/Align error ALIGN 26.4.69 ENET MAC RMON Rx Packets < 64 bytes, good CRC (HW_ENET_MAC_RMON_R_UNDERSIZE) Address: 800F_0000h base + 294h offset = 800F_0294h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_UNDERSIZE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_UNDERSIZE field descriptions Field RMON_R_ UNDERSIZE Description Count of ENET MAC RMON Rx Packets < 64 bytes, good CRC i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1836 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.70 ENET MAC RMON Rx Packets > MAX_FL, good CRC (HW_ENET_MAC_RMON_R_OVERSIZE) Address: 800F_0000h base + 298h offset = 800F_0298h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_OVERSIZE R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_OVERSIZE field descriptions Field Description RMON_R_ OVERSIZE ENET MAC RMON Rx Packet count > MAX_FL, good CRC 26.4.71 ENET MAC RMON Rx Packets < 64 bytes, bad CRC (HW_ENET_MAC_RMON_R_FRAG) Address: 800F_0000h base + 29Ch offset = 800F_029Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_FRAG R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_FRAG field descriptions Field Description RMON_R_FRAG Count of ENET MAC RMON Rx Packets < 64 bytes, bad CRC i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1837 Programmable Registers 26.4.72 ENET MAC RMON Rx Packets > MAX_FL bytes, bad CRC (HW_ENET_MAC_RMON_R_JAB) Address: 800F_0000h base + 2A0h offset = 800F_02A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_JAB R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_JAB field descriptions Field Description RMON_R_JAB Count of ENET MAC RMON Rx Packets > MAX_FL bytes, bad CRC 26.4.73 ENET MAC RMON Rx 64 byte packets (HW_ENET_MAC_RMON_R_P64) Address: 800F_0000h base + 2A8h offset = 800F_02A8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_P64 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_P64 field descriptions Field RMON_R_P64 Description Count of ENET MAC RMON Rx 64 byte packets i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1838 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.74 ENET MAC RMON Rx 65 to 127 byte packets (HW_ENET_MAC_RMON_R_P65TO127) Address: 800F_0000h base + 2ACh offset = 800F_02ACh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_P65TO127 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_P65TO127 field descriptions Field Description RMON_R_ P65TO127 Count of ENET MAC RMON Rx 65 to 127 byte packets 26.4.75 ENET MAC RMON Rx 128 to 255 byte packets (HW_ENET_MAC_RMON_R_P128TO255) Address: 800F_0000h base + 2B0h offset = 800F_02B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_P128TO255 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_P128TO255 field descriptions Field RMON_R_ P128TO255 Description Count of ENET MAC RMON Rx 128 to 255 byte packets i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1839 Programmable Registers 26.4.76 ENET MAC RMON Rx 256 to 511 byte packets (HW_ENET_MAC_RMON_R_P256TO511) Address: 800F_0000h base + 2B4h offset = 800F_02B4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_P256TO511 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_P256TO511 field descriptions Field Description RMON_R_ P256TO511 ENET MAC RMON Rx 256 to 511 byte packet count 26.4.77 ENET MAC RMON Rx 512 to 1023 byte packets (HW_ENET_MAC_RMON_R_P512TO1023) Address: 800F_0000h base + 2B8h offset = 800F_02B8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_P512TO1023 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_P512TO1023 field descriptions Field RMON_R_ P512TO1023 Description Count of ENET MAC RMON Rx 512 to 1023 byte packets i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1840 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.78 ENET MAC RMON Rx 1024 to 2047 byte packets (HW_ENET_MAC_RMON_R_P1024TO2047) Address: 800F_0000h base + 2BCh offset = 800F_02BCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_P1024TO2047 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_P1024TO2047 field descriptions Field Description RMON_R_ P1024TO2047 Count of ENET MAC RMON Rx 1024 to 2047 byte packets 26.4.79 ENET MAC RMON Rx packets w > 2048 bytes (HW_ENET_MAC_RMON_R_P_GTE2048) Address: 800F_0000h base + 2C0h offset = 800F_02C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_P_GTE2048 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_P_GTE2048 field descriptions Field RMON_R_P_ GTE2048 Description Count of ENET MAC RMON Rx packetsw > 2048 bytes i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1841 Programmable Registers 26.4.80 ENET MAC RMON Rx Octets (HW_ENET_MAC_RMON_R_OCTETS) Address: 800F_0000h base + 2C4h offset = 800F_02C4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMON_R_OCTETS R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_RMON_R_OCTETS field descriptions Field Description RMON_R_ OCTETS Count of ENET MAC RMON Rx Octets 26.4.81 ENET MAC Frames Received count drop (HW_ENET_MAC_IEEE_R_DROP) Count of frames not counted correctly Note: Counter increments if a frame with invalid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments. Address: 800F_0000h base + 2C8h offset = 800F_02C8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_R_DROP R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_R_DROP field descriptions Field Description IEEE_R_DROP Count of frames not counted correctly i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1842 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.82 ENET MAC Frames Received OK (HW_ENET_MAC_IEEE_R_FRAME_OK) Address: 800F_0000h base + 2CCh offset = 800F_02CCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_R_FRAME_OK R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_R_FRAME_OK field descriptions Field Description IEEE_R_ FRAME_OK Count of frames Received OK 26.4.83 ENET MAC Frames Received with CRC Error (HW_ENET_MAC_IEEE_R_CRC) Address: 800F_0000h base + 2D0h offset = 800F_02D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_R_CRC R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_R_CRC field descriptions Field IEEE_R_CRC Description Count of frames Received with CRC Error i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1843 Programmable Registers 26.4.84 ENET MAC Frames Received with Alignment Error (HW_ENET_MAC_IEEE_R_ALIGN) Address: 800F_0000h base + 2D4h offset = 800F_02D4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_R_ALIGN R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_R_ALIGN field descriptions Field Description IEEE_R_ALIGN Count of frames Received with Alignment Error 26.4.85 ENET MAC Frames Received overflow (HW_ENET_MAC_IEEE_R_MACERR) Receive Fifo Overflow count Address: 800F_0000h base + 2D8h offset = 800F_02D8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_R_MACERR R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_R_MACERR field descriptions Field IEEE_R_ MACERR Description Value of Frames Received overflow i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1844 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.86 ENET MAC Frames Received flow control (HW_ENET_MAC_IEEE_R_FDXFC) Flow Control Pause frames received Address: 800F_0000h base + 2DCh offset = 800F_02DCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_R_FDXFC R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_R_FDXFC field descriptions Field Description IEEE_R_FDXFC Count of flow Control Pause frames received 26.4.87 ENET MAC Frames Received error (HW_ENET_MAC_IEEE_R_OCTETS_OK) Octet count for Frames Rcvd w/o Error Note: counts total octets (includes header and FCS fields) Address: 800F_0000h base + 2E0h offset = 800F_02E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEEE_R_OCTETS_OK R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_IEEE_R_OCTETS_OK field descriptions Field IEEE_R_ OCTETS_OK Description Octet count for Frames Rcvd w/o Error i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1845 Programmable Registers 26.4.88 ENET MAC IEEE1588 Timer Control Register (HW_ENET_MAC_ATIME_CTRL) Note: The command bits can be used to trigger the corresponding events directly. It is not necessary to preserve any of the configuration bits when a command bit is set in the register (i.e. no read-modify-write is required). The bits read out 0 after the command has completed. Address: 800F_0000h base + 400h offset = 800F_0400h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EVT_PERIOD_ENA EVT_OFFSET_RST EVT_OFFSET_ENA ONE_SHOT ENABLE 0 0 0 0 0 0 RSRVD0 RSRVD4 0 PIN_PERIOD_ENA 0 RSRVD3 0 RESTART 0 RSRVD2 0 FRC_SLAVE R 0 CAPTURE Bit 0 RSRVD1 Reset EVT_PERIOD_RST W W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1846 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) HW_ENET_MAC_ATIME_CTRL field descriptions Field 31-14 RSRVD0 13 FRC_SLAVE Description Reserved bits. Write as 0. Enable timer slave mode. If set '1' the internal timer is disabled and instead the externally provided timer value from pins frc_in() is used. When operating in slave mode all other configuration bits in this register have no effect. Only the capture command bit can still be used to capture the current timer value. When disabled (0, default) the timer is active and all configuration bits in this register are relevant. 12 RSRVD1 11 CAPTURE 10 RSRVD2 9 RESTART Reserved bits. Write as 0. Capture timer value. When set the current time is captured and can be read from the ATIMER register. Command bit: When set, all other bits are ignored during a write. Reserved bits. Write as 0. Resets the timer to zero. This has no effect on the counter enable. If the counter is enabled while the command is triggered, the timer is reset to zero and starts counting from there. Command bit: When set, all other bits are ignored during a write. 8 RSRVD3 7 PIN_PERIOD_ ENA 6 RSRVD4 5 EVT_PERIOD_ RST Reserved bits. Write as 0. Enable external pin frc_evt_period assertion on period event when set. Reserved bits. Write as 0. Reset timer on periodical event. When set (1) the timer is reset to zero (wraps around) when the period setting is reached (causing an periodical event). If cleared the counter will increment continuously until it wraps around. Should be set 1 for normal operation. 4 EVT_PERIOD_ ENA Enable periodical event. When set (1) a period event interrupt can be generated (EIR(TS_TIMER)) and the external pin frc_evt_period is asserted when the timer wraps around according to the periodic setting ATIME_EVT_PERIOD. The timer period value should be set before. 3 Reset timer on offset event. When set (1) together with the EVT_OFFSET_ENA the timer is reset to zero EVT_OFFSET_ when the offset setting is reached (causing an offset event). RST 2 Enable one-shot offset event. When set (1) an offset-event interrupt can be generated (EIR(TS_TIMER)). EVT_OFFSET_ The bit is cleared when the offset event has been reached so no further event is created until the bit is set ENA again. The timer offset value should be set before. 1 ONE_SHOT Avoid timer wrap around. If set, the timer stops at maximum. An overflow interrupt is caused (if enabled) when the maximum is reached. When cleared (default) the timer operates continuously. 0 ENABLE When set (1) the timer starts incrementing. When (0) the timer stops at the current value i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1847 Programmable Registers 26.4.89 ENET MAC IEEE1588 Timer value Register (HW_ENET_MAC_ATIME) Address: 800F_0000h base + 404h offset = 800F_0404h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATIME 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_ATIME field descriptions Field Description ATIME A write sets the timer. A read returns the last captured value. To read the current, value a capture command must be issued in the ATIME_CTRL control register prior to reading this register. 26.4.90 ENET MAC IEEE1588 Offsetvalue for one-shot event generation Register (HW_ENET_MAC_ATIME_EVT_OFFSET) Address: 800F_0000h base + 408h offset = 800F_0408h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATIME_EVT_OFFSET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_ATIME_EVT_OFFSET field descriptions Field ATIME_EVT_ OFFSET Description Offsetvalue for one-shot event generation. When the timer reaches the value an event can be generated to reset the counter. If the increment value in ATIME_INC is given in true nanoseconds, this value is also given in true nanoseconds. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1848 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.91 ENET MAC IEEE1588 Timer Period Register (HW_ENET_MAC_ATIME_EVT_PERIOD) Address: 800F_0000h base + 40Ch offset = 800F_040Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 ATIME_EVT_PERIOD 0 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 HW_ENET_MAC_ATIME_EVT_PERIOD field descriptions Field ATIME_EVT_ PERIOD Description Value for generating periodic events. Each time the timer has reached this time, the period event occurs and the timer restarts. If the increment value in ATIME_INC is given in true nanoseconds, this value is also given in true nanoseconds. The value should be initialized to 1000000000 (=1*109) to represent a timer wrap around of 1 second. The increment value set in ATIME_INC should be set to the true nanoseconds of the period of clock ts_clk, hence implementing a true 1 second counter. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1849 Programmable Registers 26.4.92 ENET MAC IEEE1588 Correction counter wrap around value Register (HW_ENET_MAC_ATIME_CORR) Address: 800F_0000h base + 410h offset = 800F_0410h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 Bit ATIME_CORR W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R ATIME_CORR W Reset 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_ATIME_CORR field descriptions Field 31 RSRVD0 ATIME_CORR Description Reserved bits. Write as 0. Correction counter wrap around value. Correction period. Defines after how many clock cycles (ts_clk) the correction counter should be reset and trigger a correction increment on the timer. The amount of correction is defined in ATIME_INC(12:8) (see below). E.g. setting the increment amount to zero will stop the timer for one clock cycle, slowing it down. Larger values can be used to speed up the timer. A value of 0 disables the counter and no corrections will occur. Note: This value is given in clock cycles, not in nanoseconds as all other values. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1850 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.93 ENET MAC IEEE1588 Clock period of the timestamping clock (ts_clk) in nanoseconds and correction increment Register (HW_ENET_MAC_ATIME_INC) Address: 800F_0000h base + 414h offset = 800F_0414h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSRVD1 Reset RSRV D0 ATIME_INC_CORR ATIME_INC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_ATIME_INC field descriptions Field 31-15 RSRVD0 14-8 ATIME_INC_ CORR 7 RSRVD1 ATIME_INC Description Reserved bits. Write as 0. Correction increment value. This value will be added every time the correction timer expires (every clock cycles given in ATIME_CORR). A value smaller than in bits 6:0 will slow down the timer. A value larger than in bits 6:0 will speed up the timer. Reserved bits. Write as 0. Clock period of the timestamping clock (ts_clk) in nanoseconds. The timer will increment by this amount with every clock cycle. For example, 10 for 100MHz, 8 for 125MHz, 5 for 200MHz. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1851 Programmable Registers 26.4.94 ENET MAC IEEE1588 Timestamp of the last Frame Register (HW_ENET_MAC_TS_TIMESTAMP) Timestamp of the last Frame transmitted by the controller that had the ff_tx_ts_frm signal asserted from the user application. Valid when the Interrupt status bit TS_AVAIL is set to '1'. Address: 800F_0000h base + 418h offset = 800F_0418h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TS_TIMESTAMP R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_TS_TIMESTAMP field descriptions Field Description TS_TIMESTAMP IEEE1588 Timestamp of the last Frame Register 26.4.95 ENET MAC Supplemental MAC Address 0 (HW_ENET_MAC_SMAC_0_0) Address: 800F_0000h base + 500h offset = 800F_0500h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMAC_0_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_SMAC_0_0 field descriptions Field SMAC_0_0 Description Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact match. Note: if the supplemental MAC addresses are not used, they should all be set to the same value as the PALR/PAUR registers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1852 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.96 ENET MAC Supplemental MAC Address 0 (HW_ENET_MAC_SMAC_0_1) Address: 800F_0000h base + 504h offset = 800F_0504h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMAC_0_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_SMAC_0_1 field descriptions Field Description SMAC_0_1 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match. Register Bits 15 to 0 are reserved. 26.4.97 ENET MAC Supplemental MAC Address 1 (HW_ENET_MAC_SMAC_1_0) Same as define of MAC_SMAC_0_0. Address: 800F_0000h base + 508h offset = 800F_0508h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMAC_1_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_SMAC_1_0 field descriptions Field SMAC_1_0 Description Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact match. Note: if the supplemental MAC addresses are not used, they should all be set to the same value as the PALR/PAUR registers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1853 Programmable Registers 26.4.98 ENET MAC Supplemental MAC Address 1 (HW_ENET_MAC_SMAC_1_1) Same as define of MAC_SMAC_0_1. Address: 800F_0000h base + 50Ch offset = 800F_050Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMAC_1_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_SMAC_1_1 field descriptions Field Description SMAC_1_1 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match. Register Bits 15 to 0 are reserved. 26.4.99 ENET MAC Supplemental MAC Address 2 (HW_ENET_MAC_SMAC_2_0) Same as define of MAC_SMAC_0_0. Address: 800F_0000h base + 510h offset = 800F_0510h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMAC_2_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_SMAC_2_0 field descriptions Field SMAC_2_0 Description Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact match. Note: if the supplemental MAC addresses are not used, they should all be set to the same value as the PALR/PAUR registers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1854 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.100 ENET MAC Supplemental MAC Address 2 (HW_ENET_MAC_SMAC_2_1) Same as define of MAC_SMAC_0_1. Address: 800F_0000h base + 514h offset = 800F_0514h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMAC_2_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_SMAC_2_1 field descriptions Field Description SMAC_2_1 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match. Register Bits 15 to 0 are reserved. 26.4.101 ENET MAC Supplemental MAC Address 3 (HW_ENET_MAC_SMAC_3_0) Same as define of MAC_SMAC_0_0. Address: 800F_0000h base + 518h offset = 800F_0518h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMAC_3_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_SMAC_3_0 field descriptions Field SMAC_3_0 Description Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact match. Note: if the supplemental MAC addresses are not used, they should all be set to the same value as the PALR/PAUR registers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1855 Programmable Registers 26.4.102 ENET MAC Supplemental MAC Address 3 (HW_ENET_MAC_SMAC_3_1) Same as define of MAC_SMAC_0_1. Address: 800F_0000h base + 51Ch offset = 800F_051Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMAC_3_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_SMAC_3_1 field descriptions Field Description SMAC_3_1 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match. Register Bits 15 to 0 are reserved. 26.4.103 ENET MAC Compare register 0 (HW_ENET_MAC_COMP_REG_0) When the timer reaches this value, the event pin evt_out(0) is asserted for one ts_clk cycle. This repeats when the timer wraps around. A value of 0 disables the function. Address: 800F_0000h base + 600h offset = 800F_0600h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP_REG_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_COMP_REG_0 field descriptions Field COMP_REG_0 Description Value of compare register 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1856 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.104 ENET MAC Compare register 1 (HW_ENET_MAC_COMP_REG_1) When the timer reaches this value, the event pin evt_out(1) is asserted for one ts_clk cycle. This repeats when the timer wraps around. A value of 0 disables the function. Address: 800F_0000h base + 604h offset = 800F_0604h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP_REG_1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_COMP_REG_1 field descriptions Field Description COMP_REG_1 Value of compare register 1 26.4.105 ENET MAC Compare register 2 (HW_ENET_MAC_COMP_REG_2) When the timer reaches this value, the event pin evt_out(2) is asserted for one ts_clk cycle. This repeats when the timer wraps around. A value of 0 disables the function. Address: 800F_0000h base + 608h offset = 800F_0608h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP_REG_2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_COMP_REG_2 field descriptions Field COMP_REG_2 Description Value of compare register 2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1857 Programmable Registers 26.4.106 ENET MAC Compare register 3 (HW_ENET_MAC_COMP_REG_3) When the timer reaches this value, the event pin evt_out(3) is asserted for one ts_clk cycle. This repeats when the timer wraps around. A value of 0 disables the function. Address: 800F_0000h base + 60Ch offset = 800F_060Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMP_REG_3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_COMP_REG_3 field descriptions Field Description COMP_REG_3 Value of compare register 3 26.4.107 ENET MAC Capture register 0 (HW_ENET_MAC_CAPT_REG_0) Timer value latched when a rising edge occured on input pin evt_in(0). Address: 800F_0000h base + 640h offset = 800F_0640h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPT_REG_0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_CAPT_REG_0 field descriptions Field CAPT_REG_0 Description Value of capture register 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1858 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) 26.4.108 ENET MAC Capture register 1 (HW_ENET_MAC_CAPT_REG_1) Timer value latched when a rising edge occured on input pin evt_in(1). Address: 800F_0000h base + 644h offset = 800F_0644h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPT_REG_1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_CAPT_REG_1 field descriptions Field Description CAPT_REG_1 Value of capture register 1 26.4.109 ENET MAC Capture register 2 (HW_ENET_MAC_CAPT_REG_2) Timer value latched when a rising edge occured on input pin evt_in(2). Address: 800F_0000h base + 648h offset = 800F_0648h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPT_REG_2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_CAPT_REG_2 field descriptions Field CAPT_REG_2 Description Value of capture register 2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1859 Programmable Registers 26.4.110 ENET MAC Capture register 3 (HW_ENET_MAC_CAPT_REG_3) Timer value latched when a rising edge occured on input pin evt_in(3). Address: 800F_0000h base + 64Ch offset = 800F_064Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPT_REG_3 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_MAC_CAPT_REG_3 field descriptions Field Description CAPT_REG_3 Value of capture register 3 26.4.111 ENET MAC IEEE1588 Interrupt register. (HW_ENET_MAC_CCB_INT) For each capture/compare event an interrupt can be generated. The interrupt is cleared by writing a 1 to the corresponding bit Note: The interrupt bits are set on event occurence. To clear an interrupt the corresponding bit must be written with 1. 29 28 27 26 25 24 23 22 21 20 0 0 0 0 0 19 18 17 16 COMPARE0 30 COMPARE1 31 COMPARE2 Bit COMPARE3 Address: 800F_0000h base + 680h offset = 800F_0680h 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1860 Freescale Semiconductor, Inc. 12 11 10 9 8 7 6 5 4 0 0 0 0 0 3 2 1 0 CAPTURE0 13 CAPTURE1 14 CAPTURE2 15 Bit CAPTURE3 Chapter 26 Ethernet Controller (ENET) 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 HW_ENET_MAC_CCB_INT field descriptions Field 31-20 RSRVD0 Description Reserved bits. Write as 0. 19 COMPARE3 compare event 3. 18 COMPARE2 compare event 2. 17 COMPARE1 compare event 1. 16 COMPARE0 compare event 0. 15-4 RSRVD1 Reserved bits. Write as 0. 3 CAPTURE3 capture event 3. 2 CAPTURE2 capture event 2. 1 CAPTURE1 capture event 1. 0 CAPTURE0 capture event 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1861 Programmable Registers 26.4.112 ENET MAC IEEE1588 Interrupt enable mask register (HW_ENET_MAC_CCB_INT_MASK) An interrupt is created when an interrupt is indicated (CCB_INT) and the corresponding mask bit is set to 1. When an interrupt occurs the ccb_int pin is asserted. Address: 800F_0000h base + 684h offset = 800F_0684h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 COMPARE3 COMPARE2 COMPARE1 COMPARE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPTURE3 CAPTURE2 CAPTURE1 CAPTURE0 R 0 0 0 0 0 0 0 0 0 W Reset Bit RSRVD1 R W Reset 0 0 0 0 0 0 0 HW_ENET_MAC_CCB_INT_MASK field descriptions Field 31-20 RSRVD0 Description Reserved bits. Write as 0. 19 COMPARE3 compare event 3 interrupt mask. 18 COMPARE2 compare event 2 interrupt mask. 17 COMPARE1 compare event 1 interrupt mask. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1862 Freescale Semiconductor, Inc. Chapter 26 Ethernet Controller (ENET) HW_ENET_MAC_CCB_INT_MASK field descriptions (continued) Field 16 COMPARE0 15-4 RSRVD1 Description compare event 0 interrupt mask. Reserved bits. Write as 0. 3 CAPTURE3 capture event 3 interrupt mask. 2 CAPTURE2 capture event 2 interrupt mask. 1 CAPTURE1 capture event 1 interrupt mask. 0 CAPTURE0 capture event 0 interrupt mask. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1863 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1864 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) 27.1 I2C Overview The I2C is a standard two-wire serial interface used to connect the chip with peripherals or host controllers. This interface provides a standard speed (up to 100 kbps), and a fast speed (up to 400 kbps) I2C connection to multiple devices with the chip acting in either I2C master or I2C slave mode. Typical applications for the I2C bus include: EEPROM, LED/LCD, FM tuner, cell phone baseband chip connection, and so on. The I2C port supports multi-master configurations. As implemented on the i.MX28, the I2C block includes the following functions: * The I2C block can be configured as either a master or slave device. In master mode, it generates the clock (I2C_SCL) and initiates transactions on the data line (I2C_SDA). * The I2C block packs/unpacks data into 8-, 16-, 24-, or 32-bit words for DMA transactions. Data on the I2C bus is always byte-oriented. Short transmission (up to three bytes plus address) can be easily triggered using only PIO operations, that is, no DMA setup required. * PIO mode, that is, soft DMA mode is supported. * PIO Queue mode is supported. This mode allows software to queue up multiple commands and supporting data for later automatic execution. * The I2C block support programmable 7-bit and 10-bit device addresses for master transactions. It also has a programmable 7-bit address that defaults to 0x43 = 7'b1000011 for slave transactions. As seen in the 8-bit device address byte, this address corresponds to 0x86 where the least significant bit (LSB) is the R/W bit. 10bit address is not supported in slave mode. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1865 I2C Overview * Master transactions are composed of one or more DMA commands chained together. The first byte conveys the slave address and read/write bit for the first command. If the entire transaction is an I2C write command, then it can be sent by a single DMA command. If the command is an I2C read transaction, then at least two DMA commands are required to handle it. * When the slave interface is enabled, it immediately goes into address search mode and searches for a start event. It then looks for a match on its programmable device address. As soon as the address byte is matched, it is acknowledged on the I2C bus and then the SCL clock is held low until released by software. The address phase initiates a CPU interrupt, if a slave address match is detected. Software then reads the address LSB to determine whether to use a read or write DMA command to complete the slave transaction. * The I2C block does not support CBUS (start byte is 00000001) device in master mode. Figure 27-1 shows a block diagram of the I2C interface implemented on the i.MX28. ARM Core SRAM 24- MHz XTAL Osc. AHB APB Bridge Divide by n Shared APBX DMA APBX Bridge/ DMA APBX APBX Mast er I 2C Program m able Regist ers and FI FOs DMA I nt erface FSM I 2 C_ SCL I 2 C_ SD A Slave Search Engine I nput Sync and I 2C_CLK Generat ion I 2C Figure 27-1. I2C Interface Block Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1866 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) 27.2 Operation The I2C Interface on the i.MX28 includes the following external pins: * I2C_SDA: I2C Serial Data--This pin carries all address and data bits. * I2C_SCL: I2C Serial Clock--This pin carries the clock used to time the address and data. Pullup resistors are required on both of the I2C lines as all of the I2C drivers are open drain (pulldown only). Typically, external 2k resistors are used to pull the signals up to VddIO for normal and fast speeds. 27.2.1 I2C Interrupt Sources The I2C port can be used in either interrupt-driven or polled modes. An interrupt can be generated by the completion of a DMA command in the APBX DMA. DMA interrupts are the reporting mechanism for I2C transactions that terminate normally. Abnormal terminations or partial completions are signaled by interrupts generated within the I2C controller. If I2C interrupts are enabled, a level-sensitive interrupt are signaled to the processor upon one of the events listed in Table 27-1. Table 27-1. I2C Slave and Master Interrupt Condition in HW_I2C_CTRL1 SOURCE Bit Name Description Slave Address SLAVE_IRQ This interrupt is generated when an address match occurs. It indicates that the CPU should read the captured RW bit from the I2C address byte to determine the type of DMA to use for the data transfer phase. Slave Stop SLAVE_STOP_IRQ This interrupt is generated when a stop condition is detected after a slave address has been matched. Oversize Xfer OVERSIZE_XFER_TERM_IR The DMA and I2C controller are initialized for an expected transfer size. If Q the data phase is not terminated within this transfer size then oversize transfer processing goes into effect and the CPU is alerted through this interrupt. This interrupt is only used in slave mode. Early Termination EARLY_TERM_IRQ The DMA and I2C controller are initialized for an expected transfer size. If the data phase is terminated before this transfer size then early termination processing goes into effect and the CPU is alerted through this interrupt. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1867 Operation Table 27-1. I2C Slave and Master Interrupt Condition in HW_I2C_CTRL1 (continued) SOURCE Bit Name Description Master Loss MASTER_LOSS_IRQ A master begins transmission on an idle I2C bus and monitors the data line. If it ever attempts to send a one on the line and notes that a zero has been sent instead, then it notes that it has lost mastership of the I2C bus. It terminates its transfer and reports the condition to the CPU through this interrupt. This detection only happens on master transmit operations. No Slave Ack NO_SLAVE_ACK_IRQ When a start condition is transmitted in master mode, the next byte contains an address for a targeted slave. If the targeted slave does not acknowledge the address byte, then this interrupt is set, no further I2C protocol is processed, and the I2C bus returns to the idle state. Data Engine Complete DATA_ENGINE_CMPLT_IRQ This bit is set whenever the DMA interface state machine completes a transaction and resets its run bit. This is useful for PIO mode transmit transactions that are not mediated by the DMA and therefore cannot use the DMA command completion interrupt. This bit is still set for master completions when the DMA is used, but can be ignored in that case. Bus Free BUS_FREE_IRQ When bus mastership is lost during the I2C arbitration phase, the bus becomes busy running services for another master. This interrupt is set whenever a stop command is detected so the master transaction can attempt a retry. Read Queue Threshold RD_QUEUE_IRQ This interrupt is set whenever the read FIFO has filled up equal to or greater than the programmed threshold level. Write Queue Threshold WR_QUEUE_IRQ This interrupt is set whenever the write FIFO has drained down equal to or less than the programmed threshold level. The interrupt lines are tied directly to the bits of Control Register 1. Clearing these bits through software removes the interrupt request. 27.2.2 I2C Bus Protocol The I2C block can be programmed and driven by the SoC using one of three internal interface modes: DMA mode, PIO mode and PIO Queue mode. The discussion of the I2C protocol in the following subsections is written from the perspective of DMA mode. The descriptions of how to use the other two modes and their similarities and difference from DMA mode will be included in a later section. In DMA mode, one DMA command chain can only contain one data-transfer command besides address-transfer command(s). If it's desired to transfer data to/from two different system memory buffers, two dma transfer should be used. The I2C interface operates as shown in Figure 27-2 and Figure 27-3. * A START condition is defined as a high-to-low transition on the data line while the I2C_SCL line is held high. * After this has been transmitted by the master, the bus is considered busy. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1868 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) * The next byte of data transmitted after the start condition contains the address of the slave in the first seven bits, and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. * When an address is sent, each device in the system compares the first seven bits after a start condition with its address. * If they match, the device considers itself addressed by the master. In slave mode, the default I2C write address is 86h, and its default read address is 87h. The slave address is programmable. Data transfer with acknowledge is obligatory. * The transmitter must release the I2C_SDA line during the acknowledge pulse. * The receiver must then pull the data line low, so that it remains stable low during the high period of the acknowledge clock pulse. * A receiver that has been addressed is obliged to generate an acknowledge after each byte of data has been received. * A slave device can terminate a transfer by withholding its acknowledgement. End of the Slave Address Search Engine Processing Beginning of DMA Transfer Engine Processing SCL I2 C Clock Held SDA 8 Bits 8 Bits SLAVE Address and R /W DATA Acknowledge Signal START Condition Acknowledge Signal STOP Condition Figure 27-2. I2C Data and Clock Timing The clock is generated by the master, according to parameters set in the HW_I2C_TIMINGn register. This register also provides programmable timing for capturing received data, as well as for changing the transmitted data bit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1869 Operation TDSU TDHD SDAin Bit 0 Bit 1 Bit 2 Grab Read Data SAK Change Write Data SCLin Slave Hold Clock SCLoe High clk Low clk Master Figure 27-3. I2C Data and Clock Timing Generation 27.2.2.1 Simple Device Transactions The simplest transfer of interest on an I2C bus is writing a single data byte from a master to a slave, for example, writing a single byte to an FM tuner. In this transaction, a start condition is transmitted, followed by the device address byte, followed by a single byte of write data. This sequence always ends with a stop condition. Table 27-2. I2C Transfer When the Interface is Transmitting as a Master ST SAD+W SAK DATA SAK SP Table 27-3 defines the symbols used in describing I2C transactions. For example, in the single byte write operation, ST is a start condition, and SP is a stop condition. The data transfer occurs between these two bus events. It starts with a slave address plus write byte (SAD+W) addressing the targeted slave. A slave-generated acknowledge bit (SAK) tells the master that a slave has recognized the address and will accept the transfer. The master sends the data byte (DATA), and the slave acknowledges it with an SAK. Table 27-3. I2C Slave and Master Mode Address Definitions BIT Description ST Start Condition SR Repeated Start Condition SAD Slave Address SAK Slave Acknowledge SUB Sub-Address, e.g., for EEPROMs Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1870 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) Table 27-3. I2C Slave and Master Mode Address Definitions (continued) BIT Description DATA Data SP Stop Condition MAK Master Acknowledge NMAK No Master Acknowledge To receive one data byte from a slave device such as an FM tuner, the following bus transaction takes place. Table 27-4. I2C Transfer FM Tuner Read of One Byte ST SAD+R SAK DATA NMAK SP In this transaction: * The master first generates a start condition, ST. * It then sends the seven-bit slave address for the FM tuner plus a read bit (SAD+R). * The slave in the FM tuner responds with a slave acknowledge bit (SAK). * The master then generates I2C clocks for a data byte to be transferred (DATA). * The slave provides data to the I2C data bus during the DATA byte transfer. * Next, the master generates a master non-acknowledge to the slave (NMAK), indicating the end of the data transfer to the slave. The slave will then release the data line. * Finally, the master generates a stop condition (SP), terminating the transaction and freeing the I2C bus for other masters to use. The following example shows a multiple byte read from an FM tuner or other slave device: Table 27-5. I2C Transfer FM Tuner Read of Three Bytes ST SAD+R SAK DATA MAK DATA MAK DATA NMAK SP i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1871 Operation 27.2.2.2 Typical EEPROM Transactions I2C EEPROMs typically have a specific transaction sequence for reading and writing data bytes to and from the EEPROM array. Table 27-6 through Table 27-9 show the first two bytes of data as a sub-address for purposes of illustration. The sub-address is used to address the memory space inside the device. Table 27-3 defines each element of the transactions shown. When writing a single byte of data to the EEPROM, one must first transfer two bytes of sub-address as follows: Table 27-6. I2C Transfer When Master is Writing One Byte of Data to a Slave ST SAD+W SAK SUB SAK SUB SAK DATA SAK SP The sub-address only needs to be specified once for a multibyte transfer, as shown here. Note that the sub-address must be sent for each start condition that initiates a transaction. Table 27-7. I2C Transfer When Master is Writing Multiple Bytes to a Slave ST SAD+W SAK SUB SAK SUB SAK DATA SAK DATA SAK SP One must also provide the sub-address before reading bytes from the EEPROM. The subaddress is transmitted from the master to the slave before it can receive data bytes. The two transfers are joined into a single bus transaction through the use of a repeated start condition (SR). Normally, a stop condition precedes a start condition. However, when a start condition is preceded by another start condition, it is known as a repeated start (SR). Note that the two-byte sub address is transferred using an SAD+W address, while the data is received using a SAD+R address. Table 27-8. I2C Transfer When Master is Receiving One Byte of Data from a Slave ST SAD+W SAK SUB SAK SUB SAK SR SAD+R SAK DATA NMAK SP Table 27-9. I2C Transfer When Master is Receiving Multiple Bytes of Data from a Slave ST SAD +W SAK SUB SAK SUB SAK SR SAD +R SAK DATA MAK DATA MAK DATA NMA K SP 27.2.2.3 Master Mode Protocol In master mode, the I2C interface generates the clock and initiates all transfers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1872 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) 27.2.2.4 Clock Generation The I2C clock is generated from the APBX clock, as described in the register description. * If another device pulls the clock low before the I2C block has counted the high period, then the I2C block immediately pulls the clock low as well and starts counting its low period. * Once the low period has been counted, the I2C block releases the clock line high, but must then check to see if another device stills holds the line low, in which case it enters a high wait state. In this way, the I2C_SCL clock is generated, with its low period determined by the device with the longest clock low period and its high period determined by the one with the shortest clock high period. 27.2.2.5 Master Mode Operation The finite state machine for master mode operation is shown in Figure 27-4 through Figure 27-7. Figure 27-4 shows the generation of the optional start condition. Figure 27-5 shows the receive states, Figure 27-6 shows the transmit states. Figure 27-7 shows the generation of the optional stop state. Table 27-10 through Table 27-13 show examples of Master Mode I2C transactions. Table 27-3 defines each sub-address shown. The following read-after-write transactions are performed using the restart technique. Table 27-10. I2C Transfer When Master is Transmitting 1 Byte of Data to Slave Internal Subaddress ST SAD+W SAK SUB SAK SUB SAK DATA SAK SP Table 27-11. I2C Transfer When the Interface as Master is Receiving >1 Byte of Data from Slave ST SAD+R SAK DATA MAK DATA MAK DATA NMAK SP Table 27-12. I2C Transfer when Master is Receiving 1 Byte of Data from Slave Internal Subaddress ST SAD+W SAK SUB SAK SUB SAK SR SAD+R SAK DATA NMAK SP i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1873 Operation Table 27-13. I2C Transfer When Master is Receiving >1 byte of Data from Slave Internal Subaddress ST SAD +W SAK SUB SAK SUB SAK SR SAD +R SAK DATA MAK DATA MAK DATA NMA K SP i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1874 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) Bus Idle Multi Master & Start Cond. ? Master loss Yes No Bus Busy Stop Cond. ? Wait For Run Yes No Yes Multi Master? No No RUN? Yes Presend Start? No i2c_sda_en=1 start condition Release Held Clock Wait for start hold time Release Held Clock Yes RECEIVE MODE? Yes No TRANSMIT STATES RECEIVE STATES Figure 27-4. I2C Master Mode Flow Chart-Initial States i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1875 Operation RCV STATES Receive 1 bit No Got 8 Bits? Yes Send data to DMA Check xfer_count and decide on ACK Last byte? No Yes Send ACK Send ACK, Flush DMA Reset Run Hold Clock? Yes 2 Set Hold I C Clock Low No Yes Send Stop Post Send Stop? No Wait for Run Figure 27-5. I2C Master Mode Flow Chart-Receive States i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1876 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) XMIT STATES Get byte from DMA Send 1 Bit No 8 bits sent? Yes Check ACK ACK ? Check xfer_count Last byte? No Yes Reset Run Hold Clock? Yes Set Hold I 2C Clock Low No Yes Send Stop Post Send Stop? No Wait for Run Figure 27-6. I2C Master Mode Flow Chart-Transmit States i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1877 Operation SEND STOP Force sda to zero I2c_sda_en = 1 Wait for stop setup time Release Held Clock Release sda I2c_sda_en = 0 Reset Run, Reset post send Wait for Run Figure 27-7. I2C Master Mode Flow Chart-Send Stop States 27.2.2.6 Slave Mode Protocol The I2C slave protocol is handled by a combination of I2C functional block hardware, the DMA, and some supporting software to intervene in the transaction. The flow chart for slave mode is shown in Figure 27-8. * At device start-up, all the registers are reset so that the state is known from that time onward. * Once the I2C slave search engine is enabled, the slave waits to detect a start condition on the I2C_SCL and I2C_SDA lines. * Once this is detected, the slave reads in eight bits and checks against its programmed device address (which defaults to 0x86 == 7'b1000011) to see if a master device is trying to start a transfer with i.MX28 operating as a slave. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1878 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) * If it is the programmed address, an acknowledgement is sent; otherwise, the slave does not acknowledge and returns to state IDLE. * Once the slave search engine detects an address, it holds the clock line and interrupts the CPU. * Next the software checks the RW bit. * If it is a write operation, then the software programs the DMA channel for a DMA_WRITE (to on-chip RAM or off-chip SDRAM). * The slave search engine leaves the programmable state set up for the DMA transfer engine to send the address acknowledge for the address byte as soon as the clock is released. * It then accepts eight-bit bytes and pushes them into the DMA data register, acknowledging each data byte as it is received, until the transfer count reaches zero. * The DMA engine stops with the clock held and the hardware ready to acknowledge the last byte when the clock is released. Software decides whether the last byte is acknowledged or not. * If the master is requesting a read operation, then the i.MX28 slave must start sending data on the I2C_SDA bus immediately after acknowledging the slave address and RW bit. * After each byte, the acknowledgement from the master must be checked. When the master has received the last byte, it does not send an acknowledgement, and the slave terminates while setting the Early Termination interrupt request. This notifies software that the DMA will not be interrupting for the termination and that software should deal with a shorter than expected packet of data. * If the transfer count reaches zero and the master has not sent an MNAK or stop condition, then the slave DMA transfer controller terminates the transfer while setting the Oversize Transfer interrupt request. This notifies software to set up for an additional buffer of data to transmit to the master. Data is transmitted in byte format. Each data transfer has to contain eight bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSB) first. If a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the I2C_SCL clock line low to force the transmitter into a wait state. Data transfer can only continue when the receiver is ready for another byte and releases the clock line. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1879 Operation If a slave receiver does not acknowledge the slave address (for example, it is unable to receive because it is performing some real-time function), the data line must be left high by the slave. The master can then abort the transfer. A low-to-high transition on the I2C_SDA line while the I2C_SCL line is high is defined as a Stop condition. Each data transfer must be terminated by the generation of a Stop condition. A write transfer from a master can be terminated by the master by sending a Stop condition instead of an additional data byte. The i.MX28 slave DMA transfer engine reports this to software as an Early Termination interrupt request. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1880 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) Reset Slave Search Engine Wait for Start condition and slave enable A Receive slave address Receive 8 data bits Get 1 byte from DMA No Our address Send 8 data bits Send Data to DMA Yes Receive Master ACK Send Slave ACK and interrupt CPU Send Slave ACK No 2 Hold I C clock low Yes CPU release Stop | Restart No Last Byte No Last Byte No Yes Yes No Read Yes No Yes Stop | Restart Yes Stop | Restart No M ACK? No HoldClock? Yes No Yes No HoldClock? Yes Yes A Figure 27-8. I2C Slave Mode Flow Chart i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1881 Operation 27.2.3 Programming Examples This section provides two programming examples, Five Byte Master Write Using DMA and Reading 256 bytes from an EEPROM. 27.2.3.1 Five Byte Master Write Using DMA The example in Figure 27-9 shows sending five bytes from an i.MX28 operating as an I2C master to another device acting as an I2C slave. 1PIO, no chaining, IRQ,DMA read NEXTCMD_ADDR 6 1 1 1 1 0 10 BUFFER ADDRESS HW_I2C_CTRL0= 0x001B0006 DATA 2,DATA 1, DATA 0, I2CADDR+W 0x0000,DATA4, DATA 3 Pointer to next ccw Pointer to DMA buffer Figure 27-9. I2C Writing Five Bytes The DMA command is initialized to send six bytes to the I2C controller and one word of PIO information to the HW_I2C_CTRL0 register. Table 27-14. I2C Transfer When the Master Transmits 5 Bytes of Data to the Slave ST SAD+W SAK DATA0 SAK DATA1 SAK DATA2 SAK DATA3 SAK DATA4 SAK SP The following C code is used to send a five-byte transmission: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1882 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) // SEND: start, 0x56, 0x01,0x02,0x03,0x04,0x05,stop //-----------------------------------------------------#define I2C_CHANNEL_NUM 3 // dma buffer of 6 bytes (i2c address + 5 data bytes) static reg32_t I2C_DATA_BUFFER[2]= { 0x03020156, //slave address 56+W 0x00000504 // last two data bytes }; // DMA command chain const static reg32_t I2C_DMA_CMD[4] = { (reg32_t) 0, (BF_APBX_CHn_CMD_XFER_COUNT(6) | BF_APBX_CHn_CMD_SEMAPHORE(1) | BF_APBX_CHn_CMD_CMDWORDS(1) | BF_APBX_CHn_CMD_WAIT4ENDCMD(1)| BF_APBX_CHn_CMD_CHAIN(0) | BV_FLD(APBX_CHn_CMD, COMMAND, DMA_READ)), (reg32_t) &eeprom_command_buffer[0], BF_I2C_CTRL0_POST_SEND_STOP(BV_I2C_CTRL0_POST_SEND_STOP_SEND_STOP)| BF_I2C_CTRL0_PRE_SEND_START(BV_I2C_CTRL0_PRE_SEND_START_SEND_START) | BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE_MASTER) | BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION_TRANSMIT) | BF_I2C_CTRL0_XFER_COUNT(6) }; void SendFiveBytes(){ // Reset the APBX dma channels associated with I2C. reset_mask = BF_APBX_CTRL0_RESET_CHANNEL((1 << I2C_CHANNEL_NUM)); HW_APBX_CTRL0_SET(reset_mask); // Poll for reset to clear the channel. for (retries = 0; retries < RESET_TIMEOUT; retries++) if ((reset_mask & HW_APBX_CTRL0_RD()) == 0) break; if( retries == RESET_TIMEOUT) exit(1); // Setup dma channel configuration. BF_WRn(APBX_CHn_NXTCMDAR,I2C_CHANNEL_NUM, CMD_ADDR,(reg32_t) I2C_DMA_CMD); BF_WR(APBX_CTRL1, CH3_CMDCMPLT_IRQ, 0); // clear interrupt // Start the dma channel by incrementing semaphore. BF_WRn(APBX_CHn_SEMA, I2C_CHANNEL_NUM, INCREMENT_SEMA, 1); // Poll for the semaphore to decrement to zero on the DMA channel. for (retries = 0; retries < SEMAPHORE_TIMEOUT; retries++) if (0 == BF_RDn(APBX_CHn_SEMA, I2C_CHANNEL_NUM, PHORE)) break; // a frame with one byte of address and five bytes of data was just sent } 27.2.3.2 Reading 256 bytes from an EEPROM i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1883 Operation 1 PIO,IRQ, no chaining, DMA write NEXTCMD_ADDR=0 1PIO, chaining, DMA read NEXTCMD_ADDR 3 1 256 1 0 0 1 10 1 1 1 1 0 01 BUFFER ADDRESS BUFFER ADDRESS HW_I2C_CTRL0= 0x000B0003 HW_I2C_CTRL0= 0x00120100 0x00,SUB1, SUB0, I2CADDR+W 1PIO, chaining, DMA read NEXTCMD_ADDR 1 1 1 0 0 1 10 BUFFER ADDRESS 256-Byte Data Block HW_I2C_CTRL0= 0x002B0001 0x000000, I2CADDR+R Pointer to next ccw Pointer to DMA buffer Figure 27-10. I2C Reading 256 Bytes from an EEPROM //---------------------------------------------------------------------// dma buffers to hold i2c command string for slave addres+W plus sub0, // sub 1 and the second command, a slave address+R // eePROM write address == 0xA0, read address == 0xA1 //---------------------------------------------------------------------unsigned char eeprom_command_buffer[4] = {0xA0,0x34,0x12,0xA1}; //---------------------------------------------------------------------// I2C DMA chain //---------------------------------------------------------------------const static reg32_t I2C_DMA_CMD3[4] = { 0x0, (BF_APBX_CHn_CMD_XFER_COUNT(256) | BF_APBX_CHn_CMD_WAIT4ENDCMD(1) | BF_APBX_CHn_CMD_SEMAPHORE(1) | BF_APBX_CHn_CMD_CMDWORDS(1) | BF_APBX_CHn_CMD_CHAIN(0) | // last command BV_FLD(APBX_CHn_CMD, COMMAND, DMA_WRITE)), (reg32_t) &eeprom_command_buffer[3], BF_I2C_CTRL0_POST_SEND_STOP(BV_I2C_CTRL0_POST_SEND_STOP_SEND_STOP)| BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE_MASTER) | BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION_RECEIVE) | BF_I2C_CTRL0_XFER_COUNT(256) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1884 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) }; const static reg32_t I2C_DMA_CMD2[4] = { (reg32_t) I2C_DMA_CMD3, (BF_APBX_CHn_CMD_XFER_COUNT(1) | BF_APBX_CHn_CMD_CMDWORDS(1) | BF_APBX_CHn_CMD_WAIT4ENDCMD(1)| BF_APBX_CHn_CMD_CHAIN(1) | BV_FLD(APBX_CHn_CMD, COMMAND, DMA_READ)), (reg32_t) &eeprom_command_buffer[3], BF_I2C_CTRL0_RETAIN_CLOCK(BV_I2C_CTRL0_RETAIN_CLOCK_HOLD_LOW) | BF_I2C_CTRL0_PRE_SEND_START(BV_I2C_CTRL0_PRE_SEND_START_SEND_START)| BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE_MASTER) | BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION_TRANSMIT) | BF_I2C_CTRL0_XFER_COUNT(1) }; const static reg32_t I2C_DMA_CMD1[4] = { (reg32_t) I2C_DMA_CMD2, (BF_APBX_CHn_CMD_XFER_COUNT(3) | BF_APBX_CHn_CMD_CMDWORDS(1) | BF_APBX_CHn_CMD_WAIT4ENDCMD(1)| BF_APBX_CHn_CMD_CHAIN(1) | BV_FLD(APBX_CHn_CMD, COMMAND, DMA_READ)), (reg32_t) &eeprom_command_buffer[0], BF_I2C_CTRL0_PRE_SEND_START(BV_I2C_CTRL0_PRE_SEND_START_SEND_START) | BF_I2C_CTRL0_MASTER_MODE(BV_I2C_CTRL0_MASTER_MODE_MASTER) | BF_I2C_CTRL0_DIRECTION(BV_I2C_CTRL0_DIRECTION_TRANSMIT) | BF_I2C_CTRL0_XFER_COUNT(3) }; ///////////////////////////////////////////////////// //Read256BytesFromEEPROM returns 1 for errors and 0 for OK ///////////////////////////////////////////////////// int Read256BytesFromEEPROM(unsigned short usAddress){ // insert eePROM addres param into dma command buffer I2C_CMD_BUFFER[1] = (unsigned char) (usAddress &0x00ff); I2C_CMD_BUFFER[2] = (unsigned char) ((usAddress>>8) &0x00ff); // Reset the APBX dma channels associated with I2C. reset_mask = BF_APBX_CTRL0_RESET_CHANNEL((1 << I2C_CHANNEL_NUM)); HW_APBX_CTRL0_SET(reset_mask); // Poll for reset to clear the channel. for (retries = 0; retries < RESET_TIMEOUT; retries++) if ((reset_mask & HW_APBX_CTRL0_RD()) == 0) break; if (retries == RESET_TIMEOUT)exit(1); // Setup dma channel configuration. BF_WRn(APBX_CHn_NXTCMDAR,I2C_CHANNEL_NUM, CMD_ADDR,(reg32_t) I2C_DMA_CMD1); BF_WR(APBX_CTRL1, CH3_CMDCMPLT_IRQ, 0); // Start the dma channel by incrementing semaphore. BF_WRn(APBX_CHn_SEMA, I2C_CHANNEL_NUM, INCREMENT_SEMA, 1); // Poll for the semaphore to decrement to zero on the DMA channel. for (retries = 0; retries < SEMAPHORE_TIMEOUT; retries++){ if (0 == BF_RDn(APBX_CHn_SEMA, I2C_CHANNEL_NUM, PHORE)) break; if (1 == HW_I2C_CTRL1.MASTER_LOSS_IRQ) return 1; // error if (1 == HW_I2C_CTRL1.NO_SLAVE_ACK_IRQ) return 1; // error if (1 == HW_I2C_CTRL1.EARLY_TERM_IRQ) return 1; // error } if(ferreters == SEMAPHORE_TIMEOUT) exit(2); // the 256 bytes were read from the eePROM so return with no Error return 0; } i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1885 Internal Interface Modes 27.3 Internal Interface Modes The I2C functionality can be programmed and managed by the i.MX28 in three different modes. The description and examples above explain the DMA mode. The two additional modes are explained in the following subsections. 27.3.1 PIO Mode The I2C block on the i.MX28 supports a new PIO mode or soft-DMA mode. This mode works similar to the DMA mode except the processor is responsible for monitoring the HW_I2C_DEBUG0_DMAEREQ and HW_I2C_DEBUG0_DMAENDCMD pio bits. Also the DATA_ENGINE_CMPLT_IRQ interrupt can be enabled in the block to tell the processor when a DMA command is complete. (This is the same as the HW_I2C_DEBUG0_DMAENDCMD event.) For example, the DMA example Reading 256 bytes from an EEPROM can be executed using the CPU in PIO mode instead of using the DMA engine in DMA mode. (Be aware that the PIO_MODE bit used in previous generation SoCs is obsolete and has been removed in this version.) To execute the example in PIO mode the following basic steps should be followed: 1. Write to the HW_I2C_CTRL0 register with the desired field values to write the three byte address to the EEPROM just as it is embedded in the DMA descriptor. Set up other registers as needed, for example, HW_I2C_TIMING1 register. 2. Assert the HW_I2C_CTRL0_RUN bit. 3. Wait for the HW_I2C_DEBUG0_DMAREQ bit to assert. 4. Write the word containing the 3 bytes of EEPROM slave address to the HW_I2C_DATA register. 5. Clear the HW_I2C_DEBUG0_DMAREQ bit. 6. Wait for the HW_I2C_CTRL1_ DATA_ENGINE_CMPLT_IRQ bit to assert (or the interrupt to occur). 7. Clear the HW_I2C_CTRL1_ DATA_ENGINE_CMPLT_IRQ bit. 8. Write the next HW_I2C_CTRL0 word. 9. Reassert the HW_I2C_CTRL0_RUN bit. 10. Wait for the HW_I2C_DEBUG0_ DMAREQ bit to assert. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1886 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) 11. Write the read address to the HW_I2C_DATA register. 12. Clear the HW_I2C_DEBUG0_DMAREQ bit. 13. Wait for the HW_I2C_CTRL1_ DATA_ENGINE_CMPLT_IRQ bit to assert. 14. Clear the HW_I2C_CTRL1_ DATA_ENGINE_CMPLT_IRQ bit. 15. Write the next HW_I2C_CTRL0 word. 16. Reassert the HW_I2C_CTRL0_RUN bit. 17. Wait for the HW_I2C_DEBUG0_ DMAREQ bit to assert. 18. Get the data from the interface by reading the HW_I2C_DATA register. 19. Clear the HW_I2C_DEBUG0_DMAREQ bit. 20. Continue steps 17 through 19 until all data is read and the HW_I2C_CTRL1_ DATA_ENGINE_CMPLT_IRQ bit asserts. This basic way of handshaking with the I2C controller can be followed for reading or writing any amount of data from any slave device on the I2C bus. 27.3.2 PIO Queue Mode The PIO Queue mode is similar to the PIO mode described above except in this mode, control and data writes are queued up into internal FIFOs and executed when the HW_I2C_QUEUECTRL_QUEUE_RUN bit is set. There is one read and one write FIFO implemented in the system. Each FIFO is eight words deep. This mode is enabled by setting the HW_I2C_QUEUECTRL_PIO_QUEUE_MODE bit. This must be set before writing any control/command words or data. To write control words, the information is written to the HW_I2C_QUEUECMD register instead of the HW_I2C_CTRL register. This new register is very similar to the HW_I2C_CTRL and has almost all the same fields except for the soft reset and other block related fields. So essentially, the same control words in the PIO mode example above can be used in this mode but need to be diverted to this new control register. One difference from the other modes is that transfer data is written and read using different registers. The HW_I2C_DATA register is still used similar to the other modes but only for writing I2C transfer data. The HW_I2C_QUEUEDATA register is used to read the receive transfer data is read from the block. As an example of how this mode works, consider the PIO mode execution steps above. PIO Queue mode works the same way with only slight differences. HW_I2C_QUEUECTRL_PIO_QUEUE_MODE bit must be set before any other writes to the CTRL or DATA registers are executed. And instead of kicking off a command and polling or waiting for an interrupt to sequence the writing or reading of data or starting a i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1887 Behavior During Reset new command, all control and data writes to the registers are stored in the write FIFO. Multiple commands (control and supporting data) can be written back-to-back as long as the write FIFO is not full. The read FIFO is used only during an I2C read. This data will also be queued up by the I2C logic. This FIFO data is read back through the HW_I2C_QUEUEDATA register. If there are multiple read data words in the queue, the next one will be immediately available after a read from the data register. So, it is possible for software to wait until multiple words are available and then do multiple or burst reads from the HW_I2C_QUEUEDATA register. The HW_I2C_QUEUECTRL_QUEUE_RUN bit may be set after the commands are queued up or before. If the bit is set while the write FIFO is empty, then the logic will wait until the control word is written. Care must be taken that control words and data are written in the proper order as explained above; otherwise, commands will not execute properly. The read and write FIFOs are managed with a watermark or FIFO threshold mechanism and an interrupt per FIFO. The HW_I2C_QUEUECTRL_WR_THRESH and HW_I2C_QUEUECTRL_RD_THRESH fields set the threshold values. These values are in units of words which is the basic unit of the FIFOs. For HW_I2C_QUEUECTRL_WR_THRESH, the associated interrupt bit will assert whenever the number of words in the FIFO is less than or equal to the threshold value. For HW_I2C_QUEUECTRL_RD_THRESH, the associated interrupt bit will assert whenever the number of words in the FIFO is greater than or equal to the threshold value. Note that the associated interrupt bits will assert whether or not the interrupt is enabled back to the processor. These threshold and interrupts will allow the CPU to be notified when the I2C channel needs to be serviced and eliminates the need for software to poll for transaction status. 27.4 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1888 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) 27.4.1 Pinmux Selection During Reset For proper I2C operation, the appropriate pinmux(s) must be selected before taking the block out of reset. Failure to select the I2C pinmux selections before taking the block out of reset will cause the I2C clock to operate incorrectly and will require another I2C hardware reset. 27.4.1.1 Correct and Incorrect Reset Examples Incorrect: Clear I2C SFTRST/CLKGATE ... Setup ... I2C PinMux Selections ** I2C will not operate. Correct: I2C PinMux Selections Clear I2C SFTRST/CLKGATE ... Setup ... ** I2C operates correctly. 27.5 Programmable Registers I2C Hardware Register Format Summary I2C0 base address is 0x80058000; I2C2 base address is 0x8005A000 HW_I2C memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8005_8000 I2C Control Register 0 (HW_I2C_CTRL0) 32 R/W C000_0000h 27.5.1/1890 8005_8010 I2C Timing Register 0 (HW_I2C_TIMING0) 32 R/W 0078_0030h 27.5.2/1893 8005_8020 I2C Timing Register 1 (HW_I2C_TIMING1) 32 R/W 0080_0030h 27.5.3/1894 8005_8030 I2C Timing Register 2 (HW_I2C_TIMING2) 32 R/W 0030_0030h 27.5.4/1895 8005_8040 I2C Control Register 1 (HW_I2C_CTRL1) 32 R/W 0886_0000h 27.5.5/1896 8005_8050 I2C Status Register (HW_I2C_STAT) 32 R 8005_8060 I2C Queue control reg. (HW_I2C_QUEUECTRL) 32 R/W C000_0000h 27.5.6/1900 0000_0000h 27.5.7/1905 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1889 Programmable Registers HW_I2C memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8005_8070 I2C Queue Status Register. (HW_I2C_QUEUESTAT) 32 R 0000_2020h 27.5.8/1906 8005_8080 I2C Queue command reg (HW_I2C_QUEUECMD) 32 R/W 0000_0000h 27.5.9/1908 8005_8090 I2C Controller Read Data Register for queue mode only. (HW_I2C_QUEUEDATA) 32 R 0000_0000h 27.5.10/ 1911 8005_80A0 I2C Controller DMA Read and Write Data Register (HW_I2C_DATA) 32 R/W 0000_0000h 27.5.11/ 1911 8005_80B0 I2C Device Debug Register 0 (HW_I2C_DEBUG0) 32 R/W 0010_0000h 27.5.12/ 1912 8005_80C0 I2C Device Debug Register 1 (HW_I2C_DEBUG1) 32 R/W C000_0000h 27.5.13/ 1914 8005_80D0 I2C Version Register (HW_I2C_VERSION) 32 R 0104_0000h 27.5.14/ 1916 27.5.1 I2C Control Register 0 (HW_I2C_CTRL0) The I2C Control Register specifies the reset state and the command and transfer size information for the I2C controller. HW_I2C_CTRL0: 0x000 HW_I2C_CTRL0_SET: 0x004 HW_I2C_CTRL0_CLR: 0x008 HW_I2C_CTRL0_TOG: 0x00C This register is either written by the DMA or the CPU depending on the state of an I2C transaction. EXAMPLE // turn off soft reset and clock gating HW_I2C_CTRL0_CLR(BM_I2C_CTRL0_SFTRST | BM_I2C_CTRL0_CLKGATE); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1890 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) Address: 8005_8000h base + 0h offset = 8005_8000h 20 19 18 17 16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R RSVD1 1 RSVD2 RUN DIRECTION 21 MASTER_MODE 22 SLAVE_ADDRESS_ENABLE 23 PRE_SEND_START PRE_ ACK 24 POST_SEND_STOP 25 RETAIN_CLOCK 26 CLOCK_HELD 27 MULTI_MASTER 28 SEND_NAK_ON_LAST 29 ACKNOWLEDGE 30 CLKGATE 31 SFTRST Bit W Reset Bit R XFER_COUNT W Reset 0 0 0 0 0 0 0 0 0 HW_I2C_CTRL0 field descriptions Field 31 SFTRST Description Set to zero for normal operation. When this bit is set to one (default), then the entire block is held in its reset state. 0x0 0x1 30 CLKGATE RUN -- Allow I2C to operate normally. RESET -- Hold I2C in reset. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. 0x0 0x1 RUN -- Allow I2C to operate normally. NO_CLKS -- Do not clock I2C gates in order to minimize power consumption. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1891 Programmable Registers HW_I2C_CTRL0 field descriptions (continued) Field 29 RUN Description Set this bit to one to enable the I2C Controller operation. This bit is automatically set by DMA commands that write to CTRL1 after the last PIO write of the DMA command. For Soft DMA operation, software can set this bit to enable the controller. 0x0 0x1 28 RSVD2 27 PRE_ACK HALT -- No I2C command in progress. RUN -- Process a slave or master I2C command. Always set this bit field to zero. Reserved for Freescale use. 26 Set this bit to one to cause a pending acknowledge bit (prior to DMA transfer) to be acknowledged. Set it ACKNOWLEDGE to zero to NAK the pending acknowledge bit. This bit is set to one by the slave search engine if the criteria is met for acknowledging a slave address. Software can reset the bit to slave-not-acknowledge the address. This bit defines the state of the i2c_data line during the address acknowledge bit time. The slave search engine holds the clock at this point for a software decision. This bit has no effect when the presend start option is selected. 0x0 0x1 SNAK -- slave not acknowledge when the held clock is released. ACK -- slave acknowledge when the held clock is released. 25 Set this bit to one to cause the DMA transfer engine to send a NAK on the last byte. SEND_NAK_ON_ 0x0 ACK_IT -- Send an ACK on the last byte received. LAST 0x1 NAK_IT -- Send a NAK on the last byte received. 24 RSVD1 Always set this bit field to zero. 23 Set this bit to one to enable the master state machine to monitor the start conditions generated by other MULTI_MASTER masters. The bus is assumed to be busy from the first start condition generated by another master until a stop condition is generated. 0x0 0x1 22 CLOCK_HELD SINGLE -- Assume we are the only master. MULTIPLE -- Enable multiple master bus busy monitoring from start detects. This bit is set to one by the I2C controller state machines. It holds the I2C clock line low until cleared. It must be cleared by firmware, either by CPU instructions or DMA PIO transactions. It is set high when a slave address is matched by the slave controller. It is also set high at the end of a master or slave transaction that had the RETAIN_CLOCK bit set high. Software should not set this bit to one. 0x0 0x1 RELEASE -- Release the clock line. HELD_LOW -- The clock line is currently being held low. 21 Set this bit to one to retain the clock at the end of this transaction. This has the effect of holding the clock RETAIN_CLOCK low until the start of the next transaction. 0x0 0x1 20 POST_SEND_ STOP RELEASE -- Release the clock line after this data transfer. HOLD_LOW -- Hold the clock line low after this data transfer. Set this bit to one to send a stop condition after transferring the data associated with this transaction. This bit is automatically cleared by the hardware after the operation has been performed. 0x0 0x1 NO_STOP -- Do not send a stop condition before this transaction. SEND_STOP -- Send a stop condition before this transaction. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1892 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) HW_I2C_CTRL0 field descriptions (continued) Field Description 19 PRE_SEND_ START Set this bit to one to send a start condition before transferring the data associated with this transaction. This bit is automatically cleared by the hardware after the operation has been performed. 18 SLAVE_ ADDRESS_ ENABLE Set this bit to one to enable the slave address decoder. When an address match occurs, the I2C bus clock is frozen, by setting HW_I2C_CTRL0_CLOCK_HELD, and an interrupt is generated. 0x0 0x1 0x0 0x1 NO_START -- Do not send a start condition before this transaction. SEND_START -- Send a start condition before this transaction. DISABLED -- Disable the slave address decoder. ENABLED -- Enable the slave address decoder. 17 Set this bit to one to select master mode. Set it zero to select slave mode. MASTER_MODE 0x0 SLAVE -- Operate in slave mode. 0x1 MASTER -- Operate in master mode. 16 DIRECTION Set this bit to one to select an I2C transmit operation in either slave or master mode. XMIT = write in master mode, read in slave mode. Set this bit to zero to select an I2C receive operation in either slave or master mode. 0x0 0x1 XFER_COUNT RECEIVE -- I2C receive operation for slave or master. TRANSMIT -- I2C transmit operation for slave or master. Number of bytes to transfer. This field decrements as bytes are transferred. 27.5.2 I2C Timing Register 0 (HW_I2C_TIMING0) The timing for various phases of I2C Controller Commands are further defined by fields in the I2C Timing Register 0. HW_I2C_TIMING0: 0x010 HW_I2C_TIMING0_SET: 0x014 HW_I2C_TIMING0_CLR: 0x018 HW_I2C_TIMING0_TOG: 0x01C This register is primarily used for clock and timing generation. EXAMPLE HW_I2C_TIMING0_WR(0x00780030); // high time = 120 clocks, read bit at 48 for 95KHz at 24mhz HW_I2C_TIMING0_WR(0x000F0007); // high time = 15 clocks, read bit at 7 for 400KHz at 24mhz i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1893 Programmable Registers Address: 8005_8000h base + 10h offset = 8005_8010h Bit 31 30 29 28 27 26 25 24 23 RSVD2 R 0 0 0 0 21 20 19 18 17 16 15 14 0 0 0 0 0 1 1 1 1 13 12 11 10 9 8 7 RSVD1 HIGH_COUNT W Reset 22 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 RCV_COUNT 0 0 0 0 0 0 1 1 0 HW_I2C_TIMING0 field descriptions Field Description 31-26 RSVD2 Always set this bit field to zero. 25-16 HIGH_COUNT 15-10 RSVD1 Load this bit field with the APBX clock count for the high period of the I2C clock. Always set this bit field to zero. RCV_COUNT Load this bit field with the APBX clock count for capturing read data after the I2C clock goes high. 27.5.3 I2C Timing Register 1 (HW_I2C_TIMING1) The timing for various phases of I2C Controller Commands are further defined by fields in the I2C Timing Register 1. HW_I2C_TIMING1: 0x020 HW_I2C_TIMING1_SET: 0x024 HW_I2C_TIMING1_CLR: 0x028 HW_I2C_TIMING1_TOG: 0x02C This register is primarily used for clock and timing generation. EXAMPLE HW_I2C_TIMING1_WR(0x00800030); // low time at 128, write bit at 48 for 95 kHz at 24 MHz HW_I2C_TIMING1_WR(0x001F000F); // low time at 31, write bit at 15 for 400 kHz at 24 MHz Address: 8005_8000h base + 20h offset = 8005_8020h Bit 31 30 29 28 27 26 25 24 23 RSVD2 R 0 0 0 0 21 20 19 18 17 16 15 14 0 0 0 0 1 0 0 0 0 13 12 11 10 9 8 7 RSVD1 LOW_COUNT W Reset 22 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 XMIT_COUNT 0 0 0 0 0 0 1 1 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1894 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) HW_I2C_TIMING1 field descriptions Field Description 31-26 RSVD2 Always set this bit field to zero. 25-16 LOW_COUNT 15-10 RSVD1 Load this bit field with the APBX clock count for the low period of the I2C clock. Always set this bit field to zero. XMIT_COUNT Load this bit field with the APBX clock count for changing transmitted data after the I2C clock goes low. Set this value to produce valid i2c setup and hold times at the desired bit rate for the current APBX clock rate. 27.5.4 I2C Timing Register 2 (HW_I2C_TIMING2) The timing for various phases of I2C Controller Commands are further defined by fields in the I2C Timing Register 2. HW_I2C_TIMING2: 0x030 HW_I2C_TIMING2_SET: 0x034 HW_I2C_TIMING2_CLR: 0x038 HW_I2C_TIMING2_TOG: 0x03C This register is primarily used for clock and timing generation. EXAMPLE HW_I2C_TIMING2_WR(0x0015000d); // bus free count of 21 lead in count of 13 Address: 8005_8000h base + 30h offset = 8005_8030h Bit 31 30 29 28 27 26 25 24 23 RSVD2 R 0 0 0 0 21 20 19 18 17 16 15 14 0 0 0 0 0 0 1 1 0 13 12 11 10 9 8 7 RSVD1 BUS_FREE W Reset 22 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 LEADIN_COUNT 0 0 0 0 0 0 1 1 0 HW_I2C_TIMING2 field descriptions Field 31-26 RSVD2 25-16 BUS_FREE Description Always set this bit field to zero. Load this bit field with the APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1895 Programmable Registers HW_I2C_TIMING2 field descriptions (continued) Field 15-10 RSVD1 Description Always set this bit field to zero. LEADIN_COUNT Load this bit field with the APBX clock count for delaying the rising edge of i2c_sck after the kick. 27.5.5 I2C Control Register 1 (HW_I2C_CTRL1) The I2C Controller Command is further defined by fields in this control extension register. The I2C Control Register 1 is where the I2C slave address is specified. Fast or normal mode is selected here. HW_I2C_CTRL1: 0x040 HW_I2C_CTRL1_SET: 0x044 HW_I2C_CTRL1_CLR: 0x048 HW_I2C_CTRL1_TOG: 0x04C This control register is primarily used for interrupt management. It also controls the special slave address matching mode. EXAMPLE HW_I2C_CTRL1_CLR(BM_I2C_CTRL1_SLAVE_IRQ); // clear the slave interrupt i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1896 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) Address: 8005_8000h base + 40h offset = 8005_8040h 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA_ENGINE_CMPLT_IRQ NO_SLAVE_ACK_IRQ OVERSIZE_XFER_TERM_IRQ EARLY_TERM_IRQ MASTER_LOSS_IRQ SLAVE_STOP_IRQ SLAVE_IRQ 16 BUS_FREE_IRQ 17 BCAST_SLAVE_EN 18 SLAVE_IRQ_EN 19 FORCE_CLK_IDLE 20 SLAVE_STOP_IRQ_EN 21 FORCE_DATA_IDLE 22 MASTER_LOSS_IRQ_EN 23 ACK_MODE 24 EARLY_TERM_IRQ_EN 25 CLR_GOT_A_NAK 26 OVERSIZE_XFER_TERM_IRQ_EN 27 WR_QUEUE_IRQ 28 NO_SLAVE_ACK_IRQ_EN 29 RD_QUEUE_IRQ 30 DATA_ENGINE_CMPLT_IRQ_EN R RSVD1 31 BUS_FREE_IRQ_EN Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLAVE_ADDRESS_BYTE W Reset Bit R W Reset HW_I2C_CTRL1 field descriptions Field 31 RSVD1 Description Always set this bit field to zero. 30 This bit is set to indicate that an interrupt is requested by the I2C controller because the read queue RD_QUEUE_IRQ threshold criterion has been met. This bit is cleared by software by writing a one to its SCT clear address. Note that the enable bit for this interrupt is in the HW_I2C_QUEUECTRL register. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1897 Programmable Registers HW_I2C_CTRL1 field descriptions (continued) Field Description 0x0 0x1 29 WR_QUEUE_ IRQ This bit is set to indicate that an interrupt is requested by the I2C controller because the write queue threshold criterion has been met. This bit is cleared by software by writing a one to its SCT clear address. Note that the enable bit for this interrupt is in the HW_I2C_QUEUECTRL register. 0x0 0x1 28 CLR_GOT_A_ NAK 27 ACK_MODE NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. Setting this bit will clear the got_a_nak. 0x0 0x1 DO_NOTHING -- CLEAR -- Clear got_a_nak. This setting affects the behavior of the ACK pulse when RETAIN_CLOCK=1. 0x0 0x1 ACK_AFTER_HOLD_LOW -- ACK will occur after clock is held low at start of next access. ACK_BEFORE_HOLD_LOW -- ACK will occur at end of access before clock is held low. 26 Writing a one to this bit will force the data state machine to return to its idle state and stay there. FORCE_DATA_ IDLE 25 FORCE_CLK_ IDLE Writing a one to this bit will force the clock generator state machine to return to its idle state and stay there. 24 Set this bit to one to enable the slave address search machine to look for both a match to the programmed BCAST_SLAVE_ slave address as well as a match to the broadcast address of all zeroes. EN 0x0 NO_BCAST -- Do not watch for broadcast address while matching programmed slave address. 0x1 WATCH_BCAST -- Watch for the all zeroes broadcast address while matching programmed slave address. 23-16 SLAVE_ ADDRESS_ BYTE Slave address byte, note the slave address is only seven bits long. The slave address search state machine will respond to either a read or a write command issued to the seven bit address. Set the LSB (bit 0) to one to match ALL 7 bit i2c addresses. 15 BUS_FREE_ IRQ_EN Set this bit to one to enable bus free interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. 0x0 0x1 DISABLED -- No Interrupt Request Pending. ENABLED -- Interrupt Request Pending. 14 Set this bit to one to enable data engine complete interrupt requests to be routed to the interrupt collector. DATA_ENGINE_ Set to zero to disable interrupts from the I2C controller. CMPLT_IRQ_EN 0x0 DISABLED -- No Interrupt Request Pending. 0x1 ENABLED -- Interrupt Request Pending. 13 NO_SLAVE_ ACK_IRQ_EN Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. 0x0 0x1 DISABLED -- No Interrupt Request Pending. ENABLED -- Interrupt Request Pending. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1898 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) HW_I2C_CTRL1 field descriptions (continued) Field 12 OVERSIZE_ XFER_TERM_ IRQ_EN Description Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable interrupts from the I2C controller. 0x0 0x1 DISABLED -- No Interrupt Request Pending. ENABLED -- Interrupt Request Pending. 11 Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable EARLY_TERM_ interrupts from the I2C controller. IRQ_EN 0x0 DISABLED -- No Interrupt Request Pending. 0x1 ENABLED -- Interrupt Request Pending. 10 Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable MASTER_ interrupts from the I2C controller. LOSS_IRQ_EN 0x0 DISABLED -- No Interrupt Request Pending. 0x1 ENABLED -- Interrupt Request Pending. 9 Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable SLAVE_STOP_ interrupts from the I2C controller. IRQ_EN 0x0 DISABLED -- No Interrupt Request Pending. 0x1 ENABLED -- Interrupt Request Pending. 8 Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable SLAVE_IRQ_EN interrupts from the I2C controller. The corresponding HW_I2C_CTRL1_SLAVE_IRQ interrupt bit is set by the slave search engine to indicate that it has stopped searching due to an address match or error. 0x0 0x1 DISABLED -- No Interrupt Request Pending. ENABLED -- Interrupt Request Pending. 7 This bit is set to indicate that an interrupt is requested by the I2C controller because the bus has become BUS_FREE_IRQ free. This bit is cleared by software by writing a one to its SCT clear address. This interrupt indicates that the I2C bus, which was busy, has just become free. 0x0 0x1 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. 6 This bit is set to indicate that an interrupt is requested by the I2C controller because the data engine DATA_ENGINE_ transfer has completed. This bit is cleared by software by writing a one to its SCT clear address. This CMPLT_IRQ interrupt indicates that the data engine has completed a DMA transfer in either master or slave mode. This notification is useful for pio mode master write (transmit) or slave read (transmit) operations, i.e., data engine transmit operations. PIO receive operations are not supported. 0x0 0x1 5 NO_SLAVE_ ACK_IRQ This bit is set to indicate that an interrupt is requested by the I2C controller because the slave addressed by a master transfer did not respond with an acknowledge. This bit is cleared by software by writing a one to its SCT clear address. 0x0 0x1 4 OVERSIZE_ XFER_TERM_ IRQ NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software by writing a one to its SCT clear address. This interrupt indicates that a master DMA transfer did not complete by the end of the transfer size. This is indicated by the slave acknowledging the last byte of a write transfer instead of NAKing it. The master should then send additional bytes of data if desired. This interrupt is only used in slave mode. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1899 Programmable Registers HW_I2C_CTRL1 field descriptions (continued) Field Description 0x0 0x1 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. 3 This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software EARLY_TERM_ by writing a one to its SCT clear address. This interrupt indicates that a master write transfrom from the IRQ STMP38xx to a slave device was NAKed by the slave before the transfer was completed. In slave mode, it indicates that the master NAKed a byte transmitted by the slave causing early termination of the expected transfer. 0x0 0x1 2 MASTER_ LOSS_IRQ NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software by writing a one to its SCT clear address. This interrupt indicates that a master read or write transaction lost an arbitration with another master. Master loss is indicated by the master attempting to transmit a one to the bus at the same time as another master writes a zero. The wired and bus produces a zero on the bus which is detected by the lossing master. 0x0 0x1 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. 1 This bit is set to indicate that an I2C Stop Condition was received by the slave address search engine after SLAVE_STOP_ it had found a start command addressed to its slave address. IRQ 0x0 NO_REQUEST -- No Interrupt Request Pending. 0x1 REQUEST -- Interrupt Request Pending. 0 SLAVE_IRQ This bit is set to indicate that an interrupt is requested by the I2C controller. This bit is cleared by software by writing a one to its SCT clear address. This bit is set by the slave search engine to indicate that it has stopped searching due to an address match or error. 0x0 0x1 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. 27.5.6 I2C Status Register (HW_I2C_STAT) The I2C Controller reports status information in the I2C Status Register. The status register provides read-only access to the function presence bits, as well as the busy indicators for the slave and master state machines. EXAMPLE while(HW_I2C_STAT.SLAVE_BUSY != BV_I2C_STAT_SLAVE_BUSY__IDLE_VAL);// then wait till it finishes i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1900 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) 30 29 28 ANY_ENABLED_IRQ GOT_A_NAK R 31 SLAVE_PRESENT Bit MASTER_PRESENT Address: 8005_8000h base + 50h offset = 8005_8050h 1 1 0 0 27 26 25 24 23 22 RSVD1 21 20 19 18 17 16 0 0 RCVD_SLAVE_ADDR W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1901 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLAVE_SEARCHING DATA_ENGINE_DMA_WAIT BUS_BUSY CLK_GEN_BUSY DATA_ENGINE_BUSY SLAVE_BUSY BUS_FREE_IRQ_SUMMARY DATA_ENGINE_CMPLT_IRQ_SUMMARY NO_SLAVE_ACK_IRQ_SUMMARY OVERSIZE_XFER_TERM_IRQ_SUMMARY EARLY_TERM_IRQ_SUMMARY MASTER_LOSS_IRQ_SUMMARY SLAVE_STOP_IRQ_SUMMARY SLAVE_IRQ_SUMMARY R 15 SLAVE_FOUND Bit SLAVE_ADDR_EQ_ZERO Programmable Registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset HW_I2C_STAT field descriptions Field Description 31 MASTER_ PRESENT This read-only bit indicates that the I2C master function is present when it reads back a one. This I2C function is not available on a device that returns a zero for this bit field. 30 SLAVE_ PRESENT This read-only bit indicates that the I2C slave function is present when it reads back a one. This I2C function is not available on a device that returns a zero for this bit field. 0x0 0x1 UNAVAILABLE -- I2C is not present in this product. AVAILABLE -- I2C is present in this product. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1902 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) HW_I2C_STAT field descriptions (continued) Field Description 0x0 0x1 UNAVAILABLE -- I2C is not present in this product. AVAILABLE -- I2C is present in this product. 29 This read-only bit indicates that the I2C controller has at least one enable interrupt requesting service. It is ANY_ENABLED_ the logic OR of all of the IRQ summary bits. IRQ 0x0 NO_REQUESTS -- No enabled interrupts are requesting service. 0x1 AT_LEAST_ONE_REQUEST -- At least one of the summary interrupt bits is set. 28 GOT_A_NAK 27-24 RSVD1 Read-only view of the got-a-nak signal. 0x0 0x1 NO_NAK -- I2C master has not detected a NAK. DETECTED_NAK -- I2C master has detected a NAK. Always set this bit field to zero. 23-16 This read-only byte indicates that the state of the slave I2C address byte received, including the read/write RCVD_SLAVE_ bit received from an address byte that matched our slave address. ADDR 15 This read-only bit indicates that the I2C slave function was searching for a transaction that matches the SLAVE_ADDR_ current slave address. When set to one, it indicates that an address match was found for the exact EQ_ZERO adderss 0x00. 0x0 0x1 ZERO_NOT_MATCHED -- I2C slave search did not match a zero. WAS_ZERO -- I2C has found an address match against address 0x00. 14 This read-only bit indicates that the I2C slave function was searching for a transaction that matches the SLAVE_FOUND current slave address. When set to one, it indicates that an address match was found and the I2C clock is frozen by the slave search. This bit is cleared by starting the appropriate slave DMA transfer or restarting a slave search. 0x0 0x1 13 SLAVE_ SEARCHING IDLE -- I2C slave search is idle. WAITING -- I2C has found an address match and is holding the I2C clock line low. This read-only bit indicates that the I2C slave function is searching for a transaction that matches the current slave address. 0x0 0x1 IDLE -- I2C slave search is idle. ACTIVE -- I2C is actively searching for an address match. 12 This read-only bit is set to one when the data engine is waitng for data from a DMA device. This bit can be DATA_ENGINE_ used to transmit short I2C transactions without using a DMA channel. This generally works for up to three DMA_WAIT data bytes transmitted with one address byte. 0x0 0x1 11 BUS_BUSY This read-only bit indicates that the I2C bus is busy with a transaction. It is set by a start condition and reset by a detected stop condition. 0x0 0x1 10 CLK_GEN_ BUSY CONTINUE -- I2C master is not waiting on data from the DMA. WAITING -- I2C master is waiting on data from the DMA. IDLE -- I2C bus is idle, i.e. reset state or at least one stop condition detected. BUSY -- I2C bus is busy, i.e. at least one start condition has been detected. This read-only bit indicates that the I2C clock generator is busy with a transaction. 0x0 0x1 IDLE -- I2C clock generator is idle. BUSY -- I2C clock generator is busy performing a command. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1903 Programmable Registers HW_I2C_STAT field descriptions (continued) Field Description 9 This read-only bit indicates that the I2C data transfer engine is busy with a data transmit or recieve DATA_ENGINE_ opertion. In addition, it can be busy, as a master, sending a start or stop condition. BUSY 0x0 IDLE -- I2C Data Engine is idle. 0x1 BUSY -- I2C is Data Engine busy performing a data transfer. 8 SLAVE_BUSY This read-only bit indicates that the I2C slave address search engine is busy with a transaction. This bit will go high when an address search is started and will remain high until the slave search engine returns to its idle state. 0x0 0x1 IDLE -- I2C slave search engine is idle. BUSY -- I2C slave search engine is busy searching for an address match. 7 This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the BUS_FREE_ corresponding interrupt status bit and interrupt enable bit. IRQ_SUMMARY 0x0 NO_REQUEST -- No Interrupt Request Pending. 0x1 REQUEST -- Interrupt Request Pending. 6 This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the DATA_ENGINE_ corresponding interrupt status bit and interrupt enable bit. CMPLT_IRQ_ 0x0 NO_REQUEST -- No Interrupt Request Pending. SUMMARY 0x1 REQUEST -- Interrupt Request Pending. 5 NO_SLAVE_ ACK_IRQ_ SUMMARY This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. 0x0 0x1 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. 4 This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the OVERSIZE_ corresponding interrupt status bit and interrupt enable bit. XFER_TERM_ IRQ_SUMMARY 0x0 NO_REQUEST -- No Interrupt Request Pending. 0x1 REQUEST -- Interrupt Request Pending. 3 This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the EARLY_TERM_ corresponding interrupt status bit and interrupt enable bit. IRQ_SUMMARY 0x0 NO_REQUEST -- No Interrupt Request Pending. 0x1 REQUEST -- Interrupt Request Pending. 2 MASTER_ LOSS_IRQ_ SUMMARY This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. 0x0 0x1 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. 1 This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the SLAVE_STOP_ corresponding interrupt status bit and interrupt enable bit. IRQ_SUMMARY 0x0 NO_REQUEST -- No Interrupt Request Pending. 0x1 REQUEST -- Interrupt Request Pending. 0 SLAVE_IRQ_ SUMMARY This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the corresponding interrupt status bit and interrupt enable bit. 0x0 0x1 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1904 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) 27.5.7 I2C Queue control reg. (HW_I2C_QUEUECTRL) The I2C Control Register implements the controls for I2C PIO Queue mode. HW_I2C_QUEUECTRL: 0x060 HW_I2C_QUEUECTRL_SET: 0x064 HW_I2C_QUEUECTRL_CLR: 0x068 HW_I2C_QUEUECTRL_TOG: 0x06C Address: 8005_8000h base + 60h offset = 8005_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD3 R RD_THRESH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WR_CLEAR PIO_QUEUE_MODE RD_QUEUE_IRQ_EN WR_QUEUE_IRQ_EN Bit 0 RD_CLEAR Reset QUEUE_RUN W 0 0 0 0 0 0 RSVD2 R RSVD1 WR_THRESH W Reset 0 0 0 0 0 0 0 0 0 0 HW_I2C_QUEUECTRL field descriptions Field 31-21 RSVD3 Description Always set this bit field to zero. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1905 Programmable Registers HW_I2C_QUEUECTRL field descriptions (continued) Field 20-16 RD_THRESH 15-13 RSVD2 12-8 WR_THRESH 7-6 RSVD1 5 QUEUE_RUN Description This field specified the threshold value of the number of read queue words, or more, that should be in the queue before a read queue interrupt is generated to the CPU. The valid range for this field is 0-7. A value of 0 indicates a threshold of an empty queue. Always set this bit field to zero. This field specified the threshold value of the number of write queue words, or less, that should be in the queue before a write queue interrupt is generated to the CPU. The valid range for this field is 0-8. A value of 0 indicates a threshold of an empty queue. Always set this bit field to zero. Asserting this bit essentially tells the system to begin executing commands and data that are in the queue. This allows software to kick off a series of commands when it chooses. 0x0 0x1 STOP -- Don't process commands or stop after processing the currently executing command. START -- Start processing commands. 4 RD_CLEAR Asserting this bit clears the read queue that holds data read from the I2C port. 3 WR_CLEAR Asserting this bit clears the write queue that holds commands and data written through the QUEUECTRL and DATA registers. 2 PIO_QUEUE_ MODE When this bit is set writes to the QUEUECTRL and DATA registers are queued up. When the HW_I2C_QUEUECTRL_QUEUE_RUN bit is later set, all the commands (and associated data) will be executed in the order they are written. 1 RD_QUEUE_ IRQ_EN Set this bit to one to enable receiving interrupts from the RD_QUEUE_IRQ source to the interrupt collector. Set to zero to disable interrupts from the I2C controller. 0 WR_QUEUE_ IRQ_EN Set this bit to one to enable receiving interrupts from the WR_QUEUE_IRQ source to the interrupt collector. Set to zero to disable interrupts from the I2C controller. 0x0 0x1 0x0 0x1 DISABLED -- Interrupt source disabled. ENABLED -- Interrupt source enabled. DISABLED -- Interrupt source disabled. ENABLED -- Interrupt source enabled. 27.5.8 I2C Queue Status Register. (HW_I2C_QUEUESTAT) This register exposes the state of the internal read and write queues used in PIO Queue mode. HW_I2C_QUEUESTAT: 0x070 HW_I2C_QUEUESTAT_SET: 0x074 HW_I2C_QUEUESTAT_CLR: 0x078 HW_I2C_QUEUESTAT_TOG: 0x07C This information can be useful during debug or by the CPU during normal operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1906 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) Address: 8005_8000h base + 70h offset = 8005_8070h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD 2 WR_QUEUE_FULL WR_QUEUE_EMPTY R 0 RSVD1 Bit 0 RD_QUEUE_EMPTY Reset RD_QUEUE_FULL W 0 0 1 0 0 1 RD_QUEUE_CNT WR_QUEUE_CNT W Reset 0 0 0 0 0 0 0 0 0 0 HW_I2C_QUEUESTAT field descriptions Field 31-15 RSVD2 14 RD_QUEUE_ FULL Description Always set this bit field to zero. A read-only view of the read queue full signal. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1907 Programmable Registers HW_I2C_QUEUESTAT field descriptions (continued) Field Description 13 RD_QUEUE_ EMPTY A read-only view of the read queue empty signal. 12-8 RD_QUEUE_ CNT A read-only view of how many words are currently in the read queue. 7 RSVD1 Always set this bit field to zero. 6 WR_QUEUE_ FULL A read-only view of the write queue full signal. 5 WR_QUEUE_ EMPTY A read-only view of the write queue empty signal. WR_QUEUE_ CNT A read-only view of how many words are currently in the write queue. 27.5.9 I2C Queue command reg (HW_I2C_QUEUECMD) The I2C Command Register accepts commands that are to be queued up for later execution in PIO queue mode. HW_I2C_QUEUECMD: 0x080 HW_I2C_QUEUECMD_SET: 0x084 HW_I2C_QUEUECMD_CLR: 0x088 HW_I2C_QUEUECMD_TOG: 0x08C This register is either written by the CPU to queue up I2C transaction commands for later execution. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1908 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) Address: 8005_8000h base + 80h offset = 8005_8080h 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSVD2 R RSVD1 DIRECTION 23 MASTER_MODE PRE_ ACK 24 SLAVE_ADDRESS_ENABLE 25 PRE_SEND_START 26 POST_SEND_STOP 27 RETAIN_CLOCK 28 CLOCK_HELD 29 MULTI_MASTER 30 SEND_NAK_ON_LAST 31 ACKNOWLEDGE Bit W Reset Bit R XFER_COUNT W Reset 0 0 0 0 0 0 0 0 0 HW_I2C_QUEUECMD field descriptions Field 31-28 RSVD2 27 PRE_ACK Description Always set this bit field to zero. Reserved for Freescale use. 26 Set this bit to one to cause a pending acknowledge bit (prior to DMA transfer) to be acknowledged. Set it ACKNOWLEDGE to zero to NAK the pending acknowledge bit. This bit is set to one by the slave search engine if the criteria is met for acknowledging a slave address. Software can reset the bit to slave-not-acknowledge the address. This bit defines the state of the i2c_data line during the address acknowledge bit time. The slave Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1909 Programmable Registers HW_I2C_QUEUECMD field descriptions (continued) Field Description search engine holds the clock at this point for a software decision. This bit has no effect when the presend start option is selected. 0x0 0x1 SNAK -- slave not acknowledge when the held clock is released. ACK -- slave acknowledge when the held clock is released. 25 Set this bit to one to cause the DMA transfer engine to send a NAK on the last byte. SEND_NAK_ON_ 0x0 ACK_IT -- Send an ACK on the last byte received. LAST 0x1 NAK_IT -- Send a NAK on the last byte received. 24 RSVD1 Always set this bit field to zero. 23 Set this bit to one to enable the master state machine to monitor the start conditions generated by other MULTI_MASTER masters. The bus is assumed to be busy from the first start condition generated by another master until a stop condition is generated. 0x0 0x1 22 CLOCK_HELD SINGLE -- Assume we are the only master. MULTIPLE -- Enable multiple master bus busy monitoring from start detects. This bit is set to one by the I2C controller state machines. It holds the I2C clock line low until cleared. It must be cleared by firmware, either by CPU instructions or DMA PIO transactions. It is set high when a slave address is matched by the slave controller. It is also set high at the end of a master or slave transaction that had the RETAIN_CLOCK bit set high. Software should not set this bit to one. 0x0 0x1 RELEASE -- Release the clock line. HELD_LOW -- The clock line is currently being held low. 21 Set this bit to one to retain the clock at the end of this transaction. This has the effect of holding the clock RETAIN_CLOCK low until the start of the next transaction. 0x0 0x1 20 POST_SEND_ STOP RELEASE -- Release the clock line after this data transfer. HOLD_LOW -- Hold the clock line low after this data transfer. Set this bit to one to send a stop condition after transferring the data associated with this transaction. This bit is automatically cleared by the hardware after the operation has been performed. 0x0 0x1 NO_STOP -- Do not send a stop condition before this transaction. SEND_STOP -- Send a stop condition before this transaction. 19 PRE_SEND_ START Set this bit to one to send a start condition before transferring the data associated with this transaction. This bit is automatically cleared by the hardware after the operation has been performed. 18 SLAVE_ ADDRESS_ ENABLE Set this bit to one to enable the slave address decoder. When an address match occurs, the I2C bus clock is frozen, by setting HW_I2C_CTRL0_CLOCK_HELD, and an interrupt is generated. 0x0 0x1 0x0 0x1 NO_START -- Do not send a start condition before this transaction. SEND_START -- Send a start condition before this transaction. DISABLED -- Disable the slave address decoder. ENABLED -- Enable the slave address decoder. 17 Set this bit to one to select master mode. Set it zero to select slave mode. MASTER_MODE 0x0 SLAVE -- Operate in slave mode. 0x1 MASTER -- Operate in master mode. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1910 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) HW_I2C_QUEUECMD field descriptions (continued) Field Description 16 DIRECTION Set this bit to one to select an I2C transmit operation in either slave or master mode. XMIT = write in master mode, read in slave mode. Set this bit to zero to select an I2C receive operation in either slave or master mode. RECEIVE -- I2C receive operation for slave or master. TRANSMIT -- I2C transmit operation for slave or master. 0x0 0x1 XFER_COUNT Number of bytes to transfer. This field decrements as bytes are transferred. 27.5.10 I2C Controller Read Data Register for queue mode only. (HW_I2C_QUEUEDATA) For queue mode, I2C transfer data is read from this register. Transfer data is read from this register only when in queue mode. This register is somewhat analogous to the HW_I2C_DATA register. This is a read only register. Address: 8005_8000h base + 90h offset = 8005_8090h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_I2C_QUEUEDATA field descriptions Field DATA Description Software should read from this address to retreive data from I2C read operations when . 27.5.11 I2C Controller DMA Read and Write Data Register (HW_I2C_DATA) The I2C Controller DMA Read and Write Data Register is the target for both source and destination DMA and PIO transfers. DMA reads and writes are directed to this register. EXAMPLE The DMA data register is used by the DMA to read or write data from the I2C controller, as mediated by the I2C controller's DMA request signal. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1911 Programmable Registers Address: 8005_8000h base + A0h offset = 8005_80A0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_I2C_DATA field descriptions Field DATA Description The source DMA channel writes to this address. The Destination DMA channel reads from this address. 27.5.12 I2C Device Debug Register 0 (HW_I2C_DEBUG0) The I2C Device Debug Register 0 provides a diagnostic view into various internal states and controls. HW_I2C_DEBUG0: 0x0b0 HW_I2C_DEBUG0_SET: 0x0b4 HW_I2C_DEBUG0_CLR: 0x0b8 HW_I2C_DEBUG0_TOG: 0x0bC EXAMPLE while(HW_I2C_DEBUG0.DMAREQ == old_dma_req_value); // wait for next dma request toggle old_dma_req_value = HW_I2C_DEBUG0.DMAREQ; // remember the new state of the dma request toggle i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1912 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) DMAREQ R 30 29 28 DMATERMINATE 31 DMAKICK Bit DMAENDCMD Address: 8005_8000h base + B0h offset = 8005_80B0h 27 26 25 24 23 22 21 20 19 18 17 16 DMA_STATE STATE_ VALUE 0 0 0 0 0 0 0 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 SLAVE_HOLD_CLK 0 STATE_LATCH 0 CHANGE_TOGGLE R 0 GRAB_TOGGLE Bit 0 STOP_TOGGLE Reset START_TOGGLE W SLAVE_STATE W Reset 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1913 Programmable Registers HW_I2C_DEBUG0 field descriptions Field 31 DMAREQ 30 DMAENDCMD 29 DMAKICK Description The DMA request signal has toggled, active high. Read-only view of the toggle state of the DMA End Command signal. Read-only view of the toggle state of the DMA Kick signal. 28 Read-only view of the toggle state of the DMA Terminate signal. DMATERMINATE 27-26 STATE_VALUE 25-16 DMA_STATE This field contains the lower two bit values of the DMA state machine variable. This value is fixed or freerunning based on the STATE_LATCH bit in this register. This field is used for debug purposes. Current state of the DMA state machine. 15 Read-only view of the start detector. Toggles once for each detected start condition. START_TOGGLE 14 STOP_TOGGLE Read-only view of the stop detector. Toggles once for each detected stop condition. 13 GRAB_TOGGLE Read-only view of the grab receive data timing point. Toggles once for each read timing point, as delayed from rising clock. 12 CHANGE_ TOGGLE Read-only view of the change xmit data timing point. Toggles once for each change xmit data timing point, as delayed from falling clock. 11 STATE_LATCH Changing this bit from a 1 to 0 latches the lower two bits of the current DMA state machine variable into the STATE_VALUE field of this register. A value of 1 causes the STATE_VALUE field to be free-runing. 10 SLAVE_HOLD_ CLK Current State of the Slave Address Search FSM clock hold register. SLAVE_STATE Current State of the Slave Address Search FSM. 27.5.13 I2C Device Debug Register 1 (HW_I2C_DEBUG1) The I2C Device Debug Register 1 provides a diagnostic view of the external bus and provides OE control for the clock and data. HW_I2C_DEBUG1: 0x0c0 HW_I2C_DEBUG1_SET: 0x0c4 HW_I2C_DEBUG1_CLR: 0x0c8 HW_I2C_DEBUG1_TOG: 0x0cC EXAMPLE while(HW_I2C_DEBUG1.I2C_CLK_IN == 0); // wait for I2C clock line to go high i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1914 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) Address: 8005_8000h base + C0h offset = 8005_80C0h 25 24 23 22 21 20 19 18 17 16 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FORCE_I2C_CLK_OE 26 FORCE_I2C_DATA_OE 27 FORCE_RCV_ACK 28 FORCE_ARB_LOSS 29 FORCE_CLK_ON 30 I2C_DATA_IN R 31 I2C_CLK_IN Bit 0 0 0 0 0 RSVD4 DMA_BYTE_ENABLES CLK_GEN_STATE W Bit RSVD2 R LST_MODE W Reset 0 0 0 0 0 0 0 RSVD1 LOCAL_SLAVE_TEST Reset 0 0 0 0 HW_I2C_DEBUG1 field descriptions Field Description 31 I2C_CLK_IN A copy of the pad input signal for the I2C clock pad. 30 I2C_DATA_IN A copy of the pad input signal for the I2C data pad. 29-28 RSVD4 Always set this bit field to zero. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1915 Programmable Registers HW_I2C_DEBUG1 field descriptions (continued) Field 27-24 DMA_BYTE_ ENABLES 23-16 CLK_GEN_ STATE 15-11 RSVD2 10-9 LST_MODE Description A read-only view of the byte enables for HW_I2C_DATA register writes. These bits are used in the I2C DMA state machine to track the number of bytes written by the DMA. Individual bits are cleared as they are consummed. A read-only view on current state of clock generation state machine. Always set this bit field to zero. When in local slave test mode, this bit field defines the type of address generated for the slave. 0x0 0x1 0x2 0x3 BCAST -- Broadcast, i.e. i2c address 0x00. MY_WRITE -- Send to my slave address with a RW bit equal 0. MY_READ -- Send to my slave address with a RW bit equal 1. NOT_ME -- Send to an address that is not mine, i.e. bit four is complemented. 8 Writting a one to this bit places the slave in local test mode. one of three slave address can be sent in LOCAL_SLAVE_ either read or write mode. TEST 7-5 RSVD1 Always set this bit field to zero. 4 FORCE_CLK_ ON Writing a one to this bit will force the clock generator to send a continuous stream of clocks on the I2C bus. 3 FORCE_ARB_ LOSS Writing a one to this bit will force the appearance of an arbitration loss on the next one a master attempts to transmit. 2 FORCE_RCV_ ACK Writing a one to this bit will force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer. 1 FORCE_I2C_ DATA_OE Writting a one to this bit will force an output enable at the pad. The pad data line is tied to zero. Thus the I2C data line will either be hi-z or zero. 0 FORCE_I2C_ CLK_OE Writing a one to this bit will force an output enable at the pad. The pad data line is tied to zero. Thus the I2C clock line will either be hi-z or zero. 27.5.14 I2C Version Register (HW_I2C_VERSION) This register always returns a known read value for debug purposes it indicates the version of the block. EXAMPLE if (HW_I2C_VERSION.B.MAJOR != 1) Error(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1916 Freescale Semiconductor, Inc. Chapter 27 Inter IC (I2C) Address: 8005_8000h base + D0h offset = 8005_80D0h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 HW_I2C_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1917 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1918 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller 28.1 Pulse Width Modulator (PWM) Overview The device has eight PWM output controllers that can be used in place of GPIO pins. Applications include HSADC driving signals and LED & backlight brightness control. Independent output control of each phase allows 0, 1, or high-impedance to be independently selected for the active and inactive phases. Individual outputs can be run in lock step with guaranteed non-overlapping portions for differential drive applications. Figure 28-1 shows the block diagram of the PWM controller. The controller does not use DMA. Initial values of Period, Active, and Inactive widths are set for each desired channel. The outputs are selected by phase and then the desired PWM channels are simultaneously enabled. This effectively launches the PWM outputs to autonomously drive their loads without further intervention. 28.2 Operation Each PWM channel has two control registers that are used to specify the channel output: HW_PWM_ACTIVEn and HW_PWM_PERIODn. When programming a channel, it is important to remember that there is an order dependence for register writes. * The HW_PWM_ACTIVEn register must be written first, followed by HW_PWM_PERIODn. * If the order is reversed, the parameters written to the HW_PWM_ACTIVEn register will not take effect in the hardware. The hardware waits for a HW_PWM_PERIODn register write to update the hardware with the values in both registers. This register write order dependence allows smooth onthe-fly reprogramming of the channel. Also, when the user reprograms the channel in this i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1919 Operation manner, the new register values will not take effect until the beginning of a new output period. This eliminates the potential for output glitches that could occur if the registers were updated while the channel was enabled and in the middle of a cycle. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1920 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller ARM Core SRAM 24-MHz XTAL Osc. AHB AHB Slave AHB Master Divide by n PWM0_OUT Shared DMA AHB-to-APBX Bridge HSADC_OUT APBX APBX Master 24-MHz XTAL Osc. Hsadc clock sel 1/m, m=1,2,4, 8,16, 64, 256,1024 Count0 resets at Period0 Act.,Inact. State0 PWM Programmable Registers Period0 Hsadc clock PWM7_OUT E.L. Backlight Active0 ,Inactive0 PWM0 Active0 >= Count0 Count0 < Inactive0 ACT Active1 ,Inactive1 1/m, m=1,2,4, 8,16, 64, 256,1024 Count1 resets at Period1 Active1 >= Count1 Count1 < Inactive1 E.L. Backlight PWM1 ACT Active2 ,Inactive2 1/m, m=1,2,4, 8,16, 64, 256,1024 Count2 resets at Period2 Active2 >= Count2 Count2 < Inactive2 E.L. Backlight PWM2 ACT Active3 ,Inactive3 1/m, m=1,2,4, 8,16, 64, 256,1024 Count3 resets at Period3 Active3 >= Count3 Count3 < Inactive3 Application PWM3 ACT Active4 ,Inactive4 1/m, m=1,2,4, 8,16, 64, 256,1024 Count4 resets at Period4 Active4 >= Count4 Count4 < Inactive4 Host Power PWM4 ACT Active5 ,Inactive5 1/m, m=1,2,4, 8,16, 64, 256,1024 Count5 resets at Period5 Active5 >= Count5 Count5 < Inactive5 Host Power PWM5 ACT Host Power Active6 ,Inactive6 1/m, m=1,2,4, 8,16, 64, 256,1024 Count6 resets at Period6 HSADC_SEL Active6 >= Count6 Count6 < Inactive6 Active7 ,Inactive7 PWM6 ACT Host Power PWM7 i.MX28 Processor Reference Count7 resets 1/m, m=1,2,4, 8,16, Applications Active 7 >= Count7Manual, Rev. 2, 08/2013 ACT at Period7 64, 256,1024 Count7 < Inactive7 Freescale Semiconductor, Inc. 1921 Operation Each channel has a dedicated internal 16-bit counter that increments once for each divided clock period presented from the clock divider. * The internal counter resets when it reaches the value stored in the channel control registers, for example, HW_PWM_PERIOD0_PERIOD. * The Active flip-flop is set to 1 when the internal counter reaches the value stored in HW_PWM_ACTIVE0_ACTIVE. * It remains high until the internal counter exceeds the value stored in HW_PWM_ACTIVE0_INACTIVE. These two values define the starting and ending points for the logically "active" portion of the waveform. As shown in Figure 28-2, the actual state on the output for each phase, for example, active or inactive, is completely controlled by the active and inactive state values in the channel control registers. HW_PWM_ACTIVE0_ACTIVE HW_PWM_ACTIVE0_INACTIVE HW_PWM_PERIOD0_PERIOD PERIOD INACTIVE ACTIVE ACTIVE_FF PWM0 Output inactive_state[1:0] active_state[1:0] inactive_state[1:0] active_state[1:0] HW_PWM_PERIOD0_ACTIVE_STATE HW_PWM_PERIOD0_INACTIVE_STATE Figure 28-2. PWM Output Example The actual values obtainable on the output are shown in Figure 28-2. Notice that one possible state is to turn off the output driver to provide a high-Z output. This is useful for external circuits that drive E.L. backlights and for direct drive of LEDs. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1922 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller 28.2.1 XTAL OSC Driving Mode By default, every PWM channel outputs signals in XTAL OSC clock domain. It's a 24 MHz XTAL OSC. By setting up two channels in lock step and by setting their low and high states to opposite values, one can generate a differential signal pair that alternates between pulling to Vss and floating to high-Z. By creating an appropriate offset in the settings of the two channels with the same period and the same enables, one can generate differential drive pulses with digitally guaranteed non-overlapping intervals suitable for controlling highvoltage switches. In Figure 28-3, a differential pair is established using Channel 0 and Channel 1. The period is set for 1280 divided clocks for both channels. All active phases are set for 600 divided clocks. There is a 40 divided clock guaranteed off-time between each active phase. Since this is based on a crystal oscillator, it is a very stable non-overlapping period. The total period is also a very stable crystal-oscillator-based time interval. In this example, the active phases are pulled to Vss (ground), while the inactive phases are allowed to float to a high-Z state. 600 ACTIVE_FF0 680 40 40 600 ACTIVE_FF1 640 PWM0 Output hi-Z Vss PWM1 Output digitally guaranteed HW_PWM_PERIOD0_PERIOD = 1280 HW_PWM_PERIOD1= 1280 HW_PWM_ACTIVE0_ACTIVE = 0 HW_PWM_ACTIVE1 = 640 HW_PWM_ACTIVE0_INACTIVE = 600 HW_PWM_INACTIVE1 = 1240 HW_PWM_PERIOD0_ACTIVE_STATE = 10 HW_PWM_ACTIVE1_STATE = 10 HW_PWM0BR_INACTIVE_STATE = 00 HW_PWM_INACTIVE1_STATE = 00 Figure 28-3. PWM Differential Output Pair Example i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1923 Operation Figure 28-5 shows the generation of the PWM Channel 3 output. This channel controls the output pin when PWM control is selected in PINCTRL block and HW_PWM_CTRL_PWM3_ENABLE is set to 1. The output pin can be set to a 0, a 1, or left to float in the high-impedance state. These choices can be made independently for either the active or inactive phase of the output. 28.2.2 HSADC Driving Mode The HSADC driving mode ouputs signals in HSADC (high-speed ADC) sample clock domain, other than traditional 24 MHz XTAL OSC domain. Although the main target of HSADC block is to drive TOSHIBA TCD1304DG linear image scanner sensor, there is potential requirement for HSADC to drive other linear image scanner sensors as well. To improve flexibility, PWM is used to generate these driving signals; and to co-work with block HSADC, HSADC's sample clock is used for PWM output signals. Typically, as which is showed in Figure 28-4, three output driving signals are needed for HSADC. And one extra trigger, which is also synchronous with high-speed ADC block, might be needed to start the conversion of ADC according to HSADC's specified trigger mode. As a result, one clock mux is added for every PWM instance each to output signals synchronous with HSADC sample clock, and there is a hard-wired connection between every PWM instance and high-speed ADC block for HSADC's PWM trigger mode. For every PWM instance, software can choose whether HSADC sample clock or 24 MHz XTAL OSC clock is used for PWM output by writing 1'b1 to bit HSADC_CLK_SEL of Register PWM Channelx Period Register(x = 0-7). Meanwhile, it's programmable whether this output signal is routed to HSADC internally by writing 1'b1 to bit HSADC_OUT of Register PWM Channelx Period Register(x = 0-7). When on HSADC driving mode, it is advisable to wait enough time for another write access to the same PWM register, such as HW_PWM_CTR, HW_PWM_ACTIVEx(x = 0-7) and HW_PWM_PERIODx(x = 0-7). Because handshake is applied, if several write access to the same register is consecutive to each other, it is not guaranteed what's the content of programmed register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1924 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller Clock for ADC divider 288MHz Clock Block AHB clock 200MHz Sam pling clock 32MHz 32MHz PW M Trigger signal HSADC Ctrl signals Sample data Sensor control signals ADC Analog pixel data Linear image sensor Figure 28-4. PWM HSADC Usecase 28.2.3 Multi-Chip Attachment Mode The multi-chip attachment mode (MATT) allows a 24 MHz or 32 KHz crystal clock that is an input to the i.MX28 to be routed to the PWM output pins. In this case, the normal PWM programming parameters (for example, PERIOD, ACTIVE, and so on) are ignored. This mode allows for supplying and controlling the crystal clock for external application interfaces, as shown in Figure 28-5. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1925 Operation 24 MHz or 32 KHz Crystal Clock Divide by 1 PWM ACTIVE_STATE [BIT 0] PWM INACTIVE_STATE [BIT 0] 1 0 1 PWM INACTIVE_STATE [BIT 1] 0 PWM OUTPUT 0 MATT mode bit ACTIVE FF PWM ACTIVE_STATE [BIT 1] 1 PWM ENABLE BIT CLOCK GATE Figure 28-5. PWM Output Driver 28.2.4 Channel 2 Analog Enable Function The output generation for channel 2 is slightly different than shown in Figure 28-5. In this channel, there is an additional enable that is controlled from the analog LRADC block. This signal is synchronized in the XTAL domain and ANDed with the PWM ENABLE bit. So, in this case, either enable source can disable the output. Also, this analog enable control signal can be disabled through the PWM2_ANA_CTRL_ENABLE bit in the HW_PWM_CTRL register. When disabled, Channel 2 behaves identically to the other channels. 28.2.5 Channel Output Cutoff Using Module Clock Gate Whenever the clkgate is enabled (gated) the output from all PWM channels is hi-Z. If the clock gate is asserted while PWM is enabled and generating an output signal the output is immediately disabled. This will not affect the current state, programming or enables of the pwm channels themselves. When the clkgate is de-asserted, the PWM outputs will i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1926 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller resume according to their programmed parameters and current states. Therefore glitches on the enabled channel outputs will likely occur when the clkgate state is changed. All 8 channels will function identically in this regard. 28.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. 28.4 Programmable Registers PWM Hardware Register Format Summary HW_PWM memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8006_4000 PWM Control and Status Register (HW_PWM_CTRL) 32 R/W FFC0_0000h 28.4.1/1928 8006_4010 PWM Channel 0 Active Register (HW_PWM_ACTIVE0) 32 R/W 0000_0000h 28.4.2/1931 8006_4020 PWM Channel 0 Period Register (HW_PWM_PERIOD0) 32 R/W 0000_0000h 28.4.3/1931 8006_4030 PWM Channel 1 Active Register (HW_PWM_ACTIVE1) 32 R/W 0000_0000h 28.4.4/1933 8006_4040 PWM Channel 1 Period Register (HW_PWM_PERIOD1) 32 R/W 0000_0000h 28.4.5/1934 8006_4050 PWM Channel 2 Active Register (HW_PWM_ACTIVE2) 32 R/W 0000_0000h 28.4.6/1936 8006_4060 PWM Channel 2 Period Register (HW_PWM_PERIOD2) 32 R/W 0000_0000h 28.4.7/1937 8006_4070 PWM Channel 3 Active Register (HW_PWM_ACTIVE3) 32 R/W 0000_0000h 28.4.8/1939 8006_4080 PWM Channel 3 Period Register (HW_PWM_PERIOD3) 32 R/W 0000_0000h 28.4.9/1939 8006_4090 PWM Channel 4 Active Register (HW_PWM_ACTIVE4) 32 R/W 0000_0000h 28.4.10/ 1941 8006_40A0 PWM Channel 4 Period Register (HW_PWM_PERIOD4) 32 R/W 0000_0000h 28.4.11/ 1942 8006_40B0 PWM Channel 5 Active Register (HW_PWM_ACTIVE5) 32 R/W 0000_0000h 28.4.12/ 1944 8006_40C0 PWM Channel 5 Period Register (HW_PWM_PERIOD5) 32 R/W 0000_0000h 28.4.13/ 1945 8006_40D0 PWM Channel 6 Active Register (HW_PWM_ACTIVE6) 32 R/W 0000_0000h 28.4.14/ 1947 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1927 Programmable Registers HW_PWM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8006_40E0 PWM Channel 6 Period Register (HW_PWM_PERIOD6) 32 R/W 0000_0000h 28.4.15/ 1947 8006_40F0 PWM Channel 7 Active Register (HW_PWM_ACTIVE7) 32 R/W 0000_0000h 28.4.16/ 1949 8006_4100 PWM Channel 7 Period Register (HW_PWM_PERIOD7) 32 R/W 0000_0000h 28.4.17/ 1950 8006_4110 PWM Version Register (HW_PWM_VERSION) 32 R 0106_0000h 28.4.18/ 1952 28.4.1 PWM Control and Status Register (HW_PWM_CTRL) The PWM Control and Status Register specifies the reset state, availability, and the enables for the eight PWM units. HW_PWM_CTRL: 0x000 HW_PWM_CTRL_SET: 0x004 HW_PWM_CTRL_CLR: 0x008 HW_PWM_CTRL_TOG: 0x00C EXAMPLE HW_PWM_CTRL_WR(0x000000ff); // Enable all channels i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1928 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller Address: 8006_4000h base + 0h offset = 8006_4000h 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM1_ENABLE PWM0_ENABLE 16 PWM2_ENABLE 17 PWM3_ENABLE 18 PWM4_ENABLE 19 PWM5_ENABLE 20 PWM0_PRESENT 21 PWM6_ENABLE 22 PWM1_PRESENT 23 PWM7_ENABLE 24 PWM2_PRESENT 25 PWM3_PRESENT 26 PWM4_PRESENT 27 PWM5_PRESENT 28 PWM6_PRESENT 29 PWM7_PRESENT 30 CLKGATE 31 SFTRST Bit 0 0 0 0 0 0 0 0 0 0 R RSRVD1 Bit RSRVD1 R RSRVD2 Reset OUTPUT_CUTOFF_EN W W Reset 0 0 0 0 0 0 HW_PWM_CTRL field descriptions Field 31 SFTRST Description This bit must be cleared to 0 for normal operation. When set to 1, it forces a block-wide reset. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1929 Programmable Registers HW_PWM_CTRL field descriptions (continued) Field Description 30 CLKGATE This bit must be cleared to 0 for normal operation. When set to 1, it gates off the clocks to the block. 29 PWM7_ PRESENT 0 = PWM7 is not present in this product. 28 PWM6_ PRESENT 0 = PWM6 is not present in this product. 27 PWM5_ PRESENT 0 = PWM5 is not present in this product. 26 PWM4_ PRESENT 0 = PWM4 is not present in this product. 25 PWM3_ PRESENT 0 = PWM3 is not present in this product. 24 PWM2_ PRESENT 0 = PWM2 is not present in this product. 23 PWM1_ PRESENT 0 = PWM1 is not present in this product. 22 PWM0_ PRESENT 0 = PWM0 is not present in this product. 21-10 RSRVD1 9 OUTPUT_ CUTOFF_EN 8 RSRVD2 Reserved. When asserted this bit enables the block to automatically Hi-Z state the outputs whenever the clkgate is asserted. The default is disabled. Reserved. 7 Enables PWM channel 7 to begin cycling when set to 1. To enable PWM7 onto the output pin, the pin PWM7_ENABLE control registers must programmed accordingly. 6 Enables PWM channel 6 to begin cycling when set to 1. To enable PWM6 onto the output pin, the pin PWM6_ENABLE control registers must programmed accordingly. 5 Enables PWM channel 5 to begin cycling when set to 1. To enable PWM5 onto the output pin, the pin PWM5_ENABLE control registers must programmed accordingly. 4 Enables PWM channel 4 to begin cycling when set to 1. To enable PWM4 onto the output pin, the pin PWM4_ENABLE control registers must programmed accordingly. 3 Enables PWM channel 3 to begin cycling when set to 1. To enable PWM3 onto the output pin, the pin PWM3_ENABLE control registers must programmed accordingly. 2 Enables PWM channel 2 to begin cycling when set to 1. To enable PWM2 onto the output pin, the pin PWM2_ENABLE control registers must programmed accordingly. 1 Enables PWM channel 1 to begin cycling when set to 1. To enable PWM1 onto the output pin, the pin PWM1_ENABLE control registers must programmed accordingly. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1930 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller HW_PWM_CTRL field descriptions (continued) Field Description 0 Enables PWM channel 0 to begin cycling when set to 1. To enable PWM0 onto the output pin, the pin PWM0_ENABLE control registers must programmed accordingly. 28.4.2 PWM Channel 0 Active Register (HW_PWM_ACTIVE0) The PWM Channel 0 Active Register specifies the active time and inactive time for Channel 0. HW_PWM_ACTIVE0: 0x010 HW_PWM_ACTIVE0_SET: 0x014 HW_PWM_ACTIVE0_CLR: 0x018 HW_PWM_ACTIVE0_TOG: 0x01C EXAMPLE HW_PWM_ACTIVEn_WR(0, 0x000000ff); // Set active and inactive counts Address: 8006_4000h base + 10h offset = 8006_4010h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INACTIVE 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ACTIVE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PWM_ACTIVE0 field descriptions Field Description 31-16 INACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. ACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 28.4.3 PWM Channel 0 Period Register (HW_PWM_PERIOD0) The PWM Channel 0 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD0: 0x020 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1931 Programmable Registers HW_PWM_PERIOD0_SET: 0x024 HW_PWM_PERIOD0_CLR: 0x028 HW_PWM_PERIOD0_TOG: 0x02C EXAMPLE HW_PWM_PERIODn_WR(0, 0x00000b1f); // Set up period and active/inactive output states Address: 8006_4000h base + 20h offset = 8006_4020h Bit 31 30 29 28 27 26 25 24 23 RSRVD2 17 16 MATT 18 MATT_SEL 19 HSADC_CLK_SEL Bit 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset 21 HSADC_OUT R 22 INACTIVE_ STATE CDIV ACTIVE_ STATE R PERIOD W Reset 0 0 0 0 0 0 0 0 0 HW_PWM_PERIOD0 field descriptions Field 31-27 RSRVD2 26 HSADC_OUT Description Reserved. PWM output to HSADC. Setting this bit to 1'b1, output of PWM channel 0 is routed to HSADC internally.Only one PWM channle's HSADC_OUT should be set to 1'b1. If multiple PWM channels are set as HSADC_OUT, only the channel with the lowest channel number will be routed to HSADC Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1932 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller HW_PWM_PERIOD0 field descriptions (continued) Field Description 25 HSADC_CLK_ SEL HSADC clock select for PWM output. Setting this bit to 1'b1, PWM channel 0 counts on HSADC input clock to drive PWM output. 24 MATT_SEL Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. 23 MATT Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM0 output pin for inter-chip signaling. When this bit is set to 0x1, bit HSADC_CLK_SET in Period Register must be set to 0x0. Otherwise, something unexpected may happen. 22-20 CDIV 19-18 INACTIVE_ STATE Clock divider ratio to apply to the crystal/HSADC clock frequency that times the PWM output signal. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 DIV_1 -- Divide by 1. DIV_2 -- Divide by 2. DIV_4 -- Divide by 4. DIV_8 -- Divide by 8. DIV_16 -- Divide by 16. DIV_64 -- Divide by 64. DIV_256 -- Divide by 256. DIV_1024 -- Divide by 1024. The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to hi-Z. 0x0 0x2 0x3 HI_Z -- Inactive state sets PWM output to high-impedance. 0 -- Inactive state sets PWM output to 0 (low). 1 -- Inactive state sets PWM output to 1 (high). 17-16 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is ACTIVE_STATE mapped to high-impedance. 0x0 0x2 0x3 PERIOD HI_Z -- Active state sets PWM output to high-impedance. 0 -- Active state sets PWM output to 0 (low). 1 -- Active state sets PWM output to 1 (high). Number of divided clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. 28.4.4 PWM Channel 1 Active Register (HW_PWM_ACTIVE1) The PWM Channel 1 Active Register specifies the active time and inactive time for Channel 1. HW_PWM_ACTIVE1: 0x030 HW_PWM_ACTIVE1_SET: 0x034 HW_PWM_ACTIVE1_CLR: 0x038 HW_PWM_ACTIVE1_TOG: 0x03C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1933 Programmable Registers EXAMPLE HW_PWM_ACTIVEn_WR(1, 0x000000ff); // Set active and inactive counts Address: 8006_4000h base + 30h offset = 8006_4030h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INACTIVE 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ACTIVE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PWM_ACTIVE1 field descriptions Field Description 31-16 INACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. ACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 28.4.5 PWM Channel 1 Period Register (HW_PWM_PERIOD1) The PWM Channel 1 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD1: 0x040 HW_PWM_PERIOD1_SET: 0x044 HW_PWM_PERIOD1_CLR: 0x048 HW_PWM_PERIOD1_TOG: 0x04C EXAMPLE HW_PWM_PERIODn_WR(1, 0x00000b1f); // Set up period and active/inactive output states i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1934 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller Address: 8006_4000h base + 40h offset = 8006_4040h Bit 31 30 29 28 27 26 25 24 23 RSRVD2 17 16 MATT 18 MATT_SEL 19 HSADC_CLK_SEL Bit 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset 21 HSADC_OUT R 22 INACTIVE_ STATE CDIV ACTIVE_ STATE R PERIOD W Reset 0 0 0 0 0 0 0 0 0 HW_PWM_PERIOD1 field descriptions Field 31-27 RSRVD2 26 HSADC_OUT Description Reserved. PWM output to HSADC.Setting this bit to 1'b1, output of PWM channel 1 is routed to HSADC internally.Only one PWM channle's HSADC_OUT should be set to 1'b1. If multiple PWM channels are set as HSADC_OUT, only the channel with the lowest channel number will be routed to HSADC 25 HSADC_CLK_ SEL HSADC clock select for PWM output. Setting this bit to 1'b1, PWM channel 1 counts on HSADC input clock to drive PWM output. 24 MATT_SEL Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. 23 MATT Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM1 output pin for inter-chip signaling. When this bit is set to 0x1, bit HSADC_CLK_SET in Period Register must be set to 0x0. Otherwise, something unexpected may happen. 22-20 CDIV Clock divider ratio to apply to the crystal/HSADC clock frequency that times the PWM output signal. 0x0 DIV_1 -- Divide by 1. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1935 Programmable Registers HW_PWM_PERIOD1 field descriptions (continued) Field Description DIV_2 -- Divide by 2. DIV_4 -- Divide by 4. DIV_8 -- Divide by 8. DIV_16 -- Divide by 16. DIV_64 -- Divide by 64. DIV_256 -- Divide by 256. DIV_1024 -- Divide by 1024. 0x1 0x2 0x3 0x4 0x5 0x6 0x7 19-18 INACTIVE_ STATE The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z -- Inactive state sets PWM output to high-impedance. 0 -- Inactive state sets PWM output to 0 (low). 1 -- Inactive state sets PWM output to 1 (high). 0x0 0x2 0x3 17-16 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is ACTIVE_STATE mapped to high-impedance. HI_Z -- Active state sets PWM output to high-impedance. 0 -- Active state sets PWM output to 0 (low). 1 -- Active state sets PWM output to 1 (high). 0x0 0x2 0x3 PERIOD Number of divided clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. 28.4.6 PWM Channel 2 Active Register (HW_PWM_ACTIVE2) The PWM Channel 2 Active Register specifies the active time and inactive time for Channel 2. HW_PWM_ACTIVE2: 0x050 HW_PWM_ACTIVE2_SET: 0x054 HW_PWM_ACTIVE2_CLR: 0x058 HW_PWM_ACTIVE2_TOG: 0x05C EXAMPLE HW_PWM_ACTIVEn_WR(2, 0x000000ff); // Set active and inactive counts Address: 8006_4000h base + 50h offset = 8006_4050h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INACTIVE 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ACTIVE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1936 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller HW_PWM_ACTIVE2 field descriptions Field Description 31-16 INACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. ACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 28.4.7 PWM Channel 2 Period Register (HW_PWM_PERIOD2) The PWM Channel 2 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD2: 0x060 HW_PWM_PERIOD2_SET: 0x064 HW_PWM_PERIOD2_CLR: 0x068 HW_PWM_PERIOD2_TOG: 0x06C EXAMPLE HW_PWM_PERIODn_WR(2, 0x00000b1f); // Set up period and active/inactive output states 29 28 27 26 25 24 23 MATT 30 MATT_SEL 31 HSADC_CLK_SEL Bit HSADC_OUT Address: 8006_4000h base + 60h offset = 8006_4060h 0 0 0 0 RSRVD2 R W Reset 0 0 0 0 0 22 21 20 0 18 INACTIVE_ STATE CDIV 0 19 0 0 0 17 16 ACTIVE_ STATE 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1937 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R PERIOD W Reset 0 0 0 0 0 0 0 0 0 HW_PWM_PERIOD2 field descriptions Field 31-27 RSRVD2 26 HSADC_OUT Description Reserved. PWM output to HSADC.Setting this bit to 1'b1, output of PWM channel 2 is routed to HSADC internally.Only one PWM channle's HSADC_OUT should be set to 1'b1. If multiple PWM channels are set as HSADC_OUT, only the channel with the lowest channel number will be routed to HSADC 25 HSADC_CLK_ SEL HSADC clock select for PWM output. Setting this bit to 1'b1, PWM channel 2 counts on HSADC input clock to drive PWM output. 24 MATT_SEL Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. 23 MATT Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM2 output pin for inter-chip signaling. When this bit is set to 0x1, bit HSADC_CLK_SET in Period Register must be set to 0x0. Otherwise, something unexpected may happen. 22-20 CDIV 19-18 INACTIVE_ STATE Clock divider ratio to apply to the crystal/HSADC clock frequency that times the PWM output signal. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 DIV_1 -- Divide by 1. DIV_2 -- Divide by 2. DIV_4 -- Divide by 4. DIV_8 -- Divide by 8. DIV_16 -- Divide by 16. DIV_64 -- Divide by 64. DIV_256 -- Divide by 256. DIV_1024 -- Divide by 1024. The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. 0x0 0x2 0x3 HI_Z -- Inactive state sets PWM output to high-impedance. 0 -- Inactive state sets PWM output to 0 (low). 1 -- Inactive state sets PWM output to 1 (high). 17-16 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is ACTIVE_STATE mapped to high-impedance. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1938 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller HW_PWM_PERIOD2 field descriptions (continued) Field Description HI_Z -- Active state sets PWM output to high-impedance. 0 -- Active state sets PWM output to 0 (low). 1 -- Active state sets PWM output to 1 (high). 0x0 0x2 0x3 PERIOD Number of divided clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. 28.4.8 PWM Channel 3 Active Register (HW_PWM_ACTIVE3) The PWM Channel 3 Active Register specifies the active time and inactive time for Channel 3. HW_PWM_ACTIVE3: 0x070 HW_PWM_ACTIVE3_SET: 0x074 HW_PWM_ACTIVE3_CLR: 0x078 HW_PWM_ACTIVE3_TOG: 0x07C EXAMPLE HW_PWM_ACTIVEn_WR(3, 0x000000ff); // Set active and inactive counts Address: 8006_4000h base + 70h offset = 8006_4070h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INACTIVE 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ACTIVE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PWM_ACTIVE3 field descriptions Field Description 31-16 INACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. ACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 28.4.9 PWM Channel 3 Period Register (HW_PWM_PERIOD3) The PWM Channel 3 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1939 Programmable Registers HW_PWM_PERIOD3: 0x080 HW_PWM_PERIOD3_SET: 0x084 HW_PWM_PERIOD3_CLR: 0x088 HW_PWM_PERIOD3_TOG: 0x08C EXAMPLE HW_PWM_PERIODn_WR(3, 0x00000b1f); // Set up period and active/inactive output states Address: 8006_4000h base + 80h offset = 8006_4080h Bit 31 30 29 28 27 26 25 24 23 RSRVD2 17 16 MATT 18 MATT_SEL 19 HSADC_CLK_SEL Bit 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset 21 HSADC_OUT R 22 INACTIVE_ STATE CDIV ACTIVE_ STATE R PERIOD W Reset 0 0 0 0 0 0 0 0 0 HW_PWM_PERIOD3 field descriptions Field 31-27 RSRVD2 26 HSADC_OUT Description Reserved. PWM output to HSADC. Setting this bit to 1'b1, output of PWM channel 3 is routed to HSADC internally.Only one PWM channle's HSADC_OUT should be set to 1'b1. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1940 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller HW_PWM_PERIOD3 field descriptions (continued) Field Description If multiple PWM channels are set as HSADC_OUT, only the channel with the lowest channel number will be routed to HSADC 25 HSADC_CLK_ SEL HSADC clock select for PWM output. Setting this bit to 1'b1, PWM channel 3 counts on HSADC input clock to drive PWM output. 24 MATT_SEL Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. 23 MATT Multichip Attachment mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM3 output pin for inter-chip signaling. When this bit is set to 0x1, bit HSADC_CLK_SET in Period Register must be set to 0x0. Otherwise, something unexpected may happen. 22-20 CDIV 19-18 INACTIVE_ STATE Clock divider ratio to apply to the crystal clock frequency (24.0 MHz) that times the PWM output signal. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 DIV_1 -- Divide by 1. DIV_2 -- Divide by 2. DIV_4 -- Divide by 4. DIV_8 -- Divide by 8. DIV_16 -- Divide by 16. DIV_64 -- Divide by 64. DIV_256 -- Divide by 256. DIV_1024 -- Divide by 1024. The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. 0x0 0x2 0x3 HI_Z -- Inactive state sets PWM output to high-impedance. 0 -- Inactive state sets PWM output to 0 (low). 1 -- Inactive state sets PWM output to 1 (high). 17-16 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is ACTIVE_STATE mapped to high-impedance. 0x0 0x2 0x3 PERIOD HI_Z -- Active state sets PWM output to high-impedance. 0 -- Active state sets PWM output to 0 (low). 1 -- Active state sets PWM output to 1 (high). Number of divided clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. 28.4.10 PWM Channel 4 Active Register (HW_PWM_ACTIVE4) The PWM Channel 4 Active Register specifies the active time and inactive time for Channel 4. HW_PWM_ACTIVE4: 0x090 HW_PWM_ACTIVE4_SET: 0x094 HW_PWM_ACTIVE4_CLR: 0x098 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1941 Programmable Registers HW_PWM_ACTIVE4_TOG: 0x09C EXAMPLE HW_PWM_ACTIVEn_WR(4, 0x000000ff); // Set active and inactive counts Address: 8006_4000h base + 90h offset = 8006_4090h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INACTIVE 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ACTIVE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PWM_ACTIVE4 field descriptions Field Description 31-16 INACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. ACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 28.4.11 PWM Channel 4 Period Register (HW_PWM_PERIOD4) The PWM Channel 4 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD4: 0x0A0 HW_PWM_PERIOD4_SET: 0x0A4 HW_PWM_PERIOD4_CLR: 0x0A8 HW_PWM_PERIOD4_TOG: 0x0AC EXAMPLE HW_PWM_PERIODn_WR(4, 0x00000b1f); // Set up period and active/inactive output states i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1942 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller Address: 8006_4000h base + A0h offset = 8006_40A0h Bit 31 30 29 28 27 26 25 24 23 RSRVD2 17 16 MATT 18 MATT_SEL 19 HSADC_CLK_SEL Bit 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset 21 HSADC_OUT R 22 INACTIVE_ STATE CDIV ACTIVE_ STATE R PERIOD W Reset 0 0 0 0 0 0 0 0 0 HW_PWM_PERIOD4 field descriptions Field 31-27 RSRVD2 26 HSADC_OUT Description Reserved. PWM output to HSADC. Setting this bit to 1'b1, output of PWM channel 4 is routed to HSADC internally.Only one PWM channle's HSADC_OUT should be set to 1'b1. If multiple PWM channels are set as HSADC_OUT, only the channel with the lowest channel number will be routed to HSADC 25 HSADC_CLK_ SEL HSADC clock select for PWM output. Setting this bit to 1'b1, PWM channel 4 counts on HSADC input clock to drive PWM output. 24 MATT_SEL Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. 23 MATT Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM4 output pin for inter-chip signaling. When this bit is set to 0x1, bit HSADC_CLK_SET in Period Register must be set to 0x0. Otherwise, something unexpected may happen. 22-20 CDIV Clock divider ratio to apply to the crystal/HSADC clock frequency that times the PWM output signal. 0x0 DIV_1 -- Divide by 1. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1943 Programmable Registers HW_PWM_PERIOD4 field descriptions (continued) Field Description DIV_2 -- Divide by 2. DIV_4 -- Divide by 4. DIV_8 -- Divide by 8. DIV_16 -- Divide by 16. DIV_64 -- Divide by 64. DIV_256 -- Divide by 256. DIV_1024 -- Divide by 1024. 0x1 0x2 0x3 0x4 0x5 0x6 0x7 19-18 INACTIVE_ STATE The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z -- Inactive state sets PWM output to high-impedance. 0 -- Inactive state sets PWM output to 0 (low). 1 -- Inactive state sets PWM output to 1 (high). 0x0 0x2 0x3 17-16 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is ACTIVE_STATE mapped to high-impedance. HI_Z -- Active state sets PWM output to high-impedance. 0 -- Active state sets PWM output to 0 (low). 1 -- Active state sets PWM output to 1 (high). 0x0 0x2 0x3 PERIOD Number of divided clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. 28.4.12 PWM Channel 5 Active Register (HW_PWM_ACTIVE5) The PWM Channel 5 Active Register specifies the active time and inactive time for Channel 5. HW_PWM_ACTIVE5: 0x0b0 HW_PWM_ACTIVE5_SET: 0x0b4 HW_PWM_ACTIVE5_CLR: 0x0b8 HW_PWM_ACTIVE5_TOG: 0x0bC EXAMPLE HW_PWM_ACTIVEn_WR(5, 0x000000ff); // Set active and inactive counts Address: 8006_4000h base + B0h offset = 8006_40B0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INACTIVE 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ACTIVE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1944 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller HW_PWM_ACTIVE5 field descriptions Field Description 31-16 INACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. ACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 28.4.13 PWM Channel 5 Period Register (HW_PWM_PERIOD5) The PWM Channel 5 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD5: 0x0c0 HW_PWM_PERIOD5_SET: 0x0c4 HW_PWM_PERIOD5_CLR: 0x0c8 HW_PWM_PERIOD5_TOG: 0x0cC EXAMPLE HW_PWM_PERIODn_WR(5, 0x00000b1f); // Set up period and active/inactive output states 29 28 27 26 25 24 23 MATT 30 MATT_SEL 31 HSADC_CLK_SEL Bit HSADC_OUT Address: 8006_4000h base + C0h offset = 8006_40C0h 0 0 0 0 RSRVD2 R W Reset 0 0 0 0 0 22 21 20 0 18 INACTIVE_ STATE CDIV 0 19 0 0 0 17 16 ACTIVE_ STATE 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1945 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R PERIOD W Reset 0 0 0 0 0 0 0 0 0 HW_PWM_PERIOD5 field descriptions Field 31-27 RSRVD2 26 HSADC_OUT Description Reserved. PWM output to HSADC.Setting this bit to 1'b1, output of PWM channel 5 is routed to HSADC internally.Only one PWM channle's HSADC_OUT should be set to 1'b1. If multiple PWM channels are set as HSADC_OUT, only the channel with the lowest channel number will be routed to HSADC 25 HSADC_CLK_ SEL HSADC clock select for PWM output. Setting this bit to 1'b1, PWM channel 5 counts on HSADC input clock to drive PWM output. 24 MATT_SEL Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. 23 MATT Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM5 output pin for inter-chip signaling. When this bit is set to 0x1, bit HSADC_CLK_SET in Period Register must be set to 0x0. Otherwise, something unexpected may happen. 22-20 CDIV 19-18 INACTIVE_ STATE Clock divider ratio to apply to the crystal/HSADC clock frequency that times the PWM output signal. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 DIV_1 -- Divide by 1. DIV_2 -- Divide by 2. DIV_4 -- Divide by 4. DIV_8 -- Divide by 8. DIV_16 -- Divide by 16. DIV_64 -- Divide by 64. DIV_256 -- Divide by 256. DIV_1024 -- Divide by 1024. The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. 0x0 0x2 0x3 HI_Z -- Inactive state sets PWM output to high-impedance. 0 -- Inactive state sets PWM output to 0 (low). 1 -- Inactive state sets PWM output to 1 (high). 17-16 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is ACTIVE_STATE mapped to high-impedance. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1946 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller HW_PWM_PERIOD5 field descriptions (continued) Field Description HI_Z -- Active state sets PWM output to high-impedance. 0 -- Active state sets PWM output to 0 (low). 1 -- Active state sets PWM output to 1 (high). 0x0 0x2 0x3 PERIOD Number of divided clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. 28.4.14 PWM Channel 6 Active Register (HW_PWM_ACTIVE6) The PWM Channel 6 Active Register specifies the active time and inactive time for Channel 6. HW_PWM_ACTIVE6: 0x0d0 HW_PWM_ACTIVE6_SET: 0x0d4 HW_PWM_ACTIVE6_CLR: 0x0d8 HW_PWM_ACTIVE6_TOG: 0x0dC EXAMPLE HW_PWM_ACTIVEn_WR(6, 0x000000ff); // Set active and inactive counts Address: 8006_4000h base + D0h offset = 8006_40D0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INACTIVE 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ACTIVE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PWM_ACTIVE6 field descriptions Field Description 31-16 INACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. ACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 28.4.15 PWM Channel 6 Period Register (HW_PWM_PERIOD6) The PWM Channel 6 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1947 Programmable Registers HW_PWM_PERIOD6: 0x0e0 HW_PWM_PERIOD6_SET: 0x0e4 HW_PWM_PERIOD6_CLR: 0x0e8 HW_PWM_PERIOD6_TOG: 0x0eC EXAMPLE HW_PWM_PERIODn_WR(6, 0x00000b1f); // Set up period and active/inactive output states Address: 8006_4000h base + E0h offset = 8006_40E0h Bit 31 30 29 28 27 26 25 24 23 RSRVD2 17 16 MATT 18 MATT_SEL 19 HSADC_CLK_SEL Bit 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset 21 HSADC_OUT R 22 INACTIVE_ STATE CDIV ACTIVE_ STATE R PERIOD W Reset 0 0 0 0 0 0 0 0 0 HW_PWM_PERIOD6 field descriptions Field 31-27 RSRVD2 26 HSADC_OUT Description Reserved. PWM output to HSADC. Setting this bit to 1'b1, output of PWM channel 6 is routed to HSADC internally.Only one PWM channle's HSADC_OUT should be set to 1'b1. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1948 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller HW_PWM_PERIOD6 field descriptions (continued) Field Description If multiple PWM channels are set as HSADC_OUT, only the channel with the lowest channel number will be routed to HSADC 25 HSADC_CLK_ SEL HSADC clock select for PWM output. Setting this bit to 1'b1, PWM channel 6 counts on HSADC input clock to drive PWM output. 24 MATT_SEL Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. 23 MATT Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM6 output pin for inter-chip signaling. When this bit is set to 0x1, bit HSADC_CLK_SET in Period Register must be set to 0x0. Otherwise, something unexpected may happen. 22-20 CDIV 19-18 INACTIVE_ STATE Clock divider ratio to apply to the crystal/HSADC clock frequency that times the PWM output signal. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 DIV_1 -- Divide by 1. DIV_2 -- Divide by 2. DIV_4 -- Divide by 4. DIV_8 -- Divide by 8. DIV_16 -- Divide by 16. DIV_64 -- Divide by 64. DIV_256 -- Divide by 256. DIV_1024 -- Divide by 1024. The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. 0x0 0x2 0x3 HI_Z -- Inactive state sets PWM output to high-impedance. 0 -- Inactive state sets PWM output to 0 (low). 1 -- Inactive state sets PWM output to 1 (high). 17-16 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is ACTIVE_STATE mapped to high-impedance. 0x0 0x2 0x3 PERIOD HI_Z -- Active state sets PWM output to high-impedance. 0 -- Active state sets PWM output to 0 (low). 1 -- Active state sets PWM output to 1 (high). Number of divided clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. 28.4.16 PWM Channel 7 Active Register (HW_PWM_ACTIVE7) The PWM Channel 7 Active Register specifies the active time and inactive time for Channel 7. HW_PWM_ACTIVE7: 0x0f0 HW_PWM_ACTIVE7_SET: 0x0f4 HW_PWM_ACTIVE7_CLR: 0x0f8 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1949 Programmable Registers HW_PWM_ACTIVE7_TOG: 0x0fC EXAMPLE HW_PWM_ACTIVEn_WR(7, 0x000000ff); // Set active and inactive counts Address: 8006_4000h base + F0h offset = 8006_40F0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 INACTIVE 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ACTIVE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PWM_ACTIVE7 field descriptions Field Description 31-16 INACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state. The internal count of the channel is compared for greater than this value to change to the inactive state. ACTIVE Number of divided clock cycles to count from the beginning of the period before changing the output to the active state. The internal count of the channel is compared for greater than this value to change to the active state. 28.4.17 PWM Channel 7 Period Register (HW_PWM_PERIOD7) The PWM Channel 7 Period Register specifies the multi-chip attachment mode, clock divider value, active high, low values and period. HW_PWM_PERIOD7: 0x100 HW_PWM_PERIOD7_SET: 0x104 HW_PWM_PERIOD7_CLR: 0x108 HW_PWM_PERIOD7_TOG: 0x10C EXAMPLE HW_PWM_PERIODn_WR(7, 0x00000b1f); // Set up period and active/inactive output states i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1950 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller Address: 8006_4000h base + 100h offset = 8006_4100h Bit 31 30 29 28 27 26 25 24 23 RSRVD2 17 16 MATT 18 MATT_SEL 19 HSADC_CLK_SEL Bit 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Reset 21 HSADC_OUT R 22 INACTIVE_ STATE CDIV ACTIVE_ STATE R PERIOD W Reset 0 0 0 0 0 0 0 0 0 HW_PWM_PERIOD7 field descriptions Field 31-27 RSRVD2 26 HSADC_OUT Description Reserved. PWM output to HSADC. Setting this bit to 1'b1, output of PWM channel 7 is routed to HSADC internally.Only one PWM channle's HSADC_OUT should be set to 1'b1. If multiple PWM channels are set as HSADC_OUT, only the channel with the lowest channel number will be routed to HSADC 25 HSADC_CLK_ SEL HSADC clock select for PWM output. Setting this bit to 1'b1, PWM channel 7 counts on HSADC input clock to drive PWM output. 24 MATT_SEL Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output. 0: 32 kHz, 1: 24 MHz. 23 MATT Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either the 24 MHz or 32 kHz crystal clock on the PWM7 output pin for inter-chip signaling. When this bit is set to 0x1, bit HSADC_CLK_SET in Period Register must be set to 0x0. Otherwise, something unexpected may happen. 22-20 CDIV Clock divider ratio to apply to the crystal/HSADC clock frequency that times the PWM output signal. 0x0 DIV_1 -- Divide by 1. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1951 Programmable Registers HW_PWM_PERIOD7 field descriptions (continued) Field Description DIV_2 -- Divide by 2. DIV_4 -- Divide by 4. DIV_8 -- Divide by 8. DIV_16 -- Divide by 16. DIV_64 -- Divide by 64. DIV_256 -- Divide by 256. DIV_1024 -- Divide by 1024. 0x1 0x2 0x3 0x4 0x5 0x6 0x7 19-18 INACTIVE_ STATE The logical inactive state that is mapped to the PWM output signal. Note that the undefined state of 0x1 is mapped to high-impedance. HI_Z -- Inactive state sets PWM output to high-impedance. 0 -- Inactive state sets PWM output to 0 (low). 1 -- Inactive state sets PWM output to 1 (high). 0x0 0x2 0x3 17-16 The logical active state is mapped to the PWM output signal. Note that the undefined state of 0x1 is ACTIVE_STATE mapped to high-impedance. HI_Z -- Active state sets PWM output to high-impedance. 0 -- Active state sets PWM output to 0 (low). 1 -- Active state sets PWM output to 1 (high). 0x0 0x2 0x3 PERIOD Number of divided clock cycles in the entire period of the PWM waveform, minus 1. For example, to obtain 6 clock cycles in the actual period, set this field to 5. 28.4.18 PWM Version Register (HW_PWM_VERSION) This register indicates the version of the block for debug purposes. EXAMPLE if (HW_PWM_VERSION.B.MAJOR != 1) Error(); Address: 8006_4000h base + 110h offset = 8006_4110h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 HW_PWM_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1952 Freescale Semiconductor, Inc. Chapter 28 Pulse-Width Modulator (PWM) Controller HW_PWM_VERSION field descriptions (continued) Field Description i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1953 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1954 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.1 3-Port Ethernet Switch Features * Integrated Ethernet switch engine compatible with ENET-MAC core * Three port switch with a fourth DMA bypass port * Can be configured to operate as a 3-Port Switch (Switch Mode) or as two independent ports (Passthrough Mode) * Filters and forward traffic at wire-speed on all ports * Per-queue tail-drop congestion management * Implements hardware switching look-up mechanism providing a learning capacity of up to 2 K MAC addresses * Supports configurable VLAN switching when MAC address lookup should be omitted * Classification and Priority assignment based on Port Number, MAC Address, Ipv4 DiffServ Code Point Field, Ipv6 Class of Service and VLAN Priority (IEEE802.1q) * Efficient output Queue frame buffering with shared Frame buffer of 24 Kbyte * Each port implements four priority queues with configurable weighted round-robin selection * Support Ethernet Multicast, Broadcast with flooding control to avoid unnecessary duplication of frames * Programmable Multicast destination port mask to restrict frame duplication for individual multicast addresses i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1955 Block Diagram * Multicast and Broadcast resolution with VLAN domain filtering providing a strict separation of up to 32 VLANs * IP Snooping with programmable protocol and port number registers * Programmable Ingress and Egress VLAN tag addition, removal and manipulation supporting single and double-tagged VLAN frames * Event and status signals which can be used to monitor port activity, severe error conditions or any user specific event * Programmable firmware operation with Static or Dynamic (Learning, Aging) switching tables * Switch firmware source available to provide customer specific software development capability * Support for 1588 precise time stamping applications * Supports Aggregation and Redundant Backplane applications DMA1 RX DMA1 TX 1 MAC P0 RX 0 DMA0 TX Receive Frame Buffer Switch Receive MAC P1 RX Vlan manipul. Port2 Priority Class Vlan manipul. Port1 Priority Class Vlan manipul. Port 0 Priority Class Vlan manipul. Queuing Control Port Election Shared Frame Buffer DeQueuing Control Vlan manipul. Vlan manipul. MAC P1 TX 1 MAC P0 TX Receive Interfaces 2 2 Switch Transmit Transmit Interfaces 3 3 Bipass Port Bipass Port 29.2 Block Diagram 0 Buffer DMA0 RX Transmit Status Switch Control De-Quauing Control Switch Input Port Blocking DMA Control Lookup Table Broadcast/VLAN/ Mirroring Resolution Register Map APB Host Interface APB Interface Figure 29-1. Block Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1956 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) Note * The left side is termed "Transmit Interfaces" as the interfaces are driven by the DMA transmit interfaces in pass-through mode. If the switch is enabled, these interfaces connect to the switch internal receive interfaces. The right side is named "Receive Interfaces" as the interfaces represent (are driven from) the respective MAC receive interfaces in pass-through mode connected to the DMA RX. If the switch is enabled these are driven by the switch internal transmit interfaces. See 4 page 26 for a description of the operational modes. * All descriptions related to switch functions refer to the switch internal receive/transmit interfaces. * Receive Frame buffer (DMA0 TX interface). Can hold at least one complete frame transferred from DMA0 to the switch. This is a local 64-bit wide FIFO to absorb a burst from the DMA, provide the necessary transaction handshake to the DMA, and forward the frame then to the switch logic. * Decoupling buffer only (DMA0 RX interface) to absorb switch latency (for example, 16/32 words) resulting from a rdy deassertion from DMA0. * The APB Host Interface module implements an indirect addressing scheme to the internal registers to allow arbitrary length access cycles (such as address table read/ write and configuration register read/write). However, the DMA control registers are directly mapped and accessed through APB. 29.3 Switch Configuration 29.3.1 Overview The Switch Core is designed to be seamlessly connected to the MorethanIP ENET-MAC Core and DMA controllers. For control and configuration, the switch implements an APB Register interface and multiple maskable interrupts. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1957 Switch Configuration Ethernet Port 0 Ethernet Port 1 ENET-MAC 0 ENET-MAC 1 2 APB Interface APB Bus 1 Interrupts Interrupt Controller Switch 0 3. Bypass Port DMA0 DMA1 Figure 29-2. Switch Interface The switch port assignment is listed in Table 29-1 and should be strictly followed when programming and integrating the Switch Core. Table 29-1. Port Assignment Switch Port Assignment 0 DMA 0 1 ENET-MAC 0 2 ENET-MAC 1 3 (bypass port) DMA 1 The Switch, controlled with the configuration pin sx_ena, can be programmed to operate is two modes: * Passthrough mode: The switch logic is disabled and bypassed. * Switch mode: The switch logic is enabled i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1958 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.3.2 Passthrough Mode When configuration signal sx_ena is set to '0', the switch logic is bypassed and can be totally powered down and disabled with, for example, the Switch clocks clk and pclk stopped and the Switch reset signals reset_clk and reset_pclk set to '1'. The Switch APB interface and interrupt signals are disabled and should not be used. To control the Frame transfer from DMA0 and DMA1, the ENET-MAC 0 and the ENETMAC 1 APB interfaces and interrupt signals should be used. Ethernet Port 1 '0' Switch DMA Control ENET-MAC 1 Transmit Status DMA Control Transmit Status Transmit Receive FIFO Interfaces ENET-MAC 0 Transmit Receive FIFO Interfaces APB and Interrupts Ethernet Port 0 sx_ena Bypass Port DMA0 DMA1 Figure 29-3. Passthrough Mode Configuration Overview 29.3.3 Switch Mode When the Switch is programmed to operate in Switch Mode (sx_ena set to '1'), the Bypass Mode (Port 1) interface is disabled and should not be used. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1959 Switch Configuration Frame transfers to and from the Line are performed on Port 0 only (DMA 0). The Transmit status signals are generated from the Switch Port 0 Receive Buffer and the DMA control signals from the Switch Register Space. The ENET-MAC 0 and ENETMAC 1 Transmit status and DMA control signals are not used. The ENET-MAC 0 and ENET-MAC 1 APB interfaces and interrupts are enabled and can be used to monitor the line activity and gather the line statistic information. Ethernet Port 1 Ethernet Port 0 ENET-MAC 0 ENET-MAC 1 Switch Rx Buffer Register Map APB and Interrupts "1" DMA0 Figure 29-4. Switch Mode Configuration Overview 29.3.4 Port 0 Input Buffer A dedicated input buffer of at least 2 Kbyte storage is implemented at the port0 (DMA0) input interface, when the switch is operating in switch mode. In bypass mode, this buffer is bypassed. The input buffer is normally operated in store&forward mode of operation, absorbing a DMA burst and forwarding the frame to the switch (internally) when the complete frame has been stored in the input buffer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1960 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) However, to allow for jumbo-frame support, the input buffer can be operated in cutthrough mode (see register ENET SWI Defines several global configuration settings. (HW_ENET_SWI_MODE_CONFIG)). In cut-through mode, a frame is forwarded to the switch internal input, when the buffer has reached a fill level as 1536 bytes (192 words). If a frame of less than this threshold is written by DMA0, it is forwarded as in store&forward with all options (ff_tx_xxx). If a frame larger than this threshold is written, then the input buffer will start forwarding the frame to the switch, when the threshold is reached. It is then expected that DMA0 guarantees writing data fast enough to avoid a buffer underflow. When the input buffer is operating in cut-through mode, the additional transmit options (ff_tx_crc_fwd0, ff_tx_ipchk_ins0, ff_tx_protchk_ins0, ff_tx_ts_frm0) can be used only for frames not exceeding the cut-through threshold. Frames exceeding the threshold cannot use these functions and they must be set to 0 (and they will operate as defined for 0 accordingly). 29.3.5 Port 0 Input Backpressure/Congestion Indication When frames are transferred from DMA0 to the switch port0 transmit interface, the interface signal ff_tx_rdy0 indicates if data can be transferred (written) to the port 0 input. When ff_tx_rdy0 deasserts (0), it indicates a stop request to the DMA0. The DMA0 might continue to write a few more words (typically up to 4) and is then expected to stop writing and wait for assertion (1) of the signal again. The signal is controlled by the port 0 local input buffer and deasserts when the buffer reaches an almost full threshold. In addition, a special backpressure mechanism for Port0 is implemented to pause DMA0 transfers when the output queues' shared memory (see Overview) becomes full to a programmable threshold. Respecting the output queues' shared memory fill level can avoid that the switch due to memory congestion discards frames written by the DMA0. The threshold is configured through ENET SWI Define congestion threshold for Port0 backpressure. (HW_ENET_SWI_QMGR_MINCELLSP0) configuration register. The threshold is used as follows: If the shared memory has less than QMGR_MINCELLSP0 number of free cells available, the switch stops serving port 0. That is, the switch will not start to read a frame from the port0 input buffer. The port 0 input buffer will continue to accept data from DMA0 until it becomes full and as a result deasserts ff_tx_rdy0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1961 Switch Functional Description Note that the backpressure only considers the total amount of memory available, not a specific queue. Hence, it may still happen that an outgoing frame from DMA0 is discarded by the switch, if the output queue for the frame is congested while the total amount of memory would have free space available. The backpressure threshold (QMGR_MINCELLSP0) should be set higher than the memory full threshold (ENET SWI Low Memory threshold. (HW_ENET_SWI_QMGR_MINCELLS)) to stop the DMA0 before a memory full situation, leading to discard of frames, can occur. 29.4 Switch Functional Description 29.4.1 Overview The Switch implements the following main functions: * Input/Output VLAN Processing * IP Snooping * Input Frame Parsing and Priority Extraction * Input Port Selection * Output Port(s) Resolution * Frame Queuing * Output Queue Scheduling The standard Firmware together with the switching Hardware and, optionally, MAC Cores from MorethanIP already provides a complete Ethernet switching solution. As the Switch Firmware is developed in a modular way, MorethanIP can implement, upon request, specific functions like for example, Spanning Tree) The Hardware and Software designs of the switch are also highly tightly optimized together to provide high performances and to be scalable to higher throughput switching solutions. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1962 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.4.2 VLAN Input Processing Function 29.4.2.1 Overview The VLAN input processing function is used on each switch input port to inspect and manipulate the VLAN tag of frames entering the switch. It performs the following functions: * Input Frame Parsing * VLAN tag insertion or manipulation Based on the information of the Input Processing function, the frame can be switched to the corresponding output port or will be discarded. 29.4.2.2 Terms and Definitions VLAN Information: The 16-bit field following the VLAN type field within a frame. VLAN-ID: The lower 12 bits of the VLAN information field. VLAN-Priority: The upper 3 bits of the VLAN information field. Used to prioritize incoming frames. A value of 0 represents lowest priority, a value of 7 represents highest priority. 29.4.2.3 Configuration Information The switch management provides the following information to configure and control the operation of the function: * SYSTEM_TAGINFOn: 16 bit value. The VLAN information field (VLAN-ID and priority) used for tag insertion operations. * Mode of operation: There are different modes of operation, which define how incoming frames must be processed for a port. The function can be enabled and configured individually per port: See registers ENET SWI Enable the input processing according to the VLAN_IN_MODE for a port (HW_ENET_SWI_VLAN_IN_MODE_ENA) and ENET SWI Define behavior of VLAN input manipulation function (HW_ENET_SWI_VLAN_IN_MODE). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1963 Modes of Operation Note If the vlan input processing function is not enabled (VLAN_IN_MODE_ENA bit of the port=0), the mode setting has no effect. 29.4.2.4 Modes of Operation 29.4.2.4.1 Frame Processing The VLAN input processing function modifies the frames before they enter the switching engine. This means, if a VLAN tag is inserted, the switch will only act on the inserted VLAN tag (for example, priority) and any original tag that was found in the frame before the modification, if any, has no effect within the switch. In addition, if VLAN verification is enabled for a port (see register ENET SWI Verify VLAN domain. (HW_ENET_SWI_VLAN_VERIFY)), the VLAN-id used for insertion (SYSTEM_TAGINFOn) must also be configured in the global VLAN resolution table (see register ENET SWI VLAN domain resolution entry 0. (HW_ENET_SWI_VLAN_RES_TABLE_0) to ENET SWI VLAN domain resolution entry 31. (HW_ENET_SWI_VLAN_RES_TABLE_31)), to ensure the switch accepts frames, which contain the inserted tag. When, in any of the modes, a tag is inserted, it is always inserted as first tag (outer) and its information field is set as programmed in the ENET SWI Port 0 VLAN-ID field for VLAN input manipulation function (HW_ENET_SWI_SYSTEM_TAGINFO0)..2 register for the port n where the frame is received. 29.4.2.4.2 Mode 1 -- Single Tagging with Passthrough Insert Tag only if untagged frame, leave frame unmodified if tagged. 29.4.2.4.3 Mode 2 -- Single Tagging with Replace If untagged, add the tag, if single tagged, overwrite the tag. 29.4.2.4.4 Mode 3 -- Double Tagging with Passthrough Insert a tag on untagged and tagged. This results in a single tagged frame when an untagged is received, and a double tagged frame, when a single tagged frame is received. When a double tagged frame is received the frame is left unmodified. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1964 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.4.2.4.5 Mode 4 -- Double Tagging with Replace Insert Tag on untagged and single tagged. If double tagged, overwrite outer tag. 29.4.3 IP Snooping Programmable snooping for up to eight programmable IP protocols. If the protocol field of an IPv4 or IPv6 frame matches one of the programmed values and snooping is enabled for that entry, the frame can be processed as follows: * Forward to designated management port only * Copy to management port and normal forward/flood * Discard on match The management port is identified by the port number set in register ENET SWI Bridge Management Port Configuration. (HW_ENET_SWI_MGMT_CONFIG). The function is configured using registers ENET SWI IP Snooping function1 (HW_ENET_SWI_IPSNOOP1)..8 of the register map. The snooping function can be enabled/disabled individually for each of the entries. If no protocol matches, or a match occurs but snooping is disabled or the frame is coming from the management port itself, the frame is processed normally. Note Snooping respects any optional VLAN tags (that is, extracts next after last VLAN tag). 29.4.4 TCP/UDP Port Number Snooping Programmable snooping for up to eight programmable TCP or UDP port numbers. If the source or destination port number field (configurable) within and TCP/IP or UDP/IP frame (IPv4 and IPv6) is matching the compare value and snooping is enabled for that entry, the frame can be processed as follows: * Forward to designated management port only * Copy to management port and normal forward/flood * Discard on match i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1965 VLAN Output Processing Function The management port is identified by the port number set in register ENET SWI Bridge Management Port Configuration. (HW_ENET_SWI_MGMT_CONFIG). The function is configured using registers ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP1)..8 of the register map. The snooping function can be enabled/disabled individually for each of the entries. If no entry matches, or a match occurs but snooping is disabled or the frame is coming from the management port itself, the frame is processed normally. Note Port Number Snooping is possible only if the IP header ends up to 10 words (40 bytes) after the MAC header. If the IP header is ending later (e.g. IPv6+VLAN or IPv4+>20byte Options) the port numbers cannot be parsed any more and the port number snooping will be ignored (protocol based snooping is not affected by this limit). Note For IPv6 frames the port number can only be compared if the UDP or TCP header is the very next header to the IPv6 header (i.e. it does not detect such headers if any extension headers are present in an IPv6 frame before the TCP or UDP header). 29.4.5 VLAN Output Processing Function 29.4.5.1 Overview The VLAN output processing function is used on a switch output port to manipulate the VLAN tag of the outgoing frames that leave the switch. Frames are processed based on the output Processing mode, and the number of Tags the frame contains. 29.4.5.2 Configuration Information The switch management provides the information on operating mode to configure and control the operation of the function using the register ENET SWI Define behavior of VLAN output manipulation function (HW_ENET_SWI_VLAN_OUT_MODE) of a port. There are three different modes of operation, which define how the outgoing frames should be processed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1966 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.4.5.3 Modes of Operation 29.4.5.3.1 Overview The VLAN output processing function is configured to operate in one of the following modes, which define the way outgoing frames should be treated. 29.4.5.3.2 Mode 0: disabled No frame manipulation occurs. 29.4.5.3.3 Mode 1: Strip Mode In Strip mode, all the Tags (Single or double) are removed from incoming frame 29.4.5.3.4 Mode 2: Tag Thru Mode In Tag Thru mode, the inner Tag is passed thru while the outer Tag is removed for a double Tagged frame. The following rules apply: * When a single Tagged frame is received, strip the tag from the frame. * When a double Tagged frame is received, strip the outer tag from the frame. 29.4.5.3.5 Mode 3: Transparent Mode In Transparent mode, single tagged frame is kept unchanged. The following rules apply: * When a single Tagged frame is received, frame is kept unchanged. * When a double Tagged frame is received, strip the outer tag from the frame. 29.4.6 Frame Classification and Priority Resolution 29.4.6.1 Overview When a Frame is received on an input port, several information are extracted from the frame as the Ethernet MAC Address, VLAN tag and IP Headers to determine the Frame Type and perform the relevant Classification actions. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1967 Ipv4 and Ipv6 Priority Look Up In addition, the MAC Address table can provide a priority indication for the destination MAC address if the switch management has programmed the address table accordingly (static entry). The Frame is classified into four priority levels (priority0=lowest, priority3=highest) and is eventually queued in the corresponding priority queue at the output port. 29.4.6.2 VLAN Priority Look-Up On each port, an 8 entry programmable priority table is implemented. The registers ENET SWI Port 0 VLAN priority resolution map (HW_ENET_SWI_VLAN_PRIORITY0)..2 contain the priority mapping for port n. The switch uses 3-Bits from the VLAN tag information (3-bit VLAN priority) to extract the corresponding bits from the Table, which indicates which priority the Frame should be finally classified. 2 3 8 Entries VLAN Table Priority Resolution VLAN Priority The index in the mapping table is the 3 bits of the first octet of the VLAN Tag Data with bit 5 (prio0) being the LSB and Bit 7 (prio(2)) being the MSB. VLAN Table Programming Interface Figure 29-5. VLAN Table Overview 29.4.6.3 Ipv4 and Ipv6 Priority Look Up 29.4.6.3.1 Overview The switch can classify both Ipv4 and Ipv6 frames: A 64-Entry Table is implemented per port to classify the IPv4 Frames and a 256-Entry Table is implemented per port to classify IPv6 Frames (The IP COS Tables) (see registers ENET SWI IPv4 and IPv6 priority resolution table programming (HW_ENET_SWI_IP_PRIORITY)). On the IPv4 COS table entry, the Frame's 6-Bit DiffServ field is provided and the Table returns the 3-bit priority information. On the Ipv6 COS table entry, the 8-Bit Class of Service field is provided and the Table returns the 3-bit priority information. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1968 Freescale Semiconductor, Inc. Priority Resolution IP Header Data Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 8 256 Entries Ipv6 COS Table 64 Entries Ipv4 COS Table IP COS Table Programming Interface Figure 29-6. IP COS Tables Overview 29.4.6.3.2 Classification Table Programming Model To program the mapping tables a indirect addressing scheme is implemented using a single register ENET SWI IPv4 and IPv6 priority resolution table programming (HW_ENET_SWI_IP_PRIORITY) within the register interface. 31 9 8 per port data 0 address bit 5.. 0 256..319..IPv4 TOS 8:0 mapping address 0..255: IPv6 COS mapping per port data 5:4 3:2 1:0 31: read transaction Figure 29-7. IP_PRIORITY Mapping Table Programming Model The table is implemented in a single 320 deep table which is used for both IPv4 6-bit TOS and IPv6 8-bit COS mappings. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1969 Ipv4 and Ipv6 Priority Look Up * The first 256 entries represent the IPv6 COS field mapping. The received COS field of a frame is used to address a row from 0..255. The value stored is read and used as priority for the frame. * The last 64 entries represent the IPv4 DiffServ field mapping. The received DiffServ (upper 6-bits of TOS) value of a frame is used to address a row from 256..319. * Each entry of the table provides the priority mapping for port0 in bits 1:0 (00=queue0, 01=queue1, 10=queue2, 11=queue3), for port 1 in bits 3:2 and port 2 in bits 5:4. To write a table row into the table the address is provided in bits 8:0 and the data in bits 13:9, where bit 9 represents bit0 of the data and bit13 represents bit5 of the data. To read a table row, the read bit must be set when writing into the IP_PRIORITY register. This will trigger a read transaction to the address provided in bits 8:0 of the register. After this, reading the register provides the data returned from the table for this address. When writing an entry into the table, software can only write the mapping for all ports in one write transaction. Therefore software must implement a read-modify-write scheme, to first read the current table contents, modify the priority bits for the port of interest without modifying the other ports bits and then write back the complete data word into the table. 29.4.6.4 Priority Resolution The Priority Resolution function, for a Port n, is, on each port independently, programmable with the registers to enable or disable VLAN or IP or MAC address based classification. The priority resolution follows the following ruleset depending on which classifications are enabled (PRIORITY_CFGn) and which fields are found within the frame: * if IP classification is enabled and IP header found => map priority according IP_PRIORITY table * else if VLAN classification is enabled and VLAN tag found => map priority according VLAN_PRIORITY table * else if MAC classification is enabled and MAC address found => take priority from address table, if it is a static entry * else use default priority as specified in PRIORITY_CFG. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1970 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.4.6.5 Bridge Control Protocol Identification To allow for implementation of bridge control protocols like the Spanning tree protocol, all control frames (Bridge Protocol Data Units, BPDU) are marked when they enter the switch. The mark then can be used by the Input Port Blocking function to drop the frame after the address learning (see also 5.10.5 page 43). In addition, the function can be configured to pass all frames or to pass only control frames (that is, covering spanning tree port states such as blocking, listening, learning) and discard all other frames. 29.4.7 Input Port Selection The port selection constantly checks (polling) all input ports for available data and if any data is available, a port is selected and frame data is read from the input. After one frame has been read, another port is selected, even if further data is available on the current port. This means for the application on a port atlantic input interface, that it is not allowed to perform back-to-back frame transfers to the switch. Instead the application must wait for a new selection after one frame has been transferred. 29.4.8 Layer 2 Look Up Engine 29.4.8.1 Overview A hash code is calculated using the frame destination MAC address. It is used as an entry (address) to a table, which contains, for each hash value MAC addresses with destination port number and validity information. As one hash code value can represent more than one MAC address, the memory implements for each pointer, up to eight MAC address entries, which are searched linearly. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1971 Layer 2 Look Up Engine Miss Hit Destination Address CRC-8 1 CRC Based 8-Bit Hash Code Calculation 2048x84 Destination Port 2 Linear Search Figure 29-8. Port Look-Up Overview 29.4.8.2 Hash Code For a MAC address table up to 2048 entries, an 8-bit hash value is calculated from the 48-bits of the destination MAC address. The hash code is using a CRC-8: * x^8 + x^2 + x + 1 (0x07) 29.4.8.3 Address Memory The address memory is divided into blocks. Each block contains eight records, which contain 64-bit of information each. Each record contains the 48-Bit MAC address and provides the necessary forwarding information as well as priority or time stamp information. Two types of records are defined. 1. Dynamic Record: The dynamic entry provides the MAC address together with a 10bit timestamp and destination port number. These entries are created by the learning function based on received frames to enable forwarding of frames to dedicated ports. Dynamic entries are deleted by the aging function if not updated. 2. Static Multiport/Priority Record: Switch Management can also write static entries in the table, which can include priority information as well as multiple destination ports for forwarding. The MAC address can be unicast or multicast. These records can be used to for example, specify the ports to participate in a specific multicast domain or to assign a MAC address based priority to a frame. The aging and learning functions ignore static records. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1972 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 63 60 4 bit Port# 59 50 10 bit Timestamp 47 0 0 MAC Address (48 Bits) 48: Record Valid 49: Record Type ... 53 52..50 Port Bitmask 1 n-bit Port Mask 3-bit priority Figure 29-9. Address Memory Record Types The record's bit 49 decides which type of record is found in the table: * If 0, a dynamic entry is available and the 10-bit timestamp and 4-bit port number are given in the upper bits of the record. * If 1, a static entry is available with a 3-bit priority field followed by a port bit mask of 3 bits. The record bit 53 represents Port 0, bit 54 Port 1 and bit 55 port 2. The frame will be forwarded to all ports that have a 1 in the port bitmask. The source port will be removed dynamically from the bitmask during forwarding (a frame is never forwarded to the port where it came from). The 48-bit MAC address is stored with the first octet in bits 7:0 and the sixth octet in 47:40 of the record. 29.4.9 Layer 2 Lookup Tasks Overview 29.4.9.1 MAC Address Lookup The 48-Bit destination MAC address of each frame received by the Switch, on any of its interfaces, is extracted by the Hardware and provided to the look-up engine together with the physical interface number. If the frame carries a VLAN tag, the tag information is also extracted and provided to the look-up engine. If the received frame is a Unicast or Multicast frame, a Two-Stage lookup process is implemented. The look-up engine first calculates the hash value from the MAC address. The hash code is used as an entry to the Switch address table. The look-up function can provide three results with tree different associated actions performed by the switch hardware: 1. The address is in the table and associated with a correct port number: * The switch forwards the frame only to the looked up port. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1973 Layer 2 Lookup Tasks Overview 2. The address is in the table but is associated with the port on which it was received: * The switch discards the frame and does not forward it to any port. 3. The address is not found in the table: * The Switch engine sends the received frame to all ports except the port on which it was received (Flooding). If a Broadcast frame is received, the switch Hardware sends the received frame to all output ports, except the one from which it was received (Flooding). Note Flooding and additional frame filtering can be controlled, for example, to avoid the duplication of critical information to unwanted destinations, with the mechanism described in Section 5.10.3 page 41. 29.4.9.2 Forced Forwarding The MAC address lookup result can be overwritten using the forced forwarding configuration available in the register ENET SWI Enable forced forwarding for a frame processed from port 0 (HW_ENET_SWI_FORCE_FWD_P0). This feature is available only for frames coming from the local port (Port 0). When forced forwarding is enabled for a frame, the frame will be forwarded to the forced destination port(s), ignoring any results from the MAC destination address lookup. Forced forwarding only replaces the mac lookup function, all other filtering functions (for example, VLAN verification) act as normal. 29.4.9.3 Learning The Switch Hardware extracts the source MAC address of each frame received on each of the switch ports and provides it, through the registers ENET SWI Learning Records A (0) and B (1) (HW_ENET_SWI_LRN_REC_0) and ENET SWI Learning Record B(1) (HW_ENET_SWI_LRN_REC_1), to the Switch Firmware which implements the learning task. The register ENET SWI Learning data available status. (HW_ENET_SWI_LRN_STATUS) indicates availability of learning data. Learning Interface The interface implements a FIFO buffer that stores up to 32 words of 32-bit each. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1974 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) De-Queuing Control Status Read Learning Interface Figure 29-10. Learning Interface Overview For each Frame processed by the switch engine, two 32-Bit records (Record A(0) and Record B(1)) are written in the Information FIFO, Record A is written first. The MAC address available in Records A(0) and B(1) is the source MAC address of the Frame. Record A holds the first 4 bytes of the frame source address (1st=A[7:0], 4th=A[31:24]), Record B the last 2 bytes (5th=B[7:0], 6th=B[15:8]). The Hash code in Record B is calculated, with the Source MAC Address, with the same Hash Polynomial used for Look-Up (as defined in 5.8.2 page 36) and the 4-Bit port number defines the Port / MAC Address association. 31 MAC Address (48 Bits) Frame Record A Frame Record B 0 4 Reserved Bits 4-Bit Port Number 8-Bit hash code Figure 29-11. Frame Information Records - 8-Bit Hash Values When information for at least one Frame (Two Records) is available, the status indication in register LRN_STATUS is set to '1'. To read the Frame records, the register LRN_REC_0 (Record A) must be read first followed by a read to LRN_REC_1 (Record B). Note A read to LRN_REC_1 triggers the retrieval of the next record pair from the FIFO if any. The learning task (software) is using this information and then executes as follows: 1. For every frame received, the source address with port and timestamp information is stored in the address lookup table. The following information are stored for each entry: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1975 Layer 2 Lookup Tasks Overview * MAC address: the 48-bit address is stored in the table. * Time stamp: a 10-bit value, used to determine the age of an entry. * Port number: a 4-bit value, which indicates the port through which the frame was received. 2. If there is no more space in the MAC address table, a new entry replaces the oldest entry with an identical matching hash value. 29.4.9.4 Migration If the Firmware received a MAC address, which is already in the Switch table but is associated to a different physical port number, the current entry is overwritten with the new information and the timestamp is set to the current time. 29.4.9.5 Aging Aging refers to deleting old entries within the table. It proceeds as follows: 1. The time stamp is stored with all the entries and is updated each time the source address appears again. The time stamp is a 10-bit value. 2. If a record is not updated for a longer period of time, it is removed from the table if it is a dynamic entry. 3. Static entries are not affected by the aging process and kept always. This process runs continuously in the background of the firmware. The aging period is software controlled and programmable, defaulting to 4 seconds per step giving a range of 4 seconds to 68 minutes. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1976 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.4.10 Frame Forwarding Tasks 29.4.10.1 Overview When an input port has been selected the frame is forwarded to its corresponding output port. Output port resolution and switching is based on the information from the two-stage MAC Address look-up (see 5.9 page 37) followed by additional resolution functions to allow frame duplication and flooding control, which are described in the following sections. start MAC Address Lookup VLAN Domain Verification Multicast / Broadcast VLAN Domain Resolution Port Mirroring Resolution Protocol Snooping Bridge Protocol Frame Resolution Congestion Resolution Matrix Programming discard Frame Forwarding Figure 29-12. Frame Forwarding Tasks Overview i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1977 Broadcast Multicast VLAN Domain Resolution 29.4.10.2 VLAN Domain Verification When the L2 MAC Address Lookup was successful and identified a dedicated output port for the frame, the output and input port can be verified to be within the correct VLAN domain if VLAN verification is enabled for the port (register ENET SWI Verify VLAN domain. (HW_ENET_SWI_VLAN_VERIFY)) and the frame contains a VLAN tag. The VLAN resolution table (see 5.10.3.2 page 41 below) is used as follows: * If the frame's VLAN id is found within the table but the output port number is not a member of the VLAN domain, or the input port is not a member of the VLAN domain, the frame will be marked invalid and will be discarded eventually. * If the frame's VLAN id is found within the table and the output port and input port are both members of the VLAN domain the frame will be forwarded normally. * If the frame's VLAN id is not found in the VLAN table, or the frame has no VLAN tag, the frame will be forwarded normally (default broadcast domain), or, if the discard bit for the port is set (also in register VLAN_VERIFY) it will be discarded. 29.4.10.3 Broadcast Multicast VLAN Domain Resolution 29.4.10.3.1 Overview To ensure that traffic within VLAN channels are always routed to the correct ports, for example to avoid the duplication of critical information through a Network, the Switch implements a resolution mechanism that, for any frame that is switched to multiple ports, checks the VLAN ID provided with the current frame. The VLAN resolution mechanism searches the VLAN Resolution Table (See Registers ENET SWI VLAN domain resolution entry 0. (HW_ENET_SWI_VLAN_RES_TABLE_0) to ENET SWI VLAN domain resolution entry 31. (HW_ENET_SWI_VLAN_RES_TABLE_31)), which stores up to 32 unique VLAN IDs, each associated to a port bit mask. The resolution mechanism is used for the following conditions: * Unicast Frames with a destination MAC address that are not in the Table of the Layer 2 engine * Mulicast Frames with a destination MAC address that are not in the Table of the Layer 2 engine * Any Broadcast Frame i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1978 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.4.10.3.2 VLAN Resolution Table The VLAN resolution Table (Registers VLAN_RES_TABLE_0 to VLAN_RES_TABLE_31) provides a unique VLAN ID / port bit mask association for up to 32 VLANs. A default entry (register ENET SWI Default broadcast resolution. (HW_ENET_SWI_BCAST_DEFAULT_MASK)) provides an additional port bit mask. The port bit mask implements one bit for each port. Each Port Bit indicates, if set to '1', that it is member of the VLAN and frames with the corresponding VLAN ID can be switched to the port. If the Port Bit is set to '0' a frame with the corresponding VLAN ID will not be switched to that port. If no VLAN ID matches, the default mask is applied. 14 3 Entry 0 VLAN ID #0 Entry 1 VLAN ID #1 2 1 0 * * * Entry 31 VLAN ID #31 Default Entry (BCAST_DEFAULT_MASK) [14:3] VLAN ID [2:0] Port Mask Figure 29-13. VLAN Resolution Table Overview 29.4.10.3.3 VLAN Switching and Resolution Mechanism The VLAN table is used for both, VLAN domain verification (see section VLAN Domain Verification) as well as VLAN resolution. Once the frame has passed any VLAN domain verification (that is, will not be discarded by the verification function already) the forwarding resolution applies. * If the destination MAC address (Unicast or Multicast) is found in the MAC address table and i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1979 Broadcast Multicast VLAN Domain Resolution * The frame carries a VLAN tag that is found in the VLAN table, the frame can be forwarded only to the ports within the VLAN domain and will be discarded if the destination port is not member of the VLAN domain. * Otherwise, if the frame carries a VLAN tag that is not found in the VLAN table, or does not contain a VLAN tag, it is forwarded as indicated by the lookup table (note that VLAN domain verification can be configured to discard the frame in this case if enabled). * If the destination MAC address (Unicast or Multicast) is not found in the MAC address table, or if the destination address is the Broadcast address, the frame is forwarded according to the following rules: * If the frame carries a VLAN tag, the VLAN resolution table is searched for a matching VLAN ID and the frame is sent to all ports that are associated with the VLAN ID. * If the frame carries a VLAN tag and the VLAN ID does not match any entry in the VLAN Resolution Table, the frame is forwarded to all ports that are enabled to receive broadcast frames by the default entry. * If the frame does not carry a VLAN tag the frame is forwarded to all ports that are enabled to receive broadcast frames by the default entry. * The frame is discarded, if it cannot be associated with any VLAN group and if the default (broadcast) group has been set to all zero. To disable the VLAN resolution, set all VLAN IDs to 0xFFF or (0x000 if that id is not used) and all Port Mask bits to '1'. If the VLAN resolution is disabled, normal port flooding is implemented as described in section VLAN Priority Look-Up. The default entry can still be used to restrict broadcast to only dedicated ports, if not programmed to all '1'. 29.4.10.4 Port Mirroring The function allows duplicating traffic to a dedicated mirror port. Any one of the ports can be assigned to act as a mirror port (register ENET SWI Port Mirroring configuration. (HW_ENET_SWI_MIRROR_CONTROL)). The mirror port then is always added to the list of output ports and therefore receives a copy of the frame, if any of the following rules matches with the currently processed frame: * Ingress Port Number Match i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1980 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) When a frame is received on port N and the corresponding bit in the register ENET SWI Port Mirroring Ingress port definitions. (HW_ENET_SWI_MIRROR_ING_MAP) is set to 1, the frame is mirrored. * Egress Port Number Match When a frame is forwarded to port N and the corresponding bit in the register ENET SWI Port Mirroring Egress port definitions. (HW_ENET_SWI_MIRROR_EG_MAP) is set to 1, the frame will be mirrored. * MAC Ingress SA Match When the Ingress Port Number match succeeded (see above) and the MAC source address matches the MIRROR_ISRC, the frame will be mirrored. * MAC Ingress DA Match When the Ingress Port Number match succeeded (see above) and the MAC destination address matches the MIRROR_IDST, the frame will be mirrored. * MAC Egress SA Match When the Egress Port Number match succeeded (see above) and the MAC source address matches the MIRROR_ESRC, the frame will be mirrored. * MAC Egress DA Match When the Egress Port Number match succeeded (see above) and the MAC destination address matches the MIRROR_EDST, the frame will be mirrored. In addition, a counter is implemented (Register ENET SWI Count Value for Mirror filtering. (HW_ENET_SWI_MIRROR_CNT)) that allows specifying that only every Nth frame that matches any of the above criteria is mirrored. If the counter is set to 1 or 0, every frame is mirrored that matches any of the above criteria. 29.4.10.5 Protocol Snooping The incoming frames are parsed for IPv4 and IPv6 headers and UDP/TCP if available. The snooping function can be programmed to redirect specific protocols exclusively to the management port. See section IP Snooping and TCP/UDP Port Number Snooping for a description of the snooping options. The snooping is active only for frames received from the external ports. When a frame is transmitted from the management port itself, snooping does not apply and the frames are forwarded normally (MAC lookup). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1981 Bridge Protocol Frame Resolution 29.4.10.6 Bridge Protocol Frame Resolution 29.4.10.6.1 Overview To implement bridge control protocols like the Spanning Tree protocol, the following control functions are performed by the Protocol Frame Resolution function: 29.4.10.6.2 Input Port Blocking The input port blocking function is used to avoid forwarding of frames after address learning. The firmware can program the register ENET SWI Define port in blocking state and enable or disable learning. (HW_ENET_SWI_INPUT_LEARN_BLOCK) and if a frame is received on a port N that should be blocked (blocking bit N=1) and the frame is not a bridge protocol frame (see below), the frame will be marked for discard and will not be forwarded to any output port. 29.4.10.6.3 Input Port Learning Disable To reduce processing load from the firmware, a port can be configured for exclusion from learning (see register INPUT_LEARN_BLOCK). When learning is disabled on a port no source address extraction happens for incoming frames, with the exception of incoming BPDU frames. BPDU frame source addresses are always extracted and forwarded to the learning interface. 29.4.10.6.4 Management Port Forwarding Bridge Protocol Frames are, if enabled, always forwarded to the dedicated management port (see ENET SWI Bridge Management Port Configuration. (HW_ENET_SWI_MGMT_CONFIG)) independent of any address lookup or other resolution functions. Bridge Protocol Frames are identified by its destination address being any of the following: * 01-80-c2-00-00-00 to 01-80-c2-00-00-0F (Spanning Tree, IEEE 802.1d, Table 7-9) * 01-80-c2-00-00-10 (Bridge Management Address, 802.1d, Table 7-10) * "01-80-c2-00-00-20 to 01-80-c2-00-00-2F (Generic Attribute Registration Protocol, 802.1d, Table 12-1) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1982 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.4.10.6.5 Management Frame Forwarding If the management port transmits Frames, they are forwarded according to the port mask defined in the configuration register ENET SWI Bridge Management Port Configuration. (HW_ENET_SWI_MGMT_CONFIG). A handshaking mechanism is implemented that can be used by the firmware to configure the destination port mask on a frame-by-frame basis for management frames. Note VLAN domain verification/discard (see register ENET SWI Verify VLAN domain. (HW_ENET_SWI_VLAN_VERIFY)) should be switched off for the management port to avoid that the switch discards management frames. 29.4.10.7 Congestion Resolution 29.4.10.7.1 Overview The congestion resolution function is used whenever an output port is not available and data needs to be sent to that port. An output port is defined to be available if the port is enabled (bit in PORT_ENA set 1) and the output buffer (shared memory) is not congested. If, for a port, one of these conditions is not valid, the port is not available and frames cannot be switched to that port. The congestion resolution function determines whether the frame should be processed further or discarded according to the following rules: 29.4.10.7.2 Unique Destination (one input to one output) If the output port is enabled and can accept a frame the frame will be forwarded normally. In any other case the frame will be discarded. If a frame switched to port N, the counter ODISCN is incremented. 29.4.10.7.3 Multiple Destinations (Flooding) After broadcast / flooding resolution a frame needs to be switched to multiple output ports. * Output disabled: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1983 Output Frame Queuing All disabled ports are removed from the list of outputs. * Output congestion: If any of the outputs cannot accept a frame (as indicated by the output queue management for the port, implementation specific) it is also removed from the list of outputs. If no output port is left in the list of outputs, the frame is discarded. If a frame switched to port N, the counter ODISCN is incremented. 29.4.10.8 Switching After the output port(s) have been determined, the switch control enables the corresponding path though the Switch Matrix and the frame is forwarded to the output queue(s). In a similar fashion, if a Frame should be switched to multiple ports (for example, Broadcast), the switch control enables the corresponding paths though the Switch Matrix and the frame is forwarded to all the destination output ports. 29.5 Output Frame Queuing 29.5.1 Overview The memory controller implements a shared memory architecture to store Frames of arbitrary size for multiple destination ports. Each destination port implements 4 priority queues. The memory controller implements a single write input port and three output ports with the capability to perform virtual frame duplication on the output ports (Multiple reads on multiple ports of a single frame stored in the buffer). A single large memory, partitioned in 256 byte cells, is implemented to efficiently share the available space for small and large frames without leaving large unused spaces when storing small frames. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1984 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) read data write data Dual Port Shared Memory write address write enable cell used Cell Factory write data to each port read address cell# return select free cell# read address Write Control destination ports write cell# eop, last cell length Output Queue Manager data available select Port Read Manager (timemultiplex) per port ready indication per port control signals (sop,eop,mod, wren) Figure 29-14. Memory Controller Overview 29.5.2 Cell and Queue Concept The shared memory is partitioned in 256 byte cells using a 32-bit datapath implementation. This results in a cell holding 64 32-bit words. Incoming frames are stored, partitioned in cells, in the shared memory and only the cell numbers are managed by the individual port queues. Due to the arbitrary length of incoming frames, the last cell may not be fully utilized. A frame can spread from one to any number of cells. The number of bytes used in the last cell is also stored in the queue FIFO together with the individual cell numbers. Cells can be stored anywhere in the shared memory. A single frame must not necessarily be stored in consecutive cells but instead can be scattered over the complete memory at arbitrary positions. The start of a cell is fixed to a 64-word boundary (that is, the memory start address of a cell is simply the cell # multiplied by 64). Per port, a queue FIFO is implemented that stores the cell numbers for the frames The number of bytes used in the last cell is also stored in the queue FIFO together with the individual cell numbers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1985 Output Frame Queuing 1 1 cell 41 cell 40 1 cell 33 2 cell 27 1 cell 20 1 cell 12 per cell use count last cell length # 27 (eop) last cell length # 40 (eop) # 12 Queue 1 FIFO last cell length # 41 (eop) # 33 # 20 Queue 2 FIFO last cell length # 27 (eop) Queue 3 FIFO Shared Memory Figure 29-15. Cell Storage Concept The example in Figure 29-15 shows the storage of three frames with one frame duplicated and stored in two queues (see the orange cells in the figure). 29.5.3 Write Control Module The Write Control Module receives frames from the Switch engine, partitions and stores the frames in the shared memory. The cell numbers used to store the frame are forwarded to the port output managers. 29.5.4 Cell Factory Module The Cell Factory implements the cell management, it always provides a free cell number to the write control module so, the write control module can immediately start writing into memory to avoid any write latency. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1986 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.5.5 Output Queue Manager 29.5.5.1 Overview The Output Queue Manager implements, per port, the individual queue FIFOs (One queue FIFO per priority). The queue FIFOs are addressed by the priority information extracted by the Switch classification engine. Per port, eight prioritized queues are implemented. When more than one queue has data available, the read logic selects one of the queues with a Weighted Fair Queuing scheduling algorithm. 29.5.5.2 Weighted Fair Queuing scheduling algorithm The weight of each queue, common for all ports, can be configured between 0 and 30 with the register ENET SWI Queue weights for each queue. (HW_ENET_SWI_QM_WEIGHTS). A Queue with a higher weight is served more often than a queue with lower weight. Queue 0 represents the lowest priority, Queue 3 the highest priority queue. The scheduler first serves the queue with the highest weight. Each time the scheduler serves a queue, the weight of the other queues is increased and the weight of the selected queue is reset (decreased) to its programmed weight value. This guarantees that all queues are served eventually. When multiple queues have the same weight, the queue with the higher number is served first. If all weights are programmed to 0 (default), a strict priority scheme is active where the higher priority queues are served as long as they are not empty. 29.5.6 Congestion Management The Write control logic is protected against memory overflow. When data is written is the cell factory has no more free cells (Number of available cells less than value programmed in register ENET SWI Low Memory threshold. (HW_ENET_SWI_QMGR_MINCELLS) ), the frame is discarded or terminated with an error (i.e. forwarded to the output queue manager with the end-of-packet and error indication). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1987 Reset and Stop Functions If the congestion persists, the Switch resolves the congestion as specified in section "Congestion Resolution". 29.5.7 Implementation Notes Memory Size The memory controller is capable of addressing up to 32768 bytes of memory. The external address bus to the shared memory provides the necessary bits to address a memory of size 8192x32 (deep x wide). However, only 24 Kbyte will be used and the controller will only use addresses from 0 to 6143. Datapath The switch and all datapath has a width of 32 bit. 29.6 Reset and Stop Functions 29.6.1 Stop Controls The register ENET SWI Defines several global configuration settings. (HW_ENET_SWI_MODE_CONFIG) offers several bits that control output pins. In addition, some controls have an effect on internal logic functions: * stop_en: no internal function. * switch_en: when de-asserted, all DMA registers are cleared. * switch_reset: no internal function. An external logic may use the controls to disable or enable the switch function as necessary. 29.6.2 Port Disable The switch toplevel offers a disable input for each port (port_dis(2:0). When a pin is asserted (1), the corresponding port enable bits within register ENET SWI Port Enable Bits. (HW_ENET_SWI_PORT_ENA) for both transmit and receive will be cleared. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1988 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) This results in the following behavior: * If the port-enable bits of port0 are cleared, it also resets the input buffer and output buffer at the port0 DMA interface. * The ready output to DMA0 (ff_tx_rdy0) will be asserted allowing the application to continue writing data at the interface, which will be ignored (application flush). No further transmitted frame status (tx_ts_val0) will be given (that is, for any currently stored if any, as well as the currently ignored). * If the transmit enable is cleared while the interface is currently transferring a frame to the DMA, the frame is aborted (output buffer reset). The eop is not produced. Therefore, the connected DMA module must be reset to ensure proper restart after re-enabling the port. * If any port's transmit enable bit is cleared, the shared memory will continue delivering the frames stored currently for a port as normal (that is, flushing the memory). New frames will be discarded before they are written into the shared memory. That is, no invalid frame will appear on the MAC interfaces after disabling or re-enabling a port. * If any port's receive enable bit is cleared while a frame is transferred, this frame will be aborted with an error internally. The port's ready indication will stay asserted (output ff_tx_rdy=1) to flush any application data. Reenabling the port at any time will ignore any input data until a sop starts a new frame. 29.6.3 Port 0 Input Protection The port 0 input buffer is protected for application errors that abort a frame without writing a proper eop to the interface. The next frame then written to the port 0 transmit interface will be concatenated with whatever data was already written before, but the frame will be marked with an error and hence will be forwarded and transmitted with an error indication (mii tx error). If the port0 input buffer is reset (by deasserting PORT_ENA receive enable bit) while a frame is transferred to the switch internally, the frame transfer will be aborted in a clean way (producing an eop with error indication) to avoid blocking the switch. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1989 Firmware Architecture and Tasks 29.6.4 Port 1,2 Input Protection Ports 1 and 2 are protected for a second SOP in case the MAC is reset in the middle of a receive transaction to the switch hence did not produce a proper EOP to the switch. The next frame will be concatenated with whatever was provided to the switch before and marked with an error. If the MAC is stopped in the middle of a transaction, the switch is blocked, waiting for the EOP, not serving any of the other ports. Clearing the PORT_ENA receive enable bit in this situation will terminate the frame with an error internally to the switch hence remove the blocking condition. 29.6.5 DMA Bus Error When the DMA bus error input (dma_eberr_int) is asserted, the DMA registers are all cleared. If the corresponding interrupt was enabled the ipi_eberr_int pin will be asserted. 29.7 Firmware Architecture and Tasks 29.7.1 Overview The switch firmware provides the necessary functions and a reference implementation to operate the switch. 29.7.2 Firmware Environment The Switch is typically used together with an embedded 32-Bit processor subsystem, connected to the register, learning and address table interfaces. The firmware is available in generic C source code to allow for ease of use and migration to any processor environment. 29.7.3 Firmware Overview The firmware can be used in a low memory footprint stand-alone C environment or together with any operating system. The firmware can be divided in the following functional modules. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1990 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.7.3.1 Application Main The task performs the following functions: 1. Initialization: On system startup, all the variables, tables and memory spaces are initialized and allocated. 2. Supervision: It takes care of time and ensures all other tasks are called to maintain runtime operation. 29.7.3.2 Learning Task The learning task reads records from the learning interface and updates the address lookup table with new entries and updates timestamps of existing entries. 29.7.3.3 Timer Task A timer task is called typically every 4 seconds (configurable) and increments the local time that is used for time stamping table entries. The aging process to determine old entries also uses the time. 29.7.3.4 Aging Task The task periodically checks the address table for old entries. If an entry is older than a configurable maximum, the entry is removed from the table. 29.8 FIFO Interface Data Structure The data structure defined in the following tables for the FIFO interface must be respected to ensure proper data transmission on the Ethernet Line. Byte 0 is sent and received first to/from the line. Table 29-2. FIFO Interface Data Structure 63 Word 0 56 55 Byte 7 48 Byte 6 47 40 Byte 5 39 32 Byte 4 31 24 Byte 3 23 16 Byte 2 15 8 Byte 1 7 0 Byte 0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1991 Programmable Registers Table 29-2. FIFO Interface Data Structure (continued) Word 1 ... Byte 15 Byte 14 Byte 13 Byte 12 Byte 11 Byte 10 Byte 9 Byte 8 ... The size of a Frame on the FIFO interface may not be a modulo of 64-Bit. Together with the last word of the frame, the valid byte(s) of data is (are) defined by the interface signal ff_tx_modN(2:0) for transmit and ff_rx_modN(2:0) for receive respectively. Table 29-3. Transmit/Receive FIFO Interface Last Word Modulo Definition ..._mod(2:0) Valid Bytes 000 ff_tx_data(63:0) ff_rx_data(63:0) 001 ff_tx_data(7:0) ff_rx_data(7:0) 010 ff_tx_data(15:0) ff_rx_data(15:0) 011 ff_tx_data(23:0) ff_rx_data(23:0) 100 ff_tx_data(31:0) ff_rx_data(31:0) 101 ff_tx_data(39:0) ff_rx_data(39:0) 110 ff_tx_data(47:0) ff_rx_data(47:0) 111 ff_tx_data(55:0) ff_rx_data(55:0) 29.9 Programmable Registers The SWITCH module implements a register space of 1K 32-bit registers, base address is 0x800F8000. All writes must provide 32-bit of data and all reads return 32-bits of data. Reserved bits should be written with 0 and ignored on read to allow future extension. Unused registers read back 0 and a write has no effect. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1992 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800F_8000 ENET SWI revision (HW_ENET_SWI_REVISION) 32 R 0001_0121h 29.9.1/1998 800F_8000 ENET SWI lookup MAC address memory start (HW_ENET_SWI_LOOKUP_MEMORY_START) 32 R/W 0000_0000h 29.9.2/1999 800F_8004 ENET SWI Scratch Register (HW_ENET_SWI_SCRATCH) 32 R/W 0000_0000h 29.9.3/1999 800F_8008 ENET SWI Port Enable Bits. (HW_ENET_SWI_PORT_ENA) 32 R/W 0000_0000h 29.9.4/2000 800F_8010 ENET SWI Verify VLAN domain. (HW_ENET_SWI_VLAN_VERIFY) 32 R/W 0000_0000h 29.9.5/2002 800F_8014 ENET SWI Default broadcast resolution. (HW_ENET_SWI_BCAST_DEFAULT_MASK) 32 R/W 0000_0000h 29.9.6/2003 800F_8018 ENET SWI Default multicast resolution. (HW_ENET_SWI_MCAST_DEFAULT_MASK) 32 R/W 0000_0000h 29.9.7/2004 32 R/W 0000_0000h 29.9.8/2006 ENET SWI Define port in blocking state and enable or 800F_801C disable learning. (HW_ENET_SWI_INPUT_LEARN_BLOCK) 800F_8020 ENET SWI Bridge Management Port Configuration. (HW_ENET_SWI_MGMT_CONFIG) 32 R/W 0000_0000h 29.9.9/2007 800F_8024 ENET SWI Defines several global configuration settings. (HW_ENET_SWI_MODE_CONFIG) 32 R/W 0000_0000h 29.9.10/ 2009 800F_8028 ENET SWI Define behavior of VLAN input manipulation function (HW_ENET_SWI_VLAN_IN_MODE) 32 R/W 0000_0000h 29.9.11/ 2010 800F_802C ENET SWI Define behavior of VLAN output manipulation function (HW_ENET_SWI_VLAN_OUT_MODE) 32 R/W 0000_0000h 29.9.12/ 2011 800F_8030 ENET SWI Enable the input processing according to the VLAN_IN_MODE for a port (HW_ENET_SWI_VLAN_IN_MODE_ENA) 32 R/W 0000_0000h 29.9.13/ 2012 800F_8034 ENET SWI The VLAN type field value to expect to identify a VLAN tagged frame. (HW_ENET_SWI_VLAN_TAG_ID) 32 R/W 0000_8100h 29.9.14/ 2013 800F_8040 ENET SWI Port Mirroring configuration. (HW_ENET_SWI_MIRROR_CONTROL) 32 R/W 0000_0000h 29.9.15/ 2014 800F_8044 ENET SWI Port Mirroring Egress port definitions. (HW_ENET_SWI_MIRROR_EG_MAP) 32 R/W 0000_0000h 29.9.16/ 2015 800F_8048 ENET SWI Port Mirroring Ingress port definitions. (HW_ENET_SWI_MIRROR_ING_MAP) 32 R/W 0000_0000h 29.9.17/ 2016 800F_804C ENET SWI Ingress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ISRC_0) 32 R/W 0000_0000h 29.9.18/ 2018 800F_8050 ENET SWI Ingress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ISRC_1) 32 R/W 0000_0000h 29.9.19/ 2018 800F_8054 ENET SWI Ingress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_IDST_0) 32 R/W 0000_0000h 29.9.20/ 2019 800F_8058 ENET SWI Ingress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_IDST_1) 32 R/W 0000_0000h 29.9.21/ 2019 800F_805C ENET SWI Egress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ESRC_0) 32 R/W 0000_0000h 29.9.22/ 2020 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1993 Programmable Registers HW_ENET_SWI memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800F_8060 ENET SWI Egress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ESRC_1) 32 R/W 0000_0000h 29.9.23/ 2020 800F_8064 ENET SWI Egress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_EDST_0) 32 R/W 0000_0000h 29.9.24/ 2021 800F_8068 ENET SWI Egress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_EDST_1) 32 R/W 0000_0000h 29.9.25/ 2021 800F_806C ENET SWI Count Value for Mirror filtering. (HW_ENET_SWI_MIRROR_CNT) 32 R/W 0000_0000h 29.9.26/ 2021 800F_8080 ENET SWI Memory Manager Status. (HW_ENET_SWI_OQMGR_STATUS) 32 R/W 0060_004Ah 29.9.27/ 2022 800F_8084 ENET SWI Low Memory threshold. (HW_ENET_SWI_QMGR_MINCELLS) 32 R/W 0000_0009h 29.9.28/ 2024 800F_8088 ENET SWI Statistic providing the lowest number of free cells reached in memory (HW_ENET_SWI_QMGR_ST_MINCELLS) 32 R/W 0000_0000h 29.9.29/ 2024 800F_808C ENET SWI Port Congestion status (internal). (HW_ENET_SWI_QMGR_CONGEST_STAT) 32 R 0000_0000h 29.9.30/ 2025 800F_8090 ENET SWI Switch input and output interface status (internal). (HW_ENET_SWI_QMGR_IFACE_STAT) 32 R 0000_0007h 29.9.31/ 2027 800F_8094 ENET SWI Queue weights for each queue. (HW_ENET_SWI_QM_WEIGHTS) 32 R/W 0000_0000h 29.9.32/ 2028 800F_809C ENET SWI Define congestion threshold for Port0 backpressure. (HW_ENET_SWI_QMGR_MINCELLSP0) 32 R/W 0000_0009h 29.9.33/ 2029 800F_80BC ENET SWI Enable forced forwarding for a frame processed from port 0 (HW_ENET_SWI_FORCE_FWD_P0) 32 R/W 0000_0000h 29.9.34/ 2029 800F_80C0 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP1) 32 R/W 0000_0000h 29.9.35/ 2031 800F_80C4 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP2) 32 R/W 0000_0000h 29.9.36/ 2032 800F_80C8 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP3) 32 R/W 0000_0000h 29.9.37/ 2033 800F_80CC ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP4) 32 R/W 0000_0000h 29.9.38/ 2035 800F_80D0 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP5) 32 R/W 0000_0000h 29.9.39/ 2036 800F_80D4 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP6) 32 R/W 0000_0000h 29.9.40/ 2038 800F_80D8 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP7) 32 R/W 0000_0000h 29.9.41/ 2039 800F_80DC ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP8) 32 R/W 0000_0000h 29.9.42/ 2041 800F_80E0 ENET SWI IP Snooping function1 (HW_ENET_SWI_IPSNOOP1) 32 R/W 0000_0000h 29.9.43/ 2042 800F_80E4 ENET SWI IP Snooping function2 (HW_ENET_SWI_IPSNOOP2) 32 R/W 0000_0000h 29.9.44/ 2044 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1994 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800F_80E8 ENET SWI IP Snooping function3 (HW_ENET_SWI_IPSNOOP3) 32 R/W 0000_0000h 29.9.45/ 2045 800F_80EC ENET SWI IP Snooping function4 (HW_ENET_SWI_IPSNOOP4) 32 R/W 0000_0000h 29.9.46/ 2046 800F_80F0 ENET SWI IP Snooping function5 (HW_ENET_SWI_IPSNOOP5) 32 R/W 0000_0000h 29.9.47/ 2047 800F_80F4 ENET SWI IP Snooping function6 (HW_ENET_SWI_IPSNOOP6) 32 R/W 0000_0000h 29.9.48/ 2048 800F_80F8 ENET SWI IP Snooping function7 (HW_ENET_SWI_IPSNOOP7) 32 R/W 0000_0000h 29.9.49/ 2050 800F_80FC ENET SWI IP Snooping function8 (HW_ENET_SWI_IPSNOOP8) 32 R/W 0000_0000h 29.9.50/ 2051 800F_8100 ENET SWI Port 0 VLAN priority resolution map (HW_ENET_SWI_VLAN_PRIORITY0) 32 R/W 0000_0000h 29.9.51/ 2052 800F_8104 ENET SWI Port 1 VLAN priority resolution map (HW_ENET_SWI_VLAN_PRIORITY1) 32 R/W 0000_0000h 29.9.52/ 2053 800F_8108 ENET SWI Port 2 VLAN priority resolution map (HW_ENET_SWI_VLAN_PRIORITY2) 32 R/W 0000_0000h 29.9.53/ 2054 800F_8140 ENET SWI IPv4 and IPv6 priority resolution table programming (HW_ENET_SWI_IP_PRIORITY) 32 R/W 0000_0000h 29.9.54/ 2054 800F_8180 ENET SWI Port 0 Priority resolution configuration (HW_ENET_SWI_PRIORITY_CFG0) 32 R/W 0000_0000h 29.9.55/ 2056 800F_8184 ENET SWI Port 1 Priority resolution configuration (HW_ENET_SWI_PRIORITY_CFG1) 32 R/W 0000_0000h 29.9.56/ 2057 800F_8188 ENET SWI Port 2 Priority resolution configuration (HW_ENET_SWI_PRIORITY_CFG2) 32 R/W 0000_0000h 29.9.57/ 2058 800F_8200 ENET SWI Port 0 VLAN-ID field for VLAN input manipulation function (HW_ENET_SWI_SYSTEM_TAGINFO0) 32 R/W 0000_0000h 29.9.58/ 2060 800F_8204 ENET SWI Port 1 VLAN-ID field for VLAN input manipulation function (HW_ENET_SWI_SYSTEM_TAGINFO1) 32 R/W 0000_0000h 29.9.59/ 2060 800F_8208 ENET SWI Port 2 VLAN-ID field for VLAN input manipulation function (HW_ENET_SWI_SYSTEM_TAGINFO2) 32 R/W 0000_0000h 29.9.60/ 2061 800F_8280 ENET SWI VLAN domain resolution entry 0. (HW_ENET_SWI_VLAN_RES_TABLE_0) 32 R/W 0000_0000h 29.9.61/ 2061 800F_8284 ENET SWI VLAN domain resolution entry 1. (HW_ENET_SWI_VLAN_RES_TABLE_1) 32 R/W 0000_0000h 29.9.62/ 2062 800F_8288 ENET SWI VLAN domain resolution entry 2. (HW_ENET_SWI_VLAN_RES_TABLE_2) 32 R/W 0000_0000h 29.9.63/ 2063 800F_828C ENET SWI VLAN domain resolution entry 3. (HW_ENET_SWI_VLAN_RES_TABLE_3) 32 R/W 0000_0000h 29.9.64/ 2064 800F_8290 ENET SWI VLAN domain resolution entry 4. (HW_ENET_SWI_VLAN_RES_TABLE_4) 32 R/W 0000_0000h 29.9.65/ 2065 800F_8294 ENET SWI VLAN domain resolution entry 5. (HW_ENET_SWI_VLAN_RES_TABLE_5) 32 R/W 0000_0000h 29.9.66/ 2066 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1995 Programmable Registers HW_ENET_SWI memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800F_8298 ENET SWI VLAN domain resolution entry 6. (HW_ENET_SWI_VLAN_RES_TABLE_6) 32 R/W 0000_0000h 29.9.67/ 2067 800F_829C ENET SWI VLAN domain resolution entry 7. (HW_ENET_SWI_VLAN_RES_TABLE_7) 32 R/W 0000_0000h 29.9.68/ 2068 800F_82A0 ENET SWI VLAN domain resolution entry 8. (HW_ENET_SWI_VLAN_RES_TABLE_8) 32 R/W 0000_0000h 29.9.69/ 2069 800F_82A4 ENET SWI VLAN domain resolution entry 9. (HW_ENET_SWI_VLAN_RES_TABLE_9) 32 R/W 0000_0000h 29.9.70/ 2070 800F_82A8 ENET SWI VLAN domain resolution entry 10. (HW_ENET_SWI_VLAN_RES_TABLE_10) 32 R/W 0000_0000h 29.9.71/ 2071 800F_82AC ENET SWI VLAN domain resolution entry 11. (HW_ENET_SWI_VLAN_RES_TABLE_11) 32 R/W 0000_0000h 29.9.72/ 2072 800F_82B0 ENET SWI VLAN domain resolution entry 12. (HW_ENET_SWI_VLAN_RES_TABLE_12) 32 R/W 0000_0000h 29.9.73/ 2073 800F_82B4 ENET SWI VLAN domain resolution entry 13. (HW_ENET_SWI_VLAN_RES_TABLE_13) 32 R/W 0000_0000h 29.9.74/ 2074 800F_82B8 ENET SWI VLAN domain resolution entry 14. (HW_ENET_SWI_VLAN_RES_TABLE_14) 32 R/W 0000_0000h 29.9.75/ 2075 800F_82BC ENET SWI VLAN domain resolution entry 15. (HW_ENET_SWI_VLAN_RES_TABLE_15) 32 R/W 0000_0000h 29.9.76/ 2076 800F_82C0 ENET SWI VLAN domain resolution entry 16. (HW_ENET_SWI_VLAN_RES_TABLE_16) 32 R/W 0000_0000h 29.9.77/ 2077 800F_82C4 ENET SWI VLAN domain resolution entry 17. (HW_ENET_SWI_VLAN_RES_TABLE_17) 32 R/W 0000_0000h 29.9.78/ 2078 800F_82C8 ENET SWI VLAN domain resolution entry 18. (HW_ENET_SWI_VLAN_RES_TABLE_18) 32 R/W 0000_0000h 29.9.79/ 2079 800F_82CC ENET SWI VLAN domain resolution entry 19. (HW_ENET_SWI_VLAN_RES_TABLE_19) 32 R/W 0000_0000h 29.9.80/ 2080 800F_82D0 ENET SWI VLAN domain resolution entry 20. (HW_ENET_SWI_VLAN_RES_TABLE_20) 32 R/W 0000_0000h 29.9.81/ 2081 800F_82D4 ENET SWI VLAN domain resolution entry 21. (HW_ENET_SWI_VLAN_RES_TABLE_21) 32 R/W 0000_0000h 29.9.82/ 2082 800F_82D8 ENET SWI VLAN domain resolution entry 22. (HW_ENET_SWI_VLAN_RES_TABLE_22) 32 R/W 0000_0000h 29.9.83/ 2083 800F_82DC ENET SWI VLAN domain resolution entry 23. (HW_ENET_SWI_VLAN_RES_TABLE_23) 32 R/W 0000_0000h 29.9.84/ 2084 800F_82E0 ENET SWI VLAN domain resolution entry 24. (HW_ENET_SWI_VLAN_RES_TABLE_24) 32 R/W 0000_0000h 29.9.85/ 2085 800F_82E4 ENET SWI VLAN domain resolution entry 25. (HW_ENET_SWI_VLAN_RES_TABLE_25) 32 R/W 0000_0000h 29.9.86/ 2086 800F_82E8 ENET SWI VLAN domain resolution entry 26. (HW_ENET_SWI_VLAN_RES_TABLE_26) 32 R/W 0000_0000h 29.9.87/ 2087 800F_82EC ENET SWI VLAN domain resolution entry 27. (HW_ENET_SWI_VLAN_RES_TABLE_27) 32 R/W 0000_0000h 29.9.88/ 2088 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1996 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 800F_82F0 ENET SWI VLAN domain resolution entry 28. (HW_ENET_SWI_VLAN_RES_TABLE_28) 32 R/W 0000_0000h 29.9.89/ 2089 800F_82F4 ENET SWI VLAN domain resolution entry 29. (HW_ENET_SWI_VLAN_RES_TABLE_29) 32 R/W 0000_0000h 29.9.90/ 2090 800F_82F8 ENET SWI VLAN domain resolution entry 30. (HW_ENET_SWI_VLAN_RES_TABLE_30) 32 R/W 0000_0000h 29.9.91/ 2091 800F_82FC ENET SWI VLAN domain resolution entry 31. (HW_ENET_SWI_VLAN_RES_TABLE_31) 32 R/W 0000_0000h 29.9.92/ 2092 800F_8300 ENET SWI Total number of incoming frames processed (HW_ENET_SWI_TOTAL_DISC) 32 R 0000_0000h 29.9.93/ 2093 800F_8304 ENET SWI Sum of bytes of frames counted in TOTAL_DISC (HW_ENET_SWI_TOTAL_BYT_DISC) 32 R 0000_0000h 29.9.94/ 2094 800F_8308 ENET SWI Total number of incoming frames processed (HW_ENET_SWI_TOTAL_FRM) 32 R 0000_0000h 29.9.95/ 2094 800F_830C ENET SWI Sum of bytes of frames counted in TOTAL_FRM (HW_ENET_SWI_TOTAL_BYT_FRM) 32 R 0000_0000h 29.9.96/ 2094 800F_8310 ENET SWI Port 0 Outgoing frames discarded due to output Queue congestion (HW_ENET_SWI_ODISC0) 32 R 0000_0000h 29.9.97/ 2095 800F_8314 ENET SWI Port 0 incoming frames discarded due to mismatching or missing VLAN id (HW_ENET_SWI_IDISC_VLAN0) 32 R 0000_0000h 29.9.98/ 2095 800F_8318 ENET SWI Port 0 incoming frames discarded due to missing vlan tag (HW_ENET_SWI_IDISC_UNTAGGED0) 32 R 0000_0000h 29.9.99/ 2096 ENET SWI Port 0 incoming frames discarded (after learning) 800F_831C as port is configured in blocking mode (HW_ENET_SWI_IDISC_BLOCKED0) 32 R 0000_0000h 29.9.100/ 2096 800F_8320 ENET SWI Port 1 Outgoing frames discarded due to output Queue congestion (HW_ENET_SWI_ODISC1) 32 R 0000_0000h 29.9.101/ 2097 800F_8324 ENET SWI Port 1 incoming frames discarded due to mismatching or missing VLAN id (HW_ENET_SWI_IDISC_VLAN1) 32 R 0000_0000h 29.9.102/ 2097 800F_8328 ENET SWI Port 1 incoming frames discarded due to missing vlan tag (HW_ENET_SWI_IDISC_UNTAGGED1) 32 R 0000_0000h 29.9.103/ 2097 ENET SWI Port 1 incoming frames discarded (after learning) 800F_832C as port is configured in blocking mode (HW_ENET_SWI_IDISC_BLOCKED1) 32 R 0000_0000h 29.9.104/ 2098 800F_8330 ENET SWI Port 2 Outgoing frames discarded due to output Queue congestion (HW_ENET_SWI_ODISC2) 32 R 0000_0000h 29.9.105/ 2098 800F_8334 ENET SWI Port 2 incoming frames discarded due to mismatching or missing VLAN id (HW_ENET_SWI_IDISC_VLAN2) 32 R 0000_0000h 29.9.106/ 2099 800F_8338 ENET SWI Port 2 incoming frames discarded due to missing vlan tag (HW_ENET_SWI_IDISC_UNTAGGED2) 32 R 0000_0000h 29.9.107/ 2099 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1997 Programmable Registers HW_ENET_SWI memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page ENET SWI Port 2 incoming frames discarded (after learning) 800F_833C as port is configured in blocking mod (HW_ENET_SWI_IDISC_BLOCKED2) 32 R 0000_0000h 29.9.108/ 2100 800F_8400 ENET SWI Interrupt Event Register (HW_ENET_SWI_EIR) 32 R/W 0000_0020h 29.9.109/ 2100 800F_8404 ENET SWI Interrupt Mask Register (HW_ENET_SWI_EIMR) 32 R/W 0000_0000h 29.9.110/ 2101 800F_8408 ENET SWI Pointer to Receive Descriptor Ring (HW_ENET_SWI_ERDSR) 32 R/W 0000_0000h 29.9.111/ 2103 800F_840C ENET SWI Pointer to Transmit Descriptor Ring (HW_ENET_SWI_ETDSR) 32 R/W 0000_0000h 29.9.112/ 2104 800F_8410 ENET SWI Maximum Receive Buffer Size (HW_ENET_SWI_EMRBR) 32 R/W 0000_0000h 29.9.113/ 2104 800F_8414 ENET SWI Receive Descriptor Active Register (HW_ENET_SWI_RDAR) 32 R/W 0000_0000h 29.9.114/ 2105 800F_8418 ENET SWI Transmit Descriptor Active Register (HW_ENET_SWI_TDAR) 32 R/W 0000_0000h 29.9.115/ 2105 800F_8500 ENET SWI Learning Records A (0) and B (1) (HW_ENET_SWI_LRN_REC_0) 32 R 0000_0000h 29.9.116/ 2105 800F_8504 ENET SWI Learning Record B(1) (HW_ENET_SWI_LRN_REC_1) 32 R 0000_0000h 29.9.117/ 2106 800F_8508 ENET SWI Learning data available status. (HW_ENET_SWI_LRN_STATUS) 32 R 0000_0000h 29.9.118/ 2107 8010_7FFC ENET SWI lookup MAC address memory end (HW_ENET_SWI_LOOKUP_MEMORY_END) 32 R/W 0000_0000h 29.9.119/ 2108 29.9.1 ENET SWI revision (HW_ENET_SWI_REVISION) Address: 800F_8000h base + 0h offset = 800F_8000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 CUSTOMER_REVISION R 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 CORE_REVISION W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 HW_ENET_SWI_REVISION field descriptions Field 31-16 CUSTOMER_ REVISION Description Customer Revision Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 1998 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_REVISION field descriptions (continued) Field Description CORE_ REVISION Core Revision 29.9.2 ENET SWI lookup MAC address memory start (HW_ENET_SWI_LOOKUP_MEMORY_START) Address: 800F_8000h base + 0h offset = 800F_8000h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMORY_DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_LOOKUP_MEMORY_START field descriptions Field Description MEMORY_DATA Memroy cell. 29.9.3 ENET SWI Scratch Register (HW_ENET_SWI_SCRATCH) The Scratch Register provides a memory location to test the register access. It returns all data written to it in inverted form. Address: 800F_8000h base + 4h offset = 800F_8004h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_SCRATCH field descriptions Field SCRATCH Description The Scratch Register provides a memory location to test the register access. It returns all data written to it in inverted form. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 1999 Programmable Registers 29.9.4 ENET SWI Port Enable Bits. (HW_ENET_SWI_PORT_ENA) Port Enable Bits. Two bits per port. The transmit and receive direction for each port can be independently enabled. When the transmit direction is enabled a frame can be forwarded to the port. When disabled, all frames forwarded to the port are discarded. When the receive direction is enabled the port is selected and a frame is accepted if it indicates data available. If the receive direction is disabled the input is ignored and never selected for frame reception. Address: 800F_8000h base + 8h offset = 800F_8008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 RSRVD1 ENA_RECEIVE_2 ENA_RECEIVE_1 ENA_RECEIVE_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENA_TRANSMIT_1 ENA_TRANSMIT_0 Bit 0 0 0 0 0 0 0 0 0 RSRVD0 R W Reset 16 0 W Reset 17 ENA_TRANSMIT_2 R 18 0 0 0 0 0 0 0 HW_ENET_SWI_PORT_ENA field descriptions Field 31-19 RSRVD1 Description Reserved bits. Write as 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2000 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_PORT_ENA field descriptions (continued) Field Description 18 enable receive on port 2. ENA_RECEIVE_ 2 17 enable receive on port 1. ENA_RECEIVE_ 1 16 enable receive on port 0. ENA_RECEIVE_ 0 15-3 RSRVD0 Reserved bits. Write as 0. 2 ENA_ TRANSMIT_2 enable transmit on port 2. 1 ENA_ TRANSMIT_1 enable transmit on port 1. 0 ENA_ TRANSMIT_0 enable transmit on port 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2001 Programmable Registers 29.9.5 ENET SWI Verify VLAN domain. (HW_ENET_SWI_VLAN_VERIFY) Address: 800F_8000h base + 10h offset = 800F_8010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 DISCARD_P2 DISCARD_P1 DISCARD_P0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VLAN_VERIFY_2 VLAN_VERIFY_1 VLAN_VERIFY_0 R 0 0 0 0 0 0 0 0 0 W Reset Bit RSRVD0 R W Reset 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_VERIFY field descriptions Field 31-19 RSRVD1 Description Reserved bits. Write as 0. 18 DISCARD_P2 Discard unknown on port 2. 17 DISCARD_P1 Discard unknown on port 1. When set, and a frame is received with a VLAN ID that is unknown, or has no VLAN tag, the frame is discarded and not forwarded (i.e. the default bcast is ignored). When set, and a frame is received with a VLAN ID that is unknown, or has no VLAN tag, the frame is discarded and not forwarded (i.e. the default bcast is ignored). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2002 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_VLAN_VERIFY field descriptions (continued) Field Description 16 DISCARD_P0 Discard unknown on port 0. When set, and a frame is received with a VLAN ID that is unknown, or has no VLAN tag, the frame is discarded and not forwarded (i.e. the default bcast is ignored). 15-3 RSRVD0 Reserved bits. Write as 0. 2 Verify VLAN domain on port 2. VLAN_VERIFY_2 When enabled (Bit=1) a frame is accepted from the port as valid only when the input and output ports are members of the VLAN domain of the frame. When disabled (Bit=0) frames are routed to the output port without VLAN domain checking. 1 Verify VLAN domain on port 1. VLAN_VERIFY_1 When enabled (Bit=1) a frame is accepted from the port as valid only when the input and output ports are members of the VLAN domain of the frame. When disabled (Bit=0) frames are routed to the output port without VLAN domain checking. 0 Verify VLAN domain on port 0. VLAN_VERIFY_0 When enabled (Bit=1) a frame is accepted from the port as valid only when the input and output ports are members of the VLAN domain of the frame. When disabled (Bit=0) frames are routed to the output port without VLAN domain checking. 29.9.6 ENET SWI Default broadcast resolution. (HW_ENET_SWI_BCAST_DEFAULT_MASK) For broadcast/flooding resolution, the default output port list Address: 800F_8000h base + 14h offset = 800F_8014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2003 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 2 1 0 BCAST_DEFAULT_MASK_0 14 BCAST_DEFAULT_MASK_1 15 Bit BCAST_DEFAULT_MASK_2 Programmable Registers 0 0 0 HW_ENET_SWI_BCAST_DEFAULT_MASK field descriptions Field 31-3 RSRVD0 Description Reserved bits. Write as 0. 2 BCAST_ DEFAULT_ MASK_2 port 2 1 BCAST_ DEFAULT_ MASK_1 port 1 0 BCAST_ DEFAULT_ MASK_0 port 0 29.9.7 ENET SWI Default multicast resolution. (HW_ENET_SWI_MCAST_DEFAULT_MASK) Used for broadcast/flooding resolution. The default output port list used instead of the BCST_DEFAULT_MASK, when the received frame carries a multicast address. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2004 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) Address: 800F_8000h base + 18h offset = 800F_8018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MCAST_DEFAULT_MASK_0 Bit 0 MCAST_DEFAULT_MASK_1 Reset MCAST_DEFAULT_MASK_2 W 0 0 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 HW_ENET_SWI_MCAST_DEFAULT_MASK field descriptions Field 31-3 RSRVD0 Description Reserved bits. Write as 0. 2 MCAST_ DEFAULT_ MASK_2 port 2 1 MCAST_ DEFAULT_ MASK_1 port 1 0 MCAST_ DEFAULT_ MASK_0 port 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2005 Programmable Registers 29.9.8 ENET SWI Define port in blocking state and enable or disable learning. (HW_ENET_SWI_INPUT_LEARN_BLOCK) When blocking is enabled for a port (Bit=1) only Bridge Protocol data units are accepted on that input, all other frames are discarded. When learning is disabled for a port (Bit=1), only Bridge Protocol Data Unit frames will be learned. Other frames will be ignored for learning. Both functions operate independently from each other. Address: 800F_8000h base + 1Ch offset = 800F_801Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 RSRVD1 LEARNING_DIS_P2 LEARNING_DI_P1 LEARNING_DI_P0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BLOCKING_ENA_P1 BLOCKING_ENA_P0 Bit 0 0 0 0 0 0 0 0 0 RSRVD0 R W Reset 16 0 W Reset 17 BLOCKING_ENA_P2 R 18 0 0 0 0 0 0 0 HW_ENET_SWI_INPUT_LEARN_BLOCK field descriptions Field 31-19 RSRVD1 Description Reserved bits. Write as 0. 18 disable learning on port 2. LEARNING_DIS_ P2 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2006 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_INPUT_LEARN_BLOCK field descriptions (continued) Field Description 17 disable learning on port 1. LEARNING_DI_ P1 16 disable learning on port 0. LEARNING_DI_ P0 15-3 RSRVD0 Reserved bits. Write as 0. 2 BLOCKING_ ENA_P2 enable blocking on port 2. 1 BLOCKING_ ENA_P1 enable blocking on port 1. 0 BLOCKING_ ENA_P0 enable blocking on port 0. 29.9.9 ENET SWI Bridge Management Port Configuration. (HW_ENET_SWI_MGMT_CONFIG) Enables and defines the management port that receives Bridge Protocol Frames Address: 800F_8000h base + 20h offset = 800F_8020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD2 R PORTMASK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2007 12 11 10 9 8 7 6 5 4 RSRVD0 13 MESSAGE_TRANSMITTED 14 ENABLE 15 Bit DISCARD Programmable Registers 0 0 0 0 RSRVD1 R PRIORITY 3 2 1 0 0 0 PORT W Reset 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_MGMT_CONFIG field descriptions Field 31-19 RSRVD2 Description Reserved bits. Write as 0. 18-16 PORTMASK Portmask for transmission of BPDU frames as defined in 5.10.6.4 page 44. When the management port transmits a BPDU frame to the switch, it is forwarded to all ports in this portmask (bit16=port0, bit17=port1, bit 18=port2). 15-13 PRIORITY Priority to use for transmitted management frames. Used to e.g. put a management frame in a high-priority output queue for fast delivery. 12-8 RSRVD1 Reserved bits. Write as 0. 7 DISCARD If set, BPDU frames are discarded always. Setting has no effect, when the enable bit is set. 6 ENABLE If set, all BPDU frames are forwarded exclusively to the management port specified in bits 3:0. If cleared, BPDU frames are forwarded as any other frame, or discarded if the discard bit is set. 5 Set (latched) when a BPDU frame as defined in 5.10.6.4 page 44 was transmitted from the management MESSAGE_ port to any output port. Bit is reset by writing into the register. TRANSMITTED 4 RSRVD0 PORT Reserved bits. Write as 0. The Port number of the port that should act as a management port. Relevant to all functions that forward frames to the management port (i.e. BPDU processing, snooping). Note: It must be set 0 in this switch configuration (Port 0 to DMA0 is the management port). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2008 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.9.10 ENET SWI Defines several global configuration settings. (HW_ENET_SWI_MODE_CONFIG) Defines several global configuration settings. Address: 800F_8000h base + 24h offset = 800F_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 STATSRESET R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWITCH_RESET 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 STOP_EN 0 CRC_TRANSPARENT Bit 0 P0BUF_CUT_THROUGH Reset SWITCH_EN W 0 0 0 RSRVD0 0 0 0 HW_ENET_SWI_MODE_CONFIG field descriptions Field 31 STATSRESET Description Reset Statistics Counters Command. When set during a write, all statistics counters are cleared. When set, all other bits are ignored and do not influence the currently stored value in the register (i.e. it is not necessary to read/preserve the register contents prior to writing this bit). 30-10 RSRVD1 Reserved bits. Write as 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2009 Programmable Registers HW_ENET_SWI_MODE_CONFIG field descriptions (continued) Field 9 P0BUF_CUT_ THROUGH Description Enable Port0 input buffer cut-through mode. Cut-through mode may be used for allowing jumbo frames to be transferred. When cleared (0, default) the input buffer operates in store/forward mode, which is the recommended mode of operation. 8 When enabled (1) the MAC ports are expected to process frames to/from the switch including CRC. CRC_ Frames from a MAC port to a MAC port will then have their respective ff_rx_crc_fwd1/2 pin (wired to TRANSPARENT MAC's ff_tx_crc_fwd) asserted, indicating that no CRC should be appended. However, even when enabled, the DMA0 port is not expected to provide frames with crc: Frames from port 0 (DMA0 transmit) are always forwarded with the crc option as defined by the input ff_tx_crc_fwd0, independent of the crc_transparent setting. This means, if the DMA0 port will never transmit frames with CRC, ff_tx_crc_fwd0 can be wired to permanently 0. Note that the MAC configuration bit RCR(CRC_FWD) must be set to ensure the MAC forwards received frames with CRC to the switch. When disabled (0, default) the output pins ff_rx_crc_fwd1/2 to the MACs are always 0 to ensure a CRC is appended to outgoing frames no matter from which port they were received. DMA0 still can influence the crc append through its ff_tx_crc_fwd0 input pin if required. Note: The ff_tx_crc_fwd0 input to the switch must be valid throughout the complete frame (from sop to eop). This is in contrast to the MAC definition for this signal, which requires validity during eop only. 7 STOP_EN 6-2 RSRVD0 1 SWITCH_EN Controls toplevel output pin stop_en. No internal function. Reserved bits. Write as 0. Controls toplevel output pin switch_en. When deasserted (0), all DMA registers are cleared. 0 Controls toplevel output pin switch_reset. SWITCH_RESET No internal function. 29.9.11 ENET SWI Define behavior of VLAN input manipulation function (HW_ENET_SWI_VLAN_IN_MODE) Define behavior of VLAN input manipulation function, if such a function is present on an input port. Each input port can operate in one of four modes individually defining 2 bits per port: "00": Mode 1, Single Tag passthrough "01": Mode 2, Single Tag overwrite "10": Mode 3, Double Tag passthrough "11": Mode 4, Double Tag overwrite The settings have effect only, when enabled by setting the corresponding bit in VLAN_IN_MODE_ENA below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2010 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) Address: 800F_8000h base + 28h offset = 800F_8028h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R VLAN_IN_ MODE_2 W Reset 0 0 0 0 0 0 0 0 0 0 0 VLAN_IN_ MODE_1 0 0 0 VLAN_IN_ MODE_0 0 0 HW_ENET_SWI_VLAN_IN_MODE field descriptions Field Description 31-6 RSRVD0 Reserved bits. Write as 0. 5-4 VLAN_IN_ MODE_2 port 2. 3-2 VLAN_IN_ MODE_1 port 1. VLAN_IN_ MODE_0 port 0. 29.9.12 ENET SWI Define behavior of VLAN output manipulation function (HW_ENET_SWI_VLAN_OUT_MODE) Define behavior of VLAN output manipulation function, if such a function is present on an output port. Each output port can operate in one of three modes individually defining 2 bits per port: "00": no output manipulation "01": Mode 1, Strip Mode "10": Mode 2, Tag Thru "11": Mode 3, Transparent Address: 800F_8000h base + 2Ch offset = 800F_802Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R VLAN_OUT_ VLAN_OUT_ VLAN_OUT_ MODE_2 MODE_1 MODE_0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2011 Programmable Registers HW_ENET_SWI_VLAN_OUT_MODE field descriptions Field Description 31-6 RSRVD0 Reserved bits. Write as 0. 5-4 VLAN_OUT_ MODE_2 port 2. 3-2 VLAN_OUT_ MODE_1 port 1. VLAN_OUT_ MODE_0 port 0. 29.9.13 ENET SWI Enable the input processing according to the VLAN_IN_MODE for a port (HW_ENET_SWI_VLAN_IN_MODE_ENA) Enable the input processing according to the VLAN_IN_MODE for a port (1 bit per port). When disabled (bit=0) the VLAN_IN_MODE setting for that port has no effect and the frames are processed unmodified. Address: 800F_8000h base + 30h offset = 800F_8030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2012 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 2 1 0 VLAN_IN_MODE_ENA_0 14 VLAN_IN_MODE_ENA_1 15 Bit VLAN_IN_MODE_ENA_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 HW_ENET_SWI_VLAN_IN_MODE_ENA field descriptions Field Description 31-3 RSRVD0 Reserved bits. Write as 0. 2 VLAN_IN_ MODE_ENA_2 port 2. 1 VLAN_IN_ MODE_ENA_1 port 1. 0 VLAN_IN_ MODE_ENA_0 port 0. 29.9.14 ENET SWI The VLAN type field value to expect to identify a VLAN tagged frame. (HW_ENET_SWI_VLAN_TAG_ID) The VLAN type field value to expect to identify a VLAN tagged frame. A valid 802.1Q VLAN tagged frame must use the value 0x8100. Address: 800F_8000h base + 34h offset = 800F_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD0 R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 SWI_VLAN_TAG_ID W Reset 10 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2013 Programmable Registers HW_ENET_SWI_VLAN_TAG_ID field descriptions Field Description 31-16 RSRVD0 Reserved bits. Write as 0. SWI_VLAN_ TAG_ID Defaults to 0x8100 upon reset. 29.9.15 ENET SWI Port Mirroring configuration. (HW_ENET_SWI_MIRROR_CONTROL) Define mirror port and filtering conditions. Address: 800F_8000h base + 40h offset = 800F_8040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ING_DA_MATCH ING_SA_MATCH EG_MAP_ENABLE ING_MAP_ENABLE MIRROR_ENABLE Bit 0 EG_SA_MATCH Reset EG_DA_MATCH W 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 PORTX 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2014 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_MIRROR_CONTROL field descriptions Field 31-11 RSRVD0 Description Reserved bits. Write as 0. 10 If set, only frames transmitted on an egress port with a destination address matching the value EG_DA_MATCH programmed in register MIRROR_EDST are mirrored. Other frames are not mirrored. Note: if the egress map is not enabled (eg_map_enable=0) then any frame with a matching destination address will be mirrored. 9 If set, only frames transmitted on an egress port with a source address matching the value programmed in EG_SA_MATCH register MIRROR_ESRC are mirrored. Other frames are not mirrored. Note: if the egress map is not enabled (eg_map_enable=0) then any frame with a matching source address will be mirrored. 8 If set, only frames received on an ingress port with a destination address matching the value programmed ING_DA_MATCH in register MIRROR_IDST are mirrored. Other frames are not mirrored. Note: if the ingress map is not enabled (ing_map_enable=0) then any frame with a matching destination address will be mirrored. 7 If set, only frames received on an ingress port with a source address matching the value programmed in ING_SA_MATCH register MIRROR_ISRC are mirrored. Other frames are not mirrored. Note: if the ingress map is not enabled (ing_map_enable=0) then any frame with a matching source address will be mirrored. 6 EG_MAP_ ENABLE If set the egress map is enabled (MIRROR_EG_MAP). A frame forwarded to an output port that has a bit set in the egress map will be mirrored. 5 ING_MAP_ ENABLE If set the ingress map is enabled (MIRROR_ING_MAP). A frame received on an ingress port that has a bit set in the ingress map will be mirrored. 4 MIRROR_ ENABLE Enable (1) / Disable (0) mirroring. PORTX If cleared, the egress port map has no effect. If cleared, the ingress port map has no effect. The port number of the port that should act as the mirror port and receive all mirrored frames. 29.9.16 ENET SWI Port Mirroring Egress port definitions. (HW_ENET_SWI_MIRROR_EG_MAP) 1 Bit per Port. If enabled (Bit=1) frames destined to the port(s) are mirrored to the mirror port i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2015 Programmable Registers Address: 800F_8000h base + 44h offset = 800F_8044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIRROR_EG_MAP_0 Bit 0 MIRROR_EG_MAP_1 Reset MIRROR_EG_MAP_2 W 0 0 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_EG_MAP field descriptions Field 31-3 RSRVD0 Description Reserved bits. Write as 0. 2 MIRROR_EG_ MAP_2 port 2. 1 MIRROR_EG_ MAP_1 port 1. 0 MIRROR_EG_ MAP_0 port 0. 29.9.17 ENET SWI Port Mirroring Ingress port definitions. (HW_ENET_SWI_MIRROR_ING_MAP) 1 Bit per Port. If enabled (Bit=1) frames from the port(s) are mirrored on the mirror port i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2016 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) Address: 800F_8000h base + 48h offset = 800F_8048h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MIRROR_ING_MAP_0 Bit 0 MIRROR_ING_MAP_1 Reset MIRROR_ING_MAP_2 W 0 0 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_ING_MAP field descriptions Field 31-3 RSRVD0 Description Reserved bits. Write as 0. 2 port 2. MIRROR_ING_ MAP_2 1 port 1. MIRROR_ING_ MAP_1 0 port 0. MIRROR_ING_ MAP_0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2017 Programmable Registers 29.9.18 ENET SWI Ingress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ISRC_0) Address: 800F_8000h base + 4Ch offset = 800F_804Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIRROR_ISRC_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_ISRC_0 field descriptions Field Description MIRROR_ISRC_ First 4 bytes of address. 0 First byte of MAC address is 7:0, .. , 4th byte is 31:24. 29.9.19 ENET SWI Ingress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ISRC_1) Address: 800F_8000h base + 50h offset = 800F_8050h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD0 R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 MIRROR_ISRC_1 W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_ISRC_1 field descriptions Field 31-16 RSRVD0 Description Reserved bits. Write as 0. MIRROR_ISRC_ Last 2 bytes of address. 5th Byte in 7:0 and 6th byte in 15:8 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2018 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.9.20 ENET SWI Ingress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_IDST_0) Address: 800F_8000h base + 54h offset = 800F_8054h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIRROR_IDST_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_IDST_0 field descriptions Field Description MIRROR_IDST_ First 4 bytes of address (as ISRC_0). 0 29.9.21 ENET SWI Ingress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_IDST_1) Address: 800F_8000h base + 58h offset = 800F_8058h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD0 R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 MIRROR_IDST_1 W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_IDST_1 field descriptions Field 31-16 RSRVD0 Description Reserved bits. Write as 0. MIRROR_IDST_ Last 2 bytes of address (as ISRC_1). 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2019 Programmable Registers 29.9.22 ENET SWI Egress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ESRC_0) Address: 800F_8000h base + 5Ch offset = 800F_805Ch Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIRROR_ESRC_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_ESRC_0 field descriptions Field Description MIRROR_ ESRC_0 First 4 bytes of address (as ISRC_0). 29.9.23 ENET SWI Egress Source MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_ESRC_1) Address: 800F_8000h base + 60h offset = 800F_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD0 R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 MIRROR_ESRC_1 W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_ESRC_1 field descriptions Field Description 31-16 RSRVD0 Reserved bits. Write as 0. MIRROR_ ESRC_1 Last 2 bytes of address (as ISRC_1). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2020 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.9.24 ENET SWI Egress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_EDST_0) Address: 800F_8000h base + 64h offset = 800F_8064h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIRROR_ESRC_0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_EDST_0 field descriptions Field Description MIRROR_ ESRC_0 First 4 bytes of address (as ISRC_0). 29.9.25 ENET SWI Egress Destination MAC Address for Mirror filtering. (HW_ENET_SWI_MIRROR_EDST_1) Address: 800F_8000h base + 68h offset = 800F_8068h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD0 R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 MIRROR_ESRC_1 W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_EDST_1 field descriptions Field Description 31-16 RSRVD0 Reserved bits. Write as 0. MIRROR_ ESRC_1 Last 2 bytes of address (as ISRC_1). 29.9.26 ENET SWI Count Value for Mirror filtering. (HW_ENET_SWI_MIRROR_CNT) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2021 Programmable Registers Every nth frame is forwarded to the mirror port if enabled. A value of 0 or 1 means every frame. Valid values are 0..255. Note: If the egress filtering port map is active, every forwarded frame is considered. Otherwise, frames are counted only if the mirroring decision indicated that the frame should be mirrored. Address: 800F_8000h base + 6Ch offset = 800F_806Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 MIRROR_CNT W Reset 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_MIRROR_CNT field descriptions Field Description 31-8 RSRVD0 Reserved bits. Write as 0. MIRROR_CNT ENET SWI Count Value for Mirror filtering. 29.9.27 ENET SWI Memory Manager Status. (HW_ENET_SWI_OQMGR_STATUS) All latched bits are cleared upon a write with any content to the register. Address: 800F_8000h base + 80h offset = 800F_8080h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 RSRVD2 R CELLS_AVAILABLE W Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2022 Freescale Semiconductor, Inc. 12 11 10 9 8 7 DEQUEUE_GRANT RSRVD1 R W Reset 0 0 0 0 0 6 0 0 0 0 1 5 4 RSRVD0 0 0 3 2 1 0 BUSY_INITIALIZING 13 NO_CELL_LATCH 14 MEM_FULL 15 Bit MEM_FULL_LATCH Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 1 0 1 0 HW_ENET_SWI_OQMGR_STATUS field descriptions Field 31-24 RSRVD2 23-16 CELLS_ AVAILABLE 15-7 RSRVD1 6 DEQUEUE_ GRANT 5-4 RSRVD0 Description Reserved bits. Write as 0. Real-time indication of currently available cells in memory. Reserved bits. Write as 0. Indication of if currently inputs are de-queued. Should be set always and is cleared when the memory becomes full (see also mem_full indication). Note: the bit is cleared upon reset, however set shortly after when the memory manager has completed initialization. Reserved bits. Write as 0. 3 MEM_FULL_ LATCH Latched version of mem_full. Is kept set even when mem_full is cleared again. 2 MEM_FULL Current memory full indication. The memory is full when less than the programmed minimum cell threshold is available in memory. This is not an error and the memory controller is working fine. The bit is cleared when the register is written. It just indicates that the switch does no longer serve its input ports to avoid memory overrun (no_cell error). 1 NO_CELL_ LATCH Set, when memory has exceeded the maximum available number of cells. The event is latched and the bit stays set if the event is no longer active. This is a fatal error and must never happen during operation. The minimum cells threshold must be increased if it happens. The bit is always set after reset (during initialization) and must be cleared when the busy initialization (see bit 0) indication is cleared. IMPORTANT NOTE: When this bit is set any time during operation (after initialization completed) the switch is in an inoperable state and must be reset completely to restore correct operation. If such an event happens, the QMGR_MINCELLS setting must be increased during initialization to avoid such situation. The bit is cleared when the register is written. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2023 Programmable Registers HW_ENET_SWI_OQMGR_STATUS field descriptions (continued) Field Description 0 BUSY_ INITIALIZING When set (1), Memory controller is initializing. The initialization is only preparing the internal data structures within the controller, it does not initialize the shared memory used for frame storage as this is not required. It is asserted after reset and stays set until the memory controller is ready to store frames. The switch must not be enabled before initialization of the memory controller has been completed. 29.9.28 ENET SWI Low Memory threshold. (HW_ENET_SWI_QMGR_MINCELLS) If less than the programmed number of cells is available in the memory, the switch will discard frames. The value should be chosen to give enough margin of at least 2 full sized frames. A memory overflow due to a too low threshold is a fatal error and may require a device reset. Address: 800F_8000h base + 84h offset = 800F_8084h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 QMGR_MINCELLS W Reset 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 HW_ENET_SWI_QMGR_MINCELLS field descriptions Field Description 31-8 RSRVD0 Reserved bits. Write as 0. QMGR_ MINCELLS Default: 9 = (2,3Kbyte). 29.9.29 ENET SWI Statistic providing the lowest number of free cells reached in memory (HW_ENET_SWI_QMGR_ST_MINCELLS) Statistic providing the lowest number of free cells reached in memory during operation since this statistics was last cleared. The value is reset to the maximum when a write to the register with any value is performed. Address: 800F_8000h base + 88h offset = 800F_8088h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QMGR_ST_MINCELLS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2024 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_QMGR_ST_MINCELLS field descriptions Field Description QMGR_ST_ MINCELLS ENET SWI Statistic providing the lowest number of free cells reached in memory 29.9.30 ENET SWI Port Congestion status (internal). (HW_ENET_SWI_QMGR_CONGEST_STAT) One bit per port. If any queue of a port is congested the bit is set. Address: 800F_8000h base + 8Ch offset = 800F_808Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2025 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 RSRVD0 R 2 1 0 QMGR_CONGEST_STAT_0 14 QMGR_CONGEST_STAT_1 15 Bit QMGR_CONGEST_STAT_2 Programmable Registers 0 0 0 W Reset 0 0 0 0 0 0 0 HW_ENET_SWI_QMGR_CONGEST_STAT field descriptions Field 31-3 RSRVD0 Description Reserved bits. Write as 0. 2 QMGR_ CONGEST_ STAT_2 port 2. 1 QMGR_ CONGEST_ STAT_1 port 1. 0 QMGR_ CONGEST_ STAT_0 port 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2026 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.9.31 ENET SWI Switch input and output interface status (internal). (HW_ENET_SWI_QMGR_IFACE_STAT) Address: 800F_8000h base + 90h offset = 800F_8090h 26 25 24 23 22 21 20 19 18 17 16 INPUT_0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUTPUT_0 28 INPUT_1 29 OUTPUT_1 30 INPUT_2 31 OUTPUT_2 Bit 0 0 0 0 0 0 1 1 1 RSRVD1 R W Reset Bit RSRVD0 R W Reset 0 0 0 0 0 0 0 HW_ENET_SWI_QMGR_IFACE_STAT field descriptions Field 31-19 RSRVD1 Description Reserved bits. Write as 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2027 Programmable Registers HW_ENET_SWI_QMGR_IFACE_STAT field descriptions (continued) Field Description 18 INPUT_2 input data available on port 2. 17 INPUT_1 input data available on port 1. 16 INPUT_0 input data available on port 0. 15-3 RSRVD0 Reserved bits. Write as 0. 2 OUTPUT_2 output ready to accept data on port 2. 1 OUTPUT_1 output ready to accept data on port 1. 0 OUTPUT_0 output ready to accept data on port 0. 29.9.32 ENET SWI Queue weights for each queue. (HW_ENET_SWI_QM_WEIGHTS) Defines the weight for the corresponding queue for all ports. A higher weight gives more priority to the queue. Valid values are between 0 and 30 for each queue setting. Setting all weights to 0 implements a strict priority scheme. Queue 3 is the highest priority queue. Address: 800F_8000h base + 94h offset = 800F_8094h Bit R 31 30 29 28 RSRVD3 0 0 0 26 25 24 0 0 0 0 23 22 21 20 RSRVD2 QUEUE_3 W Reset 27 0 0 0 0 19 18 17 16 0 0 0 14 13 12 RSRVD1 QUEUE_2 0 15 0 0 0 0 11 10 9 8 0 0 0 6 5 4 RSRVD0 QUEUE_1 0 7 0 0 0 0 3 2 1 0 QUEUE_0 0 0 0 0 0 HW_ENET_SWI_QM_WEIGHTS field descriptions Field 31-29 RSRVD3 28-24 QUEUE_3 23-21 RSRVD2 20-16 QUEUE_2 15-13 RSRVD1 Description Reserved bits. Write as 0. Queue 3 Reserved bits. Write as 0. Queue 2 Reserved bits. Write as 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2028 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_QM_WEIGHTS field descriptions (continued) Field Description 12-8 QUEUE_1 Queue 1 7-5 RSRVD0 Reserved bits. Write as 0. QUEUE_0 Queue 0 29.9.33 ENET SWI Define congestion threshold for Port0 backpressure. (HW_ENET_SWI_QMGR_MINCELLSP0) If the total output queues shared memory has less than this amount of free cells available, the switch stops serving the port0 input buffer. This will eventually fill up the input buffer deasserting ff_tx_rdy0. A value of 0 disables the function (no backpressure). Address: 800F_8000h base + 9Ch offset = 800F_809Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSRVD0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 QMGR_MINCELLSP0 W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 HW_ENET_SWI_QMGR_MINCELLSP0 field descriptions Field 31-8 RSRVD0 QMGR_ MINCELLSP0 Description Reserved bits. Write as 0. Mininum umber of free cells required. 29.9.34 ENET SWI Enable forced forwarding for a frame processed from port 0 (HW_ENET_SWI_FORCE_FWD_P0) Enable forced forwarding for a frame processed from port 0. The forced forwarding, if enabled, directs a frame from the processor to output port(s) ignoring any lookup resolution. Forced forwarding for Port 0 frames (i.e. frames transmitted from the DMA0 to the port 0 of the switch). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2029 Programmable Registers Address: 800F_8000h base + BCh offset = 800F_80BCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD1 R FORCE_ DESTINATIO N FORCE_ENABLE Bit 0 RSRVD0 Reset W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_FORCE_FWD_P0 field descriptions Field 31-4 RSRVD1 3-2 FORCE_ DESTINATION Description Reserved bits. Write as 0. When force is enabled, the bits define if the frame should be forwarded to the MAC at port 1 (bit2=1) and/ or the MAC at port 2 (bit(3=1)). Note, it is possible to forward to one or both MAC ports. If none of the bits is set, the force enable is ignored and the frame is processed normally. This can be used to implement a handshake, as the force enable bit will still be reset but no further action will happen. 1 RSRVD0 Reserved bits. Write as 0. 0 FORCE_ ENABLE When set (1) the next frame received from port 0 (the local DMA port) will be forwarded to the ports defined in the force destination port map. The bit is reset to 0 automatically when one frame from port 0 has been processed by the switch (i.e. has been read from the port 0 input buffer;). Therefore the bit must be set again as necessary. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2030 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.9.35 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP1) TCP/UDP Port number Snooping function configuration. Note: it is possible to set both the compare source/dest bits. The result is OR'ed, meaning if any of the fields match the compare value, the frame is processed as defined by the mode bits. Address: 800F_8000h base + C0h offset = 800F_80C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R DESTINATION_PORT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 MODE 0 0 ENABLE Bit 0 COMPARE_DEST Reset COMPARE_SOURCE W 0 HW_ENET_SWI_PORTSNOOP1 field descriptions Field Description 31-16 The 16-bit port number to compare within the TCP or UDP header of a frame. DESTINATION_ PORT 15-5 RSRVD0 Reserved bits. Write as 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2031 Programmable Registers HW_ENET_SWI_PORTSNOOP1 field descriptions (continued) Field Description 4 COMPARE_ SOURCE When set, the TCP or UDP source port number field within the frame is compared with the compare value provided in 31:16. 3 COMPARE_ DEST When set, the TCP or UDP destination port number field within the frame is compared with the compare value provided in 31:16. 2-1 MODE Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the TCP/UDP destination port value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the snooping function only if the enable bit is set. Otherwise the settings are ignored. When written with 0 will also force bits 3,4 to 0. Defaults to 0 upon reset. 29.9.36 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP2) TCP/UDP Port number Snooping function configuration. Note: it is possible to set both the compare source/dest bits. The result is OR'ed, meaning if any of the fields match the compare value, the frame is processed as defined by the mode bits. Address: 800F_8000h base + C4h offset = 800F_80C4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 R DESTINATION_PORT W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2032 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 4 3 0 0 2 1 MODE 0 0 0 ENABLE 14 COMPARE_DEST 15 Bit COMPARE_SOURCE Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 HW_ENET_SWI_PORTSNOOP2 field descriptions Field Description 31-16 The 16-bit port number to compare within the TCP or UDP header of a frame. DESTINATION_ PORT 15-5 RSRVD0 Reserved bits. Write as 0. 4 COMPARE_ SOURCE When set, the TCP or UDP source port number field within the frame is compared with the compare value provided in 31:16. 3 COMPARE_ DEST When set, the TCP or UDP destination port number field within the frame is compared with the compare value provided in 31:16. 2-1 MODE Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the TCP/UDP destination port value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the snooping function only if the enable bit is set. Otherwise the settings are ignored. When written with 0 will also force bits 3,4 to 0. Defaults to 0 upon reset. 29.9.37 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP3) TCP/UDP Port number Snooping function configuration. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2033 Programmable Registers Note: it is possible to set both the compare source/dest bits. The result is OR'ed, meaning if any of the fields match the compare value, the frame is processed as defined by the mode bits. Address: 800F_8000h base + C8h offset = 800F_80C8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R DESTINATION_PORT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 MODE 0 0 ENABLE Bit 0 COMPARE_DEST Reset COMPARE_SOURCE W 0 HW_ENET_SWI_PORTSNOOP3 field descriptions Field Description 31-16 The 16-bit port number to compare within the TCP or UDP header of a frame. DESTINATION_ PORT 15-5 RSRVD0 Reserved bits. Write as 0. 4 COMPARE_ SOURCE When set, the TCP or UDP source port number field within the frame is compared with the compare value provided in 31:16. 3 COMPARE_ DEST When set, the TCP or UDP destination port number field within the frame is compared with the compare value provided in 31:16. 2-1 MODE Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2034 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_PORTSNOOP3 field descriptions (continued) Field Description Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the TCP/UDP destination port value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the snooping function only if the enable bit is set. Otherwise the settings are ignored. When written with 0 will also force bits 3,4 to 0. Defaults to 0 upon reset. 29.9.38 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP4) TCP/UDP Port number Snooping function configuration. Note: it is possible to set both the compare source/dest bits. The result is OR'ed, meaning if any of the fields match the compare value, the frame is processed as defined by the mode bits. Address: 800F_8000h base + CCh offset = 800F_80CCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 R DESTINATION_PORT W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2035 13 12 11 10 9 8 7 6 5 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 4 3 0 0 2 1 MODE 0 0 0 ENABLE 14 COMPARE_DEST 15 Bit COMPARE_SOURCE Programmable Registers 0 HW_ENET_SWI_PORTSNOOP4 field descriptions Field Description 31-16 The 16-bit port number to compare within the TCP or UDP header of a frame. DESTINATION_ PORT 15-5 RSRVD0 Reserved bits. Write as 0. 4 COMPARE_ SOURCE When set, the TCP or UDP source port number field within the frame is compared with the compare value provided in 31:16. 3 COMPARE_ DEST When set, the TCP or UDP destination port number field within the frame is compared with the compare value provided in 31:16. 2-1 MODE Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the TCP/UDP destination port value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the snooping function only if the enable bit is set. Otherwise the settings are ignored. When written with 0 will also force bits 3,4 to 0. Defaults to 0 upon reset. 29.9.39 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP5) TCP/UDP Port number Snooping function configuration. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2036 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) Note: it is possible to set both the compare source/dest bits. The result is OR'ed, meaning if any of the fields match the compare value, the frame is processed as defined by the mode bits. Address: 800F_8000h base + D0h offset = 800F_80D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R DESTINATION_PORT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 MODE 0 0 ENABLE Bit 0 COMPARE_DEST Reset COMPARE_SOURCE W 0 HW_ENET_SWI_PORTSNOOP5 field descriptions Field Description 31-16 The 16-bit port number to compare within the TCP or UDP header of a frame. DESTINATION_ PORT 15-5 RSRVD0 Reserved bits. Write as 0. 4 COMPARE_ SOURCE When set, the TCP or UDP source port number field within the frame is compared with the compare value provided in 31:16. 3 COMPARE_ DEST When set, the TCP or UDP destination port number field within the frame is compared with the compare value provided in 31:16. 2-1 MODE Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2037 Programmable Registers HW_ENET_SWI_PORTSNOOP5 field descriptions (continued) Field Description Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the TCP/UDP destination port value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the snooping function only if the enable bit is set. Otherwise the settings are ignored. When written with 0 will also force bits 3,4 to 0. Defaults to 0 upon reset. 29.9.40 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP6) TCP/UDP Port number Snooping function configuration. Note: it is possible to set both the compare source/dest bits. The result is OR'ed, meaning if any of the fields match the compare value, the frame is processed as defined by the mode bits. Address: 800F_8000h base + D4h offset = 800F_80D4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 R DESTINATION_PORT W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2038 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 4 3 0 0 2 1 MODE 0 0 0 ENABLE 14 COMPARE_DEST 15 Bit COMPARE_SOURCE Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 HW_ENET_SWI_PORTSNOOP6 field descriptions Field Description 31-16 The 16-bit port number to compare within the TCP or UDP header of a frame. DESTINATION_ PORT 15-5 RSRVD0 Reserved bits. Write as 0. 4 COMPARE_ SOURCE When set, the TCP or UDP source port number field within the frame is compared with the compare value provided in 31:16. 3 COMPARE_ DEST When set, the TCP or UDP destination port number field within the frame is compared with the compare value provided in 31:16. 2-1 MODE Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the TCP/UDP destination port value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the snooping function only if the enable bit is set. Otherwise the settings are ignored. When written with 0 will also force bits 3,4 to 0. Defaults to 0 upon reset. 29.9.41 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP7) TCP/UDP Port number Snooping function configuration. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2039 Programmable Registers Note: it is possible to set both the compare source/dest bits. The result is OR'ed, meaning if any of the fields match the compare value, the frame is processed as defined by the mode bits. Address: 800F_8000h base + D8h offset = 800F_80D8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R DESTINATION_PORT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 MODE 0 0 ENABLE Bit 0 COMPARE_DEST Reset COMPARE_SOURCE W 0 HW_ENET_SWI_PORTSNOOP7 field descriptions Field Description 31-16 The 16-bit port number to compare within the TCP or UDP header of a frame. DESTINATION_ PORT 15-5 RSRVD0 Reserved bits. Write as 0. 4 COMPARE_ SOURCE When set, the TCP or UDP source port number field within the frame is compared with the compare value provided in 31:16. 3 COMPARE_ DEST When set, the TCP or UDP destination port number field within the frame is compared with the compare value provided in 31:16. 2-1 MODE Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2040 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_PORTSNOOP7 field descriptions (continued) Field Description Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the TCP/UDP destination port value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the snooping function only if the enable bit is set. Otherwise the settings are ignored. When written with 0 will also force bits 3,4 to 0. Defaults to 0 upon reset. 29.9.42 ENET SWI Port Snooping function. Eight independent entries are available. (HW_ENET_SWI_PORTSNOOP8) TCP/UDP Port number Snooping function configuration. Note: it is possible to set both the compare source/dest bits. The result is OR'ed, meaning if any of the fields match the compare value, the frame is processed as defined by the mode bits. Address: 800F_8000h base + DCh offset = 800F_80DCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 R DESTINATION_PORT W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2041 13 12 11 10 9 8 7 6 5 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 4 3 0 0 2 1 MODE 0 0 0 ENABLE 14 COMPARE_DEST 15 Bit COMPARE_SOURCE Programmable Registers 0 HW_ENET_SWI_PORTSNOOP8 field descriptions Field Description 31-16 The 16-bit port number to compare within the TCP or UDP header of a frame. DESTINATION_ PORT 15-5 RSRVD0 Reserved bits. Write as 0. 4 COMPARE_ SOURCE When set, the TCP or UDP source port number field within the frame is compared with the compare value provided in 31:16. 3 COMPARE_ DEST When set, the TCP or UDP destination port number field within the frame is compared with the compare value provided in 31:16. 2-1 MODE Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the TCP/UDP destination port value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the snooping function only if the enable bit is set. Otherwise the settings are ignored. When written with 0 will also force bits 3,4 to 0. Defaults to 0 upon reset. 29.9.43 ENET SWI IP Snooping function1 (HW_ENET_SWI_IPSNOOP1) IP Snooping function. Eight independent snooping entries are available. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2042 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) Address: 800F_8000h base + E0h offset = 800F_80E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R PROTOCOL MODE ENABLE Reset W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IPSNOOP1 field descriptions Field 31-16 RSRVD1 15-8 PROTOCOL 7-3 RSRVD0 2-1 MODE Description Reserved bits. Write as 0. The 8-bit protocol value to match with the incoming frame's IP header protocol field. Reserved bits. Write as 0. Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the protocol value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the IP snooping function only if the enable bit is set. Otherwise the settings are ignored. Defaults to 0 upon reset. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2043 Programmable Registers 29.9.44 ENET SWI IP Snooping function2 (HW_ENET_SWI_IPSNOOP2) IP Snooping function. Eight independent snooping entries are available. Address: 800F_8000h base + E4h offset = 800F_80E4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R PROTOCOL MODE ENABLE Reset W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IPSNOOP2 field descriptions Field 31-16 RSRVD1 15-8 PROTOCOL 7-3 RSRVD0 2-1 MODE Description Reserved bits. Write as 0. The 8-bit protocol value to match with the incoming frame's IP header protocol field. Reserved bits. Write as 0. Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the protocol value occurs, the frame is processed as defined by the mode setting. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2044 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_IPSNOOP2 field descriptions (continued) Field Description All other bits of the register are interpreted by the IP snooping function only if the enable bit is set. Otherwise the settings are ignored. Defaults to 0 upon reset. 29.9.45 ENET SWI IP Snooping function3 (HW_ENET_SWI_IPSNOOP3) IP Snooping function. Eight independent snooping entries are available. Address: 800F_8000h base + E8h offset = 800F_80E8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R PROTOCOL MODE ENABLE Reset W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IPSNOOP3 field descriptions Field 31-16 RSRVD1 15-8 PROTOCOL 7-3 RSRVD0 2-1 MODE Description Reserved bits. Write as 0. The 8-bit protocol value to match with the incoming frame's IP header protocol field. Reserved bits. Write as 0. Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2045 Programmable Registers HW_ENET_SWI_IPSNOOP3 field descriptions (continued) Field Description Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the protocol value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the IP snooping function only if the enable bit is set. Otherwise the settings are ignored. Defaults to 0 upon reset. 29.9.46 ENET SWI IP Snooping function4 (HW_ENET_SWI_IPSNOOP4) IP Snooping function. Eight independent snooping entries are available. Address: 800F_8000h base + ECh offset = 800F_80ECh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R PROTOCOL MODE ENABLE Reset W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2046 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_IPSNOOP4 field descriptions Field Description 31-16 RSRVD1 Reserved bits. Write as 0. 15-8 PROTOCOL The 8-bit protocol value to match with the incoming frame's IP header protocol field. 7-3 RSRVD0 Reserved bits. Write as 0. 2-1 MODE Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the protocol value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the IP snooping function only if the enable bit is set. Otherwise the settings are ignored. Defaults to 0 upon reset. 29.9.47 ENET SWI IP Snooping function5 (HW_ENET_SWI_IPSNOOP5) IP Snooping function. Eight independent snooping entries are available. Address: 800F_8000h base + F0h offset = 800F_80F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2047 Programmable Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R PROTOCOL MODE ENABLE Bit W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IPSNOOP5 field descriptions Field 31-16 RSRVD1 15-8 PROTOCOL 7-3 RSRVD0 2-1 MODE Description Reserved bits. Write as 0. The 8-bit protocol value to match with the incoming frame's IP header protocol field. Reserved bits. Write as 0. Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the protocol value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the IP snooping function only if the enable bit is set. Otherwise the settings are ignored. Defaults to 0 upon reset. 29.9.48 ENET SWI IP Snooping function6 (HW_ENET_SWI_IPSNOOP6) IP Snooping function. Eight independent snooping entries are available. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2048 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) Address: 800F_8000h base + F4h offset = 800F_80F4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R PROTOCOL MODE ENABLE Reset W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IPSNOOP6 field descriptions Field 31-16 RSRVD1 15-8 PROTOCOL 7-3 RSRVD0 2-1 MODE Description Reserved bits. Write as 0. The 8-bit protocol value to match with the incoming frame's IP header protocol field. Reserved bits. Write as 0. Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the protocol value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the IP snooping function only if the enable bit is set. Otherwise the settings are ignored. Defaults to 0 upon reset. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2049 Programmable Registers 29.9.49 ENET SWI IP Snooping function7 (HW_ENET_SWI_IPSNOOP7) IP Snooping function. Eight independent snooping entries are available. Address: 800F_8000h base + F8h offset = 800F_80F8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R PROTOCOL MODE ENABLE Reset W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IPSNOOP7 field descriptions Field 31-16 RSRVD1 15-8 PROTOCOL 7-3 RSRVD0 2-1 MODE Description Reserved bits. Write as 0. The 8-bit protocol value to match with the incoming frame's IP header protocol field. Reserved bits. Write as 0. Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Bits 2:1:IP Snooping function 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the protocol value occurs, the frame is processed as defined by the mode setting. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2050 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_IPSNOOP7 field descriptions (continued) Field Description All other bits of the register are interpreted by the IP snooping function only if the enable bit is set. Otherwise the settings are ignored. Defaults to 0 upon reset. 29.9.50 ENET SWI IP Snooping function8 (HW_ENET_SWI_IPSNOOP8) IP Snooping function. Eight independent snooping entries are available. Address: 800F_8000h base + FCh offset = 800F_80FCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD0 R PROTOCOL MODE ENABLE Reset W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IPSNOOP8 field descriptions Field 31-16 RSRVD1 15-8 PROTOCOL 7-3 RSRVD0 2-1 MODE Description Reserved bits. Write as 0. The 8-bit protocol value to match with the incoming frame's IP header protocol field. Reserved bits. Write as 0. Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the protocol value (see bits 15:8). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2051 Programmable Registers HW_ENET_SWI_IPSNOOP8 field descriptions (continued) Field Description Bits 2:1: 00: forward frame to designated management port only 01: copy to management port and forward normally 10: discard Note: the management port is defined in register MGMT_CONFIG. 0 ENABLE When set (1) the entry contains valid data and the function is active. If a match with the protocol value occurs, the frame is processed as defined by the mode setting. All other bits of the register are interpreted by the IP snooping function only if the enable bit is set. Otherwise the settings are ignored. Defaults to 0 upon reset. 29.9.51 ENET SWI Port 0 VLAN priority resolution map (HW_ENET_SWI_VLAN_PRIORITY0) Port 0 VLAN priority resolution map. The 3-bit to 3-bit priority map addressed by the priority bits of the VLAN tag The VLAN_PRIORITY0 registers implement a 3-bit to 3-bit VLAN priority mapping capability. The current frame's 3-bit VLAN priority field is used as an index and the corresponding priority is taken from the respective position of the register giving the final classification for the frame. Address: 800F_8000h base + 100h offset = 800F_8100h Bit 31 30 29 28 27 26 25 24 23 RSRVD0 R 0 0 0 0 0 21 20 P7 W Reset 22 0 0 0 0 0 19 18 17 P6 0 0 0 16 15 14 P5 0 0 0 13 12 11 P4 0 0 0 10 9 8 P3 0 0 0 7 6 5 P2 0 0 0 4 3 2 P1 0 0 0 1 0 P0 0 0 0 0 HW_ENET_SWI_VLAN_PRIORITY0 field descriptions Field Description 31-24 RSRVD0 Reserved bits. Write as 0. 23-21 P7 Priority for input priority 7 20-18 P6 Priority for input priority 6 17-15 P5 Priority for input priority 5 14-12 P4 Priority for input priority 4 11-9 P3 Priority for input priority 3 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2052 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_VLAN_PRIORITY0 field descriptions (continued) Field Description 8-6 P2 Priority for input priority 2 5-3 P1 Priority for input priority 1 P0 Priority for input priority 0 29.9.52 ENET SWI Port 1 VLAN priority resolution map (HW_ENET_SWI_VLAN_PRIORITY1) Port 1 VLAN priority resolution map. The 3-bit to 3-bit priority map addressed by the priority bits of the VLAN tag The VLAN_PRIORITY1 registers implement a 3-bit to 3-bit VLAN priority mapping capability. The current frame's 3-bit VLAN priority field is used as an index and the corresponding priority is taken from the respective position of the register giving the final classification for the frame. Address: 800F_8000h base + 104h offset = 800F_8104h Bit 31 30 29 28 27 26 25 24 23 RSRVD0 R 0 0 0 0 0 21 20 P7 W Reset 22 0 0 0 0 0 19 18 17 P6 0 0 0 16 15 14 P5 0 0 0 13 12 11 P4 0 0 0 10 9 8 P3 0 0 0 7 6 5 P2 0 0 0 4 3 2 P1 0 0 0 1 0 P0 0 0 0 0 HW_ENET_SWI_VLAN_PRIORITY1 field descriptions Field Description 31-24 RSRVD0 Reserved bits. Write as 0. 23-21 P7 Priority for input priority 7 20-18 P6 Priority for input priority 6 17-15 P5 Priority for input priority 5 14-12 P4 Priority for input priority 4 11-9 P3 Priority for input priority 3 8-6 P2 Priority for input priority 2 5-3 P1 Priority for input priority 1 P0 Priority for input priority 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2053 Programmable Registers 29.9.53 ENET SWI Port 2 VLAN priority resolution map (HW_ENET_SWI_VLAN_PRIORITY2) Port 2 VLAN priority resolution map. The 3-bit to 3-bit priority map addressed by the priority bits of the VLAN tag The VLAN_PRIORITY2 registers implement a 3-bit to 3-bit VLAN priority mapping capability. The current frame's 3-bit VLAN priority field is used as an index and the corresponding priority is taken from the respective position of the register giving the final classification for the frame. Address: 800F_8000h base + 108h offset = 800F_8108h Bit 31 30 29 28 27 26 25 24 23 RSRVD0 R 0 0 0 0 0 21 20 P7 W Reset 22 0 0 0 0 0 19 18 17 P6 0 0 0 16 15 14 P5 0 0 0 13 12 11 P4 0 0 0 10 9 8 P3 0 0 0 7 6 5 P2 0 0 0 4 3 2 P1 0 0 0 1 0 P0 0 0 0 0 HW_ENET_SWI_VLAN_PRIORITY2 field descriptions Field Description 31-24 RSRVD0 Reserved bits. Write as 0. 23-21 P7 Priority for input priority 7 20-18 P6 Priority for input priority 6 17-15 P5 Priority for input priority 5 14-12 P4 Priority for input priority 4 11-9 P3 Priority for input priority 3 8-6 P2 Priority for input priority 2 5-3 P1 Priority for input priority 1 P0 Priority for input priority 0 29.9.54 ENET SWI IPv4 and IPv6 priority resolution table programming (HW_ENET_SWI_IP_PRIORITY) IPv4 and IPv6 priority resolution table programming. One Register per port i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2054 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) Address: 800F_8000h base + 140h offset = 800F_8140h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 READ R W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSRV D0 PRIORITY_ PORT2 PRIORITY_ PORT1 PRIORITY_ PORT0 W Reset 0 0 0 0 0 0 0 IPV4_SELECT Reset 0 ADDRESS 0 0 0 0 0 HW_ENET_SWI_IP_PRIORITY field descriptions Field 31 READ Description Must be cleared to write values in the tables. When set during register writes, the IPv6 select and address bits are stored in the register only and the priority bits are ignored and not written into the addressed table. When the register is read, the priority bits represent the value read from the table always. 30-15 RSRVD0 14-13 PRIORITY_ PORT2 Reserved bits. Write as 0. The priority information to write into the addressed table entry. These 2 bits represent the output priority selected when the frame is received on port 2. When reading from the register, the bits show the value from the addressed table entry (address from last write operation). 12-11 PRIORITY_ PORT1 The priority information to write into the addressed table entry. These 2 bits represent the output priority selected when the frame is received on port 1. When reading from the register, the bits show the value from the addressed table entry (address from last write operation). 10-9 PRIORITY_ PORT0 The priority information to write into the addressed table entry. These 2 bits represent the output priority selected when the frame is received on port 0. 00=priority 0 (will be forwarded to output queue 0) 01=priority 1 (output queue 1) 10=priority 2 (output queue 2) 11=priority 3 (output queue 3) Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2055 Programmable Registers HW_ENET_SWI_IP_PRIORITY field descriptions (continued) Field Description When reading from the register, the bits show the value from the addressed table entry (address from last write operation). 8 IPV4_SELECT If set during a write, the IPv4 table is accessed. Valid address values range from 0 to 63. If cleared, the IPv6 table is accessed. Valid address values range from 0 to 255. ADDRESS The address of the priority entry to read or write for a frame received on port n. The IPv4 priority table has 64 entries. The IPv6 table has 256 entries. 29.9.55 ENET SWI Port 0 Priority resolution configuration (HW_ENET_SWI_PRIORITY_CFG0) Port 0 Priority resolution configuration. Defines which priority information should be used for priority resolution Address: 800F_8000h base + 180h offset = 800F_8180h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IP_EN VLAN_EN Bit 0 0 0 0 RSRVD0 Reset MAC_EN W RSRVD1 R DEFAULT_ PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2056 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_PRIORITY_CFG0 field descriptions Field Description 31-7 RSRVD1 Reserved bits. Write as 0. 6-4 DEFAULT_ PRIORITY The default priority of a frame received on port 0, if none of the priority resolutions could define a priority of the frame. Up to 3 bits can be implemented. 3 RSRVD0 Reserved bits. Write as 0. 2 MAC_EN Enable MAC based priority resolution for frame received on port n. If set, the priority information found within the MAC address table is used. 1 IP_EN Enable IP priority resolution for frame received on port n. If set, the IP DiffServ/COS field is used and priority is resolved according to the IP_PRIORITYn setting for the port. If cleared, IP Diffserv/COS fields are ignored. 0 VLAN_EN Enable VLAN priority resolution for frame received on port n. If set, the VLAN tag field of a frame is inspected and priority is resolved according to the setting programmed in VLAN_PRIORITYn for the port on which the frame was received. If cleared, VLAN priority is ignored. 29.9.56 ENET SWI Port 1 Priority resolution configuration (HW_ENET_SWI_PRIORITY_CFG1) Port 1 Priority resolution configuration. Defines which priority information should be used for priority resolution Address: 800F_8000h base + 184h offset = 800F_8184h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2057 12 11 10 9 8 7 6 5 4 RSRVD1 R 3 DEFAULT_ PRIORITY 2 1 0 VLAN_EN 13 IP_EN 14 RSRVD0 15 Bit MAC_EN Programmable Registers 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_PRIORITY_CFG1 field descriptions Field 31-7 RSRVD1 6-4 DEFAULT_ PRIORITY Description Reserved bits. Write as 0. The default priority of a frame received on port 1, if none of the priority resolutions could define a priority of the frame. Up to 3 bits can be implemented. 3 RSRVD0 Reserved bits. Write as 0. 2 MAC_EN Enable MAC based priority resolution for frame received on port n. 1 IP_EN If set, the priority information found within the MAC address table is used. Enable IP priority resolution for frame received on port n. If set, the IP DiffServ/COS field is used and priority is resolved according to the IP_PRIORITYn setting for the port. If cleared, IP Diffserv/COS fields are ignored. 0 VLAN_EN Enable VLAN priority resolution for frame received on port n. If set, the VLAN tag field of a frame is inspected and priority is resolved according to the setting programmed in VLAN_PRIORITYn for the port on which the frame was received. If cleared, VLAN priority is ignored. 29.9.57 ENET SWI Port 2 Priority resolution configuration (HW_ENET_SWI_PRIORITY_CFG2) Port 2 Priority resolution configuration. Defines which priority information should be used for priority resolution i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2058 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) Address: 800F_8000h base + 188h offset = 800F_8188h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IP_EN VLAN_EN Bit 0 0 0 0 RSRVD0 Reset MAC_EN W RSRVD1 R DEFAULT_ PRIORITY W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_PRIORITY_CFG2 field descriptions Field 31-7 RSRVD1 6-4 DEFAULT_ PRIORITY Description Reserved bits. Write as 0. The default priority of a frame received on port 2, if none of the priority resolutions could define a priority of the frame. Up to 3 bits can be implemented. 3 RSRVD0 Reserved bits. Write as 0. 2 MAC_EN Enable MAC based priority resolution for frame received on port n. 1 IP_EN If set, the priority information found within the MAC address table is used. Enable IP priority resolution for frame received on port n. If set, the IP DiffServ/COS field is used and priority is resolved according to the IP_PRIORITYn setting for the port. If cleared, IP Diffserv/COS fields are ignored. 0 VLAN_EN Enable VLAN priority resolution for frame received on port n. If set, the VLAN tag field of a frame is inspected and priority is resolved according to the setting programmed in VLAN_PRIORITYn for the port on which the frame was received. If cleared, VLAN priority is ignored. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2059 Programmable Registers 29.9.58 ENET SWI Port 0 VLAN-ID field for VLAN input manipulation function (HW_ENET_SWI_SYSTEM_TAGINFO0) Port 0 VLAN-ID field for VLAN input manipulation function of a port if it exists (synthesis option). Address: 800F_8000h base + 200h offset = 800F_8200h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD0 R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 SYSTEM_TAGINFO0 W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_SYSTEM_TAGINFO0 field descriptions Field Description 31-16 RSRVD0 Reserved bits. Write as 0. SYSTEM_ TAGINFO0 VLAN information field. 29.9.59 ENET SWI Port 1 VLAN-ID field for VLAN input manipulation function (HW_ENET_SWI_SYSTEM_TAGINFO1) Port 1 VLAN-ID field for VLAN input manipulation function of a port if it exists (synthesis option). Address: 800F_8000h base + 204h offset = 800F_8204h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD0 R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 SYSTEM_TAGINFO0 W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_SYSTEM_TAGINFO1 field descriptions Field 31-16 RSRVD0 SYSTEM_ TAGINFO0 Description Reserved bits. Write as 0. VLAN information field. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2060 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.9.60 ENET SWI Port 2 VLAN-ID field for VLAN input manipulation function (HW_ENET_SWI_SYSTEM_TAGINFO2) Port 2 VLAN-ID field for VLAN input manipulation function of a port if it exists (synthesis option). Address: 800F_8000h base + 208h offset = 800F_8208h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RSRVD0 R 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 SYSTEM_TAGINFO0 W Reset 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_SYSTEM_TAGINFO2 field descriptions Field Description 31-16 RSRVD0 Reserved bits. Write as 0. SYSTEM_ TAGINFO0 VLAN information field. 29.9.61 ENET SWI VLAN domain resolution entry 0. (HW_ENET_SWI_VLAN_RES_TABLE_0) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 280h offset = 800F_8280h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2061 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_0 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_0 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_0 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.62 ENET SWI VLAN domain resolution entry 1. (HW_ENET_SWI_VLAN_RES_TABLE_1) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 284h offset = 800F_8284h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2062 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_1 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_1 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_1 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.63 ENET SWI VLAN domain resolution entry 2. (HW_ENET_SWI_VLAN_RES_TABLE_2) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 288h offset = 800F_8288h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2063 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_2 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_2 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_2 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.64 ENET SWI VLAN domain resolution entry 3. (HW_ENET_SWI_VLAN_RES_TABLE_3) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 28Ch offset = 800F_828Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2064 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_3 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_3 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_3 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.65 ENET SWI VLAN domain resolution entry 4. (HW_ENET_SWI_VLAN_RES_TABLE_4) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 290h offset = 800F_8290h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2065 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_4 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_4 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_4 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.66 ENET SWI VLAN domain resolution entry 5. (HW_ENET_SWI_VLAN_RES_TABLE_5) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 294h offset = 800F_8294h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2066 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_5 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_5 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_5 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.67 ENET SWI VLAN domain resolution entry 6. (HW_ENET_SWI_VLAN_RES_TABLE_6) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 298h offset = 800F_8298h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2067 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_6 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_6 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_6 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.68 ENET SWI VLAN domain resolution entry 7. (HW_ENET_SWI_VLAN_RES_TABLE_7) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 29Ch offset = 800F_829Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2068 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_7 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_7 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_7 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.69 ENET SWI VLAN domain resolution entry 8. (HW_ENET_SWI_VLAN_RES_TABLE_8) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2A0h offset = 800F_82A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2069 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_8 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_8 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_8 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.70 ENET SWI VLAN domain resolution entry 9. (HW_ENET_SWI_VLAN_RES_TABLE_9) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2A4h offset = 800F_82A4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2070 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_9 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_9 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_9 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.71 ENET SWI VLAN domain resolution entry 10. (HW_ENET_SWI_VLAN_RES_TABLE_10) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2A8h offset = 800F_82A8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2071 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_10 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_10 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_10 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.72 ENET SWI VLAN domain resolution entry 11. (HW_ENET_SWI_VLAN_RES_TABLE_11) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2ACh offset = 800F_82ACh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2072 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_11 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_11 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_11 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.73 ENET SWI VLAN domain resolution entry 12. (HW_ENET_SWI_VLAN_RES_TABLE_12) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2B0h offset = 800F_82B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2073 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_12 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_12 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_12 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.74 ENET SWI VLAN domain resolution entry 13. (HW_ENET_SWI_VLAN_RES_TABLE_13) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2B4h offset = 800F_82B4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2074 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_13 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_13 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_13 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.75 ENET SWI VLAN domain resolution entry 14. (HW_ENET_SWI_VLAN_RES_TABLE_14) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2B8h offset = 800F_82B8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2075 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_14 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_14 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_14 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.76 ENET SWI VLAN domain resolution entry 15. (HW_ENET_SWI_VLAN_RES_TABLE_15) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2BCh offset = 800F_82BCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2076 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_15 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_15 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_15 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.77 ENET SWI VLAN domain resolution entry 16. (HW_ENET_SWI_VLAN_RES_TABLE_16) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2C0h offset = 800F_82C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2077 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_16 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_16 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_16 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.78 ENET SWI VLAN domain resolution entry 17. (HW_ENET_SWI_VLAN_RES_TABLE_17) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2C4h offset = 800F_82C4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2078 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_17 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_17 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_17 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.79 ENET SWI VLAN domain resolution entry 18. (HW_ENET_SWI_VLAN_RES_TABLE_18) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2C8h offset = 800F_82C8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2079 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_18 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_18 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_18 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.80 ENET SWI VLAN domain resolution entry 19. (HW_ENET_SWI_VLAN_RES_TABLE_19) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2CCh offset = 800F_82CCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2080 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_19 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_19 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_19 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.81 ENET SWI VLAN domain resolution entry 20. (HW_ENET_SWI_VLAN_RES_TABLE_20) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2D0h offset = 800F_82D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2081 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_20 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_20 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_20 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.82 ENET SWI VLAN domain resolution entry 21. (HW_ENET_SWI_VLAN_RES_TABLE_21) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2D4h offset = 800F_82D4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2082 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_21 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_21 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_21 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.83 ENET SWI VLAN domain resolution entry 22. (HW_ENET_SWI_VLAN_RES_TABLE_22) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2D8h offset = 800F_82D8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2083 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_22 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_22 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_22 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.84 ENET SWI VLAN domain resolution entry 23. (HW_ENET_SWI_VLAN_RES_TABLE_23) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2DCh offset = 800F_82DCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2084 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_23 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_23 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_23 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.85 ENET SWI VLAN domain resolution entry 24. (HW_ENET_SWI_VLAN_RES_TABLE_24) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2E0h offset = 800F_82E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2085 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_24 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_24 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_24 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.86 ENET SWI VLAN domain resolution entry 25. (HW_ENET_SWI_VLAN_RES_TABLE_25) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2E4h offset = 800F_82E4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2086 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_25 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_25 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_25 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.87 ENET SWI VLAN domain resolution entry 26. (HW_ENET_SWI_VLAN_RES_TABLE_26) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2E8h offset = 800F_82E8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2087 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_26 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_26 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_26 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.88 ENET SWI VLAN domain resolution entry 27. (HW_ENET_SWI_VLAN_RES_TABLE_27) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2ECh offset = 800F_82ECh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2088 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_27 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_27 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_27 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.89 ENET SWI VLAN domain resolution entry 28. (HW_ENET_SWI_VLAN_RES_TABLE_28) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2F0h offset = 800F_82F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2089 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_28 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_28 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_28 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.90 ENET SWI VLAN domain resolution entry 29. (HW_ENET_SWI_VLAN_RES_TABLE_29) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2F4h offset = 800F_82F4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2090 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_29 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_29 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_29 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.91 ENET SWI VLAN domain resolution entry 30. (HW_ENET_SWI_VLAN_RES_TABLE_30) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2F8h offset = 800F_82F8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2091 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Programmable Registers 0 0 0 RSRV D0 VLAN_ID_30 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_30 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_30 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.92 ENET SWI VLAN domain resolution entry 31. (HW_ENET_SWI_VLAN_RES_TABLE_31) Note: the VLAN table is always searched completely, hence there is no order in which the table entries need to be written. Address: 800F_8000h base + 2FCh offset = 800F_82FCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2092 Freescale Semiconductor, Inc. 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 2 1 0 PORT_0 R 14 PORT_1 15 Bit PORT_2 Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 RSRV D0 VLAN_ID_31 W Reset 0 0 0 0 0 0 0 0 HW_ENET_SWI_VLAN_RES_TABLE_31 field descriptions Field Description 31-15 RSRVD0 Reserved bits. Write as 0. 14-3 VLAN_ID_31 12-bit VLAN identifier 0. 2 PORT_2 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2. 1 PORT_1 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1. 0 PORT_0 member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0. 29.9.93 ENET SWI Total number of incoming frames processed (HW_ENET_SWI_TOTAL_DISC) Total number of incoming frames processed but discarded in the switch. Address: 800F_8000h base + 300h offset = 800F_8300h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOTAL_DISC R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_TOTAL_DISC field descriptions Field TOTAL_DISC Description ENET SWI Total number of incoming frames processed i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2093 Programmable Registers 29.9.94 ENET SWI Sum of bytes of frames counted in TOTAL_DISC (HW_ENET_SWI_TOTAL_BYT_DISC) Sum of bytes of frames counted in TOTAL_DISC Address: 800F_8000h base + 304h offset = 800F_8304h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOTAL_BYT_DISC R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_TOTAL_BYT_DISC field descriptions Field Description TOTAL_BYT_ DISC ENET SWI Sum of bytes of frames counted in TOTAL_DISC 29.9.95 ENET SWI Total number of incoming frames processed (HW_ENET_SWI_TOTAL_FRM) Total number of incoming frames processed and not discarded. Address: 800F_8000h base + 308h offset = 800F_8308h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOTAL_FRM R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_TOTAL_FRM field descriptions Field TOTAL_FRM Description ENET SWI Total number of incoming frames processed 29.9.96 ENET SWI Sum of bytes of frames counted in TOTAL_FRM (HW_ENET_SWI_TOTAL_BYT_FRM) Sum of bytes of frames counted in TOTAL_FRM i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2094 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) Address: 800F_8000h base + 30Ch offset = 800F_830Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOTAL_BYT_FRM R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_TOTAL_BYT_FRM field descriptions Field Description TOTAL_BYT_ FRM ENET SWI Sum of bytes of frames counted in TOTAL_FRM 29.9.97 ENET SWI Port 0 Outgoing frames discarded due to output Queue congestion (HW_ENET_SWI_ODISC0) Port 0 Outgoing frames discarded due to output Queue congestion. Address: 800F_8000h base + 310h offset = 800F_8310h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODISC0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_ODISC0 field descriptions Field Description ODISC0 ENET SWI Port 0 Outgoing frames discarded due to output Queue congestion 29.9.98 ENET SWI Port 0 incoming frames discarded due to mismatching or missing VLAN id (HW_ENET_SWI_IDISC_VLAN0) Port 0 incoming frames discarded due to mismatching or missing VLAN id while VLAN verification was enabled See also Register VLAN_VERIFY. Address: 800F_8000h base + 314h offset = 800F_8314h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDISC_VLAN0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2095 Programmable Registers HW_ENET_SWI_IDISC_VLAN0 field descriptions Field Description IDISC_VLAN0 ENET SWI Port 0 incoming frames discarded due to mismatching or missing VLAN id 29.9.99 ENET SWI Port 0 incoming frames discarded due to missing vlan tag (HW_ENET_SWI_IDISC_UNTAGGED0) Port 0 incoming frames discarded due to missing vlan tag. See also Register VLAN_VERIFY. Address: 800F_8000h base + 318h offset = 800F_8318h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDISC_UNTAGGED0 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IDISC_UNTAGGED0 field descriptions Field Description IDISC_ UNTAGGED0 ENET SWI Port 0 incoming frames discarded due to missing vlan tag 29.9.100 ENET SWI Port 0 incoming frames discarded (after learning) as port is configured in blocking mode (HW_ENET_SWI_IDISC_BLOCKED0) Port 0 incoming frames discarded (after learning) as port is configured in blocking mode Address: 800F_8000h base + 31Ch offset = 800F_831Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDISC_BLOCKED0 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IDISC_BLOCKED0 field descriptions Field IDISC_ BLOCKED0 Description ENET SWI Port 0 incoming frames discarded (after learning) as port is configured in blocking mode i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2096 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.9.101 ENET SWI Port 1 Outgoing frames discarded due to output Queue congestion (HW_ENET_SWI_ODISC1) Port 1 Outgoing frames discarded due to output Queue congestion. Address: 800F_8000h base + 320h offset = 800F_8320h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODISC1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_ODISC1 field descriptions Field Description ODISC1 ENET SWI Port 1 Outgoing frames discarded due to output Queue congestio 29.9.102 ENET SWI Port 1 incoming frames discarded due to mismatching or missing VLAN id (HW_ENET_SWI_IDISC_VLAN1) Port 1 incoming frames discarded due to mismatching or missing VLAN id while VLAN verification was enabled See also Register VLAN_VERIFY. Address: 800F_8000h base + 324h offset = 800F_8324h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDISC_VLAN1 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IDISC_VLAN1 field descriptions Field IDISC_VLAN1 Description ENET SWI Port 1 incoming frames discarded due to mismatching or missing VLAN id 29.9.103 ENET SWI Port 1 incoming frames discarded due to missing vlan tag (HW_ENET_SWI_IDISC_UNTAGGED1) Port 1 incoming frames discarded due to missing vlan tag. See also Register VLAN_VERIFY. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2097 Programmable Registers Address: 800F_8000h base + 328h offset = 800F_8328h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDISC_UNTAGGED1 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IDISC_UNTAGGED1 field descriptions Field Description IDISC_ UNTAGGED1 ENET SWI Port 1 incoming frames discarded due to missing vlan tag 29.9.104 ENET SWI Port 1 incoming frames discarded (after learning) as port is configured in blocking mode (HW_ENET_SWI_IDISC_BLOCKED1) Port 1 incoming frames discarded (after learning) as port is configured in blocking mode Address: 800F_8000h base + 32Ch offset = 800F_832Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDISC_BLOCKED1 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IDISC_BLOCKED1 field descriptions Field Description IDISC_ BLOCKED1 ENET SWI Port 1 incoming frames discarded (after learning) as port is configured in blocking mode 29.9.105 ENET SWI Port 2 Outgoing frames discarded due to output Queue congestion (HW_ENET_SWI_ODISC2) Port 2 Outgoing frames discarded due to output Queue congestion. Address: 800F_8000h base + 330h offset = 800F_8330h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODISC2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2098 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_ODISC2 field descriptions Field Description ODISC2 ENET SWI Port 2 Outgoing frames discarded due to output Queue congestion 29.9.106 ENET SWI Port 2 incoming frames discarded due to mismatching or missing VLAN id (HW_ENET_SWI_IDISC_VLAN2) Port 2 incoming frames discarded due to mismatching or missing VLAN id while VLAN verification was enabled See also Register VLAN_VERIFY. Address: 800F_8000h base + 334h offset = 800F_8334h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDISC_VLAN2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IDISC_VLAN2 field descriptions Field Description IDISC_VLAN2 ENET SWI Port 2 incoming frames discarded due to mismatching or missing VLAN id 29.9.107 ENET SWI Port 2 incoming frames discarded due to missing vlan tag (HW_ENET_SWI_IDISC_UNTAGGED2) Port 2 incoming frames discarded due to missing vlan tag. See also Register VLAN_VERIFY. Address: 800F_8000h base + 338h offset = 800F_8338h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDISC_UNTAGGED2 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IDISC_UNTAGGED2 field descriptions Field IDISC_ UNTAGGED2 Description ENET SWI Port 2 incoming frames discarded due to missing vlan tag i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2099 Programmable Registers 29.9.108 ENET SWI Port 2 incoming frames discarded (after learning) as port is configured in blocking mod (HW_ENET_SWI_IDISC_BLOCKED2) Port 2 incoming frames discarded (after learning) as port is configured in blocking mode Address: 800F_8000h base + 33Ch offset = 800F_833Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDISC_BLOCKED2 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_IDISC_BLOCKED2 field descriptions Field Description IDISC_ BLOCKED2 ENET SWI Port 2 incoming frames discarded (after learning) as port is configured in blocking mod 29.9.109 ENET SWI Interrupt Event Register (HW_ENET_SWI_EIR) The event bits are latched. To clear a bit it must be written with 1. The bit will stay set if the event condition persists. Address: 800F_8000h base + 400h offset = 800F_8400h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2100 Freescale Semiconductor, Inc. 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LRN OD2 OD1 OD0 QM TXF TXB RXF RXB EBERR Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 0 0 0 0 1 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 HW_ENET_SWI_EIR field descriptions Field 31-10 RSRVD0 Description Reserved bits. Write as 0. 9 LRN Learning Record available in registers LNR_REC_0 and LNR_REC_1 (Signal ipi_lrn_int asserted). 8 OD2 Outgoing frames discarded due to output Queue congestion on Port 2 or port is disabled (PORT_ENA). 7 OD1 Outgoing frames discarded due to output Queue congestion on Port 1or port is disabled (PORT_ENA). 6 OD0 Outgoing frames discarded due to output Queue congestion on Port 0 or port is disabled (PORT_ENA). 5 QM Low Memory Threshold. Asserted if the memory became congested and number of free cells dropped below threshold QMGR_MINCELLS (Signal ipi_qm_int asserted). Note: this interrupt can be very frequent on a heavy loaded network. It is not recommended to use this interrupt source as interrupt but rather implement a slow background task polling the bit to perform learning. Asserts ipi_od2_int Asserts ipi_od1_int Asserts ipi_od0_int Note: will become asserted after reset immediately due to memory initialization. 4 TXF Transmit frame interrupt. This bit indicates a frame has been transmitted and the last corresponding buffer descriptor has been updated (Signal ipi_txf_int asserted). 3 TXB Transmit buffer interrupt. This bit indicates a transmit buffer descriptor has been updated (Signal ipi_txb_int asserted). 2 RXF Receive frame interrupt. This bit indicates a frame has been received and the last corresponding buffer descriptor has been updated (Signal ipi_rxf_int asserted). 1 RXB Receive buffer interrupt. This bit indicates a receive buffer descriptor not the last in the frame has been updated (Signal ipi_rxb_int asserted). 0 EBERR Ethernet bus error. This bit indicates a system bus error occurs when a DMA transaction is underway (Signal ipi_eberr_int asserted). 29.9.110 ENET SWI Interrupt Mask Register (HW_ENET_SWI_EIMR) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2101 Programmable Registers Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The corresponding EIMR bit determines whether an interrupt condition can generate an interrupt. At every processor clock, the EIR samples the signal generated by the interrupting source. The corresponding EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit is set. 0 The corresponding interrupt source is masked. 1 The corresponding interrupt source is not masked and an interrupt can occur (asserting corresponding ipi_xxx signal). Address: 800F_8000h base + 404h offset = 800F_8404h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LRN OD2 OD1 OD0 QM TXF TXB RXF RXB EBERR W 0 0 0 0 0 0 0 0 0 0 RSRVD0 R W Reset 0 0 0 0 0 0 HW_ENET_SWI_EIMR field descriptions Field 31-10 RSRVD0 Description Reserved bits. Write as 0. 9 LRN 0: interrupt masked1 8 OD2 0: interrupt masked 7 OD1 0: interrupt masked 6 OD0 0: interrupt masked 5 QM 0: interrupt masked 1: interrupt enabled. 1: interrupt enabled. 1: interrupt enabled. 1: interrupt enabled. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2102 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) HW_ENET_SWI_EIMR field descriptions (continued) Field Description 1: interrupt enabled. 4 TXF 0: interrupt masked 3 TXB 0: interrupt masked 2 RXF 0: interrupt masked 1 RXB 0: interrupt masked 0 EBERR 0: interrupt masked 1: interrupt enabled. 1: interrupt enabled. 1: interrupt enabled. 1: interrupt enabled. 1: interrupt enabled. 29.9.111 ENET SWI Pointer to Receive Descriptor Ring (HW_ENET_SWI_ERDSR) Pointer to Receive Descriptor Ring. Only Bits 31:2 are writeable. 1:0 always 0. Address: 800F_8000h base + 408h offset = 800F_8408h Bit 31 30 29 28 27 26 25 R Bit 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RSRVD0 ERDSR W Reset 23 ERDSR W Reset 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_ERDSR field descriptions Field Description 31-2 ERDSR ERDSR RSRVD0 Reserved bits. Write as 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2103 Programmable Registers 29.9.112 ENET SWI Pointer to Transmit Descriptor Ring (HW_ENET_SWI_ETDSR) Pointer to Transmit Descriptor Ring. Only Bits 31:2 are writeable. 1:0 always 0. Address: 800F_8000h base + 40Ch offset = 800F_840Ch Bit 31 30 29 28 27 26 25 24 R 22 21 20 19 18 17 16 ETDSR W Reset Bit 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RSRVD0 ETDSR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_ETDSR field descriptions Field Description 31-2 ETDSR ERDSR RSRVD0 Reserved bits. Write as 0. 29.9.113 ENET SWI Maximum Receive Buffer Size (HW_ENET_SWI_EMRBR) Maximum Receive Buffer Size. Address: 800F_8000h base + 410h offset = 800F_8410h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 RSRVD0 EMRBR W Reset 9 0 0 0 0 0 0 0 0 HW_ENET_SWI_EMRBR field descriptions Field Description 31-14 RSRVD1 Reserved bits. Write as 0. 13-4 EMRBR ENET SWI Maximum Receive Buffer Size RSRVD0 Reserved bits. Write as 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2104 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.9.114 ENET SWI Receive Descriptor Active Register (HW_ENET_SWI_RDAR) Receive Descriptor Active Register Address: 800F_8000h base + 414h offset = 800F_8414h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDAR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_RDAR field descriptions Field Description RDAR ENET SWI Receive Descriptor Active Register 29.9.115 ENET SWI Transmit Descriptor Active Register (HW_ENET_SWI_TDAR) Transmit Descriptor Active Register Address: 800F_8000h base + 418h offset = 800F_8418h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDAR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_TDAR field descriptions Field TDAR Description ENET SWI Transmit Descriptor Active Register 29.9.116 ENET SWI Learning Records A (0) and B (1) (HW_ENET_SWI_LRN_REC_0) Learning Records A (0) and B (1). Lower 32-Bit of the Frame MAC Address. 7:0 = first octet, 31:24=4th octet. Note: this register must be read first, before reading LRN_REC_1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2105 Programmable Registers Address: 800F_8000h base + 500h offset = 800F_8500h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 LRN_REC_0 R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_LRN_REC_0 field descriptions Field Description LRN_REC_0 ENET SWI Learning Records A (0) and B (1) 29.9.117 ENET SWI Learning Record B(1) (HW_ENET_SWI_LRN_REC_1) Learning Record B(1). Address: 800F_8000h base + 504h offset = 800F_8504h Bit 31 30 29 28 27 26 24 23 22 21 SW_ PORT RSRVD0 R 25 20 19 18 17 16 15 14 13 12 11 10 HASH 9 8 MAC_ADDR1 W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_LRN_REC_1 field descriptions Field 31-26 RSRVD0 25-24 SW_PORT 23-16 HASH MAC_ADDR1 Description Reserved bits. Write as 0. Port number on which the Frame is received. The 8-bit Hash value Upper 16-Bit of the Frame MAC Address. 7:0=5th octet, 15:8=6th octet. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2106 Freescale Semiconductor, Inc. Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH) 29.9.118 ENET SWI Learning data available status. (HW_ENET_SWI_LRN_STATUS) Address: 800F_8000h base + 508h offset = 800F_8508h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD0 R W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LRN_STATUS Reset RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_LRN_STATUS field descriptions Field 31-1 RSRVD0 0 LRN_STATUS Description Reserved bits. Write as 0. 1 indicates if the learning record is valid and can be read. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2107 Programmable Registers 29.9.119 ENET SWI lookup MAC address memory end (HW_ENET_SWI_LOOKUP_MEMORY_END) Address: 800F_8000h base + FFFCh offset = 8010_7FFCh Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMORY_DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_ENET_SWI_LOOKUP_MEMORY_END field descriptions Field Description MEMORY_DATA Memroy cell. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2108 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) 30.1 Application UART Overview The Application UART: * Performs serial-to-parallel conversion on data received from a peripheral device. * Performs parallel-to-serial conversion on data transmitted to the peripheral device. * Operates up to 3.25 Mb/s. The CPU or DMA controller reads and writes data and control/status information through the APBX interface. The transmit and receive paths are buffered with internal FIFO memories, enabling up to 16 bytes to be stored independently in both transmit and receive modes. The Application UART includes a programmable baud rate generator that generates a transmit and receive internal clock from the 24 MHz UART internal reference clock input UARTCLK. XCLK (apbclk) is not tied to the UARTCLK in the i.MX28. Automatic baud rate detection is supported up to 1.2 Mbps. One or two reference frames can be used in detecting the baud rate. It offers similar functionality to the industry-standard 16C550 UART device and supports baud rates of up to 3.25 Mbits/s (in high-speed configuration with a minimum XCLK frequency of 1.5 MHz). Figure 30-1 shows a block diagram of the Application UART. The Application UART operation and baud rate values are controlled by the line control register (HW_UARTAPP_LINECTRL). The HW_UARTAPP_LINECTRL register controls both receive and transmit operations. However, when HW_UARTAPP_CTRL2_USE_LCR2 is set, then HW_UARTAPP_LINECTRL controls receive operations and HW_UARTAPP_LINECTRL2 controls transmit operations. The Application UART can generate a single combined interrupt, so that the output is asserted if any of the individual interrupts are asserted and unmasked. Interrupt sources include the receive (including timeout), transmit, modem status, and error conditions. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2109 Application UART Overview Two DMA channels are supported, one for transmit and one for receive. If a timeout condition occurs in the middle of a receive DMA block transfer, then the UART ends the DMA transfer and signals the end of the DMA block transfer. A receive DMA can be setup to get the status of the previous receive DMA block transfer. The status indicates the amount of valid data bytes in the previous receive DMA block transfer. If a framing, parity, or break error occurs during reception, the appropriate error bit is set and stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and FIFO data is prevented from being overwritten. You can program the FIFOs to be one-byte deep, providing a conventional double-buffered UART interface. The modem status input signal Clear To Send (CTS) and output modem control line Request To Send (RTS) are supported. A programmable hardware flow control feature uses the nUARTCTS input and the nUARTRTS output to automatically control the serial data flow. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2110 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) ARM Core SRAM AHB 24-MHz XTAL Osc. XCLK Divide by n AHB Master APBX APBX Master AHB-to-APBX Bridge XCLK Shared DMA UARTCLK AHB Slave UART Programmable Registers and FIFOs UART_RXD UART_RTS UART_CTS UART_TXD RX FSM BAUDRATE TX FSM UART Figure 30-1. Application UART Block Diagram 30.2 Operation Control data is written to the Application UART line control register. This register defines: * Transmission parameters * Word length i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2111 Operation * Buffer mode * Number of transmitted stop bits * Parity mode * Break generation * Baud rate divisor If USE_LCR2 is set, the Application UART Line Control Register applies to the receive operation, and similar control data written to the Application UART Line Control 2 Register applies to the transmit operation. 30.2.1 Fractional Baud Rate Divider The baud rate divisor is calculated from the frequency of UARTCLK and the desired baud rate by using the following formula: divisor = (UARTCLK * 32) / baud rate, rounded to the nearest integer The divisor must be between 0x000000EC and 0x003FFFC0, inclusive. Program the lowest 6 bits of the divisor into BAUD_DIVFRAC, and the next 16 bits of the divisor into BAUD_DIVINT. 30.2.2 Automatic Baud Rate Detection The receive baud rate can be automatically detected by the Application UART. Some UART protocol are based on packets of frames with the first 1 or 2 frames being reference frames for baud detection. The UARTAPP detection logic is capable of starting in the middle of a RX packet and find the reference frame at the start of the next packet, then set the corresponding baud rate for the remainder of the packet. Note, the RXD is gated off to the UART Receiver module until the reference frames are detected. So, the reference frames are stripped from the packet and absent from the RXFIFO. The UART firmware will tell the hardware when to detect the baud rate. The Autobaud Detection logic can be configured to detect RX baud rate each time a RX DMA is kicked off, or just each time the firmware writes the START_BAUD_DETECT bit in the AUTOBAUD register. Once the baud rate is found, it is loaded into the RX baud divisor register, and optionally loaded into the TX baud divisor register. Refer to the AutoBaud register for programming details. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2112 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) 30.2.3 UART Character Frame Figure 30-2 illustrates the UART character frame. UARTTXD lsb 1 msb 1-2 stop bits 5-8 data bits 0 n Start Parity bit if enabled Figure 30-2. Application UART Character Frame 30.2.4 DMA Operation The Application UART can generate a DMA request signal for interfacing with a Direct Memory Access (DMA) controller. Two DMA channels are supported, one for transmit and one for receive. Each channel has an associated 16-bit transfer counter for the number of bytes to transfer. Each DMA request is associated with one to four data bytes. For APBX DMA UART RX channel, the first PIO word in the DMA command is CTRL0. However, for APBX DMA UART TX channel, the first PIO word in a DMA command is CTRL1. At the end of a receive DMA block transfer, the status register indicates any error conditions. If a timeout condition occurs in the middle of a receive DMA block transfer, then the UART sends dummy data to the DMA controller until the transfer counter is decremented to zero. A receive DMA can be setup to get the status of the previous receive DMA block transfer. The status indicates the amount of valid data bytes in the previous receive DMA block transfer. 30.2.5 Data Transmission or Reception Data received or transmitted is stored in two 16-byte FIFOs, although the receive FIFO has an extra four bits per character for status information. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2113 Operation For transmission, data is written into the transmit FIFO. If the Application UART is enabled, it causes a data frame to start transmitting with the parameters indicated in UARTAPP_LINECTRL or UARTAPP_LINECTRL2 (if USE_LCR2 is set). Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY signal goes HIGH as soon as the data is written to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted HIGH while data is being transmitted. BUSY is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. BUSY can be asserted HIGH, even though the Application UART might no longer be enabled. For each sample of data, three readings are taken and the majority value is kept. In the following paragraphs, the middle sampling point is defined, and one sample is taken on either side of it. * When the receiver is idle (UARTRXD continuously 1, in the marking state) and a LOW is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by BaudClk, begins running and data is sampled on the first cycle of that counter in normal UART mode to allow for the shorter logic 0 pulses (half way through a bit period). * The start bit is valid if UARTRXD is still LOW on the first cycle of BaudClk, otherwise a false start bit is detected and it is ignored. If the start bit was valid, successive data bits are sampled on every second cycle of BaudClk (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. * Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word (see Table 30-1). 30.2.6 Error Bits Three error bits are stored in bits [10:8] of the receive FIFO and are associated with a particular character. An additional error indicating an overrun error is stored in bit 11 of the receive FIFO. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2114 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) 30.2.7 Overrun Bit The overrun bit is not associated with the character in the receive FIFO. The overrun error is set when the FIFO is full and the next character is completely received in the shift register. The data in the shift register is overwritten, but it is not written into the FIFO. When an empty location is available in the receive FIFO and another character is received, the state of the overrun bit is copied into the receive FIFO along with the received character. The overrun state is then cleared. The table shows the bit functions of the receive FIFO. Table 30-1. Receive FIFO Bit Functions FIFO bit Function 11 Overrun indicator 10 Break error 9 Parity error 8 Framing error 7:0 Received data 30.2.8 Disabling the FIFOs FIFOs can be disabled. In this case, the transmit and receive sides of the Application UART have one-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word has been received and the previous one was not yet read. In this implementation, the FIFOs are not physically disabled, but the flags are manipulated to give the illusion of a one-byte register. 30.3 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2115 Programmable Registers 30.4 Programmable Registers UARTAPP Hardware Register Format Summary UARTAPP0 base address is 0x8006A000; UARTAPP1 base address is 0x8006C000; UARTAPP2 base address is 0x8006E000; UARTAPP3 base address is 0x80070000; UARTAPP4 base address is 0x80072000 HW_UARTAPP memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8006_A000 UART Receive DMA Control Register (HW_UARTAPP_CTRL0) 32 R/W C003_0000h 30.4.1/2116 8006_A010 UART Transmit DMA Control Register (HW_UARTAPP_CTRL1) 32 R/W 0000_0000h 30.4.2/2117 8006_A020 UART Control Register (HW_UARTAPP_CTRL2) 32 R/W 0022_0300h 30.4.3/2118 8006_A030 UART Line Control Register (HW_UARTAPP_LINECTRL) 32 R/W 0000_0000h 30.4.4/2121 8006_A040 UART Line Control 2 Register (HW_UARTAPP_LINECTRL2) 32 R/W 0000_0000h 30.4.5/2122 8006_A050 UART Interrupt Register (HW_UARTAPP_INTR) 32 R/W 0000_0000h 30.4.6/2124 8006_A060 UART Data Register (HW_UARTAPP_DATA) 32 R/W 0000_0000h 30.4.7/2126 8006_A070 UART Status Register (HW_UARTAPP_STAT) 32 R/W C9F0_0000h 30.4.8/2128 8006_A080 UART Debug Register (HW_UARTAPP_DEBUG) 32 R 0000_0000h 30.4.9/2130 8006_A090 UART Version Register (HW_UARTAPP_VERSION) 32 R 0301_0000h 30.4.10/ 2131 32 R/W 0000_0000h 30.4.11/ 2132 8006_A0A0 UART AutoBaud Register (HW_UARTAPP_AUTOBAUD) 30.4.1 UART Receive DMA Control Register (HW_UARTAPP_CTRL0) The UART Receive DMA Control Register contains the dynamic information associated with the receive command. HW_UARTAPP_CTRL0: 0x000 HW_UARTAPP_CTRL0_SET: 0x004 HW_UARTAPP_CTRL0_CLR: 0x008 HW_UARTAPP_CTRL0_TOG: 0x00C This register contains the main DMA controls for Receiving data. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2116 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) 31 30 29 28 27 CLKGATE RUN W SFTRST RX_SOURCE RXTO_ ENABLE Address: 8006_A000h base + 0h offset = 8006_A000h Bit Reset 1 1 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 0 R Bit 26 25 24 23 22 21 20 19 18 17 16 0 0 0 1 1 5 4 3 2 1 0 0 0 0 0 0 0 RXTIMEOUT R XFER_COUNT W Reset 0 0 0 0 0 0 0 0 0 HW_UARTAPP_CTRL0 field descriptions Field 31 SFTRST 30 CLKGATE 29 RUN 28 RX_SOURCE Description Set to zero for normal operation. When this bit is set to one (default), then the entire block is held in its reset state. Set this bit zero for normal operation. Setting this bit to one (default), gates all of the block level clocks off for miniminizing AC energy consumption. Tell the UART to execute the RX DMA Command. The UART will clear this bit at the end of receive execution. Source of Receive Data. If this bit is set to 1, the status register will be the source of the DMA, otherwise RX data will be the source. 27 RXTIMEOUT Enable: If this bit is set to 0, the RX timeout will not affect receive DMA operation. If this bit is RXTO_ENABLE set to 1, a receive timeout will cause the receive DMA logic to terminate. 26-16 RXTIMEOUT XFER_COUNT Receive Timeout Counter Value: number of 8-bit-time to wait before asserting timeout on the RX input. If the RXFIFO is not empty and the RX input is idle, then the watchdog counter will decrement each bit-time. Note 7-bit-time is added to the programmed value, so a value of zero will set the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also note that the counter is reloaded at the end of each frame, so if the frame is 10 bits long and the timeout counter value is zero, then timeout will occur (when FIFO is not empty) even if the RX input is not idle. The default value is 0x3 (31 bit-time). Number of bytes to receive. This must be a multiple of 4. 30.4.2 UART Transmit DMA Control Register (HW_UARTAPP_CTRL1) The UART Transmit DMA Control Register contains the dynamic information associated with the transmit command. HW_UARTAPP_CTRL1: 0x010 HW_UARTAPP_CTRL1_SET: 0x014 HW_UARTAPP_CTRL1_CLR: 0x018 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2117 Programmable Registers HW_UARTAPP_CTRL1_TOG: 0x01C This register contains the main DMA controls for Transmitting data. Address: 8006_A000h base + 10h offset = 8006_A010h Bit 31 30 29 RSVD2 R Bit 27 26 25 23 22 21 20 19 18 17 16 RSVD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R XFER_COUNT W Reset 24 RUN W Reset 28 0 0 0 0 0 0 0 0 0 HW_UARTAPP_CTRL1 field descriptions Field 31-29 RSVD2 28 RUN 27-16 RSVD1 XFER_COUNT Description Reserved, read as zero, do not modify. Tell the UART to execute the TX DMA Command. The UART will clear this bit at the end of transmit execution. Reserved, read as zero, do not modify. Number of bytes to transmit. 30.4.3 UART Control Register (HW_UARTAPP_CTRL2) The UART Control Register contains configuration, including interrupt FIFO level select and the DMA control. HW_UARTAPP_CTRL2: 0x020 HW_UARTAPP_CTRL2_SET: 0x024 HW_UARTAPP_CTRL2_CLR: 0x028 HW_UARTAPP_CTRL2_TOG: 0x02C Use this register to define the FIFO level at which the UARTTXINTR and UARTRXINTR are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the design is such that the interrupts are generated when the fill level progresses through the trigger level. The bits are reset so that the trigger level is when the FIFOs are at the half-way mark. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2118 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) Address: 8006_A000h base + 20h offset = 8006_A020h 30 29 28 27 26 25 24 22 21 20 19 18 17 16 INVERT_RTS INVERT_CTS INVERT_TX INVERT_RX RTS_SEMAPHORE DMAONERR TXDMAE RXDMAE 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIRLP SIREN UARTEN R 23 RSVD3 31 RSVD2 Bit 0 0 0 RXIFLSEL TXIFLSEL W Reset Bit RSVD4 CTSEN RTSEN OUT2 OUT1 R RTS 0 0 0 0 0 DTR RXE TXE LBE USE_ LCR2 0 1 1 0 0 W Reset 0 0 0 HW_UARTAPP_CTRL2 field descriptions Field Description 31 INVERT_RTS Invert RTS signal. If this bit is set to 1, the RTS output is inverted before transmitted. 30 INVERT_CTS Invert CTS signal. If this bit is set to 1, the CTS input is inverted before sampled. 29 INVERT_TX Invert TX signal. If this bit is set to 1, the TX output is inverted before transmitted. 28 INVERT_RX Invert RX signal. If this bit is set to 1, the RX input is inverted before sampled. 27 RTS_ SEMAPHORE If this bit is set to 1, RTS is deasserted when the semaphore threshold is less than 2. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2119 Programmable Registers HW_UARTAPP_CTRL2 field descriptions (continued) Field 26 DMAONERR Description DMA On Error. If this bit is set to 1, receive dma will terminate on error. (Cmd_end signal may not be asserted when this occurs.) 25 TXDMAE Transmit DMA Enable. Data Register can be loaded with up to 4 bytes per write. TXFIFO must be enabled in TXDMA mode. 24 RXDMAE Receive DMA Enable. Data Register can be contain up to 4 bytes per read. RXFIFO must be enabled in RXDMA mode. 23 RSVD2 22-20 RXIFLSEL 19 RSVD3 18-16 TXIFLSEL Reserved, do not modify, read as zero. Receive Interrupt FIFO Level Select. The trigger points for the receive interrupt are as follows: 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 NOT_EMPTY -- Trigger on FIFO containing at least 2 of 16 entries. ONE_QUARTER -- Trigger on FIFO full to at least 4 of 16 entries. ONE_HALF -- Trigger on FIFO full to at least 8 of 16 entries. THREE_QUARTERS -- Trigger on FIFO full to at least 12 of 16 entries. SEVEN_EIGHTHS -- Trigger on FIFO full to at least 14 of 16 entries. INVALID5 -- Reserved. INVALID6 -- Reserved. INVALID7 -- Reserved. Reserved, do not modify, read as zero. Transmit Interrupt FIFO Level Select. The trigger points for the transmit interrupt are as follows: 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 EMPTY -- Trigger on FIFO less than or equal to 2 of 16 entries. ONE_QUARTER -- Trigger on FIFO less than or equal to 4 of 16 entries. ONE_HALF -- Trigger on FIFO less than or equal to 8 of 16 entries. THREE_QUARTERS -- Trigger on FIFO less than or equal to 12 of 16 entries. SEVEN_EIGHTHS -- Trigger on FIFO less than or equal to 14 of 16 entries. INVALID5 -- Reserved. INVALID6 -- Reserved. INVALID7 -- Reserved. 15 CTSEN CTS Hardware Flow Control Enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. 14 RTSEN RTS Hardware Flow Control Enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. The FIFO space is controlled by RXIFLSEL value. 13 OUT2 This bit is the complement of the UART Out2 (nUARTOut2) modem status output. This bit is not supported. 12 OUT1 This bit is the complement of the UART Out1 (nUARTOut1) modem status output. This bit is not supported. 11 RTS Request To Send. Software can manually control the nUARTRTS pin through this bit when RTSEN = 0. This bit is the complement of the UART request to send (nUARTRTS) modem status output. That is, when the bit is programmed to a 1, the output is 0. 10 DTR Data Transmit Ready. This bit is the complement of the UART data transmit ready (nUARTDTR) modem status output. This bit is not supported. 9 RXE Receive Enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for the UART signals. When the UART is disabled in the middle of reception, it completes the current character before stopping. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2120 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) HW_UARTAPP_CTRL2 field descriptions (continued) Field Description 8 TXE Transmit Enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for the UART signals. When the UART is disabled in the middle of transmission, it completes the current character before stopping. 7 LBE Loop Back Enable. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, the UARTTXD path is fed through to the UARTRXD path. When this bit is set, the modem outputs are also fed through to the modem inputs. 6 USE_LCR2 =If this bit is set to 1, the Line Control 2 Register values are used. 5-3 RSVD4 Reserved, do not modify, read as zero. 2 SIRLP IrDA SIR Low Power Mode. Unsupported. 1 SIREN SIR Enable. Unsupported. 0 UARTEN UART Enable. If this bit is set to 1, the UART is enabled. Data transmission and reception occurs for the UART signals. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 30.4.4 UART Line Control Register (HW_UARTAPP_LINECTRL) HW_UARTAPP_LINECTRL: 0x030 HW_UARTAPP_LINECTRL_SET: 0x034 HW_UARTAPP_LINECTRL_CLR: 0x038 HW_UARTAPP_LINECTRL_TOG: 0x03C The UART Line Control Register contains integer and fractional part of the baud rate divisor value. It also contains the line control bits. Address: 8006_A000h base + 30h offset = 8006_A030h Bit 31 30 29 28 27 26 25 R Bit R 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FEN STP2 EPS PEN BRK 0 0 0 0 0 RSVD BAUD_DIVFRAC W Reset 23 BAUD_DIVINT W Reset 24 0 0 0 0 0 0 SPS 0 0 0 WLEN 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2121 Programmable Registers HW_UARTAPP_LINECTRL field descriptions Field 31-16 BAUD_DIVINT 15-14 RSVD Description Baud Rate Integer [15:0]. The integer baud rate divisor. Reserved, do not modify, read as zero. 13-8 Baud Rate Fraction [5:0]. The fractional baud rate divisor. BAUD_DIVFRAC 7 SPS Stick Parity Select. When bits 1, 2, and 7 of this register are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this bit is cleared stick parity is disabled. 6-5 WLEN Word length [1:0]. The select bits indicate the number of data bits transmitted or received in a frame as follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits. 4 FEN Enable FIFOs. If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, the FIFOs are disabled (character mode); that is, the FIFOs become 1-byte-deep holding registers. 3 STP2 Two Stop Bits Select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. 2 EPS Even Parity Select. If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed which checks for an odd number of 1s. This bit has no effect when parity is disabled by Parity Enable (PEN, bit 1) being cleared to 0. 1 PEN Parity Enable. If this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no parity bit added to the data frame. 0 BRK Send Break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. 30.4.5 UART Line Control 2 Register (HW_UARTAPP_LINECTRL2) HW_UARTAPP_LINECTRL2: 0x040 HW_UARTAPP_LINECTRL2_SET: 0x044 HW_UARTAPP_LINECTRL2_CLR: 0x048 HW_UARTAPP_LINECTRL2_TOG: 0x04C The UART Line Control 2 Register contains integer and fractional part of the baud rate divisor value. It also contains the line control bits. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2122 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) Address: 8006_A000h base + 40h offset = 8006_A040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BAUD_DIVINT W Bit R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FEN STP2 EPS PEN 0 0 0 0 RSVD1 Reset RSVD BAUD_DIVFRAC SPS WLEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_UARTAPP_LINECTRL2 field descriptions Field 31-16 BAUD_DIVINT 15-14 RSVD Description Baud Rate Integer [15:0]. The integer baud rate divisor. Reserved, do not modify, read as zero. 13-8 Baud Rate Fraction [5:0]. The fractional baud rate divisor. BAUD_DIVFRAC 7 SPS Stick Parity Select. When bits 1, 2, and 7 of this register are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this bit is cleared stick parity is disabled. 6-5 WLEN Word length [1:0]. The select bits indicate the number of data bits transmitted or received in a frame as follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits. 4 FEN Enable FIFOs. If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, the FIFOs are disabled (character mode); that is, the FIFOs become 1-byte-deep holding registers. 3 STP2 Two Stop Bits Select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. 2 EPS Even Parity Select. If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed which checks for an odd number of 1s. This bit has no effect when parity is disabled by Parity Enable (PEN, bit 1) being cleared to 0. 1 PEN Parity Enable. If this bit is set to 1, parity checking and generation is enabled, else parity is disabled and no parity bit added to the data frame. 0 RSVD1 Reserved, do not modify, read as zero. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2123 Programmable Registers 30.4.6 UART Interrupt Register (HW_UARTAPP_INTR) HW_UARTAPP_INTR: 0x050 HW_UARTAPP_INTR_SET: 0x054 HW_UARTAPP_INTR_CLR: 0x058 HW_UARTAPP_INTR_TOG: 0x05C The UART Interrupt Register contains the interrupt enables and the interrupt status. The interrupt status bits report the unmasked state of the interrupts. To clear a particular interrupt status bit, write the bit-clear address with the particular bit set to 1. The enable bits control the UART interrupt output: a 1 will enable a particular interrupt to assert the UART interrupt output, while a 0 will disable the particular interrupt from affecting the interrupt output. All the bits, except for the modem status interrupt bits, are cleared to 0 when reset. The modem status interrupt bits are undefined after reset. Address: 8006_A000h base + 50h offset = 8006_A050h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD1 ABDIEN OEIEN BEIEN PEIEN FEIEN RTIEN TXIEN RXIEN DSRMIEN DCDMIEN CTSMIEN RIMIEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEIS FEIS RTIS TXIS RXIS DSRMIS DCDMIS CTSMIS RIMIS R 0 0 0 0 0 0 0 0 0 W Reset Bit RSVD2 ABDIS R OEIS BEIS W Reset 0 0 0 0 0 0 0 HW_UARTAPP_INTR field descriptions Field 31-28 RSVD1 Description Reserved, read as zero, do not modify. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2124 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) HW_UARTAPP_INTR field descriptions (continued) Field 27 ABDIEN Description Automatic Baudrate Detected Interrupt Enable. 26 OEIEN Overrun Error Interrupt Enable. 25 BEIEN Break Error Interrupt Enable. 24 PEIEN Parity Error Interrupt Enable. 23 FEIEN Framing Error Interrupt Enable. 22 RTIEN Receive Timeout Interrupt Enable. 21 TXIEN Transmit Interrupt Enable. 20 RXIEN Receive Interrupt Enable. 19 DSRMIEN nUARTDSR Modem Interrupt Enable. This bit is not supported. 18 DCDMIEN nUARTDCD Modem Interrupt Enable. This bit is not supported. 17 CTSMIEN nUARTCTS Modem Interrupt Enable. 16 RIMIEN nUARTRI Modem Interrupt Enable. This bit is not supported. 15-12 RSVD2 Reserved, read as zero, do not modify. 11 ABDIS Automatic Baudrate Detected Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. 10 OEIS Overrun Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. 9 BEIS Break Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. 8 PEIS Parity Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. 7 FEIS Framing Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. 6 RTIS Receive Timeout Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. 5 TXIS Transmit Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. 4 RXIS Receive Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. 3 DSRMIS nUARTDSR Modem Interrupt Status. This bit is not supported. 2 DCDMIS nUARTDCD Modem Interrupt Status. This bit is not supported. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2125 Programmable Registers HW_UARTAPP_INTR field descriptions (continued) Field 1 CTSMIS 0 RIMIS Description nUARTCTS Modem Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1. nUARTRI Modem Interrupt Status. This bit is not supported. 30.4.7 UART Data Register (HW_UARTAPP_DATA) The UART Data Register is the receive and transmit data register. Receive (read) and transmit (write) up to four data characters per APB cycle. For words to be transmitted: 1) If the FIFOs are enabled, data written to this location is pushed onto the transmit FIFO; 2) If the FIFOs are not enabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the PrimeCell UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. Note: With the use of APB byte-enables you can write 1, 2, or 4 valid bytes sumultaneously to the TXFIFO. The invalid bytes will also take up space in the TXFIFO. So every write cycle will consume 4 bytes in the TXFIFO. If TXFIFO is disabled, you must only write the LSByte of the DATA register. For received words: 1) If the FIFOs are enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO; 2) if the FIFOs are not enabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data bytes (up to 4) are read by performing reads from the 32-bit DATA register. The status information can be read by a read of the UART Status register. The Overrun Error bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. The Break Error bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a fullword transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. When the Parity Error bit is set to 1, it indicates that the parity of the received data character does not match the parity selected as defined by bits 2 and 7 of the LCR_H register. In FIFO mode, this error is associated with the character at the top of the FIFO. When the Framing Error bit is set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2126 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) Address: 8006_A000h base + 60h offset = 8006_A060h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_UARTAPP_DATA field descriptions Field DATA Description In DMA mode, up to 4 Received/Transmit characters can be accessed at a time. In PIO mode, only one character can be accessed at a time. The status register contains the receive data flags and valid bits. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2127 Programmable Registers 30.4.8 UART Status Register (HW_UARTAPP_STAT) The UART Status Register contains the various flags and receive status. If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the UART Data Register prior to reading the UART Status Register. The status information for overrun is set immediately when an overrun condition occurs. 30 29 28 27 26 25 24 CTS TXFE RXFF TXFF RXFE 23 22 21 20 19 18 17 16 1 1 0 0 1 0 0 1 1 1 1 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 OERR HISPEED R 31 PRESENT Bit BUSY Address: 8006_A000h base + 70h offset = 8006_A070h RXBYTE_INVALID BERR PERR FERR W Reset Bit RXCOUNT R W Reset 0 0 0 0 0 0 0 0 0 HW_UARTAPP_STAT field descriptions Field 31 PRESENT Description This read-only bit indicates that the Application UART function is present when it reads back a one. This Application UART function is not available on a device that returns a zero for this bit field. 0x0 0x1 UNAVAILABLE -- UARTAPP is not present in this product. AVAILABLE -- UARTAPP is present in this product. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2128 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) HW_UARTAPP_STAT field descriptions (continued) Field 30 HISPEED Description This read-only bit indicates that the high-speed function is present when it reads back a one. This high speed function is not available on a device that returns a zero for this bit field. 0x0 0x1 29 BUSY UNAVAILABLE -- HISPEED is not present in this product. AVAILABLE -- HISPEED is present in this product. UART Busy. 28 CTS Clear To Send. 27 TXFE Transmit FIFO Empty. The meaning of this bit depends on the state of the FEN bit in the UART Line Control Register. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. 26 RXFF Receive FIFO Full. 25 TXFF Transmit FIFO Full. 24 RXFE Receive FIFO Empty. 23-20 RXBYTE_ INVALID The invalid state of the last read of Receive Data. Each bit corresponds to one byte of the RX data. (1 = invalid.) 19 OERR Overrun Error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by any write to the Status Register. The FIFO contents remain valid since no further data is written when the FIFO is full; only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. 18 BERR Break Error. For PIO mode, this is for the last character read from the data register. For DMA mode, it will be set to 1 if any received character for a particular RXDMA command had a Break Error. To clear this bit, write a zero to it. Note that clearing this bit does not affect the interrupt status, which must be cleared by writing the interrupt register. 17 PERR Parity Error. For PIO mode, this is for the last character read from the data register. For DMA mode, it will be set to 1 if any received character for a particular RXDMA command had a Parity Error. To clear this bit, write a zero to it. Note that clearing this bit does not affect the interrupt status, which must be cleared by writing the interrupt register. 16 FERR Framing Error. For PIO mode, this is for the last character read from the data register. For DMA mode, it will be set to 1 if any received character for a particular RXDMA command had a Framing Error. To clear this bit, write a zero to it. Note that clearing this bit does not affect the interrupt status, which must be cleared by writing the interrupt register. RXCOUNT Number of bytes received during a Receive DMA command. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2129 Programmable Registers 30.4.9 UART Debug Register (HW_UARTAPP_DEBUG) The UART Debug Register contains the state of the DMA signals. Address: 8006_A000h base + 80h offset = 8006_A080h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXIBAUD_DIV R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCMDEND RXCMDEND TXDMARQ RXDMARQ Bit 0 RXDMARUN Reset TXDMARUN W 0 0 0 0 0 0 RXFBAUD_DIV R RSVD1 W Reset 0 0 0 0 0 0 0 0 0 0 HW_UARTAPP_DEBUG field descriptions Field 31-16 RXIBAUD_DIV Description RX Integer Baud Divisor. 15-10 RX Fractional Baud Divisor. RXFBAUD_DIV 9-6 RSVD1 Reserved, read as zero, do not modify. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2130 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) HW_UARTAPP_DEBUG field descriptions (continued) Field Description 5 TXDMARUN DMA Command Run Status: This bit reflects the state of the toggle signal for TXDMARUN. 4 RXDMARUN DMA Command Run Status: This bit reflects the state of the toggle signal for RXDMARUN. 3 TXCMDEND DMA Command End Status: This bit reflects the state of the toggle signal for UART_TXCMDEND. 2 RXCMDEND DMA Command End Status: This bit reflects the state of the toggle signal for UART_RXCMDEND. 1 TXDMARQ DMA Request Status: This bit reflects the state of the toggle signal for UART_TXDMAREQ. Note that TX burst request is not supported. 0 RXDMARQ DMA Request Status: This bit reflects the state of the toggle signal for UART_RXDMAREQ. Note that RX burst request is not supported. 30.4.10 UART Version Register (HW_UARTAPP_VERSION) The UART version register can be used to read the version of the UARTAPP IP being used in this chip. Address: 8006_A000h base + 90h offset = 8006_A090h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 HW_UARTAPP_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of RTL version. STEP Fixed read-only value reflecting the stepping of RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2131 Programmable Registers 30.4.11 UART AutoBaud Register (HW_UARTAPP_AUTOBAUD) The UART AutoBaud register provides the reference characters and control info for the automatic baudrate detection logic. Address: 8006_A000h base + A0h offset = 8006_A0A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R REFCHAR1 REFCHAR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 START_WITH_RUNBIT START_BAUD_DETECT BAUD_DETECT_ENABLE Bit 0 TWO_REF_CHARS Reset UPDATE_TX W 0 0 0 0 0 0 0 0 0 0 RSVD1 R W Reset 0 0 0 0 0 0 HW_UARTAPP_AUTOBAUD field descriptions Field 31-24 REFCHAR1 Description Second reference character used in baud rate detection. During autobaud detection of the second reference frame is stripped from the incoming packet. So it will not appear in the RXFIFO. This field is ignored when TWO_REF_CHARS is 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2132 Freescale Semiconductor, Inc. Chapter 30 Application UART (AUART) HW_UARTAPP_AUTOBAUD field descriptions (continued) Field 23-16 REFCHAR0 Description First reference character used in baud rate detection. During autobaud detection of the first reference frame received is not available for reading. It is stripped from the incoming packet, so the UART receiver does not get this character and the RXFIFO is not updated. 15-5 RSVD1 Reserved, read as zero, do not modify. 4 UPDATE_TX Set this bit to 1 will cause the TX baud rate divisor to be updated when the RX baud rate divisor is updated by the autobaud detection logic. This should not be set if it is possible that transmit function may be busy. 3 TWO_REF_ CHARS Set this bit to 1 when using 2 reference characters for baud detection, and set to 0 for 1 reference character. 2 Set this bit to 1 will cause the assertion of HW_UARTAPP_CTRL0_RUN to start the autobaud detection START_WITH_ logic. RUNBIT Set this bit to 0 will cause the assertion of START_BAUD_DETECT to start the autobaud detection logic. 1 Set to 1 to start automatic baudrate detection. This bit is ignored when START_WITH_RUNBIT is set to 1. START_BAUD_ Each time a 1 is written to START_BAUD_DETECT it toggles the read value if START_WITH_RUNBIT is DETECT zero. 0 Enable automatic baudrate detection. BAUD_DETECT_ ENABLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2133 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2134 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.1 Overview i.MX28 has two USB high-speed controllers, the first one is a OTG-capable USB high speed controller (OTG), and the second one is host-only high-speed USB controller (HOST). This chapter describes the USB high-speed OTG-capable controller (OTG) included on the i.MX28. The host-only high-speed USB controller (HOST) is a subset of the OTG-capable controller (OTG). This chapter includes sections on the PIO, DMA, and UTMI interfaces, along with USB controller flowcharts. The i.MX28 includes a Universal Serial Bus (USB) version 2.0 controller capable of operating as either a USB device or a USB host, as shown in Figure 31-1. In addition, OTG contains supporting circuitry for USB On-the-Go (OTG). HOST is configured as host-only controller. The USB controller is used to download digital music data or program code into external memory and to upload voice recordings from memory to the PC. Program updates can also be loaded into the flash memory area using the USB interface. As a host controller, it can enumerate and control USB devices attached to it. The USB controller included on the i.MX28 supports eight endpoints: one control, one bulk-out, one bulk-in, and five flexible endpoints. Using the OTG features, the USB controller can negotiate with another OTG system to be either the host or the device in a peer connection. The USB controller operates either in full-speed mode or high-speed mode. Refer to the USB Implementer's Forum website www.usb.org for detailed specifications and information on the USB protocol, timing and electrical characteristics. The USB 2.0 controller comprises both a programmed I/O (PIO) interface and a DMA interface. Both of these interfaces are designed to meet an ARM Ltd. AMBA Hardware Bus (AHB). The AHB is used by the USB controller as a slave (PIO register accesses) and as a master (DMA memory accesses). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2135 Overview The USB 2.0 PHY is fully integrated on-chip and is described in USB PHY Overview. The PHY is controlled over the APBX peripheral bus. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2136 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller ARM Core SRAM EMI AHB AHB Slave AHB-to-APBX Bridge APBX APBX Master Programmed I/O Target Inteface * Bus Interface * Control and Status * Interrupts DMA Engine * Bus Interface * Endpoint Priming State Machine * Data Movement Dual Port RAM Controller * Virtual FIFO Channels * DMA Contexts On-Chip Dual Port Synchronous SRAM Protocol Engine * Interval Timers * Error Handling * CRC Handling USB 2.0 Device/ Host/OTG Controller Port Controller * Asynchronous Clock Domain Crossing * Transceiver Interface Logic USB UTM Interface USB Interface Block PHY Registers 480-MHz PLL USB Xcvr Integrated USB 2.0 PHY Figure 31-1. USB 2.0 Device Controller Block Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2137 Functional Description 31.2 Functional Description These sections describe the functionality of the various building blocks of the USB. 31.2.1 Difference between OTG and HOST OTG is the High speed OTG-capable USB controller and HOST is the host only high speed USB controller. OTG is capable of supplying VBUS, while HOST is for connection to on-system (onboard) connectivity peripherals such as cellular modems and no support of VBUS. 31.2.2 USB Programmed I/O (PIO) Target Interface The PIO interface is on an AHB slave of the USB controller. It allows the ARM processor to access the configuration, control, and status registers. There are identification registers for hardware configuration parameters and operational registers for control and status. 31.2.3 USB DMA Interface The DMA is a master AHB interface that allows USB data to be transferred to/from the system memory. The data in memory is structured to implement a software framework supported by the controller. For a device controller, this structure is a linked-list interface that consists of queue heads and pointers that are transfer descriptors. The queue head is where transfers are managed. It has status information and location of the data buffers. The hardware controller's PIO registers enable the entire data structure, and once USB data is transferred between the host, the status of the transfer is updated in the queue head, with minimal latency to the system. For a host controller, there is also a linked-list interface. It consists of a periodic frame list and pointers to transfer descriptors. The period frame list is a schedule of transfers. The frame list points to the data buffers through the transfer descriptors. The hardware controller's PIO registers enable the data structure and manage the transfers within a USB frame. The period frame list works as a sliding window of host transfers over time. As each transfer is completed, the status information is updated in the frame list. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2138 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.4 USB UTM Interface The USB UTM interface on the i.MX28 implements the specification that allows USB controllers to interface with the USB PHY. Please refer to the USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.05, for additional details: http:// www.intel.com/technology/usb/spec.htm 31.2.4.1 Digital/Analog Loopback Test Mode Since the UTM has to operate at high frequencies (480 MHz), it has a capacity to selftest. A pseudo-random number generator transmits data to the receive path, and data is compared for validity. In the digital loopback, the data transfer only resides in the UTM. It checks for sync, EOP, and bit-stuffing generation and data integrity. The analog loopback is the same as the digital loopback, but involves the analog PHY. This allows for checking of the high-speed (HS) and full-speed (FS) comparators and transmitters. 31.2.5 USB Controller Flowcharts i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2139 Functional Description Start NO HW_POWER_STS_ VDD5V_GT_VDDIO Check for 5-V input YES HW_USBPHY_CTRL_ SFTRST Play_Startup Set HW_USBPHY_DEBUG_ENHSTPULLDOWN Clear HW_USBPHY_DEBUG_HSTPULLDOWN Set HW_USBPHY_CTRL_ENDEVPLUGINDETECT Wait for 1 microsecond NO HW_USBPHY_ STATUS_DEVPLUGIN _STATUS DONE Figure 31-2. USB 2.0 Check_USB_Plugged_In Flowchart i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2140 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller PHY Startup Clear HW_USBPHY_CTRL_SFTRST Clear HW_USBPHY_CTRL_CLKGATE Clear HW_USBPHY_PWD Clear HW_POWER_CTRL_CLKGATE Set HW_POWER_DEBUG_VBUSVALIDPIOLOCK Set HW_POWER_DEBUG_AVALIDPIOLOCK Set HW_POWER_DEBUG_BVALIDPIOLOCK Device and Host operation not OTG Set HW_POWER_STS_BVALID Set HW_POWER_STS_AVALID Set HW_POWER_STS_VBUSVALID Set CPU Clock to 1.2 MHz Set HW_CLKCTRL_CPU_DIV_CPU=400 Set GPMI Clock to 1.2 MHz Set HW_CLKCTRL_GPMI_DIV=400 Set HW_CLKCTRL_XBUS_DIV=20 Make sure XBUS is lower than HBUS Power on PLL Set HW_CLKCTRL_PLLCTRL0_POWER NO HW_CLKCTRL _ PLLCTRL1_ LOCK==1 YES Switch to PLL from Crystal Clear HW_CLKCTRL_CLKSEQ_BYPASS_CPU Set HW_CLKCTRL_XBUS_DIV=1 Set HW_CLKCTRL_PLLCTRL0_EN_USB_CLKS Figure 31-3. USB 2.0 USB PHY Startup Flowchart i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2141 Functional Description ARC IRQ To Other ARC ISR NO ARC Suspend Interrupt? YES Set HW_USBPHY_CTRL_ENIRQRESUMEDETECT PHY Shut Down Set all power-down bits in HW_USBPHY_PWD Set HW_DIGCTRL_CTRL_USB_CLKGATE PLL Bypass, switches to XTAL Set HW_CLKCTRL_CLKSEQ BYPASS bits Clear HW_CLKCTRL_PLLCTRL0_POWER Figure 31-4. USB 2.0 PHY PLL Suspend Flowchart Clear HW_DIGCTL_CTRL_USB_CLKGATE Clear HW_USBPHY_CTRL_SFTRST Clear HW_USBPHY_CTRL_CLKGATE Prepare USB controller to deassert UTMI_RESET Set HW_DIGCTL_CTRL_USB_CLKGATE Set all power-down bits in HW_USBPHY_PWD Figure 31-5. UTMI Powerdown 31.2.5.1 References * USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.05, March 2001, Jon Lueker, Steve McGowan (Editor) Ken Oliver, Dean Warren. http:// www.intel.com * VSI Alliance Virtual Component Interface Standard, Version 2 (OCB 2 2.0), April 2001, On-Chip Bus Development Working Group. http://www.vsi.org * Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, HewlettPackard, Intel, Lucent, Microsoft, NEC, Philips. http://www.usb.org i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2142 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller * On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0, Dec 2001, OnThe-Go Working Group of the USB-IF. http://www.usb.org * Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95, November 2000, Intel Corporation. http://www.intel.com * Universal Serial Bus Specification, Revision 1.1, September 1998, Compaq, Intel, Microsoft, NEC. http://www.usb.org * AMBA Specification, Revision 2.0, May 1999, ARM Limited. http://www.arm.com * UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.0 February 2004, ULPI Specification Organization. http://www.ulpi.org 31.2.6 USB Operation Model This section describes the detailed application knowledge for Host and OTG ports. It can be generally divided in two parts, one for Host and the other for Device. Host part applies to the host port, and to OTG port when operating in Host mode. Device part only applies to all OTG ports when operating in Device mode. 31.2.6.1 OTG Operations 31.2.6.1.1 Register Bits In the previous section, the Register interface has behaviors described for device mode and behaviors described for host mode. However, for OTG operations it is necessary to perform tasks independent of the controller mode. Note that the only way to transit the controller mode out of host or device mode is with the controller reset bit. Therefore, it is also necessary for the OTG tasks to be performed independent of a controller reset as well as independent of the controller mode. The following figure shows the controller mode. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2143 Functional Description Hardware Reset or USBCMD.Reset = 1 Idle (00) Write "10" to USBMODE Write "11" to USBMODE Device (10) Host (11) Figure 31-6. Controller Mode To this end, listed below are the register bits that are used for OTG operations, which are independent of the controller mode and are also not affected by a write to the reset bit in the USBCMD register: All Identification Registers All Device/Host Capability Registers OTGSC: All bits PORTSC1: Physical Interface Select Physical Interface Serial Select Physical Interface Data Width Physical Interface Low Power Physical Interface Wake Signals Port Indicators Port Power i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2144 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.1.2 Hardware Assist The hardware assist provides automated response and sequencing that may not be possible to software with significant interrupt latency response times. The use of this additional circuitry is optional and can be used to assist the 3 sequences below. 31.2.6.1.2.1 Auto-Reset When the HAAR is set to one, the host automatically starts a reset after a connect event. This shortcuts the normal process where software is notified of the connect event and starts the reset. Software still receives notification of the connect event but should not write the reset bit when the HAAR is set. Software is notified again after the reset is complete via the enable change bit in the USB_PORTSC1 register which cause a port change interrupt. This assist ensures the OTG parameter TB_ACON_BSE0_MAX = 1ms is met. 31.2.6.1.2.2 Data-Pulse Writing one to HADP starts a data pulse of approximately 7ms and then automatically cease the data pulsing. During the data pulse, the DP is set and then cleared. This automation relieves software from accurately controlling the data-pulse duration. During the data pulse, the HCD can poll to see that the HADP and DP bit have returned low to recognize the completion or simply launch the data pulse and wait to see if a VBUS Valid interrupt occurs when the A-side supplies bus power. This assist ensures data pulsing meets the OTG requirement of > 5ms and < 10ms. 31.2.6.1.2.3 B-Disconnect to A-Connect During HNP, the B-disconnect occurs from the OTG A_suspend state and within 3 ms, the A device must enable the pullup on the DP leg in the A-peripheral state. When HABA is set, the Host Controller port is in suspend mode, and the device disconnects, then this hardware assist begins. 1. Reset the OTG core. 2. Write the OTG core into device mode. 3. Write the device run bit to 1 and enable necessary interrupts including: USB Reset Enable (URE); enables interrupt on usb bus reset to device Sleep Enable (SLE); enables interrupt on device suspend i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2145 Functional Description Port Change Detect Enable (PCE); enables interrupt on device connect When software has enabled this hardware assist, it must not interfere during the transition and should not write any register in the core until it gets an interrupt from the device controller signifying that a reset interrupt has occurred or at least first verify that the core has entered device mode. HCD/DCD must not activate the core soft reset at any time because this action is performed by hardware. During the transition, the software may see an interrupt from the disconnect and/or other spurious interrupts (that is SOF, and so on) that may or may not cascade and may be cleared by the soft reset depending on the software response time. After the core has entered device mode by the hardware assist, the DCD must ensure that the USB_ENDPTLISTADDR is programmed properly before the host sends a setup packet. Because the end of the reset duration, which may be initiated quickly (a few microseconds) after connect, will require at a minimum 50 ms, this is the time for which the DCD must be ready to accept setup packets after having received notification that the reset has been detected or simply that the OTG is in device mode which ever occurs first. In the case where the A-peripheral fails to see a reset after the controller enters device mode and engages the DP-pullup, the device controller interrupt the DCD signifying that a suspend has occurred. This assist ensures the parameter TA_BDIS_ACON_MAX = 3ms is met. 31.2.6.2 Host Data Structures This section defines the interface data structures used to communicate control, status, and data between HCD (software) and the Enhanced Host Controller (hardware). The data structure definitions in this chapter support a 32-bit memory buffer address space. The interface consists of a Periodic Schedule, Periodic Frame List, Asynchronous Schedule, Isochronous Transaction Descriptors, Split-transaction Isochronous Transfer Descriptors, Queue Heads, and Queue Element Transfer Descriptors. The periodic frame list is the root of all periodic (isochronous and interrupt transfer type) transfers for the host controller. The asynchronous list is the root for all the bulk and control transfers. Isochronous data streams are managed using Isochronous Transaction Descriptors. Isochronous split-transaction data streams are managed with Splittransaction Isochronous Transfer Descriptors. All Interrupt, Control, and Bulk data streams are managed via queue heads and Queue Element Transfer Descriptors. These data structures are optimized to reduce the total memory footprint of the schedule and to reduce (on average) the number of memory accesses needed to execute a USB transaction. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2146 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Note that software must ensure that no interface data structure reachable by the EHCI host controller spans a 4 K-page boundary. The data structures defined in this section are (from the host controller's perspective) a mix of read-only and read/writeable fields. The host controller must preserve the readonly fields on all data structure writes. 31.2.6.2.1 Periodic Frame List This schedule is for all periodic transfers (isochronous and interrupt). The periodic schedule is referenced from the operational registers space using the USB_PERIODICLISTBASE address register and the USB_FRINDEX register. The periodic schedule is based on an array of pointers called the Periodic Frame List. The USB_PERIODICLISTBASE address register is combined with the USB_FRINDEX register to produce a memory pointer into the frame list. The Periodic Frame List implements a sliding window of work over time. The following figure shows the organization of periodic schedule. Periodic Frame List Operational Registers 1024, 512, or 256 elements FRINDEX PeriodicList Base . . . . . . Isochronous Transfer Descriptor(s) Last Periodic has end of List Mark A A A A . . . 1 4 A A Periodic Frame 8 A A List Element Address Poll Rate: N ---> 1 Interrupt Queue] Heads Figure 31-7. Periodic Schedule Organization i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2147 Functional Description Split transaction Interrupt, Bulk and Control are also managed using queue heads and queue element transfer descriptors. The periodic frame list is a 4 K-page aligned array of Frame List Link pointers. The length of the frame list may be programmable. The programmability of the periodic frame list is exported to system software via the USB_HCCPARAMS register. If nonprogrammable, the length is 1024 elements. If programmable, the length can be selected by system software as one of 256, 512, or 1024 elements. An implementation must support all three sizes. Programming the size (that is, the number of elements) is accomplished by system software writing the appropriate value into Frame List Size field in the USB_USBCMD register. Frame List Link pointers direct the host controller to the first work item in the frame's periodic schedule for the current micro-frame. The link pointers are aligned on DWord boundaries within the Frame List. The table below illustrates the format of the Frame list element pointer. Table 31-1. Format of Frame List Element Pointer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Frame List Link Pointer 6 5 4 0 3 2 1 Typ 0 03-00H Frame List Link pointers always reference memory objects that are 32-byte aligned. The referenced object may be an isochronous transfer descriptor for high-speed devices, a split-transaction isochronous transfer descriptor (for full-speed isochronous endpoints), or a queue head (used to support high-, full- and low-speed interrupt). System software should not place non-periodic schedule items into the periodic schedule. The least significant bits in a frame list pointer are used to key the host controller as to the type of object the pointer is referencing. The least significant bit is the T-Bit (bit 0). When this bit is set to a one, the host controller never uses the value of the frame list pointer as a physical memory pointer. The Typ field is used to indicate the exact type of data structure being referenced by this pointer. The value encodings are. Table 31-2. Typ Field Value Definitions Value Meaning 00b Isochronous Transfer Descriptor 01b Queue Head 10b Split Transaction Isochronous Transfer Descriptor. 11b Frame Span Traversal Node. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2148 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.2.2 Asynchronous List Queue Head Pointer The Asynchronous Transfer List (based at the USB_ASYNCLISTADDR register) is where all of the control and bulk transfers are managed. Host controllers use this list only when it reaches the end of the periodic list, the periodic list is disabled, or the periodic list is empty. Operational Registers Bulk/Control Queue Heads AsynListAddr H Figure 31-8. Asynchronous Schedule Organization The Asynchronous list is a simple circular list of queue heads. The USB_ASYNCLISTADDR register is simply a pointer to the next queue head. This implements a pure round-robin service for all queue heads linked into the asynchronous list. 31.2.6.2.3 Isochronous (High-Speed) Transfer Descriptor (iTD) The format of an isochronous transfer descriptor is shown in the table below. This structure is used only for high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous TDs must be aligned on a 32-byte boundary. Table 31-3. Isochronous Transaction Descriptor (iTD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Next Link Pointer Status 5 4 0 Transaction 0 Length IO PG* C Transaction 0 Offset* 3 2 1 Typ 0 T 03-00 H 07-04 H Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2149 Functional Description Table 31-3. Isochronous Transaction Descriptor (iTD) (continued) Status Transaction 1 Length IO PG* C Transaction 1 Offset* 0B-0 8H Status Transaction 2 Length IO PG* C Transaction 2 Offset* 0F-0 CH Status Transaction 3 Length IO PG* C Transaction 3 Offset* 13-10 H Status Transaction 4 Length IO PG* C Transaction 4 Offset* 17-14 H Status Transaction 5 Length IO PG* C Transaction 5 Offset* 1B-1 8H Status Transaction 6 Length IO PG* C Transaction 6 Offset* 1F-1 CH Status Transaction 7 Length IO PG* C Transaction 7 Offset* 23-20 H Buffer Pointer (Page 0) EndPt 27-24 H Buffer Pointer (Page 1) I/ Maximum Packet Size O Buffer Pointer (Page 2) - Buffer Pointer (Page 3) - 33-30 H Buffer Pointer (Page 4) - 37-34 H Buffer Pointer (Page 5) - 3B-3 8H Buffer Pointer (Page 6) - 3F-3 CH Host Controller Read/Write R Device Address 2B-2 8H Mult 2F-2 CH Host Controller Read Only These fields may be modified by the host controller if the I/O field indicates an OUT. 31.2.6.2.3.1 Next Link Pointer The first DWord of an iTD is a pointer to the next schedule data structure. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2150 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller The following table describes the Next Schedule Element pointer field. Table 31-4. Next Schedule Element Pointer Bit Description 31-5 Link Pointer (LP) 4-3 Reserved These bits correspond to memory address signals [31:5], respectively. This field points to another Isochronous Transaction Descriptor (iTD/siTD) or Queue Head (QH). These bits are reserved and their value has no effect on operation. Software should initialize this field to zero. 2-1 This field indicates to the Host Controller whether the item referenced is an iTD, siTD or a QH. This allows the Host Controller to perform the proper type of processing on the item after it is fetched. Value QH/(s)iTD Select encodings are: (Typ) Value Meaning 00b iTD (isochronous transfer descriptor) 01b QH (queue head) 10b siTD (split transaction isochronous transfer descriptor 11b FSTN (frame span traversal node) 0 1= Link Pointer field is not valid. 0= Link Pointer field is valid. Terminate (T) 31.2.6.2.3.2 iTD Transaction Status and Control List DWords 1 through 8 are eight slots of transaction control and status. Each transaction description includes: * Status results field * Transaction length (bytes to send for OUT transactions and bytes received for IN transactions). * Buffer offset. The PG and Transaction X Offset fields are used with the buffer pointer list to construct the starting buffer address for the transaction. The host controller uses the information in each transaction description plus the endpoint information contained in the first three DWords of the Buffer Page Pointer list, to execute a transaction on the USB. The following table describes iTD Transaction Status and Control fields. Table 31-5. iTD Transaction Status and Control Bit 31-28 Status Description This field records the status of the transaction executed by the host controller for this slot. This field is a bit vector with the following encoding: Bit Definition 31 Active. Set to one by software to enable the execution of an isochronous transaction by the Host Controller. When the transaction associated with this descriptor is completed, the Host Controller sets this bit to zero indicating that a transaction for this element should not be executed when it is next encountered in the schedule. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2151 Functional Description Table 31-5. iTD Transaction Status and Control (continued) Bit 27-16 Transaction X Length 15 Interrupt On Complete (IOC) 14-12 Page Select (PG) 11-0 Transaction X Offset 31.2.6.2.3.3 Description 30 Data Buffer Error. Set to a one by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). If an overrun condition occurs, no action is necessary. 29 Babble Detected. Set to one by the Host Controller during status update when" babble" is detected during the transaction generated by this descriptor. 28 Transaction Error (XactErr). Set to one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions. For an OUT, this field is the number of data bytes the host controller sends during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer. For an IN, the initial value of the endpoint to deliver. During the status update, the host controller writes back the field is the number of bytes the host expects the number of bytes successfully received. The value in this register is the actual byte count (0zero length data, 1one byte, 2two bytes, etc.). The maximum value this field may contain is 0xC00 (3072). If this bit is set to one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold. These bits are set by software to indicate which of the buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6. This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. This field is concatenated onto the buffer page pointer indicated in the adjacent PG field to produce the starting buffer address for this transaction. iTD Buffer Page Pointer List (Plus) DWords 9-15 of an isochronous transaction descriptor are nominally page pointers (4 K aligned) to the data buffer for this transfer descriptor. This data structure requires the associated data buffer to be contiguous (relative to virtual memory), but allows the physical memory pages to be non-contiguous. Seven page pointers are provided to support the expression of eight isochronous transfers. The seven pointers allow for 3 (transactions) * 1024 (maximum packet size) * 8 (transaction records) (24576 bytes) to be moved with this data structure, regardless of the alignment offset of the first page. Because each pointer is a 4 K aligned page pointer, the least significant 12 bits in several of the page pointers are used for other purposes. The tables below illustrate the field descriptions. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2152 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-6. iTD Buffer Pointer Page 0 (Plus) Bit Description 31-12 Buffer Pointer (Page 0) 11-8 Endpoint Number (Endpt) 7 This is a 4 K aligned pointer to physical memory. Corresponds to memory address bits [31:12]. This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. Bit reserved for future use and should be initialized by software to zero. Reserved 6-0 This field selects the specific device serving as the data source or sink. Device Address Table 31-7. iTD Buffer Pointer Page 1 (Plus) Bit Description 31-12 Buffer Pointer (Page 1) 11 This is a 4K aligned pointer to physical memory. Corresponds to memory address bits [31:12]. 0 = OUT; 1 = IN. This field encodes whether the high-speed transaction should use an IN or OUT PID. Direction (I/O) 10-0 Maximum Packet Size This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize). This field is used for high-bandwidth endpoints where more than one transaction is issued per transaction description (per micro-frame). This field is used with the Multi field to support high-bandwidth pipes. This field is also used for all IN transfers to detect packet babble. Software should not set a value larger than 1024 (400h). Any value larger yields undefined results. Table 31-8. iTD Buffer Pointer Page 2 (Plus) Bit Description 31-12 This is a 4K aligned pointer to physical memory. Corresponds to memory address bits [31:12]. Buffer Pointer 11-2 This bit reserved for future use and should be set to zero. Reserved 1-0 This field is used to indicate to the host controller the number of transactions that should be executed per transaction description (per micro-frame). The valid values are: Multi Value Meaning 00b Reserved. A zero in this field yields undefined results. 01b One transaction to be issued for this endpoint per micro- frame 10b Two transactions to be issued for this endpoint per micro- frame 11b Three transactions to be issued for this endpoint per micro- frame Table 31-9. iTD Buffer Pointer Page 3-6 Bit Description 31-12 This is a 4 K aligned pointer to physical memory. Corresponds to memory address bits [31:12]. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2153 Functional Description Table 31-9. iTD Buffer Pointer Page 3-6 (continued) Bit Description Buffer Pointer 11-0 These bits reserved for future use and should be set to zero. Reserved 31.2.6.2.4 Split Transaction Isochronous Transfer Descriptor (siTD) All Full-speed isochronous transfers through the internal transaction translator are managed using the siTD data structure. This data structure satisfies the operational requirements for managing the split transaction protocol. The following table shows the Split Transaction Isochronous Transfer Descriptor (siTD). Table 31-10. Split Transaction Isochronous Transfer Descriptor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Next Link Pointer 3 0 I/ Port Number O - Hub Addr Reserved io P Reserved c 4 Total Bytes to Transfer Reserved EndPt - 2 1 Typ 0 Addr T 0300 Device Address 07041 Frame C-mask Frame S-mask 0B081 Frame C-prog-mask Status 0F0C2 Buffer Pointer (Page 0) Current Offset Buffer Pointer (Page 1) Reserved Back Pointer 13102 TP T-count 0 T 17142 1B18 1. 04-0B: Static Endpoint State 2. 0C-13: Transfer results Host Controller Read/Write 31.2.6.2.4.1 Host Controller Read Only Next Link Pointer DWord0 of a siTD is a pointer to the next schedule data structure. The following table describes the Next Link Pointer fields. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2154 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-11. Next Link Pointer Bit Description 31-5 Next Link Pointer (LP). This field contains the address of the next data object to be processed in the periodic list and corresponds to memory address signals [31:5], respectively. 4-3 Reserved. These bits must be written as zeros. 2-1 QH/(s)iTD Select (Typ). This field indicates to the Host Controller whether the item referenced is an iTD/siTD or a QH. This allows the Host Controller to perform the proper type of processing on the item after it is fetched. Value encodings are: Value Meaning 00b iTD (isochronous transfer descriptor) 01b QH (queue head) 10b siTD (split transaction isochronous transfer descriptor 11b FSTN (frame span traversal node) 0 Terminate (T). 1=Link Pointer field is not valid. 0=Link Pointer is valid. 31.2.6.2.4.2 siTD Endpoint Capabilities/Characteristics DWords 1 and 2 specify static information about the full-speed endpoint, the addressing of the parent Companion Controller, and micro-frame scheduling control. The tables below describe the Endpoint and transaction translator characteristics and micro-frame schedule control fields. Table 31-12. Endpoint and Transaction Translator Characteristics Bit Description 31 Direction (I/O).0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT. 30-24 Port Number. This field is the port number of the recipient Transaction Translator. 23 Reserved. Bit reserved and should be set to zero. 22-16 Hub Address. This field holds the device address of the Companion Controllers' hub. 15-12 Reserved. Field reserved and should be set to zero. 11-8 Endpoint Number (Endpt). This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. 7 Reserved. Bit is reserved for future use. It should be set to zero. 6-0 Device Address. This field selects the specific device serving as the data source or sink. Table 31-13. Micro-frame Schedule Control Bit Description 31-16 Reserved. This field reserved for future use. It should be set to zero. 15-8 Split Completion Mask (mFrame C-Mask). This field (along with the Active and SplitX- state fields in the Status byte) is used to determine during which micro-frames the host controller should execute complete-split transactions. When the criteria for using this field is met, an all zeros value has undefined behavior. The host controller uses the value of the three low-order bits of the FRINDEX register to index into this bit field. If the FRINDEX register value indexes to a position where the mFrame C-Mask field is a one, then this siTD is a candidate for transaction execution. There may be more than one bit in this mask set. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2155 Functional Description Table 31-13. Micro-frame Schedule Control (continued) Bit 7-0 Description Split Start Mask (mFrame S-mask). This field (along with the Active and SplitX-state fields in the Status byte) is used to determine during which micro-frames the host controller should execute start-split transactions. The host controller uses the value of the three low-order bits of the FRINDEX register to index into this bit field. If the FRINDEX register value indexes to a position where the mFrame S-mask field is a one, then this siTD is a candidate for transaction execution. An all zeros value in this field, in combination with existing periodic frame list has undefined results. 31.2.6.2.4.3 siTD Transfer State DWords 3-6 are used to manage the state of the transfer. The following table describes siTD transfer state fields. Table 31-14. siTD Transfer Status and Control Bit Description 31 Interrupt On Complete (ioc). 0 = Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete. When the host controller determines that the split transaction has completed it asserts a hardware interrupt at the next interrupt threshold. 30 Page Select (P). Used to indicate which data page pointer should be concatenated with the CurrentOffset field to construct a data buffer pointer (0 selects Page 0 pointer and 1 selects Page 1). The host controller is not required to write this field back when the siTD is retired (Active bit transitioned from a one to a zero). 29-26 Reserved. This field reserved for future use and should be set to zero. 25-16 Total Bytes To Transfer. This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023 (3FFh) 15-8 Frame Complete-split Progress Mask (C-prog-Mask). This field is used by the host controller to record which split-completes has been executed. 7-0: Status--This field records the status of the transaction executed by the host controller for this slot. It is a bit vector with the encoding shown in the following rows. 7 Active. Set to one by software to enable the execution of an isochronous split transaction by the Host Controller. 6 ERR. Set to a one by the Host Controller when an ERR response is received from the Companion Controller. 5 Data Buffer Error. Set to a one by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). In the case of an under run, the Host Controller transmits an incorrect CRC (thus invalidating the data at the endpoint). If an overrun condition occurs, no action is necessary. 4 Babble Detected. Set to a one by the Host Controller during status update when" babble" is detected during the transaction generated by this descriptor. 3 Transaction Error (XactErr). Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit is set only for IN transactions. 2 Missed Micro-Frame. The host controller detected that a host-induced hold- off caused the host controller to miss a required complete-split transaction. 1 Split Transaction State (SplitXstate). The bit encodings are: Value Meaning 00b Do Start Split. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2156 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-14. siTD Transfer Status and Control (continued) Bit Description This value directs the host controller to issue a Start split transaction to the endpoint when a match is encountered in the S-mask. 01b Do Complete Split. This value directs the host controller to issue a Complete split transaction to the endpoint when a match is encountered in the C-mask. 0 Reserved. Bit reserved for future use and should be set to zero. 31.2.6.2.4.4 siTD Buffer Pointer List (plus) DWords 4 and 5 are the data buffer page pointers for the transfer. This structure supports one physical page cross. The most significant 20 bits of each DWord in this section are the 4 K (page) aligned buffer pointers. The least significant 12 bits of each DWord are used as additional transfer state. The following table describes the siTD buffer pointer fields. Table 31-15. Buffer Page Pointer List (plus) Bit Description 31-12 Buffer Pointer List. Bits [31:12] of DWords 4 and 5 are 4 K page aligned physical memory addresses. These bits correspond to physical address bits [31:12] respectively. The lower 12 bits in each pointer are defined and used as specified below. The field P (see siTD Transfer State) specifies the current active pointer. Bits 11-0 Current Offset--The 12 least significant bits of the Page 0 pointer are the current byte offset for the current page pointer (as selected with the page indicator bit (P field). The host controller is not required to write this field back when the siTD is retired (Active bit transitioned from a one to a zero). (Page 0) Bits 11-0 (Page 1)--The least significant bits of the Page 1 pointer are split into three subfields as shown in the following rows. 11-5 Reserved (Page 1) 4-3 (Page 1) Transaction position (TP). This field is used with T-count to determine whether to send all, first, middle, or last with each outbound transaction payload. System software must initialize this field with the appropriate starting value. The host controller must correctly manage this state during the lifetime of the transfer. The bit encodings are: Value Meaning 00b All. The entire full-speed transaction data payload is in this transaction (that is, less than or equal to 188 bytes). 01b Begin. This is the first data payload for a full- speed that is greater than 188 bytes.transaction 10B Mid. This is the middle payload for a full-speed OUT transaction that is larger than 188 bytes. 11b End. This is the last payload for a full-speed OUT transaction that was larger than 188 bytes. 2-0 (Page 1) Transaction count (T-Count). Software initializes this field with the number of OUT start-splits this transfer requires. Any value larger than 6 is undefined. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2157 Functional Description 31.2.6.2.4.5 siTD Back Link Pointer DWord 6 of a siTD is simply another schedule link pointer. This pointer is always zero, or references a siTD, and it cannot reference any other schedule data structure. The following table describes the siTD back link pointer fields . Table 31-16. siTD Back Link Pointer Bit Description 31-5 siTD Back Pointer. This field is a physical memory pointer to a siTD. 4-1 Reserved. This field is reserved for future use. It should be set to zero. 0 Terminate (T). 1 = siTD Back Pointer field is not valid. 0 = siTD Back Pointer field is valid. 31.2.6.2.5 Queue Element Transfer Descriptor (qTD) This data structure is only used with a queue head. It describes one or more USB transactions to transfer up to 20480 (5*4096) bytes. The structure contains two structure pointers used for queue advancement, a DWord of transfer state, and a five-element array of data buffer pointers. It is 32 bytes and must be physically contiguous. The buffer associated with this transfer must be virtually contiguous. The buffer may start on any byte boundary; however, for optimal utilization of on-chip busses it is recommended to align the buffers on a 32-byte boundary. A separate buffer pointer list element must be used for each physical page in the buffer, regardless of whether the buffer is physically contiguous. Host controller updates (host controller writes) to stand-alone qTDs only occur during transfer retirement. References in the following bit field definitions of updates to the qTD are to the qTD portion of a queue head. The following table shows the queue head data structure. Table 31-17. Queue Head Data Structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Next qTD Pointer 8 7 6 5 4 0 3 2 1 0 Addr T 0300 Alternate Next qTD Pointer 0 T 0704 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2158 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-17. Queue Head Data Structure (continued) dt Total Bytes to Transfer Buffer Pointer (page 0) io C_Page c Cerr PID Status Code Current Offset 0B081 0F0C1 Buffer Pointer (page 0) Reserved 1310 Buffer Pointer (page 0) Reserved 1714 Buffer Pointer (page 0) Reserved 1B18 Buffer Pointer (page 0) Reserved 1F1C 1. 08-0F: Transfer Results Host Controller Read/Write Host Controller Read Only Queue Element Transfer Descriptors must be aligned on 32-byte boundaries. 31.2.6.2.5.1 Next qTD Pointer The first DWord of an element transfer descriptor is a pointer to another transfer element descriptor. The following table describes Next qTD pointer fields. Table 31-18. qTD Next Element Transfer Pointer (DWord 0) Bit Description 31-5 Next Transfer Element Pointer. This field contains the physical memory address of the next qTD to be processed. The field corresponds to memory address signals[31:5], respectively. 4-1 Reserved 0 Terminate (T). 1= pointer is invalid. 0=Pointer is valid (points to a valid Transfer Element Descriptor). This bit indicates to the Host Controller that there are no more valid entries in the queue. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2159 Functional Description 31.2.6.2.5.2 Alternate Next qTD Pointer The second DWord of a queue element transfer descriptor is used to support hardwareonly advance of the data stream to the next transfer descriptor on short packet. To be more explicit the host controller always uses this pointer when the current qTD is retired due to short packet. The following table describes the TD Alternate Next Element Transfer Pointer field descriptions. Table 31-19. TD Alternate Next Element Transfer Pointer (DWord 1) Bit Description 31-5 Alternate Next Transfer Element Pointer. This field contains the physical memory address of the next qTD to be processed in the event that the current qTD execution encounters a short packet (for an IN transaction). The field corresponds to memory address signals [31:5], respectively. 4-1 Reserved 0 Terminate (T). 1= pointer is invalid. 0=Pointer is valid (points to a valid Transfer Element Descriptor). This bit indicates to the Host Controller that there are no more valid entries in the queue. 31.2.6.2.5.3 qTD Token The third DWord of a queue element transfer descriptor contains most of the information the host controller requires to execute a USB transaction (the remaining endpointaddressing information is specified in the queue head). NOTE The field descriptions forward reference fields defined in the queue head. Where necessary, these forward references are preceded with a QH notation. The following table describes the TD Token fields. Table 31-20. TD Token (DWord 2) Bit Description 31 This is the data toggle sequence bit. The use of this bit depends on the setting of the Data Toggle Control bit in the queue head. Data Toggle 30-16 Total Bytes to Transfer This field specifies the total number of bytes to be moved with this transfer descriptor. This field is decremented by the number of bytes actually moved during the transaction, only on the successful completion of the transaction. The maximum value software may store in this field is 5 * 4K (5000H). This is the maximum number of bytes 5 page pointers can access. If the value of this field is zero when the host controller fetches this transfer descriptor (and the active bit is set), the host controller executes a zero-length transaction and retires the transfer descriptor. It is not a requirement for OUT transfers that Total Bytes To Transfer be an even multiple of QHD.Maximum Packet Length. If software builds such a transfer descriptor for an OUT transfer, the last transaction is always less than QHD.Maximum Packet Length. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2160 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-20. TD Token (DWord 2) (continued) Bit Description Although it is possible to create a transfer up to 20K this assumes the 1st offset into the first page is 0. When the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting the total bytes to 16K**. Therefore, the maximum recommended transfer is 16 K(4000H). 15 Interrupt On Complete (IOC) 14-12 Current Page (C_Page) 11-10 Error Counter (CERR) If this bit is set to a one, it specifies that when this qTD is completed, the Host Controller should issue an interrupt at the next interrupt threshold. This field is used as an index into the qTD buffer pointer list. Valid values are in the range 0H to 4H. The host controller is not required to write this field back when the qTD is retired. This field is a 2-bit down counter that keeps track of the number of consecutive Errors detected while executing this qTD. If this field is programmed with a non-zero value during set-up, the Host Controller decrements the count and writes it back to the qTD if the transaction fails. If the counter counts from one to zero, the Host Controller marks the qTD inactive, sets the Halted bit to a one, and error status bit for the error that caused CERR to decrement to zero. An interrupt is generated if the USB Error Interrupt Enable bit in the USBINTR register is set to a one. If HCD programs this field to zero during set-up, the Host Controller does not count errors for this qTD and there is no limit on the retries of this qTD. Note that write-backs of intermediate execution state are to the queue head overlay area, not the qTD. Transaction Error - Decrement Data Buffer Error - No Decrement3 Stalled - No Decrement1 Babble Detected - No Decrement1 No Error - No Decrement2 Error Decrement Counter 1 Detection of Babble or Stall automatically halts the queue head. Thus, count is not decremented 2 If the EPS field indicates a HS device or the queue head is in the Asynchronous Schedule (and PIDCode indicates an IN or OUT) and a bus transaction completes and the host controller does not detect a transaction error, then the host controller should reset CERR to extend the total number of errors for this transaction. For example, CERR should be reset with maximum value (3) on each successful completion of a transaction. The host controller must never reset this field if the value at the start of the transaction is 00b. See Split Transaction Interrupt for CERR adjustment rules when the EPS field indicates a FS or LS device and the queue head is in the Periodic Schedule. See Asynchronous - Do Complete Split for CERR adjustment rules when the EPS field indicates a FS or LS device, the queue head is in the Asynchronous schedule and the PIDCode indicates a SETUP. 3 Data buffer errors are host problems. They don't count against the device's retries. NOTE: Software must not program CERR to a value of zero when the EPS field is programmed with a value indicating a Full- or Low-speed device. This combination could result in undefined behavior. 9-8 This field is an encoding of the token, which should be used for transactions associated with this transfer descriptor. Encodings are: PID Code 00b OUT Token generates token (E1H) 01b IN Token generates token (69H) Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2161 Functional Description Table 31-20. TD Token (DWord 2) (continued) Bit 7-0 Status Description 10b SETUP Token generates token (2DH) (undefined if endpoint is an interrupt, the queue head is non-zero) transfer type, for example, Frame S-mask field in 11b Reserved This field is used by the Host Controller to communicate individual command execution states back to HCD. This field contains the status of the last transaction performed on this qTD. The bit encodings are: Bit Status Field Description 7 Active. Set to one by software to enable the execution of transactions by the Host Controller. 6 Halted. Set to one by the Host Controller during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this qTD. This can be caused by babble, the error counter counting down to zero, or reception of the STALL handshake from the device during a transaction. Any time that a transaction results in the Halted bit being set to a one, the Active bit is also set to zero. 5 Data Buffer Error. Set to a one by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (under run). If an overrun condition occurs, the Host Controller forces a timeout condition on the USB, invalidating the transaction at the source. If the host controller sets this bit to a one, then it remains a one for the duration of the transfer. 4 Babble Detected. Set to a one by the Host Controller during status update when" babble" is detected during the transaction. In addition to setting this bit, the Host Controller also sets the Halted bit to a one. Because "babble" is considered a fatal error for the transfer, setting the Halted bit to a one insures that no more transactions occur because of this descriptor. 3 Transaction Error (XactErr). Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). If the host controller sets this bit to a one, then it remains a one for the duration of the transfer. 2 Missed Micro-Frame. This bit is ignored unless the QH.EPS field indicates a fullor low-speed endpoint and the queue head is in the periodic list. This bit is set when the host controller detected that a host-induced hold-off caused the host controller to miss a required complete-split transaction. If the host controller sets this bit to a one, then it remains a one for the duration of the transfer. 1 Split Transaction State (SplitXstate). This bit is ignored by the host controller unless the QH.EPS field indicates a full- or low-speed endpoint. When a Full- or Low-speed device, the host controller uses this bit to track the state of the splittransaction. The functional requirements of the host controller for managing this state bit and the split transaction protocol depends on whether the endpoint is in the periodic or asynchronous schedule. The bit encodings are: Value Meaning 0b Do Start Split. This value directs the host controller to issue a Start split transaction to the endpoint. 1b Do Complete Split. This value directs the host controller to issue a Complete split transaction to the endpoint. 0 Ping State (P)/ERR. If the QH.EPS field indicates a High-speed device and the PID_Code indicates an OUT endpoint, then this is the state bit for the Ping protocol. The bit encodings are: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2162 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-20. TD Token (DWord 2) Bit Description Value Meaning 0b Do OUT. This value directs the host controller to issue an OUT PID to the endpoint. 1b Do Ping. This value directs the host controller to issue a PING PID to the endpoint. If the QH.EPS field does not indicate a High-speed device, then this field is used as an error indicator bit. It is set to a one by the host controller whenever a periodic split-transaction receives an ERR handshake. 31.2.6.2.5.4 qTD Buffer Page Pointer List The last five DWords of a queue element transfer descriptor is an array of physical memory address pointers. These pointers reference the individual pages of a data buffer. System software initializes Current Offset field to the starting offset into the current page, where current page is selected through the value in the C_Page field. The following table describes the qTD Buffer Pointer(s) (DWords 3-7) fields. Table 31-21. qTD Buffer Pointer(s) (DWords 3-7) Bit Description 31-12 Buffer Pointer List. Each element in the list is a 4 K page aligned physical memory address. The lower 12 bits in each pointer are reserved (except for the first one), as each memory pointer must reference the start of a 4 K page. The field C_Page specifies the current active pointer. When the transfer element descriptor is fetched, the starting buffer address is selected using C_Page (similar to an array index to select an array element). If a transaction spans a 4K buffer boundary, the host controller must detect the page-span boundary in the data stream, increment C_Page and advance to the next buffer pointer in the list, and conclude the transaction through the new buffer pointer. 11-0 Current Offset (Reserved). This field is reserved in all pointers except the first one (for example Page 0). The host controller should ignore all reserved bits. For the page 0 current offset interpretation, this field is the byte offset into the current page (as selected by C_Page). The host controller is not required to write this field back when the qTD is retired. Software should ensure the Reserved fields are initialized to zero. 31.2.6.2.6 Queue Head The following table shows the queue head structure layout. Table 31-22. Queue Head Structure Layout 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Queue Head Horizontal Link Pointer RL Mult C Maximum Packet Length Port Number2 Hub Addr2 6 5 4 3 0 H dt EP c EndPt Frame C-mask2 I 2 Typ Device Address Frame S-mask 1 0 Addr T 03-00 07041 0B081 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2163 Functional Description Table 31-22. Queue Head Structure Layout (continued) Current qTD Pointer 0 Next qTD Pointer 0 T 13103 Alternate Next qTD pointer NakC T nt 17144 dt Total Bytes to Transfer io C_Page c Cerr 0F0C PID Status Code 1B18 Buffer Pointer (Page 0) Current Offset Buffer Pointer (Page 1) Reserved Buffer Pointer (Page 2) S-bytes2 Buffer Pointer (Page 3) Reserved 2B28 Buffer Pointer (Page 4) Reserved 2F2C3 1. 2. 3. 4. 1F1C C-prog-mask2 23-20 FrameTa 27g2 244 04-0B: Static endpoint state. These fields are used exclusively to support split transactions to USB 2.0 hubs 10-2F: Transfer overlay. 14-27: Transfer results. Host Controller Read/Write 31.2.6.2.6.1 Host Controller Read Only Queue Head Horizontal Link Pointer The first DWord of a Queue Head contains a link pointer to the next data object to be processed after any required processing in this queue has been completed, as well as the control bits defined below. This pointer may reference a queue head or one of the isochronous transfer descriptors. It must not reference a queue element transfer descriptor. The following table describes the Queue head DWord 0 fields. Table 31-23. Queue Head DWord 0 Bit Description 31-5 Queue Head Horizontal Link Pointer (QHLP). This field contains the address of the next data object to be processed in the horizontal list and corresponds to memory address signals [31:5], respectively. 4-3 Reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2164 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-23. Queue Head DWord 0 (continued) 2-1 QH/(s)iTD Select (Typ). This field indicates to the hardware whether the item referenced by the link pointer is an iTD, siTD or a QH. This allows the Host Controller to perform the proper type of processing on the item after it is fetched. Value encodings are: Value Meaning 00b iTD (isochronous transfer descriptor) 01b QH (queue head) 10b siTD (split transaction isochronous transfer descriptor) 11b FSTN (frame span traversal node) 0 Terminate (T). 1=Last QH (pointer is invalid). 0=Pointer is valid. If the queue head is in the context of the periodic list, a one bit in this field indicates to the host controller that this is the end of the periodic list. This bit is ignored by the host controller when the queue head is in the Asynchronous schedule. Software must ensure that queue heads reachable by the host controller always have valid horizontal link pointers. 31.2.6.2.6.2 Queue Head Endpoint Capabilities/Characteristics The second and third DWords of a Queue Head specifies static information about the endpoint. This information does not change over the lifetime of the endpoint. There are three types of information in this region: * Endpoint Characteristics. These are the USB endpoint characteristics including addressing, maximum packet size, and endpoint speed. * Endpoint Capabilities. These are adjustable parameters of the endpoint. They effect how the endpoint data stream is managed by the host controller. * Split Transaction Characteristics. This data structure is used to manage full- and lowspeed data streams for bulk, control, and interrupt via split transactions to USB2.0 Hub Transaction Translator. There are additional fields used for addressing the hub and scheduling the protocol transactions (for periodic). The host controller must not modify the bits in this region. The following table describes the Endpoint characteristics: Queue head DWord 1 fields. Table 31-24. Endpoint Characteristics: Queue Head DWord 1 Bit Description 31-28 Nak Count Reload (RL). This field contains a value, which is used by the host controller to reload the Nak Counter field. 27 Control Endpoint Flag (C). If the QH.EPS field indicates the endpoint is not a high-speed device, and the endpoint is a control endpoint, then software must set this bit to a one. Otherwise, it should always set this bit to zero. 26-16 Maximum Packet Length. This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize). The maximum value this field may contain is 0x400 (1024). 15 Head of Reclamation List Flag (H). This bit is set by System Software to mark a queue head as being the head of the reclamation list. 14 Data Toggle Control (DTC). This bit specifies where the host controller should get the initial data toggle on an overlay transition. 0b Ignore DT bit from incoming qTD. Host controller preserves DT bit in the queue head. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2165 Functional Description Table 31-24. Endpoint Characteristics: Queue Head DWord 1 (continued) 1b Initial data toggle comes from incoming qTD DT bit. Host controller replaces DT bit in the queue head from the DT bit in the qTD. 13-12 Endpoint Speed (EPS). This is the speed of the associated endpoint. Bit combinations are: Value Meaning 00b Full-Speed (12 Mbits/sec) 01b Low-Speed (1.5 Mbits/sec) 10b High-Speed (480 Mbits/sec) 11b Reserved This field must not be modified by the host controller. 11-8 Endpoint Number (Endpt). This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. 7 Inactivate on Next Transaction (I). This bit is used by system software to request that the host controller set the Active bit to zero. See Rebalancing the periodic schedule , for full operational details. This field is only valid when the queue head is in the Periodic Schedule and the EPS field indicates a Full or Low-speed endpoint. Setting this bit to one when the queue head is in the Asynchronous Schedule or the EPS field indicates a high-speed device yields undefined results. 6-0 Device Address. This field selects the specific device serving as the data source or sink. The table below describes the Endpoint capabilities: Queue head DWord 2 field descriptions. Table 31-25. Endpoint Capabilities: Queue Head DWord 2 Bit Description 31-30 High-Bandwidth Pipe Multiplier (Mult). This field is a multiplier used to key the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. The host controller makes the simplifying assumption that software properly initializes this field (regardless of location of queue head in the schedules or other run time parameters). The valid values are: Value Meaning 00b Reserved. A zero in this field yields undefined results. 01b One transaction to be issued for this endpoint per micro-frame 10b Two transactions to be issued for this endpoint per micro-frame 11b Three transactions to be issued for this endpoint per micro-frame 29-23 Port Number. This field is ignored by the host controller unless the EPS field indicates a full- or low-speed device. The value is the port number identifier on the USB 2.0 Hub (for hub at device address Hub Addr below), below which the full- or low-speed device associated with this endpoint is attached. This information is used in the split-transaction protocol. 22-16 Hub Addr. This field is ignored by the host controller unless the EPS field indicates a full-or low-speed device. The value is the USB device address of the USB 2.0 Hub below which the full- or low-speed device associated with this endpoint is attached. This field is used in the split-transaction protocol. 15-8 Split Completion Mask (Frame C-Mask). This field is ignored by the host controller unless the EPS field indicates this device is a low- or full-speed device and this queue head is in the periodic list. This field (along with the Active and SplitX-state fields) is used to determine during which micro-frames the host controller should execute a complete-split transaction. When the criteria for using this field are met, a zero value in this field has undefined behavior. This field is used by the host controller to match against the three low-order bits of the FRINDEX register. If the FRINDEX register bits decode to a position where the Frame C- Mask field is a one, then this queue head is a candidate for transaction execution. There may be more than one bit in this mask set. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2166 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-25. Endpoint Capabilities: Queue Head DWord 2 (continued) 7-0 Interrupt Schedule Mask (Frame S-mask). This field is used for all endpoint speeds. Software should set this field to a zero when the queue head is on the asynchronous schedule. A non-zero value in this field indicates an interrupt endpoint. The host controller uses the value of the three low-order bits of the FRINDEX register as an index into a bit position in this bit vector. If the Frame S-mask field has a one at the indexed bit position then this queue head is a candidate for transaction execution. If the EPS field indicates the endpoint is a high-speed endpoint, then the transaction executed is determined by the PID_Code field contained in the execution area. This field is also used to support split transaction types: Interrupt (IN/OUT). This condition is true when this field is non-zero and the EPS field indicates this is either a full- or low-speed device. A zero value in this field, in combination with existing in the periodic frame list has undefined results. 31.2.6.2.6.3 Transfer Overlay-Queue Head The nine DWords in this area represent a transaction working space for the host controller. The general operational model is that the host controller can detect whether the overlay area contains a description of an active transfer. If it does not contain an active transfer, then it follows the Queue Head Horizontal Link Pointer to the next queue head. The host controller will never follow the Next Transfer Queue Element or Alternate Queue Element pointers unless it is actively attempting to advance the queue. For the duration of the transfer, the host controller keeps the incremental status of the transfer in the overlay area. When the transfer is complete, the results are written back to the original queue element. The DWord3 of a Queue Head contains a pointer to the source qTD currently associated with the overlay. The host controller uses this pointer to write back the overlay area into the source qTD after the transfer is complete. The following table describes the current qTD link pointer field descriptions. Table 31-26. Current qTD Link Pointer Bit Description 31-5 Current Element Transaction Descriptor Link Pointer. This field contains the address Of the current transaction being processed in this queue and corresponds to memory address signals [31:5], respectively. 4-0 Reserved (R). These bits are ignored by the host controller when using the value as an address to write data. The actual value may vary depending on the usage. The DWords 4-11 of a queue head are the transaction overlay area. This area has the same base structure as a Queue Element Transfer Descriptor. The queue head utilizes the reserved fields of the page pointers to implement tracking the state of split transactions. This area is characterized as an overlay because when the queue is advanced to the next queue element, the source queue element is merged onto this area. This area serves as execution cache for the transfer. The table below describes the Host-controller rules for bits in overlay. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2167 Functional Description Table 31-27. Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8 and 9) DWord Bit Description 5 4-1 Nak Counter (NakCnt)RW. This field is a counter the host controller decrements whenever a transaction for the endpoint associated with this queue head results in a Nak or Nyet response. This counter is reloaded from RL before a transaction is executed during the first pass of the reclamation list (relative to an Asynchronous List Restart condition). It is also loaded from RL during an overlay. 6 31 Data Toggle. The Data Toggle Control controls whether the host controller preserves this bit when an overlay operation is performed. 6 15 Interrupt On Complete (IOC). The IOC control bit is always inherited from the source qTD when the overlay operation is performed. 6 11-10 Error Counter (C_ERR). This two-bit field is copied from the qTD during the overlay and written back during queue advancement. 6 0 Ping State (P)/ERR. If the EPS field indicates a high-speed endpoint, then this field should be preserved during the overlay operation. 8 7-0 Split-transaction Complete-split Progress (C-prog-mask). This field is initialized to zero during any overlay. This field is used to track the progress of an interrupt split-transaction. 9 4-0 Split-transaction Frame Tag (Frame Tag). This field is initialized to zero during any overlay. This field is used to track the progress of an interrupt split-transaction. 9 11-5 S-bytes. Software must ensure that the S-bytes field in a qTD is zero before activating the qTD. This field is used to keep track of the number of bytes sent or received during an IN or OUT split transaction. 31.2.6.2.7 Periodic Frame Span Traversal Node (FSTN) This data structure is to be used only for managing Full- and Low-speed transactions that span a Host-frame boundary. See Host Controller Operational Model for FSTNs for full operational details. Software must not use an FSTN in the Asynchronous Schedule. An FSTN in the Asynchronous schedule results in undefined behavior. Software must not use the FSTN feature with a host controller whose USB_HCIVERSION register indicates a revision implementation below 0096h. FSTNs are not defined for implementations before 0.96 and their use yields undefined results. Table 31-28. Frame Span Traversal Node Structure Layout 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Addr Normal Path Link Pointer 0 Typ T 0300 Back Path Link Pointer 0 Typ1 T 0704 1. Must be set to indicate a queue head i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2168 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Host Controller Read/Write 31.2.6.2.7.1 Host Controller Read Only FSTN Normal Path Pointer The first DWord of an FSTN contains a link pointer to the next schedule object. This object can be of any valid periodic schedule data type. The following table describes the FSTN normal path pointer fields. Table 31-29. FSTN Normal Path Pointer Field Descriptions Bit Description 31-5 Normal Path Link Pointer (NPLP). This field contains the address of the next data object to be processed in the periodic list and corresponds to memory address signals [31:5], respectively. 4-3 Reserved 2-1 QH/(s)iTD/FSTN Select (Typ). This field indicates to the Host Controller whether the item referenced is a iTD/ siTD, a QH or an FSTN. This allows the Host Controller to perform the proper type of processing on the item after it is fetched. Value encodings are: Value Meaning 00b iTD (isochronous transfer descriptor) 01b QH (queue head) 10b siTD (split transaction isochronous transfer descriptor) 11b FSTN (Frame Span Traversal Node) 0 Terminate (T). 1=Link Pointer field is not valid. 0=Link Pointer is valid. 31.2.6.2.7.2 FSTN Back Path Link Pointer The second DWord of an FTSN node contains a link pointer to a queue head. If the T-bit in this pointer is zero, then this FSTN is a Save-Place indicator. Its Typ field must be set by software to indicate the target data structure is a queue head. If the T-bit in this pointer is set to one, then this FSTN is the Restore indicator. When the T-bit is one, the host controller ignores the Typ field. The following table describes the FSTN back path link pointer fields. Table 31-30. FSTN Back Path Link Pointer Field Descriptions Bit Description 31-5 Back Path Link Pointer (BPLP). This field contains the address of a Queue Head. This field corresponds to memory address signals [31:5], respectively. 4-3 Reserved 2-1 Typ. Software must ensure this field is set to indicate the target data structure is a Queue Head. Any other value in this field yields undefined results. 0 Terminate (T). 1=Link Pointer field is not valid (that is the host controller must not use bits [31:5] as a valid memory address). This value also indicates that this FSTN is a Restore indicator. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2169 Functional Description Table 31-30. FSTN Back Path Link Pointer Field Descriptions 0=Link Pointer is valid (that is the host controller may use bits [31:5] (in combination with the CTRLDSSEGMENT register if applicable) as a valid memory address). This value also indicates that this FSTN is a Save-Place indicator. 31.2.6.3 Host Operational Model The general operational model is for the enhanced interface host controller hardware and enhanced interface host controller driver (generally referred to as system software). Each significant operational feature of the EHCI host controller is discussed in a separate section. Each section presents the operational model requirements for the host controller hardware. Where appropriate, recommended system software operational models for features are also presented. 31.2.6.3.1 Host Controller Initialization After initial power-on or HCReset (hardware or through HCReset bit in the USB_USBCMD register), all of the operational registers are at their default values. After a hardware reset, only the operational registers not contained in the Auxiliary power well are at their default values. The following table describes the default values of operational registers. . Table 31-31. Default Values of Operational Register Space Operational Register Default Value (after Reset) USB_USBCMD 00080000h (00080B00h, if Asynchronous Schedule Park Capability is one) USB_USBSTS 00001000h USB_USBINTR 00000000h USB_FRINDEX 00000000h USB_CTRLDSSEGMENT 00000000h USB_PERIODICLISTBASE Undefined USB_ASYNCLISTADDR Undefined USB_CONFIGFLAG 00000000h USB_PORTSC1 00002000h (w/PPC set to one); 00003000h (w/PPC set to zero) To initialize the host controller, software should perform the following steps: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2170 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller * Write the appropriate value to the USB_USBINTR register to enable the appropriate interrupts. * Write the base address of the Periodic Frame List to the USB_PERIODICLIST BASE register. If no work items are in the periodic schedule, all elements of the Periodic Frame List should have their T-Bits set to one. * Write the USB_USBCMD register to set the desired interrupt threshold, frame list size (if applicable) and turn the host controller ON through setting the Run/Stop bit. At this point, the host controller is up and running and the port registers begin reporting device connects, and so on. System software can enumerate a port through the reset process (where the port is in the enabled state). At this point, the port is active with SOFs occurring down the enabled ports, but the schedules have not enabled. To communicate with devices through the asynchronous schedule, system software must write the USB_ASYNCLISTADDR register with the address of a control or bulk queue head. Software must then enable the asynchronous schedule by writing one to the Asynchronous Schedule Enable bit in the USB_USBCMD register. To communicate with devices through the periodic schedule, system software must enable the periodic schedule by writing one to the Periodic Schedule Enable bit in the USB_USBCMD register. NOTE The schedules can be turned on before the first port is reset (and enabled). When the USB_USBCMD register is written, system software must ensure the appropriate bits are preserved, depending on the intended operation. 31.2.6.3.2 Port Routing and Control The EHCI specification defines that a USB 2.0 Host controller is comprised of one highspeed host controller, which implements the EHCI programming interface and 0 to N USB 1.1 companion host controllers. Companion host controllers (cHCs) may be implementations of either Universal or Open host controller specifications. This configuration is used to deliver the required full USB 2.0-defined port capability; for example, Low-, Full-, and High-speed capability for every port. NOTE The USB controllers on i.MX parts do not require nor support companion controllers to support Full and Low Speed device. Full and Low Speed devices are supported within the USB controller by emulating the functionality of a high-speed HUB. Therefore, no port routing is present in the controller. Please refer to Embedded Transaction Translator Function for detail! i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2171 Functional Description The following figure illustrates a simple block diagram of the port routing logic and its relationship to the high-speed and companion host controllers within a USB 2.0 host controller. USB 2.0 Host Controller Companion USB1.1 HC Data Port Reg. High-Speed (ehci) HC Data Port Reg. Port Routing Logic Port Owner Transceiver Port 1 Figure 31-9. Example USB 2.0 Host Controller Port Routing Block Diagram There exists one transceiver per physical port and each host controller block has its own port status and control registers. The EHCI controller has port status and control registers for every port. Each companion host controller has only the port control and status registers it is required to operate. Either the EHCI host controller or one companion host controller controls each transceiver. Routing logic lies between the transceiver, the port status and control registers.1 The port routing logic is controlled from signals originating in the EHCI host controller. The EHCI host controller has a global routing policy control field and per-port ownership control fields. The Configured Flag (CF) bit is the global routing policy control. At power-on or reset, the default routing policy is to the companion controllers (if they exist). If the system does not include a driver for the EHCI host controller and the host controller includes Companion Controllers, then the ports still work in Full- and Low1. The routing logic should not be implemented in the 480 MHz clock domain of the transceiver. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2172 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller speed mode (assuming the system includes a driver for the companion controllers). In general, when the EHCI owns the ports, the companion host controllers' port registers do not see a connect indication from the transceiver. Similarly, when a companion host controller owns a port, the EHCI controller's port registers do not see a connect indication from the transceiver. The details on the rules for the port routing logic are described in the following sections. The USB 2.0 host controller must be implemented as a multifunction PCI device if the implementation includes companion controllers. The companion host controllers' function numbers must be less than the EHCI host controller function number. The EHCI host controller must be a larger function number with respect to the companion host controllers associated with this EHCI host controller. If a PCI device implementation contains only an EHCI controller (that is no companion controllers or other PCI functions), then the EHCI host controller must be function zero, in accordance with the PCI Specification. The N_CC field in the Structural Parameter register (HCSPARAMS) indicates whether the controller implementation includes companion host controllers. When N_CC has a non-zero value there exists companion host controllers. If N_CC has a value of zero, then the host controller implementation does not include companion host controllers. If the host controller root ports are exposed to attachment of full- or low-speed devices, the ports always fails the high-speed chirp during reset and the ports are not enabled. System software can notify the user of the illegal condition. This type of implementation requires a USB 2.0 hub be connected to a root port to provide full and low-speed device connectivity. System software uses information in the host controller capability registers to determine how the ports are routed to the companion host controllers. See Host Control Structural Parameters (EHCI-Compliant with Extensions) Register (HW_USBCTRL_HCSPARAMS). 31.2.6.3.2.1 Port Routing Control through EHCI Configured (CF) Bit Each port in the USB 2.0 host controller are routed either to a single companion host controller or to the EHCI host controller. The port routing logic is controlled by two mechanisms in the EHCI HC: a host controller global flag and per-port control. The Configured Flag (CF) bit, is used to globally set the policy of the routing logic. Each port register has a Port Owner control bit which allows the EHCI Driver to explicitly control the routing of individual ports. Whenever the CF bit transitions from zero to one (this transition is only available under program control) the port routing unconditionally routes all of the port registers to the EHCI HC (all Port Owner bits go to zero). While the CF-bit is one, the EHCI Driver controls individual ports' routing through the Port Owner control bit. Likewise, whenever the CF bit transitions from one to zero (as a result of Aux power application, HCRESET, or i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2173 Functional Description software writing zero to CF-bit), the port routing unconditionally routes all of the port registers to the appropriate companion HC. The default value for the EHCI HC's CF bit (after Aux power application or HCRESET) is zero. The view of the port depends on the current owner. A Universal or Open companion host controller will see port register bits consistent with the appropriate specification. Port bit definitions that are required for EHCI host controllers are not visible to companion host controllers. The following table summarizes the default routing for all the ports, based on the value of the EHCI HC's CF bit. Table 31-32. Default Port Routing Depending on EHCI HC CF Bit HS CF Bit Default Port Ownership Explanation 0B Companion HCs The companion host controllers own the ports and only Full- and Low-speed devices are supported in the system. The exact port assignments are implementation dependent. The ports behave only as Full- and Low-speed ports in this configuration 1B EHCI HC The EHCI host controller has default ownership over all of the ports. The routing logic inhibits device connect events from reaching the companion HCs' port status and control registers when the port owner is the EHCI HC.The EHCI HC has access to the additional port status and control bits defined in this specification (see )Port Status and Control 1 Register (HW_USBCTRL_PORTSC1). The EHCI HC can temporarily release control of the port to a companion HC by setting the PortOwner bit in the PORTSC1 register to one. 31.2.6.3.2.2 Port Routing Control through PortOwner and Disconnect Event Manipulating the port routing through the CF-bit is an extreme process and not intended to be used during normal operation. The normal mode of port ownership transferal is on the granularity of individual ports using the Port Owner bit in the EHCI HC's USB_PORTSC1 register (for hand-offs from EHCI to companion host controllers). Individual port ownership is returned to the EHCI controller when the port registers a device disconnect. When the disconnect is detected, the port routing logic immediately returns the port ownership to the EHCI controller. The companion host controller port register detects the device disconnect and operates normally. Under normal operating conditions (assuming all HC drivers loaded and operational and the EHCI CF-bit is set to one), the typical port enumeration sequence proceeds as illustrated below: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2174 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller * Initial condition is that EHCI is port owner. A device is connected causing the port to detect a connect, set the port connect change bit and issue a port-change interrupt (if enabled). * EHCI Driver identifies the port with the new connect change bit asserted and sends a change report to the hub driver. Hub driver issues a GetPortStatus() request and identifies the connect change. It then issues a request to clear the connect change, followed by a request to reset and enable the port. * When the EHCI Driver receives the request to reset and enable the port, it first checks the value reported by the LineStatus bits in the USB_PORTSC1 register. If they indicate the attached device is a full-speed device (for example, D+ is asserted), then the EHCI Driver sets the PortReset control bit to one (and sets the PortEnable bit to zero) which begins the reset-process. Software times the duration of the reset, then terminates reset signaling by writing zero to the port reset bit. The reset process is actually complete when software reads zero in the PortReset bit. The EHCI Driver checks the PortOwner bit in the USB_PORTSC1 register. If set to one, the connected device is a high-speed device and EHCI Driver (root hub emulator) issues a change report to the hub driver and the hub driver continues to enumerate the attached device. * At the time the EHCI Driver receives the port reset and enable request the LineStatus bits might indicate a low-speed device. Additionally, when the port reset process is complete, the PortEnable field may indicate that a full-speed device is attached. In either case the EHCI driver sets the PortOwner bit in the USB_PORTSC1 register to one to release port ownership to a companion host controller. * When the EHCI Driver sets PortOwner bit to one, the port routing logic makes the connection state of the transceiver available to the companion host controller port register and removes the connection state from the EHCI HC port. The EHCI USB_PORTSC1 register observes and reports a disconnect event through the disconnect change bit. The EHCI Driver detects the connection status change (either by polling or by port change interrupt) and then sends a change report to the hub driver. When the hub driver requests that port-state, the EHCI Driver responds with a reset complete change set to one, a connect change set to one and a connect status set to zero. This information is derived directly from the EHCI port register. This allows the hub driver to assume the device was disconnected during reset. It acknowledges the change bits and wait for the next change event. While the EHCI controller does not own the port, it simply remains in a state where the port reports no device connected. The device-connect evaluation circuitry of the companion HC activates and detects the device, the companion Driver detects the connection and enumerates the port. When a port is routed to a companion HC, it remains under the control of the companion HC until the device is disconnected from the root port (ignoring for now the scenario where EHCI's CF-bit transitions from1b to 0b). When a disconnect occurs, the disconnect i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2175 Functional Description event is detected by both the companion HC port control and the EHCI port ownership control. On the event, the port ownership is returned immediately to the EHCI controller. The companion HC stack detects the disconnect and acknowledges as it would in an ordinary standalone implementation. Subsequent connects is detected by the EHCI port register and the process repeats. 31.2.6.3.2.3 Example Port Routing State Machine The following figure illustrates an example of how the port ownership should be managed. The following sections describe the entry conditions to each state. PortOwner neq 0 AND EHCI CF EQ 1 EHCI CF --->1 EHCI Owner EHCI CF = 0 Companion Owner PortOwner .eq. 0 OR Disconnect AND EHCI CF .eq. 1 Figure 31-10. Port Owner Handoff State Machine 31.2.6.3.2.3.1 EHCI HC Owner Entry to this state occurs when one of the following events occur: * When the EHCI HC's Configure Flag (CF) bit in the USB_CONFIGFLAG register transitions from zero to one. This signals the fact that the system has a host controller driver for the EHCI HC and that all ports in the USB 2.0 host controller must default route to the EHCI controller. * When the port is owned by a companion HC and the device is disconnected from the port. The EHCI port routing control logic is notified of the disconnect, and returns port routing to the EHCI controller. The connection state of the companion HC goes immediately to the disconnected state (with appropriate side effect to connect change, enable and enable change). The companion HC driver acknowledges the disconnect by setting the connect status change bit to zero. This allows the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2176 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller companion HC's driver to interact with the port completely through the disconnect process. * When system software writes zero to the PortOwner bit in the USB_PORTSC1 register. This allows software to take ownership of a port from a companion host controller. When this occurs, the routing logic to the companion HC effectively signals a disconnect to the companion HC's port status and control register. 31.2.6.3.2.3.2 Companion HC Owner Entry to this state occurs whenever one of the following events occur: * When the PortOwner field transitions from zero to one. * When the HS-mode HC's Configure Flag (CF) is equal to zero. On entry to this state, the routing logic allows the companion HC port register to detect a device connect. Normal port enumeration proceeds. 31.2.6.3.3 VBUS Power Control 31.2.6.3.3.1 Port Power The Port Power Control (PPC) bit in the USB_HCSPARAMS register indicates whether the USB 2.0 host controller has port power control (see )Host Control Structural Parameters (EHCI-Compliant with Extensions) Register (HW_USBCTRL_HCSPARAMS). When this bit is zero, then the host controller does not support software control of port power switches. When in this configuration, the port power is always available and the companion host controllers must implement functionality consistent with port power always on. When the PPC bit is one, then the host controller implementation includes port power switches. Each available switch has an output enable, which is referred to in this discussion as PortPowerOutputEnable (PPE). PPE is controlled based on the state of the combination bits PPC bit, EHCI Configured (CF)-bit and individual Port Power (PP) bits. The following table describes the summary behavioral model. Table 31-33. Port Power Enable Control Rules CF CHC1 (PP) EHC2 (PP) Owner PPE3 Description 0 0 X CHC 0 When the EHCI controller is not configured, the port is owned by the companion host controller. When the companion HC's port power select is off, then the port power is off. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2177 Functional Description Table 31-33. Port Power Enable Control Rules (continued) 0 1 X CHC 1 Similar to previous entry. When the companion HC's port power select is on, then the port power is on. 1 0 0 CHC 0 Port owner has port power turned off, the power to port is off. 1 0 0 EHC 0 Port owner has port power turned off, the power to port is off. 1 0 1 EHC 1 Port owner has port power on, so power to port is on. 1 0 1 CHC 1 If either HC has port power turned on, the power to the port is on. 1 1 0 EHC 1 If either HC has port power turned on, the power to the port is on. 1 1 0 CHC 1 Port owner has port power on, so power to port is on. 1 1 1 CHC 1 Port owner has port power on, so power to port is on. 1 1 1 EHC 1 Port owner has port power on, so power to port is on. 1. CHC (Companion Host Controller). 2. EHC (EHCI Host Controller). 3. PPE (Port Power Enable). This bit actually turns on the port power switch (if one exists). 31.2.6.3.3.2 Port Reporting Over-Current Host controllers are by definition power providers on USB. Whether the ports are considered high- or low-powered is a platform implementation issue. Each EHCI USB_PORTSC1 register has an over-current status and over-current change bit. The functionality of these bits are specified in the USB Specification Revision 2.0. The over current detection and limiting logic usually resides outside the host controller logic. This logic may be associated with one or more ports. When this logic detects an over-current condition it is made available to both the companion and EHCI ports. The effect of an over-current status on a companion host controller port is beyond the scope of this document. The over-current condition effects the following bits in the USB_PORTSC1 register on the EHCI port: * Over-current Active bits are set to one. When the over-current condition goes away, the Over-current Active bit transitions from one to zero. * Over-current Change bits are set to one. On every transition of the Over-current Active bit the host controller sets the Over-current Change bit to one. Software sets the Over-current Change bit to zero by writing one to this bit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2178 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller * Port Enabled/Disabled bit is set to zero. When this change bit gets set to one, then the Port Change Detect bit in the USB_USBSTS register is set to one. * Port Power (PP) bits may optionally be set to zero. There is no requirement in USB that a power provider shut off power in an over current condition. It is sufficient to limit the current and leave power applied. When the Over-current Change bit transitions from zero to one, the host controller also sets the Port Change Detect bit in the USB_USBSTS register to one. In addition, if the Port Change Interrupt Enable bit in the USB_USBINTR register is one, then the host controller issues an interrupt to the system. Refer to Table 31-34 for summary behavior for over-current detection when the host controller is halted (suspended from a device component point of view). 31.2.6.3.4 Suspend/Resume-Host Operational Model The EHCI host controller provides an equivalent suspend and resume model as that defined for individual ports in a USB 2.0 Hub. Control mechanisms are provided to allow system software to suspend and resume individual ports. The mechanisms allow the individual ports to be resumed completely through software initiation. Other control mechanisms are provided to parameterize the host controller's response (or sensitivity) to external resume events. In this discussion, host-initiated, or software initiated resumes are called Resume Events/Actions. Businitiated resume events are called wake-up events. The classes of wake-up events are: * Remote-wake-up enabled device asserts resume signaling. In similar kind to USB 2.0 Hubs, EHCI controllers must always respond to explicit device resume signaling and wake-up the system (if necessary). * Port connect and disconnect and over-current events. Sensitivity to these events can be turned on or off by using the per-port control bits in the USB_PORTSC1 registers. Selective suspend is a feature supported by every USB_PORTSC1 register. It is used to place specific ports into a suspend mode. This feature is used as a functional component for implementing the appropriate power management policy implemented in a particular operating system. When system software intends to suspend the entire bus, it should selectively suspend all enabled ports, then shut off the host controller by setting the Run/ Stop bit in the USB_USBCMD register to zero. The EHCI sub-block can then be placed into a lower device state through the PCI power management interface (see Appendix A, Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95, November 2000, Intel Corporation. http://www.intel.com). When a wake event occurs, the system resumes operation and system software eventually set the Run/Stop bit to one and resume the suspended ports. Software must not set the Run/Stop bit to one until it is confirmed that the clock to the host controller is stable. This i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2179 Functional Description is usually confirmed in a system implementation in that all of the clocks in the system are stable before the ARM platform is restarted. So, by definition, if software is running, clocks in the system are stable and the Run/Stop bit in the USB_USBCMD register can be set to one. Minimum system software delays are also defined in the PCI Power Management Specification. Refer to PCI Power Management Specification for more information. 31.2.6.3.4.1 Port Suspend/Resume System software places individual ports into suspend mode by writing one into the appropriate USB_PORTSC1 Suspend bit. Software must only set the Suspend bit when the port is in the enabled state (Port Enabled bit is one) and the EHCI is the port owner (PortOwner bit is zero). The host controller may evaluate the Suspend bit immediately or wait until a micro-frame or frame boundary occurs. If evaluated immediately, the port is not suspended until the current transaction (if one is executing) completes. Therefore, there may be several micro-frames of activity on the port until the host controller evaluates the Suspend bit. The host controller must evaluate the Suspend bit at least every frame boundary. System software can initiate a resume on a selectively suspended port by writing one to the Force Port Resume bit. Software should not attempt to resume a port unless the port reports that it is in the suspended state (see )Port Status and Control 1 Register (HW_USBCTRL_PORTSC1). If system software sets Force Port Resume bit to one when the port is not in the suspended state, the resulting behavior is undefined. In order to assure proper USB device operation, software must wait for at least 10 ms after a port indicates that it is suspended (Suspend bit is one) before initiating a port resume through the Force Port Resume bit. When Force Port Resume bit is one, the host controller sends resume signaling down the port. System software times the duration of the resume (nominally 20 ms) then sets the Force Port Resume bit to zero. When the host controller receives the write to transition Force Port Resume to zero, it completes the resume sequence as defined in the USB specification, and sets both the Force Port Resume and Suspend bits to zero. Software-initiated port resumes do not affect the Port Change Detect bit in the USB_USBSTS register nor do they cause an interrupt if the Port Change Interrupt Enable bit in the USB_USBINTR register is one. An external USB event may also initiate a resume. The wake events are defined above. When a wake event occurs on a suspended port, the resume signaling is detected by the port and the resume is reflected downstream within 100 sec. The port's Force Port Resume bit is set to one and the Port Change Detect bit in the USB_USBSTS register is set to one. If the Port Change Interrupt Enable bit in the USB_USBINTR register is one the host controller issues a hardware interrupt. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2180 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller System software observes the resume event on the port, delays a port resume time (nominally 20 ms), then terminates the resume sequence by writing zero to the Force Port Resume bit in the port. The host controller receives the write of zero to Force Port Resume, terminates the resume sequence and sets Force Port Resume and Suspend port bits to zero. Software can determine that the port is enabled (not suspended) by sampling the USB_PORTSC1 register and observing that the Suspend and Force Port Resume bits are zero. Software must ensure that the host controller is running (that is HCHalted bit in the USB_USBSTS register is zero), before terminating a resume by writing zero to a port's Force Port Resume bit. If HCHalted is one when Force Port Resume is set to zero, then SOFs do not occur down the enabled port and the device returns to suspend mode in a maximum of 10 msec. The table below summarizes the wake-up events. Whenever a resume event is detected, the Port Change Detect bit in the USB_USBSTS register is set to one. If the Port Change Interrupt Enable bit is one in the USB_USBINTR register, the host controller generates an interrupt on the resume event. Software acknowledges the resume event interrupt by clearing the Port Change Detect status bit in the USB_USBSTS register. Table 31-34. Behavior During Wake-up Events Port Status and Signaling Type Signaled Port Response Device State D0 Not D0 N/A N/A Port disabled, resume K-State received No Effect Port suspended, resume K-State received Resume reflected downstream on signaled port. Force [1], [2] Port Resume status bit in USB_PORTSC1 register is set to one. Port Change Detect bit in USB_USBSTS register set to one. [2] Port is enabled, disabled or suspended, Depending in the initial port state, theUSB_ PORTSC1 and the port's WKDSCNNT_E bit is one. Connected Enable status bits are set to zero, and the A disconnect is detected. Connect Change status bit is set to one. Port Change Detect bit in the USB_USBSTS register is set to one. [1], [2] [2] Port is enabled, disabled or suspended, Depending on the initial port state, the USB_PORTSC1 and the port's WKDSCNNT_E bit is zero. Connect and Enable status bits are set to zero, and the A disconnect is detected. Connect Change status bit is set to one. Port Change Detect bit in the USB_USBSTS register is set to one. [1], [3] [3] Port is not connected and the port's WKCNNT_E bit is one. A connect is detected. USB_PORTSC1 Connect Status and Connect Status Change bits are set to one. Port Change Detect bit in the USB_USBSTS register is set to one. [1], [2] [2] Port is not connected and the port's WKCNNT_E bit is zero. A connect is detected. USB_PORTSC1 Connect Status and Connect Status Change bits are set to one. Port Change Detect bit in the USB_USBSTS register is set to one. [1], [3] [3] Port is connected and the port's WKOC_E bit is one. An over-current condition occurs. USB_PORTSC1 Over-current Active, Over-current Change bits are set to one. If Port Enable/Disable bit is one, it is set to zero. Port Change Detect bit in the USB_USBSTS register is set to one [1], [2] [2] Port is connected and the port's WKOC_E bit is zero. An over-current condition occurs. USB_PORTSC1 Over-current Active, Over-current Change bits are set to one. If Port Enable/Disable bit is one, it is set to zero. Port Change Detect bit in the USB_USBSTS register is set to one. [1], [3] [3] i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2181 Functional Description [1] Hardware interrupt issued if Port Change Interrupt Enable bit in the USB_USBINTR register is one. [2] PME# asserted if enabled (Note: PME Status must always be set to one). [3] PME# not asserted. 31.2.6.3.5 Schedule Traversal Rules The host controller executes transactions for devices using a simple, shared-memory schedule. The schedule is comprised of a few data structures, organized into two distinct lists. The data structures are designed to provide the maximum flexibility required by USB, minimize memory traffic and hardware / software complexity. System software maintains two schedules for the host controller: a periodic schedule and an asynchronous schedule. The root of the periodic schedule is the USB_PERIODICLISTBASE register (see Frame List Base Address Register (Host Controller mode) (HW_USBCTRL_PERIODICLISTBASE))/ USB Device Address Register (Device Controller mode) (HW_USBCTRL_DEVICEADDR). The USB_PERIODICLISTBASE register is the physical memory base address of the periodic frame list. The periodic frame list is an array of physical memory pointers. The objects referenced from the frame list must be valid schedule data structures as defined in Host Data Structures. In each micro-frame, if the periodic schedule is enabled (see Periodic scheduling threshold) then the host controller must execute from the periodic schedule before executing from the asynchronous schedule. It only executes from the asynchronous schedule after it encounters the end of the periodic schedule. The host controller traverses the periodic schedule by constructing an array offset reference from the USB_PERIODICLISTBASE and the USB_FRINDEX registers (see the following figure). It fetches the element and begins traversing the graph of linked schedule data structures. The end of the periodic schedule is identified by a next link pointer of a schedule data structure having its T-bit set to one. When the host controller encounters a T-Bit set to one during a horizontal traversal of the periodic list, it interprets this as an End-OfPeriodic-List mark. This causes the host controller to cease working on the periodic schedule and transitions immediately to traversing the asynchronous schedule. After the transition, the host controller executes from the asynchronous schedule until the end of the micro-frame. The following figure illustrates the derivation of pointer into frame list array. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2182 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Periodic Frame List DWord-aligned Periodic Frame List Element Address 12 11 2 1 0 31 31 12 13 12 Periodic Frame List Base Address 3 2 1 0 Frame Index Register Figure 31-11. Derivation of Pointer into Frame List Array When the host controller determines that it is the time to execute from the asynchronous list, it uses the operational register USB_ASYNCLISTADDR to access the asynchronous schedule, see the figure below. USBCMD H USBSTS ... ASYNCLISTADDR ... Operational Registers Figure 31-12. General Format of Asynchronous Schedule List The USB_ASYNCLISTADDR register contains a physical memory pointer to the next queue head. When the host controller makes a transition to executing the asynchronous schedule, it begins by reading the queue head referenced by the USB_ASYNCLISTADDR register. Software must set queue head horizontal pointer Tbits to zero for queue heads in the asynchronous schedule. See Asynchronous Schedule for complete operational details. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2183 Functional Description 31.2.6.3.5.1 Example - Preserving Micro-Frame Integrity One of the requirements of a USB host controller is to maintain Frame Integrity. This means that the HC must preserve the micro-frame boundaries. For example, SOF packets must be generated on time (within the specified allowable jitter), and High-speed EOF1,2 thresholds must be enforced. The end of micro-frame timing points EOF1 and EOF2 are clearly defined in the USB Specification Revision 2.0. One implication of this responsibility is that the HC must ensure that it does not start transactions that do not complete before the end of the micro-frame. More precisely, no transactions should be started by the host controller, which do not complete in their entirety before the EOF1 point. In order to enforce this rule, the host controller must check each transaction before it starts to ensure that it completes before the end of the micro-frame. So, what exactly needs to be involved in this check? Fundamentally, the transaction data payload, plus bit stuffing, plus transaction overhead must be taken into consideration. It is possible to be extremely accurate on how much time the next transaction takes. Take OUTs for an example. The host controller must fetch all of the OUT data from memory in order to send it onto the USB bus. A host controller implementation could pre-fetch all of the OUT data, and pre-compute the actual number of bits in the token and data packets. In addition, the system knows the depth of the target endpoint, so it could closely estimate turnaround time for handshake. In addition, the host controller knows the size of a handshake packet. Pre-computing effects of bit stuffing and summing up the other overhead numbers can allow the host controller to know exactly whether there is enough bus time, before EOF1 to complete the OUT transaction. To accomplish this particular approach takes an inordinate amount of time and hardware complexity. The alternative is to make a reasonable guess whether the next transaction can be started. An example approximation algorithm is described below. This example algorithm relies on the EHCI policy that periodic transactions are scheduled first in the micro-frame. It is a reasonable assumption that software never over-commits the micro-frame to periodic transactions greater than the specification allowable 80%. In the available remaining 20% bandwidth, the host controller has some ability (in this example) to decide whether or not to execute a transaction. The result of this algorithm is that sometimes, under some circumstances a transaction is not executed that could have been executed. However, under all circumstances, a transaction is never started unless there is enough time in the frame to complete the transaction. 31.2.6.3.5.1.1 Transaction Fit - A Best-Fit Approximation Algorithm A curve is calculated which represents the latest start time for every packet size, at which software schedules the start of a periodic transaction. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2184 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller This curve is the 80% bandwidth curve. Another curve is calculated which is the absolute, latest permitted start time for every packet size. This curve represents the absolute latest time, that a transaction of each packet size can be started and completed, in the micro-frame. A plot of these two curves are illustrated in Figure 31-13. The plot Yaxis represents the number of byte-times left in a frame. The space between the 80% and the Last Start plots is bandwidth reclamation area. In this algorithm the host controller may skip transactions during this time if it is prudent. The Best-Fit Approximation method plots a function (f(x)) between the 80% and Last Start curves. The function f(x) adds a constant to every transaction's maximum packet size and the result compared with the number of bytes left in the frame. The constant represents an approximation of the effects of bit stuffing and protocol overhead. The host controller starts transactions whose results land above the function curve. The host controller will not start transactions whose results land below the function curve. The following figure illustrates the Best-Fit Approximation. 7000 6000 Transactions that will be started 5000 Byte Times to EOF 4000 3000 2000 Goal is to minimize area under this curve 1000 0 Transactions that will be skipped 1 64 127 190 253 316 379 442 505 588 631 694 757 820 883 946 1009 Packet Size in Bytes 80% Threshold Last Start f(x) Figure 31-13. Best Fit Approximation The LastStart line was calculated in this example to assume the absolute worst-case bus overhead per transaction. The particular transaction used is a start-split, zero-length OUT transaction with a handshake. Summaries of the component parts are listed in the table below. The component times were derived from the protocol timings defined in the USB Specification Revision 2.0. Table 31-35. Example Worse-case Transaction Timing Components Component Bit time Byte Time Explanation Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2185 Functional Description Table 31-35. Example Worse-case Transaction Timing Components (continued) Split Token 76 9.5 Split token as defined in USB core specification. Includes sync, token, eop, and so on. Host 2 Host IPG 88 11 Number of bit times required between consecutive host packets. Token 67 8.375 Token as defined in USB core specification. Includes sync, token, eop, and so on. Host 2 Host IPG 88 11 Token as defined in USB core specification. Includessync, token, eop, and so on. Data Packet (0 data bytes) 66.7 8.34 Zero-length data packet. Includes sync, PID, crc16, eop, and so on. Turnaround time 721 90.125 Time for packet initiator (Host) to see the beginning of a response to a transmitted packet. Handshake packet 48 6 Handshake packet as defined in USB core specification. Includes sync, PID, eop, and so on. 144 Total The exact details of the function (f(x)) are up to the particular implementation. However, it should be obvious that the goal is to minimize the area under the curve between the approximation function and the Last Start curve, without dipping below the LastStart line, while at the same time keeping the check as simple as possible for hardware implementation. The f(x) in Figure 31-13 was constructed using the following pseudocode test on each transaction size data point. This algorithm assumes that the host controller keeps track of the remaining bits in the frame. Alorithm CheckTransactionWillFit (MaximumPacketSize, HC_BytesLeftInFrame) Begin Local Temp = MaximumPacketSize + 192 Local rvalue = TRUE If MaximumPacketSize >= 128 then Temp += 128 End If If Temp > HC_BytesLeftInFrame then Rvalue = FALSE End If Return rvalue End This algorithm takes two inputs, the current maximum packet size of the transaction and the hardware counter of the number of bytes left in the current micro-frame. It unconditionally adds a simple constant of 192 to the maximum packet size to account for a first-order effect of transaction overhead and bit stuffing. If the transaction size is greater than or equal to 128 bytes, then an additional constant of 128 is added to the running sum to account for the additional worst-case bit stuffing of payloads larger than 128. An inflection point was inserted at 128 because the f(x) plot was getting close to the LastStart line. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2186 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.3.6 Periodic Schedule Frame Boundaries vs Bus Frame Boundaries The USB Specification Revision 2.0 requires that the frame boundaries (SOF frame number changes) of the high-speed bus and the full- and low-speed bus(s) below USB 2.0 Hubs be strictly aligned. Super-imposed on this requirement is that USB 2.0 Hubs manage full- and low-speed transactions through a micro-frame pipeline (see start- (SS) and complete- (CS) splits illustrated in the following figure). A simple, direct projection of the frame boundary model into the host controller interface schedule architecture creates tension (complexity for both hardware and software) between the frame boundaries and the scheduling mechanisms required to service the full- and low-speed transaction translator periodic pipelines. Frame Boundary 7 HS Bus SS Micro-frame number(s) 0 1 CS 2 CS 3 CS SS 4 CS 5 CS 6 CS 7 CS 0 CS FS/LS Bus Figure 31-14. Frame Boundary Relationship between HS bus and FS/LS Bus The simple projection, as the above figure illustrates, introduces frame-boundary wrap conditions for scheduling on both the beginning and end of a frame. In order to reduce the complexity for hardware and software, the host controller is required to implement one micro-frame phase shift for its view of frame boundaries. The phase shift eliminates the beginning of frame and frame-wrap scheduling boundary conditions. The implementation of this phase shift requires that the host controller use one register value for accessing the periodic frame list and another value for the frame number value included in the SOF token. These two values are separate, but tightly coupled. The periodic frame list is accessed through the Frame List Index Register (USB_FRINDEX) documented in USB Frame Index Register (HW_USBCTRL_FRINDEX) and initially illustrated in Schedule Traversal Rules . Bits FRINDEX[2:0], represent the micro-frame number. The SOF value is coupled to the value of FRINDEX[13:3]. Both FRINDEX[13:3] and the SOF value are increment based on FRINDEX[2:0]. It is required that the SOF value be delayed from the FRINDEX value by one micro-frame. The one micro-frame delay yields host controller periodic schedule and bus frame boundary relationship as illustrated in the following figure. This adjustment allows software to trivially schedule the periodic start and complete-split transactions for full- i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2187 Functional Description and low-speed periodic endpoints, using the natural alignment of the periodic schedule interface. The reasons for selecting this phase-shift are beyond the scope of this specification. The following figure illustrates how periodic schedule data structures relate to schedule frame boundaries and bus frame boundaries. To aid the presentation, two terms are defined: The host controller's view of the 1 msec boundaries is called H-Frames. The high-speed bus's view of the 1 msec boundaries is called B-Frames. HC Periodic Schedule Frame Boundaries HC Periodic Schedule Micro-frames 7 0 SS 1 HS/FS/LS Bus Frame Boundaries 2 3 4 5 CS CS CS CS full/low-speed transaction HS Bus Frames 6 7 0 SS 1 2 3 4 5 CS CS CS CS 6 7 0 1 2 full/low-speed transaction B-Frame N B-Frame N+1 H-Frame N H-Frame N+1 Interface Data Structure Interface Data Structure Figure 31-15. Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries H-Frame boundaries for the host controller correspond to increments of FRINDEX[13:3]. Micro-frame numbers for the H-Frame are tracked by FRINDEX[2:0]. B-Frame boundaries are visible on the high-speed bus through changes in the SOF token's frame number. Micro-frame numbers on the high-speed bus are only derived from the SOF token's frame number (that is the high-speed bus sees eight SOFs with the same frame number value). H-Frames and B-Frames have the fixed relationship (that is B-Frames lag H-Frames by one micro-frame time) illustrated in the figure above. The host controller's periodic schedule is naturally aligned to H-Frames. Software schedules transactions for full- and low-speed periodic endpoints relative the H-Frames. The result is these transactions execute on the high-speed bus at exactly the right time for the USB 2.0 Hub periodic pipeline. As described in USB Frame Index Register (HW_USBCTRL_FRINDEX), the SOF Value can be implemented as a shadow register (in this example, called SOFV), which lags the FRINDEX register bits [13:3] by one micro-frame count. This lag behavior can be accomplished by incrementing FRINDEX[13:3] based on carry-out on the 7 to 0 increment of FRINDEX[2:0] and incrementing SOFV based on the transition of 0 to 1 of FRINDEX[2:0]. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2188 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Software is allowed to write to FRINDEX. USB Frame Index Register (HW_USBCTRL_FRINDEX) provides the requirements that software should adhere when writing a new value in FRINDEX. The table below illustrates the required relationship between the value of FRINDEX and the value of SOFV. Table 31-36. Operation of FRINDEX and SOFV (SOF Value Register) Current Next FRINDEX[F] SOFV FRINDEX[mF] FRINDEX[F] SOFV FRINDEX[mF] N N 111b N+1 N 000b N+1 N 000b N+1 N+1 001b N+1 N+1 001b N+1 N+1 010b N+1 N+1 010b N+1 N+1 011b N+1 N+1 011b N+1 N+1 100b N+1 N+1 100b N+1 N+1 101b N+1 N+1 101b N+1 N+1 110b N+1 N+1 110b N+1 N+1 111b NOTE Where [F] = [13:3]; [F] = [2:0] 31.2.6.3.7 Periodic Schedule The periodic schedule traversal is enabled or disabled through the Periodic Schedule Enable bit in the USB_USBCMD register. If the Periodic Schedule Enable bit is set to zero, then the host controller simply does not try to access the periodic frame list through the USB_PERIODICLISTBASE register. Likewise, when the Periodic Schedule Enable bit is one, then the host controller does use the USB_PERIODICLISTBASE register to traverse the periodic schedule. The host controller will not react to modifications to the Periodic Schedule Enable immediately. In order to eliminate conflicts with split transactions, the host controller evaluates the Periodic Schedule Enable bit only when FRINDEX[2:0] is zero. System software must not disable the periodic schedule if the schedule contains an active split transaction work item that spans the 000b micro-frame. These work items must be removed from the schedule before the Periodic Schedule Enable bit is written to zero. The Periodic Schedule Status bit in the USB_USBSTS register indicates status of the periodic schedule. System software enables (or disables) the periodic schedule by writing one (or zero) to the Periodic Schedule Enable bit in the USB_USBCMD register. Software then can poll the Periodic Schedule Status bit to determine when the periodic schedule has i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2189 Functional Description made the desired transition. Software must not modify the Periodic Schedule Enable bit unless the value of the Periodic Schedule Enable bit equals that of the Periodic Schedule Status bit. The periodic schedule is used to manage all isochronous and interrupt transfer streams. The base of the periodic schedule is the periodic frame list. Software links schedule data structures to the periodic frame list to produce a graph of scheduled data structures. The graph represents an appropriate sequence of transactions on the The following figure illustrates isochronous transfers (using iTDs and siTDs) with a period of one are linked directly to the periodic frame list. Interrupt transfers (are managed with queue heads) and isochronous streams with periods other than one are linked following the period-one iTD/siTDs. Interrupt queue heads are linked into the frame list ordered by poll rate. Longer poll rates are linked first (for example, closest to the periodic frame list), followed by shorter poll rates, with queue heads with a poll rate of one, on the very end. Periodic Frame List 1024, 512, or 256 elements Isochronous Transfer Descriptor(s) A A A A Last Periodic has End of List Mark A 1 A 4 A Poll Rate: 1 8 Poll Rate: N 1 Interrupt Queue Heads Figure 31-16. Example Periodic Schedule i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2190 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.3.8 Managing Isochronous Transfers Using iTDs The structure of an iTD is presented in Isochronous (High-Speed) Transfer Descriptor (iTD). The four distinct sections to an iTD: * The first field is the Next Link Pointer. This field is for schedule linkage purposes only. * Transaction description array. This area is an eight-element array. Each element represents control and status information for one micro-frame's worth of transactions for a single high-speed isochronous endpoint. * The buffer page pointer array is a 7-element array of physical memory pointers to data buffers. These are 4 K aligned pointers to physical memory. * Endpoint capabilities. This area utilizes the unused low-order 12 bits of the buffer page pointer array. The fields in this area are used across all transactions executed for this iTD, including endpoint addressing, transfer direction, maximum packet size and high-bandwidth multiplier. 31.2.6.3.8.1 Host Controller Operational Model for iTDs The host controller uses FRINDEX register bits [12:3] to index into the periodic frame list. This means that the host controller visits each frame list element eight consecutive times before incrementing to the next periodic frame list element. Each iTD contains eight transaction descriptions, which map directly to FRINDEX register bits [2:0]. Therefore, each transaction descriptor corresponds to one micro-frame. Each iTD can span 8 micro-frames worth of transactions. When the host controller fetches an iTD, it uses FRINDEX register bits [2:0] to index into the transaction description array. If the active bit in the Status field of the indexed transaction description is set to zero, the host controller ignores the iTD and follows the Next pointer to the next schedule data structure. When the indexed active bit is one, the host controller continues to parse the iTD. It stores the indexed transaction description and the general endpoint information (device address, endpoint number, maximum packet size, and so on.). It also uses the Page Select (PG) field to index the buffer pointer array, storing the selected buffer pointer and the next sequential buffer pointer. For example, if PG field is 0, then the host controller stores Page 0 and Page 1. The host controller constructs a physical data buffer address by concatenating the current buffer pointer (as selected using the current transaction description's PG field) and the transaction description's Transaction Offset field. The host controller uses the endpoint addressing information and I/O-bit to execute a transaction to the appropriate endpoint. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2191 Functional Description When the transaction is complete, the host controller clears the active bit and writes back any additional status information to the Status field in the currently selected transaction description. The data buffer associated with the iTD must be virtually contiguous memory. Seven page pointers are provided to support eight high-bandwidth transactions regardless of the starting packet's offset alignment into the first page. A starting buffer pointer (physical memory address) is constructed by concatenating the page pointer (for example, page 0 pointer) selected by the active transaction descriptions' PG (for example, value: 00B) field with the transaction offset field. As the transaction moves data, the host controller must detect when an increment of the current buffer pointer crosses a page boundary. When this occurs the host controller simply replaces the current buffer pointer's page portion with the next page pointer (for example, page 1 pointer) and continues to move data. The size of each bus transaction is determined by the value in the Maximum Packet Size field. An iTD supports high-bandwidth pipes through the Mult (multiplier) field. When the Mult field is 1, 2, or 3, the host controller executes the specified number of Maximum Packet sized bus transactions for the endpoint in the current micro-frame. In other words, the Mult field represents a transaction count for the endpoint in the current micro-frame. If the Mult field is zero, the operation of the host controller is undefined. The transfer description is used to service all transactions indicated by the Mult field. For OUT transfers, the value of the Transaction X Length field represents the total bytes to be sent during the micro-frame. The Mult field must be set by software to be consistent with Transaction X Length and Maximum Packet Sixe. The host controller sends the bytes in Maximum Packet Size'd portions. After each transaction, the host controller decrements its local copy of Transaction X Length by Maximum Packet Size. The number of bytes the host controller sends is always Maximum Packet Size or Transaction X Length, whichever is less. The host controller advances the transfer state in the transfer description, updates the appropriate record in the iTD and moves to the next schedule data structure. The maximum sized transaction supported is 3 x 1024 bytes. For IN transfers, the host controller issues Mult transactions. It is assumed that software has properly initialized the iTD to accommodate all of the possible data. During each IN transaction, the host controller must use Maximum Packet Size to detect packet babble errors. The host controller keeps the sum of bytes received in the Transaction X Length field. After all transactions for the endpoint have completed for the micro-frame, Transaction X Length contains the total bytes received. If the final value of Transaction X Length is less than the value of Maximum Packet Size, then less data than was allowed for was received from the associated endpoint. This short packet condition does not set the USBINT bit in the USB_USBSTS register to one. The host controller will not detect this condition. If the device sends more than Transaction X Length or Maximum Packet Size bytes (whichever is less), then the host controller sets the Babble Detected bit to one and set the Active bit to zero. Note, that the host controller is not required to update the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2192 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller iTD field Transaction X Length in this error scenario. If the Mult field is greater than one, then the host controller automatically executes the value of Mult transactions. The host controller will not execute all Mult transactions if: * The endpoint is an OUT and Transaction X Length goes to zero before all the Mult transactions have executed (ran out of data), or * The endpoint is an IN and the endpoint delivers a short packet, or an error occurs on a transaction before Mult transactions have been executed. The end of micro-frame may occur before all of the transaction opportunities have been executed. When this happens, the transfer state of the transfer description is advanced to reflect the progress that was made, the result written back to the iTD and the host controller proceeds to processing the next micro-frame. Refer to Appendix D for a table summary of the host controller required behavior for all the high-bandwidth transaction cases. 31.2.6.3.8.2 Software Operational Model for iTDs A client buffer request to an isochronous endpoint may span 1 to N micro-frames. When N is larger than one, system software may have to use multiple iTDs to read or write data with the buffer (if N is larger than eight, it must use more than one iTD). The following figure illustrates the simple model of how a client buffer is mapped by system software to the periodic schedule (that is the periodic frame list and a set of iTDs). On the right is the client description of its request. The description includes a buffer base address plus additional annotations to identify which portions of the buffer should be used with each bus transaction. In the middle is the iTD data structures used by the system software to service the client request. Each iTD can be initialized to service up to 24 transactions, organized into eight groups of up to three transactions each. Each group maps to one micro-frame's worth of transactions. The EHCI controller does not provide per-transaction results within a micro-frame. It treats the per-micro-frame transactions as a single logical transfer. On the left is the host controller's frame list. System software establishes references from the appropriate locations in the frame list to each of the appropriate iTDs. If the buffer is large, then system software can use a small set of iTDs to service the entire buffer. System software can activate the transaction description records (contained in each iTD) in any pattern required for the particular data stream. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2193 Functional Description iTD0 Client Request ... USB Xact Information Frame i Frame i+1 iTD1 Frame i+2 ... Frame i+n ... iTDn ... Figure 31-17. Example Association of iTDs to Client Request Buffer As noted above, the client request includes a pointer to the base of the buffer and offsets into the buffer to annotate which buffer sections are to be used on each bus transaction that occurs on this endpoint. System software must initialize each transaction description in an iTD to ensure it uses the correct portion of the client buffer. For example, for each transaction description, the PG field is set to index the correct physical buffer page pointer and the Transaction Offset field is set relative to the correct buffer pointer page (for example, the same one referenced by the PG field). When the host controller executes a transaction it selects a transaction description record based on FRINDEX[2:0]. It then uses the current Page Buffer Pointer (as selected by the PG field) and concatenates to the transaction offset field. The result is a starting buffer address for the transaction. As the host controller moves data for the transaction, it must watch for a page wrap condition and properly advance to the next available Page Buffer Pointer. System software must not use the Page 6 buffer pointer in a transaction description where the length of the transfer wraps a page boundary. Doing so yields undefined behavior. The host controller hardware is not required to 'alias' the page selector to Page zero. USB 2.0 isochronous i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2194 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller endpoints can specify a period greater than one. Software can achieve the appropriate scheduling by linking iTDs into the appropriate frames (relative to the frame list) and by setting appropriate transaction description elements active bits to one. 31.2.6.3.8.2.1 Periodic scheduling threshold The Isochronous Scheduling Threshold field in the USB_HCCPARAMS capability register is an indicator to system software as to how the host controller pre-fetches and effectively caches schedule data structures. It is used by system software when adding isochronous work items to the periodic schedule. The value of this field indicates to system software the minimum distance it can update isochronous data (relative to the current location of the host controller execution in the periodic list) and still have the host controller process them. The iTD and siTD data structures each describe 8 micro-frames worth of transactions. The host controller is allowed to cache one (or more) of these data structures in order to reduce memory traffic. Three basic caching models that account for the fact the isochronous data structures span 8 micro-frames. The three caching models are: no caching, micro-frame caching and frame caching. When software is adding new isochronous transactions to the schedule, it always performs a read of the USB_FRINDEX register to determine the current frame and micro-frame the host controller is currently executing. Of course, there is no information about where in the micro-frame the host controller is, so a constant uncertainty-factor of one micro-frame has to be assumed. Combining the knowledge of where the host controller is executing with the knowledge of the caching model allows the definition of simple algorithms for how closely software can reliably work to the executing host controller. No caching is indicated with a value of zero in the Isochronous Scheduling Threshold field. The host controller may pre-fetch data structures during a periodic schedule traversal (per micro-frame) but always dumps any accumulated schedule state at the end of the micro-frame. At the appropriate time relative to the beginning of every microframe, the host controller always begins schedule traversal from the frame list. Software can use the value of the USB_FRINDEX register (plus the constant 1 uncertainty-factor) to determine the approximate position of the executing host controller. When no caching is selected, software can add an isochronous transaction as near as 2 micro-frames in front of the current executing position of the host controller. Frame caching is indicated with a non-zero value in bit [7] of the Isochronous Scheduling Threshold field. In the frame-caching model, system software assumes that the host controller caches one (or more) isochronous data structures for an entire frame (8 microframes). Software uses the value of the USB_FRINDEX register (plus the constant 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2195 Functional Description uncertainty) to determine the current micro-frame/frame (assume modulo 8 arithmetic in adding the constant 1 to the micro-frame number). For any current frame N, if the current micro-frame is 0 to 6, then software can safely add isochronous transactions to Frame N + 1. If the current micro-frame is 7, then software can add isochronous transactions to Frame N + 2. Micro-frame caching is indicated with a non-zero value in the least-significant 3 bits of the Isochronous Scheduling Threshold field. System software assumes the host controller caches one or more periodic data structures for the number of micro-frames indicated in the Isochronous Scheduling Threshold field. For example, if the count value were 2, then the host controller keeps a window of 2 micro-frames worth of state (current microframe, plus the next) on-chip. On each micro-frame boundary, the host controller releases the current micro-frame state and begins accumulating the next micro-frame state. 31.2.6.3.9 Asynchronous Schedule The Asynchronous schedule traversal is enabled or disabled through the Asynchronous Schedule Enable bit in the USB_USBCMD register. If the Asynchronous Schedule Enable bit is set to zero, then the host controller simply does not try to access the asynchronous schedule through the USB_ASYNCLISTADDR register. Likewise, when the Asynchronous Schedule Enable bit is one, then the host controller does use the USB_ASYNCLISTADDR register to traverse the asynchronous schedule. Modifications to the Asynchronous Schedule Enable bit are not necessarily immediate. Rather the new value of the bit is taken into consideration the next time the host controller needs to use the value of the USB_ASYNCLISTADDR register to get the next queue head. The Asynchronous Schedule Status bit in the USB_USBSTS register indicates status of the asynchronous schedule. System software enables (or disables) the asynchronous schedule by writing one (or zero) to the Asynchronous Schedule Enable bit in the USB_USBCMD register. Software then can poll the Asynchronous Schedule Status bit to determine when the asynchronous schedule has made the desired transition. Software must not modify the Asynchronous Schedule Enable bit unless the value of the Asynchronous Schedule Enable bit equals that of the Asynchronous Schedule Status bit. The asynchronous schedule is used to manage all Control and Bulk transfers. Control and Bulk transfers are managed using queue head data structures. The asynchronous schedule is based at the USB_ASYNCLISTADDR register. The default value of the USB_ASYNCLISTADDR register after reset is undefined and the schedule is disabled when the Asynchronous Schedule Enable bit is zero. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2196 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Software may only write this register with defined results when the schedule is disabled. For example, Asynchronous Schedule Enable bit in the USB_USBCMD and the Asynchronous Schedule Status bit in the USB_USBSTS register are zero. System software enables execution from the asynchronous schedule by writing a valid memory address (of a queue head) into this register. Then software enables the asynchronous schedule by setting the Asynchronous Schedule Enable bit to one. The asynchronous schedule is actually enabled when the Asynchronous Schedule Status bit is one. When the host controller begins servicing the asynchronous schedule, it begins by using the value of the USB_ASYNCLISTADDR register. It reads the first referenced data structure and begins executing transactions and traversing the linked list as appropriate. When the host controller completes processing the asynchronous schedule, it retains the value of the last accessed queue head's horizontal pointer in the USB_ASYNCLISTADDR register. Next time the asynchronous schedule is accessed, this is the first data structure that is serviced. This provides round-robin fairness for processing the asynchronous schedule. A host controller completes processing the asynchronous schedule when one of the following events occur: * The end of a micro-frame occurs. * The host controller detects an empty list condition (see Empty Asynchronous Schedule Detection ) * The schedule has been disabled through the Asynchronous Schedule Enable bit in the USB_USBCMD register. The queue heads in the asynchronous list are linked into a simple circular list as shown in Figure 31-12. Queue head data structures are the only valid data structures that may be linked into the asynchronous schedule. An isochronous transfer descriptor (iTD or siTD) in the asynchronous schedule yields undefined results. The maximum packet size field in a queue head is sized to accommodate the use of this data structure for all non-isochronous transfer types. The USB Specification, Revision 2.0 specifies the maximum packet sizes for all transfer types and transfer speeds. System software should always parameterize the queue head data structures according to the core specification requirements. 31.2.6.3.9.1 Adding Queue Heads to Asynchronous Schedule This is a software requirement section. There are two independent events for adding queue heads to the asynchronous schedule. The first is the initial activation of the asynchronous list. The second is inserting a new queue head into an activated asynchronous list. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2197 Functional Description Activation of the list is simple. System software writes the physical memory address of a queue head into the USB_ASYNCLISTADDR register, then enables the list by setting the Asynchronous Schedule Enable bit in the USB_USBCMD register to one. When inserting a queue head into an active list, software must ensure that the schedule is always coherent from the host controllers' point of view. This means that the system software must ensure that all queue head pointer fields are valid. For example, qTD pointers have T-Bits set to one or reference valid qTDs and the Horizontal Pointer references a valid queue head data structure. The following algorithm represents the functional requirements: InsertQueueHead (pQHeadCurrent, pQueueHeadNew) --- Requirement: all inputs must be properly initialized. --- pQHeadCurrent is a pointer to a queue head that is -- already in the active list -- pQHeadNew is a pointer to the queue head to be added --- This algorithm links a new queue head into a existing -- list -pQueueHeadNew.HorizontalPointer = pQueueHeadCurrent.HorizontalPointer pQueueHeadCurrent.HorizontalPointer = physicalAddressOf(pQueueHeadNew) End InsertQueueHead 31.2.6.3.9.2 Removing Queue Heads from Asynchronous Schedule This is a software requirement section. There are two independent events for removing queue heads from the asynchronous schedule. The first is shutting down (deactivating) the asynchronous list. The second is extracting a single queue head from an activated list. Software deactivates the asynchronous schedule by setting the Asynchronous Schedule Enable bit in the USB_USBCMD register to zero. Software can determine when the list is idle when the Asynchronous Schedule Status bit in the USB_USBSTS register is zero. The normal mode of operation is that software removes queue heads from the asynchronous schedule without shutting it down. Software must not remove an active queue head from the schedule. Software should first deactivate all active qTDs, wait for the queue head to go inactive, then remove the queue head from the asynchronous list. Software removes a queue head from the asynchronous list through the following algorithm. As illustrated, the unlinking is quite easy. Software merely must ensure all of the link pointers reachable by the host controller are kept consistent. UnlinkQueueHead (pQHeadPrevious, pQueueHeadToUnlink, pQHeadNext) --- Requirement: all inputs must be properly initialized. --- pQHeadPrevious is a pointer to a queue head that -- references the queue head to remove -- pQHeadToUnlink is a pointer to the queue head to be -- removed i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2198 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller -- pQheadNext is a pointer to a queue head still in the -- schedule. Software provides this pointer with the -- following strict rules: -if the host software is one queue head, then -pQHeadNext must be the same as -QueueheadToUnlink.HorizontalPointer. If the host -software is unlinking a consecutive series of -queue heads, QHeadNext must be set by software to -the queue head remaining in the schedule. --- This algorithm unlinks a queue head from a circular list -pQueueHeadPrevious.HorizontalPointer = pQueueHeadToUnlink.HorizontalPointer pQueueHeadToUnlink.HorizontalPointer = pQHeadNext End UnlinkQueueHead If software removes the queue head with the H-bit set to one, it must select another queue head still linked into the schedule and set its H-bit to one. This should be completed before removing the queue head. The requirement is that software keep one queue head in the asynchronous schedule, with its H-bit set to one. At the point software has removed one or more queue heads from the asynchronous schedule, it is unknown whether the host controller has a cached pointer to them. Similarly, it is unknown how long the host controller might retain the cached information, as it is implementation dependent and may be affected by the actual dynamics of the schedule load. Therefore, once software has removed a queue head from the asynchronous list, it must retain the coherency of the queue head (link pointers, and so on). It cannot disturb the removed queue heads until it knows that the host controller does not have a local copy of a pointer to any of the removed data structures. The method software uses to determine when it is safe to modify a removed queue head is to handshake with the host controller. The handshake mechanism allows software to remove items from the asynchronous schedule, then execute a simple, lightweight handshake that is used by software as a key that it can free (or reuse) the memory associated the data structures it has removed from the asynchronous schedule. The handshake is implemented with three bits in the host controller. The first bit is a command bit (Interrupt on Async Advance Doorbell bit in the USB_USBCMD register) that allows software to inform the host controller that something has been removed from its asynchronous schedule. The second bit is a status bit (Interrupt on Async Advance bit in the USB_USBSTS register) that the host controller sets after it has released all on-chip state that may potentially reference one of the data structures just removed. When the host controller sets this status bit to one, it also sets the command bit to zero. The third bit is an interrupt enable (Interrupt on Async Advance bit in the USB_USBINTR register) that is matched with the status bit. If the status bit is one and the interrupt enable bit is one, then the host controller asserts a hardware interrupt. The figure below illustrates a general example. In this example, consecutive queue heads (B and C) are unlinked from the schedule using the algorithm above. Before the unlink operation, the host controller has a copy of queue head A. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2199 Functional Description The unlink algorithm requires that as software unlinks each queue head, the unlinked queue head is loaded with the address of a queue head that remains in the asynchronous schedule. When the host controller observes that doorbell bit being set to one, it makes a note of the local reachable schedule information. In this example, the local reachable schedule information includes both queue heads (A and B). It is sufficient that the host controller can set the status bit (and clear the doorbell bit) as soon as it has traversed beyond current reachable schedule information (that is traversed beyond queue head (B) in this example). The following figure illustrates the generic queue head unlink scenario. Memory State Memory State A A A B C D B D C A USBCMD.Interrupt on Async Advance Doorbell = 1 HC State USBSTS.Interrupt on Async Advance = 0 USBCMD.Interrupt on Async Advance Doorbell = 0 HC State Before Unlink After Unlink (B,C) & @ Doorbell Memory State A B D C D USBCMD.Interrupt on Async Advance Doorbell = 0 HC State USBSTS.Interrupt on Async Advance = 1 After Doorbell Figure 31-18. Generic Queue Head Unlink Scenario Alternatively, a host controller implementation is allowed to traverse the entire asynchronous schedule list (for example, observed the head of the queue (twice)) before setting the Advance on Async status bit to one. Software may re-use the memory associated with the removed queue heads after it observes the Interrupt on Async Advance status bit is set to one, following assertion of the doorbell. Software should acknowledge the Interrupt on Async Advance status as indicated in the USB_USBSTS register, before using the doorbell handshake again. 31.2.6.3.9.3 Empty Asynchronous Schedule Detection The Enhanced Host Controller Interface uses two bits to detect when the asynchronous schedule is empty. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2200 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller The queue head data structure (see Table 31-22) defines an H-bit in the queue head, which allows software to mark a queue head as being the head of the reclaim list. The Enhanced Host Controller Interface also keeps a 1-bit flag in the USB_USBSTS register (Reclamation) that is set to zero when the Enhanced Interface Host Controller observes a queue head with the H-bit set to one. The reclamation flag in the status register is set to one when any USB transaction from the asynchronous schedule is executed (or whenever the asynchronous schedule starts, see Asynchronous schedule traversal: Start Event). If the Enhanced Host Controller Interface ever encounters an H-bit of one and a Reclamation bit of zero, the EHCI controller simply stops traversal of the asynchronous schedule. An example illustrating the H-bit in a schedule is shown in the following figure. 1: Transaction Executed 0: Head of List Seen Reclamation Flag USBCMD USBSTS ... Typ T ASYNCLISTADDR ... Operational Registers Horizontal Ptr 01 0 Typ T Horizontal Ptr 01 0 Typ T Horizontal Ptr 01 0 1 Operational Area 0 Operational Area 0 Operational Area H H H List Head Asynchronous Schedule Figure 31-19. Asynchronous Schedule List w/Annotation to Mark Head of List Software must ensure there is at most one queue head with the H-bit set to one, and that it is always coherent with respect to the schedule. 31.2.6.3.9.4 Restarting Asynchronous Schedule Before EOF There are many situations where the host controller will detect an empty list long before the end of the micro-frame. It is important to remember that under many circumstances the schedule traversal has stopped due to Nak/Nyet responses from all endpoints. An example of particular interest is when a start-split for a bulk endpoint occurs early in the micro-frame. Given the EHCI simple traversal rules, the complete-split for that transaction may Nak/Nyet out very quickly. If it is the only item in the schedule, then the host controller ceases traversal of the Asynchronous schedule very early in the microframe. In order to provide reasonable service to this endpoint, the host controller should issue the complete-split before the end of the current micro-frame, instead of waiting i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2201 Functional Description until the next micro-frame. When the reason for host controller idling asynchronous schedule traversal is because of empty list detection, it is mandatory the host controller implement a 'waking' method to resume traversal of the asynchronous schedule. An example method is described below. 31.2.6.3.9.4.1 Example Method for Restarting Asynchronous Schedule Traversal The reason for idling the host controller when the list is empty is to keep the host controller from unnecessarily occupying too much memory bandwidth. The question is: how long should the host controller stay idle before restarting? The answer in this example is based on deriving a manifest constant, which is the amount of time the host controller will stay idle before restarting traversal. In this example, the manifest constant is called AsyncSchedSleepTime, and has a value of 10 sec. The value is derived based on the analysis in Example Derivation for AsyncSchedSleepTime, The traversal algorithm is simple: * Traverse the Asynchronous schedule until the either an End-Of-micro-Frame event occurs, or an empty list is detected. If the event is an End-of-micro-Frame, go attempt to traverse the Periodic schedule. If the event is an empty list, then set a sleep timer and go to a schedule sleep state. * When the sleep timer expires, set working context to the Asynchronous Schedule start condition and go to schedule active state. The start context allows the HC to reload Nakcnt fields, and so on. So the HC has a chance to run for more than one iteration through the schedule. This process simply repeats itself each micro-frame. The figure below illustrates a sample state machine to manage the active and sleep states of the Asynchronous Schedule traversal policy. There are three states: Actively traversing the Asynchronous schedule, Sleeping, and Not Active. The last two are similar in terms of interaction with the Asynchronous schedule, but the Not Active state means that the host controller is busy with the Periodic schedule or the Asynchronous schedule is not enabled. The Sleeping state is specifically a special state where the host controller is just waiting for a period of time before resuming execution of the Asynchronous schedule. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2202 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Sleep Timer Expires => B Periodic Schedule Complete And Async Schedule Empty List => A Enabled Asyn Sched Asyn Sched Sleeping Active End of micro-Frame Asyn Sched Denotes an action is Not Active triggered by this event. Action is described where is defined End of micro-Frame => C End of micro-Frame Figure 31-20. Example State Machine for Managing Asynchronous Schedule Traversal The actions referred to in the figure above are defined in the following table. Table 31-37. Asynchronous Schedule SM Transition Actions Action Action Description Label A On detection of the empty list, the host controller sets the AsynchronousTraversalSleepTimer to AsyncSchedSleepTime. B When the AsynchronousTraversalSleepTimer expires, the host controller sets the Reclamation bit in the USBSTS register to one and moves the Nak Counter reload state machine to WaitForListHead (see Nak Count Reload Control ). C The host controller cancels the sleep timer (AsynchronousTraversalSleepTimer). 31.2.6.3.9.4.2 Async Sched Not Active This is the initial state of the traversal state machine after a host controller reset. The traversal state machine does not leave this state when the Asynchronous Schedule Enable bit in the USB_USBCMD register is zero. This state is entered from Async Sched Active or Async Sched Sleeping states when the end-of-micro-frame event is detected. 31.2.6.3.9.4.3 Async Sched Active This state is entered from the Async Sched Not Active state when the periodic schedule is not active. It is also entered from the Async Sched Sleeping states when the AsyncrhonousTraversalSleepTimer expires. On every transition into this state, the host controller sets the Reclamation bit in the USB_USBSTS register to one. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2203 Functional Description While in this state, the host controller continually traverses the asynchronous schedule until either the end of micro-frame or an empty list condition is detected. 31.2.6.3.9.4.4 Async Sched Sleeping The state is entered from the Async Sched Active state when a schedule empty condition is detected. On entry to this state, the host controller sets the AsynchronousTraversalSleepTimer to AsyncSchedSleepTime. 31.2.6.3.9.4.5 Example Derivation for AsyncSchedSleepTime The derivation is based on analysis of what work the host controller could be doing next. It assumes the host controller does not keep any state about what work is possibly pending in the asynchronous schedule. The schedule could contain any mix of the possible combinations of high- full- or low-speed control and bulk requests. The table below summarizes some of the typical 'next transactions' that could be in the schedule, and the amount of time (for example footprint, or wall clock) the transaction takes to complete. Table 31-38. Typical Low-/Full-speed Transaction Times Transaction Attributes Footprint (time) Description Speed HS 11.9 ms Maximum foot print for a worst-case, full-sized bulk data transaction. Size 512 9.45 ms Maximum footprint for an approximate best-case, full-sized bulk data transaction. Type Bulk Speed FS ~50 ms Approximate typical for full-sized bulk data. An 8-byte low-speed is about 2x, or between 90 and 100 ms. Size 64 Type Bulk Speed FS ~12 ms Approximate typical for 8-byte bulk/control (that is setup) Size 8 Type Cntrl A AsyncSchedSleepTime value of 10 s provides a reasonable relaxation of the system memory load and still provides a good level of service for the various transfer types and payload sizes. For example, say we detect an empty list after issuing a start-split for a 64byte full-speed bulk request. Assuming this is the only thing in the list, the host controller gets the results of the full-speed transaction from the hub during the fifth complete-split request. If the full-speed transaction was an IN and it nak'd, the 10 s sleep period would allow the host controller to get the NAK results on the first complete-split. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2204 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.3.9.5 Asynchronous schedule traversal: Start Event Once the HC has idled itself through the empty schedule detection (Section 0), it will naturally activate and begin processing from the Periodic Schedule at the beginning of each micro-frame. In addition, it may have idled itself early in a micro-frame. When this occurs (idles early in the micro-frame) the HC must occasionally re-activate during the micro-frame and traverse the asynchronous schedule to determine whether any progress can be made. The requirements and method for this restart are described in Restarting Asynchronous Schedule Before EOF . Asynchronous schedule Start Events are defined to be: * Whenever the host controller transitions from the periodic schedule to the asynchronous schedule. If the periodic schedule is disabled and the asynchronous schedule is enabled, then the beginning of the micro-frame is equivalent to the transition from the periodic schedule, or * The asynchronous schedule traversal restarts from a sleeping state (see Restarting Asynchronous Schedule Before EOF ). 31.2.6.3.9.6 Reclamation Status Bit (USBSTS Register) The operation of the empty asynchronous schedule detection feature (see Empty Asynchronous Schedule Detection ) depends on the proper management of the Reclamation bit in the USB_USBSTS register. The host controller tests for an empty schedule just after it fetches a new queue head while traversing the asynchronous schedule (see Fetch Queue Head ). It is required that the host controller sets the Reclamation bit to one whenever an asynchronous schedule traversal Start Event, as documented inAsynchronous schedule traversal: Start Event, occurs. The Reclamation bit is also set to one whenever the host controller executes a transaction while traversing the asynchronous schedule (see Execute Transaction ). The host controller sets the Reclamation bit to zero whenever it finds a queue head with its H-bit set to one. Software should only set a queue head's H-bit if the queue head is in the asynchronous schedule. If software sets the H-bit in an interrupt queue head to one, the resulting behavior is undefined. The host controller may set the Reclamation bit to zero when executing from the periodic schedule. 31.2.6.3.10 Operational Model for Nak Counter This section describes the operational model for the NakCnt field defined in a queue head. See Queue Head Initialization for more information. Software should not use this feature for interrupt queue heads. This rule is not required to be enforced by the host controller. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2205 Functional Description USB protocol has built-in flow control through the Nak response by a device. There are several scenarios, beyond the Ping feature, where an endpoint may naturally Nak or Nyet the majority of the time. An example is the host controller management of the split transaction protocol for control and bulk endpoints. All bulk endpoints (High- or Fullspeed) are serviced through the same asynchronous schedule. The time between the Startsplit transaction and the first Complete-split transaction could be very short (that is like when the endpoint is the only one in the asynchronous schedule). The hub NYETs (effectively Naks) the Complete-split transaction until the classic transaction is complete. This could result in the host controller thrashing memory, repeatedly fetching the queue head and executing the transaction to the Hub, which does not complete until after the transaction on the classic bus completes. The two component fields in a queue head to support the throttling feature: a counter field (NakCnt), and a counter reload field (RL). NakCnt is used by the host controller as one of the criteria to determine whether or not to execute a transaction to the endpoint. The two operational modes associated with this counter: * Not Used- This mode is set when the RL field is zero. The host controller ignores the NakCnt field for any execution of transactions through a queue head with an RL field of zero. Software must use this selection for interrupt endpoints. * Nak Throttle Mode- This mode is selected when the RL field is non-zero. In this mode, the value in the NakCnt field represents the maximum number of Nak or Nyet responses the host controller tolerates on each endpoint. In this mode, the HC decrements the NakCnt field based on the token/handshake criteria listed in the table below. The host controller must reload NakCnt when the endpoint successfully moves data (for example, policy to reward device for moving data). The following table describes the NakCnt field adjustment rules. Table 31-39. NakCnt Field Adjustment Rules Token Handshake Handshake NAK NYET IN/PING decrement NakCnt N/A (protocol error) OUT decrement NakCnt No Action1 Start Split decrement NakCnt N/A (protocol error) Complete Split No Action Decrement NakCnt 1. Recommended behavior on this response is to reload NakCnt In summary, system software enables the counter by setting the reload field (RL) to a non-zero value. The host controller may execute a transaction if NakCnt is non-zero. The host controller does not execute a transaction if NakCnt is zero. The reload mechanism is described in detail in Nak Count Reload Control . i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2206 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller NOTE When all queue heads in the Asynchronous Schedule either exhausts all transfers or all NakCnt's go to zero, then the host controller detects an empty Asynchronous Schedule and idle schedule traversal (see Empty Asynchronous Schedule Detection ). Any time the host controller begins a new traversal of the Asynchronous Schedule, a Start Event is assumed, see Asynchronous schedule traversal: Start Event. Every time a Start-Event occurs, the Nak Count reload procedure is enabled. 31.2.6.3.10.1 Nak Count Reload Control When the host controller reaches the Execute Transaction state for a queue head (meaning that it has an active operational state), it checks to determine whether the NakCnt field should be reloaded from RL (see Execute Transaction ). If the answer is yes, then RL is copied into NakCnt. After the reload or if the reload is not active, the host controller evaluates whether to execute the transaction. The host controller must reload nak counters (NakCnt see Table 31-22) in queue heads during the first pass through the reclamation list after an asynchronous schedule Start Event (see Asynchronous schedule traversal: Start Event for the definition of the Start Event). The Asynchronous Schedule should have at most one queue head marked as the head (see Figure 31-19). The following figure illustrates an example state machine that satisfies the operational requirements of the host controller detecting the first pass through the Asynchronous Schedule. This state machine is maintained internal to the host controller and is only used to gate reloading of the nak counter during the queue head traversal state: Execute Transaction (see the figure below). The host controller does not perform the nak counter reload operation if the RL field (see Table 31-22) is set to zero. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2207 Functional Description Do Reload QH.H == 1 Wait for List Head Start Event QH.H == 1 Wait for Start Event Figure 31-21. Example HC State Machine for Controlling Nak Counter Reloads 31.2.6.3.10.1.1 Wait for List Head This is the initial state. The state machine enters this state from Wait for Start Event when a start event as defined in Asynchronous schedule traversal: Start Eventoccurs. The purpose of this state is to wait for the first observation of the head of the Asynchronous Schedule. This occurs when the host controller fetches a queue head whose H-bit is set to one. 31.2.6.3.10.1.2 Do Reload This state is entered from the Wait for List Head state when the host controller fetches a queue head with the H-bit set to one. While in this state, the host controller performs nak counter reloads for every queue head visited that has a non-zero nak reload value (RL) field. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2208 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.3.10.1.3 Wait for Start Event This state is entered from the Do Reload state when a queue head with the H-bit set to one is fetched. While in this state, the host controller does not perform nak counter reloads. 31.2.6.3.11 Managing Control/Bulk/Interrupt Transfers through Queue Heads This section presents an overview of how the host controller interacts with queuing data structures. Queue heads use the Queue Element Transfer Descriptor (qTD) structure. One queue head is used to manage the data stream for one endpoint. The queue head structure contains static endpoint characteristics and capabilities. It also contains a working area from where individual bus transactions for an endpoint are executed (see Overlay area defined in Table 31-22). Each qTD represents one or more bus transactions, which is defined in the context of this specification as a transfer. The general processing model for the host controller's use of a queue head is simple: * * * * read a queue head, execute a transaction from the overlay area, write back the results of the transaction to the overlay area, move to the next queue head. If the host controller encounters errors during a transaction, the host controller sets one (or more) of the error reporting bits in the queue head's Status field. The Status field accumulates all errors encountered during the execution of a qTD (for example, the error bits in the queue head Status field are 'sticky' until the transfer (qTD) has completed). This state is always written back to the source qTD when the transfer is complete. On transfer (for example, buffer or halt conditions) boundaries, the host controller must autoadvance (without software intervention) to the next qTD. Additionally, the hardware must be able to halt the queue so no additional bus transactions occurs for the endpoint and the host controller does not advance the queue. An example host controller operational state machine of a queue head traversal is illustrated in the following figure. This state machine is a model for how a host controller should traverse a queue head. The host controller must be able to advance the queue from the Fetch QH state in order to avoid all hardware/software race conditions. This simple mechanism allows software to simply link qTDs to the queue head and activate them, then the host controller always find them if/when they are reachable. The figure below illustrates the Host Controller Queue Head Traversal State Machine. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2209 Functional Description Start Halted or !Active and 1 bit !Active Advance Queue Fetch QH !Active And !Halted Active And !Halted Active Execute Transaction Active !Active Write Back qTD Follow Qh Horizontal Pointer Figure 31-22. Host Controller Queue Head Traversal State Machine This traversal state machine applies to all queue heads, regardless of transfer type or whether split transactions are required. The following sections describe each state. Each state description describes the entry criteria. The Execute Transaction state (see Execute i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2210 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Transaction ) describes the basic requirements for all endpoints. Split Transactions for Asynchronous Transfers and Split Transaction Interrupt describe details of the required extensions to the Execute Transaction state for endpoints requiring split transactions. NOTE Prior to software placing a queue head into either the periodic or asynchronous list, software must ensure the queue head is properly initialized. Minimally, the queue head should be initialized to the following (see Section Queue Head for layout of a queue head): Valid static endpoint state. * For the very first use of a queue head, software may zero-out the queue head transfer overlay, then set the Next qTD Pointer field value to reference a valid qTD. 31.2.6.3.11.1 Fetch Queue Head A queue head can be referenced from the physical address stored in the ASYNCLISTADDR Register (see _ASYNCLISTADDR)/_ENDPTLISTADDR Additionally, it may be referenced from the Next LinkPointer field of an iTD, siTD, FSTN or another Queue Head. If the referencing link pointer has the Typ field set to indicate a queue head, it is assumed to reference a queue head structure as defined in Table 31-22. While in this state, the host controller performs operations to implement empty schedule detection (see Empty Asynchronous Schedule Detection ) and Nak Counter reloads (see Operational Model for Nak Counter). After the queue head has been fetched, the host controller conducts the following queries for empty schedule detection: * If queue head is not an interrupt queue head (that is S-mask is zero), and * The H-bit is one, and * The Reclamation bit in the USBSTS register is zero. When these criteria are met, the host controller stops traversing the asynchronous list (as described in Empty Asynchronous Schedule Detection ). When the criteria are not met, the host controller continues schedule traversal. If the queue head is not an interrupt and the H-bit is one and the Reclamation bit is one, then the host controller sets the Reclamation bit in the USBSTS register to zero before completing this state. The operations for reloading of the Nak Counter are described in detail in Operational Model for Nak Counter. This state is complete when the queue head has been read on-chip. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2211 Functional Description 31.2.6.3.11.2 Advance Queue To advance the queue, the host controller must find the next qTD, adjust pointers, perform the overlay and write back the results to the queue head. This state is entered from the FetchQHD state if the overlay Active and Halt bits are set to zero. On entry to this state, the host controller determines which next pointer to use to fetch a qTD, fetches a qTD and determines whether or not to perform an overlay. NOTE If the I-bit is one and the Active bit is zero, the host controller immediately skips processing of this queue head, exits this state and uses the horizontal pointer to the next schedule data structure. If the field Bytes to Transfer is not zero and the T-bit in the Alternate Next qTD Pointer is set to zero, then the host controller uses the Alternate Next qTD Pointer. Otherwise, the host controller uses the NextqTD Pointer. If NextqTD Pointer's T-bit is set to one, then the host controller exits this state and uses the horizontal pointer to the next schedule data structure. Using the selected pointer the host controller fetches the referenced qTD. If the fetched qTD has its Active bit set to one, the host controller moves the pointer value used to reach the qTD (Next or Alternate Next) to the Current qTD Pointer field, then performs the overlay. If the fetched qTD has its Active bit set to zero, the host controller aborts the queue advance and follows the queue head's horizontal pointer to the next schedule data structure. The host controller performs the overlay based on the following rules: * The value of the data toggle (dt) field in the overlay area depends on the value of the data toggle control (dtc) bit (see Table 31-24). * If the EPS field indicates the endpoint is a high-speed endpoint, the Ping state field is preserved by the host controller. The value of this field is not changed as a result of the overlay. * C-prog-mask field is set to zero (field from incoming qTD is ignored, as is the current contents of the overlay area). * Frame Tag field is set to zero (field from incoming qTD is ignored, as is the current contents of the overlay area). * NakCnt field in the overlay area is loaded from the RL field in the queue head's Static Endpoint State. * All other areas of the overlay are set by the incoming qTD. The host controller exits this state when it has committed the write to the queue head. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2212 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.3.11.3 Execute Transaction The host controller enters this state from the Fetch Queue Head state only if the Active bit in Status field of the queue head is set to one. On entry to this state, the host controller executes a few pre-operations, then checks some pre-condition criteria before committing to executing a transaction for the queue head. The pre-operations performed and the pre-condition criteria depend on whether the queue head is an interrupt endpoint. The host controller can determine that a queue head is an interrupt queue head when the queue head's S-mask field contains a non-zero value. It is the responsibility of software to ensure the S-mask field is appropriately initialized based on the transfer type. There are other criteria that must be met if the EPS field indicates that the endpoint is a low- or full-speed endpoint, see Split Transactions for Asynchronous Transfers and Split Transaction Interrupt . 31.2.6.3.11.3.1 Interrupt Transfer Pre-condition Criteria If the queue head is for an interrupt endpoint (for example, non-zero S-mask field), then the FRINDEX[2:0] field must identify a bit in the S-mask field that has one in it. For example, an S-mask value of 00100000b would evaluate to true only when FRINDEX[2:0] is equal to 101b. If this condition is met then the host controller considers this queue head for a transaction. 31.2.6.3.11.3.2 Asynchronous Transfer Pre-operations and Pre-condition Criteria If the queue head is not for an interrupt endpoint (for example, zero S-mask field), then the host controller performs one pre-operation and then evaluates one pre-condition criteria. The pre-operation is: Checks the Nak counter reload state (Operational Model for Nak Counter). It may be necessary for the host controller to reload the Nak Counter field. The reload is performed at this time. The pre-condition evaluated is: * Whether or not the NakCnt field has been reloaded, the host controller checks the value of the NakCnt field in the queue head. If NakCnt is non-zero, or if the Reload Nak Counter field is zero, then the host controller considers this queue head for a transaction. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2213 Functional Description 31.2.6.3.11.3.3 Transfer Type Independent Pre-operations Regardless of the transfer type, the host controller always performs at least one preoperation and evaluates one pre-condition. The pre-operation is: * A host controller internal transaction (down) counter qHTransactionCounter is loaded from the queue head's Mult field. A host controller implementation is allowed to ignore this for queue heads on the asynchronous list. It is mandatory for interrupt queue heads. Software should ensure that the Mult field is set appropriately for the transfer type. The pre-conditions evaluated are: * The host controller determines whether there is enough time in the micro-frame to complete this transaction (see Transaction Fit - A Best-Fit Approximation Algorithm for an example evaluation method). If there is not enough time to complete the transaction, the host controller exits this state. * If the value of qHTransactionCounter for an interrupt endpoint is zero, then the host controller exits this state. When the pre-operations are complete and pre-conditions are met, the host controller sets the Reclamation bit in the USBSTS register to one and then begins executing one or more transactions using the endpoint information in the queue head. The host controller iterates qHTransactionCounter times in this state executing transactions. After each transaction is executed, qHTransactionCounter is decremented by one. The host controller exits this state when one of the following events occurs: * * * * * The qHTransactionCounter decrements to zero, or The endpoint responds to the transaction with any handshake other than an ACK,4 or The transaction experiences a transaction error, or The Active bit in the queue head goes to zero, or There is not enough time in the micro-frame left to execute the next transaction(see Transaction Fit - A Best-Fit Approximation Algorithm ) for example method for implementing the frame boundary test). NOTE For a high-bandwidth interrupt OUT endpoint, the host controller may optionally immediately retry the transaction if it fails. The results of each transaction is recorded in the on-chip overlay area. If data was successfully moved during the transaction, the transfer state in the overlay area is advanced. To advance queue head's transfer state, the Total Bytes to Transfer field is decremented by the number of bytes moved in the transaction, the data toggle bit (dt) is toggled, the current page offset is advanced to the next appropriate value (for example, i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2214 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller advanced by the number of bytes successfully moved), and the C_Page field is updated to the appropriate value (if necessary). See Buffer Pointer List Use for Data Streaming with qTDs . NOTE The Total Bytes To Transfer field may be zero when all the other criteria for executing a transaction are met. When this occurs, the host controller executes zero-length transaction to the endpoint. If the PID_Code field indicates an IN transaction and the device delivers data, the host controller detects a packet babble condition, set the babble and halted bits in the Status field, set the Active bit to zero, write back the results to the source qTD, then exit this state. In the event an IN token receives a data PID mismatch response, the host controller must ignore the received data (for example not advance the transfer state for the bytes received). Additionally, if the endpoint is an interrupt IN, then the host controller must record that the transaction occurred (for example, decrement qHTransactionCounter). It is recommended (but not required) the host controller continue executing transactions for this endpoint if the resultant value of qHTransactionCounter is greater than one. If the response to the IN bus transaction is a Nak (or Nyet) and RL is non-zero, NakCnt is decremented by one. If RL is zero, then no write-back by the host controller is required (for a transaction receiving a Nak or Nyet response and the value of CErr did not change). Software should set the RL field to zero if the queue head is an interrupt endpoint. Host controller hardware is not required to enforce this rule or operation. After the transaction has finished and the host controller has completed the post processing of the results (advancing the transfer state and possibly NakCnt, the host controller writes back the results of the transaction to the queue head's overlay area in main memory). The number of bytes moved during an IN transaction depends on how much data the device endpoint delivers. The maximum number of bytes a device can send is MaximumPacket Size. The number of bytes moved during an OUT transaction is either Maximum Packet Length bytes or Total Bytes to Transfer, whichever is less. If there was a transaction error during the transaction, the transfer state (as defined above) is not advanced by the host controller. The CErr field is decremented by one and the status field is updated to reflect the type of error observed. Transaction errors are summarized in Transaction Error . i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2215 Functional Description The following events causes the host controller to clear the Active bit in the queue head's overlay status field. When the Active bit transitions from one to zero, the transfer in the overlay is considered complete. The reason for the transfer completion (clearing the Active bit) determines the next state. * CErr field decrements to zero. When this occurs the Halted bit is set to one and Active is set to zero. This results in the hardware not advancing the queue and the pipe halts. Software must intercede to recover. * The device responds to the transaction with a STALL PID. When this occurs, the Halted bit is set to one and the Active bit is set to zero. This results in the hardware not advancing the queue and the pipe halts. Software must intercede to recover. * The Total Bytes to Transfer field is zero after the transaction completes. * For a zero length transaction, it was zero before the transaction was started. When this condition occurs, the Active bit is set to zero. * The PID code is an IN, and the number of bytes moved during the transaction is less than the Maximum Packet Length. When this occurs, the Active bit is set to zero and a short packet condition exists. The short-packet condition is detected during the Advance Queue state. Refer to Split Transactions for additional rules for managing low- and full-speed transactions. With the exception of a NAK response (when RL field is zero), the host controller always writes the results of the transaction back to the overlay area in main memory. This includes when the transfer completes. For a high-speed endpoint, the queue head information written back includes minimally the following fields: The PID Code field indicates an IN and the device sends more than the expected number of bytes (for example Maximum Packet Length or Total Bytes to Transfer bytes, whichever is less) (for example a packet babble). This results in the host controller setting the Halted bit to one. * NakCnt, dt, Total Bytes to Transfer, C_Page, Status, CERR, and Current Offset For a low- or full-speed device the queue head information written back also includes the fields: * C-prog-mask, FrameTag and S-bytes. The duration of this state depends on the time it takes to complete the transaction(s) and the status write to the overlay is committed. 31.2.6.3.11.3.4 Halting a Queue Head A halted endpoint is defined only for the transfer types that are managed through queue heads (control, bulk and interrupt). The following events indicate that the endpoint has reached a condition where no more activity can occur without intervention from the driver: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2216 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller * An endpoint may return a STALL handshake during a transaction, * A transaction had three consecutive error conditions, or * A Packet Babble error occurs on the endpoint. When any of these events occur (for a queue head) the Host Controller halts the queue head and set the USBERRINT status bit in the USB_n_USBSTS register to one. To halt the queue head, the Active bit is set to zero and the Halted bit is set to one. There may be other error status bits that are set when a queue is halted. The host controller always writes back the overlay area to the source qTD when the transfer is complete, regardless of the reason (normal completion, short packet or halt). The host controller does not advance the transfer state on a transaction that results in a Halt condition (for example no updates necessary for Total Bytes to Transfer, C_Page, Current Offset, and dt). The host controller must update CErr as appropriate. When a queue head is halted, the USB Error Interrupt bit in the USB_n_USBSTS register is set to one. If the USB Error Interrupt Enable bit in the USB_n_USBINTR register is set to one, a hardware interrupt is generated at the next interrupt threshold. 31.2.6.3.11.3.5 Asynchronous Schedule Park Mode Asynchronous Schedule Park mode is a special execution mode that can be enabled by system software, where the host controller is permitted to execute more than one bus transaction from a high-speed queue head in the Asynchronous schedule before continuing horizontal traversal of the Asynchronous schedule. This feature has no effect on queue heads or other data structures in the Periodic schedule. This feature is similar in intent as the Mult feature that is used in the Periodic schedule. Where-as the Mult feature is a characteristic that is tunable for each endpoint; park-mode is a policy that is applied to all high-speed queue heads in the asynchronous schedule. It is essentially the specification of an iterator for consecutive bus transactions to the same endpoint. All of the rules for managing bus transactions and the results of those as defined in Execute Transaction apply. This feature merely specifies how many consecutive times the host controller is permitted to execute from the same queue head before moving to the next queue head in the Asynchronous List. This feature should allow the host controller to attain better bus utilization for those devices that are capable of moving data at maximum rate, while at the same time providing a fair service to all endpoints. A host controller exports its capability to support this feature to system software by setting the Asynchronous Schedule Park Capability bit in the USB_n_HCCPARAMs register to one. This information keys system software that the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USB_n_USBCMD register are modifiable. System software enables the feature by writing a one to the Asynchronous Schedule Park Mode Enable bit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2217 Functional Description When park-mode is not enabled (for example Asynchronous Schedule Park Mode Enable bit in the USB_n_USBCMD register is zero), the host controller must not execute more than one bus transaction per high-speed queue head, per traversal of the asynchronous schedule. When park-mode is enabled, the host controller must not apply the feature to a queue head whose EPS field indicates a Low/Full-speed device (for example only one bus transaction is allowed from each Low/Full-speed queue head per traversal of the asynchronous schedule). Park-mode may only be applied to queue heads in the Asynchronous schedule whose EPS field indicates that it is a high-speed device. The host controller must apply park mode to queue heads whose EPS field indicates a high-speed endpoint. The maximum number of consecutive bus transactions a host controller may execute on a high-speed queue head is determined by the value in the Asynchronous Schedule Park Mode Count field in the USB_n_USBCMD register. Software must not set Asynchronous Schedule Park Mode Enable bit to one and also set Asynchronous Schedule Park Mode Count field to zero. The resulting behavior is not defined. An example behavioral example describes the operational requirements for the host controller implementing park-mode. This feature does not affect how the host controller handles the bus transaction as defined in Execute Transaction . It only effects how many consecutive bus transactions for the current queue head can be executed. All boundary conditions, error detection and reporting applies as usual. This feature is similar in concept to the use of the Mult field for high-bandwidth Interrupt for queue heads in the Periodic Schedule. The host controller effectively loads an internal down-counter PM-Count from Asynchronous Schedule Park Mode Count when Asyncrhonous Schedule Park Mode Enable bit is one, and a high-speed queue head is first fetched and meets all the criteria for executing a bus transaction. After the bus transaction, PM-Count is decremented. The host controller may continue to execute bus transactions from the current queue head until PM-Count goes to zero, an error is detected, the buffer for the current transfer is exhausted or the endpoint responds with a flow-control or STALL handshake. The following table summarizes the responses that effect whether the host controller continues with another bus transaction for the current queue head. Table 31-40. Actions for Park Mode, based on Endpoint Response and Residual Transfer State PID Endpoint Response Transfer State after Transaction PM-Count IN Bytes to Transfer Not Zero Allowed to perform another bus transaction.12 Zero Retire qTD and move to next QH Zero Don't care Move to next QH. Don't care Don't care Retire qTD and move to next QH. DATA[0,1] w/Maximum Not zero Packet sized data Not zero DATA[0,1] w/short packet Action Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2218 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-40. Actions for Park Mode, based on Endpoint Response and Residual Transfer State (continued) OUT PING NAK Don't care Don't care Move to next QH. STALL, XactErr Don't care Don't care Move to next QH. ACK Not zero Not Zero Allowed to perform another bus transaction.2 Not zero Zero Retire qTD and move to next QH Zero Don't' care Move to next QH. NYET, NAK Don't care Don't care Move to next QH. STALL, XactErr Don't care Don't care Move to next QH ACK Not Zero Not Zero Allowed to perform another bus transaction. 2 NAK Don't care Don't care Move to next QH STALL, XactErr Don't care Don't care Move to next QH 1. The host controller may continue to execute bus transactions from the current high-speed queue head (if PM-Count is not equal to zero), if a PID mismatch is detected (for example expected DATA1 and received DATA0, or visa-versa). 2. This specification does not require that the host controller execute another bus transaction when PM-Count is non-zero. Implementations are encouraged to make appropriate complexity and performance trade-offs. 31.2.6.3.11.4 Write Back qTD This state is entered from the Execute Transaction state when the Active bit is set to zero. The source data for the write-back is the transfer results area of the queue head overlay area (see Table 31-40). The host controller uses the Current qTD Pointer field as the target address for the qTD. The queue head transfer result area is written back to the transfer result area of the target qTD. This state is also referred to as: qTD retirement. The fields that must be written back to the source qTD include Total Bytes to Transfer, Cerr, and Status. The duration of this state depends on when the qTD write-back is committed. 31.2.6.3.11.5 Follow Queue Head Horizontal Pointer The host controller must use the horizontal pointer in the queue head to the next schedule data structure when any of the following conditions exist: * If the Active bit is one on exit from the Execute Transaction state, or * When the host controller exits the Write Back qTD state, or * If the Advance Queue state fails to advance the queue because the target qTD is not active, or * If the Halted bit is one on exit from the Fetch QH state. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2219 Functional Description There is no functional requirement that the host controller wait until the current transaction is complete before using the horizontal pointer to read the next linked data structure. However, it must wait until the current transaction is complete before executing the next data structure. 31.2.6.3.11.6 Buffer Pointer List Use for Data Streaming with qTDs A qTD has an array of buffer pointers, which is used to reference the data buffer for a transfer. This specification requires that the buffer associated with the transfer be virtually contiguous. This means: if the buffer spans more than one physical page, it must obey the following rules (the figure below illustrates an example): * The first portion of the buffer must begin at some offset in a page and extend through the end of the page. * The remaining buffer cannot be allocated in small chunks scattered around memory. For each 4 K chunk beyond the first page, each buffer portion matches to a full 4 K page. The final portion, which may only be large enough to occupy a portion of a page, must start at the top of the page and be contiguous within that page. The buffer pointer list in the qTD is long enough to support a maximum transfer size of 20 K bytes. This case occurs when all five buffer pointers are used and the first offset is zero. A qTD handles a 16 Kbyte buffer with any starting buffer alignment. The host controller uses the field C_Page field as an index value to determine which buffer pointer in the list should be used to start the current transaction. The host controller uses a different buffer pointer for each physical page of the buffer. This is always true, even if the buffer is physically contiguous. The host controller must detect when the current transaction spans a page boundary and automatically move to the next available buffer pointer in the page pointer list. The next available pointer is reached by incrementing C_Page and pulling the next page pointer from the list. Software must ensure there are sufficient buffer pointers to move the amount of data specified in the Bytes to Transfer field. The following figure illustrates a nominal example of how System software would initialize the buffer pointers list and the C_Page field for a transfer size of 16383 bytes. C_Page is set to zero. The upper 20-bits of Page 0 references the start of the physical page. Current Offset (the lower 12-bits of queue head Dword 7) holds the offset in the page for example 2049 (for example 4096-2047). The remaining page pointers are set to reference the beginning of each subsequent 4 K page. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2220 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 2047 The physical pages in memory may or may not be physically contiguous. C_Page = 0 Pointer (page 0) 4K Bytes to Transfer = 16383 bytes Pointer (page 1) Pointer (page 2) 4K Pointer (page 3) Pointer (page 4) 4K Page 0 = 2047 Page 1 = 4096 Page 2 = 4096 Page 3 = 4096 Page 4 = 2048 Total: 16383 2048 Figure 31-23. Example Mapping of qTD Buffer Pointers to Buffer Pages For the first transaction on the qTD (assuming a 512-byte transaction), the host controller uses the first buffer pointer (page 0 because C_Page is set to zero) and concatenates the Current Offset field. The 512 bytes are moved during the transaction, the Current Offset and Total Bytes to Transfer are adjusted by 512 and written back to the queue head working area. During the 4th transaction, the host controller needs 511 bytes in page 0 and one byte in page 1. The host controller increments C_Page (to 1) and use the page 1 pointer to move the final byte of the transaction. After the 4th transaction, the active page pointer is the page 1 pointer and Current Offset has rolled to one, and both are written back to the overlay area. The transactions continue for the rest of the buffer, with the host controller automatically moving to the next page pointer (that is C_Page) when necessary. The three conditions for how the host controller handles C_Page: * The current transaction does not span a page boundary. The value of C_Page is not adjusted by the host controller. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2221 Functional Description * The current transaction does span a page boundary. The host controller must detect the page cross condition and advance to the next buffer while streaming data to/from the USB. * The current transaction completes on a page boundary (that is the last byte moved for the current transaction is the last byte in the page for the current page pointer). The host controller must increment C_Page before writing back status for the transaction. NOTE The only valid adjustment the host controller may make to C_Page is to increment by one. 31.2.6.3.11.7 Adding Interrupt Queue Heads to the Periodic Schedule The link path(s) from the periodic frame list to a queue head establishes in which frames a transaction can be executed for the queue head. Queue heads are linked into the periodic schedule so they are polled at the appropriate rate. System software sets a bit in a queue head's S-Mask to indicate which micro-frame within 1 msec period a transaction should be executed for the queue head. Software must ensure that all queue heads in the periodic schedule have S-Mask set to a non-zero value. An S-mask with zero value in the context of the periodic schedule yields undefined results. If the desired poll rate is greater than one frame, system software can use a combination of queue head linking and S-Mask values to spread interrupts of equal poll rates through the schedule so that the periodic bandwidth is allocated and managed in the most efficient manner possible. Some examples are illustrated in the following table. Table 31-41. Example Periodic Reference Patterns for Interrupt Transfers with 2ms Poll Rate Frame # Reference Sequence Description 0, 2, 4, 6, 8, and so on A queue head for the bInterval of 2 msec (16 micro-frames) is linked into the periodic schedule so that it is reachable from the periodic frame list locations indicated in the previous column. In addition, the S-Mask field in the queue head is set to 01h, indicating that the transaction for the endpoint should be executed on the bus during micro-frame 0 of the frame. S-Mask = 01h 0, 2, 4, 6, 8, and so on S-Mask = 02h Another example of a queue head with a bInterval of 2 msec is linked into the periodic frame list at exactly the same interval as the previous example. However, the S-Mask is set to 02h indicating that the transaction for the endpoint should be executed on the bus during micro-frame 1 of the frame. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2222 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.3.11.8 Managing Transfer Complete Interrupts from Queue Heads The host controller sets an interrupt to be signaled at the next interrupt threshold when the completed transfer (qTD) has an Interrupt on Complete (IOC) bit set to one, or whenever a transfer (qTD) completes with a short packet. If system software needs multiple qTDs to complete a client request (that is like a control transfer) the intermediate qTDs do not require interrupts. System software may only need a single interrupt to notify it that the complete buffer has been transferred. System software may set IOC's to occur more frequently. A motivation for this may be that it wants early notification so that interface data structures can be re-used in a timely manner. 31.2.6.3.12 Ping Control USB 2.0 defines an addition to the protocol for high-speed devices called Ping. Ping is required for all USB 2.0 High-speed bulk and control endpoints. Ping is not allowed for a split-transaction stream. This extension to the protocol eliminates the bad side-effects of Naking OUT endpoints. The Status field has a Ping State bit, which the host controller uses to determine the next actual PID it uses in the next transaction to the endpoint (see the table below). The Ping State bit is only managed by the host controller for queue heads that meet the following criteria: * Queue head is not an interrupt and * EPS field equals High-Speed and * PIDCode field equals OUT The following table illustrates the state transition table for the host controller's responsibility for maintaining the PING protocol. Refer to Chapter 8 in the USB Specification Revision 2.0 for detailed description on the Ping protocol. Table 31-42. Ping Control State Transition Table Event Current Host Device Next Do Ping PING Nak Do Ping Do Ping PING Ack Do OUT 1 Do Ping PING XactErr Do Ping Do Ping PING Stall N/C 2 Do OUT OUT Nak Do Ping Do OUT OUT Nyet Do Ping Do OUT OUT Ack Do OUT Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2223 Functional Description Table 31-42. Ping Control State Transition Table (continued) Do OUT OUT XactErr1 Do Ping Do OUT OUT Stall N/C 2 1. Transaction Error (XactErr) is any time the host misses the handshake. 2. No transition change required for the Ping State bit. The Stall handshake results in the endpoint being halted (for example Active set to zero and Halt set to one). Software intervention is required to restart queue. 3 A Nyet response to an OUT means that the device has accepted the data, but cannot receive any more at this time. Host must advance the transfer state and additionally, transition the Ping State bit to Do Ping. The Ping State bit has the following encoding: Table 31-43. Ping State bit Encoding Value Meaning 0B Do OUT The host controller uses an OUT PID during the next bus transaction to this endpoint. 1B Do Ping The host controller uses a PING PID during the next bus transaction to this endpoint. The defined ping protocol (see USB 2.0 Specification, Chapter 8) allows the host to be imprecise on the initialization of the ping protocol (that is start in Do OUT when we don't know whether there is space on the device or not). The host controller manages the Ping State bit. System software sets the initial value in the queue head when it initializes a queue head. The host controller preserves the Ping State bit across all queue advancements. This means that when a new qTD is written into the queue head overlay area, the previous value of the Ping State bit is preserved. 31.2.6.3.13 Split Transactions USB 2.0 defines extensions to the bus protocol for managing USB 1.x data streams through USB 2.0 Hubs. This section describes how the host controller uses the interface data structures to manage data streams with full- and low-speed devices, connected below USB 2.0 hub, utilizing the split transaction protocol. Refer to USB 2.0 Specification for the complete definition of the split transaction protocol. Full- and Low-speed devices are enumerated identically as high-speed devices, but the transactions to the Full- and Low-speed endpoints use the split-transaction protocol on the high-speed bus. The split transaction protocol is an encapsulation of (or wrapper around) the Full- or Low-speed transaction. The high-speed wrapper portion of the protocol is addressed to the USB 2.0 Hub and Transaction Translator below which the Full- or Low-speed device is attached. The EHCI interface uses dedicated data structures for managing full-speed isochronous data streams (see Split Transaction Isochronous Transfer Descriptor (siTD)). Control, Bulk and Interrupt are managed using the queuing data structures (see Queue Head). The interface data structures need to be programmed with the device address and the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2224 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Transaction Translator number of the USB 2.0 Hub operating as the Low-/Full-speed host controller for this link. The following sections describe the details of how the host controller must process and manage the split transaction protocol. 31.2.6.3.13.1 Split Transactions for Asynchronous Transfers A queue head in the asynchronous schedule with an EPS field indicating a full-or lowspeed device indicates to the host controller that it must use split transactions to stream data for this queue head. All full-speed bulk and full-, low-speed control are managed through queue heads in the asynchronous schedule. Software must initialize the queue head with the appropriate device address and port number for the transaction translator that is serving as the full/low-speed host controller for the links connecting the endpoint. Software must also initialize the split transaction state bit (SplitXState) to Do-Start-Split. Finally, if the endpoint is a control endpoint, then system software must set the Control Transfer Type (C) bit in the queue head to one. If this is not a control transfer type endpoint, the C bit must be initialized by software to be zero. This information is used by the host controller to properly set the Endpoint Type (ET) field in the split transaction bus token. When the C bit is zero, the split transaction token's ET field is set to indicate a bulk endpoint. When the C bit is one, the split transaction token's ET field is set to indicate a control endpoint. Refer to Chapter 8 of USB Specification Revision 2.0 for details. Endpoint Halt Endpoint Halt CERR goes to zero XactErr Endpoint Active Nyet Do Complete Split Do Start Split Decrement Error Count (CERR) Stall AcK NaK !XzctErr .and. !NYET .and. !Stall XactErr CERR goes to zero Decrement Error Count (CERR) and Do immediate retry of complete-split Nak .and. PidCode .eq. SETUP Set XactErr bit and Decrement Error Count (CERR) Figure 31-24. Host Controller Asynchronous Schedule Split-Transaction State Machine i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2225 Functional Description 31.2.6.3.13.1.1 Asynchronous - Do Start Split This is the state which software must initialize a full- or low-speed asynchronous queue head. This state is entered from the Do Complete Split state only after a complete-split transaction receives a valid response from the transaction translator that is not a Nyet handshake. For queue heads in this state, the host controller executes a start-split transaction to the appropriate transaction translator. If the bus transaction completes without an error and PidCode indicates an IN or OUT transaction, then the host controller reloads the error counter (CErr). If it is a successful bus transaction and the PidCode indicates a SETUP, the host controller does not reload the error counter. If the transaction translator responds with a Nak, the queue head is left in this state, and the host controller proceeds to the next queue head in the asynchronous schedule. If the host controller times out the transaction (no response, or bad response) the host controller decrements Cerr and proceeds to the next queue head in the asynchronous schedule. 31.2.6.3.13.1.2 Asynchronous - Do Complete Split This state is entered from the Do Start Split state only after a start-split transaction receives an Ack handshake from the transaction translator. For queue heads in this state, the host controller executes a complete-split transaction to the appropriate transaction translator. If the transaction translator responds with a Nyet handshake, the queue head is left in this state, the error counter is reset and the host controller proceeds to the next queue head in the asynchronous schedule. When a Nyet handshake is received for a bus transaction where the queue head's PidCode indicates an IN or OUT, the host controller reloads the error counter (CErr). When a Nyet handshake is received for a complete-split bus transaction where the queue head's PidCode indicates a SETUP, the host controller must not adjust the value of CErr. Independent of PIDCode, the following responses have the effects: * Transaction Error (XactErr). Timeout or data CRC failure, and so on. The error counter (Cerr) is decremented by one and the complete split transaction is immediately retried (if possible). If there is not enough time in the micro-frame to execute the retry, the host controller MUST ensure that the next time the host controller begins executing from the Asynchronous schedule, it must begin executing from this queue head. If another start-split (for some other endpoint) is sent to the transaction translator before the complete-split is really completed, the transaction translator could dump the results (which were never delivered to the host). This is why the core specification states the retries must be immediate. A method to accomplish this behavior is to not advance the asynchronous schedule. When the host i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2226 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller controller returns to the asynchronous schedule in the next micro-frame, the first transaction from the schedule is the retry for this endpoint. If Cerr went to zero, the host controller must halt the queue. * NAK. The target endpoint Nak'd the full- or low-speed transaction. The state of the transfer is not advanced and the state is exited. If the PidCode is a SETUP, then the Nak response is a protocol error. The XactErr status bit is set to one and the CErr field is decremented. * STALL. The target endpoint responded with a STALL handshake. The host controller sets the halt bit in the status byte, retires the qTD but does not attempt to advance the queue. If the PidCode indicates an IN, then any of following responses are expected: * DATA0/1. On reception of data, the host controller ensures the PID matches the expected data toggle and checks CRC. If the packet is good, the host controller advances the state of the transfer, for example move the data pointer by the number of bytes received, decrement BytesToTransfer field by the number of bytes received, and toggle the dt bit. The host controller then exit this state. The response and advancement of transfer may trigger other processing events, such as retirement of the qTD and advancement of the queue. If the data sequence PID does not match the expected, the data is ignored, the transfer state is not advanced and this state is exited. If the PidCode indicates an OUT/SETUP, then any of following responses are expected: * ACK. The target endpoint accepted the data, so the host controller must advance the state of the transfer. The Current Offset field is incremented by Maximum Packet Length or Bytes to Transfer, whichever is less. The field Bytes To Transfer is decremented by the same amount and the data toggle bit (dt) is toggled. The host controller then exit this state. * Advancing the transfer state may cause other processing events such as retirement of the qTD and advancement of the queue (see Managing Control/Bulk/Interrupt Transfers through Queue Heads). 31.2.6.3.13.2 Split Transaction Interrupt Split-transaction Interrupt-IN/OUT endpoints are managed through the same data structures used for high-speed interrupt endpoints. They both co-exist in the periodic schedule. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2227 Functional Description Queue heads/qTDs offer the set of features required for reliable data delivery, which is characteristic to interrupt transfer types. The split-transaction protocol is managed completely within this defined functional transfer framework. For example, for a highspeed endpoint, the host controller visits a queue head, execute a high-speed transaction (if criteria are met) and advance the transfer state (or not) depending on the results of the entire transaction. For low- and full-speed endpoints, the details of the execution phase are different (that is takes more than one bus transaction to complete), but the remainder of the operational framework is intact. This means that the transfer advancement, and so on, occurs as defined in Managing Control/Bulk/Interrupt Transfers through Queue Heads, but only occurs on the completion of a split transaction. 31.2.6.3.13.2.1 Split Transaction Scheduling Mechanisms for Interrupt Full- and low-speed Interrupt queue heads have an EPS field indicating full- or low-speed and have a non-zero S-mask field. The host controller can detect this combination of parameters and assume the endpoint is a periodic endpoint. Low- and full-speed interrupt queue heads require the use of the split transaction protocol. The host controller sets the Endpoint Type (ET) field in the split token to indicate the transaction is an interrupt. These transactions are managed through a transaction translator's periodic pipeline. Software should not set these fields to indicate the queue head is an interrupt unless the queue head is used in the periodic schedule. System software manages the per/transaction translator periodic pipeline by budgeting and scheduling exactly during which micro-frames the start-splits and complete-splits for each endpoint occurs. The characteristics of the transaction translator are such that the high-speed transaction protocol must execute during explicit micro-frames, or the data or response information in the pipeline is lost. The following figure illustrates the general scheduling boundary conditions that are supported by the EHCI periodic schedule and queue head data structure. The S and CX labels indicate micro-frames where software can schedule start-splits and complete splits (respectively). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2228 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Periodic Schedule Micro-frame 7 0 1 2 C0 S Case 1: Normal Case 3 4 C1 5 6 7 0 C2 C0 C1 C0 C1 C2 C1 C2 S Case 2a: End of Frame S Case 2b: End of Frame C0 S Case 2c: End of Frame HS/FS/LS Bus Micro-frame 6 B-Frame N-1 7 0 1 2 1 3 4 5 6 7 C2 0 B-Frame N B-Frame N+1 H-Frame N Figure 31-25. Split Transaction, Interrupt Scheduling Boundary Conditions The scheduling cases are: * Case 1: The normal scheduling case is where the entire split transaction is completely bounded by a frame (H-Frame in this case). * Case 2a through Case 2c: The USB 2.0 Hub pipeline rules states clearly, when and how many complete-splits must be scheduled to account for earliest to latest execution on the full/low-speed link. The complete-splits may span the H-Frame boundary when the start-split is in micro-frame 4 or later. When this occurs, the HFrame to B-Frame alignment requires that the queue head be reachable from consecutive periodic frame list locations. System software cannot build an efficient schedule that satisfies this requirement unless it uses FSTNs. The figure below illustrates the general layout of the periodic schedule. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2229 Functional Description Linkage repeats every 8 for remainder of frame list Level 8 Level 4 87 43 Level 2 86 21 Level 1 85 (root) 42 84 10 83 41 Periodic Frame List 82 20 81 40 80 80b Figure 31-26. General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading The periodic frame list is effectively the leaf level a binary tree, which is always traversed leaf to root. Each level in the tree corresponds to a 2N poll rate. Software can efficiently manage periodic bandwidth on the USB by spreading interrupt queue heads that have the same poll rate requirement across all the available paths from the frame list. For example, system software can schedule eight poll rate 8 queue heads and account for them once in the high-speed bus bandwidth allocation. When an endpoint is allocated an execution footprint that spans a frame boundary, the queue head for the endpoint must be reachable from consecutive locations in the frame list. An example would be if 80b where such an endpoint. Without additional support on the interface, to get 80b reachable at the correct time, software would have to link 81 to 80b. It would then have to move 41 and everything linked after into the same path as 40. This upsets the integrity of the binary tree and disallows the use of the spreading technique. FSTN data structures are used to preserve the integrity of the binary-tree structure and enable the use of the spreading technique. Host Controller Operational Model for FSTNs defines the hardware and software operational model requirements for using FSTNs. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2230 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller The following queue head fields are initialized by system software to instruct the host controller when to execute portions of the split-transaction protocol: * SplitXState. This is single bit residing in the Status field of a queue head (see Table 31-20). This bit is used to track the current state of the split transaction. * Frame S-mask. This is a bit-field where-in system software sets a bit corresponding to the micro-frame (within an H-Frame) that the host controller should execute a start-split transaction. This is always qualified by the value of the SplitXState bit in the Status field of the queue head. For example, referring to Figure 31-25, case one, the S-mask would have a value of 00000001b indicating that if the queue head is traversed by the host controller, and the SplitXState indicates Do_Start, and the current micro-frame as indicated by FRINDEX[2:0] is 0, then execute a start-split transaction. * Frame C-mask. This is a bit-field where system software sets one or more bits corresponding to the micro-frames (within an H-Frame) that the host controller should execute complete-split transactions. The interpretation of this field is always qualified by the value of the SplitXState bit in the Status field of the queue head. For example, referring to Figure 31-25, case one, the C-mask would have a value of 00011100b indicating that if the queue head is traversed by the host controller, and the SplitXState indicates Do_Complete, and the current micro-frame as indicated by FRINDEX[2:0] is 2, 3, or 4, then execute a complete-split transaction. It is software's responsibility to ensure that the translation between H-Frames and B-Frames is correctly performed when setting bits in S-mask and C-mask 31.2.6.3.13.2.2 Host Controller Operational Model for FSTNs The FSTN data structure is used to manage Low/Full-speed interrupt queue heads that need to be reached from consecutive frame list locations (that is boundary cases 2a through 2c). An FSTN is essentially a back pointer, similar in intent to the back pointer field in the siTD data structure (see siTD Back Link Pointer). This feature provides software a simple primitive to save a schedule position, redirect the host controller to traverse the necessary queue heads in the previous frame, then restore the original schedule position and complete normal traversal. The four components to the use of FSTNs: * FSTN data structure. * A Save Place indicator. This is always an FSTN with its Back Path Link Pointer.Tbit set to zero. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2231 Functional Description * A Restore indicator. This is always an FSTN with its Back Path Link Pointer.T-bit set to one. * Host controller FSTN traversal rules. When the host controller encounters an FSTN during micro-frames 2 through 7 it simply follows the node's Normal Path Link Pointer to access the next schedule data structure. NOTE The FSTN's Normal Path Link Pointer.T-bit may set to one, which the host controller must interpret as the end of periodic list mark. When the host controller encounters a Save-Place FSTN in micro-frames 0 or 1, it saves the value of the Normal Path Link Pointer and set an internal flag indicating that it is executing in Recovery Path mode. Recovery Path mode modifies the host controller's rules for how it traverses the schedule and limits which data structures is considered for execution of bus transactions. The host controller continues executing in Recovery Path mode until it encounters a Restore FSTN or it determines that it has reached the end of the micro-frame (see details in the list below). The rules for schedule traversal and limited execution while in Recovery Path mode are: * Always follow the Normal Path Link Pointer when it encounters an FSTN that is a Save-Place indicator. The host controller must not recursively follow Save-Place FSTNs. Therefore, while executing in Recovery Path mode, it must never follow an FSTN's Back Path Link Pointer. * Do not process an siTD or, iTD data structure. Simply follow its Next Link Pointer. * Do not process a QH (Queue Head) whose EPS field indicates a high-speed device. Simply follow its Horizontal Link Pointer. * When a QH's EPS field indicates a Full/Low-speed device, the host controller considers only it for execution if its SplitXState is DoComplete (note: this applies whether the PID Code indicates an IN or an OUT). See Execute Transaction and Tracking Split Transaction Progress for Interrupt Transfers for a complete list of additional conditions that must be met in general for the host controller to issue a bus transaction. * The host controller must not execute a Start-split transaction while executing in Recovery Path mode. See Periodic Isochronous - Do Complete Split for special handling when in Recovery Path mode. * Stop traversing the recovery path when it encounters an FSTN that is a Restore indicator. The host controller unconditionally uses the saved value of the Save-Place FSTN's Normal Path Link Pointer when returning to the normal path traversal. The i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2232 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller host controller must clear the context of executing a Recovery Path when it restores schedule traversal to the Save-Place FSTN's Normal Path Link Pointer. * If the host controller determines that there is not enough time left in the micro-frame to complete processing of the periodic schedule, it abandons traversal of the recovery path, and clears the context of executing a recovery path. The result is that at the start of the next consecutive micro-frame, the host controller starts traversal at the frame list. An example traversal of a periodic schedule that includes FSTNs is illustrated in the following figure. Frame Numbers N+5 87 N+ 4 86 N+3 85 Normal Traversal for Frame N + 1, micro-frames 0,1 N+1 43 21 42 84 Save-N 83,0 83,1 83,2 N-ptr N-ptr T-bit=1 B-ptrE B-ptr T-bit=0 Restore-N 41 20 N Normal Travesal for Frame N N-1 N-2 82,0 81 82,1 82,2 82,3 10 40 Causes 'Restore' to Normal path traversal Recovery Path Traversal 80 Figure 31-27. Example Host Controller Traversal of Recovery Path via FSTNs In frame N+1 (micro-frames 0 and 1), when the host controller encounters Save-Path FSTN (Save-N), it observes that Save-N.Back Path Link Pointer.T-bit is zero (definition of a Save-Path indicator). The host controller saves the value of Save-N.Normal Path Link Pointer and follows Save-N.Back Path Link Pointer. At the same time, it sets an internal flag indicating that it is now in Recovery Path mode (the recovery path is annotated in the figure above with a large dashed line). The host controller continues traversing data structures on the recovery path and executing only those bus transactions as noted above, on the recovery path until it reaches Restore FSTN (Restore-N). RestoreN.Back Path Link Pointer.T-bit is set to one (definition of a Restore indicator), so the host controller exits Recovery Path mode by clearing the internal Recovery Path mode flag and commences (restores) schedule traversal using the saved value of the Save-Place FSTN's Normal Path Link Pointer (for example Save-N.Normal Path Link Pointer). The nodes traversed during these micro-frames include: {83.0, 83.1, 83.2, Save-A, 82.2, 82.3, 42, i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2233 Functional Description 20, Restore-N, 43, 21, Restore-N, 10 ...}. The nodes on the recovery-path are in bold. In frame N (micro-frames 0-7), for this example, the host controller traverses all of the schedule data structures utilizing the Normal Path Link Pointers in any FSTNs it encounters. This is because the host controller has not yet encountered a Save-Place FSTN so it not executing in Recovery Path mode. When it encounters the Restore FSTN, (Restore-N), during micro-frames 0 and 1, it uses Restore-N.Normal Path Link Pointer to traverse to the next data structure (that is normal schedule traversal). This is because the host controller must use a Restore FSTN's Normal Path Link Pointer when not executing in a Recovery-Path mode. The nodes traversed during frame N include: {82.0, 82.1, 82.2, 82.3, 42, 20, Restore-N, 10 ...}. In frame N+1 (micro-frames 2-7), when the host controller encounters Save-Path FSTN Save-N, it unconditionally follows Save-N.Normal Path Link Pointer. The nodes traversed during these micro-frames include: {83.0, 83.1, 83.2, Save-A, 43, 21, Restore-N, 10 ...}. 31.2.6.3.13.2.3 Software Operational Model for FSTNs Software must create a consistent, coherent schedule for the host controller to traverse. When using FSTNs, system software must adhere to the following rules: * Each Save-Place indicator requires a matching Restore indicator. * The Save-Place indicator is an FSTN with a valid Back Path Link Pointer and Tbit equal to zero. * Back Path Link Pointer.Typ field must be set to indicate the referenced data structure is a queue head. The Restore indicator is an FSTN with its Back Path Link Pointer.T-bit set to one. * A Restore FSTN may be matched to one or more Save-Place FSTNs. For example, if the schedule includes a poll-rate 1 level, then system software only needs to place a Restore FSTN at the beginning of this list in order to match all possible Save-Place FSTNs. * If the schedule does not have elements linked at a poll-rate level of one, and one or more Save-Place FSTNs are used, then System Software must ensure the Restore FSTN's Normal Path Link Pointer's T-bit is set to one, as this is used to mark the end of the periodic list. * When the schedule does have elements linked at a poll rate level of one, a Restore FSTN must be the first data structure on the poll rate one list. All traversal paths from the frame list converge on the poll-rate one list. System software must ensure that Recovery Path mode is exited before the host controller is allowed to traverse the poll rate level one list. * A Save-Place FSTN's Back Path Link Pointer must reference a queue head data structure. The referenced queue head must be reachable from the previous frame list i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2234 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller location. In other words, if the Save-Place FSTN is reachable from frame list offset N, then the FSTN's Back Path Link Pointer must reference a queue head that is reachable from frame list offset N-1. Software should make the schedule as efficient as possible. What this means in this context is that software should have no more than one Save-Place FSTN reachable in any single frame. Note there is times when two (or more, depending on the implementation) could exist as full/low-speed footprints change with bandwidth adjustments. This could occur, for example when a bandwidth re-balance causes system software to move the Save-Place FSTN from one poll rate level to another. During the transition, software must preserve the integrity of the previous schedule until the new schedule is in place. 31.2.6.3.13.2.4 Tracking Split Transaction Progress for Interrupt Transfers To correctly maintain the data stream, the host controller must be able to detect and report errors where data is lost. For interrupt-IN transfers, data is lost when it makes it into the USB 2.0 hub, but the USB 2.0 host system is unable to get it from the USB 2.0 Hub and into the system before it expires from the transaction translator pipeline. When a lost data condition is detected, the queue must be halted, thus signaling system software to recover from the error. A data-loss condition exists whenever a start-split is issued, accepted and successfully executed by the USB 2.0 Hub, but the complete-splits get unrecoverable errors on the high-speed link, or the complete-splits do not occur at the correct times. One reason complete-splits might not occur at the right time would be due to host-induced system hold-offs that cause the host controller to miss bus transactions because it cannot get timely access to the schedule in system memory. The same condition can occur for an interrupt-OUT, but the result is not an endpoint halt condition, but rather effects only the progress of the transfer. The queue head has the following fields to track the progress of each split transaction. These fields are used to keep incremental state about which (and when) portions have been executed. * C-prog-mask. This is an eight-bit bit-vector where the host controller keeps track of which complete-splits have been executed. Due to the nature of the Transaction Translator periodic pipeline, the complete-splits need to be executed in-order. The host controller needs to detect when the complete-splits have not been executed in order. This can only occur due to system hold-offs where the host controller cannot get to the memory-based schedule. C-prog-mask is a simple bit-vector that the host controller sets one of the C-prog-mask bits for each complete-split executed. The bit position is determined by the micro-frame number in which the complete-split was executed. The host controller always checks C-prog-mask before executing a i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2235 Functional Description complete-split transaction. If the previous complete-splits have not been executed then it means one (or more) have been skipped and data has potentially been lost. * FrameTag. This field is used by the host controller during the complete-split portion of the split transaction to tag the queue head with the frame number (H-Frame number) when the next complete split must be executed. * S-bytes. This field can be used to store the number of data payload bytes sent during the start-split (if the transaction was an OUT). The S-bytes field must be used to accumulate the data payload bytes received during the complete-splits (for an IN). 31.2.6.3.13.2.5 Split Transaction Execution State Machine for Interrupt In the following presentation, all references to micro-frame are in the context of a microframe within an H-Frame. >As with asynchronous Full- and Low-speed endpoints, a split-transaction state machine is used to manage the split transaction sequence. Aside from the fields defined in the queue head for scheduling and tracking the split transaction, the host controller calculates one internal mechanism that is also used to manage the split transaction. The internal calculated mechanism is: * cMicroFrameBit. This is a single-bit encoding of the current micro-frame number. It is an eight-bit value calculated by the host controller at the beginning of every microframe. It is calculated from the three least significant bits of the FRINDEX register (that is, cMicroFrameBit = (1 shifted-left(FRINDEX[2:0])). The cMicroFrameBit has at most one bit asserted, which always corresponds to the current micro-frame number. For example, if the current micro-frame is 0, then cMicroFrameBit will equal 00000001b. The variable cMicroFrameBit is used to compare against the Smask and C-mask fields to determine whether the queue head is marked for a start- or complete-splt transaction for the current micro-frame. The following figure illustrates the state machine for managing a complete interrupt split transaction. There are two phases to each split transaction. The first is a single start-split transaction, which occurs when the SplitXState is at Do_Start and the single bit in cMicroFrameBit has a corresponding bit active in QH.S-mask. The transaction translator does not acknowledge the receipt of the periodic start-split, so the host controller unconditionally transitions the state to Do_Complete. Due to the available jitter in the transaction translator pipeline, there will be more than one complete-split transaction scheduled by software for the Do_Complete state. This translates simply to the fact that there are multiple bits set to a one in the QH.C-mask field. The host controller keeps the queue head in the Do_Complete state until the split transaction is complete (see definition below), or an error condition triggers the threestrikes-rule (for example, after the host tries the same transaction three times, and each i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2236 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller encounters an error, the host controller will stop retrying the bus transaction and halt the endpoint, thus requiring system software to detect the condition and perform systemdependent recovery). !(QH.S-Mask & MicroFrameBit) (QH.S-Mask & cMicroFrameBit) Do Start Split Active Queue State Halt Queue State QH.C-Mask & cMicroFrameBit .and. (FRINDEX[7:3] .eq. QH.FrameTag) .and. CheckPreviousBit(QH.C-prog-mask, QH.C-mask, cMicroFrameBit Split Transaction Complete Data Loss .or. STALL .or. Dabble .or. CERR -> . issue start-split transaction . tag QH w/frame number according to frame tag rules . QH.c-prog-mask = zero (00b) Do Complete Split . issue complete-split transaction . tag QH w/frame number according to the ** Sframe tag rules . QH.c.prog-mask != cMicroFrameBit MDATA or NYET XactErr Decrement Error Counter (CERR) and Do immediate retry of complete-split Figure 31-28. Split Transaction State Machine for Interrupt See Previous Section for the frame tag management rules. Periodic Interrupt - Do Start Split This is the state software must initialize a full- or low-speed interrupt queue head StartXState bit. This state is entered from the Do_Complete Split state only after the split transaction is complete. This occurs when one of the following events occur: The transaction translator responds to a complete-split transaction with one of the following: * NAK. A NAK response is a propagation of the full- or low-speed endpoint's NAK response. * ACK. An ACK response is a propagation of the full- or low-speed endpoint's ACK response. Only occurs on an OUT endpoint. * DATA 0/1. Only occurs for INs. Indicates that this is the last of the data from the endpoint for this split transaction. * ERR. The transaction on the low-/full-speed link below the transaction translator had a failure (for example, timeout, bad CRC, etc.). * NYET (and Last). The host controller issued the last complete-split and the transaction translator responded with a NYET handshake. This means that the startsplit was not correctly received by the transaction translator, so it never executed a transaction to the full- or low-speed endpoint, see Section Periodic Isochronous - Do Complete Split for the definition of 'Last'. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2237 Functional Description Each time the host controller visits a queue head in this state (once within the Execute Transaction state), it performs the following test to determine whether to execute a startsplit. * QH.S-mask is bit-wise anded with cMicroFrameBit. If the result is non-zero, then the host controller will issue a start-split transaction. If the PIDCode field indicates an IN transaction, the host controller must zero-out the QH.Sbytes field. After the split-transaction has been executed, the host controller sets up state in the queue head to track the progress of the complete-split phase of the split transaction. Specifically, it records the expected frame number into QH.FrameTag field (see Section ), set C-prog-mask to zero (00h), and exits this state. Note that the host controller must not adjust the value of CErr as a result of completion of a start-split transaction. Periodic Interrupt - Do Complete Split This state is entered unconditionally from the Do Start Split state after a start-split transaction is executed on the bus. Each time the host controller visits a queue head in this state (once within the Execute Transaction state), it checks to determine whether a complete-split transaction should be executed now. There are four tests to determine whether a complete-split transaction should be executed. * Test A. cMicroFrameBit is bit-wise anded with QH.C-mask field. A non-zero result indicates that software scheduled a complete-split for this endpoint, during this micro-frame. * Test B. QH.FrameTag is compared with the current contents of FRINDEX[7:3]. An equal indicates a match. * Test C. The complete-split progress bit vector is checked to determine whether the previous bit is set, indicating that the previous complete-split was appropriately executed. An example algorithm for this test is provided below: Algorithm Boolean CheckPreviousBit(QH.C-prog-mask, QH.C-mask, cMicroFrameBit) Begin -- Return values: -- TRUE - no error -- FALSE - error -Boolean rvalue = TRUE; previousBit = cMicroframeBit logical-rotate-right(1) -- Bit-wise anding previousBit with C-mask indicates -- whether there was an intent -- to send a complete split in the previous micro-frame. So, -- if the -- 'previous bit' is set in C-mask, check C-prog-mask to -- make sure it -- happened. If (previousBit bitAND QH.C-mask)then If not(previousBit bitAND QH.C-prog-mask) then rvalue = FALSE; End if End If -- If the C-prog-mask already has a one in this bit position, i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2238 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller -- then an aliasing -- error has occurred. It will probably get caught by the -- FrameTag Test, but -- at any rate it is an error condition that as detectable here -- should not allow -- a transaction to be executed. If (cMicroFrameBit bitAND QH.C-prog-mask) then rvalue = FALSE; End if return (rvalue) End Algorithm * Test D. Check to see if a start-split should be executed in this micro-frame. Note this is the same test performed in the Do Start Split state (see Section Periodic Isochronous - Do Start Split ). Whenever it evaluates to TRUE and the controller is NOT processing in the context of a Recovery Path mode, it means a start-split should occur in this micro-frame. Test D and Test A evaluating to TRUE at the same time is a system software error. Behavior is undefined. If (A .and. B .and. C .and. not(D)) then the host controller will execute a complete-split transaction. When the host controller commits to executing the complete-split transaction, it updates QH.C-prog-mask by bit-ORing with cMicroFrameBit. On completion of the complete-split transaction, the host controller records the result of the transaction in the queue head and sets QH.FrameTag to the expected H-Frame number (see Section ). The effect to the state of the queue head and thus the state of the transfer depends on the response by the transaction translator to the complete-split transaction. The following responses have the effects (note that any responses that result in decrementing of the CErr will result in the queue head being halted by the host controller if the result of the decrement is zero): * NYET (and Last). On each NYET response, the host controller checks to determine whether this is the last complete-split for this split transaction. Last is defined in this context as the condition where all of the scheduled complete-splits have been executed. If it is the last complete-split (with a NYET response), then the transfer state of the queue head is not advanced (never received any data) and this state exited. The transaction translator must have responded to all the clompete-splits with NYETs, meaning that the start-split issued by the host controller was not received. The start-split should be retried at the next poll period. * The test for whether this is the Last complete split can be performed by XOR QH.Cmask with QH.C-prog-mask. If the result is all zeros then all complete-splits have been executed. When this condition occurs, the XactErr status bit is set to a one and the CErr field is decremented. * NYET (and not Last). See above description for testing for Last. The complete-split transaction received a NYET response from the transaction translator. Do not update any transfer state (except for C-prog-mask and FrameTag) and stay in this state. The host controller must not adjust CErr on this response. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2239 Functional Description * Transaction Error (XactErr). Timeout, data CRC failure, etc. The CErr field is decremented and the XactErr bit in the Status field is set to a one. The complete split transaction is immediately retried (if Cerr is non-zero).If there is not enough time in the micro-frame to complete the retry and the endpoint is an IN, or CErr is decremented to a zero from a one, the queue is halted. If there is not enough time in the micro-frame to complete the retry and the endpoint is an OUT and CErr is not zero, then this state is exited (that is, return to Do Start Split). This results in a retry of the entire OUT split transaction, at the next poll period. Refer to Chapter 11 Hubs (specifically the section full- and low-speed Interrupts) in the USB Specification Revision 2.0 for detailed requirements on why these errors must be immediately retried. * ACK. This can only occur if the target endpoint is an OUT. The target endpoint ACK'd the data and this response is a propagation of the endpoint ACK up to the host controller. The host controller must advance the state of the transfer. The Current Offset field is incremented by Maximum Packet Length or Bytes to Transfer, whichever is less. The field Bytes To Transfer is decremented by the same amount. And the data toggle bit (dt) is toggled. The host controller will then exit this state for this queue head. The host controller must reload CErr with maximum value on this response. Advancing the transfer state may cause other process events such as retirement of the qTD and advancement of the queue (see Section Managing Control/ Bulk/Interrupt Transfers through Queue Heads). * MDATA. This response will only occur for an IN endpoint. The transaction translator responded with zero or more bytes of data and an MDATA PID. The incremental number of bytes received is accumulated in QH.S-bytes. The host controller must not adjust CErr on this response. * DATA0/1. This response may only occur for an IN endpoint. The number of bytes received is added to the accumulated byte count in QH.S-bytes. The state of the transfer is advanced by the result and the host controller will exit this state for this queue head. * Advancing the transfer state may cause other processing events such as retirement of the qTD and advancement of the queue (see Section Managing Control/Bulk/ Interrupt Transfers through Queue Heads). * If the data sequence PID does not match the expected, the entirety of the data received in this split transaction is ignored, the transfer state is not advanced and this state is exited. * NAK. The target endpoint Nak'd the full- or low-speed transaction. The state of the transfer is not advanced, and this state is exited. The host controller must reload CErr with maximum value on this response. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2240 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller * ERR. There was an error during the full- or low-speed transaction. The ERR status bit is set to a one, Cerr is decremented, the state of the transfer is not advanced, and this state is exited. * STALL. The queue is halted (an exit condition of the Execute Transaction state). The status field bits: Active bit is set to zero and the Halted bit is set to a one and the qTD is retired. Responses which are not enumerated in the list or which are received out of sequence are illegal and may result in undefined host controller behavior. The other possible combinations of tests A, B, C, and D may indicate that data or response was lost. The table below lists the possible combinations and the appropriate action. Table 31-44. Interrupt IN/OUT Do Complete Split State Execution Criteria Condition Action Description not(A) Ignore QHD Neither a start nor complete-split is scheduled for the current microframe.Host controller should continue walking the schedule. A If PIDCode = IN not(C) Halt QHD Progress bit check failed. These means a complete-split has been missed. There is the possibility of lost data. If PIDCode is an IN, then the Queue head must be halted. not(D) If PIDCode = OUT Retry start-split If PIDCode is an OUT, then the transfer state is not advanced and the state exited (for example, start-split is retried). This is a host-induced error and does not effect CERR. In either case, set the Missed Micro-frame bit in the status field to a one. A If PIDCode = IN not(B) Halt QHD C If PIDCode = OUT Retry start-split QH.FrameTag test failed. This means that exactly one or more H-Frames have been skipped. This means complete-splits and have missed. There is the possibility of lost data. If PIDCode is an IN, then the Queue head must be halted. If PIDCode is an OUT, then the transfer state is not advanced and the state exited (for example, start-split is retried). This is a host-induced error and does not effect CERR. In either case, set the Missed Micro-frame bit in the status field to a one. A Execute B complete-split This is the non-error case where the host controller executes a completesplit transaction. C not(D) D If PIDCode = IN Halt QHD If PIDCode = OUT Retry start-split This is a degenerate case where the start-split was issued, but all of the complete-splits were skipped and all possible intervening opportunities to detect the missed data failed to fire. If PIDCode is an IN, then the Queue head must be halted. If PIDCode is an OUT, then the transfer state is not advanced and the state exited (for example, start-split is retried). This is a host-induced error and does not effect CERR. In either case, set the Missed Micro-frame bit in the status field to a one. Note: When executing in the context of a Recovery Path mode, the host controller is allowed to process the queue head and take the actions indicated above, or it may wait until the queue head is visited in the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2241 Functional Description Table 31-44. Interrupt IN/OUT Do Complete Split State Execution Criteria normal processing mode. Regardless, the host controller must not execute a start-split in the context of a executing in a Recovery Path mode. Managing QH.FrameTag Field The QH.FrameTag field in a queue head is completely managed by the host controller. The rules for setting QH.FrameTag are simple: * Rule 1: If transitioning from Do Start Split to Do Complete Split and the current value of FRINDEX[2:0] is 6 QH.FrameTag is set to FRINDEX[7:3] + 1. This accommodates split transactions whose start-split and complete-splits are in different H-Frames (case 2a, see Figure 31-25). * Rule 2: If the current value of FRINDEX[2:0] is 7, QH.FrameTag is set to FRINDEX[7:3] + 1. This accommodates staying in Do Complete Split for cases 2a, 2b, and 2c (Figure 31-25). * Rule 3: If transitioning from Do_Start Split to Do Complete Split and the current value of FRINDEX[2:0] is not 6, or currently in Do Complete Split and the current value of (FRINDEX[2:0]) is not 7, FrameTag is set to FRINDEX[7:3]. This accommodates all other cases (Figure 31-25). 31.2.6.3.13.2.6 Rebalancing the periodic schedule System software must occasionally adjust a periodic queue head's S-mask and C-mask fields during operation. This need occurs when adjustments to the periodic schedule create a new bandwidth budget and one or more queue head's are assigned new execution footprints (that is, new S-mask and C-mask values). It is imperative that System software must not update these masks to new values in the midst of a split transaction. In order to avoid any race conditions with the update, the EHCI host controller provides a simple assist to system software. System software sets the Inactivate-on-next-Transaction (I) bit to a one to signal the host controller that it intends to update the S-mask and C-mask on this queue head. System software will then wait for the host controller to observe the I-bit is a one and transition the Active bit to a zero. The rules for how and when the host controller sets the Active bit to zero are enumerated below: * If the Active bit is a zero, no action is taken. The host controller does not attempt to advance the queue when the I-bit is a one. * If the Active bit is a one and the SplitXState is DoStart (regardless of the value of Smask), the host controller will simply set Active bit to a zero. The host controller is i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2242 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller not required to write the transfer state back to the current qTD. Note that if the Smask indicates that a start-split is scheduled for the current micro-frame, the host controller must not issue the start-split bus transaction. It must set the Active bit to zero. System software must save transfer state before setting the I-bit to a one. This is required so that it can correctly determine what transfer progress (if any) occurred after the I-bit was set to a one and the host controller executed its final bus-transaction and set Active to a zero. After system software has updated the S-mask and C-mask, it must then reactivate the queue head. Because the Active bit and the I-bit cannot be updated with the same write, system software needs to use the following algorithm to coherently re-activate a queue head that has been stopped via the I-bit. 1. Set the Halted bit to a one, then 2. Set the I-bit to a zero, then 3. Set the Active bit to a one and the Halted bit to a zero in the same write. Setting the Halted bit to a one inhibits the host controller from attempting to advance the queue between the time the I-bit goes to a zero and the Active bit goes to a one. 31.2.6.3.13.3 Split Transaction Isochronous Full-speed isochronous transfers are managed using the split-transaction protocol through a USB 2.0 transaction translator in a USB2.0 Hub. The EHCI controller utilizes siTD data structure to support the special requirements of isochronous split-transactions. This data structure uses the scheduling model of isochronous TDs (iTD, Section Isochronous (High-Speed) Transfer Descriptor (iTD)) (see Section Managing Isochronous Transfers Using iTDs for the operational model of iTDs) with the contiguous data feature provided by queue heads. This simple arrangement allows a single isochronous scheduling model and adds the additional feature that all data received from the endpoint (per split transaction) must land into a contiguous buffer. 31.2.6.3.13.3.1 Split Transaction Scheduling Mechanisms for Isochronous Full-speed isochronous transactions are managed through a transaction translator's periodic pipeline. As with full- and low-speed interrupt, system software manages each transaction translator's periodic pipeline by budgeting and scheduling exactly during which micro-frames the start-splits and complete-splits for each full-speed isochronous endpoint occur. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2243 Functional Description The requirements described in Section Split Transaction Scheduling Mechanisms for Interrupt apply. The following figure illustrates the general scheduling boundary conditions that are supported by the EHCI periodic schedule. The SX and CX labels indicate micro-frames where software can schedule start- and complete-splits (respectively). The H-Frame boundaries are marked with a large, solid bold vertical line. The B-Frame boundaries are marked with a large, bold, dashed line. The bottom of the figure illustrates the relationship of an siTD to the H-Frame. Periodic Schedule Micro-frame 7 0 1 S Case 1: Normal Case S0 S1 2 C0 3 C1 S2 S3 4 C2 Case 2a: Frame Wrap @ End of H-Frame IN S OUT Case 2b: Start and Complete in H-Frame, micro-frame 0 HS/FS/LS Bus Micro-frame B-Frame 5 C3 S C0 C1 6 7 C0 C1 S0 S1 S2 S3 C2 C3 C4 C5 0 C2 B-Frame N-1 7 C3 C6 C6 6 1 S 0 1 2 3 4 5 6 7 0 B-Frame N+1 B-Frame N H-Frame N+1 H-Frame N siTDx siTDx + 1 Figure 31-29. Split Transaction, Isochronous Scheduling Boundary Conditions When the endpoint is an isochronous OUT, there are only start-splits, and no completesplits. When the endpoint is an isochronous IN, there is at most one start-split and one to N complete-splits. The scheduling boundary cases are: * Case 1: The entire split transaction is completely bounded by an H-Frame. For example: the start-splits and complete-splits are all scheduled to occur in the same HFrame. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2244 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller * Case 2a: This boundary case is where one or more (at most two) complete-splits of a split transaction IN are scheduled across an H-Frame boundary. This can only occur when the split transaction has the possibility of moving data in B-Frame, microframes 6 or 7 (H-Frame micro-frame 7 or 0). When an H-Frame boundary wrap condition occurs, the scheduling of the split transaction spans more than one location in the periodic list.(For example, it takes two siTDs in adjacent periodic frame list locations to fully describe the scheduling for the split transaction.) * Although the scheduling of the split transaction may take two data structures, all of the complete-splits for each full-speed IN isochronous transaction must use only one data pointer. For this reason, siTDs contain a back pointer, the use of which is described below. * Software must never schedule full-speed isochronous OUTs across an H-Frame boundary. * Case 2b: This case can only occur for a very large isochronous IN. It is the only allowed scenario where a start-split and complete-split for the same endpoint can occur in the same micro-frame. Software must enforce this rule by scheduling the large transaction first. Large is defined to be anything larger than 579 byte maximum packet size. A subset of the same mechanisms employed by full- and low-speed interrupt queue heads are employed in siTDs to schedule and track the portions of isochronous split transactions. The following fields are initialized by system software to instruct the host controller when to execute portions of the split transaction protocol. * SplitXState. This is a single bit residing in the Status field of an siTD (see Figure 31-30). This bit is used to track the current state of the split transaction. The rules for managing this bit are described in Section Split Transaction Execution State Machine for Interrupt . * Frame S-mask. This is a bit-field where-in system software sets a bit corresponding to the micro-frame (within an H-Frame) that the host controller should execute a start-split transaction. This is always qualified by the value of the SplitXState bit. For example, referring to the IN example in Figure 31-29, case one, the S-mask would have a value of 00000001b indicating that if the siTD is traversed by the host controller, and the SplitXState indicates Do Start Split, and the current micro-frame as indicated by USB_n_FRINDEX[2:0] is 0, then execute a start-split transaction. * Frame C-mask. This is a bit-field where system software sets one or more bits corresponding to the micro-frames (within an H-Frame) that the host controller should execute complete-split transactions. The interpretation of this field is always qualified by the value of the SplitXState bit. For example, referring to the IN example in Figure 31-29, case one, the C-mask would have a value of 00111100b indicating that if the siTD is traversed by the host controller, and the SplitXState indicates Do i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2245 Functional Description Complete Split, and the current micro-frame as indicated by USB_n_FRINDEX[2:0] is 2, 3, 4, or 5, then execute a complete-split transaction. * Back Pointer. This field in a siTD is used to complete an IN split-transaction using the previous H-Frame's siTD. This is only used when the scheduling of the complete-splits span an H-Frame boundary. There exists a one-to-one relationship between a high-speed isochronous split transaction (including all start- and complete-splits) and one full-speed isochronous transaction. An siTD contains (amongst other things) buffer state and split transaction scheduling information. An siTD's buffer state always maps to one full-speed isochronous data payload. This means that for any full-speed transaction payload, a single siTD's data buffer must be used. This rule applies to both IN an OUTs. An siTD's scheduling information usually also maps to one high-speed isochronous split transaction. The exception to this rule is the H-Frame boundary wrap cases mentioned above. The siTD data structure describes at most, one frame's worth of high-speed transactions and that description is strictly bounded within a frame boundary. The figure below illustrates some examples. On the top are examples of the full-speed transaction footprints for the boundary scheduling cases described above. In the middle are timeframe references for both the B-Frames (HS/FS/LS Bus) and the H-Frames. On the bottom is illustrated the relationship between the scope of an siTD description and the time references. Each H-Frame corresponds to a single location in the periodic frame list. The implication is that each siTD is reachable from a single periodic frame list location at a time. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2246 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Case 1 3 4 5 6 7 0 Case 2a 1 B-Frame r-1 4 5 6 7 2 3 4 5 6 7 0 1 2 B-Frame r 0 1 H-Frame r-1 2 3 4 5 Full-Speed Transaction Case 2b 3 4 5 6 7 B-Frame r+1 6 7 0 H-Frame r 1 2 3 4 H-Frame r+1 siTDx 5 0 1 2 B-Frame r+2 6 0 7 1 2 3 H-Frame r+2 siTDx+1 Back Pointer Figure 31-30. siTD Scheduling Boundary Examples Each case is described below: * Case 1: One siTD is sufficient to describe and complete the isochronous split transaction because the whole isochronous split transaction is tightly contained within a single H-Frame. * Case 2a, 2b: Although both INs and OUTs can have these footprints, OUTs always take only one siTD to schedule. However, INs (for these boundary cases) require two siTDs to complete the scheduling of the isochronous split transaction siTDX is used to always issue the start-split and the first N complete-splits. The full-speed transaction (for these cases) can deliver data on the full-speed bus segment during micro-frame 7 of H-FrameY+1, or micro-frame 0 of H-FrameY+2. The complete splits are scheduled using siTDX+2 (not shown). The complete-splits to extract this data must use the buffer pointer from siTDX+1. The only way for the host controller to reach siTDX+1 from H-FrameY+2is to use siTDX+2's back pointer. The host controller rules for when to use the back pointer are described is Section Periodic Isochronous Do Complete Split . Software must apply the following rules when calculating the schedule and linking the schedule data structures into the periodic schedule: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2247 Functional Description * Software must ensure that an isochronous split-transaction is started so that it will complete before the end of the B-Frame. * Software must ensure that for a single full-speed isochronous endpoint, there is never a start-split and complete-split in H-Frame, micro-frame 1. This is mandated as a rule so that case 2a and case 2b can be discriminated. According to the core USB specification, the long isochronous transaction illustrated in Case 2b, could be scheduled so that the start-split was in micro-frame 1 of H-Frame N and the last complete-split would need to occur in micro-frame 1 of H-Frame N+1. However, it is impossible to discriminate between cases 2a and case 2b, which has significant impact on the complexity of the host controller. 31.2.6.3.13.3.2 Tracking Split Transaction Progress for Isochronous Transfers To correctly maintain the data stream, the host controller must be able to detect and report errors where device to host data is lost. Isochronous endpoints do not employ the concept of a halt on error, however the host is required to identify and report per-packet errors observed in the data stream. This includes schedule traversal problems (skipped micro-frames), timeouts and corrupted data received. In similar kind to interrupt split-transactions, the portions of the split transaction protocol must execute in the micro-frames they are scheduled. The queue head data structure used to manage full- and low-speed interrupt has several mechanisms for tracking when portions of a transaction have occurred. Isochronous transfers use siTDs, for their transfers, and the data structures are only reachable via the schedule in the exact microframe in which they are required (so all the mechanism employed for tracking in queue heads is not required for siTDs). Software has the option of reusing siTD several times in the complete periodic schedule. However, it must ensure that the results of split transaction N are consumed and the siTD reinitialized (activated) before the host controller gets back to the siTD (in a future micro-frame). Split-transaction isochronous OUTs utilize a low-level protocol to indicate which portions of the split transaction data have arrived. Control over the low-level protocol is exposed in an siTD via the fields Transaction Position (TP) and Transaction Count (Tcount). If the entire data payload for the OUT split transaction is larger than 188 bytes, there will be more than one start-split transaction, each of which require proper annotation. If host hold-offs occur, then the sequence of annotations received from the host will not be complete, which is detected and handled by the transaction translator. See Section Periodic Isochronous - Do Start Split for a description on how these fields are used during a sequence of start-split transactions. The fields siTD.T-Count and siTD.TP are used by the host controller to drive and sequence the transaction position annotations. It is the responsibility of system software to properly initialize these fields in each siTD. Once the budget for a split-transaction i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2248 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller isochronous endpoint is established, S-mask, T-Count, and TP initialization values for all the siTD associated with the endpoint are constant. They remain constant until the budget for the endpoint is recalculated by software and the periodic schedule adjusted. For IN-endpoints, the transaction translator simply annotates the response data packets with enough information to allow the host controller to identify the last data. As with split transaction Interrupt, it is the host controller's responsibility to detect when it has missed an opportunity to execute a complete-split. The following field in the siTD is used to track and detect errors in the execution of a split transaction for an IN isochronous endpoint. * C-prog-mask. This is an eight-bit bit-vector where the host controller keeps track of which complete-splits have been executed. Due to the nature of the Transaction Translator periodic pipeline, the complete-splits need to be executed in-order. The host controller needs to detect when the complete-splits have not been executed in order. This can only occur due to system hold-offs where the host controller cannot get to the memory-based schedule. C-prog-mask is a simple bit-vector that the host controller sets a bit for each complete-split executed. The bit position is determined by the micro-frame (USB_n_FRINDEX[2:0]) number in which the complete-split was executed. The host controller always checks C-prog-mask before executing a complete-split transaction. If the previous complete-splits have not been executed, then it means one (or more) have been skipped and data has potentially been lost. System software is required to initialize this field to zero before setting an siTD's Active bit to a one. If a transaction translator returns with the final data before all of the complete-splits have been executed, the state of the transfer is advanced so that the remaining complete-splits are not executed. Refer to Section Asynchronous - Do Complete Split for a description on how the state of the transfer is advanced. It is important to note that an IN siTD is retired based solely on the responses from the Transaction Translator to the complete-split transactions. This means, for example, that it is possible for a transaction translator to respond to a complete-split with an MDATA PID. The number of bytes in the MDATA's data payload could cause the siTD field Total Bytes to Transfer to decrement to zero. This response can occur, before all of the scheduled complete-splits have been executed. In other interface, data structures (for example, high-speed data streams through queue heads), the transition of Total Bytes to Transfer to zero signals the end of the transfer and results in setting of the Active bit to zero. However, in this case, the result has not been delivered by the Transaction Translator and the host must continue with the next complete-split transaction to extract the residual transaction state. This scenario occurs because of the pipeline rules for a Transaction Translator (see Chapter 11 of the Universal Serial Bus Revision 2.0). In summary the periodic pipeline rules require that on a micro-frame boundary, the Transaction Translator will hold the final two bytes received (if it has not seen an End Of Packet (EOP)) in the full-speed bus pipe stage and give the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2249 Functional Description remaining bytes to the high-speed pipeline stage. At the micro-frame boundary, the Transaction Translator could have received the entire packet (including both CRC bytes) but not received the packet EOP. In the next micro-frame, the Transaction Translator will respond with an MDATA and send all of the data bytes (with the two CRC bytes being held in the full-speed pipeline stage). This could cause the siTD to decrement its Total Bytes to Transfer field to zero, indicating it has received all expected data. The host must still execute one more (scheduled) complete-split transaction in order to extract the results of the full-speed transaction from the Transaction Translator (for example, the Transaction Translator may have detected a CRC failure, and this result must be forwarded to the host). If the host experiences hold-offs that cause the host controller to skip one or more (but not all) scheduled split transactions for an isochronous OUT, then the protocol to the transaction translator will not be consistent and the transaction translator will detect and react to the problem. Likewise, for host hold-offs that cause the host controller to skip one or more (but not all) scheduled split transactions for an isochronous IN, the C-progmask is used by the host controller to detect errors. However, if the host experiences a hold-off that causes it to skip all of an siTD, or an siTD expires during a host hold off (for example, a hold-off occurs and the siTD is no longer reachable by the host controller in order for it to report the hold-off event), then system software must detect that the siTDs have not been processed by the host controller (that is, state not advanced) and report the appropriate error to the client driver. 31.2.6.3.13.3.3 Split Transaction Execution State Machine for Isochronous In the following presentation, all references to micro-frame are in the context of a microframe within an H-Frame. If the Active bit in the Status byte is a zero, the host controller will ignore the siTD and continue traversing the periodic schedule. Otherwise the host controller will process the siTD as specified below. A split transaction state machine is used to manage the splittransaction protocol sequence. The host controller uses the fields defined in Section Tracking Split Transaction Progress for Interrupt Transfers , plus the variable cMicroFrameBit defined in Section Split Transaction Execution State Machine for Interrupt to track the progress of an isochronous split transaction. The figure below illustrates the state machine for managing an siTD through an isochronous split transaction. Bold, dotted circles denote the state of the Active bit in the Status field of a siTD. The Bold, dotted arcs denote the transitions between these states. Solid circles denote the states of the split transaction state machine and the solid arcs denote the transitions between these states. Dotted arcs and boxes reference actions that take place either as a result of a transition or from being in a state. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2250 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Active = 1b Not Active siTD.S-mask & cMicroFrameBit .and. direction .eq. OUT Active = 0b Do Start Split Active = 0b case 2(a,b) siTD x-1 complete IN Split Transaction Complete MDATA Advance data buffer state issue start-split transaction siTD.S-mask & cMicroFrameBit .and. direction .eq. IN Active Do Complete Split NYET .and. Not Last issue complete-split transaction siTD.C-mask & cMicroFrameBit .and. checkpreviousBit(C-prog-mask, C-mask, cMicroFrameBit) Figure 31-31. Split Transaction State Machine for Isochronous 31.2.6.3.13.3.4 Periodic Isochronous - Do Start Split Isochronous split transaction OUTs use only this state. An siTD for a split-transaction isochronous IN is either initialized to this state, or the siTD transitions to this state from Do Complete Split when a case 2a (IN) or 2b scheduling boundary isochronous split-transaction completes. Each time the host controller reaches an active siTD in this state, it checks the siTD.Smask against cMicroFrameBit. If there is a one in the appropriate position, the siTD will execute a start-split transaction. By definition, the host controller cannot reach an siTD at the wrong time. If the I/O field indicates an IN, then the start-split transaction includes only the extended token plus the full-speed token. Software must initialize the siTD.Total Bytes To Transfer field to the number of bytes expected. This is usually the maximum packet size for the full-speed endpoint. The host controller exits this state when the startsplit transaction is complete. The remainder of this section is specific to an isochronous OUT endpoint (that is, the I/O field indicates an OUT). When the host controller executes a start-split transaction for an isochronous OUT it includes a data payload in the start-split transaction. The memory i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2251 Functional Description buffer address for the data payload is constructed by concatenating siTD.Current Offset with the page pointer indicated by the page selector field (siTD.P). A zero in this field selects Page 0 and a 1 selects Page 1. During the start-split for an OUT, if the data transfer crosses a page boundary during the transaction, the host controller must detect the page cross, update the siTD.P-bit from a zero to a one, and begin using the siTD.Page 1 with siTD.Current Offset as the memory address pointer. The field siTD.TP is used to annotate each start-split transaction with the indication of which part of the splittransaction data the current payload represents (ALL, BEGIN, MID, END). In all cases the host controller simply uses the value in siTD.TP to mark the start-split with the correct transaction position code. T-Count is always initialized to the number of start-splits for the current frame. TP is always initialized to the first required transaction position identifier. The scheduling boundary case (see Figure 31-30) is used to determine the initial value of TP. The initial cases are summarized in the following table. Table 31-45. Initial Conditions for OUT siTD's TP and T-count Fields Case T-count TP Description 1, 2a =1 ALL When the OUT data payload is less than (or equal to) 188 bytes, only one startsplit is required to move the data. The one start-split must be marked with an ALL. 1, 2a !=1 BEGIN When the OUT data payload is greater than 188 bytes more than one start-split must be used to move the data. The initial start-split must be marked with a BEGIN. After each start-split transaction is complete, the host controller updates T-Count and TP appropriately so that the next start-split is correctly annotated. The table below illustrates all of the TP and T-count transitions, which must be accomplished by the host controller. . Table 31-46. Transaction Position (TP)/Transaction Count (T-Count) Transition Table TP T-count next TP next Description ALL 0 N/A Transition from ALL, to done. BEGIN 1 END Transition from BEGIN to END. Occurs when T-count starts at 2. BEGIN !=1 MID Transition from BEGIN to MID. Occurs when T-count starts at greater than 2. MID !=1 MID TP stays at MID while T-count is not equal to 1 (that is, greater than 1). This case can occur for any of the scheduling boundary cases where the T-count starts greater than 3. MID 1 END Transition from MID to END. This case can occur for any of the scheduling boundary cases where the T-count starts greater than 2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2252 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller The start-split transactions do not receive a handshake from the transaction translator, so the host controller always advances the transfer state in the siTD after the bus transaction is complete. To advance the transfer state the following operations take place: * The siTD.Total Bytes To Transfer and the siTD.Current Offset fields are adjusted to reflect the number of bytes transferred. * The siTD.P (page selector) bit is updated appropriately. * The siTD.TP and siTD.T-count fields are updated appropriately as defined in Table 31-46. These fields are then written back to the memory based siTD. The S-mask is fixed for the life of the current budget. As mentioned above, TP and T-count are set specifically in each siTD to reflect the data to be sent from this siTD. Therefore, regardless of the value of S-mask, the actual number of start-split transactions depends on T-count (or equivalently, Total Bytes to Transfer). The host controller must set the Active bit to a zero when it detects that all of the schedule data has been sent to the bus. The preferred method is to detect when T-Count decrements to zero as a result of a start-split bus transaction. Equivalently, the host controller can detect when Total Bytes to Transfer decrements to zero. Either implementation must ensure that if the initial condition is Total Bytes to Transfer equal to zero and T-count is equal to a one, then the host controller will issue a single start-split, with a zero-length data payload. Software must ensure that TP, T-count and Total Bytes to Transfer are set to deliver the appropriate number of bus transactions from each siTD. An inconsistent combination will yield undefined behavior. If the host experiences hold-offs that cause the host controller to skip start-split transactions for an OUT transfer, the state of the transfer will not progress appropriately. The transaction translator will observe protocol violations in the arrival of the start-splits for the OUT endpoint (that is, the transaction position annotation will be incorrect as received by the transaction translator). Example scenarios are described in Section Split Transaction for Isochronous Processing Examples . A host controller implementation can optionally track the progress of an OUT split transaction by setting appropriate bits in the siTD.C-prog-mask as it executes each scheduled start-split. The checkPreviousBit() algorithm defined in Periodic Isochronous Do Complete Split can be used prior to executing each start-split to determine whether start-splits were skipped. The host controller can use this mechanism to detect missed micro-frames. It can then set the siTD's Active bit to zero and stop execution of this siTD. This saves on both memory and high-speed bus bandwidth. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2253 Functional Description 31.2.6.3.13.3.5 Periodic Isochronous - Do Complete Split This state is only used by a split-transaction isochronous IN endpoint. This state is entered unconditionally from the Do Start State after a start-split transaction is executed for an IN endpoint. Each time the host controller visits an siTD in this state, it conducts a number of tests to determine whether it should execute a complete-split transaction. The individual tests are listed below. The sequence they are applied depends on which micro-frame the host controller is currently executing which means that the tests might not be applied until after the siTD referenced from the back pointer has been fetched. * Test A. cMicroFrameBit is bit-wise anded with siTD.C-mask field. A non-zero result indicates that software scheduled a complete-split for this endpoint, during this micro-frame. This test is always applied to a newly fetched siTD that is in this state. * Test B. The siTD.C-prog-mask bit vector is checked to determine whether the previous complete splits have been executed. An example algorithm is below (this is slightly different than the algorithm used in Section Periodic Isochronous - Do Complete Split ). The sequence in which this test is applied depends on the current value of USB_n_FRINDEX[2:0]. If USB_n_FRINDEX[2:0] is 0 or 1, it is not applied until the back pointer has been used. Otherwise it is applied immediately. Algorithm Boolean CheckPreviousBit(siTD.C-prog-mask, siTD.C-mask, cMicroFrameBit) Begin Boolean rvalue = TRUE; previousBit = cMicroFrameBit rotate-right(1) -- Bit-wise anding previousBit with C-mask indicates whether there was an intent -- to send a complete split in the previous micro-frame. So, if the -- 'previous bit' is set in C-mask, check C-prog-mask to make sure it -- happened. if previousBit bitAND siTD.C-mask then if not (previousBit bitAND siTD.C-prog-mask) then rvalue = FALSE End if End if Return rvalue End Algorithm If Test A is true and USB_n_FRINDEX[2:0] is zero or one, then this is a case 2a or 2b scheduling boundary (see Figure 31-29). See Section Periodic Isochronous - Do Complete Split for details in handling this condition. If Test A and Test B evaluate to true, then the host controller will execute a completesplit transaction using the transfer state of the current siTD. When the host controller commits to executing the complete-split transaction, it updates QH.C-prog-mask by bitORing with cMicroFrameBit. The transfer state is advanced based on the completion status of the complete-split transaction. To advance the transfer state of an IN siTD, the host controller must: * Decrement the number of bytes received from siTD.Total Bytes To Transfer, * Adjust siTD.Current Offset by the number of bytes received, i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2254 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller * Adjust siTD.P (page selector) field if the transfer caused the host controller to use the next page pointer, and * Set any appropriate bits in the siTD.Status field, depending on the results of the transaction. Note that if the host controller encounters a condition where siTD.Total Bytes To Transfer is zero, and it receives more data, the host controller must not write the additional data to memory. The siTD.Status.Active bit must be set to zero and the siTD.Status.Babble Detected bit must be set to a one. The fields siTD.Total Bytes To Transfer, siTD.Current Offset, and siTD.P (page selector) are not required to be updated as a result of this transaction attempt. The host controller must accept (assuming good data packet CRC and sufficient room in the buffer as indicated by the value of siTD.Total Bytes To Transfer) MDATA and DATA0/1 data payloads up to and including 192 bytes. A host controller implementation may optionally set siTD.Status Active to a zero and siTD.Status.Babble Detected to a one when it receives and MDATA or DATA0/1 with a data payload of more than 192 bytes. The following responses have the noted effects: * ERR. The full-speed transaction completed with a time-out or bad CRC and this is a reflection of that error to the host. The host controller sets the ERR bit in the siTD.Status field and sets the Active bit to a zero. * Transaction Error (XactErr). The complete-split transaction encounters a Timeout, CRC16 failure, etc. The siTD.Status field XactErr field is set to a one and the complete-split transaction must be retried immediately. The host controller must use an internal error counter to count the number of retries as a counter field is not provided in the siTD data structure. The host controller will not retry more than two times. If the host controller exhausts the retries or the end of the micro-frame occurs, the Active bit is set to zero. * DATAx (0 or 1). This response signals that the final data for the split transaction has arrived. The transfer state of the siTD is advanced and the Active bit is set to a zero. If the Bytes To Transfer field has not decremented to zero (including the reception of the data payload in the DATAx response), then less data than was expected, or allowed for was actually received. This short packet event does not set the USBINT status bit in the USBSTS register to a one. The host controller will not detect this condition. * NYET (and Last). On each NYET response, the host controller also checks to determine whether this is the last complete-split for this split transaction. Last was defined in Section Periodic Isochronous - Do Complete Split . If it is the last complete-split (with a NYET response), then the transfer state of the siTD is not advanced (never received any data) and the Active bit is set to a zero. No bits are set in the Status field because this is essentially a skipped transaction. The transaction translator must have responded to all the scheduled clompete-splits with NYETs, i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2255 Functional Description meaning that the start-split issued by the host controller was not received. This result should be interpreted by system software as if the transaction was completely skipped. The test for whether this is the last complete split can be performed by XORing C-mask with C-prog-mask. A zero result indicates that all complete-splits have been executed. * MDATA (and Last). See above description for testing for Last. This can only occur when there is an error condition. Either there has been a babble condition on the fullspeed link, which delayed the completion of the full-speed transaction, or software set up the S-mask and/or C-masks incorrectly. The host controller must set XactErr bit to a one and the Active bit is set to a zero. * NYET (and not Last). See above description for testing for Last. The complete-split transaction received a NYET response from the transaction translator. Do not update any transfer state (except for C-prog-mask) and stay in this state. * MDATA (and not Last). The transaction translator responds with an MDATA when it has partial data for the split transaction. For example, the full-speed transaction data payload spans from micro-frame X to X+1 and during micro-frame X, the transaction translator will respond with an MDATA and the data accumulated up to the end of micro-frame X. The host controller advances the transfer state to reflect the number of bytes received. If Test A succeeds, but Test B fails, it means that one or more of the complete-splits have been skipped. The host controller sets the Missed Micro-Frame status bit and sets the Active bit to a zero. 31.2.6.3.13.3.6 Complete-Split for Scheduling Boundary Cases 2a, 2b Boundary cases 2a and 2b (INs only) (see Figure 31-29) require that the host controller use the transaction state context of the previous siTD to finish the split transaction. The table below enumerates the transaction state fields. Table 31-47. Summary siTD Split Transaction State Buffer State Status Execution Progress Total Bytes To Transfer All bits in the status field C-prog-mask P (page select) Current Offset TP (transaction position) T-count (transaction count) NOTE TP and T-count are used only for Host to Device (OUT) endpoints. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2256 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller If software has budgeted the schedule of this data stream with a frame wrap case, then it must initialize the siTD.Back Pointer field to reference a valid siTD and will have the siTD.Back Pointer.T-bit in the siTD.Back Pointer field set to a zero. Otherwise, software must set the siTD.Back Pointer.T-bit in the siTD.Back Pointer field to a one. The host controller's rules for interpreting when to use the siTD.Back Pointer field are listed below. These rules apply only when the siTD's Active bit is a one and the SplitXState is Do Complete Split. * When cMicroFrameBit is a 1h and the siTDX.Back Pointer.T-bit is a zero, or * If cMicroFrameBit is a 2h and siTDX.S-mask[0] is a zero When either of these conditions apply, then the host controller must use the transaction state from siTDX-1. In order to access siTDX-1, the host controller reads on-chip the siTD referenced from siTDX.Back Pointer. The host controller must save the entire state from siTDX while processing siTDX-1. This is to accommodate for case 2b processing. The host controller must not recursively walk the list of siTD.Back Pointers. If siTDX-1 is active (Active bit is a one and SplitXStat is Do Complete Split), then both Test A and Test B are applied as described above. If these criteria to execute a completesplit are met, the host controller executes the complete split and evaluates the results as described above. The transaction state (see Table 31-47) of siTDX-1 is appropriately advanced based on the results and written back to memory. If the resultant state of siTDX-1's Active bit is a one, then the host controller returns to the context of siTDX, and follows its next pointer to the next schedule item. No updates to siTDX are necessary. If siTDX-1 is active (Active bit is a one and SplitXStat is Do Start Split), then the host controller must set Active bit to a zero and Missed Micro-Frame status bit to a one and the resultant status written back to memory. If siTDX-1'sActive bit is a zero, (because it was zero when the host controller first visited siTDX-1 via siTDX's back pointer, it transitioned to zero as a result of a detected error, or the results of siTDX-1's complete-split transaction transitioned it to zero), then the host controller returns to the context of siTDX and transitions its SplitXState to Do Start Split. The host controller then determines whether the case 2b start split boundary condition exists (that is, if cMicroframeBit is a 1b and siTDX.S-mask[0] is a 1b). If this criterion is met the host controller immediately executes a start-split transaction and appropriately advances the transaction state of siTDX, then follows siTDX.Next Pointer to the next schedule item. If the criterion is not met, the host controller simply follows siTDX.Next Pointer to the next schedule item. Note that in the case of a 2b boundary case, the splittransaction of siTDX-1 will have its Active bit set to zero when the host controller returns i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2257 Functional Description to the context of siTDX. Also, note that software should not initialize an siTD with Cmask bits 0 and 1 set to a one and an S-mask with bit zero set to a one. This scheduling combination is not supported and the behavior of the host controller is undefined. 31.2.6.3.13.3.7 Split Transaction for Isochronous - Processing Examples There is an important difference between how the hardware/software manages the isochronous split transaction state machine and how it manages the asynchronous and interrupt split transaction state machines. The asynchronous and interrupt split transaction state machines are encapsulated within a single queue head. The progress of the data stream depends on the progress of each split transaction. In some respects, the split-transaction state machine is sequenced via the Execute Transaction queue head traversal state machine (see Figure 31-22). Isochronous is a pure time-oriented transaction/data stream. The interface data structures are optimized to efficiently describe transactions that need to occur at specific times. The isochronous split-transaction state machine must be managed across these time-oriented data structures. This means that system software must correctly describe the scheduling of split-transactions across more than one data structure. Then the host controller must make the appropriate state transitions at the appropriate times, in the correct data structures. For example, the table below illustrates a couple of frames worth of scheduling required to schedule a case 2a full-speed isochronous data stream. Table 31-48. Example Case 2a - Software Scheduling siTDs for an IN Endpoint siTDX Micro-Frames Initial # Masks 0 1 2 3 4 5 6 7 SplitXState X S-Mask - - - - 1 - - - Do Start Split C-Mask 1 1 - - - - 1 1 S-Mask - - - - 1 - - - C-Mask 1 1 1 1 S-Mask - - - - C-Mask 1 1 1 1 S-Mask Repeats previous pattern X+1 X+2 X+3 - - 1 - Do Complete Split Do Complete Split Do Complete Split C-Mask i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2258 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller This example shows the first three siTDs for the transaction stream. Because this is the case-2a frame-wrap case, S-masks of all siTDs for this endpoint have a value of 10h (a one bit in micro-frame 4) and C-mask value of C3h (one-bits in micro-frames 0,1, 6 and 7). Additionally, sofware ensures that the Back Pointer field of each siTD references the appropriate siTD data structure (and the Back PointerT-bits are set to zero). The initial SplitXState of the first siTD is Do Start Split. The host controller will visit the first siTD eight times during frame X. The C-mask bits in micro-frames 0 and 1 are ignored because the state is Do Start Split. During micro-frame 4, the host controller determines that it can run a start-split (and does) and changes SplitXState to Do Complete Split. During micro-frames 6 and 7, the host controller executes complete-splits. Notice the siTD for frame X+1 has its SplitXState initialized to Do Complete Split. As the host controller continues to traverse the schedule during H-Frame X+1, it will visit the second siTD eight times. During micro-frames 0 and 1 it will detect that it must execute complete-splits. During H-Frame X+1, micro-frame 0, the host controller detects that siTDX+1's Back Pointer.T-bit is a zero, saves the state of siTDX+1 and fetches siTDX. It executes the complete split transaction using the transaction state of siTDX. If the siTDX split transaction is complete, siTD's Active bit is set to zero and results written back to siTDX. The host controller retains the fact that siTDX is retired and transitions the SplitXState in the siTDX+1 to Do Start Split. At this point, the host controller is prepared to execute the start-split for siTDX+1 when it reaches micro-frame 4. If the split-transaction completes early (transaction-complete is defined in Section Periodic Isochronous - Do Complete Split ), that is, before all the scheduled complete-splits have been executed, the host controller will transition siTDX.SplitXState to Do Start Split early and naturally skip the remaining scheduled complete-split transactions. For this example, siTDX+1 does not receive a DATA0 response until H-Frame X+2, micro-frame 1. During H-Frame X+2, micro-frame 0, the host controller detects that siTDX+2's Back Pointer.T-bit is a zero, saves the state of siTDX+2 and fetches siTDX+1. As described above, it executes another split transaction, receives an MDATA response, updates the transfer state, but does not modify the Active bit. The host controller returns to the context of siTDX+2, and traverses its next pointer without any state change updates to siTDX+2. S During H-Frame X+2, micro-frame 1, the host controller detects siTDX+2's S-mask[0] is a zero, saves the state of siTDX+2 and fetches siTDX+1. It executes another complete-split transaction, receives a DATA0 response, updates the transfer state and sets the Active bit to a zero. It returns to the state of siTDX+2 and changes its SplitXState to Do Start Split. At this point, the host controller is prepared to execute start-splits for siTDX+2 when it i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2259 Functional Description reaches micro-frame 4. 0 and HubAddr is the address of the Hub where the bus transitions from HS to FS/LS (ie. Split target hub)] FS and LS device can be either downstream from a HS hub with HubAddr = X [HubAddr > 0] or directly attached [where HubAddr = 0 and HubAddr is the address of the Root Hub where the bus transitions from HS to FS/LS (ie. Split target hub is the root hub) ] 31.2.6.4.1.4 Data Structures The same data structures used for FS/LS transactions though a HS hub are also used for transactions through the Root Hub with sm embedded Transaction Translator. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2269 Functional Description Here it is demonstrated how the Hub Address and Endpoint Speed fields should be set for directly attached FS/LS devices and hubs: 1. QH (for direct attach FS/LS) - Async. (Bulk/Control Endpoints) Periodic (Interrupt) * Hub Address = 0 * Transactions to direct attached device/hub. * QH.EPS = Port Speed * Transactions to a device downstream from direct attached FS hub. * QH.EPS = Downstream Device Speed NOTE When QH.EPS = 01 (LS) and PORTSCx.PSPD = 00 (FS), a LS-pre-pid will be sent before the transmitting LS traffic. Maximum Packet Size must be less than or equal 64 or undefined behaviour may result. 2. siTD (for direct attach FS) - Periodic (ISO Endpoint) * All FS ISO transactions: * Hub Address = 0 * siTD.EPS = 00 (full speed) * Maximum Packet Size must less than or equal to 1023 or undefined behaviour may result. 31.2.6.4.1.5 Operational Model The operational models are well defined for the behavior of the Transaction Translator (see USB 2.0 specificationUniversal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips. http://www.usb.org) and for the EHCI controller moving packets between system memory and a USB-HS hub. Because the embedded Transaction Translator exists within the host controller there is no physical bus between EHCI host controller driver and the USB FS/LS bus. These sections will briefly discuss the operational model for how the EHCI and Transaction Translator operational models are combined without the physical bus between. The following sections assume the reader is familiar with both the EHCI and USB 2.0 Transaction Translator operational models. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2270 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.4.1.5.1 Micro- frame Pipeline The EHCI operational model uses the concept of H-frames and B-frames to describe the pipeline between the Host (H) and the Bus (B). The embedded Transaction Translator shall use the same pipeline algorithms specified in the USB 2.0 specification for a Hubbased Transaction Translator. All periodic transfers always begin at B-frame 0 (after SOF) and continue until the stored periodic transfers are complete. As an example of the micro-frame pipeline implemented in the embedded Transaction Translator, all periodic transfers that are tagged in EHCI to execute in H-frame 0 will be ready to execute on the bus in B-frame 0. It is important to note that when programming the S-mask and C-masks in the EHCI data structures to schedule periodic transfers for the embedded Transaction Translator, the EHCI host controller driver must follow the same rules specified in EHCI for programming the S-mask and C-mask for downstream Hub-based Transaction Translators. Once periodic transfers are exhausted, any stored asynchronous transfer will be moved. Asynchronous transfers are opportunistic in that they shall execute whenever possible and their operation is not tied to H-frame and B-frame boundaries with the exception that an asynchronous transfer can not babble through the SOF (start of B-frame 0.) 31.2.6.4.1.5.2 Split State Machines The start and complete split operational model differs from EHCI slightly because there is no bus medium between the EHCI controller and the embedded Transaction Translator. Where a start or complete-split operation would occur by requesting the split to the HS hub, the start/complete split operation is simple an internal operation to the embedded Transaction Translator. The following table summarizes the conditions where handshakes are emulated from internal state instead of actual handshakes to HS split bus traffic. Table 31-52. Summary of the Conditons of Handshakes1 Condition Emulate TT Response Start-Split: All asynchronous buffers full. NAK Start-Split: All periodic buffers full. ERR Start-Split: Success for start of Async. Transaction. ACK Start-Split: Start Periodic Transaction. No Handshake (Ok) Complete-Split: Failed to find transaction in queue. Bus Time Out Complete-Split: Transaction in Queue is Busy. NYET Complete-Split: Transaction in Queue is Complete. [Actual Handshake from LS/FS device] i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2271 Functional Description 1. The un-shaded cells represent Start-Splits and the shaded cells represent Complete-Splits 31.2.6.4.1.5.3 Asynchronous Transaction Scheduling and Buffer Management The following USB 2.0 specification items are implemented in the embedded Transaction Translator: 31.2.6.4.1.5.4 USB 2.0 - 11.17.3 31.2.6.4.1.5.5 USB 2.0 - 11.17.4 31.2.6.4.1.5.6 Periodic Transaction Scheduling and Buffer Management * Sequencing is provided & a packet length estimator ensures no full-speed/low-speed packet babbles into SOF time. * Transaction tracking for 2 data pipes. The following USB 2.0 specification items are implemented in the embedded Transaction Translator: 31.2.6.4.1.5.7 USB 2.0 - 11.18.6.[1-2] 31.2.6.4.1.5.8 USB 2.0 - 11.18.[7-8] * Abort of pending start-splits * EOF (and not started in micro-frames 6) * Idle for more than 4 micro-frames * Abort of pending complete-splits * EOF * Idle for more than 4 micro-frames * Transaction tracking for up to 16 data pipes. * Complete-split transaction searching. NOTE There is no data schedule mechanism for these transactions other than the micro-frame pipeline. The embedded TT assumes the number of packets scheduled in a frame does not exceed the frame duration (1 ms) or else undefined behavior may result. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2272 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.4.1.5.9 Multiple Transaction Translators The maximum number of embedded Transaction Translators that is currently supported is one as indicated by the N_TT field in the Host Control Structural Parameters (EHCICompliant with Extensions) Register (HW_USBCTRL_HCSPARAMS) register. 31.2.6.4.2 Device Operation The co-existence of a device operational controller within the host controller has little effect on EHCI compatibility for host operation except as noted in this section. 31.2.6.4.3 USB_USBMODE Register Given that the dual-role controller is initialized in neither host nor device mode, the _USBMODE register must be programmed for host operation before the EHCI host controller driver can begin EHCI host operations. 31.2.6.4.3.1 Non-Zero Fields the Register File Some of the reserved fields and reserved addresses in the capability registers and operational register have use in device mode, the following must be adhered to: * Write operations to all EHCI reserved fields (some of which are device fields) with the operation registers should always be written to zero. This is an EHCI requirement of the device controller driver that must be adhered to. * Read operations by the host controller must properly mask EHCI reserved fields (some of which are device fields) because fields that are used exclusive for device are undefined in host mode . 31.2.6.4.3.2 SOF Interrupt This SOF Interrupt used for device mode is shared as a free running 125us interrupt for host mode. EHCI does not specify this interrupt but it has been added for convenience and as a potential software time base. See USB Status Register (HW_USBCTRL_USBSTS) and USB Interrupt Enable Register (HW_USBCTRL_USBINTR) registers. 31.2.6.4.4 Embedded Design Interface This is an Embedded USB Host Controller as defined by the EHCI specification and thus does not implement the PCI configuration registers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2273 Functional Description 31.2.6.4.4.1 Frame Adjust Register Given that the optional PCI configuration registers are not included in this implementation, there is no corresponding bit level timing adjustments like is provided by the Frame Adjust register in the PCI configuration registers. Starts of micro-frames are timed precisely to 125 us using the transceiver clock as a reference clock. That is, a 60 Mhz transceiver clock for 8-bit physical interfaces & full-speed serial interfaces or 30 Mhz transceiver clock for 16-bit physical interfaces. 31.2.6.4.5 31.2.6.4.5.1 Miscellaneous variations from EHCI Programmable Physical Interface Behaviour This design supports multiple Physical interfaces which can operate in differing modes when the core is configured with software programmable Physical Interface Modes. Software programmability allows the selection of the Physical interface part during the board design phase instead of during the chip design phase. The control bits for selecting the Physical Interface operating mode have been added to the Port Status and Control 1 Register (HW_USBCTRL_PORTSC1) register providing a capability that is not defined by EHCI. 31.2.6.4.5.2 Discovery 31.2.6.4.5.2.1 Port Reset The port connect methods specified by EHCI require setting the port reset bit in the Port Status and Control 1 Register (HW_USBCTRL_PORTSC1) register for a duration of 10ms. Due to the complexity required to support the attachment of devices that are not high speed there are counter already present in the design that can count the 10ms reset pulse to alleviate the requirement of the software to measure this duration. Therefore, the basic connection is then summarized as the following: * [Port Change Interrupt] Port connect change occurs to notify the host controller driver that a device has attached. * Software shall write a '1' to the reset the device. * Software shall write a '0' to the reset the device after 10 ms. * This step, which is necessary in a standard EHCI design, may be omitted with this implementation. Should the EHCI host controller driver attempt to write a '0' i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2274 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller to the reset bit while a reset is in progress, the write will simple be ignored and the reset will continue until completion. * [Port Change Interrupt] Port enable change occurs to notify the host controller that the device in now operational and at this point the port speed has been determined. 31.2.6.4.5.2.2 Port Speed Detection After the port change interrupt indicates that a port is enabled, the EHCI stack should determine the port speed. Unlike the EHCI implementation, which will re-assign the port owner for any device that does not connect at High-Speed, this host controller supports direct attach of non High-Speed devices. Therefore, the following differences are important regarding port speed detection: * Port Owner is read-only and always reads 0. * A 2-bit Port Speed indicator has been added to PORTSC to provide the current operating speed of the port to the host controller driver. * A 1-bit High Speed indicator has been added to PORTSC to signify that the port is in High-Speed vs. Full/Low Speed - This information is redundant with the 2-bit Port Speed indicator above. 31.2.6.4.5.3 Port Test Mode Port Test Control mode behaves fully as described in EHCI. An alternate host controller driver procedure is not necessary or supported. 31.2.6.5 Device Data Structures This section defines the interface data structures used to communicate control, status, and data between Device Controller Driver (DCD) Software and the Device Controller. The data structure definitions in this chapter support a 32-bit memory buffer address space. The interface consists of device Queue Heads and Transfer Descriptors. NOTE Software must ensure that no interface data structure reachable by the Device Controller spans a 4K-page boundary. The data structures defined in the chapter are (from the device controller's perspective) a mix of read-only and read/ writable fields. The device controller must preserve the readonly fields on all data structure writes. The figure below shows the organization of the EndPoint Queue Head. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2275 Functional Description Endpoint Transfer Descriptor Transfer Buffer Pointer Up to 32 elements Transfer Buffer Transfer Buffer Pointer Endpoint QH 1 - Out Endpoint QH 0 - In Endpoint QH 0 - Out ENDPOINTLISTADDR Transfer Buffer Pointer Transfer Buffer Transfer Buffer Transfer Buffer Pointer Transfer Buffer Endpoint Queue Heads Figure 31-32. EndPoint Queue Head Organization Endpoint queue heads are arranged in an array in a continuous area of memory pointed to by the USB.ENDPOINTLISTADDR pointer. The even -numbered device queue heads in the list support receive endpoints (OUT/SETUP) and the odd-numbered queue heads in the list are used for transmit endpoints (IN/INTERRUPT). The device controller will index into this array based upon the endpoint number received from the USB bus. All information necessary to respond to transactions for all primed transfers is contained in this list so the Device Controller can readily respond to incoming requests without having to traverse a linked list. NOTE The Endpoint Queue Head List must be aligned to a 2k boundary. 31.2.6.5.1 Endpoint Queue Head (dQH) The device Endpoint Queue Head (dQH) is where all transfers for a given endpoint are managed. The dQH is a 48-byte data structure, but must be aligned on 64-byte boundaries. During priming of an endpoint, the dTD (device transfer descriptor) is copied into the overlay area of the dQH, which starts at the nextTD pointer DWord and continues through the end of the buffer pointers DWords. After a transfer is complete, the dTD i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2276 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller status DWord is updated in the dTD pointed to by the currentTD pointer. While a packet is in progress, the overlay area of the dQH is used as a staging area for the dTD so that the Device Controller can access needed information with little minimal latency. Table 31-53. Endpoint Queue Head (dQH) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Mult zlt 0 Maximum Packet Length 8 7 6 5 4 2 1 0 io 0 s Current dTD Pointer 0 Next dTD Pointer 0 0 3 Total Bytes io 0 c MultO 0 Buffer Pointer (Page 0) Current Offset Buffer Pointer (Page 1) Reserved Buffer Pointer (Page 2) Reserved Buffer Pointer (Page 3) Reserved Buffer Pointer (Page 4)1 Reserved T1 Status Reserved Set-up Buffer Bytes 3...0 Set-up Buffer Bytes 7...4 1. Transfer overlay starts at T and continues through Buffer Pointer (Page 4). Host Controller Read/Write 31.2.6.5.1.1 Host Controller Read Only Endpoint Capabilities/Characteristics This DWord specifies static information about the endpoint, in other words, this information does not change over the lifetime of the endpoint. Device Controller software should not attempt to modify this information while the corresponding endpoint is enabled. Table 31-54 describes the endpoint capabilities. Table 31-54. Endpoint Capabilities/Characteristics Bit Description 31-30 Mult. This field is used to indicate the number of packets executed per transaction description as given by the following: Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2277 Functional Description Table 31-54. Endpoint Capabilities/Characteristics (continued) 00 - Execute N Transactions as demonstrated by the USB variable length packet protocol where N is computed using the Maximum Packet Length (dQH) and the Total Bytes field (dTD) 01 Execute 1 Transaction. 10 Execute 2 Transactions. 11 Execute 3 Transactions. NOTE: Non-ISO endpoints must set Mult="00". ISO endpoints must set Mult="01", "10", or "11" as needed. 29 Zero Length Termination Select. This bit is used to indicate when a zero length packet is used to terminate transfers where to total transfer length is a multiple . This bit is not relevant for Isochronous 0 - Enable zero length packet to terminate transfers equal to a multiple of the Maximum Packet Length. (default). 1 - Disable the zero length packet on transfers that are equal in length to a multiple Maximum Packet Length. 28-27 Reserved. These bit reserved for future use and should be set to zero. 26-16 Maximum Packet Length. This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize). The maximum value this field may contain is 0x400 (1024). 15 Interrupt On Setup (IOS). This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. 14-0 Reserved. Bits reserved for future use and should be set to zero. 31.2.6.5.1.2 Transfer Overlay-Endpoint Queue Head The seven DWords in the overlay area represent a transaction working space for the device controller. The general operational model is that the device controller can detect whether the overlay area contains a description of an active transfer. If it does not contain an active transfer, then it will not read the associated endpoint. After an endpoint is readied, the dTD will be copied into this queue head overlay area by the device controller. Until a transfer is expired, software must not write the queue head overlay area or the associated transfer descriptor. When the transfer is complete, the device controller will write the results back to the original transfer descriptor and advance the queue. See dTD for a description of the overlay fields. 31.2.6.5.1.3 Current dTD Pointer The current dTD pointer is used by the device controller to locate the transfer in progress. This word is for Device Controller (hardware) use only and should not be modified by DCD software. The following table describes the dTD Pointer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2278 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-55. Next dTD Pointer Bit Description 31-5 Current dTD. This field is a pointer to the dTD that is represented in the transfer overlay area. This field will be modified by the Device Controller to next dTD pointer during endpoint priming or queue advance. 4-0 Reserved. Bit reserved for future use and should be set to zero. 31.2.6.5.1.4 Set-up Buffer The set-up buffer is dedicated storage for the 8-byte data that follows a set-up PID. NOTE Each endpoint has a TX and an RX dQH associated with it, and only the RX queue head is used for receiving setup data packets. The following table describes the Multiple Mode Control. Table 31-56. Multiple Mode Control (HCCPARAMS) DWord Bits Description 1 31-0 Setup Buffer 0. This buffer contains bytes 3 to 0 of an incoming setup buffer packet and is written by the device controller to be read by software. 2 31-0 Setup Buffer 1. This buffer contains bytes 7 to 4 of an incoming setup buffer packet and is written by the device controller to be read by software. 31.2.6.5.2 Endpoint Transfer Descriptor (dTD) The dTD describes to the device controller the location and quantity of data to be sent/ received for a given transfer. The DCD should not attempt to modify any field in an active dTD except the Next Like Pointer, which should only be modified as described in section Managing Transfers with Transfer Descriptors. Table below shows the Endpoint Transfer Descriptor (dTD). Table 31-57. Endpoint Transfer Descriptor (dTD) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Next Link Pointer 0 5 4 0 Total Bytes ioc 0 MultO 0 Buffer Pointer (Page 0) Current Offset Buffer Pointer (Page 1) 0 3 2 1 0 T Status Frame Number Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2279 Functional Description Table 31-57. Endpoint Transfer Descriptor (dTD) (continued) Buffer Pointer (Page 2) Reserved Buffer Pointer (Page 3) Reserved Buffer Pointer (Page 4) Reserved Host Controller Read/Write Host Controller Read Only The following table describes the dTD Pointer. Table 31-58. Next dTD Pointer Bit Description 31-5 Next Transfer Element Pointer. This field contains the physical memory address of the next dTD to be processed. The field corresponds to memory address signals [31:5], respectively. 4-1 Reserved. Bits reserved for future use and should be set to zero. 0 Terminate (T). 1=pointer is invalid. 0=Pointer is valid (points to a valid Transfer Element Descriptor). This bit indicates to the Device Controller that there are no more valid entries in the queue. The following table describes the dTD Token. Table 31-59. dTD Token Bit Description 31 Reserved. Bit reserved for future use and should be set to zero. 30-16 Total Bytes. This field specifies the total number of bytes to be moved with this transfer descriptor. This field is decremented by the number of bytes actually moved during the transaction and only on the successful completion of the transaction. The maximum value software may store in the field is 5*4K(5000H). This is the maximum number of bytes 5 page pointers can access. Although it is possible to create a transfer up to 20K this assumes the 1st offset into the first page is 0. When the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting the total bytes to 16K**. Therefore, the maximum recommended transfer is 16K(4000H). If the value of the field is zero when the host controller fetches this transfer descriptor (and the active bit is set), the device controller executes a zero-length transaction and retires the transfer descriptor. It is not a requirement for IN transfers that Total Bytes To Transfer be an even multiple of Maximum Packet Length. If software builds such a transfer descriptor for an IN transfer, the last transaction will always be less that Maximum Packet Length. 15 Interrupt On Complete (IOC). This bit is used to indicate if USBINT is to be set in response to device controller being finished with this dTD. 14-12 Reserved. Bits reserved for future use and should be set to zero. 11-10 Multiplier Override (MultO). This field can be used for transmit ISO's (ie. ISO-IN) to override the multiplier in the QH. This field must be zero for all packet types that are not transmit-ISO. Example: if QH.multiplier = 3; Maximum packet size = 8; Total Bytes = 15; MultiO = 0 [default] Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2280 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-59. dTD Token (continued) Three packets are sent: {Data2(8); Data1(7); Data0(0)} if QH.multiplier = 3; Maximum packet size = 8; Total Bytes = 15; MultiO = 2 Two packets are sent: {Data1(8); Data0(7)} For maximal efficiency, software should compute MultO = greatest integer of (Total Bytes / Max. Packet Size) except for the case when Total Bytes = 0; then MultO should be 1. Note: Non-ISO and Non-TX endpoints must set MultO="00". 9-8 Reserved. Bits reserved for future use and should be set to zero. 7-0 Status. This field is used by the Device Controller to communicate individual command execution states back to the Device Controller software. This field contains the status of the last transaction performed on this qTD. The bit encodings are: Bit Status Field Description 7 Active. 6 Halted. 5 Data Buffer Error. 3 Transaction Error. 4,2,0 Reserved. The table below describes the dTD Buffer Page Pointer List. Table 31-60. dTD Buffer Page Pointer List Bit Description 31-12 Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems will typically set the buffer pointers to a series of incrementing integers. 0,11-0 Current Offset. Offset into the 4kb buffer where the packet is to begin. 1,10-0 Frame Number. Written by the device controller to indicate the frame number in which a packet finishes. This is typically be used to correlate relative completion times of packets on an ISO endpoint. 31.2.6.6 Device Operational Model The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus. Using a set of linked list transfer descriptors, pointed to by a queue head, the device controller will perform the data transfers. The following sections explain the use of the device controller from the device controller driver (DCD) point-of-view and further describe how specific USB bus events relate to status changes in the device controller programmer's interface. 31.2.6.6.1 Device Controller Initialization After hardware reset, the device is disabled until the Run/Stop bit is set to a '1'. In the disabled state, the pull-up on the USB D+ is not active which prevents an attach event from occurring. At a minimum, it is necessary to have the queue heads setup for endpoint zero before the device attach occurs. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2281 Functional Description Shortly after the device is enabled, a USB reset will occur followed by setup packet arriving at endpoint 0. A Queue head must be prepared so that the device controller can store the incoming setup packet. In order to initialize a device, the software should perform the following steps: * Set Controller Mode in the USB.USBMODE register to device mode. NOTE Transitioning from host mode to device mode requires a device controller reset before modifying USB.USBMODE. * Allocate and Initialize device queue heads in system memory. * Minimum: Initialize device queue heads 0 Tx & 0 Rx. NOTE All device queue heads for control endpoints must be initialized before the endpoint is enabled. Non-Control device queue heads before the endpoint can be used. * For information on device queue heads, refer to section Device Data Structures. * Configure USB.ENDPOINTLISTADDR Pointer. * For additional information on USB.ENDPOINTLISTADDR, refer to the register table. * Enable the microprocessor interrupt associated with the USB core. * Recommended: enable all device interrupts including: USBINT, USBERRINT, Port Change Detect, USB Reset Received, DCSuspend. * For a list of available interrupts refer to the USB Interrupt Enable Register (HW_USBCTRL_USBINTR) and the USB Status Register (HW_USBCTRL_USBSTS) register tables. * Set Run/Stop bit to Run Mode. * After the Run bit is set and the device is connected to a host, a Bus Reset will be issued by host downstream port. The DCD must monitor the reset event and adjust the software state as described in the Bus Reset section of the Port State and Control section below. NOTE Endpoint 0 is designed as a control endpoint only and does not need to be configured using ENDPTCTRL0 register. It is also not necessary to prime Endpoint 0 initially because the first packet received will always be a setup packet. The contents of the first setup packet will require a response in accordance with USB device framework (Chapter 9) command set. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2282 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.6.2 Port State and Control From a chip or system reset, the device controller enters the powered state. A transition from the powered state to the attach state occurs when the Run/Stop bit is set to a '1'. After receiving a reset on the bus, the port will enter the defaultFS or defaultHS state in accordance with the reset protocol described in Appendix C.2 of the USB Specification Rev. 2.0. The following state diagram depicts the state of a USB 2.0 device. Active State Power Interruption Powered Attach When the host resets the device returns to the default state Default FS/HS Address FS/HS Configured FS/HS Inactive State Set Run/Stop bit to Run Mode Reset Bus Inactive Bus Activity Bus Inactive Bus Activity Bus Inactive Bus Activity Suspend FS/HS Suspend FS/HS Suspend FS/HS Software Only State Figure 31-33. Device State Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2283 Functional Description States powered, attach, defaultFS/HS, suspendFS/HS are implemented in the device controller and are communicated to the DCD using the following status bits: The following table describes the Device Controller State Information Bits. Table 31-61. Device Controller State Information Bits Bit Register DCSuspend USB Status Register (HW_USBCTRL_USBSTS) USB Reset Received USB Status Register (HW_USBCTRL_USBSTS) Port Change Detect USB Status Register (HW_USBCTRL_USBSTS) High-Speed Port Port Status and Control 1 Register (HW_USBCTRL_PORTSC1) It is the responsibility of the DCD to maintain a state variable to differentiate between the DefaultFS/HS state and the Address/Configured states. Change of state from Default to Address and the Configured states is part of the enumeration process described in the device framework section of the USB 2.0 Specification. As a result of entering the Address state, the device address register (DEVICEADDR) must be programmed by the DCD. Entry into the Configured indicates that all endpoints to be used in the operation of the device have been properly initialized by programming the USB_UOG_ENDPTCTRLx registers and initializing the associated queue heads. 31.2.6.6.2.1 Bus Reset A bus reset is used by the host to initialize downstream devices. When a bus reset is detected, the device controller will renegotiate its attachment speed, reset the device address to 0, and notify the DCD by interrupt (assuming the USB Reset Interrupt Enable is set). After a reset is received, all endpoints (except endpoint 0) are disabled and any primed transactions will be cancelled by the device controller. The concept of priming will be clarified below, but the DCD must perform the following tasks when a reset is received: Clear all setup token semaphores by reading the Endpoint Status Register (HW_USBCTRL_ENDPTSTAT) register and writing the same value back to the Endpoint Status Register (HW_USBCTRL_ENDPTSTAT) register. Clear all the endpoint complete status bits by reading the Endpoint Complete Register (HW_USBCTRL_ENDPTCOMPLETE) register and writing the same value back to the Endpoint Complete Register (HW_USBCTRL_ENDPTCOMPLETE) register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2284 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Cancel all primed status by waiting until all bits in the Endpoint Initialization Register (HW_USBCTRL_ENDPTPRIME) are 0 and then writing 0xFFFFFFFF to _ENDPTFLUSH. Read the reset bit in the Port Status and Control 1 Register (HW_USBCTRL_PORTSC1) register and make sure that it is still active. A USB reset will occur for a minimum of 3 ms and the DCD must reach this point in the reset cleanup before end of the reset occurs, otherwise a hardware reset of the device controller is recommended (rare.) * A hardware reset can be performed by writing a one to the device controller reset bit in the USBCMD reset. Note: a hardware reset will cause the device to detach from the bus by clearing the Run/Stop bit. Thus, the DCD must completely re-initialize the device controller after a hardware reset. Free all allocated dTDs because they will no longer be executed by the device controller. If this is the first time the DCD is processing a USB reset event, then it is likely that no dTDs have been allocated. At this time, the DCD may release control back to the OS because no further changes to the device controller are permitted until a Port Change Detect is indicated. After a Port Change Detect, the device has reached the default state and the DCD can read the Port Status and Control 1 Register (HW_USBCTRL_PORTSC1) to determine if the device is operating in FS or HS mode. At this time, the device controller has reached normal operating mode and DCD can begin enumeration according to the USB Chapter 9 - Device Framework. NOTE The device DCD may use the FS/HS mode information to determine the bandwidth mode of the device In some applications, it may not be possible to enable one or more pipes while in FS mode. Beyond the data rate issue, there is no difference in DCD operation between FS and HS modes. 31.2.6.6.2.2 31.2.6.6.2.2.1 Suspend/Resume Suspend Suspend Description In order to conserve power, USB devices automatically enter the suspended state when the device has observed no bus traffic for a specified period. When suspended, the USB device maintains any internal status, including its address and configuration. Attached devices must be prepared to suspend at any time they are powered, regardless of if they i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2285 Functional Description have been assigned a non-default address, are configured, or neither. Bus activity may cease due to the host entering a suspend mode of its own. In addition, a USB device shall also enter the suspended state when the hub port it is attached to is disabled. A USB device exits suspend mode when there is bus activity. A USB device may also request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wakeup. The ability of a device to signal remote wakeup is optional. If the USB device is capable of remote wakeup signaling, the device must support the ability of the host to enable and disable this capability. When the device is reset, remote wakeup signaling must be disabled. Suspend Operational Model The device controller moves into the suspend state when suspend signaling is detected or activity is missing on the upstream port for more than a specific period. After the device controller enters the suspend state, the DCD is notified by an interrupt (assuming DC Suspend Interrupt is enabled). When the DCSuspend bit in the Port Status and Control 1 Register (HW_USBCTRL_PORTSC1) is set to a '1', the device controller is suspended. DCD response when the device controller is suspended is application specific and may involve switching to low power operation. Information on the bus power limits in suspend state can be found in USB 2.0 specification. NOTE Review system level clocking issues defined in section (Ref: Signals-Clocking) for the clocking requirements of a suspended device controller. 31.2.6.6.2.2.2 Resume If the device controller is suspended, its operation is resumed when any non-idle signaling is received on its upstream facing port. In addition, the device can signal the system to resume operation by forcing resume signaling to the upstream port. Resume signaling is sent upstream by writing a '1' to the Resume bit in the in the _PORTSC1 while the device is in suspend state. Sending resume signal to an upstream port should cause the host to issue resume signaling and bring the suspended bus segment (one more devices) back to the active condition. NOTE Before resume signaling can be used, the host must enable it by using the Set Feature command defined in device framework (chapter 9) of the USB 2.0 Specification. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2286 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.6.2.3 Managing Endpoints The USB 2.0 specification defines an endpoint, also called a device endpoint or an address endpoint as a uniquely addressable portion of a USB device that can source or sink data in a communications channel between the host and the device. The endpoint address is specified by the combination of the endpoint number and the endpoint direction. The channel between the host and an endpoint at a specific device represents a data pipe. Endpoint 0 for a device is always a control type data channel used for device discovery and enumeration. Other types of endpoints support by USB include bulk, interrupt, and isochronous. Each endpoint type has specific behavior related to packet response and error handling. More detail on endpoint operation can be found in the USB 2.0 specification. The USB OTG device controller hardware supports up to 8 endpoint numbers. Each endpoint direction is essentially independent and can be configured with differing behavior in each direction. For example, the DCD can configure endpoint 1-IN to be a bulk endpoint and endpoint 1-OUT to be an isochronous endpoint. This helps to conserve the total number of endpoints required for device operation. The only exception is that control endpoints must use both directions on a single endpoint number to function as a control endpoint. Endpoint 0 is, for example, is always a control endpoint and uses the pair of directions. Each endpoint direction requires a queue head allocated in memory. To support the 8 endpoint numbers, 16 queue heads are required. The operation of an endpoint and use of queue heads are described later in this document. 31.2.6.6.2.4 Endpoint Initialization After hardware reset, all endpoints except endpoint zero are uninitialized and disabled. The DCD must configure and enable each endpoint by writing to configuration bit in the USB_UOG_ENDPTCTRLx register. Each 32-bit USB_UOG_ENDPTCTRLx is split into an upper and lower half. The lower half of USB_UOG_ENDPTCTRLx is used to configure the receive or OUT endpoint and the upper half is likewise used to configure the corresponding transmit or IN endpoint. Control endpoints must be configured the same in both the upper and lower half of the USB_UOG_ENDPTCTRLx register otherwise the behavior is undefined. The following i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2287 Functional Description table shows how to construct a configuration word for endpoint initialization. The following table shows the fields and values for the Device Controller Endpoint initialization. Table 31-62. Device Controller Endpoint Initialization Field Value Data Toggle Reset 1 Data Toggle Inhibit 0 Endpoint Type 00 Control 01 Isochronous 10 Bulk 11 Interrupt Endpoint Stall 31.2.6.6.2.5 0 Stalling There are two occasions where the device controller may need to return to the host a STALL. The first occasion is the functional stall, which is a condition set by the DCD as described in the USB 2.0 device framework. A functional stall is only used on non-control endpoints and can be enabled in the device controller by setting the endpoint stall bit in the USB_UOG_ENDPTCTRLx register associated with the given endpoint and the given direction. In a functional stall condition, the device controller will continue to return STALL responses to all transactions occurring on the respective endpoint and direction until the endpoint stall bit is cleared by the DCD. A protocol stall, unlike a function stall, is used on control endpoints is automatically cleared by the device controller at the start of a new control transaction (setup phase). When enabling a protocol stall, the DCD should enable the stall bits (both directions) as a pair. A single write to the USB_UOG_ENDPTCTRLx register can ensure that both stall bits are set at the same instant. NOTE Any write to the USB_UOG_ENDPTCTRLx register during operational mode must preserve the endpoint type field (that is, perform a read-modify-write). The following table shows the response matrix for the Device Controller Stall. Table 31-63. Device Controller Stall Response Matrix USB Packet Endpoint Stall Bit. Effect on STALL bit. USB Response Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2288 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-63. Device Controller Stall Response Matrix (continued) SETUP packet received by a non- N/A control endpoint. None. STALL IN/OUT/PING packet received by a non-control endpoint. '1' None. STALL IN/OUT/PING packet received by a non-control endpoint. '0' None. ACK/ NAK/ NYET SETUP packet received by a control endpoint. N/A Cleared ACK IN/OUT/PING packet received by a control endpoint '1' None STALL IN/OUT/PING packet received by a control endpoint. '0' None. ACK/ NAK/ NYET 31.2.6.6.2.6 Data Toggle Data toggle is a mechanism to maintain data coherency between host and device for any given data pipe. For more information on data toggle, refer to the USB 2.0 specification. 31.2.6.6.2.6.1 Data Toggle Reset The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device controller by writing a '1' to the data toggle reset bit in the USB_UOG_ENDPTCTRLx register. This should only be necessary when configuring/initializing an endpoint or returning from a STALL condition. 31.2.6.6.2.6.2 Data Toggle Inhibit NOTE This feature is for test purposes only and should never be used during normal device controller operation. Setting the data toggle Inhibit bit active ('1') causes the device controller to ignore the data toggle pattern that is normally sent and accept all incoming data packets regardless of the data toggle state. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2289 Functional Description In normal operation, the device controller checks the DATA0/DATA1 bit against the data toggle to determine if the packet is valid. If Data PID does not match the data toggle state bit maintained by the device controller for that endpoint, the Data toggle is considered not valid. If the data toggle is not valid, the device controller assumes the packet was already received and discards the packet (not reporting it to the DCD). To prevent the host controller from re-sending the same packet, the device controller will respond to the error packet by acknowledging it with either an ACK or NYET response. 31.2.6.6.2.6.3 Priming Transmit Endpoints Priming a transmit endpoint will cause the device controller to fetch the device transfer descriptor (dTD) for the transaction pointed to by the device queue head (dQH). After the dTD is fetched, it will be stored in the dQH until the device controller completes the transfer described by the dTD. Storing the dTD in the dQH allows the device controller to fetch the operating context needed to handle a request from the host without the need to follow the linked list, starting at the dQH when the host request is received. After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device controller. This FIFO is split into virtual channels so that the leading data can be stored for any endpoint up to the maximum number of endpoints configured at device synthesis time. After a priming request is complete, an endpoint state of primed is indicated in the USB_UOG_ENDPTSTATUS register. For a primed transmit endpoint, the device controller can respond to an IN request from the host and meet the stringent bus turnaround time of High Speed USB. Because only the leading data is stored in the device controller FIFO, it is necessary for the device controller to begin filling in behind leading data after the transaction starts. The FIFO must be sized to account for the maximum latency that can be incurred by the system memory bus. More information about FIFO sizing is presented in section . 31.2.6.6.2.6.4 Priming Receive Endpoints Priming receive endpoints is identical to priming of transmit endpoints from the point of view of the DCD. At the device controller the major difference in the operational model is that there is no data movement of the leading packet data simply because the data is to be received from the host. Note as part of the architecture, the FIFO for the receive endpoints is not partitioned into multiple channels like the transmit FIFO. Thus, the size of the RX FIFO does not scale with the number of endpoints. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2290 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.6.3 Operational Model For Packet Transfers All transactions on the USB bus are initiated by the host and in turn, the device must respond to any request from the host within the turnaround time stated in the USB 2.0 Specification. At USB 1.1 Full or Low Speed rates, this turnaround time was significant and the USB 1.1 device controllers were architected so that the device controller could access main memory or interrupt a host protocol processor in order to respond to the USB 1.1 transaction. The architecture of the USB 2.0 device controller must be different because same methods will not meet USB 2.0 High-speed turnaround time requirements by simply increasing clock rate. A USB host will send requests to the device controller in an order that can not be precisely predicted as a single pipeline, so it is not possible to prepare a single packet for the device controller to execute. However, the order of packet requests is predictable when the endpoint number and direction is considered. For example, if endpoint 3 (transmit direction) is configured as a bulk pipe, then we can expect the host will send IN requests to that endpoint. This device controller is architected in such a way that it can prepare packets for each endpoint/direction in anticipation of the host request. The process of preparing the device controller to send or receive data in response to host initiated transaction on the bus is referred to as "priming" the endpoint. This term will be used throughout the following documentation to describe the device controller operation so the DCD can be architected properly use priming. Further, note that the term "flushing" is used to describe the action of clearing a packet that was queued for execution. 31.2.6.6.3.1 Interrupt/Bulk Endpoint Operational Model The behaviors of the device controller for interrupt and bulk endpoints are identical. All valid IN and OUT transactions to bulk pipes will handshake with a NAK unless the endpoint had been primed. Once the endpoint has been primed, data delivery will commence. A dTD will be retired by the device controller when the packets described in the transfer descriptor have been completed. Each dTD describes N packets to be transferred according to the USB Variable Length transfer protocol. The formula and table on the following page describe how the device controller computes the number and length of the packets to be sent/received by the USB vary according to the total number of bytes and maximum packet length. With Zero Length Termination (ZLT) = 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2291 Functional Description N = INT(Number Of Bytes/Max. Packet Length) + 1 With Zero Length Termination (ZLT) = 1 N = MAXINT(Number Of Bytes/Max. Packet Length) Table 31-64. Variable Length Transfer Protocol Example (ZLT = 0) Bytes (dTD) Max. Packet Length (dQH) N P1 P2 511 256 2 256 255 512 256 3 256 256 512 512 2 512 0 P3 0 Table 31-65. Variable Length Transfer Protocol Example (ZLT = 1) Bytes (dTD) Max. Packet Length (dQH) N P1 P2 511 256 2 256 255 512 256 2 256 256 512 512 1 512 P3 NOTE The MULT field in the dQH must be set to "00" for bulk, interrupt, and control endpoints. TX-dTD is complete when: * All packets described dTD were successfully transmitted. *** Total bytes in dTD will equal zero when this occurs. RX-dTD is complete when: * All packets described in dTD were successfully received. *** Total bytes in dTD will equal zero when this occurs. * A short packet (number of bytes < maximum packet length) was received. *** This is a successful transfer completion; DCD must check Total Bytes in dTD to determine the number of bytes that are remaining. From the total bytes remaining in the dTD, the DCD can compute the actual bytes received. * A long packet was received (number of bytes > maximum packet size) OR (total bytes received > total bytes specified). *** This is an error condition. The device controller will discard the remaining packet, and set the Buffer Error bit in the dTD. In addition, the endpoint will be flushed and the USBERR interrupt will become active. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2292 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller On the successful completion of the packet(s) described by the dTD, the active bit in the dTD will be cleared and the next pointer will be followed when the Terminate bit is clear. When the Terminate bit is set, the device controller will flush the endpoint/direction and cease operations for that endpoint/direction. On the unsuccessful completion of a packet (see long packet above), the dQH will be left pointing to the dTD that was in error. In order to recover from this error condition, the DCD must properly reinitialize the dQH by clearing the active bit and update the nextTD pointer before attempting to re-prime the endpoint. NOTE All packet level errors such as a missing handshake or CRC error will be retried automatically by the device controller. There is no required interaction with the DCD for handling such errors. 31.2.6.6.3.1.1 Interrupt/Bulk Endpoint Bus Response Matrix The table below shows the response matrix for Interrput/Bulk Endpoint Bus. Table 31-66. Interrupt/Bulk Endpoint Bus Response Matrix Stall Not Primed Primed Underflow Overflow Setup Ignore Ignore Ignore N/A N/A In STALL NAK Transmit BS Error N/A Out STALL NAK Receive + NYET/ACK N/A NAK Ping STALL NAK ACK N/A N/A Invalid Ignore Ignore Ignore Ignore Ignore NOTE BS Error = Force Bit Stuff Error NYET/ACK - NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. SYSERR - System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. 31.2.6.6.3.2 Control Endpoint Operation Model i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2293 Functional Description 31.2.6.6.3.2.1 Setup Phase All requests to a control endpoint begin with a setup phase followed by an optional data phase and a required status phase. The device controller will always accept the setup phase unless the setup lockout is engaged. The setup lockout will engage so that future setup packets are ignored. Lockout of setup packets ensures that while software is reading the setup packet stored in the queue head, that data is not written as it is being read potentially causing an invalid setup packet. The setup lockout mechanism can be disabled and a new tripwire type semaphore will ensure that the setup packet payload is extracted from the queue head without being corrupted be an incoming setup packet. This is the preferred behavior because ignoring repeated setup packets due to long software interrupt latency would be a compliance issue. * Disable Setup Lockout by writing 1 to Setup Lockout Mode (SLOM) in USB Device Mode Register (HW_USBCTRL_USBMODE). (once at initialization). Setup lockout is not necessary when using the tripwire as described below. NOTE Leaving the Setup Lockout Mode As 0 will result in pre-2.3 hardware behavior. * After receiving an interrupt and inspecting Endpoint Setup Status Register (HW_USBCTRL_ENDPTSETUPSTAT) to determine that a setup packet was received on a particular pipe: a. Write 1 to clear corresponding bit Endpoint Setup Status Register (HW_USBCTRL_ENDPTSETUPSTAT). b. Write 1 to Setup Tripwire (SUTW) in USB Command Register (HW_USBCTRL_USBCMD) register. c. Duplicate contents of dQH.SetupBuffer into local software byte array. d. Read Setup TripWire (SUTW) in USB Command Register (HW_USBCTRL_USBCMD) register. (if set - continue; if cleared - goto 2) e. Write 0 to clear Setup Tripwire (SUTW) in USB Command Register (HW_USBCTRL_USBCMD) register. f. Process setup packet using local software byte array copy and execute status/ handshake phases. NOTE After receiving a new setup packet the status and/or handshake phases may still be pending from a previous control sequence. These should be flushed & deallocated before linking a new status and/or handshake dTD for the most recent setup packet. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2294 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.6.3.2.2 Data Phase Following the setup phase, the DCD must create a device transfer descriptor for the data phase and prime the transfer. After priming the packet, the DCD must verify a new setup packet has not been received by reading the USB.ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime will complete when the associated bit in the Endpoint Initialization Register (HW_USBCTRL_ENDPTPRIME) register is zero and the associated bit in the Endpoint Status Register (HW_USBCTRL_ENDPTSTAT) register is a one. If a prime fails, ie. The Endpoint Initialization Register (HW_USBCTRL_ENDPTPRIME) bit goes to zero and the _ENDPTSTAT bit is not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setup arriving during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit is cleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet. Should a setup arrive after the data stage is primed, the device controller will automatically clear the prime status (Endpoint Status Register (HW_USBCTRL_ENDPTSTAT)) to enforce data coherency with the setup packet. NOTE * The MULT field in the dQH must be set to "00" for bulk, interrupt, and control endpoints. * Error handling of data phase packets is the same as bulk packets described previously. 31.2.6.6.3.2.3 Status Phase Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime the endpoint for the status phase. The DCD must also perform the same checks of the USB.ENDPTSETUPSTAT as described above in the data phase. NOTE * The MULT field in the dQH must be set to 00 for bulk, interrupt, and control endpoints. * Error handling of data phase packets is the same as bulk packets described previously. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2295 Functional Description 31.2.6.6.3.2.4 Control Endpoint Bus Response Matrix Shown in the following table is the device controller response to packets on a control endpoint according to the device controller state. The table below shows the response matrix for the Control Endpoint Bus. Table 31-67. Control Endpoint Bus Response Matrix Token Type Endpoint State Setup Lockout Stall Not Primed Primed Underflow Overflow Setup ACK ACK ACK N/A SYSERR In STALL NAK Transmit BS Error N/A N/A Out STALL NAK Receive + NYET/ ACK N/A NAK N/A Ping STALL NAK ACK N/A N/A N/A Invalid Ignore Ignore Ignore Ignore Ignore Ignore BS Error = Force Bit Stuff Error NYET/ACK - NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then ACK. SYSERR - System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. 31.2.6.6.3.3 Isochronous Endpoint Operational Model Isochronous endpoints are used for real-time scheduled delivery of data and their operational model is significantly different than the host throttled Bulk, Interrupt, and Control data pipes. Real time delivery by the device controller will is accomplished by the following: * Exactly MULT Packets per (micro)Frame are transmitted/received. Note: MULT is a two-bit field in the device Queue Head. The variable length packet protocol is not used on isochronous endpoints. * NAK responses are not used. Instead, zero length packets and sent in response to an IN request to an unprimed endpoints. For unprimed RX endpoints, the response to an OUT transaction is to ignore the packet within the device controller. * Prime requests always schedule the transfer described in the dTD for the next (micro)frame. If the ISO-dTD is still active after that frame, then the ISO-dTD will be held ready until executed or canceled by the DCD. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2296 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller An EHCI compatible host controller uses the periodic frame list to schedule data exchanges to Isochronous endpoints. The operational model for device mode does not use such a data structure. Instead, the same dTD used for Control/Bulk/Interrupt endpoints is also used for isochronous endpoints. The difference is in the handling of the dTD. The first difference between bulk and ISO-endpoints is that priming an ISO-endpoint is a delayed operation such that an endpoint will become primed only after a SOF is received. After the DCD writes the prime bit, the prime bit will be cleared as usual to indicate to software that the device controller completed a priming the dTD for transfer. Internal to the design, the device controller hardware masks that prime start until the next frame boundary. This behavior is hidden from the DCD but occurs so that the device controller can match the dTD to a specific (micro)frame. Another difference with isochronous endpoints is that the transaction must wholly complete in a (micro)frame. Once an ISO transaction is started in a (micro)frame it will retire the corresponding dTD when MULT transactions occur or the device controller finds a fulfillment condition. The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment error occurs, the frame after the transfer failed to complete wholly, the device controller will force retire the ISO-dTD and move to the next ISO-dTD. It is important to note that fulfillment errors are only caused due to partially completed packets. If no activity occurs to a primed ISO-dTD, the transaction will stay primed indefinitely. This means it is up to software discard transmit ISO-dTDs that pile up from a failure of the host to move the data. Finally, the last difference with ISO packets is in the data level error handling. When a CRC error occurs on a received packet, the packet is not retried similar to bulk and control endpoints. Instead, the CRC is noted by setting the Transaction Error bit and the data is stored as usual for the application software to sort out. * TX Packet Retired * MULT counter reaches zero. * Fulfillment Error [Transaction Error bit is set] * # Packets Occurred > 0 AND # Packets Occurred < MULT NOTE For TX-ISO, MULT Counter can be loaded with a lesser value in the dTD Multiplier Override field in hardware versions 2.3 and later. If the Multiplier Override is zero, the MULT Counter is initialized to the Multiplier in the QH. * RX Packet Retired: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2297 Functional Description * MULT counter reaches zero. * Non-MDATA Data PID is received** * ** Exit criteria only valid in hardware version 2.3 or later. Previous to hardware version 2.3, any PID sequence that did not match the MULT field exactly would be flagged as a transaction error due to PID mismatch or fulfillment error. * Overflow Error: * Packet received is > maximum packet length. [Buffer Error bit is set] * Packet received exceeds total bytes allocated in dTD. [Buffer Error bit is set] * Fulfillment Error [Transaction Error bit is set] * # Packets Occurred > 0 AND # Packets Occurred < MULT * CRC Error [Transaction Error bit is set NOTE For ISO, when a dTD is retired, the next dTD is primed for the next frame. For continuous (micro)frame to (micro)frame operation the DCD should ensure that the dTD linked-list is out ahead of the device controller by at least two (micro)frames. 31.2.6.6.3.3.1 Isochronous Pipe Synchronization When it is necessary to synchronize an isochroous data pipe to the host, the (micro)frame number (USB_UOG_FRINDEX register) can be used as a marker. To cause a packet transfer to occur at a specific (micro)frame number [N], the DCD should interrupt on SOF during frame N-1. When the USB_UOG_FRINDEX=N-1, the DCD must write the prime bit. The device controller will prime the isochronous endpoint in (micro)frame N-1 so that the device controller will execute delivery during (micro)frame N. NOTE Priming an endpoint towards the end of (micro)frame N-1 will not guarantee delivery in (micro)frame N. The delivery may actually occur in (micro)frame N+1 if device controller does not have enough time to complete the prime before the SOF for packet N is received. 31.2.6.6.3.3.2 Isochronous Endpoint Bus Response Matrix The following table shows the response matrix for the Isochronous Endpoint Bus. Table 31-68. Isochronous Endpoint Bus Response Matrix Stall Not Primed Primed Underflow Overflow Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2298 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller Table 31-68. Isochronous Endpoint Bus Response Matrix (continued) Setup STALL STALL STALL N/A N/A In NULL Packet NULL Packet Transmit BS Error N/A Out Ignore Ignore Receive N/A Drop Packet Ping Ignore Ignore Ignore Ignore Ignore Invalid Ignore Ignore Ignore Ignore Ignore 1. BS Error = Force Bit Stuff Error NULL Packet = Zero Length Packet 31.2.6.6.4 Managing Queue Heads The following figure shows the End Point Queue Head. Transfer Buffer Pointer Transfer Buffer Endpoint QH 0 - Out Endpoint QH 0 - In Transfer Buffer Pointer Endpoint QH 1 - Out Transfer Buffer Transfer Buffer Pointer Transfer Buffer Transfer Buffer Pointer Up to 32 elements Endpoint Transfer Descriptor Transfer Buffer ENDPOINTLISTADDR Figure 31-34. End Point Queue Head Diagram The device queue head (dQH) points to the linked list of transfer tasks, each depicted by the device Transfer Descriptor (dTD). An area of memory pointed to by USB.ENDPOINTLISTADDR contains a group of all dQH's in a sequential list as shown in Figure 31-34. The even elements in the list of dQH's are used for receive endpoints (OUT/SETUP) and the odd elements are used for transmit endpoints (IN/INTERRUPT). Device transfer descriptors are linked head to tail starting at the queue head and ending at a terminate bit. Once the dTD has been retired, it will no longer be part of the linked list i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2299 Functional Description from the queue head. Therefore, software is required to track all transfer descriptors because pointers will no longer exist within the queue head once the dTD is retired (see section Software Link Pointers). In addition to the current and next pointers and the dTD overlay examined in section Operational Model For Packet Transfers, the dQH also contains the following parameters for the associated endpoint: Multipler, Maximum Packet Length, Interrupt On Setup. The complete initialization of the dQH including these fields is demonstrated in the next section. 31.2.6.6.4.1 Queue Head Initialization One device queue head must be initialized for each active endpoint. To initialize a device queue head: * Write the wMaxPacketSize field as required by the USB Chapter 9 or application specific protocol. * Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For ISO endpoints, set the multiplier to 1,2, or 3 as required bandwidth an in conjunction with the USB Chapter 9 protocol. NOTE In FS mode, the multiplier field can only be 1 for ISO endpoints. * Write the next dTD Terminate bit field to 1. * Write the Active bit in the status field to 0. * Write the Halt bit in the status field to 0. NOTE The DCD must only modify dQH if the associated endpoint is not primed and there are no outstanding dTD's. 31.2.6.6.4.2 Operational Model For Setup Transfers As discussed in section Control Endpoint Operation Model, setup transfer requires special treatment by the DCD. A setup transfer does not use a dTD but instead stores the incoming data from a setup packet in an 8-byte buffer within the dQH. Upon receiving notification of the setup packet, the DCD should handle the setup transfer as demonstrated here: 1. Copy setup buffer contents from dQH - RX to software buffer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2300 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 2. Acknowledge setup backup by writing a "1" to the corresponding bit in ENDPTSETUPSTAT. NOTE * The acknowledge must occur before continuing to process the setup packet. * After the acknowledge has occurred, the DCD must not attempt to access the setup buffer in the dQH - RX. Only the local software copy should be examined. 3. Check for pending data or status dTD's from previous control transfers and flush if any exist as discussed in section Flushing/De-priming an Endpoint. 4. Decode setup packet and prepare data phase [optional] and status phase transfer as required by the USB Chapter 9 or application specific protocol. NOTE It is possible for the device controller to receive setup packets before previous control transfers complete. Existing control packets in progress must be flushed and the new control packet completed. 31.2.6.6.5 31.2.6.6.5.1 Managing Transfers with Transfer Descriptors Software Link Pointers It is necessary for the DCD software to maintain head and tail pointers to the for the linked list of dTDs for each respective queue head. This is necessary because the dQH only maintains pointers to the current working dTD and the next dTD to be executed. The operations described in next section for managing dTD will assume the DCD can use reference the head and tail of the dTD linked list. The following figure shows the Software Link Pointers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2301 Functional Description Endpoint QH Head Pointer current Tail Pointer next Completed dTDs Queued dTDs Figure 31-35. Software Link Pointers NOTE To conserve memory, the reserved fields at the end of the dQH can be used to store the Head & Tail pointers, but it still remains the responsibility of the DCD to maintain the pointers. 31.2.6.6.5.2 Building a Transfer Descriptor Before a transfer can be executed from the linked list, a dTD must be built to describe the transfer. Use the following procedure for building dTDs. Allocate 8-DWord dTD block of memory aligned to 8-DWord boundaries. Example: bit address 4:0 would be equal to "00000" Write the following fields: 1. 2. 3. 4. 5. Initialize first 7 DWords to 0. Set the terminate bit to 1. Fill in total bytes with transfer size. Set the interrupt on complete if desired. Initialize the status field with the active bit set to 1 and all remaining status bits set to 0. 6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer. 7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer pointer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2302 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.6.5.3 Executing A Transfer Descriptor To safely add a dTD, the DCD must be follow this procedure which will handle the event where the device controller reaches the end of the dTD list at the same time a new dTD is being added to the end of the list. Determine whether the link list is empty: Check DCD driver to see if pipe is empty (internal representation of linked-list should indicate if any packets are outstanding). * Case 1: Link list is empty a. Write dQH next pointer AND dQH terminate bit to 0 as a single DWord operation. b. Clear active & halt bit in dQH (in case set from a previous error). c. Prime endpoint by writing 1 to correct bit position in Endpoint Initialization Register (HW_USBCTRL_ENDPTPRIME). * Case 2: Link list is not empty a. Add dTD to end of linked list. b. Read correct prime bit in Endpoint Initialization Register (HW_USBCTRL_ENDPTPRIME)- if 1 DONE. c. Set ATDTW bit in USBCMD register to 1. d. Read correct status bit in Endpoint Status Register (HW_USBCTRL_ENDPTSTAT). (store in tmp. variable for later) e. Read ATDTW bit in USBCMD register. * If 0 goto 3. * If 1 continue to 6. f. Write ATDTW bit in USBCMD register to 0. g. If status bit read in (3) is 1 DONE. h. If status bit read in (3) is 0 then Goto Case 1: Step 1. 31.2.6.6.5.4 Transfer Completion After a dTD has been initialized and the associated endpoint primed the device controller will execute the transfer upon the host-initiated request. The DCD will be notified with a USB interrupt if the Interrupt On Complete bit was set or alternately, the DCD can poll the endpoint complete register to find when the dTD had been executed. After a dTD has been executed, DCD can check the status bits to determine success or failure. NOTE Multiple dTD can be completed in a single endpoint complete notification. After clearing the notification, DCD must search the dTD linked list and retire all dTDs that have finished (Active bit cleared). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2303 Functional Description By reading the status fields of the completed dTDs, the DCD can determine if the transfers completed successfully. Success is determined with the following combination of status bits: * * * * Active = 0 Halted = 0 Transaction Error = 0 Data Buffer Error = 0 Should any combination other than the one shown above exist, the DCD must take proper action. Transfer failure mechanisms are indicated in the Device Error Matrix. In addition to checking the status bit the DCD must read the Transfer Bytes field to determine the actual bytes transferred. When a transfer is complete, the Total Bytes transferred is by decremented by the actual bytes transferred. For Transmit packets, a packet is only complete after the actual bytes reaches zero, but for receive packets, the host may send fewer bytes in the transfer according the USB variable length packet protocol. 31.2.6.6.5.5 Flushing/De-priming an Endpoint It is necessary for the DCD to flush to de-prime one more endpoints on a USB device reset or during a broken control transfer. There may also be application specific requirements to stop transfers in progress. The following procedure can be used by the DCD to stop a transfer in progress: 1. Write a '1' to the corresponding bit(s) in Endpoint De-Initialize Register (HW_USBCTRL_ENDPTFLUSH). 2. Wait until all bits in Endpoint De-Initialize Register (HW_USBCTRL_ENDPTFLUSH) are '0'. * Software note: this operation may take a large amount of time depending on the USB bus activity. It is not desirable to have this wait loop within an interrupt service routine. 3. Read Endpoint Status Register (HW_USBCTRL_ENDPTSTAT) to ensure that for all endpoints commanded to be flushed, that the corresponding bits are now '0'. If the corresponding bits are '1' after step #2 has finished, then the flush failed as described in the following: * Explanation: In very rare cases, a packet is in progress to the particular endpoint when commanded flush using Endpoint De-Initialize Register (HW_USBCTRL_ENDPTFLUSH). A safeguard is in place to refuse the flush to ensure that the packet in progress completes successfully. The DCD may need to repeatedly flush any endpoints that fail to flush be repeating steps 1-3 until each endpoint is successfully flushed. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2304 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.2.6.6.5.6 Device Error Matrix The following table summarizes packet errors that are not automatically handled by the Device Controller. Table 31-69. Device Error Matrix Error Direction Packet Type Data Buffer Error Bit Transaction Error Bit Overflow ** RX Any 1 0 ISO Packet Error RX ISO 0 1 ISO Fulfillment Error Both ISO 0 1 Notice that the device controller handles all errors on Bulk/Control/Interrupt Endpoints except for a data buffer overflow. However, for ISO endpoints, errors packets are not retried and errors are tagged as indicated. The table below describes the errors. Table 31-70. Error Descriptions Error Description Overflow Number of bytes received exceeded max. packet size or total buffer length. ** This error will also set the Halt bit in the dQH and if there are dTDs remaining in the linked list for the endpoint, then those will not be executed. ISO Packet Error CRC Error on received ISO packet. Contents not guaranteed to be correct. ISO Fulfillment Error Host failed to complete the number of packets defined in the dQH mult field within the given (micro)frame. For scheduled data delivery the DCD may need to readjust the data queue because a fulfillment error will cause Device Controller to cease data transfers on the pipe for one (micro)frame. During the "dead" (micro)frame, the Device Controller reports error on the pipe and primes for the following frame. 31.2.6.6.6 Servicing Interrupts The interrupt service routine must consider that there are high-frequency, low-frequency operations, and error operations and order accordingly. 31.2.6.6.6.1 High-Frequency Interrupts High frequency interrupts in particular should be handled in the order below. The most important of these is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible. The table below describes the High frequency interrupt events. Table 31-71. High Frequency Interrupt Events Execution Order Interrupt Action Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2305 Functional Description Table 31-71. High Frequency Interrupt Events (continued) 1a USB Interrupt USB.ENDPTSETUPSTATUS Copy contents of setup buffer and acknowledge setup packet (as indicated in Figure 31-34 shows the End Point Queue Head). Process setup packet according to USB 2.0 Chapter 9 or application specific protocol. 1b USB Interrupt1 - USB.ENDPTCOMPLETE Handle completion of dTD as indicated in Figure 31-34 shows the End Point Queue Head. 2 SOF Interrupt Action as deemed necessary by application. This interrupt may not have a use in all applications. 1. It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during the Interrupt Service Routine. 31.2.6.6.6.2 Low-Frequency Interrupts The low frequency interrupts can be handled in any order because they do not occur often in comparison to the high-frequency interrupts. The table below shows the Low frequency interrupt events. Table 31-72. Low Frequency Interrupt Events Interrupt Action Port Change Change software state information. Sleep Enable (Suspend) Change software state information. Low power handling as necessary. Reset Received Change software state information. Abort pending transfers. 31.2.6.6.6.3 Error Interrupts Error interrupts will be least frequent and should be placed last in the interrupt service routine. The following table shows the error interrput events. Table 31-73. Error Interrupt Events Interrupt Action USB Error Interrupt This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD will more aptly handle packet-level errors by checking dTD status field upon receipt of USB Interrupt (w/ USB.ENDPTCOMPLETE). System Error Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2306 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3 Programmable Registers USBCTRL Hardware Register Format Summary USB Controller0 base address is 0x80080000; USB Controller1 base address is 0x80090000 HW_USBCTRL memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8008_0000 Identification Register (HW_USBCTRL_ID) 32 R E401_FA05h 31.3.1/2309 8008_0004 General Hardware Parameters Register (HW_USBCTRL_HWGENERAL) 32 R 0000_0015h 31.3.2/2310 8008_0008 Host Hardware Parameters Register (HW_USBCTRL_HWHOST) 32 R 1002_0001h 31.3.3/2311 8008_000C Device Hardware Parameters Register (HW_USBCTRL_HWDEVICE) 32 R 0000_0011h 31.3.4/2312 8008_0010 TX Buffer Hardware Parameters Register (HW_USBCTRL_HWTXBUF) 32 R 8007_0A10h 31.3.5/2313 8008_0014 RX Buffer Hardware Parameters Register (HW_USBCTRL_HWRXBUF) 32 R 0000_0810h 31.3.6/2314 8008_0080 General-Purpose Timer 0 Load (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER0LD) 32 R/W 0000_0000h 31.3.7/2315 8008_0084 General-Purpose Timer 0 Control (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER0CTRL) 32 R/W 0000_0000h 31.3.8/2316 8008_0088 General-Purpose Timer 1 Load (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER1LD) 32 R/W 0000_0000h 31.3.9/2317 8008_008C General-Purpose Timer 1 Control (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER1CTRL) 32 R/W 0000_0000h 31.3.10/ 2318 8008_0090 System Bus Configuration (Non-EHCI-Compliant) Register (HW_USBCTRL_SBUSCFG) 32 R/W 0000_0000h 31.3.11/ 2319 8008_0100 Capability Length and HCI Version (EHCI-Compliant) Register (HW_USBCTRL_CAPLENGTH) 32 R 0100_0040h 31.3.12/ 2320 8008_0104 Host Control Structural Parameters (EHCI-Compliant with Extensions) Register (HW_USBCTRL_HCSPARAMS) 32 R 0001_0011h 31.3.13/ 2321 8008_0108 Host Control Capability Parameters (EHCI-Compliant) Register (HW_USBCTRL_HCCPARAMS) 32 R 0000_0006h 31.3.14/ 2323 8008_0120 Device Interface Version Number (Non-EHCI-Compliant) Register (HW_USBCTRL_DCIVERSION) 32 R/W 0000_0001h 31.3.15/ 2325 8008_0124 Device Control Capability Parameters (Non-EHCICompliant) Register (HW_USBCTRL_DCCPARAMS) 32 R 0000_0188h 31.3.16/ 2325 8008_0140 USB Command Register (HW_USBCTRL_USBCMD) 32 R/W 0008_0000h 31.3.17/ 2327 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2307 Programmable Registers HW_USBCTRL memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8008_0144 USB Status Register (HW_USBCTRL_USBSTS) 32 R/W 0000_0000h 31.3.18/ 2331 8008_0148 USB Interrupt Enable Register (HW_USBCTRL_USBINTR) 32 R/W 0000_0000h 31.3.19/ 2336 8008_014C USB Frame Index Register (HW_USBCTRL_FRINDEX) 32 R/W 0000_0000h 31.3.20/ 2339 8008_0154 Frame List Base Address Register (Host Controller mode) (HW_USBCTRL_PERIODICLISTBASE) 32 R/W 0000_0000h 31.3.21/ 2340 8008_0154 USB Device Address Register (Device Controller mode) (HW_USBCTRL_DEVICEADDR) 32 R/W 0000_0000h 31.3.22/ 2342 8008_0158 Next Asynchronous Address Register (Host Controller mode) (HW_USBCTRL_ASYNCLISTADDR) 32 R/W 0000_0000h 31.3.23/ 2343 8008_0158 Endpoint List Address Register (Device Controller mode) (HW_USBCTRL_ENDPOINTLISTADDR) 32 R/W 0000_0000h 31.3.24/ 2344 8008_015C Embedded TT Asynchronous Buffer Status and Control Register (Host Controller mode) (HW_USBCTRL_TTCTRL) 32 R/W 0000_0000h 31.3.25/ 2345 8008_0160 Programmable Burst Size Register (HW_USBCTRL_BURSTSIZE) 32 R/W 0000_1010h 31.3.26/ 2346 8008_0164 Host Transmit Pre-Buffer Packet Timing Register (HW_USBCTRL_TXFILLTUNING) 32 R/W 0000_0000h 31.3.27/ 2347 8008_016C Inter-Chip Control Register (HW_USBCTRL_IC_USB) 32 R/W 0000_0000h 31.3.28/ 2349 8008_0170 ULPI Viewport Register (HW_USBCTRL_ULPI) 32 R/W 0000_0000h 31.3.29/ 2351 8008_0178 Endpoint NAK Register (HW_USBCTRL_ENDPTNAK) 32 R/W 0000_0000h 31.3.30/ 2352 8008_017C Endpoint NAK Enable Register (HW_USBCTRL_ENDPTNAKEN) 32 R/W 0000_0000h 31.3.31/ 2353 8008_0184 Port Status and Control 1 Register (HW_USBCTRL_PORTSC1) 32 R/W 1000_0000h 31.3.32/ 2355 8008_01A4 OTG Status and Control Register (HW_USBCTRL_OTGSC) 32 R/W 0000_0120h 31.3.33/ 2363 8008_01A8 USB Device Mode Register (HW_USBCTRL_USBMODE) 32 R/W 0000_0000h 31.3.34/ 2367 8008_01AC Endpoint Setup Status Register (HW_USBCTRL_ENDPTSETUPSTAT) 32 R/W 0000_0000h 31.3.35/ 2369 8008_01B0 Endpoint Initialization Register (HW_USBCTRL_ENDPTPRIME) 32 R/W 0000_0000h 31.3.36/ 2369 8008_01B4 Endpoint De-Initialize Register (HW_USBCTRL_ENDPTFLUSH) 32 R/W 0000_0000h 31.3.37/ 2371 8008_01B8 Endpoint Status Register (HW_USBCTRL_ENDPTSTAT) 32 R 0000_0000h 31.3.38/ 2372 8008_01BC Endpoint Complete Register (HW_USBCTRL_ENDPTCOMPLETE) 32 R/W 0000_0000h 31.3.39/ 2373 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2308 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 8008_01C0 Endpoint Control 0 Register (HW_USBCTRL_ENDPTCTRL0) 32 R/W 0080_0080h 31.3.40/ 2375 8008_01C4 Endpoint Control 1 Register (HW_USBCTRL_ENDPTCTRL1) 32 R/W 0000_0000h 31.3.41/ 2378 8008_01C8 Endpoint Control 2 Register (HW_USBCTRL_ENDPTCTRL2) 32 R/W 0000_0000h 31.3.42/ 2382 8008_01CC Endpoint Control 3 Register (HW_USBCTRL_ENDPTCTRL3) 32 R/W 0000_0000h 31.3.43/ 2384 8008_01D0 Endpoint Control 4 Register (HW_USBCTRL_ENDPTCTRL4) 32 R/W 0000_0000h 31.3.44/ 2386 8008_01D4 Endpoint Control 5 Register (HW_USBCTRL_ENDPTCTRL5) 32 R/W 0000_0000h 31.3.45/ 2388 8008_01D8 Endpoint Control 6 Register (HW_USBCTRL_ENDPTCTRL6) 32 R/W 0000_0000h 31.3.46/ 2390 8008_01DC Endpoint Control 7 Register (HW_USBCTRL_ENDPTCTRL7) 32 R/W 0000_0000h 31.3.47/ 2392 31.3.1 Identification Register (HW_USBCTRL_ID) The Identification Register provides a simple way to determine if the USB-HS USB 2.0 core is provided in the system. The HW_USBCTRL_ID register identifies the USB-HS USB 2.0 core and its revision. The default value of this register is 0xE241FA05. Address: 8008_0000h base + 0h offset = 8008_0000h Bit 31 30 29 28 CIVERSION R 27 26 25 24 VERSION 23 22 21 20 19 18 REVISION 17 16 0 0 1 2 1 0 1 0 1 TAG W Reset Bit R 1 1 1 0 0 15 14 13 12 11 RSVD1 1 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 NID RSVD0 ID W Reset 1 1 1 1 1 0 1 0 0 0 0 0 0 HW_USBCTRL_ID field descriptions Field 31-29 CIVERSION Description Identifies the Chip Idea product version of the USB-HS USB 2.0 core. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2309 Programmable Registers HW_USBCTRL_ID field descriptions (continued) Field Description 28-25 VERSION Identifies the version of the USB-HS USB 2.0 core release. (.) 24-21 REVISION Identifies the revision of the USB-HS USB 2.0 core release. (.) 20-16 TAG Identifies the tag of the USB-HS USB 2.0 core release. (.) 15-14 RSVD1 Reserved. 13-8 NID One's complement version of ID[5:0]. 7-6 RSVD0 Reserved. ID Configuration number. This number is set to 0x05 and indicates that the peripheral is the USB-HS USB 2.0 core. 31.3.2 General Hardware Parameters Register (HW_USBCTRL_HWGENERAL) The default value of this register is 0x00000015. General Hardware Parameters Address: 8008_0000h base + 4h offset = 8008_0004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD R SM PHYM PHYW BWT CLKC RT W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2310 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_HWGENERAL field descriptions Field Description 31-11 RSVD Reserved. 10-9 SM PHY Serial Engine Type. Always 0 = Serial engine not present. 8-6 PHYM PHY Type. Always 1 = UTMI. 5-4 PHYW Data Interface Width to PHY. Always 1 = 16 bits. 3 BWT Reserved for internal testing. Always 0. 2-1 CLKC USB Controller Clocking Method. Always 2 = Mixed clocked. 0 RT Reset Type. Always 1 = Synchronous 31.3.3 Host Hardware Parameters Register (HW_USBCTRL_HWHOST) The default value of this register is 0x10020001. Host hardware params as defined in sys-level/core-config Address: 8008_0000h base + 8h offset = 8008_0008h Bit 31 30 29 28 27 26 25 24 23 22 21 TTPER R 20 19 18 17 16 0 1 0 TTASY W Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2311 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 RSVD R 2 1 NPORT 0 HC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 HW_USBCTRL_HWHOST field descriptions Field Description 31-24 TTPER Periodic contexts for hub TT. 23-16 TTASY Asynch contexts for hub TT. 15-4 RSVD Reserved. 3-1 NPORT Maximum downstream ports minus 1. 0 HC Host Capable. Always 0x1. 31.3.4 Device Hardware Parameters Register (HW_USBCTRL_HWDEVICE) The default value of this register is 0x0000000B. device hardware params as defined in sys-level/core-config Address: 8008_0000h base + Ch offset = 8008_000Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 3 2 1 RSVD R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 RSVD R DEVEP 0 DC W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2312 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_HWDEVICE field descriptions Field Description 31-6 RSVD Reserved. 5-1 DEVEP Maximum number of endpoints, which is 8. 0 DC Device Capable. Always 0x1. 31.3.5 TX Buffer Hardware Parameters Register (HW_USBCTRL_HWTXBUF) The default value of this register is 0x40060910. tx hardware buf params Address: 8008_0000h base + 10h offset = 8008_0010h 31 R 30 29 28 TXLCR Bit 27 26 25 24 23 22 21 RSVD 20 19 18 17 16 TXCHANADD W Reset Bit 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 TXADD R TXBURST W Reset 0 0 0 0 1 0 1 0 0 0 0 1 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2313 Programmable Registers HW_USBCTRL_HWTXBUF field descriptions Field Description 31 TXLCR Always 0x1. 30-24 RSVD Reserved. 23-16 TXCHANADD Number of address bits for the TX buffer. 15-8 TXADD Always 0xa. TXBURST Burst size for memory-to-TX-buffer transfers. 31.3.6 RX Buffer Hardware Parameters Register (HW_USBCTRL_HWRXBUF) The default value of this register is 0x00000710. rx hardware buf params Address: 8008_0000h base + 14h offset = 8008_0014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 RSVD R 12 11 10 9 8 7 6 RXADD 5 4 3 2 1 0 0 0 RXBURST W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 HW_USBCTRL_HWRXBUF field descriptions Field 31-16 RSVD 15-8 RXADD Description Reserved. Always 0x08. RXBURST Burst size for RX buffer-to-memory transfers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2314 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.7 General-Purpose Timer 0 Load (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER0LD) The host/device controller driver can measure time-related activities using this timer register. This register is not part of the standard EHCI controller. This register contains the timer duration or load value. See the GPTIMER0CTRL (Non-EHCI) for a description of the timer functions. General Purpose Timer #0 Load Register Address: 8008_0000h base + 80h offset = 8008_0080h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 RSVD0 R 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 GPTLD W Reset 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_GPTIMER0LD field descriptions Field 31-24 RSVD0 Description Reserved. GPTLD General-Purpose Timer Load Value. This field is the value to be loaded into the GPTCNT countdown timer on a reset action. This value in this register represents the time in microseconds minus 1 for the timer duration. Example: for a one-millisecond timer, load 1000 Note: Max value is 0xFFFFFF or 16.777215 seconds. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2315 Programmable Registers 31.3.8 General-Purpose Timer 0 Control (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER0CTRL) The host/device controller driver can measure time-related activities using this timer register. This register is not part of the standard EHCI controller. This register contains the control for the timer and a data field can be queried to determine the running count value. This timer has granularity on 1 us and can be programmed to a little over 16 seconds. There are two modes supported by this timer, the first is a one-shot and the second is a looped count that is described in the register table below. When the timer counter value transitions to 0, an interrupt can be generated through the use of the timer interrupts in the USBTS and USBINTR registers. Address: 8008_0000h base + 84h offset = 8008_0084h Bit 31 30 29 28 25 24 23 22 21 20 19 18 17 16 GPTMODE GPTCNT GPTRST GPTRUN W Bit 26 RSVD0 R Reset 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 GPTCNT R W Reset 0 0 0 0 0 0 0 0 0 HW_USBCTRL_GPTIMER0CTRL field descriptions Field 31 GPTRUN Description General-Purpose Timer Run. This bit enables the general-purpose timer to run. Setting or clearing this bit will not have an effect on the GPTCNT except if it stops or starts counting. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2316 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_GPTIMER0CTRL field descriptions (continued) Field Description 0 1 30 GPTRST STOP -- Timer stop. RUN -- Timer run. General-Purpose Timer Reset. Writing a 1 to this bit will reload the GPTCNT with the value in GPTLD. 0 1 29-25 RSVD0 NOACTION -- No action. LOADCOUNTER -- Load counter value. Reserved. 24 GPTMODE General-Purpose Timer Mode. This bit selects between a single timer countdown and a looped count down. In one-shot mode, the timer will count down to 0, generate an interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to 0, generate an interrupt, and automatically reload the counter to begin again. 0 1 ONESHOT -- One shot. REPEAT -- Repeat. GPTCNT General-Purpose Timer Counter. This field is the value of the running timer. 31.3.9 General-Purpose Timer 1 Load (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER1LD) Same as GPTIMER0LD description. Address: 8008_0000h base + 88h offset = 8008_0088h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 RSVD0 R 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 GPTLD W Reset 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_GPTIMER1LD field descriptions Field 31-24 RSVD0 Description Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2317 Programmable Registers HW_USBCTRL_GPTIMER1LD field descriptions (continued) Field Description GPTLD General-Purpose Timer Load Value. This field is the value to be loaded into the GPTCNT countdown timer on a reset action. This value in this register represents the time in microseconds minus 1 for the timer duration. Example: for a one-millisecond timer, load 1000 Note: Max value is 0xFFFFFF or 16.777215 seconds. 31.3.10 General-Purpose Timer 1 Control (Non-EHCI-Compliant) Register (HW_USBCTRL_GPTIMER1CTRL) Same as GPTIMER0CTRL description. Address: 8008_0000h base + 8Ch offset = 8008_008Ch Bit 31 30 29 28 25 24 23 22 21 20 19 18 17 16 GPTMODE GPTCNT GPTRST GPTRUN W Bit 26 RSVD0 R Reset 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 GPTCNT R W Reset 0 0 0 0 0 0 0 0 0 HW_USBCTRL_GPTIMER1CTRL field descriptions Field 31 GPTRUN Description General-Purpose Timer Run. This bit enables the general-purpose timer to run. Setting or clearing this bit will not have an effect on the GPTCNT except if it stops or starts counting. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2318 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_GPTIMER1CTRL field descriptions (continued) Field Description 0 1 30 GPTRST STOP -- Timer stop. RUN -- Timer run. General-Purpose Timer Reset. Writing a 1 to this bit will reload the GPTCNT with the value in GPTLD. 0 1 29-25 RSVD0 NOACTION -- No action. LOADCOUNTER -- Load counter value. Reserved. 24 GPTMODE General-Purpose Timer Mode. This bit selects between a single timer countdown and a looped count down. In one-shot mode, the timer will count down to 0, generate an interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to 0, generate an interrupt, and automatically reload the counter to begin again. 0 1 ONESHOT -- One shot. REPEAT -- Repeat. GPTCNT General-Purpose Timer Counter. This field is the value of the running timer. 31.3.11 System Bus Configuration (Non-EHCI-Compliant) Register (HW_USBCTRL_SBUSCFG) This register controls the AMBA system bus Master/Slave interfaces. Address: 8008_0000h base + 90h offset = 8008_0090h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 RSVD R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 AHBBRS T W Reset 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_SBUSCFG field descriptions Field 31-3 RSVD Description Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2319 Programmable Registers HW_USBCTRL_SBUSCFG field descriptions (continued) Field Description AHBBRST AMBA AHB BURST. This field selects the following options for the m_hburst signal of the AMBA master interface: U_INCR -- INCR burst of unspecified length. S_INCR4 -- INCR4, non-multiple transfers of INCR4 will be decomposed into singles. S_INCR8 -- INCR8, non-multiple transfers of INCR8 will be decomposed into INCR4 or singles. S_INCR16 -- INCR16, non-multiple transfers of INCR16 will be decomposed into INCR8, INCR4 or singles. RESERVED -- This value is reserved and should not be used. U_INCR4 -- INCR4, non-multiple transfers of INCR4 will be decomposed into smaller unspecified length bursts. U_INCR8 -- INCR8, non-multiple transfers of INCR8 will be decomposed into smaller unspecified length bursts. U_INCR16 -- INCR16, non-multiple transfers of INCR16 will be decomposed into smaller unspecified length bursts. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 31.3.12 Capability Length and HCI Version (EHCI-Compliant) Register (HW_USBCTRL_CAPLENGTH) This register contains the Capability Length and HCI Version Register. Address: 8008_0000h base + 100h offset = 8008_0100h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 HCIVERSION R 12 11 10 9 8 7 6 RSVD 5 4 3 2 1 0 0 0 CAPLENGTH W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 HW_USBCTRL_CAPLENGTH field descriptions Field 31-16 HCIVERSION 15-8 RSVD Description Contains a BCD encoding of the EHCI revision number supported by the host controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision. Reserved. CAPLENGTH Offset to add to register base address at beginning of the Operational Register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2320 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.13 Host Control Structural Parameters (EHCI-Compliant with Extensions) Register (HW_USBCTRL_HCSPARAMS) Port-steering logic capabilities are described in this register. The default value of this register is 0x00010011. Address: 8008_0000h base + 104h offset = 8008_0104h Bit 31 30 29 28 27 26 RSVD2 R 25 24 23 N_TT 22 21 20 19 N_PTT 18 17 RSVD1 16 PI W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N_CC R N_PCC RSVD0 PPC N_PORTS W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 HW_USBCTRL_HCSPARAMS field descriptions Field 31-28 RSVD2 27-24 N_TT Description Reserved. Number of Transaction Translators (N_TT). Indicates the number of embedded transaction translators associated with the USB2.0 host controller. This in a non-EHCI field to support embedded TT. 23-20 N_PTT Number of Ports per Transaction Translator (N_PTT). Indicates the number of ports assigned to each transaction translator within the USB2.0 host controller. This in a non-EHCI field to support embedded TT. 19-17 RSVD1 16 PI Reserved. Port Indicators (P INDICATOR). Indicates whether the ports support port indicator control. When set to 1, the port status and control registers include a read/writable field for controlling the state of the port indicator. 15-12 N_CC Number of Companion Controller (N_CC). Indicates the number of companion controllers associated with this USB2.0 host controller. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2321 Programmable Registers HW_USBCTRL_HCSPARAMS field descriptions (continued) Field Description A 0 in this field indicates there are no internal Companion Controllers. Port-ownership hand-off is not supported. A value larger than 0 in this field indicates there are companion USB host controller(s). Port-ownership hand-offs are supported. High, Full- and Low-speed devices are supported on the host controller root ports. 11-8 N_PCC Number of Ports per Companion Controller. Indicates the number of ports supported per internal Companion Controller. It is used to indicate the port routing configuration to the system software. For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3. The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc. In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. The number in this field must be consistent with N_PORTS and N_CC. 7-5 RSVD0 4 PPC Reserved. Port Power Control. Indicates whether the host controller implementation includes port power control. A 1 indicates the ports have port power switches. A 0 indicates the ports do not have port power switches. The value of this field affects the functionality of the Port Power field in each port status and control register. N_PORTS Number of downstream ports. Specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register. Valid values are in the range of 0x11-0xF. A 0 in this field is undefined. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2322 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.14 Host Control Capability Parameters (EHCI-Compliant) Register (HW_USBCTRL_HCCPARAMS) This register identifies multiple mode control (time-base bit functionality) addressing capability. The default value of this register is 0x00000006. Address: 8008_0000h base + 108h offset = 8008_0108h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD2 R Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASP PFL ADC Reset RSVD0 W 0 1 1 0 EECP R IST W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_HCCPARAMS field descriptions Field 31-16 RSVD2 15-8 EECP Description Reserved. EHCI Extended Capabilities Pointer. Default = 0. This optional field indicates the existence of a capabilities list. A value of 0x00 indicates no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if implemented to maintain the consistency of the PCI header defined for this class of device. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2323 Programmable Registers HW_USBCTRL_HCCPARAMS field descriptions (continued) Field 7-4 IST Description Isochronous Scheduling Threshold. Indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit 7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit 7 is a 1, then host software assumes the host controller may cache an isochronous data structure for an entire frame. 3 RSVD0 2 ASP Reserved. Asynchronous Schedule Park Capability. Default = 1. If this bit is set to a 1, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. 1 PFL Programmable Frame List Flag. If this bit is set to 0, then the system software must use a frame list length of 1024 elements with this host controller. The USBCMD register Frame List Size field is a read-only register and must be set to 0. If set to a 1, then the system software can specify and use a smaller frame list and configure the host controller through the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K page boundary. This requirement ensures that the frame list is always physically contiguous. 0 ADC 64-bit Addressing Capability. No 64-bit addressing capability is supported. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2324 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.15 Device Interface Version Number (Non-EHCI-Compliant) Register (HW_USBCTRL_DCIVERSION) The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register. Address: 8008_0000h base + 120h offset = 8008_0120h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD R 0 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 DCIVERSION W Reset 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_DCIVERSION field descriptions Field Description 31-16 RSVD Reserved. DCIVERSION Two-byte BCD encoding of the interface version number. 31.3.16 Device Control Capability Parameters (Non-EHCI-Compliant) Register (HW_USBCTRL_DCCPARAMS) These fields describe the overall host/device capability of the controller. The default value of this register is 0x00000188. Address: 8008_0000h base + 124h offset = 8008_0124h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD1 R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HC DC 1 1 0 0 RSVD1 R RSVD2 DEN W Reset 0 0 0 0 0 0 0 0 0 0 1 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2325 Programmable Registers HW_USBCTRL_DCCPARAMS field descriptions Field 31-9 RSVD1 8 HC Description Reserved. Host Capable. When this bit is 1, this controller is capable of operating as an EHCI-compatible USB 2.0 host controller. 7 DC Device Capable. When this bit is 1, this controller is capable of operating as a USB 2.0 device. 6-5 RSVD2 Reserved. DEN Device Endpoint Number. This field indicates the number of endpoints built into the device controller, which is 8. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2326 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.17 USB Command Register (HW_USBCTRL_USBCMD) The serial bus host/device controller executes the command indicated in this register. * Default Value:0x00080B00 (Host mode), 0x00080000 (Device mode) Address: 8008_0000h base + 140h offset = 8008_0140h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD3 R ITC 0 0 0 0 0 0 0 0 0 0 1 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FS2 LR IAA ASE PSE FS1 FS0 RST RS 0 0 0 0 0 0 0 0 0 0 0 R RSVD1 0 RSVD2 Bit 0 SUTW Reset ATDTW W ASPE ASP W Reset 0 0 0 0 0 HW_USBCTRL_USBCMD field descriptions Field 31-24 RSVD3 23-16 ITC Description Reserved. Interrupt Threshold Control. Default 0x08. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are: Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2327 Programmable Registers HW_USBCTRL_USBCMD field descriptions (continued) Field Description 0x0 0x1 0x2 0x4 0x8 0x10 0x20 0x40 15 FS2 14 ATDTW IMM -- Immediate (no threshold). 1_MICROFRAME -- 1_MICROFRAME. 2_MICROFRAME -- 2_MICROFRAME. 4_MICROFRAME -- 4_MICROFRAME. 8_MICROFRAME -- 8_MICROFRAME. 16_MICROFRAME -- 16_MICROFRAME. 32_MICROFRAME -- 32_MICROFRAME. 64_MICROFRAME -- 64_MICROFRAME. Bit 2 of Frame List Size field. See definition of bit FS0 for the complete definition. Add dTD TripWire (device mode only). This bit is used as a semaphore to ensure the proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software. This bit shall also be cleared by hardware when is state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized. 13 SUTW Setup TripWire (device mode only). This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (See USBMODE) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. 12 RSVD2 11 ASPE Reserved. Asynchronous Schedule Park Mode Enable (OPTIONAL). When S/W changes the USBMODE.CM to Host(11), this bit defaults to 0x1. Software uses this bit to enable or disable Park mode. When this bit is 1, Park mode is enabled. When this bit is a 0, Park mode is disabled. This field is set to 1 in host mode; 0 in device mode. 10 RSVD1 9-8 ASP Reserved. Asynchronous Schedule Park Mode Count (OPTIONAL). When S/W changes the USBMODE.CM to Host(11), this field defaults to 0x3 and is R/W. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. See Section 4.10.3.2 of the EHCI specification for full operational details. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2328 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_USBCMD field descriptions (continued) Field Description Valid values are 0x1-0x3. Software must not write a 0 to this bit as this will result in undefined behavior. This field is set to 0x3 in host mode; 0x0 in device mode. 7 LR Light Host/Device Controller Reset (OPTIONAL). Not Implemented. This field will always be 0. 6 IAA Interrupt on Async Advance Doorbell. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is 1, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to 0 after it has set the Interrupt on Sync Advance status bit in the USBSTS register to 1. Software should not write a 1 to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This bit is only used in host mode. Writing a 1 to this bit when device mode is selected will have undefined results. 5 ASE Asynchronous Schedule Enable. Default 0. This bit controls whether the host controller skips processing the Asynchronous Schedule. 0 = Do not process the Asynchronous Schedule. 1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule. Only the host controller uses this bit. 4 PSE Periodic Schedule Enable. Default Ob. This bit controls whether the host controller skips processing the Periodic Schedule. 0 = Do not process the Periodic Schedule 1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. Only the host controller uses this bit. 3 FS1 2 FS0 Bit 1 of Frame List Size field. See definition of bit FS0 for the complete definition. Bit 0 of Frame List Size field. The Frame List Size field (FS2, FS1, FS0) specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3 and 2. Default is 000b. 000b = 1024 ELEMENTS (4096 bytes) Default value. 001b = 512_ELEMENTS (2048 bytes). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2329 Programmable Registers HW_USBCTRL_USBCMD field descriptions (continued) Field Description 010b = 256_ELEMENTS (1024 bytes). 011b = 128_ELEMENTS (512 bytes). 100b = 64_ELEMENTS (256 bytes). 101b = 32_ELEMENTS (128 bytes). 110b = 16_ELEMENTS (64 bytes). 111b = 8_ELEMENTS (32 bytes). Only the host controller uses this field. 1 RST Controller Reset (RESET). Software uses this bit to reset the controller. This bit is set to 0 by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a 0 to this register. Host Controller: When software writes a 1 to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a 1 when the HCHalted bit in the USBSTS register is a 0. Attempting to reset an actively running host controller will result in undefined behavior. Device Controller: When software writes a 1 to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Writing a 1 to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. 0 RS Run/Stop (RS). Default 0. 1 = Run. 0 = Stop. Host Controller: When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a 1. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a 1 to this field unless the host controller is in the Halted state (i.e., HCHalted in the USBSTS register is a 1). Device Controller: Writing a 1 to this bit will cause the device controller to enable a pullup on D+ and initiate an attach event. This control bit is not directly connected to the pullup enable, as the pullup will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized. Writing a 0 to this will cause a detach event. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2330 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.18 USB Status Register (HW_USBCTRL_USBSTS) This register indicates various states of the Host/Device Controller and any pending interrupts. This register does not indicate status resulting from a transaction on the serial bus. Software clears certain bits in this register by writing a 1 to them. * Default Value: 0x00001000 (Host mode), 0x00000000 (Device mode) Address: 8008_0000h base + 144h offset = 8008_0144h 30 29 28 27 26 25 24 23 22 21 20 19 18 UPI UAI 17 16 NAKI 31 RSVD3 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AS PS RCL SLI SRI URI AAI SEI FRI PCI UEI UI 0 0 0 0 0 0 0 0 0 RSVD5 R RSVD4 TI1 TI0 Bit R HCH RSVD1 Reset RSVD2 W ULPII W Reset 0 0 0 0 0 0 0 HW_USBCTRL_USBSTS field descriptions Field 31-26 RSVD5 25 TI1 Description Reserved. General-Purpose Timer Interrupt 1 (GPTINT1). This bit is set when the counter in the GPTIMER1CTRL (Non-EHCI) register transitions to 0. Writing a 1 to this bit will clear it. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2331 Programmable Registers HW_USBCTRL_USBSTS field descriptions (continued) Field 24 TI0 Description General-Purpose Timer Interrupt 0 (GPTINT0). This bit is set when the counter in the GPTIMER0CTRL (Non-EHCI) register transitions to 0. Writing a 1 to this bit will clear it. 23-20 RSVD4 19 UPI Reserved. USB Host Periodic Interrupt (USBHSTPERINT). This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected AND the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. This bit is not used by the device controller and will always be 0. 18 UAI USB Host Asynchronous Interrupt (USBHSTASYNCINT). This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected AND the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes. This bit is not used by the device controller and will always be 0. 17 RSVD3 16 NAKI Reserved. NAK Interrupt Bit. It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared. 15 AS Asynchronous Schedule Status. This bit reports the current real status of the Asynchronous Schedule. When set to 0 the asynchronous schedule status is disabled and if set to 1 the status is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Only used by the host controller. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2332 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_USBSTS field descriptions (continued) Field 14 PS Description Periodic Schedule Status. 0 = Default. This bit reports the current real status of the Periodic Schedule. When set to 0 the periodic schedule is disabled, and if set to 1 the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). Only used by the host controller. 13 RCL Reclamation. 0 = Default. This is a read-only status bit used to detect an empty asynchronous schedule. Only used by the host controller; 0 in device mode. 12 HCH HC Halted. 1 = Default. This bit is a 0 whenever the Run/Stop bit is a 1. The Host Controller sets this bit to 1 after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. internal error). Only used by the host controller; 0 in device mode. 11 RSVD2 10 ULPII 9 RSVD1 8 SLI Reserved. Not present in this implementation. Reserved. DC Suspend. 0 = Default. When a device controller enters a suspend state from an active state, this bit will be set to a 1. The device controller clears the bit upon exiting from a suspend state. Only used by the device controller. 7 SRI SOF Received. 0 = Default. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2333 Programmable Registers HW_USBCTRL_USBSTS field descriptions (continued) Field Description When the device controller detects a Start Of (micro) Frame, this bit will be set to a 1. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it. This is a non-EHCI status bit. 6 URI USB Reset Received. 0 = Default. When the device controller detects a USB Reset and enters the default state, this bit will be set to a 1. Software can write a 1 to this bit to clear the USB Reset Received status bit. Only used by the device controller. NOTE: This bit should not normally be used to detect reset during suspend, as this block will normally be clock-gated during that time. Use HW_USBPHY_CTRL_RESUME_IRQ, instead. 5 AAI Interrupt on Async Advance. 0 = Default. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source. Only used by the host controller. 4 SEI System Error. This bit is not used in this implementation and will always be set to 0. 3 FRI Frame List Rollover. The Host Controller sets this bit to a 1 when the Frame List Index rolls over from its maximum value to 0. The exact value at which the rollover occurs depends on the frame list size. For example. If the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a 1 every time FHINDEX [12] toggles. Only used by the host controller. 2 PCI Port Change Detect. The Host Controller sets this bit to a 1 when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2334 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_USBSTS field descriptions (continued) Field Description The Device Controller sets this bit to a 1 when the port controller enters the full or high-speed operational state. When the port controller exits the full or highspeed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits respectively. This bit is not EHCI compatible. 1 UEI USB Error Interrupt (USBERRINT). When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. See Section 4.15.1 in the EHCI specification for a complete list of host error interrupt conditions. The device controller detects resume signaling only. 0 UI USB Interrupt (USBINT). This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2335 Programmable Registers 31.3.19 USB Interrupt Enable Register (HW_USBCTRL_USBINTR) The interrupts to software are enabled with this register. An interrupt is generated when a bit is set and the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing polling of interrupt events by the software. Address: 8008_0000h base + 148h offset = 8008_0148h 30 29 28 27 26 25 24 23 RSVD5 R 22 21 20 19 18 RSVD4 TIE1 TIE0 17 UPIE UAIE 16 NAKE 31 RSVD3 Bit W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLE SRE URE AAE SEE FRE PCE UEE UE 0 0 0 0 0 0 0 0 0 RSVD2 ULPIE R RSVD1 Reset W Reset 0 0 0 0 0 0 0 HW_USBCTRL_USBINTR field descriptions Field 31-26 RSVD5 Description Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2336 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_USBINTR field descriptions (continued) Field 25 TIE1 Description General-Purpose Timer Interrupt Enable 1. When this bit is a 1, and the GPTINT1 bit in the USBSTS register is a 1, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the GPTINT1 bit. 24 TIE0 General-Purpose Timer Interrupt Enable 0. When this bit is a 1, and the GPTINT0 bit in the USBSTS register is a 1, the controller will issue an interrupt. The interrupt is acknowledged by software clearing the GPTINT0 bit. 23-20 RSVD4 19 UPIE Reserved. USB Host Periodic Interrupt Enable. When this bit is a 1, and the USBHSTPERINT bit in the USBSTS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit. 18 UAIE USB Host Asynchronous Interrupt Enable. RW 0x0 When this bit is a 1, and the USBHSTASYNCINT bit in the USBSTS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit. 17 RSVD3 16 NAKE Reserved. NAK Interrupt Enable. This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated. 15-11 RSVD2 10 ULPIE Reserved. ULPI Enable. Not used in this implementation. 9 RSVD1 8 SLE Reserved. Sleep Enable. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2337 Programmable Registers HW_USBCTRL_USBINTR field descriptions (continued) Field Description When this bit is a 1, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a 1 to the DCSuspend bit. Only used by the device controller. 7 SRE SOF Received Enable. When this bit is a 1, and the SOF Received bit in the USBSTS register is a 1, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit. 6 URE USB Reset Enable. When this bit is a 1, and the USB Reset Received bit in the USBSTS register is a 1, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit. Only used by the device controller. 5 AAE Interrupt on Async Advance Enable. When this bit is a 1, and the Interrupt on Async Advance bit in the USBSTS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit. Only used by the host controller. 4 SEE System Error Enable. When this bit is a 1, and the System Error bit in the USBSTS register is a 1, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the System Error bit. 3 FRE Frame List Rollover Enable. When this bit is a 1, and the Frame List Rollover bit in the USBSTS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. Only used by the host controller. 2 PCE Port Change Detect Enable. When this bit is a 1, and the Port Change Detect bit in the USBSTS register is a 1, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit. 1 UEE USB Error Interrupt Enable. When this bit is a 1, and the USBERRINT bit in the USBSTS register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register. 0 UE USB Interrupt Enable. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2338 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_USBINTR field descriptions (continued) Field Description When this bit is a 1, and the USBINT bit in the USBSTS register is a 1, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit. 31.3.20 USB Frame Index Register (HW_USBCTRL_FRINDEX) This register is used by the host controller to index the periodic frame list. The register updates every 125 microseconds (once each micro-frame). Bits [N: 3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by system software in the Frame List Size field in the USBCMD register. This register must be written as a DWord. Byte writes produce-undefined results. This register cannot be written unless the Host Controller is in the 'Halted' state as indicated by the HCHalted bit. A write to this register while the Run/Stop bit is set to a 1 produces undefined results. Writes to this register also affect the SOF value. In device mode this register is ReadOnly and, the device controller updates the FRINDEX [13:3] register from the frame number indicated by the SOF marker. Whenever a SOF is received by the USB bus, FRINDEX [13:3] will be checked against the SOF marker. If FRINDEX [13:3] is different from the SOF marker, FRINDEX [13:3] will be set to the SOF value and FRINDEX [2:0] will be set to 0 (i.e., SOF for 1 ms frame). If FRINDEX [13:3] is equal to the SOF value, FRINDEX [2:0] will be incremented (i.e., SOF for 125 us microframe.) * The default value of this register is undefined (free-running counter). Address: 8008_0000h base + 14Ch offset = 8008_014Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RSVD R 9 8 7 6 5 4 3 FRINDEX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 UINDEX W Reset 2 0 0 0 0 0 0 0 HW_USBCTRL_FRINDEX field descriptions Field 31-14 RSVD 13-3 FRINDEX Description Reserved. Frame List Current Index. Read/write in host mode. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2339 Programmable Registers HW_USBCTRL_FRINDEX field descriptions (continued) Field Description Read in device mode. The value in this register increments at the end of each time frame (e.g., micro-frame). Bits [N: 3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. In device mode, the value is the current frame number of the last frame transmitted. It is not used as an index. 12 11 10 9 8 7 6 5 N_12 -- FRAME LIST SIZE = 1024, USBCMD = 3'b000. N_11 -- FRAME LIST SIZE = 512, USBCMD = 3'b001. N_10 -- FRAME LIST SIZE = 256, USBCMD = 3'b010. N_9 -- FRAME LIST SIZE = 128, USBCMD = 3'b011. N_8 -- FRAME LIST SIZE = 64, USBCMD = 3'b100. N_7 -- FRAME LIST SIZE = 32, USBCMD = 3'b101. N_6 -- FRAME LIST SIZE = 16, USBCMD = 3'b110. N_5 -- FRAME LIST SIZE = 8, USBCMD = 3'b111. UINDEX Current Microframe. 31.3.21 Frame List Base Address Register (Host Controller mode) (HW_USBCTRL_PERIODICLISTBASE) In Host Controller mode, this 32-bit register contains the beginning address of the Periodic Frame List in the system memory. HCD loads this register prior to starting the schedule execution by the Host Controller. The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. This is a read/write register. Writes must be DWORD writes. Address: 8008_0000h base + 154h offset = 8008_0154h Bit 31 30 29 28 27 26 25 24 R 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 0 0 0 0 0 RSVD PERBASE W Reset 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2340 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_PERIODICLISTBASE field descriptions Field 31-12 PERBASE Description Base Address (Low). These bits correspond to memory address signals [31:12], respectively. Only used by the host controller. RSVD Reserved. Must be written as zeros. During runtime, the values of these bits are undefined. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2341 Programmable Registers 31.3.22 USB Device Address Register (Device Controller mode) (HW_USBCTRL_DEVICEADDR) In Device Controller mode, the upper seven bits of this register represent the device address. After any controller reset or a USB reset, the device address is set to the default address (0). The default address will match all incoming addresses. Software shall reprogram the address after receiving a SET_ADDRESS descriptor. The USBADRA is used to accelerate the SET_ADDRESS sequence by allowing the DCD to preset the USBADR register before the status phase of the SET_ADDRESS descriptor. This is a read/write register. Writes must be DWORD writes. Address: 8008_0000h base + 154h offset = 8008_0154h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD USBADRA R USBADR W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 RSVD R W Reset 0 0 0 0 0 0 0 0 HW_USBCTRL_DEVICEADDR field descriptions Field 31-25 USBADR Description Device Address. These bits correspond to the USB device address. 24 USBADRA Device Address Advance. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2342 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_DEVICEADDR field descriptions (continued) Field Description Default=0. When this bit is 0', any writes to USBADR are instantaneous. When this bit is written to a 1 at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: 1. IN is ACKed to endpoint 0. (USBADR is updated from staging register). 2. OUT/SETUP occur to endpoint 0. (USBADR is not updated). 3. Device Reset occurs (USBADR is reset to 0). Note: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD cannot write of the device address within 2ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. RSVD Reserved. Must be written as zeros. During runtime, the values of these bits are undefined. 31.3.23 Next Asynchronous Address Register (Host Controller mode) (HW_USBCTRL_ASYNCLISTADDR) In Host Controller mode, this 32-bit register contains the address of the next asynchronous queue head to be executed by the host. Bits [4:0] of this register cannot be modified by the system software and will always return a 0 when read. Address: 8008_0000h base + 158h offset = 8008_0158h Bit 31 30 29 28 27 26 25 24 23 22 21 20 R 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 RSVD ASYBASE W Reset 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ASYNCLISTADDR field descriptions Field 31-5 ASYBASE Description Link Pointer Low (LPL). These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (OH). Only used by the host controller. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2343 Programmable Registers HW_USBCTRL_ASYNCLISTADDR field descriptions (continued) Field Description RSVD Reserved. These bits are reserved and their value has no effect on operation. 31.3.24 Endpoint List Address Register (Device Controller mode) (HW_USBCTRL_ENDPOINTLISTADDR) In Device Controller mode, this register contains the address of the top of the endpoint list in system memory. Bits [10:0] of this register cannot be modified by the system software and will always return a 0 when read. The memory structure referenced by this physical memory pointer is assumed 64-byte. This is a read/write register. Writes must be DWORD writes. Address: 8008_0000h base + 158h offset = 8008_0158h Bit 31 30 29 28 27 26 25 24 23 R 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 0 Reset 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 0 0 RSVD EPBASE W 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPOINTLISTADDR field descriptions Field 31-11 EPBASE Description Endpoint List Pointer (Low). These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Heads (QH). (i.e., one queue head per endpoint and direction.) RSVD Reserved. These bits are reserved and their value has no effect on operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2344 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.25 Embedded TT Asynchronous Buffer Status and Control Register (Host Controller mode) (HW_USBCTRL_TTCTRL) This register contains parameters needed for internal TT operations. This register is not used in the device controller operation. This is a read/write register. Writes must be DWORD writes. Address: 8008_0000h base + 15Ch offset = 8008_015Ch 31 R 30 29 28 27 26 25 24 23 22 21 RSVD1 Bit 20 19 18 17 16 RSVD2 TTHA W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSVD2 R W Reset 0 0 0 0 0 0 0 0 0 HW_USBCTRL_TTCTRL field descriptions Field 31 RSVD1 Description Reserved. These bits are reserved and their value has no effect on operation. 30-24 TTHA Internal TT Hub Address Representation. Default is 0 (Read/Write). This field is used to match against the Hub Address field in QH and siTD to determine if the packet is routed to the internal TT for directly attached FS/LS devices. If the Hub Address in the QH or siTD does not match this address then the packet will be broadcast on the High Speed ports destined for a downstream High Speed hub with the address in the QH/siTD. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2345 Programmable Registers HW_USBCTRL_TTCTRL field descriptions (continued) Field Description RSVD2 Reserved. These bits are reserved and their value has no effect on operation. 31.3.26 Programmable Burst Size Register (HW_USBCTRL_BURSTSIZE) This register is used to control dynamically change the burst size used during data movement on the initiator (master) interface. This is a read/write register. Writes must be DWORD writes. The default value is 0x00001010. Address: 8008_0000h base + 160h offset = 8008_0160h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 RSVD R 0 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 TXPBURST W Reset 13 0 0 0 0 0 0 0 0 0 0 1 0 0 5 4 3 2 1 0 0 0 RXPBURST 0 0 0 0 0 1 0 0 HW_USBCTRL_BURSTSIZE field descriptions Field 31-16 RSVD Description Reserved. These bits are reserved and their value has no effect on operation. 15-8 TXPBURST Programmable TX Burst Length. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus. RXPBURST Programmable RX Burst Length. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2346 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.27 Host Transmit Pre-Buffer Packet Timing Register (HW_USBCTRL_TXFILLTUNING) The fields in this register control performance tuning associated with how the host controller posts data to the TX latency FIFO before moving the data onto the USB bus. The specific areas of performance include the how much data to post into the FIFO and an estimate for how long that operation should take in the target system. Definitions: T0 = Standard packet overhead T1 = Time to send data payload Tff = Time to fetch packet into TX FIFO up to specified level. Ts = Total Packet Flight Time (send-only) packet Ts = T0 + T1 Tp = Total Packet Time (fetch and send) packet Tp = Tff + T0 + T1 Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure Tp remains before the end of the (micro)frame. If so it proceeds to prefill the TX FIFO. If at anytime during the pre-fill operation the time remaining the (micro)frame is < Ts then the packet attempt ceases and the packet is tried at a later time. Although this is not an error condition and the host controller will eventually recover, a mark will be made the scheduler health counter to note the occurrence of a "back-off" event. When a back-off event is detected, the partial packet fetched may need to be discarded from the latency buffer to make room for periodic traffic that will begin after the next SOF. Too many back-off events can waste bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated). Back-offs can be minimized with use of the TSCHHEALTH (Tff) described below. This is a read/write register. Writes must be DWORD writes. The default value of this register is 0x00000000. Address: 8008_0000h base + 164h offset = 8008_0164h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 RSVD2 R TXFIFOTHRES W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2347 Programmable Registers 14 13 12 11 10 9 8 RSVD1 R 7 6 5 4 3 2 1 0 0 0 0 RSVD0 15 Bit TXSCHEALTH TXSCHOH W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_TXFILLTUNING field descriptions Field 31-22 RSVD2 Description Reserved. These bits are reserved and their value has no effect on operation. 21-16 TXFIFOTHRES FIFO Burst Threshold. When S/W changes the USBMODE.CM to Host(11), the field defaults to 2. This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set. 15-13 RSVD1 Reserved. These bits are reserved and their value has no effect on operation. 12-8 TXSCHEALTH Scheduler Health Counter. This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31. 7 RSVD0 Reserved. This bit is reserved and its value has no effect on operation. TXSCHOH Scheduler Overhead. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2348 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_TXFILLTUNING field descriptions (continued) Field Description This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode for OTG & SPH. The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode for OTG & SPH. The time unit represented in this register is always 1.267 in the MPH product. 31.3.28 Inter-Chip Control Register (HW_USBCTRL_IC_USB) This register is present but not used in this implementation. This register enables and controls the IC_USB FS/LS transceiver. Address: 8008_0000h base + 16Ch offset = 8008_016Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD IC_ENABLE R IC_VDD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2349 Programmable Registers HW_USBCTRL_IC_USB field descriptions Field 31-4 RSVD 3 IC_ENABLE Description Reserved. Inter-Chip Transceiver Enable. These bits enables the InterChip transceiver for each port (for the MPH case). To enable the interface, the bits PTS must be set to 0b11 in the PORTSCx. Writing a '1' to each bit selects the IC_USB interface for that port. If the Controller is not MultiPort, IC8 to IC2 will be '0' and Read-Only. IC_VDD Inter-Chip Transceiver Voltage. Selects the voltage being supplied to the peripheral through each port (MPH case). 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 VOLTAGE_NONE -- . VOLTAGE_1_0 -- . VOLTAGE_1_2 -- . VOLTAGE_1_5 -- . VOLTAGE_1_8 -- . VOLTAGE_3_0 -- . RESERVED0 -- . RESERVED1 -- . i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2350 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.29 ULPI Viewport Register (HW_USBCTRL_ULPI) This register is present but not used in this implementation. 31 30 29 25 24 23 22 21 20 19 18 17 16 ULPIRW 26 ULPIRUN 27 ULPIWU R 28 ULPISS Bit RSVD0 Address: 8008_0000h base + 170h offset = 8008_0170h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 ULPIPORT ULPIADDR W Reset Bit ULPIDATRD R ULPIDATWR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ULPI field descriptions Field 31 ULPIWU 30 ULPIRUN 29 ULPIRW 28 RSVD0 Description Not used. Read as 0. Not used. Read as 0. Not used. Read as 0. Not used. Read as 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2351 Programmable Registers HW_USBCTRL_ULPI field descriptions (continued) Field Description 27 ULPISS Not used. Read as 0. 26-24 ULPIPORT Not used. Read as 0. 23-16 ULPIADDR Not used. Read as 0. 15-8 ULPIDATRD Not used. Read as 0. ULPIDATWR Not used. Read as 0. 31.3.30 Endpoint NAK Register (HW_USBCTRL_ENDPTNAK) NAK-sent indicator Address: 8008_0000h base + 178h offset = 8008_0178h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD1 R 0 0 0 0 0 19 18 17 16 15 14 13 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 RSVD0 EPTN W Reset 20 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 EPRN 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTNAK field descriptions Field 31-24 RSVD1 23-16 EPTN Description Reserved. TX Endpoint NAK. Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. EPTN[7] = Endpoint 7 EPTN[6] = Endpoint 6 EPTN[5] = Endpoint 5 EPTN[4] = Endpoint 4 EPTN[3] = Endpoint 3 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2352 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTNAK field descriptions (continued) Field Description EPTN[2] = Endpoint 2 EPTN[1] = Endpoint 1 EPTN[0] = Endpoint 0 15-8 RSVD0 Reserved. EPRN RX Endpoint NAK. Each RX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. EPRN[7] = Endpoint 7 EPRN[6] = Endpoint 6 EPRN[5] = Endpoint 5 EPRN[4] = Endpoint 4 EPRN[3] = Endpoint 3 EPRN[2] = Endpoint 2 EPRN[1] = Endpoint 1 EPRN[0] = Endpoint 0 31.3.31 Endpoint NAK Enable Register (HW_USBCTRL_ENDPTNAKEN) NAK-sent indicator enable Address: 8008_0000h base + 17Ch offset = 8008_017Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 RSVD1 R 0 0 0 0 0 18 17 16 15 14 13 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 RSVD0 EPTNE W Reset 19 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 EPRNE 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTNAKEN field descriptions Field 31-24 RSVD1 23-16 EPTNE Description Reserved. TX Endpoint NAK Enable. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2353 Programmable Registers HW_USBCTRL_ENDPTNAKEN field descriptions (continued) Field Description Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. EPTNE[7] = Endpoint 7 EPTNE[6] = Endpoint 6 EPTNE[5] = Endpoint 5 EPTNE[4] = Endpoint 4 EPTNE[3] = Endpoint 3 EPTNE[2] = Endpoint 2 EPTNE[1] = Endpoint 1 EPTNE[0] = Endpoint 0 15-8 RSVD0 Reserved. EPRNE RX Endpoint NAK Enable. Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. EPRNE[7] = Endpoint 7 EPRNE[6] = Endpoint 6 EPRNE[5] = Endpoint 5 EPRNE[4] = Endpoint 4 EPRNE[3] = Endpoint 3 EPRNE[2] = Endpoint 2 EPRNE[1] = Endpoint 1 EPRNE[0] = Endpoint 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2354 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.32 Port Status and Control 1 Register (HW_USBCTRL_PORTSC1) Host Controller: A host controller must implement one to eight port registers. The number of port registers implemented by a particular instantiation of a host controller is documented in the HCSPARAMs register and is fixed at 1 in this implementation. Software uses this information as an input parameter to determine how many ports need service. This register is only reset when power is initially applied or in response to a controller reset. The initial conditions of a port are: - No device connected - Port disabled If the port has port power control, this state remains until software applies power to the port by setting port power to 1. Device Controller: A device controller must implement only port register 1 and it does not support power control. Port control in device mode is only used for status port reset, suspend, and current connect status. It is also used to initiate test mode or force signaling and allows software to put the PHY into low power suspend mode and disable the PHY clock. * Default Value: 00010000000000000000XX0000000000b (Host mode) 00010000000000000001XX0000000100b (Device mode) X = Unknown Address: 8008_0000h base + 184h offset = 8008_0184h Bit 31 30 29 28 STS PTW 27 26 25 24 18 17 16 WKCN 19 WKDS 20 WKOC Bit 21 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PO PP HSP PR OCC OCA PEC PE CSC CCS 0 0 0 0 0 0 0 0 0 0 PTS PSPD PTS2 PFSC W Reset 22 PHCD R 23 PTC R PIC LS SUSP FPR W Reset 0 0 0 0 0 0 HW_USBCTRL_PORTSC1 field descriptions Field 31-30 PTS Description Parallel Transceiver Select. For this implementation, always set to 00b for UTMI. Note that this field is made up from PORTSCx bits 25, 30 and 31. 0 UTMI -- UTMI/UTMI+. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2355 Programmable Registers HW_USBCTRL_PORTSC1 field descriptions (continued) Field Description 1 2 3 4 29 STS PHIL -- Phillips-Classic. ULPI -- ULPI. SERIAL -- Serial/1.1FS. HSIC -- UTMI for HSIC. Serial Transceiver Select. Always 0. 28 PTW Parallel Transceiver Width. This bit is always 1, indicating an 16-bit (30-MHz) UTMI interface. 27-26 PSPD Port Speed. This register field indicates the speed at which the port is operating. For high-speed mode operation in the host controller and high-speed/fullspeed operation in the device controller, the port routing steers data to the protocol engine. This bit is not defined in the EHCI specification. 0 1 2 25 PTS2 FULL -- Full Speed. LOW -- Low Speed. HIGH -- High Speed. Parallel Transceiver Select,bit2. See PTS bits for details 24 PFSC Port Force Full Speed Connect. Default = 0. Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as high-speed. This is useful for testing full-speed configurations with a high-speed host, hub or device. This bit is not defined in the EHCI specification. This bit is for debugging purposes. 23 PHCD PHY Low Power Suspend - Clock Disable (PLPSCD). Default = 0. Writing this bit to a 1 will disable the PHY clock. Writing a 0 enables it. Reading this bit will indicate the status of the PHY clock. In Device Mode: The PHY can be put into Low Power Suspend running (USBCMD Run/Stop=0) or the host has signaled suspend (PORTSC SUSPEND=1). Lowpower suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2356 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_PORTSC1 field descriptions (continued) Field Description In Host Mode: The PHY can be put into Low Power Suspend device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. This bit is not defined in the EHCI specification. 22 WKOC Wake on Over-current Enable (WKOC_E). Default = 0. Writing this bit to a 1 enables the port to be sensitive to over-current conditions as wake-up events. This field is 0 if Port Power (PP) is 0. 21 WKDS Wake on Disconnect Enable (WKDSCNNT_E). Default=0. Writing this bit to a 1 enables the port to be sensitive to device disconnects as wake-up events. This field is 0 if Port Power (PP) is 0 or in device mode. 20 WKCN Wake on Connect Enable (WKCNNT_E). Default=0. Writing this bit to a 1 enables the port to be sensitive to device connects as wake-up events. This field is 0 if Port Power (PP) is 0 or in device mode. 19-16 PTC Port Test Control. Default = 0000b. Any other value than 0 indicates that the port is operating in test mode. Refer to Chapter 9 of the USB Specification Revision 2.0 for details on each test mode. The TEST_FORCE_ENABLE_FS and TEST_FORCE_ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the TEST_FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_DISABLE will allow the port state machines to progress normally from that point. Note: Low speed operations are not supported. 0 1 2 3 4 5 6 7 TEST_DISABLE -- Disable. TEST_J_STATE -- J-State. TEST_K_STATE -- K-State. TEST_J_SE0_NAK -- Host:SE0/Dev:NAK. TEST_PACKET -- Test-Packet. TEST_FORCE_ENABLE_HS -- Force-Enable-HS. TEST_FORCE_ENABLE_FS -- Force-Enable-FS. TEST_FORCE_ENABLE_LS -- Force-Enable-LS. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2357 Programmable Registers HW_USBCTRL_PORTSC1 field descriptions (continued) Field 15-14 PIC Description Port Indicator Control. Default = 0. Refer to the USB Specification Revision 2.0 for a description on how these bits are to be used. 0 1 2 3 13 PO OFF -- OFF. AMBER -- Amber. GREEN -- Green. UNDEF -- undefined. Port Owner. Port owner handoff is not implemented in this design, therefore this bit will always read back as 0. The EHCI definition is include here for reference: Default = 0. This bit unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1 transition. This bit unconditionally goes to 1 whenever the Configured bit is 0. System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit means that an internal companion controller owns and controls the port. 12 PP Port Power (PP). This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e., PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port, the PP bit in each affected port may be transitioned by the host controller driver from a 1 to a 0 (removing power from the port). This feature is implemented in the host/OTG controller (PPC = 1). In a device implementation, port power control is not necessary. 11-10 LS Line Status. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. The bit encodings are listed below. In Host Mode: The use of linestate by the host controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing manage the connection of LS and FS. In Device Mode: The use of linestate by the device controller driver is not necessary. 0 1 SE0 -- SE0. K_STATE -- K. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2358 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_PORTSC1 field descriptions (continued) Field Description 2 3 9 HSP J_STATE -- J. UNDEF -- Undefined. High-Speed Port. Default = 0. When the bit is 1, the host/device connected to the port is in high-speed mode and if set to 0, the host/ device connected to the port is not in a high-speed mode. Note: HSP is redundant with PSPD(27:26) but will remain in the design for compatibility. This bit is not defined in the EHCI specification. 8 PR Port Reset This field is 0 if Port Power (PP) is 0. In Host Mode: (Read/Write). 1 = Port is in Reset. 0 = Port is not in Reset. Default 0. When software writes a 1 to this bit, the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to 0 after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a 0 after the reset duration is timed in the driver. In Device Mode: This bit is a Read-Only status bit. Device reset from the USB bus is also indicated in the USBSTS register. 7 SUSP Suspend In Host Mode: (Read/Write) 0 = Port not in suspend state. 1 = Port in suspend state. Default = 0. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits Port State 0x Disable 10 Enable 11 Suspend When in suspend state, the downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to 0 when software sets the Force Port Resume bit to 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2359 Programmable Registers HW_USBCTRL_PORTSC1 field descriptions (continued) Field Description The host controller ignores a write of 0 to this bit. If host software sets this bit to a 1 when the port is not enabled (i.e., Port enabled bit is a 0) the results are undefined. This field is 0 if Port Power (PP) is 0 in host mode. In Device Mode: (Read-Only) 1 = Port in suspend state. 0 = Port not in suspend state. Default=0. In device mode, this bit is a Read-Only status bit. 6 FPR Force Port Resume. 0 = No resume (K-state) detected/driven on port. 1 = Resume detected/driven on port. Default = 0. In Host Mode: Software sets this bit to 1 to drive resume signaling. The Host Controller sets this bit to 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a 1 because a J-toK transition is detected, the Port Change Detect bit in the USBSTS register is also set to 1. This bit will automatically change to 0 after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a 0 after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a 1. This bit will remain a 1 until the port has switched to the high-speed idle. Writing a 0 has no effect because the port controller will time the resume operation and clear the bit when the port control state switches to HS or FS idle. This field is 0 if Port Power (PP) is 0 in host mode. This bit is not-EHCI compatible. In Device Mode: After the device has been in Suspend State for 5 ms or more, software must set this bit to 1 to drive resume signaling before clearing. The Device Controller will set this bit to 1 if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit transitions to a 1 because a J-to-K transition has been detected, the Port Change Detect bit in the USBSTS register is also set to 1. 5 OCC Over-Current Change. 0 = Default. 1 = This bit gets set to 1 when there is a change to Over-Current Active. Software clears this bit by writing a 1 to this bit position. For host/OTG implementations, the user can provide over-current detection to the vbus_pwr_fault input for this condition. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2360 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_PORTSC1 field descriptions (continued) Field Description For device-only implementations, this bit shall always be 0. 4 OCA Over-Current Active. 0 = This port does not have an over-current condition. 1 = This port currently has an over-current condition. Default = 0. This bit will automatically transition from 1 to 0 when the over current condition is removed. For host/OTG implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition. For device-only implementations this bit shall always be 0. 3 PEC Port Enable/Disable Change. 0 = No change. 1 = Port enabled/disabled status has changed. Default = 0. In Host Mode: For the root hub, this bit gets set to a 1 only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a 1 to it. This field is 0 if Port Power (PP) is 0. In Device Mode: The device port is always enabled. (This bit will be 0) 2 PE Port Enabled/Disabled. 0 = Disable. 1 = Enable. Default = 0. In Host Mode: Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a 1 to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled, (0) downstream propagation of data is blocked except for reset. This field is 0 if Port Power (PP) is 0 in host mode. In Device Mode: The device port is always enabled. (This bit will be 1) 1 CSC Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2361 Programmable Registers HW_USBCTRL_PORTSC1 field descriptions (continued) Field Description Connect Status Change. 0 = No change. 1 = Change in Current Connect Status. Default = 0. In Host Mode: Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a 1 to it. This field is 0 if Port Power (PP) is 0 in host mode. In Device Mode: This bit is undefined in device controller mode. 0 CCS Current Connect Status. In Host Mode: 0 = No device is present. 1 = Device is present on port. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is 0 if Port Power (PP) is 0 in host mode. In Device Mode: 0 = Not Attached. 1 = Attached. Default = 0. A 1 indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A 0 indicates that the device did not attach successfully or was forcibly disconnected by the software writing a 0 to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2362 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.33 OTG Status and Control Register (HW_USBCTRL_OTGSC) Host Controller: A host controller implements one On-The-Go (OTG) Status and Control register corresponding to Port 0 of the host controller. The OTGSC register has four sections: OTG Interrupt Enables (Read/Write) OTG Interrupt Status (Read/Write to Clear) OTG Status Inputs (Read-Only) OTG Controls (Read/Write) The status inputs are debounced using a 1-ms time constant. Values on the status inputs that do not persist for more than 1 ms will not cause an update of the status input register, or cause an OTG interrupt. See also USBMODE register. The default value of this register is 0x00000120. 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 BSE BSV ASV AVV ID 19 18 17 16 DPIS AVVIS AVVIE 0 20 ASVIS ASVIE IDIE 21 IDIS 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 IDPU DP OT HAAR DPIE 22 BSVIS 24 BSEIS 25 ONEMSS 26 HADP 27 23 VC VD 0 0 1 0 0 0 0 0 RSVD1 28 HABA 29 BSVIE R 30 BSEIE 31 RSVD2 Bit ONEMSE Address: 8008_0000h base + 1A4h offset = 8008_01A4h Bit R DPS ONEMST Reset RSVD0 W 0 0 W Reset 0 0 0 0 0 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2363 Programmable Registers HW_USBCTRL_OTGSC field descriptions Field 31 RSVD2 30 DPIE 29 ONEMSE 28 BSEIE Description Reserved. Data Pulse Interrupt Enable 1 Millisecond Timer Interrupt Enable B Session End Interrupt Enable. Setting this bit enables the B session end interrupt. 27 BSVIE B Session Valid Interrupt Enable. Setting this bit enables the B session valid interrupt. 26 ASVIE A Session Valid Interrupt Enable. Setting this bit enables the A session valid interrupt. 25 AVVIE A VBus Valid Interrupt Enable. Setting this bit enables the A VBus valid interrupt. 24 IDIE USB ID Interrupt Enable. Setting this bit enables the USB ID interrupt. 23 RSVD1 22 DPIS Reserved. Data Pulse Interrupt Status. This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when USBMODE.CM = Host (11) and PORTSC(0).PortPower = Off (0). Software must write a 1 to clear this bit. 21 ONEMSS 1 Millisecond Timer Interrupt Status. This bit is set once every millisecond. Software must write a 1 to clear this bit. 20 BSEIS B Session End Interrupt Status. This bit is set when VBus has fallen below the B session end threshold. Software must write a 1 to clear this bit. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2364 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_OTGSC field descriptions (continued) Field 19 BSVIS Description B Session Valid Interrupt Status. This bit is set when VBus has either risen above or fallen below the B session valid threshold (0.8 VDC). Software must write a 1 to clear this bit. 18 ASVIS A Session Valid Interrupt Status. This bit is set when VBus has either risen above or fallen below the A session valid threshold (0.8 VDC). Software must write a 1 to clear this bit. 17 AVVIS A VBus Valid Interrupt Status. This bit is set when VBus has either risen above or fallen below the VBus valid threshold (4.4 VDC) on an A device. Software must write a 1 to clear this bit. 16 IDIS USB ID Interrupt Status. This bit is set when a change on the ID input has been detected. Software must write a 1 to clear this bit. 15 RSVD0 14 DPS Reserved. Data Bus Pulsing Status. A 1 indicates data bus pulsing is being detected on the port. 13 ONEMST 1 Millisecond Timer Toggle. This bit toggles once per millisecond. 12 BSE B Session End. Indicates VBus is below the B session end threshold. 11 BSV B Session Valid. Indicates VBus is above the B session valid threshold. 10 ASV A Session Valid. Indicates VBus is above the A session valid threshold. 9 AVV A VBus Valid. Indicates VBus is above the A VBus valid threshold. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2365 Programmable Registers HW_USBCTRL_OTGSC field descriptions (continued) Field 8 ID Description USB ID. 0 = A device. 1 = B device. 7 HABA Hardware Assist B-Disconnect to A-connect. 0 = Disabled. 1 = Enable automatic B-disconnect to A-connect sequence. 6 HADP Hardware Assist Data-Pulse 1 = Start Data Pulse Sequence. 5 IDPU ID Pullup. This bit provide control over the ID pullup resister. 0 = off. 1 = on (default). When this bit is 0, the ID input will not be sampled. 4 DP Data Pulsing. Setting this bit causes the pullup on DP to be asserted for data pulsing during SRP. 3 OT OTG Termination. This bit must be set when the OTG device is in device mode, this controls the pulldown on DM. 2 HAAR Hardware Assist Auto-Reset. 0 = Disabled. 1 = Enable automatic reset after connect on host port. 1 VC VBUS Charge. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. 0 VD VBUS_Discharge. Setting this bit causes VBus to discharge through a resistor. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2366 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.34 USB Device Mode Register (HW_USBCTRL_USBMODE) Default Value:0x00000000 (implementation OTGmode not selected). Address: 8008_0000h base + 1A8h offset = 8008_01A8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD1 R Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLOM W ES 0 0 RSVD0 R SRT VBPS SDIS CM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_USBMODE field descriptions Field 31-16 RSVD1 15 SRT 14-6 RSVD0 5 VBPS Description Reserved. Short Reset Time. Reserved Vbus Power Select 0 = Output is 0. 1 = Output is 1. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2367 Programmable Registers HW_USBCTRL_USBMODE field descriptions (continued) Field Description This bit is connected to the vbus_pwr_select output and can be used for any generic control but is named to be used by logic that selects between an on-chip Vbus power source (charge pump) and an off-chip source in systems when both are available. 4 SDIS Stream Disable Mode. 0 = Inactive (default). 1 = Active. In Device Mode: Setting to a 1 disables double priming on both RX and TX for low bandwidth systems. This mode, when enabled, ensures that the RX and TX buffers are sufficient to contain an entire packet, so that the usual double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active. In Host Mode: Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significative when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING to characterize the adjustments needed for the scheduler when using this feature. Note: The use of this feature substantially limits of the overall USB performance that can be achieved. 3 SLOM Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. 0 = Setup Lockouts On (default). 1 = Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMD). 2 ES Endian Select. This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words. 0 = Little Endian (default): First byte referenced in least significant byte of 32-bit word. 1 = Big Endian: First byte referenced in most significant byte of 32-bit word. CM Controller Mode. Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host & device capability, the controller will default to an idle state and will need to be initialized to the desired operating mode after reset. For combination host/device controllers, this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2368 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_USBMODE field descriptions (continued) Field Description IDLE -- IDLE. DEVICE -- DEVICE. HOST -- HOST. 0x0 0x2 0x3 31.3.35 Endpoint Setup Status Register (HW_USBCTRL_ENDPTSETUPSTAT) endpoint setup status Address: 8008_0000h base + 1ACh offset = 8008_01ACh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RSVD R 0 0 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 ENDPTSETUPSTAT W Reset 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTSETUPSTAT field descriptions Field 31-8 RSVD Description Reserved. ENDPTSETUPSTAT Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. This register is only used in device mode. 31.3.36 Endpoint Initialization Register (HW_USBCTRL_ENDPTPRIME) This register is used in device mode only. endpoint prime request i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2369 Programmable Registers Address: 8008_0000h base + 1B0h offset = 8008_01B0h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD1 R 0 0 0 0 0 19 18 17 16 15 14 13 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 RSVD0 PETB W Reset 20 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 PERB 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTPRIME field descriptions Field 31-24 RSVD1 23-16 PETB Description Reserved. Prime Endpoint Transmit Buffer. For each endpoint, a corresponding bit is used to request that a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a 1 to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PETB[7] = Endpoint 7. PETB[6] = Endpoint 6. PETB[5] = Endpoint 5. PETB[4] = Endpoint 4. PETB[3] = Endpoint 3. PETB[2] = Endpoint 2. PETB[1] = Endpoint 1. PETB[0] = Endpoint 0. 15-8 RSVD0 Reserved. PERB Prime Endpoint Receive Buffer. For each endpoint, a corresponding bit is used to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a 1 to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PERB[7] = Endpoint 7. PERB[6] = Endpoint 6. PERB[5] = Endpoint 5. PERB[4] = Endpoint 4. PERB[3] = Endpoint 3. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2370 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTPRIME field descriptions (continued) Field Description PERB[2] = Endpoint 2. PERB[1] = Endpoint 1. PERB[0] = Endpoint 0. 31.3.37 Endpoint De-Initialize Register (HW_USBCTRL_ENDPTFLUSH) This register is used in device-mode only. endpoint flush request Address: 8008_0000h base + 1B4h offset = 8008_01B4h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD1 R 0 0 0 0 0 19 18 17 16 15 14 13 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 RSVD0 FETB W Reset 20 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 FERB 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTFLUSH field descriptions Field 31-24 RSVD1 23-16 FETB Description Reserved. Flush Endpoint Transmit Buffer. Writing a 1 to a bit(s) in this register will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for 1 of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful. FETB[7] = Endpoint 7. FETB[6] = Endpoint 6. FETB[5] = Endpoint 5. FETB[4] = Endpoint 4. FETB[3] = Endpoint 3. FETB[2] = Endpoint 2. FETB[1] = Endpoint 1. FETB[0] = Endpoint 0. 15-8 RSVD0 Reserved. FERB Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2371 Programmable Registers HW_USBCTRL_ENDPTFLUSH field descriptions (continued) Field Description Flush Endpoint Receive Buffer. Writing a 1 to a bit(s) will cause the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. Hardware will clear this register after the endpoint flush operation is successful. FERB[7] = Endpoint 7. FERB[6] = Endpoint 6. FERB[5] = Endpoint 5. FERB[4] = Endpoint 4. FERB[3] = Endpoint 3. FERB[2] = Endpoint 2. FERB[1] = Endpoint 1. FERB[0] = Endpoint 0. 31.3.38 Endpoint Status Register (HW_USBCTRL_ENDPTSTAT) This register is used in device mode only. endpoint ready Address: 8008_0000h base + 1B8h offset = 8008_01B8h Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD1 R 20 19 18 17 16 15 14 13 ETBR 12 11 10 9 8 7 6 5 RSVD0 4 3 2 1 0 0 0 0 ERBR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTSTAT field descriptions Field 31-24 RSVD1 23-16 ETBR Description Reserved. Endpoint Transmit Buffer Ready. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a 1 by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. Note: These bits will be momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ETBR[7] = Endpoint 7. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2372 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTSTAT field descriptions (continued) Field Description ETBR[6] = Endpoint 6. ETBR[5] = Endpoint 5. ETBR[4] = Endpoint 4. ETBR[3] = Endpoint 3. ETBR[2] = Endpoint 2. ETBR[1] = Endpoint 1. ETBR[0] = Endpoint 0. 15-8 RSVD0 Reserved. ERBR Endpoint Receive Buffer Ready. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a 1 by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. Note: These bits will be momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ERBR[7] = Endpoint 7. ERBR[6] = Endpoint 6. ERBR[5] = Endpoint 5. ERBR[4] = Endpoint 4. ERBR[3] = Endpoint 3. ERBR[2] = Endpoint 2. ERBR[1] = Endpoint 1. ERBR[0] = Endpoint 0. 31.3.39 Endpoint Complete Register (HW_USBCTRL_ENDPTCOMPLETE) This register is used in device-mode only. endpoint complete i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2373 Programmable Registers Address: 8008_0000h base + 1BCh offset = 8008_01BCh Bit 31 30 29 28 27 26 25 24 23 22 21 RSVD1 R 0 0 0 0 0 19 18 17 16 15 14 13 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 RSVD0 ETCE W Reset 20 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 ERCE 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTCOMPLETE field descriptions Field 31-24 RSVD1 23-16 ETCE Description Reserved. Endpoint Transmit Complete Event. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a 1 will clear the corresponding bit in this register. ETCE[7] = Endpoint 7. ETCE[6] = Endpoint 6. ETCE[5] = Endpoint 5. ETCE[4] = Endpoint 4. ETCE[3] = Endpoint 3. ETCE[2] = Endpoint 2. ETCE[1] = Endpoint 1. ETCE[0] = Endpoint 0. 15-8 RSVD0 Reserved. ERCE Endpoint Receive Complete Event. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a 1 will clear the corresponding bit in this register. ERCE[7] = Endpoint 7. ERCE[6] = Endpoint 6. ERCE[5] = Endpoint 5. ERCE[4] = Endpoint 4. ERCE[3] = Endpoint 3. ERCE[2] = Endpoint 2. ERCE[1] = Endpoint 1. ERCE[0] = Endpoint 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2374 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller 31.3.40 Endpoint Control 0 Register (HW_USBCTRL_ENDPTCTRL0) Every Device will implement Endpoint0 as a control endpoint. The default value of this register is 0x00800080. Address: 8008_0000h base + 1C0h offset = 8008_01C0h 31 30 29 28 27 26 25 24 23 22 RSVD6 R 21 20 19 18 17 16 RSVD4 Bit RSVD5 TXE TXT TXS W Bit 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD3 R RSVD1 Reset RSVD2 RXE RXT RXS W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTCTRL0 field descriptions Field 31-24 RSVD6 23 TXE Description Reserved. TX Endpoint Enable. 1 = Enabled. Endpoint0 is always enabled. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2375 Programmable Registers HW_USBCTRL_ENDPTCTRL0 field descriptions (continued) Field 22-20 RSVD5 Description Reserved. Bit reserved and should be read as zeroes. 19-18 TXT TX Endpoint Transmit Type. Endpoint0 is fixed as a Control endpoint. 0 17 RSVD4 16 TXS CONTROL -- Control. Reserved. Endpoint Stall. 0 = Endpoint OK (default). 1 = Endpoint Stalled. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Note: There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a 1 to it, then follow this procedure: Continually write this stall bit until it is set OR until a new SETUP has been received by checking the associated ENDPTSETUPSTAT bit. 15-8 RSVD3 Reserved. Bit reserved and should be read as zeroes. 7 RXE RX Endpoint Enable. 1 = Enabled. Endpoint0 is always enabled. 6-4 RSVD2 Reserved. Bit reserved and should be read as zeroes. 3-2 RXT RX Endpoint Receive Type. Endpoint0 is fixed as a Control endpoint. 0 CONTROL -- Control. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2376 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTCTRL0 field descriptions (continued) Field 1 RSVD1 0 RXS Description Reserved. RX Endpoint Stall. 0 = Endpoint OK (default). 1 = Endpoint Stalled. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Note: There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a 1 to it, then follow this procedure: Continually write this stall bit until it is set OR until a new SETUP has been received by checking the associated ENDPTSETUPSTAT bit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2377 Programmable Registers 31.3.41 Endpoint Control 1 Register (HW_USBCTRL_ENDPTCTRL1) Register HW_USBCTRL_ENDPTCTRL1 is the control register for endpoint 1 in a device. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/ direction. Address: 8008_0000h base + 1C4h offset = 8008_01C4h 31 30 29 28 27 26 25 24 23 22 21 TXE TXR TXI RSVD6 R 20 19 18 17 16 TXD TXS RSVD5 Bit TXT W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE RXR RXI RXD RXS 0 0 0 0 0 RSVD2 Reset RSVD3 R RXT W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTCTRL1 field descriptions Field 31-24 RSVD6 Description Reserved. 23 TXE Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2378 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTCTRL1 field descriptions (continued) Field Description TX Endpoint Enable. 0 = Disabled (default). 1 = Enabled. An endpoint should be enabled only after it has been configured. 22 TXR TX Data Toggle Reset. Write 1 to reset PID sequence. Whenever a configuration event is received for this endpoint, software must write a 1 to this bit in order to synchronize the data PIDs between the host and device. 21 TXI TX Data Toggle Inhibit. 0 = PID Sequencing Enabled (default). 1 = PID Sequencing Disabled. This bit is only used for test and should always be written as 0. Writing a 1 to this bit will cause this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet. 20 RSVD5 19-18 TXT Reserved. TX Endpoint Transmit Type. 0 1 2 3 17 TXD CONTROL -- Control. ISO -- Isochronous. BULK -- Bulk. INT -- Interrupt. TX Endpoint Data Source. 0 = Dual Port Memory Buffer/DMA Engine (default). Should always be written as 0. 16 TXS Endpoint Stall. 0 = Endpoint OK. 1 = Endpoint Stalled. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2379 Programmable Registers HW_USBCTRL_ENDPTCTRL1 field descriptions (continued) Field Description Note (control endpoint types only): There is a slight delay (50 clocks max.) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems it is unlikely the DCD software will observe this delay. However, Should the DCD observe that the stall bit is not set after writing a 1 to it, then follow this procedure: Continually write this stall bit until it is set OR until a new SETUP has been received by checking the associated ENDPTSETUPSTAT bit. 15-8 RSVD3 7 RXE Reserved. RX Endpoint Enable. 0 = Disabled (default). 1 = Enabled. An Endpoint should be enabled only after it has been configured. 6 RXR Data Toggle Reset. Write 1 to reset PID Sequence. Whenever a configuration event is received for this endpoint, software must write a 1 to this bit in order to synchronize the data PIDs between the host and device. 5 RXI RX Data Toggle Inhibit. 0 = Disabled (default). 1 = Enabled. This bit is only used for test and should always be written as 0. Writing a 1 to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packet regardless of their data PID. 4 RSVD2 3-2 RXT Reserved. RX Endpoint Receive Type. 0 1 2 3 1 RXD CONTROL -- Control. ISO -- Isochronous. BULK -- Bulk. INT -- Interrupt. RX Endpoint Data Sink. 0 = Dual Port Memory Buffer/DMA Engine (default). Should always be written as 0. 0 RXS RX Endpoint Stall. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2380 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTCTRL1 field descriptions (continued) Field Description 0 = Endpoint OK (default). 1 = Endpoint Stalled. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. Note (control endpoint types only): There is a slight delay (50 clocks maximum) between the ENDPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a 1 to it, then follow this procedure: Continually write this stall bit until it is set OR until a new SETUP has been received by checking the associated ENDPTSETUPSTAT bit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2381 Programmable Registers 31.3.42 Endpoint Control 2 Register (HW_USBCTRL_ENDPTCTRL2) Register HW_USBCTRL_ENDPTCTRL2 is the control register for endpoint 2 in a device. See the bit field defintions and descriptions of register HW_USBCTRL_ENDPTCTRL1. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/direction. Address: 8008_0000h base + 1C8h offset = 8008_01C8h 31 30 29 28 27 26 25 24 23 22 21 TXE TXR TXI RSVD6 R 20 19 18 17 16 TXD TXS RSVD5 Bit TXT W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE RXR RXI RXD RXS 0 0 0 0 0 RSVD2 Reset RSVD3 R RXT W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTCTRL2 field descriptions Field 31-24 RSVD6 Description same as HW_USBCTRL_ENDPTCTRL1 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2382 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTCTRL2 field descriptions (continued) Field Description 23 TXE same as HW_USBCTRL_ENDPTCTRL1 22 TXR same as HW_USBCTRL_ENDPTCTRL1 21 TXI same as HW_USBCTRL_ENDPTCTRL1 20 RSVD5 same as HW_USBCTRL_ENDPTCTRL1 19-18 TXT same as HW_USBCTRL_ENDPTCTRL1 17 TXD same as HW_USBCTRL_ENDPTCTRL1 16 TXS same as HW_USBCTRL_ENDPTCTRL1 15-8 RSVD3 same as HW_USBCTRL_ENDPTCTRL1 7 RXE same as HW_USBCTRL_ENDPTCTRL1 6 RXR same as HW_USBCTRL_ENDPTCTRL1 5 RXI same as HW_USBCTRL_ENDPTCTRL1 4 RSVD2 same as HW_USBCTRL_ENDPTCTRL1 3-2 RXT same as HW_USBCTRL_ENDPTCTRL1 1 RXD same as HW_USBCTRL_ENDPTCTRL1 0 RXS same as HW_USBCTRL_ENDPTCTRL1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2383 Programmable Registers 31.3.43 Endpoint Control 3 Register (HW_USBCTRL_ENDPTCTRL3) Register HW_USBCTRL_ENDPTCTRL3 is the control register for endpoint 3 in a device. See the bit field defintions and descriptions of register HW_USBCTRL_ENDPTCTRL1. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/direction. Address: 8008_0000h base + 1CCh offset = 8008_01CCh 31 30 29 28 27 26 25 24 23 22 21 TXE TXR TXI RSVD6 R 20 19 18 17 16 TXD TXS RSVD5 Bit TXT W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE RXR RXI RXD RXS 0 0 0 0 0 RSVD2 Reset RSVD3 R RXT W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTCTRL3 field descriptions Field 31-24 RSVD6 Description same as HW_USBCTRL_ENDPTCTRL1 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2384 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTCTRL3 field descriptions (continued) Field Description 23 TXE same as HW_USBCTRL_ENDPTCTRL1 22 TXR same as HW_USBCTRL_ENDPTCTRL1 21 TXI same as HW_USBCTRL_ENDPTCTRL1 20 RSVD5 same as HW_USBCTRL_ENDPTCTRL1 19-18 TXT same as HW_USBCTRL_ENDPTCTRL1 17 TXD same as HW_USBCTRL_ENDPTCTRL1 16 TXS same as HW_USBCTRL_ENDPTCTRL1 15-8 RSVD3 same as HW_USBCTRL_ENDPTCTRL1 7 RXE same as HW_USBCTRL_ENDPTCTRL1 6 RXR same as HW_USBCTRL_ENDPTCTRL1 5 RXI same as HW_USBCTRL_ENDPTCTRL1 4 RSVD2 same as HW_USBCTRL_ENDPTCTRL1 3-2 RXT same as HW_USBCTRL_ENDPTCTRL1 1 RXD same as HW_USBCTRL_ENDPTCTRL1 0 RXS same as HW_USBCTRL_ENDPTCTRL1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2385 Programmable Registers 31.3.44 Endpoint Control 4 Register (HW_USBCTRL_ENDPTCTRL4) Register HW_USBCTRL_ENDPTCTRL4 is the control register for endpoint 4 in a device. See the bit field defintions and descriptions of register HW_USBCTRL_ENDPTCTRL1. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/direction. Address: 8008_0000h base + 1D0h offset = 8008_01D0h 31 30 29 28 27 26 25 24 23 22 21 TXE TXR TXI RSVD6 R 20 19 18 17 16 TXD TXS RSVD5 Bit TXT W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE RXR RXI RXD RXS 0 0 0 0 0 RSVD2 Reset RSVD3 R RXT W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTCTRL4 field descriptions Field 31-24 RSVD6 Description same as HW_USBCTRL_ENDPTCTRL1 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2386 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTCTRL4 field descriptions (continued) Field Description 23 TXE same as HW_USBCTRL_ENDPTCTRL1 22 TXR same as HW_USBCTRL_ENDPTCTRL1 21 TXI same as HW_USBCTRL_ENDPTCTRL1 20 RSVD5 same as HW_USBCTRL_ENDPTCTRL1 19-18 TXT same as HW_USBCTRL_ENDPTCTRL1 17 TXD same as HW_USBCTRL_ENDPTCTRL1 16 TXS same as HW_USBCTRL_ENDPTCTRL1 15-8 RSVD3 same as HW_USBCTRL_ENDPTCTRL1 7 RXE same as HW_USBCTRL_ENDPTCTRL1 6 RXR same as HW_USBCTRL_ENDPTCTRL1 5 RXI same as HW_USBCTRL_ENDPTCTRL1 4 RSVD2 same as HW_USBCTRL_ENDPTCTRL1 3-2 RXT same as HW_USBCTRL_ENDPTCTRL1 1 RXD same as HW_USBCTRL_ENDPTCTRL1 0 RXS same as HW_USBCTRL_ENDPTCTRL1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2387 Programmable Registers 31.3.45 Endpoint Control 5 Register (HW_USBCTRL_ENDPTCTRL5) Register HW_USBCTRL_ENDPTCTRL5 is the control register for endpoint 5 in a device. See the bit field defintions and descriptions of register HW_USBCTRL_ENDPTCTRL1. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/direction. Address: 8008_0000h base + 1D4h offset = 8008_01D4h 31 30 29 28 27 26 25 24 23 22 21 TXE TXR TXI RSVD6 R 20 19 18 17 16 TXD TXS RSVD5 Bit TXT W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE RXR RXI RXD RXS 0 0 0 0 0 RSVD2 Reset RSVD3 R RXT W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTCTRL5 field descriptions Field 31-24 RSVD6 Description same as HW_USBCTRL_ENDPTCTRL1 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2388 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTCTRL5 field descriptions (continued) Field Description 23 TXE same as HW_USBCTRL_ENDPTCTRL1 22 TXR same as HW_USBCTRL_ENDPTCTRL1 21 TXI same as HW_USBCTRL_ENDPTCTRL1 20 RSVD5 same as HW_USBCTRL_ENDPTCTRL1 19-18 TXT same as HW_USBCTRL_ENDPTCTRL1 17 TXD same as HW_USBCTRL_ENDPTCTRL1 16 TXS same as HW_USBCTRL_ENDPTCTRL1 15-8 RSVD3 same as HW_USBCTRL_ENDPTCTRL1 7 RXE same as HW_USBCTRL_ENDPTCTRL1 6 RXR same as HW_USBCTRL_ENDPTCTRL1 5 RXI same as HW_USBCTRL_ENDPTCTRL1 4 RSVD2 same as HW_USBCTRL_ENDPTCTRL1 3-2 RXT same as HW_USBCTRL_ENDPTCTRL1 1 RXD same as HW_USBCTRL_ENDPTCTRL1 0 RXS same as HW_USBCTRL_ENDPTCTRL1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2389 Programmable Registers 31.3.46 Endpoint Control 6 Register (HW_USBCTRL_ENDPTCTRL6) Register HW_USBCTRL_ENDPTCTRL6 is the control register for endpoint 6 in a device. See the bit field defintions and descriptions of register HW_USBCTRL_ENDPTCTRL1. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/direction. Address: 8008_0000h base + 1D8h offset = 8008_01D8h 31 30 29 28 27 26 25 24 23 22 21 TXE TXR TXI RSVD6 R 20 19 18 17 16 TXD TXS RSVD5 Bit TXT W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE RXR RXI RXD RXS 0 0 0 0 0 RSVD2 Reset RSVD3 R RXT W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTCTRL6 field descriptions Field 31-24 RSVD6 Description same as HW_USBCTRL_ENDPTCTRL1 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2390 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTCTRL6 field descriptions (continued) Field Description 23 TXE same as HW_USBCTRL_ENDPTCTRL1 22 TXR same as HW_USBCTRL_ENDPTCTRL1 21 TXI same as HW_USBCTRL_ENDPTCTRL1 20 RSVD5 same as HW_USBCTRL_ENDPTCTRL1 19-18 TXT same as HW_USBCTRL_ENDPTCTRL1 17 TXD same as HW_USBCTRL_ENDPTCTRL1 16 TXS same as HW_USBCTRL_ENDPTCTRL1 15-8 RSVD3 same as HW_USBCTRL_ENDPTCTRL1 7 RXE same as HW_USBCTRL_ENDPTCTRL1 6 RXR same as HW_USBCTRL_ENDPTCTRL1 5 RXI same as HW_USBCTRL_ENDPTCTRL1 4 RSVD2 same as HW_USBCTRL_ENDPTCTRL1 3-2 RXT same as HW_USBCTRL_ENDPTCTRL1 1 RXD same as HW_USBCTRL_ENDPTCTRL1 0 RXS same as HW_USBCTRL_ENDPTCTRL1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2391 Programmable Registers 31.3.47 Endpoint Control 7 Register (HW_USBCTRL_ENDPTCTRL7) Register HW_USBCTRL_ENDPTCTRL7 is the control register for endpoint 7 in a device. See the bit field defintions and descriptions of register HW_USBCTRL_ENDPTCTRL1. CAUTION: If one endpoint direction is enabled and the paired endpoint of opposite direction is disabled then the unused direction type must be changed from the default control-type to any other type (i.e., bulk type). Leaving an unconfigured endpoint control will cause undefined behavior for the data PID tracking on the active endpoint/direction. Address: 8008_0000h base + 1DCh offset = 8008_01DCh 31 30 29 28 27 26 25 24 23 22 21 TXE TXR TXI RSVD6 R 20 19 18 17 16 TXD TXS RSVD5 Bit TXT W Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXE RXR RXI RXD RXS 0 0 0 0 0 RSVD2 Reset RSVD3 R RXT W Reset 0 0 0 0 0 0 0 0 0 0 0 HW_USBCTRL_ENDPTCTRL7 field descriptions Field 31-24 RSVD6 Description same as HW_USBCTRL_ENDPTCTRL1 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2392 Freescale Semiconductor, Inc. Chapter 31 USB High-Speed On-the-Go Host Device Controller HW_USBCTRL_ENDPTCTRL7 field descriptions (continued) Field Description 23 TXE same as HW_USBCTRL_ENDPTCTRL1 22 TXR same as HW_USBCTRL_ENDPTCTRL1 21 TXI same as HW_USBCTRL_ENDPTCTRL1 20 RSVD5 same as HW_USBCTRL_ENDPTCTRL1 19-18 TXT same as HW_USBCTRL_ENDPTCTRL1 17 TXD same as HW_USBCTRL_ENDPTCTRL1 16 TXS same as HW_USBCTRL_ENDPTCTRL1 15-8 RSVD3 same as HW_USBCTRL_ENDPTCTRL1 7 RXE same as HW_USBCTRL_ENDPTCTRL1 6 RXR same as HW_USBCTRL_ENDPTCTRL1 5 RXI same as HW_USBCTRL_ENDPTCTRL1 4 RSVD2 same as HW_USBCTRL_ENDPTCTRL1 3-2 RXT same as HW_USBCTRL_ENDPTCTRL1 1 RXD same as HW_USBCTRL_ENDPTCTRL1 0 RXS same as HW_USBCTRL_ENDPTCTRL1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2393 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2394 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.1 USB PHY Overview The chip contains 2 integrated USB 2.0 PHY macrocells capable of connecting to USB host/device systems at the USB low-speed (LS) rate of 1.5 Mbits/s, full-speed (FS) rate of 12 Mbits/s or at the USB 2.0 high-speed (HS) rate of 480 Mbits/s. See Figure 32-1 for a block diagram of the PHY. The integrated PHY provides a standard UTM interface. The USB_n_DN and USB_n_DP pins connect directly to a USB connector. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2395 SRAM ARM APBX Bridge Crystal Oscillator UTMI Digital Digital TX Digital RX Analog RX/TX DCLK System PLL Bus Interface AHB EMI USB 2.0 Controller Operation USB_DP USB_DN Integrated USB 2.0 PHY (UTMI Macrocell) Figure 32-1. USB 2.0 PHY Block Diagram USBPHY1 is the PHY interface for USB OTG controller; USBPHY2 is the PHY interface for USB Host1 controller. The following subsections describe the external interfaces, internal interfaces, major blocks, and programmable registers that comprise the integrated USB 2.0 PHY. 32.2 Operation The UTM provides a 16-bit interface to the USB controller. This interface is clocked at 30 MHz. * The digital portions of the USBPHY block include the UTMI, digital transmitter, digital receiver, and the programmable registers. * The analog transceiver section comprises an analog receiver and an analog transmitter, as shown in Figure 32-2. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2396 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.2.1 UTMI The UTMI block handles the line_state bits, reset buffering, suspend distribution, transceiver speed selection, and transceiver termination selection. The PLL supplies a 120 MHz signal to all of the digital logic. The UTMI block does a final divide-by-four to develop the 30 MHz clock used in the interface. 32.2.2 Digital Transmitter The digital transmitter receives the 16-bit transmit data from the USB controller and handles the tx_valid, tx_validh and tx_ready handshake. In addition, it contains the transmit serializer that converts the 16-bit parallel words at 30 MHz to a single bitstream at 480 Mbit for high-speed or 12 Mbit for full-speed or 1.5 Mbit for low-speed. It does this while implementing the bit-stuffing algorithm and the NRZI encoder that are used to remove the DC component from the serial bitstream. The output of this encoder is sent to the low-speed (LS), full-speed (FS) or high-speed (HS) drivers in the analog transceiver section's transmitter block. 32.2.3 Digital Receiver The digital receiver receives the raw serial bitstream from the low speed (LS) differential transceiver, full speed (FS) differential transceiver, and a 9X, 480 MHz sampled data from the high speed (HS) differential transceiver. As the phase of the USB host transmitter shifts relative to the local PLL, the receiver section's HS DLL tracks these changes to give a reliable sample of the incoming 480 Mbit/s bitstream. Since this sample point shifts relative to the PLL phase used by the digital logic, a rate-matching elastic buffer is provided to cross this clock domain boundary. Once the bitstream is in the local clock domain, an NRZI decoder and bit unstuffer restore the original payload data bitstream and pass it to a deserializer and holding register. The receive state machine handles the rx_valid, rx_validh, and handshake with the USB controller. The handshake is not interlocked, in that there is no rx_ready signal coming from the controller. The controller must take each 16-bit value as presented by the PHY. The receive state machine provides an rx_active signal to the controller that indicates when it is inside a valid packet (SYNC detected, and so on). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2397 Operation 32.2.4 Analog Receiver The analog receiver comprises five differential receivers, two single-ended receivers, and a 9X, 480 MHz HS data sampling module , as shown in the figure below and described further in this section. Transmitter RPU Enable HS Current Source Enable VDDIO (3.3V) HS Drive Enable HS Data Drive LS/FS Driver Output Enable 1500 LS/FS DataDrive Assert SE0 FS Edge Mode Select Test and discrete power-down controls USB_n_DP HS Differential RCVR USB Cable USB_n_DN Squelch 15000 LS/FS Differential RCVR 15000 HS_Disconnect_Detect USB_Plugged_In_Detect Single-Ended Detector SE_DP Single-Ended Detector SE_DM Receiver Figure 32-2. USB 2.0 PHY Analog Transceiver Block Diagram 32.2.4.1 HS Differential Receiver The high-speed differential receiver is both a differential analog receiver and threshold comparator. Its output is a one if the differential signal is greater than a 0-V threshold. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2398 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) Otherwise, its output is 0. Its purpose is to discriminate the 400-mV differential voltage resulting from the high-speed drivers current flow into the dual 45 terminations found on each pin of the differential pair. The envelope or squelch detector, described below, ensures that the differential signal has sufficient magnitude to be valid. The HS differential receiver tolerates up to 500 mV of common mode offset. 32.2.4.2 Squelch Detector The squelch detector is a differential analog receiver and threshold comparator. Its output is 1, if the differential magnitude is less than a nominal 100 mV threshold. Otherwise, its output is 0. Its purpose is to invalidate the HS differential receiver when the incoming signal is simply too low to receive reliably. 32.2.4.3 LS/FS Differential Receiver The low-speed/full-speed differential receiver is both a differential analog receiver and threshold comparator. The crossover voltage falls between 1.3 V and 2.0 V. Its output is 1, when the USB_n_DP line is above the crossover point and the USB_n_DN line is below the crossover point. The digital receiver section decodes the receiver data into J or K state according to the speed. 32.2.4.4 HS Disconnect Detector It is a differential analog receiver and threshold comparator. It outputs high when differential magnitude is greater than a nominal 575-mV threshold. Otherwise, it outputs low. 32.2.4.5 USB Plugged-In Detector The USB plugged-in detector looks for both USB_n_DP and USB_n_DN to be high. There is a pair of large on-chip pullup resistors (200 K) that hold both USB_n_DP and USB_n_DN high when the USB cable is not attached. The USB plugged-in detector signals a 0 in this case. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2399 Operation When operating in device mode, the upstream port in host/hub interface contains a 15 K pulldown resistor which could easily override the 200 K pullup resistor. When plugged in, at least one signal in the pair will be low, which will force the plugged-in detector's output high. 32.2.4.6 Single-Ended USB_DP Receiver The single-ended USB_n_DP receiver output is high whenever the USB_n_DP input is above its nominal 1.8 V threshold. 32.2.4.7 Single-Ended USB_DN Receiver The single-ended USB_n_DN receiver output is high whenever the USB_n_DN input is above its nominal 1.8 V threshold. 32.2.4.8 9X Oversample Module The 9X oversample module uses nine identically spaced phases of the 480 MHz clock to sample a high speed bit data. The squelch signal is sampled only 1X. 32.2.5 Analog Transmitter The analog transmitter comprises two differential drivers: one for high-speed signaling and one for full-speed signaling. It also contains the switchable 1.5 K pullup resistor. See Figure 32-2. 32.2.5.1 Switchable High-Speed 45 Termination Resistors High-speed current mode differential signaling requires good 90 differential termination at each end of the USB cable. This results from switching in 45 terminating resistors from each signal line to ground at each end of the cable. Because each signal is parallel terminated with 45 at each end, each driver sees a 22.5 load. This load impedance is much too low for full-speed signaling levels--hence the need for switchable high-speed terminating resistors. Switchable trimming resistors are provided to tune the actual termination resistance of each device, as shown in Figure i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2400 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32-3. The HW_USBPHY_TX_TXCAL45DP bit field, for example, allows one of 16 trimming resistor values to be placed in parallel with the 45 terminator on the USB_n_DP signal. 32.2.5.2 Low-Speed/Full-Speed Differential Driver The low-speed/full-speed differential drivers are essentially low-impedance pulldown devices that are switched in a differential mode for low-speed or full-speed signaling, that is, either one or the other device is turned on to signal the "J" state or the "K" state. 32.2.5.3 High-Speed Differential Driver The high-speed differential driver receives a 17.78 mA current from the constant current source (Iref) and essentially steers it down either the USB_DP signal or the USB_DN signal or alternatively to ground. This current will produce approximately a 400 mV drop across the 22.5 termination seen by the driver when it is steered onto one of the signal lines. The approximately 17.78 mA current source is referenced back to the integrated voltage-band-gap (Vbg) circuit. The Iref, Ibias, and V to I circuits are shared with the integrated battery charger. 32.2.5.4 Switchable 1.5K USB_DP Pullup Resistor This product contains a switchable 1.5 K pullup resistor on the USB_n_DP signal. This resistor is switched on to indicate to the host/hub controller that a full-speed-capable device is on the USB cable, powered on, and ready. This resistor is switched off at power-on reset so the host does not recognize a USB device until the processor software enables the announcement of a full-speed device. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2401 Operation 32.2.5.5 Switchable 15K USB_DP Pulldown Resistor This product contains a switchable 15 K pulldown resistor on both USB_n_DP and USB_n_DN signals. This is used in host mode to indicate to the device controller that a host is present. To External Temperature Sensor To Battery Charger Vbg Ibias V to I HW_USBPHY_TX: D_CAL Current trim 17.78mA HW_USBPHY_PWD: TXPWDV2I, TXPWDIBIAS current switch current switch Current Steering data_p,hs_xcvr data_n,hs_xcvr USB_n_DP USB Cable USB_n_DN 45 45 LS/FS DRVR LS/FS DRVR HW_USBPHY_TX_ TXCAL45DP HW_USBPHY_TX_ TXCAL45DN HW_USBPHY_TX: TXENCAL45DP,DN data_p,data_n, fs_hiz, hs_term, tx_ls_en Figure 32-3. USB 2.0 PHY Transmitter Block Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2402 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.2.6 Recommended Register Configuration for USB Certification The register settings in this section are recommended for passing USB certification. The following settings lower the J/K levels to certifiable limits: HW_USBPHY_TX_TXCAL45DP = 0x0 HW_USBPHY_TX_TXCAL45DN = 0x0 HW_USBPHY_TX_D_CAL = 0x7 32.3 USB PHY Memory Map/Register Definition USBPHY Hardware Register Format Summary USBPHY memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 0 USB PHY Power-Down Register (USBPHY_PWD) 32 R/W 001E_1C00h 32.3.1/2405 4 USB PHY Power-Down Register (USBPHY_PWD_SET) 32 R/W 001E_1C00h 32.3.1/2405 8 USB PHY Power-Down Register (USBPHY_PWD_CLR) 32 R/W 001E_1C00h 32.3.1/2405 C USB PHY Power-Down Register (USBPHY_PWD_TOG) 32 R/W 001E_1C00h 32.3.1/2405 10 USB PHY Transmitter Control Register (USBPHY_TX) 32 R/W 1006_0607h 32.3.2/2407 14 USB PHY Transmitter Control Register (USBPHY_TX_SET) 32 R/W 1006_0607h 32.3.2/2407 18 USB PHY Transmitter Control Register (USBPHY_TX_CLR) 32 R/W 1006_0607h 32.3.2/2407 1C USB PHY Transmitter Control Register (USBPHY_TX_TOG) 32 R/W 1006_0607h 32.3.2/2407 20 USB PHY Receiver Control Register (USBPHY_RX) 32 R/W 0000_0000h 32.3.3/2408 24 USB PHY Receiver Control Register (USBPHY_RX_SET) 32 R/W 0000_0000h 32.3.3/2408 28 USB PHY Receiver Control Register (USBPHY_RX_CLR) 32 R/W 0000_0000h 32.3.3/2408 2C USB PHY Receiver Control Register (USBPHY_RX_TOG) 32 R/W 0000_0000h 32.3.3/2408 30 USB PHY General Control Register (USBPHY_CTRL) 32 R/W C020_0000h 32.3.4/2410 34 USB PHY General Control Register (USBPHY_CTRL_SET) 32 R/W C020_0000h 32.3.4/2410 38 USB PHY General Control Register (USBPHY_CTRL_CLR) 32 R/W C020_0000h 32.3.4/2410 3C USB PHY General Control Register (USBPHY_CTRL_TOG) 32 R/W C020_0000h 32.3.4/2410 40 USB PHY Status Register (USBPHY_STATUS) 32 R/W 0000_0000h 50 USB PHY Debug Register (USBPHY_DEBUG) 32 R/W 7F18_0000h 32.3.6/2415 54 USB PHY Debug Register (USBPHY_DEBUG_SET) 32 R/W 7F18_0000h 32.3.6/2415 32.3.5/2413 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2403 USB PHY Memory Map/Register Definition USBPHY memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 58 USB PHY Debug Register (USBPHY_DEBUG_CLR) 32 R/W 7F18_0000h 32.3.6/2415 5C USB PHY Debug Register (USBPHY_DEBUG_TOG) 32 R/W 7F18_0000h 32.3.6/2415 60 UTMI Debug Status Register 0 (USBPHY_DEBUG0_STATUS) 32 R 0000_0000h 32.3.7/2417 70 UTMI Debug Status Register 1 (USBPHY_DEBUG1) 32 R/W 0000_1000h 32.3.8/2418 74 UTMI Debug Status Register 1 (USBPHY_DEBUG1_SET) 32 R/W 0000_1000h 32.3.8/2418 78 UTMI Debug Status Register 1 (USBPHY_DEBUG1_CLR) 32 R/W 0000_1000h 32.3.8/2418 7C UTMI Debug Status Register 1 (USBPHY_DEBUG1_TOG) 32 R/W 0000_1000h 32.3.8/2418 80 UTMI RTL Version (USBPHY_VERSION) 32 R 0402_0000h 32.3.9/2419 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2404 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.3.1 USB PHY Power-Down Register (USBPHY_PWDn) The USB PHY Power-Down Register provides overall control of the PHY power state. Before programming this register, the PHY clocks must be enabled in registers USBPHYx_CTRLn and CCM_ANALOG_USBPHYx_PLL_480_CTRLn. Address: 0h base + 0h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 RXPWDRX RXPWDDIFF RXPWD1PT1 RXPWDENV RSVD 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 TXPWDIBIAS TXPWDFS RSVD0 TXPWDV2I RSVD1 R 1 1 1 W Reset 16 0 W Bit 17 RSVD2 R Reset 18 0 0 0 0 0 0 0 0 0 USBPHY_PWDn field descriptions Field 31-21 RSVD2 20 RXPWDRX Description Reserved. 0 = Normal operation. 1 = Power-down the entire USB PHY receiver block except for the full-speed differential receiver. Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHYx_CTRL is enabled. 19 RXPWDDIFF 0 = Normal operation. 1 = Power-down the USB high-speed differential receiver. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2405 USB PHY Memory Map/Register Definition USBPHY_PWDn field descriptions (continued) Field Description Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHYx_CTRL is enabled. 18 RXPWD1PT1 0 = Normal operation. 1 = Power-down the USB full-speed differential receiver. Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHYx_CTRL is enabled. 17 RXPWDENV 0 = Normal operation. 1 = Power-down the USB high-speed receiver envelope detector (squelch signal). Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHYx_CTRL is enabled. 16-13 RSVD1 12 TXPWDV2I Reserved. 0 = Normal operation. 1 = Power-down the USB PHY transmit V-to-I converter and the current mirror. Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHYx_CTRL is enabled. Note that these circuits are shared with the battery charge circuit. Setting this to 1 does not power-down these circuits, unless the corresponding bit in the battery charger is also set for power-down. 11 TXPWDIBIAS 0 = Normal operation. 1 = Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path. Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHYx_CTRL is enabled. Note that these circuits are shared with the battery charge circuit. Setting this bit to 1 does not powerdown these circuits, unless the corresponding bit in the battery charger is also set for power-down. 10 TXPWDFS 0 = Normal operation. 1 = Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output. Note that this bit will be auto cleared if there is USB wakeup event while ENAUTOCLR_PHY_PWD bit of USBPHYx_CTRL is enabled. RSVD0 Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2406 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.3.2 USB PHY Transmitter Control Register (USBPHY_TXn) The USB PHY Transmitter Control Register handles the transmit controls. Address: 0h base + 10h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 RSVD5 R Bit 25 24 23 22 21 20 19 RSVD2 18 17 16 TXCAL45DP 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RSVD1 W Reset 26 USBPHY_TX_ EDGECTRL W Reset 27 0 0 0 TXCAL45DN 0 0 1 1 RSVD0 0 0 0 0 D_CAL 0 0 1 1 1 USBPHY_TXn field descriptions Field 31-29 RSVD5 28-26 USBPHY_TX_ EDGECTRL 25-20 RSVD2 19-16 TXCAL45DP 15-12 RSVD1 11-8 TXCAL45DN Description Reserved. Controls the edge-rate of the current sensing transistors used in HS transmit. NOT FOR CUSTOMER USE. Reserved. Decode to select a 45-Ohm resistance to the USB_DP output pin. Maximum resistance = 0000. Resistance is centered by design at 0110. Reserved. Note: This bit should remain clear. Decode to select a 45-Ohm resistance to the USB_DN output pin. Maximum resistance = 0000. Resistance is centered by design at 0110. 7-4 RSVD0 Reserved. D_CAL Resistor Trimming Code: Note: This bit should remain clear. 0000 = 0.16% 0111 = Nominal 1111 = +25% i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2407 USB PHY Memory Map/Register Definition 32.3.3 USB PHY Receiver Control Register (USBPHY_RXn) The USB PHY Receiver Control Register handles receive path controls. Address: 0h base + 20h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 20 19 18 17 16 RXDBYPASS RSVD1 W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD0 Bit 21 RSVD2 R Reset 22 RSVD1 R DISCONADJ ENVADJ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_RXn field descriptions Field 31-23 RSVD2 22 RXDBYPASS Description Reserved. 0 = Normal operation. 1 = Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver. This test mode is intended for lab use only. 21-7 RSVD1 Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2408 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) USBPHY_RXn field descriptions (continued) Field 6-4 DISCONADJ Description The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0.57500 V 001 = Trip-Level Voltage is 0.56875 V 010 = Trip-Level Voltage is 0.58125 V 011 = Trip-Level Voltage is 0.58750 V 1XX = Reserved 3 RSVD0 ENVADJ Reserved. The ENVADJ field adjusts the trip point for the envelope detector. 000 = Trip-Level Voltage is 0.12500 V 001 = Trip-Level Voltage is 0.10000 V 010 = Trip-Level Voltage is 0.13750 V 011 = Trip-Level Voltage is 0.15000 V 1XX = Reserved i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2409 USB PHY Memory Map/Register Definition 32.3.4 USB PHY General Control Register (USBPHY_CTRLn) The USB PHY General Control Register handles OTG and Host controls. This register also includes interrupt enables and connectivity detect enables and results. Address: 0h base + 30h offset + (4d x i), where i=0d to 3d ENAUTOCLR_PHY_PWD ENAUTOCLR_CLKGATE RSVD0 WAKEUP_IRQ ENIRQWAKEUP 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENDEVPLUGINDETECT HOSTDISCONDETECT_IRQ ENIRQHOSTDISCON ENHOSTDISCONDETECT ENOTG_ID_CHG_IRQ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R HOST_FORCE_LS_SE0 ENDPDMCHG_WKUP 16 DEVPLUGIN_POLARITY 17 ENIDCHG_WKUP 18 OTG_ID_CHG_IRQ 19 ENVBUSCHG_WKUP 20 ENOTGIDDETECT 21 FSDLL_RST_EN 22 RESUMEIRQSTICKY 23 ENIRQRESUMEDETECT 24 RESUME_IRQ 25 ENIRQDEVPLUGIN 26 DEVPLUGIN_IRQ OTG_ID_VALUE 27 DATA_ON_LRADC 28 CLKGATE UTMI_SUSPENDM 29 ENUTMILEVEL2 30 SFTRST 31 ENUTMILEVEL3 Bit RSVD1 W Reset Bit R W Reset i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2410 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) USBPHY_CTRLn field descriptions Field Description 31 SFTRST Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers. Set to 0 to release the PHY from reset. 30 CLKGATE Gate UTMI Clocks. Clear to 0 to run clocks. Set to 1 to gate clocks. Set this to save power while the USB is not actively being used. Configuration state is kept while the clock is gated. Note this bit can be auto-cleared if there is any wakeup event when USB is suspended while ENAUTOCLR_CLKGATE bit of USBPHYx_CTRL is enabled. 29 UTMI_SUSPENDM Used by the PHY to indicate a powered-down state. If all the power-down bits in the USBPHYx_PWD are enabled, UTMI_SUSPENDM will be 0, otherwise 1. UTMI_SUSPENDM is negative logic, as required by the UTMI specification. 28 HOST_FORCE_LS_SE0 Forces the next FS packet that is transmitted to have a EOP with LS timing. This bit is used in host mode for the resume sequence. After the packet is transferred, this bit is cleared. The design can use this function to force the LS SE0 or use the USBPHYx_CTRL_UTMI_SUSPENDM to trigger this event when leaving suspend. This bit is used in conjunction with USBPHYx_DEBUG_HOST_RESUME_DEBUG. 27 OTG_ID_VALUE Almost same as OTGID_STATUS in USBPHYx_STATUS Register. The only difference is that OTG_ID_VALUE has debounce logic to filter the glitches on ID Pad. 26-25 RSVD1 Reserved. 24 FSDLL_RST_EN Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. 23 ENVBUSCHG_WKUP 22 ENIDCHG_WKUP Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. Enables the feature to wakeup USB if ID is toggled when USB is suspended. 21 ENDPDMCHG_WKUP Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended. This bit is enabled by default. 20 ENAUTOCLR_PHY_PWD Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended. This should be enabled if needs to support auto wakeup without S/W's interaction. 19 ENAUTOCLR_CLKGATE Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended. This should be enabled if needs to support auto wakeup without S/W's interaction. 18 RSVD0 Reserved. 17 WAKEUP_IRQ Indicates that there is a wakeup event. Reset this bit by writing a 1 to the clear address space and not by a general write. 16 ENIRQWAKEUP Enables interrupt for the wakeup events. 15 ENUTMILEVEL3 Enables UTMI+ Level3. This should be enabled if needs to support external FS Hub with LS device connected 14 ENUTMILEVEL2 Enables UTMI+ Level2. This should be enabled if needs to support LS device 13 DATA_ON_LRADC Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. 12 DEVPLUGIN_IRQ Indicates that the device is connected. Reset this bit by writing a 1 to the clear address space and not by a general write. 11 ENIRQDEVPLUGIN Enables interrupt for the detection of connectivity to the USB line. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2411 USB PHY Memory Map/Register Definition USBPHY_CTRLn field descriptions (continued) Field Description 10 RESUME_IRQ Indicates that the host is sending a wake-up after suspend. This bit is also set on a reset during suspend. Use this bit to wake up from suspend for either the resume or the reset case. Reset this bit by writing a 1 to the clear address space and not by a general write. 9 ENIRQRESUMEDETECT Enables interrupt for detection of a non-J state on the USB line. This should only be enabled after the device has entered suspend mode. 8 RESUMEIRQSTICKY Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it. Set to 0, RESUME_IRQ only set during the wake-up period. 7 ENOTGIDDETECT Enables circuit to detect resistance of MiniAB ID pin. 6 OTG_ID_CHG_IRQ OTG ID change interrupt. Indicates the value of ID pin changed. 5 DEVPLUGIN_POLARITY For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in. If set to 1, then it trips the interrupt if the device is unplugged. 4 ENDEVPLUGINDETECT For device mode, enables 200-KOhm pullups for detecting connectivity to the host. 3 HOSTDISCONDETECT_ IRQ Indicates that the device has disconnected in high-speed mode. Reset this bit by writing a 1 to the clear address space and not by a general write. 2 ENIRQHOSTDISCON Enables interrupt for detection of disconnection to Device when in high-speed host mode. This should be enabled after ENDEVPLUGINDETECT is enabled. 1 For host mode, enables high-speed disconnect detector. This signal allows the override of ENHOSTDISCONDETECT enabling the detection that is normally done in the UTMI controller. The UTMI controller enables this circuit whenever the host sends a start-of-frame packet. SW shall set this bit when it found the high-speed device is connected, suggested during bus reset, after found high-speed device in USB_PORTSC1.PSPD). SW shall make sure this bit is not set at the end of resume, otherwise a wrong disconnect status may be detected. Suggest clear it after set USB_PORTSC1.SUSP, set it again after resume is ended(USB_PORTSC1.FPR==0). 0 ENOTG_ID_CHG_IRQ Enable OTG_ID_CHG_IRQ. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2412 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.3.5 USB PHY Status Register (USBPHY_STATUS) The USB PHY Status Register holds results of IRQ and other detects. Address: 0h base + 40h offset = 40h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSVD4 R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2413 RSVD4 R 10 9 0 0 8 7 6 0 0 5 4 RSVD1 3 2 HOSTDISCONDETECT_STATUS 11 DEVPLUGIN_STATUS 12 RSVD2 13 OTGID_STATUS 14 RSVD3 15 Bit RESUME_STATUS USB PHY Memory Map/Register Definition 1 0 RSVD0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_STATUS field descriptions Field Description 31-11 RSVD4 Reserved. 10 RESUME_STATUS Indicates that the host is sending a wake-up after suspend and has triggered an interrupt. 9 RSVD3 Reserved. 8 OTGID_STATUS Indicates the results of ID pin on MiniAB plug. False (0) is when ID resistance is less than Ra_Plug_ID, indicating host (A) side. True (1) is when ID resistance is greater than Rb_Plug_ID, indicating device (B) side. 7 RSVD2 Reserved. 6 DEVPLUGIN_STATUS 5-4 RSVD1 Indicates that the device has been connected on the USB_DP and USB_DM lines. Reserved. 3 Indicates that the device has disconnected while in high-speed host mode. HOSTDISCONDETECT_ STATUS RSVD0 Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2414 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.3.6 USB PHY Debug Register (USBPHY_DEBUGn) This register is used to debug the USB PHY. Address: 0h base + 50h offset + (4d x i), where i=0d to 3d 31 29 25 24 23 22 21 20 19 18 17 16 0 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OTGIDPIOLOCK 26 DEBUG_INTERFACE_HOLD 27 HOST_RESUME_DEBUG 28 CLKGATE 0 0 0 0 SQUELCHRESETLENGTH RSVD2 ENSQUELCHRESET R 30 RSVD3 Bit SQUELCHRESETCOUNT W RSVD1 RSVD0 ENTX2RXCOUNT R W Reset 0 0 0 0 TX2RXCOUNT 0 0 0 0 0 0 0 HSTPULLDOWN Bit ENHSTPULLDOWN Reset 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2415 USB PHY Memory Map/Register Definition USBPHY_DEBUGn field descriptions Field Description 31 RSVD3 Reserved. 30 CLKGATE Gate Test Clocks. Clear to 0 for running clocks. Set to 1 to gate clocks. Set this to save power while the USB is not actively being used. Configuration state is kept while the clock is gated. 29 HOST_RESUME_DEBUG Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. 28-25 Duration of RESET in terms of the number of 480-MHz cycles. SQUELCHRESETLENGTH 24 ENSQUELCHRESET 23-21 RSVD2 Set bit to allow squelch to reset high-speed receive. Reserved. 20-16 SQUELCHRESETCOUNT 15-13 RSVD1 Delay in between the detection of squelch to the reset of high-speed RX. Reserved. 12 ENTX2RXCOUNT Set this bit to allow a countdown to transition in between TX and RX. 11-8 TX2RXCOUNT Delay in between the end of transmit to the beginning of receive. This is a Johnson count value and thus will count to 8. 7-6 RSVD0 Reserved. 5-4 ENHSTPULLDOWN Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown. Set bit 4 to 1 to override the control of the USB_DM 15-KOhm pulldown. Clear to 0 to disable. 3-2 HSTPULLDOWN Set bit 3 to 1 to pull down 15-KOhm on USB_DP line. Set bit 2 to 1 to pull down 15-KOhm on USB_DM line. Clear to 0 to disable. 1 DEBUG_INTERFACE_ HOLD 0 OTGIDPIOLOCK Use holding registers to assist in timing for external UTMI interface. Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value. This is to save power for the comparators that are used to determine the ID status. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2416 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.3.7 UTMI Debug Status Register 0 (USBPHY_DEBUG0_STATUS) The UTMI Debug Status Register 0 holds multiple views for counters and status of state machines. This is used in conjunction with the USBPHYx_DEBUG1_DBG_ADDRESS field to choose which function to view. The default is described in the bit fields below and is used to count errors. Address: 0h base + 60h offset = 60h Bit 31 30 29 28 27 26 SQUELCH_COUNT R 25 24 23 22 21 20 19 18 17 16 15 14 13 12 UTMI_RXERROR_FAIL_COUNT 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 LOOP_BACK_FAIL_COUNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DEBUG0_STATUS field descriptions Field 31-26 SQUELCH_ COUNT Description Running count of the squelch reset instead of normal end for HS RX. 25-16 UTMI_ RXERROR_ FAIL_COUNT Running count of the UTMI_RXERROR. LOOP_BACK_ FAIL_COUNT Running count of the failed pseudo-random generator loopback. Each time entering testmode, counter goes to 900D and will count up for every detected packet failure in digital/analog loopback tests. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2417 USB PHY Memory Map/Register Definition 32.3.8 UTMI Debug Status Register 1 (USBPHY_DEBUG1n) Chooses the muxing of the debug register to be shown in USBPHYx_DEBUG0_STATUS. Address: 0h base + 70h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 RSVD1 R ENTA ILADJ VD RSVD0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 USBPHY_DEBUG1n field descriptions Field 31-15 RSVD1 14-13 ENTAILADJVD Description Reserved. Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% RSVD0 Reserved. Note: This bit should remain clear. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2418 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.3.9 UTMI RTL Version (USBPHY_VERSION) Fields for RTL Version. Address: 0h base + 80h offset = 80h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 USBPHY_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. 32.4 USB Analog Memory Map/Register Definition USB_ANALOG memory map Absolute address (hex) 0 Register name Width Access (in bits) Reset value Section/ page Chip Silicon Version (USB_ANALOG_DIGPROG) 32 R 0000_0000h 32.4.1/2421 1A0 USB VBUS Detect Register (USB_ANALOG_USB1_VBUS_DETECT) 32 R/W 0010_0004h 32.4.2/2422 1A4 USB VBUS Detect Register (USB_ANALOG_USB1_VBUS_DETECT_SET) 32 R/W 0010_0004h 32.4.2/2422 1A8 USB VBUS Detect Register (USB_ANALOG_USB1_VBUS_DETECT_CLR) 32 R/W 0010_0004h 32.4.2/2422 1AC USB VBUS Detect Register (USB_ANALOG_USB1_VBUS_DETECT_TOG) 32 R/W 0010_0004h 32.4.2/2422 1B0 USB Charger Detect Register (USB_ANALOG_USB1_CHRG_DETECT) 32 R/W 0000_0000h 32.4.3/2423 1B4 USB Charger Detect Register (USB_ANALOG_USB1_CHRG_DETECT_SET) 32 R/W 0000_0000h 32.4.3/2423 1B8 USB Charger Detect Register (USB_ANALOG_USB1_CHRG_DETECT_CLR) 32 R/W 0000_0000h 32.4.3/2423 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2419 USB Analog Memory Map/Register Definition USB_ANALOG memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 1BC USB Charger Detect Register (USB_ANALOG_USB1_CHRG_DETECT_TOG) 32 R/W 0000_0000h 32.4.3/2423 1C0 USB VBUS Detect Status Register (USB_ANALOG_USB1_VBUS_DETECT_STAT) 32 R 0000_0000h 32.4.4/2425 1D0 USB Charger Detect Status Register (USB_ANALOG_USB1_CHRG_DETECT_STAT) 32 R 0000_0000h 32.4.5/2427 1F0 USB Misc Register (USB_ANALOG_USB1_MISC) 32 R/W 0000_0002h 32.4.6/2428 1F4 USB Misc Register (USB_ANALOG_USB1_MISC_SET) 32 R/W 0000_0002h 32.4.6/2428 1F8 USB Misc Register (USB_ANALOG_USB1_MISC_CLR) 32 R/W 0000_0002h 32.4.6/2428 1FC USB Misc Register (USB_ANALOG_USB1_MISC_TOG) 32 R/W 0000_0002h 32.4.6/2428 200 USB VBUS Detect Register (USB_ANALOG_USB2_VBUS_DETECT) 32 R/W 0010_0004h 32.4.7/2429 204 USB VBUS Detect Register (USB_ANALOG_USB2_VBUS_DETECT_SET) 32 R/W 0010_0004h 32.4.7/2429 208 USB VBUS Detect Register (USB_ANALOG_USB2_VBUS_DETECT_CLR) 32 R/W 0010_0004h 32.4.7/2429 20C USB VBUS Detect Register (USB_ANALOG_USB2_VBUS_DETECT_TOG) 32 R/W 0010_0004h 32.4.7/2429 210 USB Charger Detect Register (USB_ANALOG_USB2_CHRG_DETECT) 32 R/W 0000_0000h 32.4.8/2431 214 USB Charger Detect Register (USB_ANALOG_USB2_CHRG_DETECT_SET) 32 R/W 0000_0000h 32.4.8/2431 218 USB Charger Detect Register (USB_ANALOG_USB2_CHRG_DETECT_CLR) 32 R/W 0000_0000h 32.4.8/2431 21C USB Charger Detect Register (USB_ANALOG_USB2_CHRG_DETECT_TOG) 32 R/W 0000_0000h 32.4.8/2431 220 USB VBUS Detect Status Register (USB_ANALOG_USB2_VBUS_DETECT_STAT) 32 R 0000_0000h 32.4.9/2433 230 USB Charger Detect Status Register (USB_ANALOG_USB2_CHRG_DETECT_STAT) 32 R 0000_0000h 32.4.10/ 2435 250 USB Misc Register (USB_ANALOG_USB2_MISC) 32 R/W 0000_0002h 32.4.11/ 2436 254 USB Misc Register (USB_ANALOG_USB2_MISC_SET) 32 R/W 0000_0002h 32.4.11/ 2436 258 USB Misc Register (USB_ANALOG_USB2_MISC_CLR) 32 R/W 0000_0002h 32.4.11/ 2436 25C USB Misc Register (USB_ANALOG_USB2_MISC_TOG) 32 R/W 0000_0002h 32.4.11/ 2436 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2420 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.4.1 Chip Silicon Version (USB_ANALOG_DIGPROG) The DIGPROG register returns the digital program ID for the silicon. Address: 0h base + 0h offset = 0h Bit 31 30 29 R 27 26 25 24 23 22 21 20 19 18 17 0 0 0 0 0 16 15 14 13 12 11 10 9 8 7 6 5 MAJOR Reserved W Reset 28 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 MINOR 0 0 0 0 0 0 0 0 0 0 0 0 USB_ANALOG_DIGPROG field descriptions Field 31-24 - Description This field is reserved. Reserved. 23-8 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. MINOR Fixed read-only value reflecting the MINOR field of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2421 USB Analog Memory Map/Register Definition 32.4.2 USB VBUS Detect Register (USB_ANALOG_USB1_VBUS_DETECTn) This register defines controls for USB VBUS detect. Address: 0h base + 1A0h offset + (4d x i), where i=0d to 3d 30 29 28 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W VBUSVALID_ PWRUP_CMPS 0 Reserved Bit 26 0 R Reset 27 DISCHARGE_ VBUS 31 CHARGE_VBUS Bit Reserved Reserved R VBUSVALID_ THRESH Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 USB_ANALOG_USB1_VBUS_DETECTn field descriptions Field 31-28 - Description This field is reserved. Reserved. 27 USB OTG charge VBUS. CHARGE_VBUS 26 DISCHARGE_ VBUS 25-21 - USB OTG discharge VBUS. This field is reserved. Reserved. 20 Powers up comparators for vbus_valid detector. VBUSVALID_ PWRUP_CMPS 19-3 VBUSVALID_ THRESH This field is reserved. Reserved. Set the threshold for the VBUSVALID comparator. This comparator is the most accurate method to determine the presence of 5v, and includes hystersis to minimize the need for software debounce of the detection. This comparator has ~50mV of hystersis to prevent chattering at the comparator trip point. 000 4V0 -- 4.0V Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2422 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) USB_ANALOG_USB1_VBUS_DETECTn field descriptions (continued) Field Description 001 010 011 100 101 110 111 4V1 -- 4.1V 4V2 -- 4.2V 4V3 -- 4.3V 4V4 -- 4.4V (default) 4V5 -- 4.5V 4V6 -- 4.6V 4V7 -- 4.7V 32.4.3 USB Charger Detect Register (USB_ANALOG_USB1_CHRG_DETECTn) This register defines controls for USB charger detect. Address: 0h base + 1B0h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 EN_B CHK_CONTACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reserved 0 Reserved Reserved W Reset Bit 16 CHK_CHRG_B R 17 Reserved R Reserved W Reset 0 0 0 0 0 0 0 0 0 USB_ANALOG_USB1_CHRG_DETECTn field descriptions Field 31-24 - Description This field is reserved. Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2423 USB Analog Memory Map/Register Definition USB_ANALOG_USB1_CHRG_DETECTn field descriptions (continued) Field Description 23 - This field is reserved. Reserved. 22-21 - This field is reserved. Reserved. 20 EN_B Control the charger detector. 19 CHK_CHRG_B 0 1 ENABLE -- Enable the charger detector. DISABLE -- Disable the charger detector. 0 CHECK -- Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. NO_CHECK -- Do not check whether a charger is connected to the USB port. 1 18 0 CHK_CONTACT 1 - NO_CHECK -- Do not check the contact of USB plug. CHECK -- Check whether the USB plug has been in contact with each other This field is reserved. Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2424 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.4.4 USB VBUS Detect Status Register (USB_ANALOG_USB1_VBUS_DETECT_STAT) This register defines fields for USB VBUS Detect status. Address: 0h base + 1C0h offset = 1C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BVALID SESSEND Bit 0 AVALID Reset VBUS_VALID W 0 0 0 0 0 0 0 0 0 R Reserved W Reset 0 0 0 0 0 0 0 USB_ANALOG_USB1_VBUS_DETECT_STAT field descriptions Field 31-4 - Description This field is reserved. Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2425 USB Analog Memory Map/Register Definition USB_ANALOG_USB1_VBUS_DETECT_STAT field descriptions (continued) Field 3 VBUS_VALID Description VBus valid for USB OTG. This bit is a read only version of the state of the analog signal. It can not be overwritten by software. 2 AVALID Indicates VBus is valid for a A-peripheral. This bit is a read only version of the state of the analog signal. It can not be overritten by software. 1 BVALID Indicates VBus is valid for a B-peripheral. This bit is a read only version of the state of the analog signal. It can not be overritten by software. 0 SESSEND Session End for USB OTG. This bit is a read only version of the state of the analog signal. It can not be overwritten by software like the SESSEND bit below. NOTE: This bit's default value depends on whether VDD5V is present, 0 if VDD5V is present, 1 if VDD5V is not present. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2426 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.4.5 USB Charger Detect Status Register (USB_ANALOG_USB1_CHRG_DETECT_STAT) This register defines fields for USB charger detect status. Address: 0h base + 1D0h offset = 1D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHRG_DETECTED PLUG_CONTACT Bit 0 DM_STATE Reset DP_STATE W 0 0 0 0 0 0 0 0 0 R Reserved W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2427 USB Analog Memory Map/Register Definition USB_ANALOG_USB1_CHRG_DETECT_STAT field descriptions Field Description 31-4 - This field is reserved. Reserved. 3 DP_STATE DP line state output of the charger detector. 2 DM_STATE DM line state output of the charger detector. 1 CHRG_ DETECTED State of charger detection. This bit is a read only version of the state of the analog signal. 0 PLUG_ CONTACT State of the USB plug contact detector. 0 1 0 1 CHARGER_NOT_PRESENT -- The USB port is not connected to a charger. CHARGER_PRESENT -- A charger (either a dedicated charger or a host charger) is connected to the USB port. NO_CONTACT -- The USB plug has not made contact. GOOD_CONTACT -- The USB plug has made good contact. 32.4.6 USB Misc Register (USB_ANALOG_USB1_MISCn) This register defines controls for USB. Address: 0h base + 1F0h offset + (4d x i), where i=0d to 3d Bit 31 30 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HS_USE_EXTERNAL_R 25 EN_DEGLITCH 26 EN_CLK_UTMI Bit 27 0 0 0 0 0 0 0 1 0 W Reset 28 Reserved R 29 Reserved R Reserved W Reset 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2428 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) USB_ANALOG_USB1_MISCn field descriptions Field Description 31 - This field is reserved. Reserved. 30 EN_CLK_UTMI Enables the clk to the UTMI block. 29-2 - This field is reserved. Reserved. 1 Enable the deglitching circuit of the USB PLL output. EN_DEGLITCH 0 HS_USE_ EXTERNAL_R Use external resistor to generate the current bias for the high speed transmitter. This bit should not be changed unless recommended by Freescale. 32.4.7 USB VBUS Detect Register (USB_ANALOG_USB2_VBUS_DETECTn) This register defines controls for USB VBUS detect. Address: 0h base + 200h offset + (4d x i), where i=0d to 3d 30 29 28 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W VBUSVALID_ PWRUP_CMPS 0 Reserved Bit 26 0 R Reset 27 DISCHARGE_ VBUS 31 CHARGE_VBUS Bit Reserved Reserved R VBUSVALID_ THRESH Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 USB_ANALOG_USB2_VBUS_DETECTn field descriptions Field 31-28 - Description This field is reserved. Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2429 USB Analog Memory Map/Register Definition USB_ANALOG_USB2_VBUS_DETECTn field descriptions (continued) Field Description 27 USB OTG charge VBUS. CHARGE_VBUS 26 DISCHARGE_ VBUS 25-21 - USB OTG discharge VBUS. This field is reserved. Reserved. 20 Powers up comparators for vbus_valid detector. VBUSVALID_ PWRUP_CMPS 19-3 VBUSVALID_ THRESH This field is reserved. Reserved. Set the threshold for the VBUSVALID comparator. This comparator is the most accurate method to determine the presence of 5v, and includes hystersis to minimize the need for software debounce of the detection. This comparator has ~50mV of hystersis to prevent chattering at the comparator trip point. 000 001 010 011 100 101 110 111 4V0 -- 4.0V 4V1 -- 4.1V 4V2 -- 4.2V 4V3 -- 4.3V 4V4 -- 4.4V (default) 4V5 -- 4.5V 4V6 -- 4.6V 4V7 -- 4.7V i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2430 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.4.8 USB Charger Detect Register (USB_ANALOG_USB2_CHRG_DETECTn) This register defines controls for USB charger detect. Address: 0h base + 210h offset + (4d x i), where i=0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 EN_B CHK_CONTACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Reserved 0 Reserved Reserved W Reset Bit 16 CHK_CHRG_B R 17 Reserved R Reserved W Reset 0 0 0 0 0 0 0 0 0 USB_ANALOG_USB2_CHRG_DETECTn field descriptions Field Description 31-24 - This field is reserved. Reserved. 23 - This field is reserved. Reserved. 22-21 - This field is reserved. Reserved. 20 EN_B Control the charger detector. 19 CHK_CHRG_B 0 1 ENABLE -- Enable the charger detector. DISABLE -- Disable the charger detector. 0 CHECK -- Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. NO_CHECK -- Do not check whether a charger is connected to the USB port. 1 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2431 USB Analog Memory Map/Register Definition USB_ANALOG_USB2_CHRG_DETECTn field descriptions (continued) Field Description 18 0 CHK_CONTACT 1 - NO_CHECK -- Do not check the contact of USB plug. CHECK -- Check whether the USB plug has been in contact with each other This field is reserved. Reserved. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2432 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.4.9 USB VBUS Detect Status Register (USB_ANALOG_USB2_VBUS_DETECT_STAT) This register defines fields for USB VBUS Detect status. Address: 0h base + 220h offset = 220h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BVALID SESSEND Bit 0 AVALID Reset VBUS_VALID W 0 0 0 0 0 0 0 0 0 R Reserved W Reset 0 0 0 0 0 0 0 USB_ANALOG_USB2_VBUS_DETECT_STAT field descriptions Field 31-4 - Description This field is reserved. Reserved. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2433 USB Analog Memory Map/Register Definition USB_ANALOG_USB2_VBUS_DETECT_STAT field descriptions (continued) Field 3 VBUS_VALID Description VBus valid for USB OTG. This bit is a read only version of the state of the analog signal. It can not be overwritten by software. 2 AVALID Indicates VBus is valid for a A-peripheral. This bit is a read only version of the state of the analog signal. It can not be overritten by software. 1 BVALID Indicates VBus is valid for a B-peripheral. This bit is a read only version of the state of the analog signal. It can not be overritten by software. 0 SESSEND Session End for USB OTG. This bit is a read only version of the state of the analog signal. It can not be overwritten by software like the SESSEND bit below. NOTE: This bit's default value depends on whether VDD5V is present, 0 if VDD5V is present, 1 if VDD5V is not present. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2434 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) 32.4.10 USB Charger Detect Status Register (USB_ANALOG_USB2_CHRG_DETECT_STAT) This register defines fields for USB charger detect status. Address: 0h base + 230h offset = 230h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHRG_DETECTED PLUG_CONTACT Bit 0 DM_STATE Reset DP_STATE W 0 0 0 0 0 0 0 0 0 R Reserved W Reset 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2435 USB Analog Memory Map/Register Definition USB_ANALOG_USB2_CHRG_DETECT_STAT field descriptions Field Description 31-4 - This field is reserved. Reserved. 3 DP_STATE DP line state output of the charger detector. 2 DM_STATE DM line state output of the charger detector. 1 CHRG_ DETECTED State of charger detection. This bit is a read only version of the state of the analog signal. 0 PLUG_ CONTACT State of the USB plug contact detector. 0 1 0 1 CHARGER_NOT_PRESENT -- The USB port is not connected to a charger. CHARGER_PRESENT -- A charger (either a dedicated charger or a host charger) is connected to the USB port. NO_CONTACT -- The USB plug has not made contact. GOOD_CONTACT -- The USB plug has made good contact. 32.4.11 USB Misc Register (USB_ANALOG_USB2_MISCn) This register defines controls for USB. Address: 0h base + 250h offset + (4d x i), where i=0d to 3d Bit 31 30 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HS_USE_EXTERNAL_R 25 EN_DEGLITCH 26 EN_CLK_UTMI Bit 27 0 0 0 0 0 0 0 1 0 W Reset 28 Reserved R 29 Reserved R Reserved W Reset 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2436 Freescale Semiconductor, Inc. Chapter 32 Universal Serial Bus 2.0 Integrated PHY (USB-PHY) USB_ANALOG_USB2_MISCn field descriptions Field 31 30 EN_CLK_UTMI 29-2 - Description This field is reserved. Reserved. Enables the clk to the UTMI block. This field is reserved. Reserved. 1 Enable the deglitching circuit of the USB PLL output. EN_DEGLITCH 0 HS_USE_ EXTERNAL_R Use external resistor to generate the current bias for the high speed transmitter. This bit should not be changed unless recommended by Freescale. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2437 USB Analog Memory Map/Register Definition i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2438 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) 33.1 LCD Interface (LCDIF) Overview Many products based on the i.MX28 include an LCD panel with an integrated controller/ driver. These smart LCDs are available in a range of sizes and capabilities, from simple text-only displays to QVGA, 16/18/24 bpp color TFT panels. Traditionally, many of these display controllers have had an asynchronous parallel MPU interface for command and data transfer to the frame buffer. There are other popular displays that support moving pictures and require the RGB interface mode (called DOTCLK interface in this document) or the VSYNC mode for high-speed data transfers. In addition to these displays, it is also common to provide support for digital video encoders that accept ITUR BT.656 format 4:2:2 YCbCr digital component video and convert it to analog TV signals. The LCDIF block supports all of these different interfaces by providing fully programmable functionality and sharing register space, FIFOs, and ALU resources at the same time. The high-level block diagram of the LCD interface is shown in Figure 33-1. The block has several major features: * High display resolutions up to 800x480 supported. * AXI-based bus master mode for LCD writes and DMA operating modes for LCD reads requiring minimal CPU overhead. * 8/16/18/24 bit LCD data bus support available depending on the package size. * Programmable timing and parameters for system, MPU, VSYNC and DOTCLK LCD interfaces to support a wide variety of displays. * ITU-R BT.656 mode (called Digital Video Interface or DVI mode here) including progressive-to-interlace feature and RGB to YCbCr 4:2:2 color space conversion to support 525/60 and 625/50 operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2439 Operation 33.2 Operation Bus Interface Mechanisms, through Initializing the LCDIF, describe the internal pipeline for the MPU write/read interface, VSYNC, DOTCLK, and DVI interfaces. Differences for each mode are then described in separate sections, as follows: * MPU Interface * VSYNC Interface * DOTCLK Interface * ITU-R BT.656 Digital Video Interface (DVI) LCDIF pin usage by interface mode is described in LCDIF Pin Usage by Interface Mode. The following figure shows the top-level block-diagram of LCDIF sub-system. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2440 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) SRAM EMI 24-MHz XTAL Osc. or PLL ARM CORE 24-MHz XTAL Osc. or PLL AHB Divide by m Divide by n APBH Master APB LCDIF AXI Master 32x16 RXFIFO HCLK AXI Shared APBH DMA DIS_LCDIF_CLK APB Bridge System / VSYNC/ DOTCLK LCD Interface HW_LCDIF_CTRL and _DATA Registers and DMA Slave APBH Ctrl 76x256 LFIFO 38x2 INTFIFO Digital Video Interface 38x16 TXFIFO HCLK Domain CLK_DIS_LCDIFn Domain To/From LCD Pins Figure 33-1. LCDIF Top Level Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2441 Operation 33.2.1 Bus Interface Mechanisms The LCDIF block has memory-mapped control, data and status registers. It provides two efficient methods of transferring data to/from an external LCD controller or a digital video encoder, the APB DMA slave and AXI bus master. In either mode of operation, the bus interface portion of the block works off the HCLK domain, while the actual interface to external display/encoder works off the CLK_DIS_LCDIFn domain. There are three main FIFOs in the block datapath. The latency FIFO (LFIFO) in the write datapath is a 256 double words deep synchronous FIFO that offers buffering against system bandwidth and latency. Another FIFO in the write datapath, called TXFIFO, is a 16 words deep asynchronous FIFO that assists data crossing between the two clock domains. In the read datapath, there is a 16-deep asynchronous RXFIFO that is read by DMA operation. The following sub-sections describe the two system bus interface mechanisms. 33.2.1.1 Bus Master Operation in Write/Display Modes In this mode, the LCDIF block acts as a master on AXI fabric shared with other blocks like PXP. This is a high performance mode and does not require DMA descriptor setup. The LCDIF_MASTER bit must be set to 1 to enable bus master operations. Software should program the LCD Interface Current Buffer Address Register (HW_LCDIF_CUR_BUF) and LCD Interface Next Buffer Address Register (HW_LCDIF_NEXT_BUF) registers to point to the base of the frame buffers that needs to be transferred out. In the MPU and VSYNC modes, once the frame buffer pointed to by the HW_LCDIF_CUR_BUF_ADDR is transferred out, LCDIF stops transmitting and turns off the RUN bit in LCDIF General Control Register (HW_LCDIF_CTRL) register. It has to be setup and kicked off again for transmitting the next frame. In the DOTCLK and DVI modes, which are streaming modes in the true sense, software should start off with programming both the HW_LCDIF_CUR_BUF_ADDR and HW_LCDIF_NEXT_BUF_ADDR registers, and then, it only has to update the HW_LCDIF_NEXT_BUF_ADDR register in every frame. LCDIF will automatically update the HW_LCDIF_CUR_BUF_ADDR register with the value in HW_LCDIF_NEXT_BUF_ADDR at the end of current frame and start fetching the next frame from the new address. Thus, software has about one frame worth of time to update HW_LCDIF_NEXT_BUF_ADDR before it actually gets used. If for some reason, the HW_LCDIF_NEXT_BUF_ADDR register was not updated within a frame, LCDIF will keep transmitting the last frame until a new value is programmed into that register. The performance of the LCDIF block can be tweaked by changing the burst length and the number of outstanding requests that can be issued at a time depending on the bandwidth requirements. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2442 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) LCDIF also provides the capability of interlacing a progressive frame by fetching odd lines in the first field and then fetching even lines in the second field. This feature can be used in the DVI mode and can be turned on by setting the INTERLACE_FIELDS bit in the HW_LCDIF_CTRL1 register. 33.2.1.2 DMA Operation in MPU Read Mode Unlike previous generation SoCs, the DMA operation is now only used with the MPU read mode. None of the write modes can use the DMA for display purposes since APBH DMA will not be able to keep up with the high bandwidth requirements of the i.MX28. The LCDIF block resides on the AHB-APBH bridge DMA as a DMA slave. The AHBAPBH bridge DMA is used to move data from an external LCD controller, or any device that uses a 6800/8080 type interface, that needs to send data to the CPU through the LCDIF block. The software designer can take advantage of the DMA's linked descriptors that give substantial flexibility for setting up the frame buffers. The LCDIF provides a request signal to the central DMA if the LCDIF_MASTER bit in HW_LCDIF_CTRL register is 0. The request signal is asserted any time the LCDIF is enabled and there is at least one data to be read in its RXFIFO.The DMA request signal is also visible in the LCDIF control and status register. The DMA reads one word from the HW_LCDIF_DATA register every time it detects a toggle on the LCDIF request signal. The CPU can also directly read commands or data by setting up the block in non-busmaster mode (HW_LCDIF_CTRL_LCDIF_MASTER = 0) and reading directly to the HW_LCDIF_DATA register without setting up the DMA descriptors. The FIFO status bits in the HW_LCDIF_STAT register indicate the full and empty states of the RXFIFO. When the RXFIFO is not empty, the data register can be safely read as required; doing otherwise will result in an incorrect operation. 33.2.2 Write Datapath LCDIF expects all frame buffers to be arranged in the raster format since external displays and digital video encoders require the same. LCDIF directly fetches little-endian data from memory. This raw input data can be swizzled according to the INPUT_DATA_SWIZZLE field in the HW_LCDIF_CTRL register before any other operation is performed on the incoming data. The following four combinations are supported: 00 (0): No swizzle (little-endian) 01 (1): Swap bytes 0 and 3, swap bytes 1 and 2 (big-endian) 10 (2): Swap half-words 11 (3): Swap bytes within each half-word i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2443 Operation The WORD_LENGTH field of HW_LCDIF_CTRL register indicates the input data/pixel format. HW_LCDIF_TRANSFER_COUNT register denotes how much data is contained in each frame. The H_COUNT field of this register indicates the number of pixels per line and V_COUNT indicates the total number of lines per frame. A special bit field in the HW_LCDIF_CTRL1 register, called the BYTE_PACKING_FORMAT, can be used to specify which bytes within the 32-bit word are going to be valid. For example, if the entire 32-bit word is valid, BYTE_PACKING_FORMAT should be set to 0xF, if only lower 3 bytes of each word in the frame buffer are valid, then BYTE_PACKING_FORMAT should be set to 0x7. The LCD_DATABUS_WIDTH field in HW_LCDIF_CTRL register suggests the width of the bus going to the external display controller. If the LCD_DATABUS_WIDTH is not the same as WORD_LENGTH, LCDIF will do minor RGB to RGB color space conversion. For example, if the input frame has more bits per pixel than the display, for example, 16 bpp input frame going to 24 bpp LCD, LCDIF will pad the MSBs of each color to the LSBs of the same color for each pixel. If the input frame has lesser bits per pixel than the display, for example, 24 bpp input frame going to 16 bpp LCD, LCDIF will drop the LSBs of each color to go to the lower resolution. LCDIF also has the capability to support delta pixel displays by swizzling the R, G and B colors of each pixel in the odd and even lines of the frame separately by programming the ODD_LINE_PATTERN and the EVEN_LINE_PATTERN bitfields. This operation occurs after the RGB-to-RGB color space conversion operation. LCDIF also supports RGB to YCbCr 4:2:2 color space conversion. This is useful in the DVI mode since the TV encoder requires input in YCbCr 4:2:2 format. The HW_LCDIF_CSC* registers have complete programmability over the CSC coefficients and offsets. The values must be written into these registers in the signed two's complement format. The following list shows how the different input/output combinations can be obtained: * WORD_LENGTH=1 indicates that the input is 8-bit data. This is most likely going to be used for sending commands in MPU interface, or maybe a grayscale image. Any combination of BYTE_PACKING_FORMAT [3:0] is permissible. Limitation: H_COUNT must be a multiple of the sum of BYTE_PACKING_FORMAT [3], BYTE_PACKING_FORMAT [2], BYTE_PACKING_FORMAT [1] and BYTE_PACKING_FORMAT [0]. LCD_DATABUS_WIDTH must be 1, indicating an 8-bit data bus. * WORD_LENGTH=0 implies the input frame buffer is RGB 16 bits per pixel. DATA_FORMAT_16_BIT field determines the pixels are RGB 555 or RGB 565. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2444 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) Limitation: BYTE_PACKING_FORMAT [3:0] should be 0x3 or 0xC if there is only one pixel per word. If there are two pixels per word, it should be 0xF and H_COUNT will be restricted to be a multiple of 2 pixels. * WORD_LENGTH=2 indicates that input frame buffer is RGB 18 bits per pixel, that is, RGB 666. The valid RGB values can be left-aligned or right-aligned within a 32bit word. The alignment of the valid 18 bits within a word is indicated by the DATA_FORMAT_18_BIT bit. Limitation: BYTE_PACKING_FORMAT can be 0x7, 0xE or 0xF. Packed pixels are not supported in this case. H_COUNT can be any number. * WORD_LENGTH=3 indicates that the input frame-buffer is RGB 24 bits per pixel (RGB 888). If BYTE_PACKING_FORMAT [3:0] is 0x7, it indicates that there is only one pixel per 32-bit word and there is no restriction on H_COUNT. Limitation: If BYTE_PACKING_FORMAT [3:0] is 0xF, it indicates that the pixels are packed, that is, there are 4 pixels in 3 words or 12 bytes and H_COUNT must be a multiple of 4 pixels. * YCBCR422_INPUT=1 implies that the input frame is in YCbCr 4:2:2 format. BYTE_PACKING_FORMAT must be 0xF. Limitation: LCD_DATABUS_WIDTH must be 8-bit and H_COUNT must be a multiple of 2 pixels. * ODD_LINE_PATTERN and EVEN_LINE_PATTERN must be 0 when any of RGB_TO_YCBCR422_CSC or INTERLACE_FIELDS or YCBCR422_INPUT bits is 1. After the RGB to RGB or RGB to YCbCr 4:2:2 color space conversions, there is one more opportunity to swizzle the data before sending it out to the display or the encoder. This can be done with the CSC_DATA_SWIZZLE field in the HW_LCDIF_CTRL register, and it provides the same options as the INPUT_DATA_SWIZZLE register. Finally, there is an option to shift the output data before sending it out to the display. This is done based on the SHIFT_DIR and SHIFT_NUM_BITS fields in HW_LCDIF_CTRL register. Figure 33-2 shows the general operations that occur in the write data path. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2445 Operation CLK_DIS_LCDIFn Domain HCLK Domain MPU/VSYNC/ DOTCLK/DVI Mode Control Write Control 38 Delta Pixel Xmit Data 38 64 64 AXI MST Control Swizzle Byte Packing 8 Count 8 Calcn 8 76x 76 256 LFIFO RGB to YCbCr 4:2:2 38 Read Control 38 Serialize, Unpack & RGB to RGB 888 CSC FIFO in Byte Enables 32 38 38x2 IntFIFO Transfer Control 38x16 TxFIFO LCD Data 8/16/18/24 8/16/18/24 4 Shift 32 Signal Gen LCD Control FIFO Status FIFO Status Figure 33-2. LCDIF Write Data Path The examples in Figure 33-3 - Figure 33-6 illustrate some different combinations of register programming for write mode. Assume that the data written into the HW_LCDIF_DATA register is of the format {A7-A0, B7-B0, C7-C0, D7-D0} in 8-bit mode and {A15-A0, B15-B0} in 16-bit mode. WORD_LENGTH = 1 HW_LCDIF_DATA A7 A0 B7 B0 D7 D0 C7 C0 BYTE_PACKING_FORMAT[3:0] = 1111 A7 A0 B7 B0 C7 C0 D7 D0 DATA_SWIZZLE[1:0] = 00 A7 A0 B7 B0 C7 C0 D7 D0 SHIFT_DIR = 1, SHIFT_NUM_BITS[1:0] = 10 LCD_DATA[7:0] Pins {0,0,A7 A2} {0,0,B7 B2} {0,0,C7 C2} {0,0,D7 D2} {0,0,D7 D2} {0,0,C7 C2} {0,0,B7 B2} {0,0,A7 A2} Figure 33-3. 8-Bit LCDIF Register Programming-Example A i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2446 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) WORD_LENGTH = 1 HW_LCDIF_DATA A7-A0 B7-B0 C7-C0 D7-D0 BYTE_PACKING_FORMAT[3:0] =0111 X B7-B0 C7-C0 D7-D0 DATA_SWIZZLE[1:0] = 01 D7-D0 C7-C0 X B7-B0 SHIFT_DIR = 0, SHIFT_NUM_BITS[1:0] = 00 D7-D0 LCD_DATA[7:0] Pins C7-C0 B7-B0 X B7-B0 C7-C0 D7-D0 Figure 33-4. 8-Bit LCDIF Register Programming-Example B WORD_LENGTH = 0 HW_LCDIF_DATA A15-A0 B15-B0 BYTE_PACKING_FORMAT[3:0] = 1111 A15-A0 B15-B0 DATA_SWIZZLE[1:0] = 00 A15-A0 B15-B0 SHIFT_DIR = 1, SHIFT_NUM_BITS[1:0] = 10 LCD_DATA[15:0] Pins {0,0,A15-A2} {0,0,B15-B2} {0,0,A15-A2} {0,0,B15-B2} Figure 33-5. 16-Bit LCDIF Register Programming-Example A i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2447 Operation HCLK Domain CLK_DIS_LCDIFn Domain LCD DMA Control 32 Swizzle 32x16 RXFIFO WORD_LENGTH 32 READ_MODE_OUTPUT _IN_RGB_FORMAT 32 32 32 32 32 RGB to RGB CSC 32 Temp Reg and Valid Subword Packing 32 8/16 Read Control Write Control Shifting LCD Data 8/16 8/16/18/24 8/16 Transfer Control FIFO Status Count Calculation Signal Gen LCD Control Figure 33-6. 16-Bit LCDIF Register Programming-Example B 33.2.3 Read Datapath HCLK Domain CLK_DIS_LCDIFn Domain LCD DMA Control 32 Swizzle 32x16 RXFIFO WORD_LENGTH 32 READ_MODE_OUTPUT _IN_RGB_FORMAT 32 32 32 32 32 RGB to RGB CSC 32 32 Temp Reg and Valid Subword Packing 8/16 Read Control Write Control Shifting LCD Data 8/16 8/16/18/24 8/16 FIFO Status Count Calculation Transfer Control Signal Gen LCD Control Figure 33-7. 16-Bit LCDIF Register Programming-Example B The above figure shows the MPU read datapath in detail. LCDIF can read from an external LCD controller or any other device that follows the 6800/8080 MPU protocol. The size of the data read at a time on the interface is determined by the LCD_DATABUS_WIDTH bitfield. The data grabbed at every read strobe is called a subword and the number of subwords that can be packed in a 32-bit word is given by the READ_MODE_NUM_PACKED_SUBWORDS bitfield. Setting a non-zero value in the INITIAL_DUMMY_READ bitfield indicates to LCDIF to skip that many number of subwords before starting to record the read data. This feature is useful in the case of an LCD controller that returns the last written data the first time a read is issued, and then sends the correct data after that point. SHIFT_DIR and SHIFT_NUM_BITS bitfields indicate whether the data needs to be shifted before getting stored in the internal registers. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2448 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) For example, a value of 2 in READ_MODE_NUM_PACKED_SUBWORDS if lcd databus width is 8 bits indicates two bytes should be packed in a 32-bit word, while if the lcd databus width is 16 bits, it indicates that two half words (or 4 bytes) should be packed. After the last subword within a word is reached, the block looks at the READ_PACK_DIR in the HW_LCDIF_CTRL2 register. If this bit is set, the block will swizzle the data, but only within the valid bytes, unlike in the write mode, where swizzle occurs across all 4 bytes. If the READ_MODE_OUTPUT_IN_RGB_FORMAT bit is set, LCDIF will convert the data obtained from the READ_PACK_DIR operation into 24-bit unpacked RGB and then re-convert it into 16/18/24 bpp RGB depending on the WORD_LENGTH field. The DATA_FORMAT_16/18/24_BIT bitfields are also considered while converting to 24-bit unpacked RGB format. For example, if DATA_FORMAT_18_BIT is 1, the RGB666 data will be packed in the upper bits [31:4]of a 32-bit word, and that bit is 0, the data will be packed in the lower bits [17:0]. After all these operations, the data gets written into the RXFIFO. The following figures show some examples of how data is handled in different MPU read modes. READ_MODE_NUM_PACKED_SUBWORDS = 2 AND LCD_DATABUS_WIDTH = 8 BITS OR READ_MODE_NUM_PACKED_SUBWORDS = 1 AND LCD_DATABUS_WIDTH = 16 BITS 8/16 SHIFT 00 00 00 00 A7-A0 B7-B0 In the case of LCD_DATABUS_WIDTH = 8 bits, Input is stored in little endian format, with the first incoming byte stored in byte 0 A7-A0 B7-B0 0 1 READ_PACK_DIR 24 BPP 00 {R4-R0,G5-G3} 00 {R4-R0,R4-R2} {G5-G0,G5-G4} {B4-B0,B4-B2} 00 {2'h0, R4-R0, R4} {2'h0, G5-G0} {2'h0, B4-B0, B4} 00 {6'h0,R4-R3} {R2-R0,R4,G5-G2} {G1-G0,G5,B4B0,B4} {R4-R0, R4,G5-G4 } {G3-G0, B4-B1 } {B0, B4, 6'h0} 00 16 BPP 00 00 {R4-R0,G5-G3} {G2-G0,B4-B0} 16 BPP 00 00 {1'h0, R4-R0, G5G4} {G3-G1,B4-B0} 24 BPP 18 BPP 18 BPP {G2-G0,B4-B0} WORD_LENGTH 00 1 0 READ_MODE_OUTPUT_I N_RGB_FORMAT RXFIFO DATA_SWIZZLE TO DMA Figure 33-8. MPU Read Mode Operation - Page 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2449 Operation READ_MODE_NUM_PACKED_SUBWORDS = 3 AND LCD_DATABUS_WIDTH = 8 BITS OR READ_MODE_NUM_PACKED_SUBWORDS = 1 AND LCD_DATABUS_WIDTH = 24 BITS 8/24 SHIFT 00 A7-A0 00 B7-B0 C7-C0 A7-A0 C7-C0 B7-B0 In the case of LCD_DATABUS_WIDTH = 8 bits, Input is stored in little endian format, with the first incoming byte stored in byte 0 0 1 READ_PACK_DIR 24 BPP G7-G0 R7-R0 B7-B0 00 {R7-R0} {G7-G0} {B7-B0} 00 {2'h0, R7-R2} {2'h0, G7-G2} {2'h0, B7-B2} 18 BPP 00 {6'h0,R7-R6} {R5-R2, G7-G4} {G3-G2, B7-B2} 18 BPP {R7-R2, G7-G6 } {G5-G2, B7-B4 } {B3-B2, 6'h0} 00 00 00 {R7-R3,G7-G5} {G4-G2, B7-B3} 00 00 {1'h0, R7-R3, G7G6} {G5-G3, B7-B3} 24 BPP 16 BPP 16 BPP WORD_LENGTH 00 1 0 READ_MODE_OUTPUT_I N_RGB_FORMAT RXFIFO DATA_SWIZZLE TO DMA Figure 33-9. MPU Read Mode Operation - Page 2 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2450 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) READ_MODE_NUM_PACKED_SUBWORDS = 1 AND LCD_DATABUS_WIDTH = 18 BITS 18 SHIFT 00 A7-A0 00 C7-C0 B7-B0 B7-B0 In the case of LCD_DATABUS_WIDTH = 8 bits, Input is stored in little endian format, with the first incoming byte stored in byte 0 A7-A0 C7-C0 0 1 READ_PACK_DIR 24 BPP {6'h0,R5-R4} {R3-R0,G5-G2} 00 {R5-R0, R5-R4} {G5-G0, G5-G4} {B5-B0, B5-B4} 00 {2'h0, R5-R0} {2'h0, G5-G0} {2'h0, B5-B0} 18 BPP 00 {6'h0,R5-R4} {R3-R0,G5-G2} {G1-G0,B5-B0} 18 BPP {R5-R0, G5-G4 } {G3-G0, B5-B2 } {B1-B0, 6'h0} 00 00 00 {R5-R1,G5-G3} {G2-G0, B5-B1} 00 00 {1'h0, R5-R1, G5G4} {G3-G1, B5-B1} 24 BPP 16 BPP 16 BPP {G1-G0,B5-B0} WORD_LENGTH 00 0 1 READ_MODE_OUTPUT _IN_RGB_FORMAT RXFIFO DATA_SWIZZLE TO DMA Figure 33-10. MPU Read Mode Operation - Page 3 Restrictions: READ_PACK_DIR should only be used if it is required to swizzle the subwords before doing RGB to RGB CSC, otherwise the DATA_SWIZZLE field should be used to swizzle across bytes. READ_PACK_DIR must be 0 if LCD_DATABUS_WIDTH is 8 bits and READ_MODE_NUM_PACKED_SUBWORDS =1 If READ_MODE_OUTPUT_IN_RGB_FORMAT bit is set, the following restrictions should be followed: * If LCD_DATABUS_WIDTH = 8 bits, then READ_MODE_NUM_PACKED_SUBWORDS <= 3. * If LCD_DATABUS_WIDTH = 16/18/24 bits, then READ_MODE_NUM_PACKED_SUBWORDS = 1. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2451 Operation 33.2.4 LCDIF Interrupts LCDIF supports a number of interrupts to aid controlling and status reporting of the block. All the interrupts have individual mask bits for enabling or disabling each of them. They all get funneled through a single interrupt line connected to the interrupt collector (ICOLL). The following list describes the different interrupts supported by LCDIF: * Underflow interrupt is asserted when the clock domain crossing FIFO (TXFIFO) becomes empty but the block is in active display portion during that time. Software should take corrective action to make sure that this does not happen. * In the bus master mode, the overflow interrupt will be asserted if the block has requested more data than it's FIFOs could hold. In the read mode, it will be asserted if the RxFIFO becomes full and the block reads more data. * VSYNC edge interrupt will be asserted every time a leading VSYNC edge occurs. * Cur_frame_done interrupt occurs at the end of every frame in all modes except DVI. In DVI mode, if IRQ_ON_ALTERNATE_FIELDS bit is set, it will occur at the end of every frame, otherwise it will occur at the end of every field. 33.2.5 Initializing the LCDIF This section describes write modes and MPU read mode 33.2.5.1 Write Modes The following initialization steps are common to all LCDIF write modes of operation before entering any particular mode. Initialization steps: 1. To select the pins and their directions for talking to the LCD panel, set the appropriate bits in the HW_PINCTRL_MUXSELx registers in the PINCTRL block. 2. Start the CLK_DIS_LCDIFn clock and set the appropriate frequency by programming the registers in CLKCTRL. 3. Start the HCLK and set the appropriate frequency by programming the registers in CLKCTRL. 4. Bring the LCDIF out of soft reset and clock gate. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2452 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) 5. Reset the LCD controller by setting LCDIF_CTRL1_RESET bit appropriately, being careful to observe the reset requirements of the controller. See Behavior During Reset for more information on Reset requirements. 6. Make sure READ_WRITEB bit in HW_LCDIF_CTRL register is 0. 7. Select AXI bus master mode by setting the LCDIF_MASTER bit in HW_LCDIF_CTRL register to 1. 8. Set the INPUT_DATA_SWIZZLE according to the endianness of the LCD controller. Also, set the DATA_SHIFT_DIR and SHIFT_NUM_BITS if it is required to shift the data left or right before it is output. 9. Set the WORD_LENGTH field appropriately: 0 = 16-bit input, 1 = 8-bit input, 2 = 18-bit input, 3 = 24-bit input. Also, select the correct 16/18/24 bit data format with the corresponding fields in HW_LCDIF_CTRL register. 10. Set the BYTE_PACKING_FORMAT field in HW_LCDIF_CTRL1 according to the input frame. 11. Set the LCD_DATABUS_WIDTH appropriately: 0 = 16-bit output, 1 = 8-bit output, 2 = 18-bit output, 3 = 24-bit output. 12. Enable the necessary IRQs. 33.2.5.2 MPU Read Mode The following initialization steps should be done to enter the MPU read mode of operation: Initialization steps: 1. To select the pins and their directions for talking to the LCD panel, set the appropriate bits in the HW_PINCTRL_MUXSELx registers in the PINCTRL block. 2. Start the CLK_DIS_LCDIFn and set the appropriate frequency by programming the registers in CLKCTRL. 3. Start the HCLK and set the appropriate frequency by programming the registers in CLKCTRL. 4. Bring the LCDIF out of soft reset and clock gate. 5. Reset the LCD controller by setting LCDIF_CTRL1_RESET bit appropriately, being careful to observe the reset requirements of the controller. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2453 Operation 6. Set the READ_WRITEB bit in HW_LCDIF_CTRL register to 1. 7. Select the DMA mode by making the LCDIF_MASTER bit in HW_LCDIF_CTRL register 0. 8. Also, set the DATA_SHIFT_DIR and SHIFT_NUM_BITS if it is required to shift the data left or right before it is output. 9. Indicate if the read data needs to color-space-converted and stored in a different RGB format by setting the READ_MODE_OUTPUT_IN_RGB_FORMAT field accordingly. 10. Set the WORD_LENGTH field appropriately: 0 = 16-bit input, 1 = 8-bit input, 2 = 18-bit input, 3 = 24-bit input if READ_MODE_OUTPUT_IN_RGB_FORMAT is required. Also, select the correct 16/18/24 bit data format with the corresponding fields in HW_LCDIF_CTRL register. 11. Set the READ_MODE_NUM_PACKED_SUBWORDS field in HW_LCDIF_CTRL2 according to the number of subwords per word required to be packed. 12. Set the READ_PACK_DIR to 1 if it is required to store the data in big-endian format. 13. Set the LCD_DATABUS_WIDTH appropriately: 0 = 16-bit output, 1 = 8-bit output, 2 = 18-bit output, 3 = 24-bit output. 14. Enable the necessary IRQs. 33.2.6 MPU Interface The MPU interface is used to transfer data and commands between the internal buffer of LCD controller/display and the MPU or vice versa at relatively lower speeds. LCDIF can support the 6800 as well as the 8080 MPU protocol. If DOTCLK_MODE, DVI_MODE and VSYNC_MODE bits in HW_LCDIF_CTRL registers are 0, it implies that the block is in MPU interface mode of operation. The LCDIF MPU mode has four basic timing parameters: Setup and Hold for the Command/Data register selection (TCS, TCH) and Setup and Hold for the Data bus (TDS, TDH). These parameters are expressed in CLK_DIS_LCDIFn cycles. The LCD_WR signal is used as the write strobe while LCD_RS signal is typically used to switch between command and data modes. Figure 33-11 shows the timing-related information in the write mode of both 6800 and 8080 protocols. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2454 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) IDLE START W1+ W3 WR/RD LATCH W2 WR/RD LATCH STOP IDLE VSYNC_PULSE_WIDTH LCD_VSYNC LCD_RS TCS TCH LCD_CS LCD_WR (8080) LCD_WR (6800) TDSW TDHW TDSW Data0 LCD_DATA[23:0] TDHW Data1 Figure 33-11. LCD Interface Signals in MPU Write Mode IDLE START W1+W3 WR/RD LATCH W2 WR/RD LATCH STOP IDLE LCD_RS TCS TCH LCD_CS LCD_RD_E (8080) LCD_WR_RWn (8080) LCD_RD_E (6800) LCD_WR_RWn (6800) TDSR TDHR Data0 LCD_DATA[15:0] TDSR TDHR Data1 Figure 33-12. LCD Interface Signals in MPU Read Mode The LCDIF has flexible pin and strobe timings which enable it to optimally support a wide range of LCDs. The minimum cycle time is two CLK_DIS_LCDIFn cycles (TDS=TDH=1). For example, this results in a maximum LCD data rate of 12 MB/s when CLK_DIS_LCDIFn is 24 MHz. TDS and TDH are 8-bit values, so the minimum LCDIF i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2455 Operation period is 510 CLK_DIS_LCDIFn cycles (47 KHz with a 24 MHz CLK_DIS_LCDIFn). The timings are not automatically adjusted if the CLK_DIS_LCDIFn frequency changes, so it may be necessary to adjust the timings if CLK_DIS_LCDIFn changes. In the MPU interface mode, the HW_LCDIF_CTRL_ BYPASS_COUNT bit must be 0. The RUN bit is cleared automatically once the LCDIF has received/transmitted all the data as per the HW_LCDIF_TRANSFER_COUNT register and has completed the transfer to the panel. The current transfer can be cancelled/aborted if the RUN bit is manually made 0. 33.2.6.1 Code Example to Initialize the LCDIF in MPU Write Mode // Note: Common initialization steps in Initializing the LCDIF must also be // executed along with the following code BF_CS1(LCDIF_CTRL, DATA_SELECT, 1); // 0 if sending command, 1 if sending data. Note that the // idle state for LCD_RS signal is high, regardless of the // programming of the DATA_SELECT register. BF_CS1 (LCDIF_CTRL, MODE86, 8080_MODE); BF_CS1 (LCDIF_CTRL, READ_WRITEB, 0); BF_CS1 (LCDIF_CTRL, BYPASS_COUNT, 0); //Must be 0 in MPU mode BF_CS1 (LCDIF_CTRL1, BUSY_ENABLE, 1);//Only if LCD controller implements a busy line BF_CS4 (LCDIF_TIMING, CMD_HOLD, 2, CMD_SETUP, 2, DATA_HOLD, 2, DATA_SETUP, 2); //Values based // on CLK_DIS_LCDIFn frequency and timing requirements of controller. // Note that these register must be non-zero for correct operation. BF_CS2 (LCDIF_TRANSFER_COUNT, H_COUNT, 320, V_COUNT, 240); //For a 320 RGB x 240 display BF_CS1 (LCDIF_CTRL, RUN, 1); The LCDIF is now ready to receive data through DMA writes to the HW_LCDIF_DATA register or fetch data directly from memory as a bus master. Also, note that, while in soft DMA mode, the software will need to poll the FIFO STATUS bits to ensure that it does not overflow the LCDIF data buffers. When LCDIF is done transmitting H_COUNT x V_COUNT pixels, it will stop, turn off the RUN bit and assert the cur_frame_done interrupt. 33.2.7 VSYNC Interface The VSYNC interface uses the same protocol as the MPU interface, with an additional signal VSYNC at the frame rate of the display, as shown in Figure 33-11. It is used in the moving picture display mode where data has to be written to the internal LCD buffer at a speed higher than the display rate and displayed in synchronization with the VSYNC signal. This mode is selected by setting the VSYNC_MODE bit in HW_LCDIF_CTRL register. The VSYNC signal is programmable for period, polarity and direction. Many other programmable parameters are shared with the MPU interface. The VSYNC_OEB i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2456 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) bit in HW_LCDIF_VDCTRL0 register indicates whether the display controller will send the VSYNC signal, or whether it should be generated by LCDIF. The timing of the VSYNC signal is based on the CLK_DIS_LCDIFn (make sure VSYNC_PULSE_WIDTH_UNIT = VSYNC_PERIOD_UNIT = 0 and VSYNC_ONLY = 1) and it is determined by the VSYNC_PERIOD, VSYNC_PULSE_WIDTH and VSYNC_POL fields in HW_LCDIF_VDCTRL0-4 registers. The SYNC_SIGNALS_ON bit in HW_LCDIF_VDCTRL4 register must be set if the target requires the VSYNC signal to be generated by LCDIF. If the WAIT_FOR_VSYNC_EDGE bit in HW_LCDIF_CTRL register is set, it indicates that the hardware should wait until it sees the leading VSYNC edge before starting the data transfer. The VERITCAL_WAIT_CNT indicates the number of CLK_DIS_LCDIFn cycles from the leading VSYNC edge after which data transfer will be started on the interface. In the VSYNC interface mode, the HW_LCDIF_CTRL_ BYPASS_COUNT bit must be 0. The RUN bit is cleared automatically once the LCDIF has received/transmitted all the data as per the HW_LCDIF_TRANSFER_COUNT register and has completed the transfer to the panel. The current transfer can be cancelled/aborted if the RUN bit is manually made 0. 33.2.7.1 Code Example to initialize LCDIF in VSYNC mode // Note: Common initialization steps in Initializing the LCDIF must also be // executed along with the following code BF_CS1 (LCDIF_CTRL, DATA_SELECT, 1); // 0 if sending command, 1 if sending data. Note that //the idle state for LCD_RS signal is high, regardless of the programming of the DATA_SELECT //register. BF_CS1 (LCDIF_CTRL, MODE86, 8080_MODE); BF_CS1 (LCDIF_CTRL, BYPASS_COUNT, 0); //Must be 0 in MPU mode BF_CS1 (LCDIF_CTRL1, BUSY_ENABLE, 0); BF_CS4 (LCDIF_TIMING, CMD_HOLD, 2, CMD_SETUP, 2, DATA_HOLD, 2, DATA_SETUP, 2); //Values //based on CLK_DIS_LCDIFn frequency and timing requirements of controller. Note that these register //must be non-zero for the MPU and VSYNC modes. BF_CS2 (LCDIF_TRANSFER_COUNT, H_COUNT, 320, V_COUNT, 240);//For a 320 RGB x 240 display //The following section indicates setting up the VSYNC signal timing when VSYNC is an output BF_CS1 (LCDIF_VDCTRL0, VSYNC_OEB, 0); //Making VSYNC signal an output BF_CS1 (LCDIF_VDCTRL4, VSYNC_ONLY, 1); //Only need to generate VSYNC signal BF_CS1 (VDCTRL0, VSYNC_POL, 0); //Setting the polarity of VSYNC signal to be low during //VSYNC_PULSE_WIDTH time BF_CS2 (LCDIF_VDCTRL0, VSYNC_PERIOD_UNIT, 0, VSYNC_PULSE_WIDTH_UNIT, 0); BF_CS2 (LCDIF_VDCTRL1, VSYNC_PERIOD, 400000, VSYNC_PULSE_WIDTH, 100);//Frame display rate in //terms of number of CLK_DIS_LCDIFns. BF_CS2 (LCDIF_VDCTRL2, HSYNC_PULSE_WIDTH, 0, HSYNC_PERIOD, 0); BF_CS1 (LCDIF_VDCTRL3, VERTICAL_WAIT_CNT, 50); BF_CS1 (LCDIF_VDCTRL4, SYNC_SIGNALS_ON, 1); BF_CS2 (LCDIF_CTRL, VSYNC_MODE, 1, WAIT_FOR_VSYNC_EDGE, 1); //set WAIT_FOR_VSYNC_EDGE if //software wishes to transfer the next frame after the VSYNC edge occurs. BF_CS1 (LCDIF_CTRL, RUN, 1); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2457 Operation The LCDIF is now ready to receive data through DMA writes to the HW_LCDIF_DATA register or fetch data directly from memory as a bus master. When LCDIF is done transmitting H_COUNT x V_COUNT pixels, it will stop, turn off the RUN bit and assert the cur_frame_done interrupt. 33.2.8 DOTCLK Interface The DOTCLK interface is another mode used in moving picture displays. It includes the VSYNC, HSYNC, DOTCLK and (optional) ENABLE signals. The interface is popularly called the RGB interface if the ENABLE signal is present. Figure 33-13 shows the DOTCLK protocol with its programmable parameters. One Frame (VSYNC) Period Vertical Front Porch Vertical Back Porch VSYNC VSYNC Pulse Width HSYNC DOTCLK Vertical Valid Data Count ENABLE VSYNC Wait Count D7-D0 VSYNC_POL = 0 One Line (HSYNC) Period HSYNC_POL = 0 DOTCLK_POL = 0 HSYNC Pulse Width ENABLE_POL = 0 HSYNC DOTCLK ENABLE HSYNC Wait Count D7-D0 Horizontal Valid Data Count Figure 33-13. LCD Interface Signals in DOTCLK Mode i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2458 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) The DOTCLK mode writes data at high speed to the LCD, and the display operation is synchronized with the VSYNC, HSYNC, ENABLE and DOTCLK signals. The polarities, periods and pulse-widths of the sync signals are programmable using the HW_LCDIF_VDCTRL0-4 registers. The units for the VSYNC signal must be number of horizontal lines and can be selected using the VSYNC_PULSE_WIDTH_UNIT and VSYNC_PERIOD_UNIT bit fields. The VERTICAL_WAIT_CNT is by default given the same unit as the VSYNC_PERIOD. The CLK_DIS_LCDIFn is controlled using the HW_CLKCTRL_PIX, HW_CLKCTRL_FRAC, and HW_CLKCTRL_CLKSEQ registers in the CLCKTRL block. In DOTCLK mode, HW_LCDIF_CTRL_BYPASS_COUNT bit must be set to 1. To end the current transfer, the software should make the DOTCLK_MODE bit 0, so that all data that is currently in the LCDIF LFIFO and TXFIFO is transmitted. Once that transfer is complete, the block will automatically clear the RUN bit and issue the cur_frame_done interrupt. 33.2.8.1 Code Example The following code shows an example for programming a 320x240 display. Note that setting up the display must be done through the MPU mode or through SPI. // Note: Common initialization steps in Initializing the LCDIF must also be // executed along with the following code BF_CS1 (LCDIF_CTRL, DOTCLK_MODE, 1); BF_CS1 (LCDIF_CTRL, BYPASS_COUNT, 1); //Always for DOTCLK mode BF_CS1 (LCDIF_VDCTRL0, VSYNC_OEB, 0); //Vsync is always an output in the DOTCLK mode BF_CS4 (LCDIF_VDCTRL0, VSYNC_POL, 0, HSYNC_POL, 0, DOTCLK_POL, 0, ENABLE_POL, 0); BF_CS1 (LCDIF_VDCTRL0, ENABLE_PRESENT, 1); BF_CS2 (LCDIF_VDCTRL0, VSYNC_PERIOD_UNIT, 1, VSYNC_PULSE_WIDTH_UNIT, 1); BF_CS1 (LCDIF_VDCTRL0, VSYNC_PULSE_WIDTH, 2); BF_CS1 (LCDIF_VDCTRL1, VSYNC_PERIOD, 280); BF_CS2 (LCDIF_VDCTRL2, HSYNC_PULSE_WIDTH, 10, HSYNC_PERIOD, 360); //Assuming LCD_DATABUS_WIDTH // is 24bit BF_CS2 (LCDIF_VDCTRL3, VSYNC_ONLY, 0); BF_CS2 (LCDIF_VDCTRL3, HORIZONTAL_WAIT_CNT, 20, VERTICAL_WAIT_CNT, 20); BF_CS1 (LCDIF_VDCTRL4, DOTCLK_H_VALID_DATA_CNT, 320);//Note that DOTCLK_V_VALID_DATA_CNT is //implicitly assumed to be HW_LCDIF_TRANSFER_COUNT_V_COUNT BF_CS1 (LCDIF_VDCTRL4, SYNC_SIGNALS_ON, 1); BF_CS1 (LCDIF_CTRL, RUN, 1); To stop the transfer completely, the ideal way is to make DOTCLK_MODE = 0. In that case, the block will transmit whatever it had in its FIFO, turn off the RUN bit and toggle the dma_end_cmd signal indicating to the DMA that it is done with the transfer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2459 Operation 33.2.9 ITU-R BT.656 Digital Video Interface (DVI) ITU-R BT.656 Digital Video Interface shown below transmits 4:2:2 YCbCr digital component video to a digital video encoder that can translate it into 525/60 or 625/50 analog TV signal. Unique timing codes (timing reference signals) are embedded within the video stream to indicate the different timing events that would have been otherwise indicated by VSYNC, HSYNC and BLANK signals. The hardware supports 8-bit data transfers; the pins are shared with the lower 8 bits of LCD data bus. The LCD_RS pin is shared with the clock signal of the interface (called CCIRCLK here for uniqueness). CCIRCLK also can be obtained on the LCD_DOTCK pin. The mode shares the write FIFO with the LCD interface and the associated pipeline. The programmable parameters in registers HW_LCDIF_DVICTRL0-3 allow setting the total number of horizontal lines per frame, vertical and horizontal blanking interval, odd and even field start and end positions, and so on. In short, these parameters are provided to ensure that the hardware has enough flexibility to generate the right 525/60 or 625/50 data streams. Most of the initialization steps in Initializing the LCDIF such as data shifting, swizzle, and so on, are applicable to DVI mode also. The register descriptions in the programmable registers section at the end of this chapter include example code for programming the DVICTRL0-3 registers. In DVI mode, HW_LCDIF_CTRL_BYPASS_COUNT bit must be set to 1. To end the current transfer, the software should make the DVI_MODE bit the value 0, so that all data that is currently in the LCDIF LFIFO and TXFIFO is transmitted. Once that transfer is complete, the block will automatically clear the RUN bit and assert the cur_frame_done interrupt. H ControlSignal Start of Digital Line EAV Code F F 0 0 0 0 4 X Y Blanking 8 0 Next Line Start of Digital Active Line 1 0 8 0 1 0 SAV Code 8 0 1 0 F F 0 0 0 0 4 268 (280) X Y Co-Sited C B Y C R Co-Sited Y C B Y C R Y C B Y F F Digital Video Stream 1440 1716 (1728) Figure 33-14. LCDIF Interface Signals in ITU-R BT.656 Digital Video Interface Mode i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2460 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) 33.2.10 LCDIF Pin Usage by Interface Mode The following table shows the pin usage for all of the supported modes when the PINCTRL registers are programmed for LCD functionality. See Pin Control and GPIO Overview for a more complete description of pin multiplexing options and how to program each pin individually. The VSYNC signal has been mapped onto two pins, LCD_BUSY and LCD_VSYNC. The pin multiplexing can be programmed to select either of those pins to function as VSYNC. NOTE There is an option to internally mux the HSYNC, DOTCLK and ENABLE signals in the DOTCLK mode by setting the MUX_SYNC_SIGNALS bit in the VDCTRL0 register. There is also an option to internally mux the LCD_WR_RWn and LCD_RD_E pins in the CTRL1 register for backward compatibility. Table 33-1. Pin Usage in System Mode and VSYNC Mode 8-bit 16-bit 18-bit 24-bit 8-bit 16-bit 18-bit 24-bit MPU MPU MPU MPU VSYNC VSYNC VSYNC VSYNC LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF LCD_RS LCD_ RS LCD_ RS LCD_ RS LCD_RS LCD_RS LCD_ RS LCD_RS LCD_RS LCD_CS LCD_CS LCD_CS LCD_ CS LCD_CS LCD_CS LCD_CS LCD_ CS LCD_CS LCD_WR LCD_WR LCD_WR LCD_WR LCD_WR LCD_WR LCD_WR LCD_WR LCD_WR _RWn _RWn _RWn _RWn _RWn _RWn _RWn _RWn _RWn PIN NAME LCD_RD_E LCD_VSYNC * LCD_RD_E LCD_RD_E LCD_RD_E LCD_RD_E LCD_RD_E LCD_RD_E LCD_RD_E LCD_RD_E LCD_ LCD_ LCD_ LCD_ VSYNC VSYNC VSYNC VSYNC X X X X X X X X X X X X X X X X X X X X X LCD_D23 X X X LCD_D23 LCD_D22 X X X LCD_D22 X X X LCD_D22 LCD_D21 X X X LCD_D21 X X X LCD_D21 LCD_D20 X X X LCD_D20 X X X LCD_D20 LCD_D19 X X X LCD_D19 X X X LCD_D19 LCD_D18 X X X LCD_D18 X X X LCD_D18 LCD_D17 X X LCD_D17 LCD_D17 X X LCD_D17 LCD_D17 X X X X LCD_HSYNC X X X LCD_DOTCL K X X LCD_ENABL E X LCD_D23 (Two options) Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2461 Operation Table 33-1. Pin Usage in System Mode and VSYNC Mode (continued) 8-bit 16-bit 18-bit 24-bit 8-bit 16-bit 18-bit 24-bit MPU MPU MPU MPU VSYNC VSYNC VSYNC VSYNC LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF LCD IF X X LCD_D16 LCD_D16 X X LCD_D16 LCD_D16 X LCD_D15 LCD_D15 LCD_D15 X LCD_D14 LCD_D14 LCD_D14 X LCD_D14 X LCD_D14 X LCD_D13 LCD_D13 LCD_D13 X LCD_D13 X LCD_D13 X LCD_D12 LCD_D12 LCD_D12 X LCD_D12 X LCD_D12 LCD_D11 X LCD_D11 LCD_D11 LCD_D11 X LCD_D11 X LCD_D11 LCD_D10 X LCD_D10 LCD_D10 LCD_D10 X LCD_D10 X LCD_D10 LCD_D9 X LCD_D9 LCD_D9 LCD_D9 X LCD_D9 X LCD_D9 LCD_D8 X LCD_D8 LCD_D8 LCD_D8 X LCD_D8 X LCD_D8 LCD_D7 LCD_D7 LCD_D7 LCD_D7 LCD_D7 LCD_D7 LCD_D7 LCD_D7 LCD_D7 LCD_D6 LCD_D6 LCD_D6 LCD_D6 LCD_D6 LCD_D6 LCD_D6 LCD_D6 LCD_D6 LCD_D5 LCD_D5 LCD_D5 LCD_D5 LCD_D5 LCD_D5 LCD_D5 LCD_D5 LCD_D5 LCD_D4 LCD_D4 LCD_D4 LCD_D4 LCD_D4 LCD_D4 LCD_D4 LCD_D4 LCD_D4 LCD_D3 LCD_D3 LCD_D3 LCD_D3 LCD_D3 LCD_D3 LCD_D3 LCD_D3 LCD_D3 LCD_D2 LCD_D2 LCD_D2 LCD_D2 LCD_D2 LCD_D2 LCD_D2 LCD_D2 LCD_D2 LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D0 LCD_D0 LCD_D0 LCD_D0 LCD_D0 LCD_D0 LCD_D0 LCD_D0 LCD_D0 PIN NAME LCD_D16 LCD_D15 / VSYNC* LCD_D14 / HSYNC** VSYNC (optional) LCD_D15 VSYNC (optional) LCD_D15 LCD_D13 / LCD_DOTCL K** LCD_D12 / ENABLE** LCD_RESET LCD_RESE LCD_RESE LCD_RESE LCD_RESE LCD_RESE LCD_RESE LCD_RESE LCD_RESE T T T T T T T T LCD_BUSY LCD_BUSY LCD_BUSY LCD_BUSY LCD_BUSY / LCD_VSYNC LCD_BUSY LCD_BUSY LCD_BUSY LCD_BUSY (OR optional (OR optional (OR optional (OR optional LCD_VSYN LCD_VSYN LCD_VSYN LCD_VSYN C) C) C) C) Table 33-2. Pin Usage in DOTCLK Mode and DVI Mode 8-bit DOTCLK 16-bit DOTCLK 18-bit DOTCLK 24-bit DOTCLK 8-bit DVI LCD IF LCD IF LCD IF LCD IF LCD IF LCD_RS X X X X CCIR_CLK LCD_CS X X X X X LCD_WR_RWn X X X X X LCD_RD_E X X X X X LCD_VSYNC* LCD_VSYNC LCD_VSYNC LCD_VSYNC LCD_VSYNC X PIN NAME Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2462 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) Table 33-2. Pin Usage in DOTCLK Mode and DVI Mode (continued) 8-bit DOTCLK 16-bit DOTCLK 18-bit DOTCLK 24-bit DOTCLK 8-bit DVI LCD IF LCD IF LCD IF LCD IF LCD IF LCD_HSYNC LCD_HSYNC LCD_HSYNC LCD_HSYNC LCD_HSYNC X LCD_DOTCLK LCD_DOTCLK LCD_DOTCLK LCD_DOTCLK LCD_DOTCLK X LCD_ENABLE LCD_ENABLE LCD_ENABLE LCD_ENABLE LCD_ENABLE X LCD_D23 X X X LCD_D23 X LCD_D22 X X X LCD_D22 X LCD_D21 X X X LCD_D21 X LCD_D20 X X X LCD_D20 X LCD_D19 X X X LCD_D19 X LCD_D18 X X X LCD_D18 X LCD_D17 X X LCD_D17 LCD_D17 X LCD_D16 X X LCD_D16 LCD_D16 X X LCD_D15 LCD_D15 LCD_D15 X X LCD_D14 LCD_D14 LCD_D14 X X LCD_D13 LCD_D13 LCD_D13 X LCD_D12 / ENABLE** X LCD_D12 LCD_D12 LCD_D12 X LCD_D11 X LCD_D11 LCD_D11 LCD_D11 X LCD_D10 X LCD_D10 LCD_D10 LCD_D10 X LCD_D9 X LCD_D9 LCD_D9 LCD_D9 X LCD_D8 X LCD_D8 LCD_D8 LCD_D8 X LCD_D7 LCD_D7 LCD_D7 LCD_D7 LCD_D7 LCD_D7 LCD_D6 LCD_D6 LCD_D6 LCD_D6 LCD_D6 LCD_D6 LCD_D5 LCD_D5 LCD_D5 LCD_D5 LCD_D5 LCD_D5 LCD_D4 LCD_D4 LCD_D4 LCD_D4 LCD_D4 LCD_D4 LCD_D3 LCD_D3 LCD_D3 LCD_D3 LCD_D3 LCD_D3 LCD_D2 LCD_D2 LCD_D2 LCD_D2 LCD_D2 LCD_D2 LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D1 LCD_D0 LCD_D0 LCD_D0 LCD_D0 LCD_D0 LCD_D0 LCD_RESET LCD_RESET LCD_RESET LCD_RESET LCD_RESET X LCD_BUSY LCD_BUSY LCD_BUSY LCD_BUSY (OR optional (OR optional (OR optional (OR optional LCD_VSYNC) LCD_VSYNC) LCD_VSYNC) LCD_VSYNC) PIN NAME (Two options) LCD_D15/ VSYNC* LCD_D14 / HSYNC** LCD_D13 / LCD_DOTCLK** LCD_BUSY / LCD_VSYNC X i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2463 Behavior During Reset 33.3 Behavior During Reset HCLK and CLK_DIS_LCDIF must be running before making any changes to SFTRST or CLKGATE bits. A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See the section Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. 33.4 Programmable Registers LCDIF Hardware Register Format Summary HW_LCDIF memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8003_0000 LCDIF General Control Register (HW_LCDIF_CTRL) 32 R/W C000_0000h 33.4.1/2465 8003_0010 LCDIF General Control1 Register (HW_LCDIF_CTRL1) 32 R/W 000F_0000h 33.4.2/2469 8003_0020 LCDIF General Control2 Register (HW_LCDIF_CTRL2) 32 R/W 0020_0000h 33.4.3/2472 8003_0030 LCDIF Horizontal and Vertical Valid Data Count Register (HW_LCDIF_TRANSFER_COUNT) 32 R/W 0001_0000h 33.4.4/2476 8003_0040 LCD Interface Current Buffer Address Register (HW_LCDIF_CUR_BUF) 32 R/W 0000_0000h 33.4.5/2476 8003_0050 LCD Interface Next Buffer Address Register (HW_LCDIF_NEXT_BUF) 32 R/W 0000_0000h 33.4.6/2477 8003_0060 LCD Interface Timing Register (HW_LCDIF_TIMING) 32 R/W 0000_0000h 33.4.7/2477 8003_0070 LCDIF VSYNC Mode and Dotclk Mode Control Register0 (HW_LCDIF_VDCTRL0) 32 R/W 0000_0000h 33.4.8/2478 8003_0080 LCDIF VSYNC Mode and Dotclk Mode Control Register1 (HW_LCDIF_VDCTRL1) 32 R/W 0000_0000h 33.4.9/2480 8003_0090 LCDIF VSYNC Mode and Dotclk Mode Control Register2 (HW_LCDIF_VDCTRL2) 32 R/W 0000_0000h 33.4.10/ 2481 8003_00A0 LCDIF VSYNC Mode and Dotclk Mode Control Register3 (HW_LCDIF_VDCTRL3) 32 R/W 0000_0000h 33.4.11/ 2481 8003_00B0 LCDIF VSYNC Mode and Dotclk Mode Control Register4 (HW_LCDIF_VDCTRL4) 32 R/W 0000_0000h 33.4.12/ 2482 8003_00C0 Digital Video Interface Control0 Register (HW_LCDIF_DVICTRL0) 32 R/W 0000_0000h 33.4.13/ 2484 8003_00D0 Digital Video Interface Control1 Register (HW_LCDIF_DVICTRL1) 32 R/W 0000_0000h 33.4.14/ 2484 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2464 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) HW_LCDIF memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8003_00E0 Digital Video Interface Control2 Register (HW_LCDIF_DVICTRL2) 32 R/W 0000_0000h 33.4.15/ 2485 8003_00F0 Digital Video Interface Control3 Register (HW_LCDIF_DVICTRL3) 32 R/W 0000_0000h 33.4.16/ 2486 8003_0100 Digital Video Interface Control4 Register (HW_LCDIF_DVICTRL4) 32 R/W 0000_0000h 33.4.17/ 2487 8003_0110 RGB to YCbCr 4:2:2 CSC Coefficient0 Register (HW_LCDIF_CSC_COEFF0) 32 R/W 0000_0000h 33.4.18/ 2488 8003_0120 RGB to YCbCr 4:2:2 CSC Coefficient1 Register (HW_LCDIF_CSC_COEFF1) 32 R/W 0000_0000h 33.4.19/ 2489 8003_0130 RGB to YCbCr 4:2:2 CSC Coefficent2 Register (HW_LCDIF_CSC_COEFF2) 32 R/W 0000_0000h 33.4.20/ 2490 8003_0140 RGB to YCbCr 4:2:2 CSC Coefficient3 Register (HW_LCDIF_CSC_COEFF3) 32 R/W 0000_0000h 33.4.21/ 2491 8003_0150 RGB to YCbCr 4:2:2 CSC Coefficient4 Register (HW_LCDIF_CSC_COEFF4) 32 R/W 0000_0000h 33.4.22/ 2492 8003_0160 RGB to YCbCr 4:2:2 CSC Offset Register (HW_LCDIF_CSC_OFFSET) 32 R/W 0080_0010h 33.4.23/ 2492 8003_0170 RGB to YCbCr 4:2:2 CSC Limit Register (HW_LCDIF_CSC_LIMIT) 32 R/W 00FF_00FFh 33.4.24/ 2493 8003_0180 LCD Interface Data Register (HW_LCDIF_DATA) 32 R/W 0000_0000h 33.4.25/ 2494 8003_0190 Bus Master Error Status Register (HW_LCDIF_BM_ERROR_STAT) 32 R/W 0000_0000h 33.4.26/ 2495 8003_01A0 CRC Status Register (HW_LCDIF_CRC_STAT) 32 R/W 0000_0000h 33.4.27/ 2495 8003_01B0 LCD Interface Status Register (HW_LCDIF_STAT) 32 R 9500_0000h 33.4.28/ 2496 8003_01C0 LCD Interface Version Register (HW_LCDIF_VERSION) 32 R 0400_0000h 33.4.29/ 2497 8003_01D0 LCD Interface Debug0 Register (HW_LCDIF_DEBUG0) 32 R 0E81_0000h 33.4.30/ 2498 8003_01E0 LCD Interface Debug1 Register (HW_LCDIF_DEBUG1) 32 R 0000_0000h 33.4.31/ 2501 8003_01F0 LCD Interface Debug2 Register (HW_LCDIF_DEBUG2) 32 R 0000_0000h 33.4.32/ 2502 33.4.1 LCDIF General Control Register (HW_LCDIF_CTRL) The LCD Interface Control Register provides overall control of the LCDIF block. HW_LCDIF_CTRL: 0x000 HW_LCDIF_CTRL_SET: 0x004 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2465 Programmable Registers HW_LCDIF_CTRL_CLR: 0x008 HW_LCDIF_CTRL_TOG: 0x00C The LCDIF Control Register provides a variety of control functions to the programmer. These functions allow the interface to be very flexible to work with a variety of LCD controllers, and to minimize overhead and increase performance of LCD programming. The register has been organized such that switching between the different LCD modes can be done with minimum PIO writes. Address: 8003_0000h base + 0h offset = 8003_0000h DATA_SELECT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RUN 0 0 0 0 0 0 INPUT_ DATA_ SWIZZLE LCD_ DATABUS_ WIDTH WORD_ LENGTH LCDIF_MASTER CSC_DATA_SWIZZLE R SHIFT_NUM_BITS RSRVD0 DOTCLK_MODE 16 DATA_FORMAT_24_BIT 17 VSYNC_MODE 18 DATA_FORMAT_18_BIT 19 BYPASS_COUNT 20 DATA_FORMAT_16_BIT 21 DVI_MODE 22 Reserved 23 1 W Bit 24 1 R Reset 25 RGB_TO_YCBCR422_CSC 26 DATA_SHIFT_DIR 27 WAIT_FOR_VSYNC_EDGE 28 READ_WRITEB 29 YCBCR422_INPUT 30 CLKGATE 31 SFTRST Bit W Reset 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2466 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) HW_LCDIF_CTRL field descriptions Field 31 SFTRST 30 CLKGATE 29 YCBCR422_ INPUT Description This bit must be set to zero to enable normal operation of the LCDIF. When set to one, it forces a block level reset. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. Zero implies input data is in RGB color space. One implies input data is in YCbCr 4:2:2 format, such that YCbYCr are packed in a 32-bit word. It also means that there are 2 pixels in 4 bytes. If this bit is set, software should program the H_COUNT field in the TRANSFER_COUNT register to the total number of pixels that will have to be fetched by the LCDIF block per line and the BYTE_PACKING_FORMAT should be 0xF. The WORD_LENGTH does not matter in this case. 28 By default, LCDIF is in the write mode. Setting this bit to 1 will make the hardware go into 6800/8080 READ_WRITEB system read mode. Make sure that DMA operation is selected (LCDIF_MASTER bit is 0) when performing read operations. 27 WAIT_FOR_ VSYNC_EDGE Setting this bit to 1 will make the hardware wait for the triggering VSYNC edge before starting write transfers to the LCD. Used only in the VSYNC mode of operation. 26 DATA_SHIFT_ DIR Use this bit to determine the direction of shift of transmit data. In the DVI mode, it works only on the active data, not on the timing codes and ancillary data. 25-21 SHIFT_NUM_ BITS The data to be transmitted is shifted left or right by this number of bits. 20 DVI_MODE 19 BYPASS_ COUNT 0x0 0x1 TXDATA_SHIFT_LEFT -- Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits. TXDATA_SHIFT_RIGHT -- Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. Set this bit to 1 to get into theITU-R BT.656 digital video interface mode. Toggle this bit from 1 to 0 to make the hardware go out of DVI mode after completing all data transfer, deasserting the RUN bit and toggling the dma_end_cmd signal. When this bit is 0, it means that LCDIF will stop the block operation and turn off the RUN bit after the amount of data indicated by the HW_LCDIF_TRANSFER_COUNT register has been transferred out. When this bit is set to 1, the block will continue normal operation indefinitely until it is told to stop. This bit must be 0 in system and VSYNC modes, and must be 1 in DOTCLK and DVI modes of operation. 18 Setting this bit to 1 will make the LCDIF hardware go into VSYNC mode. WAIT_FOR_VSYNC_EDGE can VSYNC_MODE be used only if this bit is set. If VSYNC signal is required to be an output from the block, SYNC_SIGNALS_ON bit in HW_LCDIF_VDCTRL4 register must be set. 17 Set this bit to 1 to make the hardware go into the DOTCLK mode, i.e. VSYNC/HSYNC/DOTCLK/ENABLE DOTCLK_MODE interface mode. ENABLE is optional, selected by the ENABLE_PRESENT bit. Toggle this bit from 1 to 0 to make the hardware go out of DOTCLK mode after completing all data transfer and deasserting the RUN bit. 16 Command Mode polarity bit. This bit should only be changed when RUN is 0. DATA_SELECT 0x0 CMD_MODE -- Command Mode. DCn signal is Low. 0x1 DATA_MODE -- Data Mode. DCn signal is High. 15-14 INPUT_DATA_ SWIZZLE This field specifies how to swap the bytes either in the HW_LCDIF_DATA register or those fetched by the AXI master part of LCDIF.The swizzle function is independent of the WORD_LENGTH bit. See the explanation of the HW_LCDIF_DATA below for names and definitions of data register fields. The supported swizzle configurations are: 0x0 0x0 0x1 0x1 NO_SWAP -- No byte swapping.(Little endian) LITTLE_ENDIAN -- Little Endian byte ordering (same as NO_SWAP). BIG_ENDIAN_SWAP -- Big Endian swap (swap bytes 0,3 and 1,2). SWAP_ALL_BYTES -- Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2467 Programmable Registers HW_LCDIF_CTRL field descriptions (continued) Field Description 0x2 0x3 13-12 CSC_DATA_ SWIZZLE HWD_SWAP -- Swap half-words. HWD_BYTE_SWAP -- Swap bytes within each half-word. This field specifies how to swap the bytes after the data has been converted into an internal representation of 24 bits per pixel and before it is transmitted over the LCD interface bus. The data is always transmitted with the least significant byte/hword (half word) first after the swizzle takes place. So, INPUT_DATA_SWIZZLE takes place first on the incoming data, and then CSC_DATA_SWIZZLE is applied. The swizzle function is independent of the WORD_LENGTH or the LCD_DATABUS_WIDTH fields. If RGB_TO_YCRCB422_CSC bit is set, the swizzle occurs on the Y, Cb, Cr values. The supported swizzle configurations are: 0x0 0x0 0x1 0x1 0x2 0x3 NO_SWAP -- No byte swapping.(Little endian) LITTLE_ENDIAN -- Little Endian byte ordering (same as NO_SWAP). BIG_ENDIAN_SWAP -- Big Endian swap (swap bytes 0,3 and 1,2). SWAP_ALL_BYTES -- Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian). HWD_SWAP -- Swap half-words. HWD_BYTE_SWAP -- Swap bytes within each half-word. 11-10 LCD Data bus transfer width. LCD_DATABUS_ 0x0 16_BIT -- 16-bit data bus mode. WIDTH 0x1 8_BIT -- 8-bit data bus mode. 0x2 18_BIT -- 18-bit data bus mode. 0x3 24_BIT -- 24-bit data bus mode. 9-8 Input data format. WORD_LENGTH 0x0 16_BIT -- Input data is 16 bits per pixel. 0x1 8_BIT -- Input data is 8 bits wide. 0x2 18_BIT -- Input data is 18 bits per pixel. 0x3 24_BIT -- Input data is 24 bits per pixel. 7 Set this bit to 1 to enable conversion from RGB to YCbCr colorspace. See the HW_LCDIF_CSC_ RGB_TO_ registers for further details. YCBCR422_CSC 6 Reserved This field is reserved. Reserved, always set to zero. 5 Set this bit to make the LCDIF act as a bus master. If this bit is reset, the LCDIF will act in its traditional LCDIF_MASTER DMA slave mode. 4 RSRVD0 Reserved bits. Write as 0. 3 DATA_ FORMAT_16_ BIT When this bit is 1 and WORD_LENGTH = 0, it implies that the the 16-bit data is in ARGB555 format. When this bit is 0 and WORD_LENGTH = 0, it implies that the 16-bit data is in RGB565 format. When WORD_LENGTH is not 0, this bit is a dont care. 2 DATA_ FORMAT_18_ BIT Used only when WORD_LENGTH = 2, i.e. 18-bit. 0x0 0x1 LOWER_18_BITS_VALID -- Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data. UPPER_18_BITS_VALID -- Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2468 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) HW_LCDIF_CTRL field descriptions (continued) Field 1 DATA_ FORMAT_24_ BIT Description Used only when WORD_LENGTH = 3, i.e. 24-bit. Note that this applies to both packed and unpacked 24bit data. 0x0 0x1 0 RUN ALL_24_BITS_VALID -- Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits. DROP_UPPER_2_BITS_PER_BYTE -- Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in each byte do not contain any useful data, and should be dropped. When this bit is set by software, the LCDIF will start fetching data in either the DMA mode or the bus master mode and sending it across the interface. This bit must remain set for all the time the block is in operation. 33.4.2 LCDIF General Control1 Register (HW_LCDIF_CTRL1) The LCDIF Control Register provides overall control of the LCDIF block. HW_LCDIF_CTRL1: 0x010 HW_LCDIF_CTRL1_SET: 0x014 HW_LCDIF_CTRL1_CLR: 0x018 HW_LCDIF_CTRL1_TOG: 0x01C The LCDIF Control1 Register provides additional programming to the LCDIF. It implements some bits which are unlikely to change often in a particular application. It also carries interrupt-related bits which are common across more than one mode of operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2469 Programmable Registers Address: 8003_0000h base + 10h offset = 8003_0010h FIFO_CLEAR IRQ_ON_ALTERNATE_FIELDS 0 0 0 0 0 0 0 0 0 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUSY_ENABLE MODE86 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 W BYTE_PACKING_FORMAT START_INTERLACE_FROM_SECOND_FIELD 16 INTERLACE_FIELDS 17 RECOVER_ON_UNDERFLOW 18 VSYNC_EDGE_IRQ 19 BM_ERROR_IRQ 20 CUR_FRAME_DONE_IRQ 21 BM_ERROR_IRQ_EN 22 UNDERFLOW_IRQ 23 COMBINE_MPU_WR_STRB 24 0 R Reset 25 0 W Bit 26 0 RSRVD1 R Reset 27 OVERFLOW_IRQ 28 VSYNC_EDGE_IRQ_EN 29 CUR_FRAME_DONE_IRQ_EN 30 UNDERFLOW_IRQ_EN 31 OVERFLOW_IRQ_EN Bit RSRVD0 0 0 0 HW_LCDIF_CTRL1 field descriptions Field 31-28 RSRVD1 Description Reserved bits. Write as 0. 27 If this bit is not set, the write strobe will be driven on LCD_WR_RWn pin in the 8080 mode and on the COMBINE_ LCD_RD_E pin in the 6800 mode. If it is set, the write strobe of both the 6800 and 8080 modes will be MPU_WR_STRB driven only on the LCD_WR_RWn pin. Note that this does not work for read strobe. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2470 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) HW_LCDIF_CTRL1 field descriptions (continued) Field Description 26 BM_ERROR_ IRQ_EN This bit is set to enable bus master error interrupt in the LCDIF master mode. 25 BM_ERROR_ IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software by writing a one to its SCT clear address. This bit will be set when the LCDIF is in master mode and an error response was returned by the slave. 0x0 0x1 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. 24 Set this bit to enable the LCDIF block to recover in the next field/frame if there was an underflow in the RECOVER_ON_ current field/frame. UNDERFLOW 23 INTERLACE_ FIELDS Set this bit if it is required that the LCDIF block fetches odd lines in one field and even lines in the other field. It will work only in LCDIF_MASTER is set to 1. 22 The default is to grab the odd lines first and then the even lines. Set this bit if it is required to grab the even START_ lines first and then the odd lines. (Line numbers start from 1, so odd lines are 1,3,5,etc. and even lines are INTERLACE_ 2,4,6, etc.) FROM_ SECOND_FIELD 21 FIFO_CLEAR Set this bit to clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO. 20 IRQ_ON_ ALTERNATE_ FIELDS If this bit is set, the LCDIF block will assert the cur_frame_done interrupt only on alternate fields, otherwise it will issue the interrupt on both odd and even field. This bit is mostly relevant if INTERLACE_FIELDS is set. This feature is only available in DOTCLK and DVI modes. 19-16 BYTE_ PACKING_ FORMAT This bitfield is used to show which data bytes in the 32-bit word written in the HW_LCDIF_DATA register are valid and should be transmitted. Default value 0xf indicates that all bytes are valid. For 8-bit transfers, any combination in this bitfield will mean valid data is present in the corresponding bytes. In the 16-bit mode, a 16-bit half-word is valid only if adjacent bits [1:0] or [3:2] or both are 1. A value of 0x0 will mean that none of the bytes are valid and should not be used. For example, set the bit field value to 0x7 if the display data is arranged in the 24-bit unpacked format (A-R-G-B where A value does not have be transmitted). When input data is is in YCbCr 4:2:2 format (YCBCR422_INPUT is 1), H_COUNT should be the number of pixels that should be fetched by the block and the BYTE_PACKING_FORMAT should be 0xF.(Note - YCBCR422_INPUT = 1 implies 2 pixels per 32 bits). 15 OVERFLOW_ IRQ_EN This bit is set to enable an overflow interrupt in the TXFIFO in the write mode. 14 This bit is set to enable an underflow interrupt in the TXFIFO in the write mode. UNDERFLOW_ IRQ_EN 13 This bit is set to 1 enable an interrupt every time the hardware enters in the vertical blanking state. CUR_FRAME_ DONE_IRQ_EN 12 This bit is set to enable an interrupt every time the hardware encounters the leading VSYNC edge in the VSYNC_EDGE_ VSYNC and DOTCLK modes, or the beginning of every field in DVI mode. IRQ_EN 11 OVERFLOW_ IRQ This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software by writing a one to its SCT clear address. A latency FIFO (LFIFO) overflow in the write mode (system/ VSYNC/DOTCLK/DVI mode) was detected, data samples have been lost. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2471 Programmable Registers HW_LCDIF_CTRL1 field descriptions (continued) Field Description 0x0 0x1 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. 10 This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software UNDERFLOW_ by writing a one to its SCT clear address. A TXFIFO underflow in the write mode (system/VSYNC/ IRQ DOTCLK/DVI mode) was detected. Could produce an error in the DOTCLK / DVI modes. 0x0 0x1 9 CUR_FRAME_ DONE_IRQ NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software by writing a one to its SCT clear address. It indicates that the hardware has completed transmitting the current frame and is in the vertical blanking period in the DOTCLK/DVI modes. In the VSYNC and system modes, this IRQ is asserted at the end of the data transfer indicated by HW_LCDIF_TRANSFER_COUNT register. 0x0 0x1 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. 8 This bit is set to indicate that an interrupt is requested by the LCDIF block. This bit is cleared by software VSYNC_EDGE_ by writing a one to its SCT clear address. It is set whenever the leading VSYNC edge is detected in the IRQ VSYNC and DOTCLK modes. In the DVI mode, it is asserted every time the block enters a new field. 0x0 0x1 7-3 RSRVD0 NO_REQUEST -- No Interrupt Request Pending. REQUEST -- Interrupt Request Pending. Reserved bits. Write as 0. 2 This bit enables the use of the interface's busy signal input. This should be enabled for LCD controllers BUSY_ENABLE that implement a busy line (to stall the LCDIF from sending more data until ready). Otherwise this bit should be cleared. 0x0 0x1 1 MODE86 This bit is used to select between the 8080 and 6800 series of microprocessor modes. This bit should only be changed when RUN is 0. 0x0 0x1 0 RESET BUSY_DISABLED -- The busy signal from the LCD controller will be ignored. BUSY_ENABLED -- Enable the use of the busy signal from the LCD controller. 8080_MODE -- Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively. 6800_MODE -- Pins LCD_WR_RWn and LCD_RD_E function as Read/Writeb and active high Enable signals respectively. Reset bit for the external LCD controller. This bit can be changed at any time. It CANNOT be reset by SFTRST. 0x0 0x1 LCDRESET_LOW -- LCD_RESET output signal is low. LCDRESET_HIGH -- LCD_RESET output signal is high. 33.4.3 LCDIF General Control2 Register (HW_LCDIF_CTRL2) The LCDIF Control Register provides overall control of the LCDIF block. HW_LCDIF_CTRL2: 0x020 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2472 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) HW_LCDIF_CTRL2_SET: 0x024 HW_LCDIF_CTRL2_CLR: 0x028 HW_LCDIF_CTRL2_TOG: 0x02C The LCDIF Control2 Register provides additional programming to the LCDIF. It implements some bits which are unlikely to change often in a particular application. 31 30 29 28 27 26 25 24 23 22 21 20 OUTSTANDING_ REQS RSRVD5 R 19 18 17 16 RSRVD4 Bit BURST_LEN_8 Address: 8003_0000h base + 20h offset = 8003_0020h ODD_LINE_ PATTERN W Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2473 8 0 0 0 7 6 5 4 3 2 1 0 RSRVD0 9 RSRVD1 11 EVEN_LINE_ PATTERN 10 READ_MODE_6_BIT_INPUT 12 READ_MODE_OUTPUT_IN_RGB_FORMAT 13 RSRVD2 R 14 RSRVD3 15 Bit READ_PACK_DIR Programmable Registers READ_MODE_ NUM_PACKED_ SUBWORDS INITIAL_DUMMY_ READ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_CTRL2 field descriptions Field 31-24 RSRVD5 Description Reserved bits. Write as 0. 23-21 This bitfield indicates the maximum number of outstanding transactions that LCDIF should request when OUTSTANDING_ it is acting as a bus master. Default is 2 outstanding transactions. REQS 0x0 REQ_1 -- 0x1 REQ_2 -- 0x2 REQ_4 -- 0x3 REQ_8 -- 0x4 REQ_16 -- 20 BURST_LEN_8 19 RSRVD4 18-16 ODD_LINE_ PATTERN By default, when the LCDIF is in the bus master mode, it will issue AXI bursts of length 16 (except when in packed 24 bpp mode, it will issue bursts of length 15). When this bit is set to 1, the block will issue bursts of length 8 (except when in packed 24 bpp mode, it will issue bursts of length 9). Note that this bitfield is only applicable when LCDIF_MASTER is set to 1. Reserved bits. Write as 0. This field determines the order of the RGB components of each pixel in ODD lines (line numbers 1,3,5,..). This bitfield must be 0 in DVI mode. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2474 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) HW_LCDIF_CTRL2 field descriptions (continued) Field Description 0x0 0x1 0x2 0x3 0x4 0x5 15 RSRVD3 14-12 EVEN_LINE_ PATTERN 11 RSRVD2 RGB -- RBG -- GBR -- GRB -- BRG -- BGR -- Reserved bits. Write as 0. This field determines the order of the RGB components of each pixel in EVEN lines (line numbers 2,4,6,..). This bitfield must be 0 in DVI mode. 0x0 0x1 0x2 0x3 0x4 0x5 RGB -- RBG -- GBR -- GRB -- BRG -- BGR -- Reserved bits. Write as 0. 10 The default value of 0 indicates data is stored in the little endian format. When LCD_DATABUS_WIDTH READ_PACK_DIR is 8-bit, this bit provides the option of rearranging the data byte-wise in the big endian format. For example, if READ_MODE_NUM_PACKED_SUBWORDS = 3 and the order of incoming data is 0x11, 0x22 and 0x33, then setting this bit to 1 will cause the data to be stored as 0x00112233 as opposed to the default 0x00332211. This operation occurs after the shifting operation done by SHIFT_NUM_BITS bitfield. 9 READ_MODE_ OUTPUT_IN_ RGB_FORMAT Setting this bit will enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield. This feature is not available when WORD_LENGTH is set to 8 bits. LCDIF performs this operation of converting to RGB format after the endianness has been determined by the READ_PACK_DIR bitfield. 8 Setting this bit to 1 indicates to LCDIF that even though LCD_DATABUS_WIDTH is set to 8 bits, the READ_MODE_6_ input data is actually only 6 bits wide and exists on D5-D0. BIT_INPUT 7 RSRVD1 6-4 READ_MODE_ NUM_PACKED_ SUBWORDS Reserved bits. Write as 0. Indicates the number of valid 8/16/18/24-bit subwords that will be packed in the 32-bit HW_LCDIF_DATA register in the read mode. The subword size (8,16, 18 or 24 bits) is determined by the LCD_DATABUS_WIDTH field. The swizzle operation is performed after READ_MODE_NUM_PACKED_SUBWORDS number of data has been received from the interface and stored in the little-endian format. For example, if LCD_DATABUS_WIDTH is set to 8-bit and data to be read back has to be stored in memory in 24-bit unpacked RGB format, set READ_MODE_NUM_PACKED_SUBWORDS to 0x3 so that each 32-bit word will contain only 3 valid bytes (RGB). Maximum value of READ_MODE_NUM_PACKED_SUBWORDS is 4 for 8-bit databus, 2 for 16-bit databus and 1 for 18/24-bit databus. 3-1 The value in this field determines the number of dummy 8/16/18/24-bit subwords that have to be read INITIAL_DUMMY_ back from the LCD panel/controller. They will then not be stored in the read FIFO. READ 0 RSRVD0 Reserved bits. Write as 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2475 Programmable Registers 33.4.4 LCDIF Horizontal and Vertical Valid Data Count Register (HW_LCDIF_TRANSFER_COUNT) This register tells the LCDIF how much data will be sent for this frame, or transaction. The total number of words is a product of the V_COUNT and H_COUNT fields. The word size is specified by the WORD_LENGTH field. This register gives the dimensions of the input frame. For normal operation, but V_COUNT and H_COUNT should be non-zero. Address: 8003_0000h base + 30h offset = 8003_0030h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 V_COUNT 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 H_COUNT 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_TRANSFER_COUNT field descriptions Field Description 31-16 V_COUNT Number of horizontal lines per frame which contain valid data. In DOTCLK mode, V_COUNT should be the same as the number of active horizontal lines in a progressive frame. In DVI mode, V_COUNT should be the number of active horizontal lines per frame, and not per field. H_COUNT Total valid data (pixels) in each horizontal line. The data size is given by the WORD_LENGTH. When input data is is in YCbCr 4:2:2 format (YCBCR422_INPUT is 1), H_COUNT should be the number of 32-bit words that should be fetched by the block and the BYTE_PACKING_FORMAT should be 0xF. In 24-bit packed format (WORD_LENGTH=0x3, BYTE_PACKING_FORMAT=0xF), the H_COUNT must be a multiple of 4 pixels. In 16-bit packed format (WORD_LENGTH=0x0, BYTE_PACKING_FORMAT=0xF), the H_COUNT must be a multiple of 2 pixels. 33.4.5 LCD Interface Current Buffer Address Register (HW_LCDIF_CUR_BUF) This register indicates the address of the current frame that is being transmitted by LCDIF. When the LCDIF is behaving as a master, this address points to the address of the current frame of data being sent out through the LCDIF. When the current frame is done, the LCDIF block will assert the cur_frame_done interrupt for software to take action. The block will also copy the HW_LCDIF_NEXT_BUF_ADDR into this bitfield so that the software can program the next frame address into the HW_LCDIF_NEXT_BUF_ADDR bitfield. This address must always be double-word aligned. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2476 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) Address: 8003_0000h base + 40h offset = 8003_0040h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_CUR_BUF field descriptions Field Description ADDR start address of current buffer 33.4.6 LCD Interface Next Buffer Address Register (HW_LCDIF_NEXT_BUF) This register indicates the address of next frame that will be transmitted by LCDIF. When the LCDIF is behaving as a master, this address points to the address of the next frame of data that will be sent out through the LCDIF. It is upto the software to make sure that this register is programmed before the end of the current frame, otherwise it might result in old data going out the LCDIF. This address must always be double-word aligned. Address: 8003_0000h base + 50h offset = 8003_0050h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_NEXT_BUF field descriptions Field ADDR Description start address of next buffer 33.4.7 LCD Interface Timing Register (HW_LCDIF_TIMING) The LCD interface timing register controls the various setup and hold times enforced by the LCD interface in the 6800/8080 system and VSYNC modes of operation. The values used in this register are dependent on the particular LCD controller used, consult the users manual for the particular controller for required timings. Each field of the register must be non-zero, therefore the minimum value is: 0x01010101. NOTE: the timings are not automatically adjusted if the CLK_DIS_LCDIFn frequency changes--it i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2477 Programmable Registers may be necessary to adjust the timings if CLK_DIS_LCDIFn changes. NOTE: Each field in this register must be non-zero for the system and VSYNC modes to function. The settings in this register do not affect the DOTCLK and DVI modes. Address: 8003_0000h base + 60h offset = 8003_0060h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 CMD_HOLD 0 0 0 0 0 21 20 19 18 17 16 15 14 CMD_SETUP 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 DATA_HOLD 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 DATA_SETUP 0 0 0 0 0 0 0 0 HW_LCDIF_TIMING field descriptions Field Description 31-24 CMD_HOLD Number of CLK_DIS_LCDIFn cycles that the DCn signal is active after CEn is deasserted. 23-16 CMD_SETUP Number of CLK_DIS_LCDIFn cycles that the the DCn signal is active before CEn is asserted. 15-8 DATA_HOLD Data bus hold time in CLK_DIS_LCDIFn cycles. Also the time that the data strobe is de-asserted in a cycle DATA_SETUP Data bus setup time in CLK_DIS_LCDIFn cycles. Also the time that the data strobe is asserted in a cycle. 33.4.8 LCDIF VSYNC Mode and Dotclk Mode Control Register0 (HW_LCDIF_VDCTRL0) This register is used to control the VSYNC and DOTCLK modes of the LCDIF so as to work with different types of LCDs like moving picture displays and delta pixel displays. HW_LCDIF_VDCTRL0: 0x070 HW_LCDIF_VDCTRL0_SET: 0x074 HW_LCDIF_VDCTRL0_CLR: 0x078 HW_LCDIF_VDCTRL0_TOG: 0x07C This register gives general programmability to the VSYNC signal including polarity, direction, pulse width, etc. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2478 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) Address: 8003_0000h base + 70h offset = 8003_0070h 21 20 19 18 17 16 HALF_LINE_MODE 22 HALF_LINE 23 VSYNC_PULSE_WIDTH_UNIT 24 VSYNC_PERIOD_UNIT 25 ENABLE_POL 26 DOTCLK_POL Bit 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 RSRVD2 RSRVD1 W Reset 28 HSYNC_POL 29 VSYNC_POL R 30 ENABLE_PRESENT 31 VSYNC_OEB Bit VSYNC_ PULSE_ WIDTH R VSYNC_PULSE_WIDTH W Reset 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_VDCTRL0 field descriptions Field 31-30 RSRVD2 29 VSYNC_OEB Description Reserved bits. Write as 0. 0 means the VSYNC signal is an output, 1 means it is an input. Should be set to 0 in the DOTCLK mode. 0x0 0x1 VSYNC_OUTPUT -- The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block. VSYNC_INPUT -- The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. 28 ENABLE_ PRESENT Setting this bit to 1 will make the hardware generate the ENABLE signal in the DOTCLK mode, thereby making it the true RGB interface along with the remaining three signals VSYNC, HSYNC and DOTCLK. 27 VSYNC_POL Default 0 active low during VSYNC_PULSE_WIDTH time and will be high during the rest of the VSYNC period. Set it to 1 to invert the polarity. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2479 Programmable Registers HW_LCDIF_VDCTRL0 field descriptions (continued) Field Description 26 HSYNC_POL Default 0 active low during HSYNC_PULSE_WIDTH time and will be high during the rest of the HSYNC period. Set it to 1 to invert the polarity. 25 DOTCLK_POL Default is data launched at negative edge of DOTCLK and captured at positive edge. Set it to 1 to invert the polarity. Set it to 0 in DVI mode. 24 ENABLE_POL Default 0 active low during valid data transfer on each horizontal line. 23-22 RSRVD1 Reserved bits. Write as 0. 21 VSYNC_ PERIOD_UNIT Default 0 for counting VSYNC_PERIOD in terms of CLK_DIS_LCDIFn cycles. Set it to 1 to count in terms of complete horizontal lines. CLK_DIS_LCDIFn cycles should be used in the VSYNC mode, while horizontal line should be used in the DOTCLK mode. 20 Default 0 for counting VSYNC_PULSE_WIDTH in terms of CLK_DIS_LCDIFn cycles. Set it to 1 to count in VSYNC_PULSE_ terms of complete horizontal lines. WIDTH_UNIT 19 HALF_LINE Setting this bit to 1 will make the total VSYNC period equal to the VSYNC_PERIOD field plus half the HORIZONTAL_PERIOD field (i.e. VSYNC_PERIOD field plus half horizontal line), otherwise it is just VSYNC_PERIOD. Should be only used in the DOTCLK mode, not in the VSYNC interface mode. 18 HALF_LINE_ MODE When this bit is 0, the first field (VSYNC period) will end in half a horizontal line and the second field will begin with half a horizontal line. When this bit is 1, all fields will end with half a horizontal line, and none will begin with half a horizontal line. VSYNC_PULSE_ Number of units for which VSYNC signal is active. For the DOTCLK mode, the unit is determined by the WIDTH VSYNC_PULSE_WIDTH_UNIT. If the VSYNC_PULSE_WIDTH_UNIT is 0 for DOTCLK mode, VSYNC_PULSE_WIDTH must be less than HSYNC_PERIOD. For the VSYNC interface mode, it should be in terms of number of CLK_DIS_LCDIFn cycles only. 33.4.9 LCDIF VSYNC Mode and Dotclk Mode Control Register1 (HW_LCDIF_VDCTRL1) This register is used to control the VSYNC signal in the VSYNC and DOTCLK modes of the block. This register determines the period and duty cycle of the VSYNC signal when it is generated in the block. Address: 8003_0000h base + 80h offset = 8003_0080h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSYNC_PERIOD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_VDCTRL1 field descriptions Field Description VSYNC_PERIOD Total number of units between two positive or two negative edges of the VSYNC signal. If HALF_LINE is set, it is implicitly calculated to be VSYNC_PERIOD plus half HSYNC_PERIOD. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2480 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) 33.4.10 LCDIF VSYNC Mode and Dotclk Mode Control Register2 (HW_LCDIF_VDCTRL2) This register is used to control the HSYNC signal in the DOTCLK mode of the block. This register determines the period and duty cycle of the HSYNC signal when it is generated in the block. Address: 8003_0000h base + 90h offset = 8003_0090h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 HSYNC_PULSE_WIDTH 0 0 0 0 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 HSYNC_PERIOD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_VDCTRL2 field descriptions Field Description 31-18 Number of CLK_DIS_LCDIFn cycles for which HSYNC signal is active. HSYNC_PULSE_ WIDTH HSYNC_PERIOD Total number of CLK_DIS_LCDIFn cycles between two positive or two negative edges of the HSYNC signal. 33.4.11 LCDIF VSYNC Mode and Dotclk Mode Control Register3 (HW_LCDIF_VDCTRL3) This register is used to determine the vertical and horizontal wait counts. This register determines the back porches of HSYNC and VSYNC signals when they are generated by the block. 31 R 30 29 28 RSRVD0 VSYNC_ONLY Bit MUX_SYNC_SIGNALS Address: 8003_0000h base + A0h offset = 8003_00A0h 0 0 W Reset 0 0 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 HORIZONTAL_WAIT_CNT 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2481 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 R VERTICAL_WAIT_CNT W Reset 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_VDCTRL3 field descriptions Field 31-30 RSRVD0 29 MUX_SYNC_ SIGNALS 28 VSYNC_ONLY Description Reserved bits, write as 0. When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins. This feature can be used to maintain backward compatability with 37xx. This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation. 27-16 In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HORIZONTAL_ HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving WAIT_CNT picture information begins. VERTICAL_ WAIT_CNT In the VSYNC interface mode, wait for this number of CLK_DIS_LCDIFn cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set. Minimum is CMD_SETUP+5. In the DOTCLK mode, it accounts for the veritcal back porch lines plus the number of horizontal lines before the moving picture begins. The unit for this parameter is inherently the same as the VSYNC_PERIOD_UNIT. 33.4.12 LCDIF VSYNC Mode and Dotclk Mode Control Register4 (HW_LCDIF_VDCTRL4) This register is used to control the DOTCLK mode of the block. This register determines the active data in each horizontal line in the DOTCLK mode. Note that the total number of active horizontal lines in the DOTCLK mode is the same as the V_COUNT bitfield in the HW_LCDIF_TRANSFER_COUNT register. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2482 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) Address: 8003_0000h base + B0h offset = 8003_00B0h 31 30 29 28 27 26 25 24 23 22 21 20 19 RSRVD0 R DOTCLK_DLY_SEL W Reset Bit 18 SYNC_SIGNALS_ON Bit 17 16 DOTCLK_H_ VALID_ DATA_CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 R DOTCLK_H_VALID_DATA_CNT W Reset 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_VDCTRL4 field descriptions Field Description 31-29 This bitfield selects the amount of time by which the DOTCLK signal should be delayed before coming out DOTCLK_DLY_ of the LCD_DOTCK pin. 0 = 2ns; 1=4ns;2=6ns;3=8ns. Remaining values are reserved. SEL 28-19 RSRVD0 Reserved bits, write as 0. 18 SYNC_ SIGNALS_ON Set this field to 1 if the LCD controller requires that the VSYNC or VSYNC/HSYNC/DOTCLK control signals should be active atleast one frame before the data transfers actually start and remain active atleast one frame after the data transfers end. The hardware does not count the number of frames automatically. Rather, the VSYNC edge interrupt can be monitored by software to count the number of frames that have occured after this bit is set and then the RUN bit can be set to start the data transactions. This bit must always be set in the DOTCLK mode of operation, and it must be set in the VSYNC mode of operation when VSYNC signal is an output. DOTCLK_H_ VALID_DATA_ CNT Total number of CLK_DIS_LCDIFn cycles on each horizontal line that carry valid data in DOTCLK mode. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2483 Programmable Registers 33.4.13 Digital Video Interface Control0 Register (HW_LCDIF_DVICTRL0) The Digital Video interface Control0 register provides the overall control of the Digital Video interface. This register gives information about the horizontal active, horizontal blanking and total number of lines in the ITU-R BT.656 interface. EXAMPLE //525/60 video system HW_LCDIF_DVICTRL0_H_ACTIVE_CNT_WR(0x5A0);//1440 HW_LCDIF_DVICTRL0_H_BLANKING_CNT_WR(0x106);//262 //625/50 video system HW_LCDIF_DVICTRL0_H_ACTIVE_CNT_WR(0x5A0);//1440 HW_LCDIF_DVICTRL0_H_BLANKING_CNT_WR(0x112);//274 Address: 8003_0000h base + C0h offset = 8003_00C0h Bit 31 30 29 28 27 26 25 24 RSRVD1 R 0 0 0 22 21 20 19 18 17 16 15 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 RSRVD0 H_ACTIVE_CNT W Reset 23 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 H_BLANKING_CNT 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_DVICTRL0 field descriptions Field 31-28 RSRVD1 Description Reserved bits, write as 0. 27-16 Number of active video samples to be transmitted. (Mostly will be 1440 for both PAL and NTSC). Must H_ACTIVE_CNT always be a multiple of 4. 15-12 RSRVD0 H_BLANKING_ CNT Reserved bits, write as 0. Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval. 33.4.14 Digital Video Interface Control1 Register (HW_LCDIF_DVICTRL1) The Digital Video interface Control1 register provides the overall control of the Digital Video interface. This register contains information about the Field1 start and end, and the Field2 start in the ITU-R BT.656 interface. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2484 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) EXAMPLE //525/60 video system HW_LCDIF_DVICTRL1_F1_START_LINE_WR(0x4);//4 HW_LCDIF_DVICTRL1_F1_END_LINE_WR(0x109);//265 HW_LCDIF_DVICTRL1_F2_START_LINE_WR(0x10A);//266 //625/50 video system HW_LCDIF_DVICTRL1_F1_START_LINE_WR(0x1);//1 HW_LCDIF_DVICTRL1_F1_END_LINE_WR(0x138);//312 HW_LCDIF_DVICTRL1_F2_START_LINE_WR(0x139);//313 Address: 8003_0000h base + D0h offset = 8003_00D0h Bit 31 R 30 29 28 27 26 RSRVD0 Bit 23 22 21 20 19 18 17 16 F1_END_LINE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R F1_END_LINE W Reset 24 F1_START_LINE W Reset 25 0 0 0 0 F2_START_LINE 0 0 0 0 0 0 0 0 HW_LCDIF_DVICTRL1 field descriptions Field 31-30 RSRVD0 Description Reserved bits, write as 0. 29-20 Vertical line number from which Field 1 begins. F1_START_LINE 19-10 F1_END_LINE Vertical line number at which Field1 ends. F2_START_LINE Vertical line number from which Field 2 begins. 33.4.15 Digital Video Interface Control2 Register (HW_LCDIF_DVICTRL2) The Digital Video interface Control2 register provides the overall control of the Digital Video interface. This register contains information about the Field2 end, and the Vertical Blanking1 interval in the ITU-R BT.656 interface. EXAMPLE //525/60 video system HW_LCDIF_DVICTRL2_F2_END_LINE_WR(0x3);//3 HW_LCDIF_DVICTRL2_V1_BLANK_START_LINE_WR(0x108);//264 HW_LCDIF_DVICTRL2_V1_BLANK_END_LINE_WR(0x11A);//282 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2485 Programmable Registers //625/50 video system HW_LCDIF_DVICTRL2_F2_END_LINE_WR(0x271);//625 HW_LCDIF_DVICTRL2_V1_BLANK_START_LINE_WR(0x137);//311 HW_LCDIF_DVICTRL2_V1_BLANK_END_LINE_WR(0x14F);//335 Address: 8003_0000h base + E0h offset = 8003_00E0h Bit 31 R 30 29 28 27 26 RSRVD0 Bit 23 22 21 20 19 18 17 16 V1_BLANK_START_LINE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 R V1_BLANK_START_LINE W Reset 24 F2_END_LINE W Reset 25 0 0 0 0 0 V1_BLANK_END_LINE 0 0 0 0 0 0 0 0 HW_LCDIF_DVICTRL2 field descriptions Field 31-30 RSRVD0 Description Reserved bits, write as 0. 29-20 F2_END_LINE Vertical line number at which Field 2 ends. 19-10 V1_BLANK_ START_LINE Vertical line number towards the end of Field1 where first Vertical Blanking interval starts. V1_BLANK_ END_LINE Vertical line number in the beginning part of Field2 where first Vertical Blanking interval ends. 33.4.16 Digital Video Interface Control3 Register (HW_LCDIF_DVICTRL3) The Digital Video interface Control3 register provides the overall control of the Digital Video interface. This register contains information about the Vertical Blanking2 interval in the ITU-R BT. 656 interface. EXAMPLE //525/60 video system HW_LCDIF_DVICTRL3_V2_BLANK_START_LINE_WR(0x1);//1 HW_LCDIF_DVICTRL3_V2_BLANK_END_LINE_WR(0x13);//19 HW_LCDIF_DVICTRL0_V_LINES_CNT_WR(0x20D);//525 //625/50 video system HW_LCDIF_DVICTRL3_V2_BLANK_START_LINE_WR(0x270);//624 HW_LCDIF_DVICTRL3_V2_BLANK_END_LINE_WR(0x16);//22 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2486 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) HW_LCDIF_DVICTRL0_V_LINES_CNT_WR(0x271);//625 Address: 8003_0000h base + F0h offset = 8003_00F0h Bit 31 R 30 29 28 27 RSRVD0 Bit 24 23 22 21 20 19 18 17 16 V2_BLANK_END_LINE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R V2_BLANK_END_LINE W Reset 25 V2_BLANK_START_LINE W Reset 26 0 0 0 0 0 V_LINES_CNT 0 0 0 0 0 0 0 HW_LCDIF_DVICTRL3 field descriptions Field 31-30 RSRVD0 Description Reserved bits, write as 0. 29-20 V2_BLANK_ START_LINE Vertical line number towards the end of Field2 where second Vertical Blanking interval starts. 19-10 V2_BLANK_ END_LINE Vertical line number in the beginning part of Field1 where second Vertical Blanking interval ends. V_LINES_CNT Total number of vertical lines per frame (generally 525 or 625) 33.4.17 Digital Video Interface Control4 Register (HW_LCDIF_DVICTRL4) The Digital Video interface Control4 register provides the overall control of the Digital Video interface. This register is used to add side borders to the output if the input frame width is less than 720 pixels. EXAMPLE //If input frame has only 640 pixels per line, but output is supposed to have 720 pixels per line. HW_LCDIF_DVICTRL4_H_FILL_CNT_WR(0x50);//80 HW_LCDIF_DVICTRL4_Y_FILL_VALUE_WR(0x10);//16 HW_LCDIF_DVICTRL4_CB_FILL_VALUE_WR(0x80);//128 HW_LCDIF_DVICTRL4_CR_FILL_VALUE_WR(0x80);//128 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2487 Programmable Registers Address: 8003_0000h base + 100h offset = 8003_0100h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 Y_FILL_VALUE 0 0 0 0 0 21 20 19 18 17 16 15 14 CB_FILL_VALUE 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 CR_FILL_VALUE 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 H_FILL_CNT 0 0 0 0 0 0 0 0 HW_LCDIF_DVICTRL4 field descriptions Field Description 31-24 Value of Y component of filler data Y_FILL_VALUE 23-16 Value of CB component of filler data CB_FILL_VALUE 15-8 Value of CR component of filler data. CR_FILL_VALUE H_FILL_CNT Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval. Must be a multiple of 4. This field will have to be programmed if the input frame has less than 720 pixels per line. 33.4.18 RGB to YCbCr 4:2:2 CSC Coefficient0 Register (HW_LCDIF_CSC_COEFF0) HW_LCDIF_CSC_COEFF0 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE HW_LCDIF_CSC_COEFF0_C0_WR(0x41);//0.257x256=65 HW_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_WR(0x3); Address: 8003_0000h base + 110h offset = 8003_0110h Bit 31 30 29 28 27 26 25 24 23 22 21 RSRVD1 R 0 0 0 0 19 18 17 16 0 0 0 0 0 C0 W Reset 20 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2488 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 W Reset 0 0 0 0 0 0 0 0 CSC_ SUBSAMPL E_FILTER RSRVD0 R 1 0 0 0 0 0 0 0 0 0 HW_LCDIF_CSC_COEFF0 field descriptions Field 31-26 RSRVD1 25-16 C0 15-2 RSRVD0 CSC_ SUBSAMPLE_ FILTER Description Reserved bits, write as 0. Two's complement red multiplier coefficient for Y Reserved bits, write as 0. This register describes the filtering and subsampling scheme to be performed on the chroma components in order to convert from YCbCr 4:4:4 to YCbCr 4:2:2 space. Note that the following descriptions apply individually to Cb and Cr. 0x0 0x1 0x2 0x3 SAMPLE_AND_HOLD -- No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with all samples numbered 2n+1. RSRVD -- Reserved INTERSTITIAL -- Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2) and that chroma value replaces the two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway between the two luma samples. COSITED -- Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4,1/2,1/4) and that chroma value exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are discarded. 33.4.19 RGB to YCbCr 4:2:2 CSC Coefficient1 Register (HW_LCDIF_CSC_COEFF1) HW_LCDIF_CSC_COEFF1 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE HW_LCDIF_CSC_COEFF1_C1_WR(0x81);//0.504x256=129 HW_LCDIF_CSC_COEFF1_C2_WR(0x19);//0.098x256=25 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2489 Programmable Registers Address: 8003_0000h base + 120h offset = 8003_0120h Bit 31 30 29 28 27 26 25 24 23 22 RSRVD1 R 0 0 0 0 20 19 18 17 16 15 14 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 RSRVD0 C2 W Reset 21 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 0 0 C1 0 0 0 0 0 0 0 0 HW_LCDIF_CSC_COEFF1 field descriptions Field Description 31-26 RSRVD1 Reserved bits, write as 0. 25-16 C2 Two's complement blue multiplier coefficient for Y 15-10 RSRVD0 Reserved bits, write as 0. C1 Two's complement green multiplier coefficient for Y 33.4.20 RGB to YCbCr 4:2:2 CSC Coefficent2 Register (HW_LCDIF_CSC_COEFF2) HW_LCDIF_CSC_COEFF2 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE HW_LCDIF_CSC_COEFF2_C3_WR(0x3DB);//-0.148x256=-37 HW_LCDIF_CSC_COEFF2_C4_WR(0x3B6);//-0.291x256=-74 Address: 8003_0000h base + 130h offset = 8003_0130h Bit 31 30 29 28 27 26 25 24 23 22 RSRVD1 R 0 0 0 0 20 19 18 17 16 15 14 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 RSRVD0 C4 W Reset 21 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 0 0 C3 0 0 0 0 0 0 0 0 HW_LCDIF_CSC_COEFF2 field descriptions Field 31-26 RSRVD1 Description Reserved bits, write as 0. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2490 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) HW_LCDIF_CSC_COEFF2 field descriptions (continued) Field Description 25-16 C4 Two's complement green multiplier coefficient for Cb 15-10 RSRVD0 Reserved bits, write as 0. C3 Two's complement red multiplier coefficient for Cb 33.4.21 RGB to YCbCr 4:2:2 CSC Coefficient3 Register (HW_LCDIF_CSC_COEFF3) HW_LCDIF_CSC_COEFF3 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE HW_LCDIF_CSC_COEFF3_C5_WR(0x70);//0.439x256=112 HW_LCDIF_CSC_COEFF3_C6_WR(0x70);//0.439x256=112 Address: 8003_0000h base + 140h offset = 8003_0140h Bit 31 30 29 28 27 26 25 24 23 22 RSRVD1 R 0 0 0 0 20 19 18 17 16 15 14 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 RSRVD0 C6 W Reset 21 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 0 0 C5 0 0 0 0 0 0 0 0 HW_LCDIF_CSC_COEFF3 field descriptions Field 31-26 RSRVD1 25-16 C6 15-10 RSRVD0 C5 Description Reserved bits, write as 0. Two's complement red multiplier coefficient for Cr Reserved bits, write as 0. Two's complement blue multiplier coefficient for Cb i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2491 Programmable Registers 33.4.22 RGB to YCbCr 4:2:2 CSC Coefficient4 Register (HW_LCDIF_CSC_COEFF4) HW_LCDIF_CSC_COEFF4 register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset This register carries programming information about RGB to YCbCr 4:2:2 CSC. EXAMPLE HW_LCDIF_CSC_COEFF4_C7_WR(0x3A2);//-0.368x256=-94 HW_LCDIF_CSC_COEFF4_C8_WR(0x3EE);//-0.071x256=-18 Address: 8003_0000h base + 150h offset = 8003_0150h Bit 31 30 29 28 27 26 25 24 23 22 RSRVD1 R 0 0 0 0 20 19 18 17 16 15 14 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 RSRVD0 C8 W Reset 21 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 0 0 C7 0 0 0 0 0 0 0 0 HW_LCDIF_CSC_COEFF4 field descriptions Field 31-26 RSRVD1 25-16 C8 15-10 RSRVD0 C7 Description Reserved bits, write as 0. Two's complement blue multiplier coefficient for Cr Reserved bits, write as 0. Two's complement green multiplier coefficient for Cr 33.4.23 RGB to YCbCr 4:2:2 CSC Offset Register (HW_LCDIF_CSC_OFFSET) HW_LCDIF_CSC_OFFSET register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset This register carries programming information about RGB to YCbCr 4:2:2 CSC. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2492 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) Address: 8003_0000h base + 160h offset = 8003_0160h Bit 31 30 29 28 27 26 25 24 23 RSRVD1 R 0 0 0 0 0 21 20 19 18 17 16 15 14 0 0 0 1 0 0 0 0 0 13 12 11 10 9 8 7 6 RSRVD0 CBCR_OFFSET W Reset 22 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 0 Y_OFFSET 0 0 0 0 0 0 1 0 HW_LCDIF_CSC_OFFSET field descriptions Field 31-25 RSRVD1 Description Reserved bits, write as 0. 24-16 Two's complement offset for the Cb and Cr components CBCR_OFFSET 15-9 RSRVD0 Y_OFFSET Reserved bits, write as 0. Two's complement offset for the Y component 33.4.24 RGB to YCbCr 4:2:2 CSC Limit Register (HW_LCDIF_CSC_LIMIT) HW_LCDIF_CSC_LIMIT register provides overall control over color space conversion from RGB to 4:2:2 YCbCr. The equations for the conversion are given by: Y = C0*R + C1*G + C2*B + Y_offset Cb= C3*R + C4*G + C5*B + CbCr_offset Cr= C6*R + C7*G + C8*B + CbCr_offset The coefficients are as follows: LCDIF_CSC_COEFF0.C0 = 0x41 LCDIF_CSC_COEFF1.C1 = 0x81 LCDIF_CSC_COEFF1.C2 = 0x19 LCDIF_CSC_COEFF2.C3 = 0x3DB LCDIF_CSC_COEFF2.C4 = 0x3B6 LCDIF_CSC_COEFF3.C5 = 0x70 LCDIF_CSC_COEFF3.C6 = 0x70 LCDIF_CSC_COEFF4.C7 = 0x3A2 LCDIF_CSC_COEFF4.C8 = 0x3EE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2493 Programmable Registers LCDIF_CSC_OFFSET.CBCR_OFFSET = 128 LCDIF_CSC_OFFSET.Y_OFFSET = 16 This register carries programming information about RGB to YCbCr 4:2:2 CSC. Note that the values in this register are unsigned. EXAMPLE HW_LCDIF_CSC_LIMIT_CBCR_MIN_WR(0x10);//16 HW_LCDIF_CSC_LIMIT_CBCR_MAX_WR(0xF0);//240 HW_LCDIF_CSC_LIMIT_Y_MIN_WR(0x10);//16 HW_LCDIF_CSC_LIMIT_Y_MAX_WR(0xEB);//235 Address: 8003_0000h base + 170h offset = 8003_0170h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 CBCR_MIN 0 0 0 0 0 21 20 19 18 17 16 15 14 13 CBCR_MAX 0 0 1 1 1 1 1 1 12 11 10 9 8 7 6 5 Y_MIN 1 1 0 0 0 0 0 4 3 2 1 0 1 1 1 Y_MAX 0 0 0 1 1 1 1 1 HW_LCDIF_CSC_LIMIT field descriptions Field Description 31-24 CBCR_MIN Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion 23-16 CBCR_MAX Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion 15-8 Y_MIN Lower limit of Y after RGB to 4:2:2 YCbCr conversion Y_MAX Upper limit of Y after RGB to 4:2:2 YCbCr conversion 33.4.25 LCD Interface Data Register (HW_LCDIF_DATA) The data sent to an external LCD controller is written to this register. Data can be written to this register (from the processor\'s perspective) as bytes half-words (16 bits) or words (32 bits) as appropriate. This register holds the 32-bit word written by either the CPU or the DMA into LCDIF. This data then gets sent out by the block across the interface. When the block is in bus master mode, this register gets the value of the lower 32 bits of the 64-bit data bus whenever it is received. Address: 8003_0000h base + 180h offset = 8003_0180h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 DATA_THREE 0 0 0 0 0 21 20 19 18 17 16 15 14 DATA_TWO 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 DATA_ONE 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 DATA_ZERO 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2494 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) HW_LCDIF_DATA field descriptions Field Description 31-24 DATA_THREE Byte 3 (most significant byte) of data written to LCDIF by the DMA or the CPU. 23-16 DATA_TWO Byte 2 of data written to LCDIF by the DMA or the CPU. 15-8 DATA_ONE Byte 1 of data written to LCDIF by the DMA or the CPU. DATA_ZERO Byte 0 (least significant byte) of data written to LCDIF by the DMA or the CPU. 33.4.26 Bus Master Error Status Register (HW_LCDIF_BM_ERROR_STAT) This register reflects the virtual address at which the AXI master received an error response from the slave. When the BM_ERROR_IRQ is asserted, the address of the bus error is updated in the register. Address: 8003_0000h base + 190h offset = 8003_0190h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_BM_ERROR_STAT field descriptions Field ADDR Description Virtual address at which bus master error occurred. 33.4.27 CRC Status Register (HW_LCDIF_CRC_STAT) This register reflects the CRC value of each frame sent out by LCDIF. The CRC is done on the final output bus, so the value will be dependent on the LCD_DATABUS_WIDTH bitfield even if the input data is the same. This register will be updated when the CUR_FRAME_DONE_IRQ is asserted. In the case of DVI mode, the CRC is calculated for the entire frame, not separately for each field in the frame. The CRC equation is as follows: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2495 Programmable Registers Address: 8003_0000h base + 1A0h offset = 8003_01A0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC_VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_CRC_STAT field descriptions Field Description CRC_VALUE Calculated CRC value. 33.4.28 LCD Interface Status Register (HW_LCDIF_STAT) The LCD interface status register can be used to check the current status of the LCDIF block. The LCD interface status register that contains read only views of some parameters or current state of the block. 30 29 28 27 26 25 24 LFIFO_FULL LFIFO_EMPTY TXFIFO_FULL TXFIFO_EMPTY BUSY DVI_CURRENT_FIELD R 31 DMA_REQ Bit PRESENT Address: 8003_0000h base + 1B0h offset = 8003_01B0h 1 0 0 1 0 1 0 1 23 22 21 20 19 18 17 16 0 0 0 RSRVD0 W Reset 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2496 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) 15 Bit 14 13 12 11 10 9 8 7 6 RSRVD0 R 5 4 3 2 1 0 0 0 0 LFIFO_COUNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_STAT field descriptions Field Description 31 PRESENT 0: LCDIF not present on this product 30 DMA_REQ Reflects the current state of the DMA Request line for the LCDIF. The DMA Request line toggles for each new request. 29 LFIFO_FULL 1: LCDIF is present. Read only view of the signal that indicates that LCD read datapath FIFO is full, will be generally used in the write mode of the LCD interface. 28 LFIFO_EMPTY Read only view of the signal that indicates that LCD read dapatath FIFO is empty, will be generally used in the read mode of the LCD interface. 27 TXFIFO_FULL Read only view of the signal that indicates that LCD write datapath FIFO is full, will be generally used in the write mode of the LCD interface. 26 Read only view of the signal that indicates that LCD write dapatath FIFO is empty, will be generally used TXFIFO_EMPTY in the read mode of the LCD interface. 25 BUSY Read only view of the input busy signal from the external LCD controller. 24 Read only view of the current field being transmitted. DVI_CURRENT_FIELD = 0 means field 1. DVI_CURRENT_ DVI_CURRENT_FIELD = 1 means field 2. FIELD 23-9 RSRVD0 LFIFO_COUNT Reserved bits. Write as 0. Read only view of the current count in Latency buffer (LFIFO). 33.4.29 LCD Interface Version Register (HW_LCDIF_VERSION) The LCD interface version register can be used to read the version of the LCDIF IP being used in this SoC. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2497 Programmable Registers The LCD interface debug register is for diagnostic use only. Address: 8003_0000h base + 1C0h offset = 8003_01C0h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of RTL version. STEP Fixed read-only value reflecting the stepping of RTL version. 33.4.30 LCD Interface Debug0 Register (HW_LCDIF_DEBUG0) The LCD interface debug0 register provides a diagnostic view of the state machine and other useful internal signals. The LCD interface debug register is for diagnostic use only. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2498 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) 30 29 28 27 26 25 24 23 SYNC_SIGNALS_ON_REG DMACMDKICK ENABLE HSYNC VSYNC CUR_FRAME_TX EMPTY_WORD R 31 WAIT_FOR_VSYNC_EDGE_OUT Bit STREAMING_END_DETECTED Address: 8003_0000h base + 1D0h offset = 8003_01D0h 0 0 0 0 1 1 1 0 1 22 21 20 19 18 17 16 0 1 CUR_STATE W Reset 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2499 13 12 Reserved 0 0 0 0 11 10 CUR_REQ_ STATE 9 MST_AVALID 14 Reserved R 15 Reserved Bit Reserved Programmable Registers 8 7 6 5 4 3 MST_OUTSTANDING_REQS 2 1 0 MST_WORDS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_DEBUG0 field descriptions Field Description 31 Read only view of the DOTCLK_MODE or DVI_MODE bit going from 1 to 0. STREAMING_ END_DETECTED 30 WAIT_FOR_ VSYNC_EDGE_ OUT Read only view of WAIT_FOR_VSYNC_EDGE bit in the VSYNC mode after it comes out of the TXFIFO. 29 Read only view of internal sync_signals_on_reg signal. SYNC_SIGNALS_ ON_REG 28 DMACMDKICK 27 ENABLE Read only view of the DMA command kick signal. Read only view of ENABLE signal. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2500 Freescale Semiconductor, Inc. Chapter 33 LCD Interface (LCDIF) HW_LCDIF_DEBUG0 field descriptions (continued) Field Description 26 HSYNC Read only view of HSYNC signal. 25 VSYNC Read only view of VSYNC signal. 24 This bit is 1 for the time the current frame is being transmitted in the VSYNC mode. Useful for VSYNC CUR_FRAME_TX mode debug. 23 EMPTY_WORD 22-16 CUR_STATE Indicates that the current word is empty. Read only view of the current state machine state in the current mode of operation. 15 Reserved This field is reserved. Reserved, always set to zero. 14 Reserved This field is reserved. Reserved, always set to zero. 13 Reserved This field is reserved. Reserved, always set to zero. 12 Reserved This field is reserved. Reserved, always set to zero. 11-10 CUR_REQ_ STATE Read only view of the request state machine. 9 MST_AVALID Read only view of the mst_avalid signal issued by the AXI bus master. 8-4 Read only view of the current outstanding requests issued by the AXI bus master. MST_ OUTSTANDING_ REQS MST_WORDS Read only view of the current bursts issued by the AXI bus master. 33.4.31 LCD Interface Debug1 Register (HW_LCDIF_DEBUG1) The LCD interface debug1 register provides a diagnostic view of the state machine and other useful internal signals. The LCD interface debug register is for diagnostic use only. Address: 8003_0000h base + 1E0h offset = 8003_01E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 H_DATA_COUNT R 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 V_DATA_COUNT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2501 Programmable Registers HW_LCDIF_DEBUG1 field descriptions Field Description 31-16 H_DATA_ COUNT Read only view of the current state of the horizontal data counter. V_DATA_ COUNT Read only view of the current state of the vertical data counter. 33.4.32 LCD Interface Debug2 Register (HW_LCDIF_DEBUG2) The LCD interface debug2 register provides a diagnostic view of the state machine and other useful internal signals. The LCD interface debug register is for diagnostic use only. Address: 8003_0000h base + 1F0h offset = 8003_01F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MST_ADDRESS R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LCDIF_DEBUG2 field descriptions Field Description MST_ADDRESS Read only view of the current address issued by the AXI bus master. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2502 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) 34.1 Pixel Pipeling (PXP) Overview The pixel pipeline is used to perform alpha blending of graphic or video buffers with graphics data before sending to an LCD display or TV encoder. The PXP also supports image rotation for hand-held devices that require both portrait and landscape image support. AXI APBH APBH Bridge/DMA PXP PXP Programmable Registers S0/ Colorspace /Scaling S0 Data S1/Overlay Control Logic RGB S1 RGB Data AXI Interface RGB Colorkey/ Alpha Blend RGB Rotation Buffers RGB Write Data Figure 34-1. Pixel Pipeline (PXP) Block Diagram i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2503 Pixel Pipeling (PXP) Overview The PXP is organized as having a background image (S0) and one or more overlay images that can be blended with the background. Each overlay image must be a multiple of the block size in pixels in both height and width and the offset of the overlay into the background image must also be a multiple of the block size in pixels. As the PXP processes data, it reads each NxN block from the background image and finds the highest priority (lowest numbered) overlay that is co-located at that block coordinate. The PXP then fetches the overlay and performs the alpha blending and color key operations on the two blocks. The resulting pixel block is then written to the corresponding block in the output buffer. For the S0 plane, the PXP supports RGB images (unscaled) or color space conversion (YUV->RGB) and scaling of YUV images. The S1 plane consists of up to eight overlay regions consisting of 16- or 32-bit RGB data. The S0 and S1 planes may then be combined by alpha blending, color key substitution, or raster operations (ROPs) to form the output image. Finally, the resulting image may be clockwise rotated in 90 degree increments and/or flipped horizontally and/or vertically. The PXP also supports letterboxing and interlacing of progressive content (by writing alternate lines to different frame buffers). The flow of data through the PXP is shown below. Overlay S1 RGB alpha blending/ color key S3 rotation Y U Scaler CSC S0 V Figure 34-2. Pixel Pipeline (PXP) Data Flow 34.1.1 Image Support The PXP's S0 buffer supports the following image formats: * 24-bit unpacked RGB (32bpp) * 24-bit packed RGB (24bpp) * 16-bit RGB in either 555 or 565 format * 3-plane YUV/YCbCr in 4:2:0 or 4:2:2 format i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2504 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) * 2-plane YUV/YCbCr in 4:2:0 or 4:2:2 format * 2-plane YUV/YCbCr in 4:2:2 format The PXP's S1 buffer supports the following image formats: * 32-bit RGB (with or without alpha) * 16-bit RGB in either 555, 565, or 1555 (alpha) The PXP's output buffer supports: * 32-bit RGB (with alpha) * 24-bit packed RGB (24bpp) * 16-bit RGB in either 565, 555, or 1555 format * YUV 4:4:4/4:2:2 1-plane * YUV 4:2:2/4:2:0 2-plane * Interlaced output processing Internally, all image data is handled as 32bpp data (either RGB or YUV, depending on output mode selection) for all steps after the color space conversion. Input RGB images are always converted to the equivalent 32bpp format before processing. 34.1.2 Block Size Selection The PXP can be configured to process blocks that are either 8x8 pixels or 16x16 pixels. The granularity of image size and location of video or overlay buffers within the final destination frame buffer has twice the precision when selecting 8x8 pixel block sizes. When selecting a 16x16 pixel block size, the accesses to fetch S0 and S1 images and write the final frame buffer are more efficient since twice as much data is requested and processed per memory request. When optimizing the system for memory bandwidth and image processing time, configure the PXP to process 16x16 pixel blocks. The control registers that are in block size units need to be programmed consistently with the BLOCK_SIZE control bit setting. If the source image is 32x32 pixels, then the width and height setting will be 4 when selecting 8x8 pixel block size and 2 when selecting 16x16 block size. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2505 Operation 34.1.3 PXP Limitations/Issues * The PXP's scalar uses a bilinear scaling algorithm and can scale YUV images from 1/4x to 4096x in 12-bit fractional steps. * When using the NEXT register, the interrupt enable setting should remain the same for all frames. If not, the PXP will change the interrupt enable register value and possibly cause the loss of an interrupt. * The PXP cannot rotate/flip video in the interlaced modes. * When performing input interlacing, the input image and overlays must be multiples of 8x16 (in 8x8 block size mode) or 16x32 (16x16 pixel blocks) pixels. Overlays must also reside on the same boundaries. 34.2 Operation The PXP operates by rendering the output frame buffer in 8x8 or 16x16 pixel macroblocks in display order (left to right, then top to bottom). At each output macroblock location, the PXP determines whether the S0 buffer is visible based on the cropping register and S0 offset parameters. If the S0 plane is visible, the PXP will fetch and process the required data from the S0 image, otherwise, the S0's contribution to the output macroblock will be the S0BACKGROUND register value. This value is effectively the color of the letterboxed region or background color. The PXP will also determine if an overlay is present for that macroblock location, and if so, instruct the S1 buffer to fetch the required data. If multiple overlays cover the macroblock, the PXP will select only the lowest numbered overlay and direct the S1 buffer to load the data for this overlay. For areas with no overlays, the S1 buffer contributes nothing to the rendered image. The following figure shows the order in which the output blocks are generated (blocks 0, 1, 2) and indicates how various blocks are rendered (blocks A-E). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2506 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) Figure 34-3. Pixel Pipeline (PXP) Macro Blocks It is important to understand how the PXP renders each output macroblock to properly understand how it accomplishes cropping, letterboxing, and overlay blending. The following sections will provide more details on these operations. The PXP also has the ability to rotate/flip images for cases when the pixel scan order is not in the traditional left-to-right/top-to-bottom raster scan (landscape raster). This can occur when a handheld device with a traditional landscape scan is rotated into a portrait orientation (in which the scan order is now bottom-to-top/left-to-right or vice versa) or when a cell phone oriented display (portrait raster) is rotated into a landscape orientation for viewing videos. In these cases, the PXP still renders the image in scan-order format (as sent to the device), but it will traverse the input images based on the transformations required. The following sections detail each of the PXP's functional capabilities. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2507 Operation 34.2.1 Pixel Handling All pixels are internally represented as 24-bit RGB or YUV/YCbCr values with an 8-bit alpha value at all stages in the PXP after the color space converter (CSC). The output format selected determines the colorspace representation of pixels after the CSC stage of the pixel pipeline. It should be noted that pixels in the YUV/YCbCr color space cannot be blended with S1 overlay pixels since this channel only processes RGB pixel formats. Input pixels are converted into the RGB format using the following rules: * 32-bit ARGB8888 pixels are read directly with no conversion for both the S0 and overlay images. * 32-bit RGB888 pixels are assumed to have an alpha value of 0xFF (full opaque). * 16-bit RGB565 and RGB555 values are expanded into the corresponding 24-bit color space and assigned an alpha value of 0xFF (opaque). The expansion process replicates the upper pixel bits into the lower pixel bits (for instance a 16-bit RGB565 triplet of 0x1F/0x20/0x07 would be expanded to 0xFF/0x82/0x39). * 16-bit RGB1555 values are expanded into the corresponding 24-bit color space and assigned an alpha value of either 0x00 or 0xFF, based on the 1-bit alpha value in the pixel. The ALPHA_MULTIPLY function is useful in this scenario to allow scaling of the opaque pixels to a semi-transparent value. Input pixels are processed in the YUV/YCbCr format using the following rules: * All pixels are processed through the scaling engine for conversion to the YUV/ YCbCr 4:4:4 24-bit format. * When not resizing the input image, the input pixels are still processed through the scaling engine to convert 4:2:2 or 4:2:0 formats to 4:4:4 formats. Essentially, the chroma values are resized to contain a unique chroma sample for each pixel site. * S1, or overlays cannot be supported in this case since S1 RGB pixels cannot be converted to YUV/YCbCr. Output pixels will retain the effective alpha value of the overlay or can be set to a programmed alpha value using the ALPHA field of the S0PARAM register. 16-bit pixels values are formed from the most significant bits of the 24-bit pixel values. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2508 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) 34.2.2 S0 Cropping/Masking The PXP's cropping operation should be viewed as a mask on the output image through which the background S0 plane can be viewed. Using this definition clarifies a subtlety on the usage of cropping an image when the image is scaled. When scaling is not used, the input and output image sizes are the same, therefore, the operation is analogous to cropping the input source image. The background output image can be cropped to a width and height independent of the image size at a given offset into the image (all sizes are in terms of block size pixel units) using the values in the S0CROP register. The XBASE and YBASE provide the coordinates of the first block to be displayed from the source image and the WIDTH and HEIGHT parameters specify an effective size of the resulting image in the output buffer. Cropping must be enabled by setting the CROP bit in the CTRL register to a 1. When not set, the visible portions of the S0 image will be rendered based on the WIDTH and HEIGHT specified in the S0SIZE field. The following figure indicates how the various cropping parameters relate to the source and RGB images (non-scaled case). S0 width RGB width s0 ybase clip ybase S0 height clip xbase clip height clip height RGB height s0 xbase clip width clip width RGB Buffer S0 Buffer Figure 34-4. Pixel Pipeline (PXP) Cropping It is important to note that when scaling an image, software must specify a valid cropping region since the PXP will default to using the source image size. When downscaling, this is not an issue, but with upscaling the resulting image will be a scaled up version of the source, but cropped to the same size as the source image as shown below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2509 Operation 320 240 320 Source Image 240 Boundary of rendered image 480 When upscaling, the CROP register should be used to properly mask the resulting scaled image. Resulting image when upscaling if the CROP register is not used (default cropping is based on input image size) 640 Resulting image when CROP register is programmed to the RGB Buffer size (CTRL_CROP=1, CROP_XBASE=0, CROP_YBASE=0 CROP_WIDTH=RGB Width CROP_HEIGHT=RGB Height) Figure 34-5. Pixel Pipeline (PXP) Scaling and Cropping Example The cropping extents should fall completely within the S0 buffer to avoid displaying incorrect data. The PXP hardware does not check for these conditions and will render the image as shown in the following two diagrams. (Note that the cropping width and height can be viewed as applying to the input buffer only because it is not scaled. In actuality, it is applied to the output buffer). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2510 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) S0 width RGB width s0 ybase s0 xbase crop width S0 height crop ybase crop height crop xbase RGB height S0 Buffer crop width RGB Buffer crop height If the clipping extents fall outside the S0 buffer (vertically), data beyond the S0 buffer will be fetched when rendering the S0 plane. S0 width RGB width s0 ybase s0 xbase crop width S0 height crop ybase crop height crop xbase RGB height S0 Buffer crop width crop height data aliases to here RGB Buffer If the clipping area extends outside the S0 buffer in the horizontal direction, the data read will effectively "wrap" to the next lines in the S0 buffer. Figure 34-6. Invalid PXP Cropping Examples 34.2.3 Scaling The PXP can scale YUV images from 1/4x to about 4096x using a bilinear scaling algorithm. The hardware is capable of scaling with 12-bit fractional resolution, or in 1/4096th pixel increments with independent scaling ratios for the X and Y direction. The scaler also implements an initial offset, which can be useful when scaling by powers of 2 in order to ensure that the resulting pixels are averages (select 1/2 pixel offset) of the source pixels instead of producing a decimated or replicated image. Also, the offset can be used to achieve per pixel addressing on the input source image. The scaling parameter is specified to the hardware in terms of the inverse of the scaling ratio desired. This can also be viewed as the step size between computed sample values. For instance, when scaling by 2x the inverse is 1/2, therefore the scaler will increment by 1/2 pixel steps across the input image and compute the bilinear average for each sample point. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2511 Operation The scaling values are represented by 12-bit fractional values in the scaling register and hardware. The scaling ratios are computed as the input size divided by the output size. The resulting decimal value must then be converted into a 12-bit fixed point value by multiplying by 212 or 4096 to produce the value programmed into the scaling registers. To scale an image from 400x300 to 320x200, the horizontal XSCALE factor is computed as InputSize XSCALE = OutputSize x 4096 = 400 320 x 4096 = 5120 x 4096 = 0x0140 _ 0000 The vertical YSCALE can be similarly computed as InputSize YSCALE = OutputSize x 4096 = 300 200 x 4096 = 6144 x 4096 = 0x0180 _ 0000 The scaler will use the CROP_XBASE and CROP_YBASE values as an offset into the source S0 image for the origin of the input image to be scaled. The CROP_WIDTH and CROP_HEIGHT parameters will be used to determine the extent of the scaled image in the output buffer. It is tempting to view the cropping width and height as being applied to the input buffer, but this is incorrect -- the PXP uses these values as a mask on the output buffer to determine which regions of the output buffer require data from the scaled input image. To enable scaling, the HW_PXP_CTRL_SCALE bit must be set and the desired scaling ratios written into the HW_PXP_S0SCALE registers. Initial offsets should be programmed into the HW_PXP_S0OFFSET register. 34.2.4 Color Space Conversion (CSC) The CSC module receives scaled YUV/YCbCr444 pixels from the scale engine and converts the pixels to the RGB888 color space. These pixels are loaded into the pixel FIFO for processing by the alpha blend module. The CSC module can also be bypassed to allow pixel output formats in the YUV/YCbCr color space. The following equations are used to perform YUV/YCbCr -> RGB conversion. The constants will be stored in the PXP control registers as two's complement values to allow flexibility in the implementation and to allow for differences in the video encode and decode operations. In addition, this provides a software mechanism to manipulate brightness or contrast. R = C0(Y+Yoffset) + C1(V+UVoffset) G = C0(Y+Yoffset) + C3(U+UVoffset) + C2(V+UVoffset) B = C0(Y+Yoffset) + C4(U+UVoffset) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2512 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) Note In the equations above, U and V are synonymous with Cb and Cr in regards to the color space format of the source frame buffer. Saturation of each color channel is checked and corrected for excursions outside the nominal YUV/YCbCr color spaces. Overflow for the three channels are saturated at 0x255 and underflow is saturated at 0x00. The following table indicates the expected coefficients for YUV and YCbCr modes of operation: Table 34-1. Coefficients for YUV and YCbCr Operation Coefficient YUV YCbCr Yoffset 0x000 0x1F0 (-16) UVoffset 0x000 0x180 (-128) C0 0x100 (1.00) 0x12A (1.164) C1 0x123 (1.140) 0x198 (1.596) C2 0x76B (-0.581) 0x730 (-0.813) C3 0x79B (-0.394) 0x79C (-0.392) C4 0x208 (2.032) 0x204 (2.017) By default, the PXP color space coefficients are set to support the conversion of YUV data to RGB data. If YCbCr input is present, software must change the coefficient registers appropriately (see the register definitions for values). Software must also set the YCBCR_MODE bit in the COEFF0 register to ensure proper conversion of YUV versus YCbCr data. 34.2.5 Overlays The PXP supports up to eight overlays that can be used to merge graphic data with video (or other graphic data). Each overlay consists of a rectangular area that is a multiple of On' (where n is the block size) pixels in both the vertical and horizontal directions. Overlays must also be located on NxN boundaries within the output image. As the PXP processes each NxN macroblock, it determines if any of the enabled overlays cover the block and then merges the overlay data with the background image as specified in the overlay's control registers. If multiple overlays overlap for a given NxN block, the PXP will select the lowest numbered one for the blending operation. If the desired affect is to blend the overlays together, this can be accomplished as a multi-step process using the IN_PLACE functionality (see In-place Rendering). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2513 Operation Output Buffer 0,0 1,0 2,0 3,0 4,0 5,0 0,1 1,1 2,1 3,1 4,1 5,1 0,2 1,2 S0 Buffer WIDTH=6 2,2 HEIGHT=3 3,2 XBASE=0 YBASE=1 OL2 WIDTH=1 HEIGHT=5 4,2 XBASE=4 YBASE=0 5,2 0,3 1,3 2,3 0,4 1,4 OL0 WIDTH=2 HEIGHT=2 XBASE=1 YBASE=3 2,4 OL1 WIDTH=4 HEIGHT=1 3,3 4,3 XBASE=2 YBASE=3 3,4 4,4 5,3 5,4 Background Color The S0 buffer and each overlay can be placed within the output buffer using their XBASE and YBASE registers and the dimensions of each region are set using their WIDTH and HEIGHT parameters. Overlay 0 has the highest priority (effectively it is the highest in the stacking order) and the S0 buffer and background color have the lowest priority. Overlays can be blended with the background or S0 planes, but not with each other. Effectively only a single overlay is active for each 8x8 pixel block. Figure 34-7. Pixel Pipeline Overlay Support Each overlay can perform one of three classes of operations between the overlay and the underlying background (S0) image: alpha blending, color keying, or raster operations. An overlay can be enabled by writing the address of the overlay image to the OLn register, the overlay's size and location information into the OLnSIZE register, and then setting the OLnPARAM_ENABLE bit. The OLnPARAM registers also contain further controls to select the modes of operation (below). 34.2.6 Alpha Blending The alpha value for an individual pixel represents a mathematical weighting factor applied to the S1 pixel. An alpha value of 0x00 corresponds to a transparent pixel and a value of 0xFF corresponds to an opaque pixel. The effective alpha value for an overlay pixel is determined by the ALPHA bit-field and the two ALPHA control bits in the OLnPARAM register. If the ALPHA_CTRL field is set to ALPHA_OVERRIDE, the alpha value for the pixel is taken from the ALPHA bitfield. This can be useful for applying a constant alpha to an entire image or for image formats that do not include an alpha value. If ALPHA_MULTIPLY is selected, the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2514 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) pixel's alpha value will be multiplied by the ALPHA value in order to allow scaling of the pixel's alpha or to provide better control for pixel formats such as RGB1555, which only contains a single bit of alpha. For each color channel, the equation used to blend two source pixels is defined below: E = Embedded alpha associated with S1 pixel = G * E + 0x80 G = PIO programmed global alpha (8-bit value) The result for the red channel as an example is as follows: Yr[7:0] = ( * S1.r) + ((1 - ) * S0.r) When alpha is 0xFF, the S1 pixel will not be blended with S0, but S1 will be passed as the output pixel and will not be blended with S0. In this case, S0 will be discarded. Likewise, if alpha is 0x00 for a given pixel, S0 will be loaded as the output pixel. Alpha values in the overlays are loaded from the source image for all pixel formats. For formats that do not support an alpha value, the pixel is assigned an alpha value of 0xFF (opaque). This can be modified by the overlay processing by setting either the ALPHA_MULTIPLY or ALPHA_OVERRIDE bit in the associated OLnPARAM register. 34.2.7 Color Key Pixels may be made transparent to the corresponding overlay by using the S0 color key registers. If an S0 pixel matches the range specified by the S0COLORKEYLOW and S0COLORKEYHIGH registers, the pixel from the associated overlay will be displayed. If no overlay is present for that block, a black pixel will be generated since the default overlay pixel is 0x00000000 (transparent black pixel). The most common use for this is when a bitmap does not support an alpha-field or for applications such as "green screen" where an image is substituted for a solid background color as shown below. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2515 Operation Figure 34-8. Pixel Pipeline (PXP) Color Key Example The green portion of the overlay image can be color keyed to display the contents of the S0 buffer for locations that match the color range. For this example, the color range is OL Colorkey: 00RGB Coefficient Values S0CSCCOEFF1 0x01230208 S0CSCCOEFF2 0x076b079b OL0PARAM 0x00000000 Overlay 0 disabled OL1PARAM 0x00000000 Overlay 1 disabled OL2PARAM 0x00000000 Overlay 2 disabled OL3PARAM 0x00000000 Overlay 3 disabled OL4PARAM 0x00000000 Overlay 4 disabled OL5PARAM 0x00000000 Overlay 5 disabled OL6PARAM 0x00000000 Overlay 6 disabled OL7PARAM 0x00000000 Overlay 7 disabled CTRL 0x00009003 S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 The resulting image is simply the RGB equivalent of the YUV image: Figure 34-13. Example: RGB Equivalent of YUV image 34.3.2 Basic QVGA with Overlays This example is similar to the last, but adds two overlay images, one for a logo and the other as a time counter/control bar. The two overlay images are shown below. (Note that the black background is actually transparent in the real image). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2523 Examples Figure 34-14. Example: QVGA with Overlays Table 34-5. Register Use for Conversion Register Value Description RGBBUF *example1_rgb Pointer to the output buffer. RGBSIZE 0xFF1400F0 ALPHA=0xFF WIDTH=0x140=320 HEIGHT=0x0F0=240 S0BUF *morraine_y Pointer to input Y buffer S0UBUF *morraine_u Pointer to input U buffer SOVBUF *morraine_v Pointer to input V buffer S0PARAM 0x0000281E WIDTH=0x28=40 (40*8=320 pixels) S0BACKGROUND 0x00000000 Black background region S0CROP 0x00000000 No Cropping S0CSCCOEFF0 0x04030000 YUV->RGB Coefficient Values S0CSCCOEFF1 0x01230208 S0CSCCOEFF2 0x076b079b OL0 *overlay1_rgb Pointer to control graphic OL0SIZE 0x00000A02 WIDTH=0x0A=80 pixels HEIGHT=0x1E=30 (30*8= 240 pixels) HEIGHT=0x02=16pixels OL0PARAM 0x0000FF01 ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 OL1 *logo_rgb Pointer to logo graphic OL1SIZE 0x0A181D06 XBASE=0x0A=80pixels YBASE=0x18=192pixels WIDTH=0x1D=232pixels HEIGHT=0x06=48pixels Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2524 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) Table 34-5. Register Use for Conversion (continued) Register Value Description OL1PARAM 0x0000FF01 ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 OL2PARAM 0x00000000 Overlay 2 disabled OL3PARAM 0x00000000 Overlay 3 disabled OL4PARAM 0x00000000 Overlay 4 disabled OL5PARAM 0x00000000 Overlay 5 disabled OL6PARAM 0x00000000 Overlay 6 disabled OL7PARAM 0x00000000 Overlay 7 disabled CTRL 0x00009003 S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 The resulting image is shown below. Note the presence of the overlays in the upper left and lower right corners of the image. Figure 34-15. Example: QVGA with Overlays 34.3.3 Cropped QVGA Example This example displays the same image as the first example, but does so on a portraitoriented display (240x320) without the overlays. Changes from the first example are shown in bold. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2525 Examples Table 34-6. Register Use for Conversion Register Value Description RGBBUF *example1_rgb Pointer to the output buffer. RGBSIZE 0xFF0F0140 ALPHA=0xFF WIDTH=0x0F0=240 pixels HEIGHT=0x140=320 pixels S0BUF *morraine_y Pointer to input Y buffer S0UBUF *morraine_u Pointer to input U buffer SOVBUF *morraine_v Pointer to input V buffer S0PARAM 0x0005281E YBASE=0x05=40pixels WIDTH=0x28=40 (40*8=320 pixels) HEIGHT=0x1E=30 (30*8= 240 pixels) S0BACKGROUND 0x00000000 Black background region S0CROP 0x05001E1E XBASE=0x05=40 pixels YBASE=00=0pixels WIDTH=0x1E=240pixels HEIGHT=0x1E=240 pixels S0CSCCOEFF0 0x04030000 YUV->RGB Coefficient Values S0CSCCOEFF1 0x01230208 S0CSCCOEFF2 0x076b079b OL0PARAM 0x00000000 Overlay 0 disabled OL1PARAM 0x00000000 Overlay 1 disabled OL2PARAM 0x00000000 Overlay 2 disabled OL3PARAM 0x00000000 Overlay 3 disabled OL4PARAM 0x00000000 Overlay 4 disabled OL5PARAM 0x00000000 Overlay 5 disabled OL6PARAM 0x00000000 Overlay 6 disabled OL7PARAM 0x00000000 Overlay 7 disabled CTRL 0x00089003 CROP=1 S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 In this case, we have now changed the RGB size to reflect the portrait nature of the display. The S0PARAM_YBASE has been changed to 0x05 (40 pixels) to place the S0 plane down 40 pixels from the top of the screen. The cropping register is now also used to control the cropping extents. The CROP_XBASE is set to 0x05 (40 pixels) to move the origin of the S0 buffer to the (40,0) location within the buffer. The CROP_WIDTH/ CROP_HEIGHT are also programmed to ensure that the resulting image in the output i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2526 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) buffer is cropped to 240x240 pixels. Since the image no longer covers the entire output buffer, the S0BACKGROUND register is used to letterbox the image in black. The resulting image is shown below. Figure 34-16. Example: Cropped QVGA 34.3.4 Upscale QVGA to VGA with Overlays In this example, the image will be upscaled from QVGA to VGA resolution and displayed with the two overlays from the second example. Changes from the second example are shown in bold. Table 34-7. Register Use for Conversion Register Value Description RGBBUF *example1_rgb Pointer to the output buffer. RGBSIZE 0xFF2801E0 ALPHA=0xFF WIDTH=0x280=640 HEIGHT=0x1E0=480 S0BUF *morraine_y Pointer to input Y buffer S0UBUF *morraine_u Pointer to input U buffer SOVBUF *morraine_v Pointer to input V buffer S0PARAM 0x0000281E WIDTH=0x28=40 (40*8=320 pixels) Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2527 Examples Table 34-7. Register Use for Conversion (continued) Register Value Description HEIGHT=0x1E=30 (30*8= 240 pixels) S0BACKGROUND 0x00000000 Black background region S0CROP 0x0000503C WIDTH=0x50=640pixels HEIGHT=0x3C=320pixels S0SCALE 0x08000800 XSCALE=0x0800=2x scale YSCALE=0x0800=2x scale S0CSCCOEFF0 0x04030000 YUV->RGB Coefficient Values S0CSCCOEFF1 0x01230208 S0CSCCOEFF2 0x076b079b OL0 *overlay1_rgb Pointer to control graphic OL0SIZE 0x23000A02 XBASE=0x23=280pixels WIDTH=0x0A=80 pixels HEIGHT=0x02=16pixels OL0PARAM 0x0000FF01 ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 OL1 *logo_rgb Pointer to logo graphic OL1SIZE 0x19361D06 XBASE=0x19=200pixels YBASE=0x36=432pixels WIDTH=0x1D=232pixels HEIGHT=0x06=48pixels OL1PARAM 0x0000FF01 ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 OL2PARAM 0x00000000 Overlay 2 disabled OL3PARAM 0x00000000 Overlay 3 disabled OL4PARAM 0x00000000 Overlay 4 disabled OL5PARAM 0x00000000 Overlay 5 disabled OL6PARAM 0x00000000 Overlay 6 disabled OL7PARAM 0x00000000 Overlay 7 disabled CTRL 0x000c9003 SCALE=1 CROP=1 S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2528 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) The resulting image is shown in the figure below. The overlays have moved in this image and that the overall image size is now larger than before. Figure 34-17. Example: Upscale QVGA to VGA with Overlays 34.3.5 Downscale VGA to WQVGA (480x272) to fill screen In this example, a VGA image will be downscaled to fix the extents of a 480x272 WQVGA display. This means that the aspect ratio of the resulting image will not match that of the source image, therefore the scaling factors in the horizontal and vertical directions will differ from each other. Table 34-8. Register Use for Conversion Register Value Description RGBBUF *example_rgb Pointer to the output buffer. RGBSIZE 0xFFf1E0110 ALPHA=0xFF WIDTH=0x1E0=480 HEIGHT=0x110=272 S0BUF *garden_y Pointer to input Y buffer S0UBUF *garden_u Pointer to input U buffer SOVBUF *garden_v Pointer to input V buffer S0PARAM 0x0000503C WIDTH=0x50=80=640 pixels HEIGHT=0x3C=60=480 pixels S0BACKGROUND 0x00000000 Black background region S0CROP 0x00003C22 WIDTH=0x3C=480 pixels Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2529 Examples Table 34-8. Register Use for Conversion (continued) Register Value Description HEIGHT=0x22=272 pixels S0SCALE 0x1C3C1555 YSCALE=0x1C3C=1/1.765x XSCALE=0x1555=1/1.333x S0CSCCOEFF0 0x04030000 YUV->RGB Coefficient Values S0CSCCOEFF1 0x01230208 S0CSCCOEFF2 0x076b079b OL0PARAM 0x00000000 Overlay 0 disabled OL1PARAM 0x00000000 Overlay 1 disabled OL2PARAM 0x00000000 Overlay 2 disabled OL3PARAM 0x00000000 Overlay 3 disabled OL4PARAM 0x00000000 Overlay 4 disabled OL5PARAM 0x00000000 Overlay 5 disabled OL6PARAM 0x00000000 Overlay 6 disabled OL7PARAM 0x00000000 Overlay 7 disabled CTRL 0x000C9003 SCALE=1 CROP=1 S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 Note that the scaling factors are computed as (source/dest)*4096, thus in the horizontal direction 640/480*4096=5461=0x1555. In the vertical direction, the scaling factor is computed as 480/272*4096=7228=0x1C3C. The original source image and resulting scaled images are shown below: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2530 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) Figure 34-18. Example: Downscale VGA to WQVGA (480x272) to fill screen 34.3.6 Downscale VGA to QVGA with Overlapping Overlays The final example will perform a 1/2x scaling of a VGA image to QVGA to maintain the aspect ratio. It will also add four overlays to present the image as if it were a photo album application. Table 34-9. Register Use for Conversion Register Value Description RGBBUF *example_rgb Pointer to the output buffer. RGBSIZE 0xFFf1E0110 ALPHA=0xFF WIDTH=0x1E0=480 HEIGHT=0x110=272 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2531 Examples Table 34-9. Register Use for Conversion (continued) Register Value Description S0BUF *garden_y Pointer to input Y buffer S0UBUF garden_u Pointer to input U buffer SOVBUF garden_v Pointer to input V buffer S0PARAM 0x0000503C WIDTH=0x50=80=640 pixels HEIGHT=0x3C=60=480 pixels S0BACKGROUND 0x00000040 Dark Blue background region S0CROP 0x0000281E WIDTH=0x28=320 pixels HEIGHT=0x1E=240 pixels S0SCALE 0x20002000 YSCALE=0x2000=1/2x XSCALE=0x1555=1/2x S0OFFSET 0x08000800 XOFFSET=0x0800 (1/2 pixel) YOFFSET=0x0800 (1/2 pixel) S0CSCCOEFF0 0x04030000 YUV->RGB Coefficient Values S0CSCCOEFF1 0x01230208 S0CSCCOEFF2 0x076b079b OL0 *prev_rgb Pointer to previous graphic OL0SIZE 0x0B1B0402 XBASE=0x0B=88pixels YBASE=0x1B=216pixels WIDTH=0x04=32 pixels HEIGHT=0x02=16pixels OL0PARAM 0x0000FF01 ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 OL1 *next_rgb Pointer to next graphic OL1SIZE 0x2D1B0402 XBASE=0x2D=360pixels YBASE=0x1B=216pixels WIDTH=0x04=32 pixels HEIGHT=0x02=16pixels OL1PARAM 0x0000FF01 ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 OL2 *text_overlay Pointer to text graphic OL2SIZE 0x00000A1E XBASE=0x00=0pixels YBASE=0x00=0pixels WIDTH=0x0A=80pixels HEIGHT=0x1E=240pixels Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2532 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) Table 34-9. Register Use for Conversion (continued) Register Value Description OL2PARAM 0x0000FF01 ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 OL3 *border_rgb Pointer to rectangular border graphic OL3SIZE 0x0A00281E XBASE=0x0A=80pixels YBASE=0x00=0pixels WIDTH=0x28=320pixels HEIGHT=0x1E=240pixels OL3PARAM 0x0000FF01 ALPHA=0xFF FORMAT=0x0 (RGB8888) ALPHA_CTRL=0 (embedded alpha) ENABLE=1 OL4PARAM 0x00000000 Overlay 4 disabled OL5PARAM 0x00000000 Overlay 5 disabled OL6PARAM 0x00000000 Overlay 6 disabled OL7PARAM 0x00000000 Overlay 7 disabled CTRL 0x000C9003 SCALE=1 CROP=1 S0_FORMAT=9 (YUV420) IRQ_ENABLE=1 ENABLE=1 The resulting image is shown below. The text is rendered in a transparent overlay (overlay #2) on the right side of the screen. The background color (#000040) is dark blue and shows through the overlay as the background color. Overlay #3 applies a thin white alpha-blended border around the image to frame it. Overlays #0 and #1 generate the Next> and 24*8=192 pixels) // output height is 128 (0x10->16*8=128 pixels) Address: 8002_A000h base + A0h offset = 8002_A0A0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 XBASE 0 0 0 0 20 19 18 17 16 15 14 13 YBASE 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 WIDTH 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 HEIGHT 0 0 0 0 0 0 0 0 HW_PXP_S0CROP field descriptions Field 31-24 XBASE Description This field indicates the horizontal offset (in terms of N-pixel blocks) into the S0 buffer which is considered the origin of the image. This allows selection of a subset of a source image for processing. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2547 Programmable Registers HW_PXP_S0CROP field descriptions (continued) Field Description 23-16 YBASE This field indicates the vertical offset (in terms of N-pixel blocks) into the S0 buffer which is considered the origin of the image. This allows selection of a subset of a source image for processing. 15-8 WIDTH Output buffer cropped video width (in terms of N pixel blocks, non-rotated). This field should be programmed to the desired cropped width of the S0 plane in the output buffer. When scaling is not used, this value is effectively the width of the input buffer that should appear in the output buffer. For scaling operations, it's important that this field be programmed to the width of the scaled size of the S0 output image. HEIGHT Output buffer cropped video height (in terms of N pixel blocks, non-rotated). This field should be programmed to the desired cropped height of the S0 plan in the output buffer. When scaling is not used, this value is effectively the height of the input buffer that should appear in the output buffer. For scaling operations, it's important that this field be programmed to the height of the scaled size of the S0 output image. 34.4.12 Source 0 Scale Factor Register (HW_PXP_S0SCALE) S0 Scale Factor. This register provides the scale factor for the S0 (video) buffer. The maximum down scaling factor is 1/4 such that the output image in either axis is 1/4th the size of the source. The maximum up scaling factor is 2^12 for either axis. The reciprocal of the scale factor should be loaded into this register. To reduce the S0 buffer by a factor of two in the output frame buffer, a value of 10.0000_0000_0000 should be loaded into this register. The scale up by a factor of 4, the value of 1/4, or 00.0100_0000_0000, should be loaded into this register. To scale up by 8/5, the value of 00.1010_0000_0000 should be loaded. EXAMPLE HW_PXP_S0SCALE_WR(0x10001000); HW_PXP_S0SCALE_WR(0x08000800); HW_PXP_S0SCALE_WR(0x20002000); // 1:1 scaling (0x1.000) // 2x scaling (0x0.800) // 1/2x scaling (0x2.000) Address: 8002_A000h base + B0h offset = 8002_A0B0h 31 R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSVD2 Bit YSCALE W Reset 0 0 0 1 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2548 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RSVD1 15 Bit XSCALE W Reset 0 0 0 1 0 0 0 0 0 HW_PXP_S0SCALE field descriptions Field 31 RSVD2 30-16 YSCALE 15 RSVD1 XSCALE Description Reserved, always set to zero. This is a three bit integer and 12 bit fractional representation (###.####_####_####) of the Y scaling factor for the S0 source buffer. The maximum value programmed should be 4 since scaling down by a factor greater than 4 is not supported. Reserved, always set to zero. This is a three bit integer and 12 bit fractional representation (###.####_####_####) of the X scaling factor for the S0 source buffer. The maximum value programmed should be 4 since scaling down by a factor greater than 4 is not supported. 34.4.13 Source 0 Scale Offset Register (HW_PXP_S0OFFSET) S0 Scale Offset. This register provides the initial scale offset for the S0 (video) buffer. The X and Y offset provides the ability to access the source image with a per pixel or per sub-pixel granularity. To shift the source input image by a single pixel, for example, a value of 0x200 (for 8x8 block size) would be loaded into this offset field. For a 8x8 block size, 0x200 (or 1/8), will provide a fixed offset of 1 pixel for the entire PXP operation. With this setting for 16x16 block size, the value of 0x200 will provide a fixed offset of 2 pixels since 1/8 of a 16 pixel block is 2. The fixed offset values can also be used for subpixel adjustments in the bilinear scaling filter. For example, when scaling an image down by a factor of 2, an initial offset of 0x0 would result in sub-sampling every other pixel. If a fixed offset of 0x100 (1/16) with 8x8 block size selected is programmed, all pixels are used in scaling the final output pixel value. EXAMPLE HW_PXP_S0SCALE_WR(0x20002000); HW_PXP_S0OFFSET_WR(0x01000100); // 1/2x scaling (0x2.000) // half-pixel offset for 8x8 block size in both X and Y to i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2549 Programmable Registers ensure averaging versus pixel replication Address: 8002_A000h base + C0h offset = 8002_A0C0h Bit 31 30 29 28 27 26 25 24 RSVD2 R 0 0 0 22 21 20 19 18 17 16 15 0 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 RSVD1 YOFFSET W Reset 23 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 XOFFSET 0 0 0 0 0 0 0 0 HW_PXP_S0OFFSET field descriptions Field 31-28 RSVD2 27-16 YOFFSET 15-12 RSVD1 XOFFSET Description Reserved, always set to zero. This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed block offset which gets added to the scaled block address to determine source data for the scaling engine. Reserved, always set to zero. This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed block offset which gets added to the scaled block address to determine source data for the scaling engine. 34.4.14 Color Space Conversion Coefficient Register 0 (HW_PXP_CSCCOEFF0) This register contains color space conversion coefficients in two's complement notation. The Coefficient 0 register contains coefficients used in the color space conversion algorithm. The Y and UV offsets are added to the source buffer to normalize them before the conversion. C0 is the coefficient that is used to multiply the luma component of the data for all three RGB components. EXAMPLE // // // // The equations used for Colorspace conversion are: R = C0*(Y+YOFFSET) + C1(V+UV_OFFSET) G = C0*(Y+YOFFSET) + C3(U+UV_OFFSET) + C2(V+UV_OFFSET) R = C0*(Y+YOFFSET) + C4(U+UV_OFFSET) HW_PXP_CSCCOEFF0_WR(0x04030000); // YUV coefficients: C0, Yoffset, UVoffset HW_PXP_CSCCOEFF1_WR(0x01230208); // YUV coefficients: C1, C4 HW_PXP_CSCCOEFF2_WR(0x076B079b); // YUV coefficients: C2, C3 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2550 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) Address: 8002_A000h base + D0h offset = 8002_A0D0h Bit 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD1 W YCBCR_MODE R 30 Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 Bit C0 UV_OFFSET R UV_OFFSET Y_OFFSET W Reset 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_CSCCOEFF0 field descriptions Field Description 31 Set to 1 when performing YCbCr conversion to RGB. Set to 0 when converting YUV to RGB data. This bit YCBCR_MODE changes the behavior of the scaler when performing U/V scaling. 30-29 RSVD1 Reserved, always set to zero. 28-18 C0 Two's complement Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) 17-9 UV_OFFSET Y_OFFSET Two's complement phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range) Two's complement amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is typically -16 (0x1F0) 34.4.15 Color Space Conversion Coefficient Register 1 (HW_PXP_CSCCOEFF1) This register contains color space conversion coefficients in two's complement notation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2551 Programmable Registers The Coefficient 1 register contains coefficients used in the color space conversion algorithm. C1 is the coefficient that is used to multiply the chroma (Cr/V) component of the data for the red component. C4 is the coefficient that is used to multiply the chroma (Cb/U) component of the data for the blue component. Both values should be coded as a two's complement fixed point number with 8 bits right of the decimal. EXAMPLE HW_PXP_CSCCOEFF0_WR(0x04030000); // YUV coefficients: C0, Yoffset, UVoffset HW_PXP_CSCCOEFF1_WR(0x01230208); // YUV coefficients: C1, C4 HW_PXP_CSCCOEFF2_WR(0x076B079b); // YUV coefficients: C2, C3 Address: 8002_A000h base + E0h offset = 8002_A0E0h Bit 31 30 29 28 27 26 25 24 23 22 RSVD1 R 0 0 0 0 20 19 18 17 16 15 0 0 0 1 0 0 1 14 13 12 11 10 9 8 7 6 RSVD0 C1 W Reset 21 0 0 0 1 1 0 0 0 0 5 4 3 2 1 0 0 1 0 0 0 C4 0 0 1 0 0 0 0 HW_PXP_CSCCOEFF1 field descriptions Field Description 31-27 RSVD1 Reserved, always set to zero. 26-16 C1 Two's complement Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) 15-11 RSVD0 Reserved, always set to zero. C4 Two's complement Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) 34.4.16 Color Space Conversion Coefficient Register 2 (HW_PXP_CSCCOEFF2) This register contains color space conversion coefficients in two's complement notation. The Coefficient 2 register contains coefficients used in the color space conversion algorithm. C2 is the coefficient that is used to multiply the chroma (Cr/V) component of the data for the green component. C3 is the coefficient that is used to multiply the chroma (Cb/U) component of the data for the green component. Both values should be coded as a two's complement fixed point number with 8 bits right of the decimal. EXAMPLE // NOTE: The default values for the CSCCOEFF2 register are incorrect. and C3 should be 0x79C for proper operation. C2 should be 0x76B HW_PXP_CSCCOEFF0_WR(0x04030000); // YUV coefficients: C0, Yoffset, UVoffset i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2552 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) HW_PXP_CSCCOEFF1_WR(0x01230208); // YUV coefficients: C1, C4 HW_PXP_CSCCOEFF2_WR(0x076B079b); // YUV coefficients: C2, C3 Address: 8002_A000h base + F0h offset = 8002_A0F0h Bit 31 30 29 28 27 26 25 24 23 22 RSVD1 R 0 0 0 0 20 19 18 17 16 15 0 1 1 1 1 0 0 14 13 12 11 10 9 8 7 6 RSVD0 C2 W Reset 21 1 1 0 1 1 0 0 0 0 5 4 3 2 1 0 0 1 1 0 0 C3 0 1 1 1 0 1 1 HW_PXP_CSCCOEFF2 field descriptions Field Description 31-27 RSVD1 Reserved, always set to zero. 26-16 C2 Two's complement Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) 15-11 RSVD0 Reserved, always set to zero. C3 Two's complement Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) 34.4.17 PXP Next Frame Pointer (HW_PXP_NEXT) This register contains a pointer to a data structure used to reload the PXP registers at the end of the current frame. HW_PXP_NEXT: 0x100 HW_PXP_NEXT_SET: 0x104 HW_PXP_NEXT_CLR: 0x108 HW_PXP_NEXT_TOG: 0x10C To enable this functionality, software must write this register while the PXP is processing the current data frame (if the PXP is currently idle, this will also initiate an immediate load of registers from the pointer). The process of writing this register (WRITE operation) will set a semaphore in hardware to notify the control logic that a register reload operation must be performed when the current frame processing is complete. At the end of a frame, the PXP will fetch the register settings from this location, signal an interrupt to software, then proceed with rendering the next frame of data. Software may cancel the reload operation by issuing a CLEAR operation to this register. SET and TOGGLE operations should not be used when addressing this register. All registers will be reloaded with the exception of the following: STAT, CSCCOEFFn, NEXT, i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2553 Programmable Registers VERSION. All other registers will be loaded in the order they appear in the register map. Once the pointer's contents have been loaded into the PXP's registers, the NEXT_IRQ interrupt will be issued (see the PXP_STATUS register). EXAMPLE // create register command structure in memory u32* pxp_commands0[48], pxp_commands1; u32 rc; // initialize control structure for frame 0 pxp_commands0[0] = ...; // CTRL pxp_commands0[1] = ...; // OUT Buffer ... pxp_commands0[47] = ..; // Overlay7 param2 // initialize control structure for frame 1 pxp_commands1[0] = ...; // CTRL pxp_commands1[1] = ...; // OUT Buffer ... pxp_commands1[47] = ..; // Overlay7 param2 // poll until a command isn't queued while (rc=HW_PXP_NEXT_RD() & BM_PXP_NEXT_ENABLED ); HW_PXP_NEXT_WR(pxp_commands0); // enable PXP operation 0 via command pointer // poll until first command clears while (rc=HW_PXP_NEXT_RD() & BM_PXP_NEXT_ENABLED ); HW_PXP_NEXT_WR(pxp_commands1); // enable PXP operation 1 via command pointer Address: 8002_A000h base + 100h offset = 8002_A100h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 R POINTER W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2554 Freescale Semiconductor, Inc. 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 R 1 0 ENABLED 15 Bit RSVD Chapter 34 Pixel Pipeline (PXP) 0 0 POINTER W Reset 0 0 0 0 0 0 0 0 HW_PXP_NEXT field descriptions Field Description 31-2 POINTER A pointer to a data structure containing register values to be used when processing the next frame. The pointer must be 32-bit aligned and should reside in on-chip or off-chip memory. 1 RSVD Reserved, always set to zero. 0 ENABLED Indicates that the next frame functionality has been enabled. This bit reflects the status of the hardware semaphore indicating that a reload operation is pending at the end of the current frame. 34.4.18 PXP S0 Color Key Low (HW_PXP_S0COLORKEYLOW) This register contains the color key low value for the S0 buffer. When processing an image, the if the PXP finds a pixel in the background image with a color that falls in the range from the S0COLORKEYLOW to S0COLORKEYHIGH range, it will substitute the color found in the matching overlay. If no overlay is present or if the overlay also matches its colorkey range, the s0background color is used. EXAMPLE // colorkey values between HW_PXP_S0COLORKEYLOW_WR (0x008000); // medium green and HW_PXP_S0COLORKEYHIGH_WR(0x00FF00); // light green Address: 8002_A000h base + 180h offset = 8002_A180h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 RSVD1 R 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 PIXEL W Reset 12 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2555 Programmable Registers HW_PXP_S0COLORKEYLOW field descriptions Field Description 31-24 RSVD1 Reserved, always set to zero. PIXEL Low range of RGB color key applied to S0 buffer. To disable S0 colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. 34.4.19 PXP S0 Color Key High (HW_PXP_S0COLORKEYHIGH) This register contains the color key high value for the S0 buffer. When processing an image, the if the PXP finds a pixel in the background image with a color that falls in the range from the S0COLORKEYLOW to S0COLORKEYHIGH range, it will substitute the color found in the matching overlay. If no overlay is present or if the overlay also matches its colorkey range, the s0background color is used. EXAMPLE // colorkey values between HW_PXP_S0COLORKEYLOW_WR (0x008000); // medium green and HW_PXP_S0COLORKEYHIGH_WR(0x00FF00); // light green Address: 8002_A000h base + 190h offset = 8002_A190h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 RSVD1 R 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 PIXEL W Reset 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_S0COLORKEYHIGH field descriptions Field Description 31-24 RSVD1 Reserved, always set to zero. PIXEL High range of RGB color key applied to S0 buffer. To disable S0 colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. 34.4.20 PXP Overlay Color Key Low (HW_PXP_OLCOLORKEYLOW) This register contains the color key low value for the OL buffer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2556 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) When processing an image, the if the PXP finds a pixel in the current overlay image with a color that falls in the range from the OLCOLORKEYLOW to OLCOLORKEYHIGH range, it will use the S0 pixel value for that location. If no S0 image is present or if the S0 image also matches its colorkey range, the s0background color is used. Colorkey operations are higher priority than alpha or ROP operations. EXAMPLE // colorkey values between HW_PXP_OLCOLORKEYLOW_WR (0x000000); // black and HW_PXP_OLCOLORKEYHIGH_WR(0x800000); // medium red Address: 8002_A000h base + 1A0h offset = 8002_A1A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 RSVD1 R 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 PIXEL W Reset 12 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 HW_PXP_OLCOLORKEYLOW field descriptions Field Description 31-24 RSVD1 Reserved, always set to zero. PIXEL Low range of RGB color key applied to OL buffer. Each overlay has an independent colorkey enable. 34.4.21 PXP Overlay Color Key High (HW_PXP_OLCOLORKEYHIGH) This register contains the color key high value for the OL buffer. When processing an image, the if the PXP finds a pixel in the current overlay image with a color that falls in the range from the OLCOLORKEYLOW to OLCOLORKEYHIGH range, it will use the S0 pixel value for that location. If no S0 image is present or if the S0 image also matches its colorkey range, the s0background color is used. Colorkey operations are higher priority than alpha or ROP operations. EXAMPLE // colorkey values between HW_PXP_OLCOLORKEYLOW_WR (0x000000); // black and HW_PXP_OLCOLORKEYHIGH_WR(0x800000); // medium red i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2557 Programmable Registers Address: 8002_A000h base + 1B0h offset = 8002_A1B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 RSVD1 R 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 PIXEL W Reset 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OLCOLORKEYHIGH field descriptions Field Description 31-24 RSVD1 Reserved, always set to zero. PIXEL High range of RGB color key applied to OL buffer. Each overlay has an independent colorkey enable. 34.4.22 PXP Debug Control Register (HW_PXP_DEBUGCTRL) This register controls the debug features of the PXP. This register controls the PXP Debug features. This register is not intended for customer use. EXAMPLE Address: 8002_A000h base + 1D0h offset = 8002_A1D0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 RSVD R W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2558 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) 15 14 13 12 11 10 9 RSVD R W Reset 0 0 0 0 8 7 6 5 RESET_TLB_STATS Bit 0 0 0 0 4 3 2 1 0 0 0 0 SELECT 0 0 0 0 0 HW_PXP_DEBUGCTRL field descriptions Field 31-9 RSVD 8 RESET_TLB_ STATS SELECT Description Reserved, always set to zero. Fixed read-only value reflecting the MINOR field of the RTL version. Index into one of the PXP debug registers. The data for the selected register will be returned 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0xF0 0xF1 0xF2 0xF3 0xF8 NONE -- None CTRL -- Control Debug S0REGS -- S0 Debug S0BAX -- S0 BA X Scale S0BAY -- S0 BA Y Scale PXBUF -- PXBUF Debug ROTATION -- Rotation Debug ROTBUF0 -- Rotation Buffer 0 ROTBUF1 -- Rotation Buffer 1 TLBCOUNT -- TLB Lookup Count TLBHIT -- TLB Hit Count TLBMISS -- TLB Miss Count TLBLAT -- TLB Latency Count TLBSTATE -- TLB State Information 34.4.23 PXP Debug Register (HW_PXP_DEBUG) This register returns selected debug register values. Debug register. Select the appropriate register in debug control and the values are returned here. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2559 Programmable Registers Address: 8002_A000h base + 1E0h offset = 8002_A1E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_DEBUG field descriptions Field Description DATA Debug data 34.4.24 PXP Version Register (HW_PXP_VERSION) This register always returns a known read value for debug purposes it indicates the version of the block. This register indicates the RTL version in use. EXAMPLE if (HW_PXP_VERSION.B.MAJOR != 2) Error(); Address: 8002_A000h base + 1F0h offset = 8002_A1F0h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. 34.4.25 PXP Overlay 0 Buffer Pointer (HW_PXP_OL0) Overlay 0 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 0 input buffer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2560 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE u32* overlay_ptr; HW_PXP_OLn_WR(0,overlay_ptr); Address: 8002_A000h base + 200h offset = 8002_A200h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL0 field descriptions Field Description ADDR Address pointer for the overlay 0 buffer. The address MUST be word-aligned for proper PXP operation. 34.4.26 PXP Overlay 0 Size (HW_PXP_OL0SIZE) This register contains buffer size/location information for the Overlay 0 input buffer. This register contains information about Overlay 0 indicating the size of the overlay (in NxN blocks) and the overlay's location within the output frame buffer (in NxN blocks). In 16 pixel block size mode, only the low 7 bits of each field can be used and the most significant bit must be set to 0. EXAMPLE HW_PXP_OLnSIZE_WR(0,0x10000401); // 32x8 overlay at offset +128+0 Address: 8002_A000h base + 210h offset = 8002_A210h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 XBASE 0 0 0 0 20 19 18 17 16 15 14 13 YBASE 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 WIDTH 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 HEIGHT 0 0 0 0 0 0 0 0 HW_PXP_OL0SIZE field descriptions Field Description 31-24 XBASE This field indicates the X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 23-16 YBASE This field indicates the Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2561 Programmable Registers HW_PXP_OL0SIZE field descriptions (continued) Field Description 15-8 WIDTH Indicates number of horizontal NxN blocks in the image (non-rotated). HEIGHT Indicates the number of vertical NxN blocks in the image (non-rotated). 34.4.27 PXP Overlay 0 Parameters (HW_PXP_OL0PARAM) This register contains buffer parameters for the Overlay 0 input buffer. The S1 Overlay 0 Parameter register provides additional controls for Overlay 0. EXAMPLE u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(0,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay Address: 8002_A000h base + 220h offset = 8002_A220h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 RSVD1 R ROP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2562 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) 13 12 11 10 9 8 7 6 5 4 R ALPHA FORMAT W Reset 0 0 0 0 0 0 0 0 0 0 0 3 0 0 2 1 ALPHA_ CNTL 0 0 0 ENABLE 14 ENABLE_COLORKEY 15 Bit 0 HW_PXP_OL0PARAM field descriptions Field Description 31-20 RSVD1 Reserved, always set to zero. 19-16 ROP Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 15-8 ALPHA 7-4 FORMAT MASKOL -- OL AND S0 MASKNOTOL -- nOL AND S0 MASKOLNOT -- OL AND nS0 MERGEOL -- OL OR S0 MERGENOTOL -- nOL OR S0 MERGEOLNOT -- OL OR nS0 NOTCOPYOL -- nOL NOT -- nS0 NOTMASKOL -- OL NAND S0 NOTMERGEOL -- OL NOR S0 XOROL -- OL XOR S0 NOTXOROL -- OL XNOR S0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. 0x0 0x1 0x3 0x4 0x5 ARGB8888 -- 32-bit pixels with alpha RGB888 -- 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 -- 16-bit pixels with alpha RGB565 -- 16-bit pixels without alpha RGB555 -- 16-bit pixels without alpha 3 ENABLE_ COLORKEY Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). 2-1 ALPHA_CNTL Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2563 Programmable Registers HW_PXP_OL0PARAM field descriptions (continued) Field Description Embedded -- Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override -- Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply -- Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs -- Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0x0 0x1 0x2 0x3 0 ENABLE Indicates that the overlay is active for this operation. 34.4.28 PXP Overlay 0 Parameters 2 (HW_PXP_OL0PARAM2) This register contains buffer parameters for the Overlay 0 input buffer. The Overlay 0 Parameter 2 register is reserved for future use. Address: 8002_A000h base + 230h offset = 8002_A230h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL0PARAM2 field descriptions Field RSVD Description Reserved, always set to zero. 34.4.29 PXP Overlay 1 Buffer Pointer (HW_PXP_OL1) Overlay 1 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 1 input buffer. This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE u32* overlay_ptr; HW_PXP_OLn_WR(1,overlay_ptr); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2564 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) Address: 8002_A000h base + 240h offset = 8002_A240h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL1 field descriptions Field Description ADDR Address pointer for the overlay 1 buffer. The address MUST be word-aligned for proper PXP operation. 34.4.30 PXP Overlay 1 Size (HW_PXP_OL1SIZE) This register contains buffer size/location information for the Overlay 1 input buffer. This register contains information about Overlay 1 indicating the size of the overlay (in NxN blocks) and the overlay's location within the output frame buffer (in NxN blocks). In 16 pixel block size mode, only the low 7 bits of each field can be used and the most significant bit must be set to 0. EXAMPLE HW_PXP_OLnSIZE_WR(1,0x10000401); // 32x8 overlay at offset +128+0 Address: 8002_A000h base + 250h offset = 8002_A250h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 XBASE 0 0 0 0 20 19 18 17 16 15 14 13 YBASE 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 WIDTH 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 HEIGHT 0 0 0 0 0 0 0 0 HW_PXP_OL1SIZE field descriptions Field Description 31-24 XBASE This field indicates the X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 23-16 YBASE This field indicates the Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 15-8 WIDTH Indicates number of horizontal NxN blocks in the image (non-rotated). HEIGHT Indicates the number of vertical NxN blocks in the image (non-rotated). 34.4.31 PXP Overlay 1 Parameters (HW_PXP_OL1PARAM) This register contains buffer parameters for the Overlay 1 input buffer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2565 Programmable Registers The S1 Overlay 1 Parameter register provides additional controls for Overlay 1. EXAMPLE u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(1,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay Address: 8002_A000h base + 260h offset = 8002_A260h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD1 R ROP W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ALPHA FORMAT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 ALPHA_ CNTL 0 0 ENABLE Bit 0 ENABLE_COLORKEY Reset 0 HW_PXP_OL1PARAM field descriptions Field Description 31-20 RSVD1 Reserved, always set to zero. 19-16 ROP Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. 0x0 0x1 MASKOL -- OL AND S0 MASKNOTOL -- nOL AND S0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2566 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) HW_PXP_OL1PARAM field descriptions (continued) Field Description 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 15-8 ALPHA 7-4 FORMAT MASKOLNOT -- OL AND nS0 MERGEOL -- OL OR S0 MERGENOTOL -- nOL OR S0 MERGEOLNOT -- OL OR nS0 NOTCOPYOL -- nOL NOT -- nS0 NOTMASKOL -- OL NAND S0 NOTMERGEOL -- OL NOR S0 XOROL -- OL XOR S0 NOTXOROL -- OL XNOR S0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. 0x0 0x1 0x3 0x4 0x5 ARGB8888 -- 32-bit pixels with alpha RGB888 -- 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 -- 16-bit pixels with alpha RGB565 -- 16-bit pixels without alpha RGB555 -- 16-bit pixels without alpha 3 ENABLE_ COLORKEY Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). 2-1 ALPHA_CNTL Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. 0x0 0x1 0x2 0x3 0 ENABLE Embedded -- Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override -- Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply -- Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs -- Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. Indicates that the overlay is active for this operation. 34.4.32 PXP Overlay 1 Parameters 2 (HW_PXP_OL1PARAM2) This register contains buffer parameters for the Overlay 1 input buffer. The Overlay 1 Parameter 2 register is reserved for future use. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2567 Programmable Registers Address: 8002_A000h base + 270h offset = 8002_A270h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD R W 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL1PARAM2 field descriptions Field Description RSVD Reserved, always set to zero. 34.4.33 PXP Overlay 2 Buffer Pointer (HW_PXP_OL2) Overlay 2 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 2 input buffer. This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE u32* overlay_ptr; HW_PXP_OLn_WR(2,overlay_ptr); Address: 8002_A000h base + 280h offset = 8002_A280h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL2 field descriptions Field ADDR Description Address pointer for the overlay 2 buffer. The address MUST be word-aligned for proper PXP operation. 34.4.34 PXP Overlay 2 Size (HW_PXP_OL2SIZE) This register contains buffer size/location information for the Overlay 2 input buffer. This register contains information about Overlay 2 indicating the size of the overlay (in NxN blocks) and the overlay's location within the output frame buffer (in NxN blocks). In 16 pixel block size mode, only the low 7 bits of each field can be used and the most significant bit must be set to 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2568 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) EXAMPLE HW_PXP_OLnSIZE_WR(2,0x10000401); // 32x8 overlay at offset +128+0 Address: 8002_A000h base + 290h offset = 8002_A290h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 XBASE 0 0 0 0 20 19 18 17 16 15 14 13 YBASE 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 WIDTH 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 HEIGHT 0 0 0 0 0 0 0 0 HW_PXP_OL2SIZE field descriptions Field Description 31-24 XBASE This field indicates the X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 23-16 YBASE This field indicates the Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 15-8 WIDTH Indicates number of horizontal NxN blocks in the image (non-rotated). HEIGHT Indicates the number of vertical NxN blocks in the image (non-rotated). 34.4.35 PXP Overlay 2 Parameters (HW_PXP_OL2PARAM) This register contains buffer parameters for the Overlay 2 input buffer. The S1 Overlay 2 Parameter register provides additional controls for Overlay 2. EXAMPLE u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(2,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2569 Programmable Registers Address: 8002_A000h base + 2A0h offset = 8002_A2A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD1 R ROP W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ALPHA FORMAT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 ALPHA_ CNTL 0 0 ENABLE Bit 0 ENABLE_COLORKEY Reset 0 HW_PXP_OL2PARAM field descriptions Field Description 31-20 RSVD1 Reserved, always set to zero. 19-16 ROP Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB MASKOL -- OL AND S0 MASKNOTOL -- nOL AND S0 MASKOLNOT -- OL AND nS0 MERGEOL -- OL OR S0 MERGENOTOL -- nOL OR S0 MERGEOLNOT -- OL OR nS0 NOTCOPYOL -- nOL NOT -- nS0 NOTMASKOL -- OL NAND S0 NOTMERGEOL -- OL NOR S0 XOROL -- OL XOR S0 NOTXOROL -- OL XNOR S0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2570 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) HW_PXP_OL2PARAM field descriptions (continued) Field Description 15-8 ALPHA Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. 7-4 FORMAT Indicates the input buffer format for overlay 0. ARGB8888 -- 32-bit pixels with alpha RGB888 -- 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 -- 16-bit pixels with alpha RGB565 -- 16-bit pixels without alpha RGB555 -- 16-bit pixels without alpha 0x0 0x1 0x3 0x4 0x5 3 ENABLE_ COLORKEY Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). 2-1 ALPHA_CNTL Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Embedded -- Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override -- Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply -- Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs -- Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0x0 0x1 0x2 0x3 0 ENABLE Indicates that the overlay is active for this operation. 34.4.36 PXP Overlay 2 Parameters 2 (HW_PXP_OL2PARAM2) This register contains buffer parameters for the Overlay 2 input buffer. The Overlay 2 Parameter 2 register is reserved for future use. Address: 8002_A000h base + 2B0h offset = 8002_A2B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL2PARAM2 field descriptions Field RSVD Description Reserved, always set to zero. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2571 Programmable Registers 34.4.37 PXP Overlay 3 Buffer Pointer (HW_PXP_OL3) Overlay 3 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 3 input buffer. This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE u32* overlay_ptr; HW_PXP_OLn_WR(3,overlay_ptr); Address: 8002_A000h base + 2C0h offset = 8002_A2C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL3 field descriptions Field Description ADDR Address pointer for the overlay 3 buffer. The address MUST be word-aligned for proper PXP operation. 34.4.38 PXP Overlay 3 Size (HW_PXP_OL3SIZE) This register contains buffer size/location information for the Overlay 3 input buffer. This register contains information about Overlay 3 indicating the size of the overlay (in NxN blocks) and the overlay's location within the output frame buffer (in NxN blocks). In 16 pixel block size mode, only the low 7 bits of each field can be used and the most significant bit must be set to 0. EXAMPLE HW_PXP_OLnSIZE_WR(3,0x10000401); // 32x8 overlay at offset +128+0 Address: 8002_A000h base + 2D0h offset = 8002_A2D0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 XBASE 0 0 0 0 20 19 18 17 16 15 14 13 YBASE 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 WIDTH 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 HEIGHT 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2572 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) HW_PXP_OL3SIZE field descriptions Field Description 31-24 XBASE This field indicates the X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 23-16 YBASE This field indicates the Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 15-8 WIDTH Indicates number of horizontal NxN blocks in the image (non-rotated). HEIGHT Indicates the number of vertical NxN blocks in the image (non-rotated). 34.4.39 PXP Overlay 3 Parameters (HW_PXP_OL3PARAM) This register contains buffer parameters for the Overlay 3 input buffer. The S1 Overlay 3 Parameter register provides additional controls for Overlay 3. EXAMPLE u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(3,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay Address: 8002_A000h base + 2E0h offset = 8002_A2E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 RSVD1 R ROP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2573 Programmable Registers 13 12 11 10 9 8 7 6 5 4 R ALPHA FORMAT W Reset 0 0 0 0 0 0 0 0 0 0 0 3 0 0 2 1 ALPHA_ CNTL 0 0 0 ENABLE 14 ENABLE_COLORKEY 15 Bit 0 HW_PXP_OL3PARAM field descriptions Field Description 31-20 RSVD1 Reserved, always set to zero. 19-16 ROP Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 15-8 ALPHA 7-4 FORMAT MASKOL -- OL AND S0 MASKNOTOL -- nOL AND S0 MASKOLNOT -- OL AND nS0 MERGEOL -- OL OR S0 MERGENOTOL -- nOL OR S0 MERGEOLNOT -- OL OR nS0 NOTCOPYOL -- nOL NOT -- nS0 NOTMASKOL -- OL NAND S0 NOTMERGEOL -- OL NOR S0 XOROL -- OL XOR S0 NOTXOROL -- OL XNOR S0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. 0x0 0x1 0x3 0x4 0x5 ARGB8888 -- 32-bit pixels with alpha RGB888 -- 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 -- 16-bit pixels with alpha RGB565 -- 16-bit pixels without alpha RGB555 -- 16-bit pixels without alpha 3 ENABLE_ COLORKEY Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). 2-1 ALPHA_CNTL Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2574 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) HW_PXP_OL3PARAM field descriptions (continued) Field Description Embedded -- Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override -- Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply -- Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs -- Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0x0 0x1 0x2 0x3 0 ENABLE Indicates that the overlay is active for this operation. 34.4.40 PXP Overlay 3 Parameters 2 (HW_PXP_OL3PARAM2) This register contains buffer parameters for the Overlay 3 input buffer. The Overlay 3 Parameter 2 register is reserved for future use. Address: 8002_A000h base + 2F0h offset = 8002_A2F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL3PARAM2 field descriptions Field RSVD Description Reserved, always set to zero. 34.4.41 PXP Overlay 4 Buffer Pointer (HW_PXP_OL4) Overlay 4 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 4 input buffer. This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE u32* overlay_ptr; HW_PXP_OLn_WR(4,overlay_ptr); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2575 Programmable Registers Address: 8002_A000h base + 300h offset = 8002_A300h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL4 field descriptions Field Description ADDR Address pointer for the overlay 4 buffer. The address MUST be word-aligned for proper PXP operation. 34.4.42 PXP Overlay 4 Size (HW_PXP_OL4SIZE) This register contains buffer size/location information for the Overlay 4 input buffer. This register contains information about Overlay 4 indicating the size of the overlay (in NxN blocks) and the overlay's location within the output frame buffer (in NxN blocks). In 16 pixel block size mode, only the low 7 bits of each field can be used and the most significant bit must be set to 0. EXAMPLE HW_PXP_OLnSIZE_WR(4,0x10000401); // 32x8 overlay at offset +128+0 Address: 8002_A000h base + 310h offset = 8002_A310h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 XBASE 0 0 0 0 20 19 18 17 16 15 14 13 YBASE 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 WIDTH 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 HEIGHT 0 0 0 0 0 0 0 0 HW_PXP_OL4SIZE field descriptions Field Description 31-24 XBASE This field indicates the X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 23-16 YBASE This field indicates the Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 15-8 WIDTH Indicates number of horizontal NxN blocks in the image (non-rotated). HEIGHT Indicates the number of vertical NxN blocks in the image (non-rotated). 34.4.43 PXP Overlay 4 Parameters (HW_PXP_OL4PARAM) This register contains buffer parameters for the Overlay 4 input buffer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2576 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) The S1 Overlay 4 Parameter register provides additional controls for Overlay 4. EXAMPLE u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(4,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay Address: 8002_A000h base + 320h offset = 8002_A320h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD1 R ROP W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ALPHA FORMAT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 ALPHA_ CNTL 0 0 ENABLE Bit 0 ENABLE_COLORKEY Reset 0 HW_PXP_OL4PARAM field descriptions Field Description 31-20 RSVD1 Reserved, always set to zero. 19-16 ROP Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. 0x0 0x1 MASKOL -- OL AND S0 MASKNOTOL -- nOL AND S0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2577 Programmable Registers HW_PXP_OL4PARAM field descriptions (continued) Field Description 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 15-8 ALPHA 7-4 FORMAT MASKOLNOT -- OL AND nS0 MERGEOL -- OL OR S0 MERGENOTOL -- nOL OR S0 MERGEOLNOT -- OL OR nS0 NOTCOPYOL -- nOL NOT -- nS0 NOTMASKOL -- OL NAND S0 NOTMERGEOL -- OL NOR S0 XOROL -- OL XOR S0 NOTXOROL -- OL XNOR S0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. 0x0 0x1 0x3 0x4 0x5 ARGB8888 -- 32-bit pixels with alpha RGB888 -- 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 -- 16-bit pixels with alpha RGB565 -- 16-bit pixels without alpha RGB555 -- 16-bit pixels without alpha 3 ENABLE_ COLORKEY Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). 2-1 ALPHA_CNTL Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. 0x0 0x1 0x2 0x3 0 ENABLE Embedded -- Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override -- Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply -- Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs -- Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. Indicates that the overlay is active for this operation. 34.4.44 PXP Overlay 4 Parameters 2 (HW_PXP_OL4PARAM2) This register contains buffer parameters for the Overlay 4 input buffer. The Overlay 4 Parameter 2 register is reserved for future use. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2578 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) Address: 8002_A000h base + 330h offset = 8002_A330h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL4PARAM2 field descriptions Field Description RSVD Reserved, always set to zero. 34.4.45 PXP Overlay 5 Buffer Pointer (HW_PXP_OL5) Overlay 5 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 5 input buffer. This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE u32* overlay_ptr; HW_PXP_OLn_WR(5,overlay_ptr); Address: 8002_A000h base + 340h offset = 8002_A340h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL5 field descriptions Field ADDR Description Address pointer for the overlay 5 buffer. The address MUST be word-aligned for proper PXP operation. 34.4.46 PXP Overlay 5 Size (HW_PXP_OL5SIZE) This register contains buffer size/location information for the Overlay 5 input buffer. This register contains information about Overlay 5 indicating the size of the overlay (in NxN blocks) and the overlay's location within the output frame buffer (in NxN blocks). In 16 pixel block size mode, only the low 7 bits of each field can be used and the most significant bit must be set to 0. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2579 Programmable Registers EXAMPLE HW_PXP_OLnSIZE_WR(5,0x10000401); // 32x8 overlay at offset +128+0 Address: 8002_A000h base + 350h offset = 8002_A350h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 XBASE 0 0 0 0 20 19 18 17 16 15 14 13 YBASE 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 WIDTH 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 HEIGHT 0 0 0 0 0 0 0 0 HW_PXP_OL5SIZE field descriptions Field Description 31-24 XBASE This field indicates the X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 23-16 YBASE This field indicates the Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 15-8 WIDTH Indicates number of horizontal NxN blocks in the image (non-rotated). HEIGHT Indicates the number of vertical NxN blocks in the image (non-rotated). 34.4.47 PXP Overlay 5 Parameters (HW_PXP_OL5PARAM) This register contains buffer parameters for the Overlay 5 input buffer. The S1 Overlay 5 Parameter register provides additional controls for Overlay 5. EXAMPLE u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(5,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2580 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) Address: 8002_A000h base + 360h offset = 8002_A360h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD1 R ROP W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ALPHA FORMAT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 ALPHA_ CNTL 0 0 ENABLE Bit 0 ENABLE_COLORKEY Reset 0 HW_PXP_OL5PARAM field descriptions Field Description 31-20 RSVD1 Reserved, always set to zero. 19-16 ROP Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB MASKOL -- OL AND S0 MASKNOTOL -- nOL AND S0 MASKOLNOT -- OL AND nS0 MERGEOL -- OL OR S0 MERGENOTOL -- nOL OR S0 MERGEOLNOT -- OL OR nS0 NOTCOPYOL -- nOL NOT -- nS0 NOTMASKOL -- OL NAND S0 NOTMERGEOL -- OL NOR S0 XOROL -- OL XOR S0 NOTXOROL -- OL XNOR S0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2581 Programmable Registers HW_PXP_OL5PARAM field descriptions (continued) Field Description 15-8 ALPHA Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. 7-4 FORMAT Indicates the input buffer format for overlay 0. ARGB8888 -- 32-bit pixels with alpha RGB888 -- 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 -- 16-bit pixels with alpha RGB565 -- 16-bit pixels without alpha RGB555 -- 16-bit pixels without alpha 0x0 0x1 0x3 0x4 0x5 3 ENABLE_ COLORKEY Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). 2-1 ALPHA_CNTL Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Embedded -- Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override -- Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply -- Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs -- Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0x0 0x1 0x2 0x3 0 ENABLE Indicates that the overlay is active for this operation. 34.4.48 PXP Overlay 5 Parameters 2 (HW_PXP_OL5PARAM2) This register contains buffer parameters for the Overlay 5 input buffer. The Overlay 5 Parameter 2 register is reserved for future use. Address: 8002_A000h base + 370h offset = 8002_A370h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL5PARAM2 field descriptions Field RSVD Description Reserved, always set to zero. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2582 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) 34.4.49 PXP Overlay 6 Buffer Pointer (HW_PXP_OL6) Overlay 6 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 6 input buffer. This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE u32* overlay_ptr; HW_PXP_OLn_WR(6,overlay_ptr); Address: 8002_A000h base + 380h offset = 8002_A380h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL6 field descriptions Field Description ADDR Address pointer for the overlay 6 buffer. The address MUST be word-aligned for proper PXP operation. 34.4.50 PXP Overlay 6 Size (HW_PXP_OL6SIZE) This register contains buffer size/location information for the Overlay 6 input buffer. This register contains information about Overlay 6 indicating the size of the overlay (in NxN blocks) and the overlay's location within the output frame buffer (in NxN blocks). In 16 pixel block size mode, only the low 7 bits of each field can be used and the most significant bit must be set to 0. EXAMPLE HW_PXP_OLnSIZE_WR(6,0x10000401); // 32x8 overlay at offset +128+0 Address: 8002_A000h base + 390h offset = 8002_A390h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 XBASE 0 0 0 0 20 19 18 17 16 15 14 13 YBASE 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 WIDTH 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 HEIGHT 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2583 Programmable Registers HW_PXP_OL6SIZE field descriptions Field Description 31-24 XBASE This field indicates the X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 23-16 YBASE This field indicates the Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 15-8 WIDTH Indicates number of horizontal NxN blocks in the image (non-rotated). HEIGHT Indicates the number of vertical NxN blocks in the image (non-rotated). 34.4.51 PXP Overlay 6 Parameters (HW_PXP_OL6PARAM) This register contains buffer parameters for the Overlay 6 input buffer. The S1 Overlay 6 Parameter register provides additional controls for Overlay 6. EXAMPLE u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(6,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay Address: 8002_A000h base + 3A0h offset = 8002_A3A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 RSVD1 R ROP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2584 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) 13 12 11 10 9 8 7 6 5 4 R ALPHA FORMAT W Reset 0 0 0 0 0 0 0 0 0 0 0 3 0 0 2 1 ALPHA_ CNTL 0 0 0 ENABLE 14 ENABLE_COLORKEY 15 Bit 0 HW_PXP_OL6PARAM field descriptions Field Description 31-20 RSVD1 Reserved, always set to zero. 19-16 ROP Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 15-8 ALPHA 7-4 FORMAT MASKOL -- OL AND S0 MASKNOTOL -- nOL AND S0 MASKOLNOT -- OL AND nS0 MERGEOL -- OL OR S0 MERGENOTOL -- nOL OR S0 MERGEOLNOT -- OL OR nS0 NOTCOPYOL -- nOL NOT -- nS0 NOTMASKOL -- OL NAND S0 NOTMERGEOL -- OL NOR S0 XOROL -- OL XOR S0 NOTXOROL -- OL XNOR S0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. 0x0 0x1 0x3 0x4 0x5 ARGB8888 -- 32-bit pixels with alpha RGB888 -- 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 -- 16-bit pixels with alpha RGB565 -- 16-bit pixels without alpha RGB555 -- 16-bit pixels without alpha 3 ENABLE_ COLORKEY Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). 2-1 ALPHA_CNTL Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2585 Programmable Registers HW_PXP_OL6PARAM field descriptions (continued) Field Description Embedded -- Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override -- Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply -- Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs -- Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. 0x0 0x1 0x2 0x3 0 ENABLE Indicates that the overlay is active for this operation. 34.4.52 PXP Overlay 6 Parameters 2 (HW_PXP_OL6PARAM2) This register contains buffer parameters for the Overlay 6 input buffer. The Overlay 6 Parameter 2 register is reserved for future use. Address: 8002_A000h base + 3B0h offset = 8002_A3B0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL6PARAM2 field descriptions Field RSVD Description Reserved, always set to zero. 34.4.53 PXP Overlay 7 Buffer Pointer (HW_PXP_OL7) Overlay 7 Buffer Address Pointer. This register points to the beginning of the RGB Overlay 7 input buffer. This register points to the is used by the logic to point to the current output location for the RGB frame buffer. EXAMPLE u32* overlay_ptr; HW_PXP_OLn_WR(7,overlay_ptr); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2586 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) Address: 8002_A000h base + 3C0h offset = 8002_A3C0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL7 field descriptions Field Description ADDR Address pointer for the overlay 7 buffer. The address MUST be word-aligned for proper PXP operation. 34.4.54 PXP Overlay 7 Size (HW_PXP_OL7SIZE) This register contains buffer size/location information for the Overlay 7 input buffer. This register contains information about Overlay 7 indicating the size of the overlay (in NxN blocks) and the overlay's location within the output frame buffer (in NxN blocks). In 16 pixel block size mode, only the low 7 bits of each field can be used and the most significant bit must be set to 0. EXAMPLE HW_PXP_OLnSIZE_WR(7,0x10000401); // 32x8 overlay at offset +128+0 Address: 8002_A000h base + 3D0h offset = 8002_A3D0h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 XBASE 0 0 0 0 20 19 18 17 16 15 14 13 YBASE 0 0 0 0 0 0 0 0 12 11 10 9 8 7 6 5 WIDTH 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 HEIGHT 0 0 0 0 0 0 0 0 HW_PXP_OL7SIZE field descriptions Field Description 31-24 XBASE This field indicates the X-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 23-16 YBASE This field indicates the Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output frame buffer. 15-8 WIDTH Indicates number of horizontal NxN blocks in the image (non-rotated). HEIGHT Indicates the number of vertical NxN blocks in the image (non-rotated). 34.4.55 PXP Overlay 7 Parameters (HW_PXP_OL7PARAM) This register contains buffer parameters for the Overlay 7 input buffer. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2587 Programmable Registers The S1 Overlay 7 Parameter register provides additional controls for Overlay 7. EXAMPLE u32 olparam; olparam = BF_PXP_OLnPARAM_ENABLE (1); olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs); olparam |= BF_PXP_OLnPARAM_FORMAT (BV_PXP_OLnPARAM_FORMAT__ARGB8888); olparam |= BF_PXP_OLnPARAM_ROP (BV_PXP_OLnPARAM_ROP__XOROL); HW_PXP_OLnPARAM_WR(7,olparam); // enable overlay to perform XOR ROP using RGB8888 overlay Address: 8002_A000h base + 3E0h offset = 8002_A3E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSVD1 R ROP W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ALPHA FORMAT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 ALPHA_ CNTL 0 0 ENABLE Bit 0 ENABLE_COLORKEY Reset 0 HW_PXP_OL7PARAM field descriptions Field Description 31-20 RSVD1 Reserved, always set to zero. 19-16 ROP Indicates a raster operation to perform when enabled. Raster operations are enabled through the ALPHA_CNTL field. 0x0 0x1 MASKOL -- OL AND S0 MASKNOTOL -- nOL AND S0 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2588 Freescale Semiconductor, Inc. Chapter 34 Pixel Pipeline (PXP) HW_PXP_OL7PARAM field descriptions (continued) Field Description 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 15-8 ALPHA 7-4 FORMAT MASKOLNOT -- OL AND nS0 MERGEOL -- OL OR S0 MERGENOTOL -- nOL OR S0 MERGEOLNOT -- OL OR nS0 NOTCOPYOL -- nOL NOT -- nS0 NOTMASKOL -- OL NAND S0 NOTMERGEOL -- OL NOR S0 XOROL -- OL XOR S0 NOTXOROL -- OL XNOR S0 Alpha modifier used when the ALPHA_MULTIPLY or ALPHA_OVERRIDE bits are set. The output alpha value will either be replaced (ALPHA_OVERRIDE) or scaled (ALPHA_MULTIPLY) when enabled in the ALPHA_CNTL field. Indicates the input buffer format for overlay 0. 0x0 0x1 0x3 0x4 0x5 ARGB8888 -- 32-bit pixels with alpha RGB888 -- 32-bit pixels without alpha (unpacked 24-bit format) ARGB1555 -- 16-bit pixels with alpha RGB565 -- 16-bit pixels without alpha RGB555 -- 16-bit pixels without alpha 3 ENABLE_ COLORKEY Indicates that colorkey functionality is enabled for this overlay. Pixels found in the overlay colorkey range will be displayed as transparent (the S0 pixel will be used). 2-1 ALPHA_CNTL Determines how the alpha value is constructed for this overlay. Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. 0x0 0x1 0x2 0x3 0 ENABLE Embedded -- Indicates that the OL pixel alpha value will be used to blend the OL with S0. The ALPHA field is ignored. Override -- Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels. Multiply -- Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel alpha is multiplied by the value in the ALPHA field. ROPs -- Enable ROPs. The ROP field indicates an operation to be performed on the overlay and S0 pixels. Indicates that the overlay is active for this operation. 34.4.56 PXP Overlay 7 Parameters 2 (HW_PXP_OL7PARAM2) This register contains buffer parameters for the Overlay 7 input buffer. The Overlay 7 Parameter 2 register is reserved for future use. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2589 Programmable Registers Address: 8002_A000h base + 3F0h offset = 8002_A3F0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSVD R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_PXP_OL7PARAM2 field descriptions Field RSVD Description Reserved, always set to zero. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2590 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) 35.1 Serial Audio Interface (SAIF) Overview The SAIF provides the following functions: * 3-, 4-, or 5-wire serial interface to industry's most common analog codecs. * Transmit or receive (half-duplex). * 16-bit to 24-bit serial stereo digital audio PCM play/record. * Two, four, or six channels supported--three stereo pairs (mono supported in twochannel mode). * Generic frame control supports DSP Compatible SIF, I2S, left- and right-justified frame formats, as well as other non-standard variants of these formats. * Master and slave BITCLK and LRCLK modes (clocks driven to codec or received from codec), as well as optional master MCLK mode. * Supports a continuous range of sample rates from 8 KHz to 192 KHz using a highresolution fractional divider driven by the PLL. * Programmable over-sample rate for MCLK output (32x, 48x, 64x, 96x, 128x, 192x, 256x, 384x, and 512x) supports codecs found in systems with both audio and video. * Four-entry FIFOs (per sample pair) buffer either two-channel sample pairs (17-bit through 24-bit PCM) or four-packed-channel sample pairs (16-bit PCM). * Samples transferred to/from the FIFO through the APBX DMA interface, a FIFO service interrupt, or software polling. Figure 35-1 shows the major functional blocks within the SAIF. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2591 Operation APBX SAIF__MCLK_BITCLK Pin MCLK/ BITCLK/ LRCLK Dividers DMA Interface SAIF_ALT_BITCLK Pin SAIF_LRCLK Pin saif_clk CLKCTRL (IFRAC reg) Registers FIFOs Serial Frame Control Front Surround 1, 2, or 3 Center/ LFE SAIF_SDATA Pins Figure 35-1. Serial Audio Interface (SAIF) Block Diagram 35.2 Operation The SAIF is a half-duplex port, meaning it can either transmit or receive PCM audio, but not simultaneously. (Full-duplex support is availabe with two SAIF modules: one transmits while the other receives.) Data is communicated serially one sample at a time, alternating between left and right samples. One to three serial data lines (SDATA0- SDATA2) can be used to transmit or receive either two (stereo/mono), four (stereo/ surround), or six (stereo/surround/center/LFE) channels of digital PCM audio data. Stereo data is transmitted from Front FIFO to SDATA0. Surround data is transmitted from Surround FIFO to SDATA1. Center/LFE data is transmitted from Center/LFE FIFO to SDATA2. Similarly, data received from SDATA0, SDATA1, and SDATA2 are stored on Front, Surround, and Center/LFE FIFO respectively. Samples boundaries are delineated by a left/right clock (LRCLK) pin, and individual bits within each sample are delineated by a bit clock (BITCLK) pin. The LRCLK can be programmed to toggle every 16, 24, or 32 BITCLK transitions, and, because data ranges from 16 to 24 bits, serial data within each LRCLK period can either fully occupy the LRCLK cycle or cause the LRCLK period to contain BITCLK cycles in which no data is being communicated. Because of this, three basic types of sample frame i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2592 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) formats can be programmed: I2S, left-justified, and right-justified. However, many programming options exist to alter these basic frame types, such as the LRCLK signal polarity, BITCLK edge selection to drive/sample serial data, and sample justification/ delay within an LRCLK period. For codecs that do not contain their own PLL, or in applications where including a crystal oscillator to drive the codec is not desired, the SAIF can provide a master clock (MCLK) reference that can be configured from 512x down to 32x the audio data's sample rate. This master clock is used by the off-chip codec for all of its internal logic and to synchronize the BITCLK/LRCLK/SDATA inputs for DAC operation. The digital PCM audio sample rate is determined by programming a fractional divider within the clock controller module. 35.2.1 Sample Rate Programming and Codec Clocking Operation SAIF clocking is programmed in three blocks of the device: * Clock control module (CLKCTRL) * SAIF module * Digital control module (DIGCTL) The saif_clk (shown in Figure 35-1) is generated by the CLKCTRL block with a 16-bit fractional divider that divides down the 480 MHz PLL reference. The fractional divider minimizes system cost and power by eliminating the need for a second on-chip PLL. This fractional divider continuously selects which edge of the PLL reference clock (positive or negative) to use to best represent the oversample rate, such that less than 2 ns of correlated jitter occurs in saif_clk (jitter of the PLL plus periodic jitter of the fractional divide). This low level of jitter is required by most codec manufacturers to ensure a high SNR. Table 35-1 shows the values to program the HW_CLKCTRL_SAIF_DIV bit field for all standard sample rates with either a base oversample rate of 512 or 384 times the sample rate. These two base oversample values are the base rates typically required by codecs for the master clock (MCLK). An additional divider exists within the SAIF to generate submultiples of these two base rates if MCLK is required by the codec. * The sub-rates that can be generated from 512x are: 256x, 128x, 64x, and 32x. * The sub-rates for the 384x base rate are: 192x, 96x, and 48x. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2593 Operation The 384xFs base rate is common among systems that include MPEG1/2/4 audio and video, and AAC and AC-3 (Dolby Digital) audio. These MCLK rates are generated by programming the HW_SAIF_CTRL_BITCLK_BASE_RATE and HW_SAIF_CTRL_BITCLK_MULT_RATE bit fields. Because there is a small amount of error in the sample rates generated by the fractional divider, software needs to periodically alter the HW_CLKCTRL_SAIF_DIV value higher or lower, depending on the difference between the required and actual sample rates. For an audio-only playback application, this adjustment need not ever be performed, because the frequency phase shift is imperceptible. However, it is needed for applications such as locking to and playing from an FM tuner, or audio/video applications where AV synchronization is required. For an audio/video application, it is typically accepted that audio and video cannot diverge any greater than 20 ms. Table 35-1 contains a column that lists the average elapsed time between each DIV adjustment required to keep within this 20-ms limit. Note that the smallest elapsed time is just under 20 seconds. Typically, software can be configured to periodically monitor the read and write pointers for the digital PCM audio buffer in OCRAM or SDRAM. When the pointers either become close to overrunning each other or close to the 20-ms AV divergence point, the DIV value should be increased or decreased incrementally (LSBs). Table 35-1. HW_CLKCTRL_SAIF_DIV Values for Standard Sample Rates/ Oversample Base Rates DIV Adjustment Sampl e Rate (Hz) 192000 176200 128000 96000 88100 64000 48000 Oversam ple Base Rate Multiplier saif_clk Require d (MHz) Closest Desired Fractional Divisor Actual Fractional DIV Binary Value DIV Error Hex (ppm ) Value Divisor Frequency (seconds) (Notes 1 and , 2) DIV DIV < Actual > Actual 512 98.304 0.2048000000 0.2048034668 0011010001101110 0x346E 16.9 347.3 1181.5 384 73.728 0.1536000000 0.1535949707 0010011101010010 0x2752 32.7 610.8 300.3 512 90.2144 0.1879466667 0.1879425049 0011000000011101 0x301D 22.1 903.2 338.8 384 67.6608 0.1409600000 0.1409606934 0010010000010110 0x2416 4.9 193.5 4066.0 512 65.536 0.1365333333 0.1365356445 0010001011110100 0x22F4 16.9 210.9 1181.5 384 49.152 0.1024000000 0.1024017334 0001101000110111 0x1A37 16.9 151.4 1181.5 512 49.152 0.1024000000 0.1024017334 0001101000110111 0x1A38 16.9 151.4 1181.5 384 36.864 0.0768000000 0.0767974854 0001001110101001 0x13A9 32.7 610.8 120.5 512 45.1072 0.0939733333 0.0939788818 0001100000001111 0x180F 59.0 193.5 338.8 384 33.8304 0.0704800000 0.0704803467 0001001000001011 0x120B 4.9 94.5 4066.0 512 32.768 0.0682666667 0.0682678223 0001000101111010 0x117A 16.9 96.8 1181.5 384 24.576 0.0512000000 0.0511932373 0000110100011011 0x0D1B 132.1 151.4 120.5 512 24.576 0.0512000000 0.0511932373 0000110100011011 0x0D1B 132.1 151.4 120.5 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2594 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) Table 35-1. HW_CLKCTRL_SAIF_DIV Values for Standard Sample Rates/Oversample Base Rates (continued) DIV Adjustment Sampl e Rate (Hz) 44100 32000 24000 22050 16000 12000 11025 8000 Oversam ple Base Rate Multiplier saif_clk Require d (MHz) Desired Fractional Divisor Closest Actual Fractional DIV Binary Value DIV Error Hex (ppm ) Value Divisor Frequency (seconds) (Notes 1 and , 2) DIV DIV < Actual > Actual 384 18.432 0.0384000000 0.0384063721 0000100111010101 0x09D5 165.9 86.4 120.5 512 22.5792 0.0470400000 0.0470428467 0000110000001011 0x0C0B 60.5 75.8 330.5 384 16.9344 0.0352800000 0.0352783203 0000100100001000 0x0908 47.6 420.1 52.0 512 16.384 0.0341333333 0.0341339111 0000100010111101 0x08BD 16.9 46.5 1181.5 384 12.288 0.0256000000 0.0256042480 0000011010001110 0x068E 165.9 46.5 120.5 512 12.288 0.0256000000 0.0256042480 0000011010001110 0x068E 165.9 46.5 120.5 384 9.216 0.0192000000 0.0191955566 0000010011101010 0x04EA 231.4 86.4 35.5 512 11.2896 0.0235200000 0.0235137939 0000011000000101 0x0605 263.9 75.8 52.0 384 8.4672 0.0176400000 0.0176391602 0000010010000100 0x0484 47.6 420.1 24.5 512 8.192 0.0170666667 0.0170593262 0000010001011110 0x045E 430.1 46.5 43.1 384 6.144 0.0128000000 0.0128021240 0000001101000111 0x0347 165.9 19.5 120.5 512 6.144 0.0128000000 0.0128021240 0000001101000111 0x0347 165.9 19.5 120.5 384 4.608 0.0096000000 0.0095977783 0000001001110101 0x0275 231.4 86.4 14.7 512 5.6448 0.0117600000 0.0117645264 0000001100000011 0x0303 384.9 21.9 52.0 384 4.2336 0.0088200000 0.0088195801 0000001001000010 0x0242 47.6 420.1 11.9 512 4.096 0.0085333333 0.0085296631 0000001000101111 0x022F 430.1 46.5 14.7 384 3.072 0.0064000000 0.0063934326 0000000110100011 0x01A3 1026. 2 19.5 14.7 1. HW_CLKCTRL_SAIF_DIV_FRAC_EN=1 2. Average elapsed time between each DIV adjustment to maintain audio within 20 ms of sample rate. BITCLK is used to launch or capture each bit of the serial PCM data, while LRCLK clocks the individual left/right samples (transitions at every sample boundary). For transmit, BITCLK and LRCLK are always driven by the SAIF. However, there are two different clocking modes for receive. In master mode, the SAIF drives both BITCLK and LRCLK, while in slave clock mode it is the responsibility of the codec to drive BITCLK and LRCLK to the SAIF. Note that, for any of these modes, an alternate MCLK reference can be multiplexed out to a pin to drive the codec's main system clock. In slave clocking mode, the SAIF configures the BITCLK and LRCLK pins as inputs, and the off-chip codec is responsible for driving both clocks to the SAIF. The SAIF synchronizes these inputs and uses them to determine when to latch serial PCM data from i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2595 Operation the ADC for receive. The codec must be configured to run BITCLK either at 32xFs for 16-bit operation, 64xFs for 17-bit through 24-bit operation, or 48xFs for certain codecs for 16-bit through 24-bit operation. In master clocking mode, it is the responsibility of the SAIF to drive both BITCLK and LRCLK out to the off-chip codec. In this mode, BITCLK is again programmed to transition at a the standard 32x, 48x, or 64x the sample rate. On the device, two SAIF modules are instantiated on-chip. Each SAIF has a set of clock pins and can be operating in master mode simultaneously if they are connected to different off-chip codecs. Also, one of the two SAIFs can master or drive the clock pins while the other SAIF, in slave mode, receives clocking from the master SAIF. This also means that both SAIFs must operate at the same sample rate. Following are the valid configurations for SAIF1 and SAIF2 on the i.MX28: * One SAIF in TX mode (is the default clock master) while the other SAIF is in RX slave mode and is internally controlled by the TX SAIF's BITCLK and LRCLK. * One SAIF in RX master mode while the other SAIF is in RX slave mode and again is internally controlled by the RX master SAIF's BITCLK and LRCLK. * Both SAIFs in RX slave mode, with BITCLK and LRCLK controlled by the off-chip codec. * Both SAIFs in master mode, driving their BITCLK and LRCLK. * Only one SAIF used (any configuration). For any of these configurations, MCLK can also be output through a multiplexed pin to provide the clock reference for the off-chip codec. Configuring the SAIF for transmit makes it the master by default. However, for receive, the SAIF can either be master or slave. For master mode, it drives BITCLK and LRCLK to the pins the off-chip codec, which uses the clocks to time when to serially transmit PCM data back to the SAIF. For slave mode, the BITCLK and LRCLK are pin inputs driven by the off-chip codec or the other SAIF (master), and the SAIF (slave) uses these clocks to determine when to latch each incoming bit and push the assembled PCM data to the FIFO. The DIGCTL module contains the HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL bit field which selects the clock sources for the SAIFs input BITCLK and LRCLK. Each SAIF has two source options: from external device through SAIF0 clock pins, from external device through SAIF1 clock pins. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2596 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) Table 35-2. HW_DIGCTL_CTRL_SAIF_CLKMUX_SEL Programming Module Port SAIF0_BITCLK_IN, SAIF1_BITCLK_IN, SAIF0_LRCLK_IN SAIF1_LRCLK_IN 00 SAIF0 Clock pins SAIF1 Clock pins DIRECT 01 SAIF1 Clock pins SAIF0 Clock pins CROSSINPUT 10 SAIF0 Clock pins SAIF0 Clock pins EXTMSTR0 11 SAIF1 Clock pins SAIF1 Clock pins EXTMSTR HW_SAIF_CLKMUX_SEL MODE See Pin Control and GPIO Overview for instructions on which pins the two SAIFs use and how to configure them for operation. The SAIF contains a four-entry FIFO for each channel pair that buffers data between the SAIF and the on-chip or off-chip RAM buffer used to supply or collect serial PCM audio data. Both the SAIF's register and DMA interface are clocked by APBX clock. To ensure the SAIF FIFO does not overrun or underrun, the minimum APBX clock frequency to sample rate frequency ratio is 22:1. Therefore, if the sample rate is configured to 192 KHz, then APBX must be set to 4.224 MHz or greater. 35.2.2 Transmit Operation If the APBX DMA is to supply PCM data to the SAIF FIFO, the user first configures its corresponding DMA channel and initializes the buffer(s) of PCM data that are to be played. Next the SAIF control register is initialized, selecting the frame format and number of channel pairs, clearing the CLKGATE bit, and setting the RUN bit. Once running, the BITCLK, LRCLK, and optional MCLK pins begin to transition, and null data is output to the off-chip analog DAC. The SAIF DMA interface requests PCM samples until the FIFO(s) is/are filled, and continues to request a sample (or sample pair for 16-bit operation) whenever an empty FIFO entry is available. Once valid PCM data resides within the bottom of the front channel pair FIFO, the current null sample left/right pair(s) are allowed to complete. At this point, the serialization frame control logic begins to output the first valid left sample. In 16-bit operation, sample pairs are packed with the right samples occupying the upper halfword and left samples the lower halfword of the FIFO entries. For 17-bit to 24-bit operation, each FIFO entry contains a sample that is right-justified (LSB in bit 0). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2597 Operation The first sample DMA-ed to the FIFO at the start of operation should always be a left sample, followed by a right, and so on. If four or six channel pairs are enabled, samples should be grouped with all left samples first, followed by all right samples (for example, front left, surround left, then center, followed by front right, surround right then LFE, and so on). As long as data resides within the FIFO(s), valid sample pairs continue to be output. If the FIFO(s) ever underflow or overflow, an interrupt occurs. At this point, the system software should shut down the SAIF, clear the FIFO(s), and then cleanly resume operation because there is not a way to prevent left/right swap of the PCM channels after this point. If the FIFO does underflow, null samples are output until valid data once again resides within the bottom of the FIFO. Any PCM value that is written to a full FIFO is discarded, preventing the top entry from be overwritten. When the RUN bit is cleared at the end of operation, all PCM data corresponding to one sample collection (either two, four, or six channel pairs) that are currently being transmitted are allowed to complete before operation ceases and the BITCLK, LRCLK, and SDATA pins stop transitioning. Alternately, software can be used to maintain the FIFO(s) if the DMA is not used, either by responding to an interrupt that is issued whenever an empty FIFO entry exists, or by polling a FIFO status bit. 35.2.3 Receive Operation If the APBX DMA is to collect PCM data from the SAIF FIFO(s), the user first configures its corresponding DMA channel and allocates the buffer(s) where PCM data is to be recorded. Next the SAIF control register is initialized, selecting the frame format and number of channel pairs, selecting whether the SAIF is BITCLK/LRCLK master or slave, clearing the CLKGATE bit, and setting the RUN bit. Once running, the SAIF either waits until the BITCLK and LRCLK pins begin to transition (slave mode) or begins to toggle BITCLK and LRCLK (master mode). In either case, once an LRCLK edge that corresponds to the start of a left sample is detected, the SAIF frame-control logic begins to assemble the sample in its serial shift register. Each time the LRCLK pin toggles, a new sample is pushed to the FIFO(s). In 16-bit operation, sample pairs are packed with the right samples occupying the upper halfword and left samples the lower halfword of the FIFO entries. For 17-bit to 24-bit operation, samples are placed in individual FIFO entries, are right justified (LSB in bit 0), and the unused MSBs are zero-filled. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2598 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) The first sample pushed to the FIFO at the start of operation is always a left sample, followed by a right, and so on. If 4 or 6 channel pairs are enabled, sample pairs are grouped when pushed to the FIFO with all left samples first, followed by all right samples (for example, front left, surround left, then center, followed by front right, surround right then LFE, and so on). As long as the BITCLK and LRCLK pins continue to transition, data is collected within the FIFO. If the FIFO ever overflows or underflows, an interrupt occurs. At this point, the system software should shut down the SAIF, clear the FIFO(s), and then cleanly resume operation because there is not a way to determine left from right PCM channel data within the FIFO after this point. If the FIFO does overflow, any PCM value that is pushed to the full FIFO is discarded, not allowing the top entry to be overwritten. If the FIFO underflows, the read of the empty FIFO returns all zeros. When the run bit is cleared at the end of operation, all PCM data corresponding to one sample collection (either two, four, or six channel pairs) that are currently being serially received are allowed to complete and are stored to the FIFO before operation ceases. Software can be used to empty the FIFO if the DMA is not used, either by responding to an interrupt that is issued whenever an empty FIFO entry exists, or by polling a FIFO status bit. 35.2.4 DMA Interface Both SAIFs on the device are assigned to APBX DMA channels. See AHB-to-APBX Bridge Overview for the DMA channel assignments. Once the DMA channel and SAIF are programmed (except for the RUN bit), operation can be initiated either by setting the SAIF's RUN bit or by signaling a kick from the DMA channel. The HW_SAIF_CTRL_DMAWAIT_COUNT bit field can be programmed to wait 0 to 31 APBX clock cycles between each DMA request. This feature acts as a throttle on the bandwidth required by the SAIF to allow delays such that DMA requests from other modules can be serviced by the DMA controller. 35.2.5 PCM Data FIFO The SAIF contains three 4-entry by 32-bit wide FIFOs. These FIFOs serve as a buffer to ensure data is not corrupted if the DMA cannot service the SAIF before the next sample or sample pair is processed by the SAIF. Access to the FIFOs is achieved through read/ writes of the 32-bit HW_SAIF_DATA register. Writes place PCM values at the top of the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2599 Operation FIFOs, and reads take them from the bottom of the FIFOs. Each FIFO is used to store different sets of left/right channel pairs. FIFO1 stores the stereo or front channels, FIFO2 the surround or rear channels, and FIFO3 the center and low frequency effect (LFE) or subwoofer channels (see Figure 35-1). Read/write accesses are made to the FIFOs in a round-robin fashion such that all left channel samples are transferred first including the center channel, followed by all right channel samples including the LFE channel. In 16-bit operation, sample pairs are packed with the right samples occupying the upper halfword and left samples the lower halfword of the FIFO entries. For 17-bit to 24-bit operation, sample pairs are placed in individual FIFO entries, left channel first then followed by the right channel, and are right justified (LSB in bit 0) in each FIFO entry. The FIFO underflow, overflow, and service interrupt status bits reside within the HW_SAIF_STAT register. 35.2.6 Serial Frame Formats There are six types of serial PCM frames that can be transmitted or received. The three basic formats are I2S, left-justified, and right-justified. Because there are two variations of a frame based on whether or not the data consumes the entire frame width, these three formats have two frame types each that make up the six basic frame types. One variation exists for 16-bit and 24-bit serial PCM data that consumes the whole frame width, and the other for 17-bit to 24-bit serial PCM data that does not. Recall that for 16-bit operation, BITCLK is either 32xFs or 48xFs, while for 17-bit to 24-bit, it is either 48xFs or 64xFs. These six types of serial PCM frames are shown in Figure 35-2. * In left-justified (LJ) format, the serial PCM data is left-justified within the sample's start and end point indicated by the LRCLK. The first bit of PCM data is coincident with the first BITCLK period after LRCLK transitions. * Conversely, in right-justified (RJ) format, the last bit of PCM data in a sample is coincident with the last BITCLK period before LRCLK transitions, indicating the start of the next sample. * I2S format is simply a variant of LJ format, in that the first BITCLK period after the LRCLK transitions, is a null wait state, followed by the first serial PCM bit during the next BITCLK period. For both LJ and RJ formats, LRCLK is high for left samples and low for right samples. For I2S, it is the opposite: LRCLK is low for left samples and high for right samples. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2600 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) When the programmed data size is smaller than the frame size or number of BITCLKs per LRCLK, there are BITCLK periods within the sample frame in which no data is being transmitted or received. This occurs in 48xFs mode when that data is less than 24 bits, and for all data sizes allowed in 64xFs mode. For LJ and I2S modes, this occurs after the sample has been transmitted or received, while for RJ mode, this occurs prior to the sample being transmitted or received. For 16-bit (32xFs mode) operation and 24-bit (48xFs mode) operation, data is always being transmitted, so that LJ and RJ modes are identical. I2S is a special case for these modes. At the start of transmit or receive, the first BITCLK period after LRCLK transitions is a null or wait state cycle in which no PCM data is present. However, this means one too few BITCLK periods remain to transmit or receive data before LRCLK transitions. As a result, the protocol dictates that the last serial PCM bit of each sample be transmitted or received during the BITCLK wait state at the start of the next sample. Another format, the DSP Compatible Serial Interface Format, is now supported by the SAIF module. In DSP format, the Right channel data immediately follows the left channel data as in 16 and 24 bit operation with BITCLK being 32xFs and 48xFs respectively. This format is one of the type where a synch pulse on the LRCLK is followed by a left and right data pair. The pulse is 1 BITCLK clock cycle wide, as oppose to 16 or 24 BITCLK clock cycles in the other formats. DSP format has 2 data modes: A and B. Mode A resembles LJ format where the first bit is aligned with the LRCLK pulse. Mode B resembles I2S format where the first bit is delayed by 1 BITCLK cycle. Additionally data can be programmed to be transmitted or received MSB or LSB first. The bits to program frame format reside within the HW_SAIF_CTRL register. 35.2.7 Pin Timing The figure below shows the six basic frame formats supported by the SAIF. Keep in mind that for 16-bit operation, BITCLK runs at either 32x or 48x the sample rate, and for 17bit through 24-bit operation, it runs at either 48x or 64x the sample rate (that is, the clock frequency relationship of differing data sizes is not shown here). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2601 Programmable Registers LRCLK BITCLK SDATA I 2 S w/ nulls WAIT MSB MSB-1 SDATA I 2 S w/ nulls WAIT MSB MSB-1 SDATA LJ w/ nulls MSB MSB-1 MSB-2 SDATA LJ w/ nulls SDATA LJ/RJ w/o nulls 0 WAIT MSB LSB MSB MSB MSB-1 LSB+1 LSB 0 LSB MSB 0 MSB-2 MSB-1 MSB 0 LSB MSB MSB-1 I2S, Left and R ight Justified Formats Note: LRCLK_POLARITY=1 and B ITCLK_EDGE=0 for this example. LRCLK BITCLK SDATA DSP Format B SDATA DSP Format A Ln Ln-1 Ln-2 L0 Rn Rn-1 R0 Ln Ln-1 Ln Ln-1 L0 Rn Rn-1 R1 R0 Ln DSP Compatible Serial Interface Format Note: LRCLK_POLARITY=1 and B ITCLK_EDGE=1 required. Figure 35-2. Frame Formats Supported by SAIF 35.3 Programmable Registers SAIF Hardware Register Format Summary SAIF0 base address is 0x80042000;SAIF1 base address is 0x80046000 HW_SAIF memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8004_2000 SAIF Control Register (HW_SAIF_CTRL) 32 R/W C000_0000h 35.3.1/2603 8004_2010 SAIF Status Register (HW_SAIF_STAT) 32 R/W 8000_0000h 35.3.2/2607 Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2602 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) HW_SAIF memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 8004_2020 SAIF Data Register (HW_SAIF_DATA) 32 R/W 0000_0000h 35.3.3/2609 8004_2030 SAIF Version Register (HW_SAIF_VERSION) 32 R 0101_0000h 35.3.4/2611 35.3.1 SAIF Control Register (HW_SAIF_CTRL) The SAIF Control Register controls the frame format and operation of the three-wire serial audio interface. HW_SAIF_CTRL: 0x000 HW_SAIF_CTRL_SET: 0x004 HW_SAIF_CTRL_CLR: 0x008 HW_SAIF_CTRL_TOG: 0x00C The SAIF Control Register is used to configure the SAIF's input/output frame format, MCLK, BITCLK and LRCLK, and interrupt enables. EXAMPLE HW_SAIF_CTRL.RUN = 1; // start SAIF operation 30 29 28 27 SFTRST CLKGATE R 1 1 BITCLK_MULT_ RATE W Reset 0 0 0 25 24 FIFO_SERVICE_IRQ_EN 31 FIFO_ERROR_IRQ_EN Bit BITCLK_BASE_RATE Address: 8004_2000h base + 0h offset = 8004_2000h 26 0 0 0 23 22 21 20 19 18 17 16 RSRVD2 DMAWAIT_COUNT 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2603 10 9 8 JUSTIFY LRCLK_POLARITY BITCLK_EDGE 0 0 0 0 0 0 7 6 5 4 R CHANNEL_ NUM_ SELECT W Reset 0 0 WORD_LENGTH 0 0 0 0 3 2 1 0 READ_MODE 11 SLAVE_MODE 12 BITCLK_48XFS_ENABLE 13 DELAY 14 BIT_ORDER 15 Bit LRCLK_PULSE Programmable Registers RUN 0 0 0 0 HW_SAIF_CTRL field descriptions Field 31 SFTRST 30 CLKGATE Description Setting this bit to 1 forces a reset to the entire block. SFTRST has no effect on CLKGATE. Also, the SFTRST bit may be written when CLKGATE=1. This bit must be cleared to 0 for normal operation. This bit gates the clocks to the SAIF to save power when the clocks are not in use. When set to 1, this bit gates off the clocks to the block. When this bit is cleared to 0, the block receives its clocks for normal operation. 29-27 BITCLK Mutiplier Rate. This bit field selects the multiple of the base frequency rate of BITCLK for transmit BITCLK_MULT_ mode and receive master clock mode (READ_MODE=1, SLAVE_MODE=0), or if the alternate BITCLK pin RATE is used, it selects the multiple of the base frequency rate of MCLK (any mode). When BITCLK_BASE_RATE = 0 (32x base rate): 000=512 x Fs, 001=256 x Fs, 010=128 x Fs, 011=64 x Fs, 100=32 x Fs, 101-111=reserved. When BITCLK_BASE_RATE = 1 (48x base rate): 000=384 x Fs, 001=192 x Fs, 010=96 x Fs, 011=48 x Fs, 100-111=reserved. When the SAIF_BITCLK_MCLK pin is used as BITCLK, this field should be programmed to 32x for 16-bit data, 48x for 16-bit to 24-bit data (BITCLK_48XFS_ENABLE=1), and 64x for 17-bit to 24-bit data, depending on the modes supported by the off-chip codec. When the SAIF_BITCLK_MCLK pin is used as MCLK (and the alternate BITCLK pin mux function is enabled), any oversample rate can be selected as dictated by the codec's required MCLK frequency. Note that the clock controller block should be programmed with the correct DIV value to produce the correct oversample clock base frequency (either 512x or 384x the sample rate) to the SAIF. 26 BITCLK Base Rate. This bit selects the base frequency rate at which the BITCLK pin toggles when BITCLK_BASE_ configured as an output (either in transmit mode or in receive master clock mode), or if the alternate RATE BITCLK pin is used, it selects the base frequency rate at which both the MCLK and alternate BITCLK pin toggles. 0 = BITCLK/MCLK base frequency rate is in multiples of 32x the sample rate. 1 = BITCLK/MCLK base frequency rate in in multiples of 48x the sample rate. This bit field is used in conjunction with the BITCLK_MULT_RATE field to program the BITCLK/MCLK output frequency. 25 Set this bit to one to enable a SAIF interrupt request on FIFO overflow or underflow status condition. FIFO_ERROR_ IRQ_EN Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2604 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) HW_SAIF_CTRL field descriptions (continued) Field Description 24 Set this bit to one to enable a SAIF interrupt request to service the FIFO when it contains an empty entry FIFO_SERVICE_ (for transmit) or a full entry (for receive). IRQ_EN 23-21 RSRVD2 20-16 DMAWAIT_ COUNT 15-14 CHANNEL_ NUM_SELECT Reserved. DMA Request Delay Count. This bit field specifies the number of APBX clock cycles (0 to 31) to delay after a DMA request has been serviced and before the next request is granted. This field acts as a throttle on the bandwidth consumed by the SAIF block. This field can be loaded by the DMA. Channel Number Select. This bit field selects the number of channel pairs (left and right) that are transmitted and/or received by the SAIF. 00 = One channel pair (stereo) 01 = Two channel pairs (front, surround) 10 = Three channel pairs (front, surround, center/lfe) 11 = Reserved 13 SAIF LRCLK Pulse Select. This bit used for the PCM Format where the LRCLK is high for one BITCLK LRCLK_PULSE cycle at the beginning of the left PCM sample only. 0 = LRCLK toggles between Left and Right PCM samples 1 = LRCLK pulses high for 1 Bitclk cycle at the beginning of a PCM sample pair (left,Right). 12 BIT_ORDER SAIF PCM Data Serial Bit Order. This bit selects whether PCM data is serially transmitted or received LSB or MSB first. 0 = MSB first 1 = LSB first Note that the two's complement audio data written to and read from the FIFO is always ordered MSB to LSB (LSB located in bit 0 for 17-bit through 24-bit operation, and in bits 15 and 0 for 16-bit operation). 11 DELAY SAIF Data Delay. In left-justified mode, this bit selects whether or not serial PCM data transmission/ reception is delayed by one BITCLK period each LRCLK frame (to generate I2S serial operation). 0 = Data is not delayed. MSB of serial sample is output/input coincident with LRCLK transition (leftjustified mode) 1 = Data is delayed one BITCLK period. MSB of serial serial sample is output/input one BITCLK period after LRCLK transitions (I2S mode). Note that this bit is ignored in right-justified mode (JUSTIFY=1). 10 JUSTIFY SAIF Data Justification. This bit selects whether serial PCM data is left- or right-justified within each sample's LRCLK frame. 0 = Data is left-justified (start or MSB of serial sample transmission/reception coincides with LRCLK transition) 1 = Data is right-justified (end or LSB of serial sample transmission/reception coincides with LRCLK transition). 9 LRCLK_ POLARITY SAIF LRCLK Polarity Select. This bit selects which LRCLK levels (high/low) correspond to left and right PCM samples. 0 = Left low/right high 1 = Left high/right low. 8 BITCLK_EDGE SAIF BITCLK Edge Select. For both transmit and receive, this bit selects the BITCLK edge upon which serial PCM data changes. For receive, data is sampled and stored to the receive FIFO on the opposite edge as selected by BITCLK_EDGE that corresponds to the midpoint of the data. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2605 Programmable Registers HW_SAIF_CTRL field descriptions (continued) Field Description 0 = TX: data is driven (changes) on falling-edges of BITCLK; RX: data is sampled on rising-edges of BITCLK 1 = TX: data is driven (changes) on rising-edges of BITCLK; RX: data is sampled on falling-edges of BITCLK. 7-4 SAIF data size. Selects one of nine PCM data widths from 16-bit to 24-bit to serially input or output from/to WORD_LENGTH a codec. 17-bit to 24-bit PCM data should be right-justified (LSB in bit 0) when it is DMAed or written to the HW_SAIF_DATA register. These samples should be interleaved starting with a left sample first, followed by a right, then left and so on. For 16-bit PCM data, stereo pairs should be constructed with the right sample in the upper half-word (bits 31-16) and the left sample in the lower half word (bits 15-0). 0000 = 16-bit 0001 = 17-bit 0010 = 18-bit 0011 = 19-bit 0100 = 20-bit 0101 = 21-bit 0110 = 22-bit 0111 = 23-bit 1000 = 24-bit 1001-1111 = Reserved but defaults to 24-bit. 3 BITCLK 48x Sample Rate Enable. For 384x base frequency multiples, this bit enables generation of 48 BITCLK_48XFS_ BITCLKs per sample pair (24 BITCLKs per channel or LRCLK transition) when the SAIF is BITCLK ENABLE master. This bit is ignored for the following cases: BITCLK_BASE_RATE=0, or READ_MODE=1, or READ_MODE=0 and SLAVE_MODE=1. 2 SLAVE_MODE SAIF Receive Master/Slave Clock Mode Select. For receive operation, this bit selects whether BITCLK and LRCLK are driven to the off-chip codec or uses the two clock pins as inputs to determine when to receive data from the codec. In receive master mode (SLAVE_MODE=0), BITCLK and LRCLK are output to the codec. When SLAVE_MODE=0, both BITCLK and LRCLK start to transition immediately after the RUN bit is set. Note that when in transmit mode or receive master mode, the user must configure the SAIF's clock controls within the clock controller to the correct oversample rate (see BITCLK_BASE_RATE/ BITCLK_MULT_RATE above). 0 = Master mode. SAIF drives BITCLK and LRCLK 1 = Slave mode. SAIF uses BITCLK and LRCLK as inputs to determine when to sample input PCM data. Note that is bit is ignored in transmit operation (READ_MODE=0). 1 READ_MODE SAIF Transmit/Receive Select. This bit selects whether the SAIF block transmits to an off-chip DAC (write mode) or receives from an off-chip ADC (read mode). The selected mode (TX or RX) starts operation once the RUN bit is set. 0 = TX or write mode 1 = RX or read mode 0 RUN Setting this bit to one causes the SAIF to begin transmitting or receiving serial PCM data, depending on the programming of the READ_MODE bit. For transmit, when this bit is cleared, operation ends after transmission of the current active channel set (pairs from all enabled channels) from the FIFO. If the FIFO is already empty and the RUN bit is cleared, operation halts immediately and the LRCLK and BITCLK pins stop transitioning. For receive, when the RUN bit is cleared, reception ends after the current active channel set (pairs from all enabled channels) are pushed to the FIFO. Note for 4- and 6-channel Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2606 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) HW_SAIF_CTRL field descriptions (continued) Field Description operation, clearing the RUN bit means that the SAIF does not stop until the corresponding audio samples for all 4 or 6 channels have been transmitted or received. 35.3.2 SAIF Status Register (HW_SAIF_STAT) The SAIF Status Register provides status of key hardware components required by software of the SAIF module. HW_SAIF_STAT: 0x010 HW_SAIF_STAT_SET: 0x014 HW_SAIF_STAT_CLR: 0x018 HW_SAIF_STAT_TOG: 0x01C The SAIF Status Register provides the status of interrupt requests and active operation of the SAIF. EXAMPLE unsigned TestBit = HW_SAIF_STAT.PRESENT; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2607 Programmable Registers Address: 8004_2000h base + 10h offset = 8004_2010h R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DMA_PREQ 31 PRESENT Bit RSRVD2 W 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD1 R 0 0 BUSY 0 FIFO_SERVICE_IRQ 0 FIFO_OVERFLOW_IRQ Bit 1 FIFO_UNDERFLOW_IRQ Reset RSRVD0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2608 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) HW_SAIF_STAT field descriptions Field 31 PRESENT 30-17 RSRVD2 16 DMA_PREQ 15-7 RSRVD1 6 FIFO_ UNDERFLOW_ IRQ 5 FIFO_ OVERFLOW_ IRQ Description This bit is set to 1 in products in which SAIF is present. Reserved. DMA Request Status. This read-only bit reflects the current state of the SAIF's DMA request signal. DMA requests are issued any time the request signal toggles. Reserved. This bit is set by hardware if the FIFO underflows during SAIF operation. Underflow occurs whenever a read or pop is attempted on an empty FIFO. This occurs in transmit mode when the FIFO is not filled in time and the hardware tries to pop a sample from the bottom of the FIFO. It also occurs in receive mode when the DMA or software attempts to read data from an empty FIFO. Reset this bit by writing a one to the SCT clear address space and not by a general write. This bit is set by hardware if the FIFO overflows during SAIF operation. Overflow occurs whenever a write or push is attempted to a full FIFO. This occurs in transmit mode if the FIFO is full and software or the DMA attempts to write additional data to the top of the FIFO. It also occurs in receive mode when the DMA or software does not respond in time to a service request, and the hardware attempts to push data to a full FIFO. Reset this bit by writing a one to the SCT clear address space and not by a general write. 4 This bit is set by hardware when the FIFO requires service. FIFO service requests are made when an FIFO_SERVICE_ empty entry exists during transmit or a full entry exists during receive. A DMA request is generated IRQ (DMA_PREQ toggles) each time this bit is set. Once the DMA or software has serviced the request and the FIFO is filled (TX) or emptied (RX), this bit is automatically cleared. This interrupt can be used by software to trigger the manual movement of samples from/to the SAIF's FIFO to/from a memory buffer when the SAIF's DMA channel is not used. 3-1 RSRVD0 0 BUSY Reserved. This bit indicates when the SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s). For transmit, it is automatically set when the first sample from the FIFO begins to be output by the serial shifter. For receive, it is set coincident with the RUN bit beging set as serial receive begins immediately. After the RUN bit is cleared and the serial shifter becomes inactive (end of the current sample set), this bit is automatically cleared. 35.3.3 SAIF Data Register (HW_SAIF_DATA) The SAIF Data Register is used to either write PCM data samples to the top of the SAIF FIFOs for transmit, or read PCM samples from the bottom of the FIFOs during receive. 32-bit values written/read to/from this register contain either one 17-bit to 24-bit sample or two 16-bit samples. HW_SAIF_DATA: 0x020 HW_SAIF_DATA_SET: 0x024 HW_SAIF_DATA_CLR: 0x028 HW_SAIF_DATA_TOG: 0x02C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2609 Programmable Registers In transmit mode, writing a value to this register causes it to push the value to the top of the FIFO. In receive mode, reads cause values to be popped from the bottom of the FIFO. Writing to a full FIFO does not change the contents of the FIFO's top entry, and reading from an empty FIFO returns all zeros. For 16-bit operation, the left sample should be written to the register's lower half word, and the right to the upper half word. For all other data sizes, PCM audio values should be right-justified within the 32-bit word. Three FIFOs exist, one for each channel pair. If two-channel operation is enabled, only the stereo or front FIFO is accessed. Four-channel opearation causes both the front and surround FIFOs to be accessed. Six-channel operation uses all three FIFOs: front, surround, and center/LFE FIFOs. For both transmit and receive FIFO accesses, left and right samples should be interleaved, starting with all left samples for a given sample time, followed by all right samples (e.g., left front, left surround, center, right front, right surround, LFE (subwoofer), and so on). Operation should always start with the left samples. All left or all right channels for a given sample collection in time are received/ transmitted simultaneously (e.g., for 6-channel mode, three PCM audio samples are popped from the FIFO prior to serialization and transmission). For mono operation, use the left channel to transmit/receive PCM audio, while the right channel should be zerofilled (TX) or discarded (RX). For transmit, if the FIFO is empty when operation begins, null (zero) data is output until the FIFO contains valid PCM data. Once a complete set of left samples resides within the bottom of the active FIFOs, the SAIF waits for the current collection of null samples (all left and right samples for a given time) to complete before transmitting the left sample collection from the FIFOs. EXAMPLE HW_SAIF_DATA = 0x12345678; // write 0x1234 to the right channel and 0x5678 to the left channel in 16 bit mode HW_SAIF_DATA = 0x12345678; // write 0x12345678 to either the left or right channel in 32 bit per sample mode. Address: 8004_2000h base + 20h offset = 8004_2020h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PCM_RIGHT 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PCM_LEFT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_SAIF_DATA field descriptions Field 31-16 PCM_RIGHT PCM_LEFT Description For 16-bit mode, this field contains the entire right channel sample. For 17-bit through 24-bit modes, this field contains 1 through 8 of the MSBs of the sample (either left or right). For 16-bit mode, this field contains the entire left channel sample. For 17-bit through 24-bit modes, this field contains the 16 LSBs of the sample (either left or right). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2610 Freescale Semiconductor, Inc. Chapter 35 Serial Audio Interface (SAIF) 35.3.4 SAIF Version Register (HW_SAIF_VERSION) The SAIF Version Register is read-only and is used for debug to determine the implementation version number for the block. EXAMPLE if (HW_SAIF_VERSION.B.MAJOR != 1) Error(); Address: 8004_2000h base + 30h offset = 8004_2030h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 HW_SAIF_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2611 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2612 Freescale Semiconductor, Inc. Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) 36.1 Overview The Sony-Philips Digital Interface Format (SPDIF) transmitter module transmits data according to the SPDIF digital audio interface standard (IEC-60958). Figure 36-1 shows a block diagram of the SPDIF transmitter module. Data samples are transmitted as blocks of 192 frames, each frame consisting of two 32bit sub-frames. A 32-bit sub-frame is composed of a 4-bit preamble, a 24-bit data payload (that is, a leftor right-channel PCM sample), and a 4-bit status field. The status fields are encoded according to the IEC-60958 consumer specification, reflecting the contents of the HW_SPDIF_FRAMECTRL and HW_SPDIF_CTRL registers. See the IEC-60958 specification for proper programming of these fields. The sub-frame is transmitted serially, LSB-first, using a biphase-mark channel-coding scheme. This encoding allows an SPDIF receiver to recover the embedded clock signal. Note Sub-frame information can be changed on-the-fly but is not reflected in the serial stream until the current frame is transmitted. This ensures consistency of the frame and the generated parity appended to that frame. 36.2 Operation The SPDIF transmitter operates at one of three register-selectable base sample rates: 32 KHz, 44.1 KHz, or 48 KHz. Double-rate output (64 KHz, 88.2 KHz, and 96 KHz) can also be selected using HW_SPDIF_SRR_BASEMULT. The data-clock required to i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2613 Operation transmit a SPDIF frame at these sample-rates is generated using a fractional clockdivider. This divider uses both edges of a 120 MHz clock, which is derived from a divide-by-4 of the PLL 480 MHz clock. This divider is located in the CLKCTRL module where all the system clocks are generated; the resultant clock (pcm_spdif_clk) is the output to the SPDIF module to be used for data transmission. Programming the HW_SPDIF_SRR register automatically generates the right frequency of pcm_spdif_clk from the divider in the clock controller block. There are no separate registers to control these dividers. Make sure that the CLKGATE bit in HW_CLKCTRL_SPDIF is cleared before starting the transmission. The SPDIF module receives data by one of two methods: * Software-directed PIO writes to the HW_SPDIF_DATA register * Appropriate programming of the DMA-engine. (See AHB-to-APBX Bridge Overview for a detailed description of the DMA module and how to perform DMA data transfers to/from modules and memory.) Once provided by the DMA, the received data is placed in a 2x24 word FIFO for each channel, left and right. At initialization, the FIFO is filled before SPDIF data transfer occurs. After this, data is requested whenever this FIFO has an empty entry or at a nominal rate corresponding to the programmed sample- rate in HW_SPDIF_SRR. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2614 Freescale Semiconductor, Inc. Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) ARM Core SRAM 24-MHz XTAL Osc. AHB AHB Slave AHB Master 480 MHz PLL Divide by n CLKCTRL Module Divide by 4 Dual-Edge Fractional Clock Divider Shared DMA Divide Ratio ROM AHB-to-APBX Bridge APBX Master Clock Divider APBX pcm_spdif_clk SPDIF Data Encoding SPDIF Programmable Registers DMA Data Flow Control HW_SPDIF_SRR DMA Request Engine HW_SPDIF_CTRL HW_SPDIF_SRR_RATE HW_SPDIF_FRAMECTRL SPDIF Stream Control FIFO Control and Request Generation 2x24 Left-Channel FIFO 2x24 Right-Channel FIFO Clock Crossing Data Formatting (16-Bit/24-Bit) SPDIF Data APBX Clock Domain pcm_spdif_clk Domain Figure 36-1. SPDIF Transmitter Block Diagram The behavior of the SPDIF module during or after a FIFO underflow is programmable. On detection of an underflow event, the SPDIF module sends the current sample for four frames before muting (sending zeros) the data stream based on the configuration of HW_SPDIF_FRAMECTRL_AUTO_MUTE. The final validity unit embedded within each frame dictates whether the receiver processes the data within that frame. HW_SPDIF_FRAMECTRL determines the behavior of this bit. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2615 Operation SPDIF Normal Operation 0 0 1 HW_SPDIF_ FRAMECTRL_V Underflow asserted after 4-frames consecutive frames w/empty FIFO HW_SPDIF_CTRL_FIFO _UNDERFLOW_IRQ 1 HW_SPDIF_FRAMECTRL_AUTO_MUTE 0 1 HW_SPDIF_DATA = 0 HW_SPDIF_DATA = LAST_VALUE HW_SPDIF_FRAMECTRL_V_CONFIG 0 Final Validity=0 Final Validity=0 1 Final Validity=1 Final Validity=1 Figure 36-2. SPDIF Flow Chart SPDIF data can be transmitted in one of two modes: 32-bit mode and 16-bit mode. Selection between these modes is done with the WORD_LENGTH bit in the HW_SPDIF_CTR register. In either case, data samples must be interleaved in main memory for proper behavior, although in 32-bit mode, 32-bit words are interleaved and in 16-bit mode, 16-bit words are interleaved. * When WORD_LENGTH = 0, 32-bit mode is enabled, and HW_SPDIF_DATA contains either the left or right data sample. Since the SPDIF frame allows for transmission of only 24 bits, only the 24 MSBs stored in the HW_SPDIF_DATA register will be transmitted. * Alternately, when WORD_LENGTH = 1, 16-bit mode is enabled, and the HW_SPDIF_DATA register will contain one of each left AND right samples. The data transmitted in the SPDIF frame will be these 16 MSBs with 8 zeros appended in the LSB positions. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2616 Freescale Semiconductor, Inc. Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) Note If the data supplied actually represents a lower resolution analog-to-digital conversion, this information is not captured by the SPDIF transmitter, which always reports a 24-bit samplesize. 36.2.1 Interrupts The SPDIF module contains a single interrupt source that is asserted on FIFO overflows and/or FIFO underflows. This interrupt is enabled by setting HW_SPDIF_CTRL_FIFO_ERROR_IRQ_EN. On interrupt detection, the HW_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ and HW_SPDIF_CTRL_FIFO_OVERFLOW_IRQ fields can be polled for the exact cause of the interrupt and appropriate action taken. Note These bits remain valid for polling, regardless of the state of the interrupt enable. 36.2.2 Clocking The IEC-60958 specification outlines the requirements for SPDIF clocking. The SPDIF module is designed according to the Consumer Audio requirements. These dictate that: * Average Sample-Rate Error must not exceed 1000 ppm * Maximum Instantaneous Jitter must not exceed ~4.4 ns. The jitter requirement implies either a single-phase of a >240 MHz clock or both phases of a 120 MHz clock. It also implies the use of a fractional divider for which the divisors are maintained to sufficient significant digits to yield the required ppm tolerance. The SPDIF module in the i.MX28 uses nine-bit fractional coefficients that yield an average frequency error of 52 ppm. These coefficients are determined according to the required clock-rates that are dictated by the sample rates implemented. The required clock frequencies provided by the CLKCTRL module for the implemented sample-rates are: F(48 kHz) 6.144 MHz F(44.1 kHz) 5.6448 MHz F(32 kHz) 4.096 MHz F(96 kHz) 12.288 MHz i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2617 Operation F(88.2 kHz) 11.2896 MHz F(64 kHz) 8.192 MHz All clocks within the SPDIF module are gated according to the state of HW_SPDIF_CTRL_CLKGATE. When set, all clocks derived from the apb_clk are gated. Gating of the pcm_spdif_clk is accomplished through HW_CLKCTRL_SPDIF_CLKGATE. A module-level reset is also provided in HW_SPDIF_CTRL_SFTRST. Setting this bit performs a module-wide reset and subsequent assertion of the HW_SPDIF_CTRL_CLKGATE. Note A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. 36.2.3 DMA Operation Using the SPDIF module in DMA mode involves configuring the appropriate DMA channel to provide the interleaved data blocks stored in memory. See AHB-to-APBX Bridge Overview for detailed information on DMA programming. Once programmed, the DMA engine references a set of linked DMA descriptors stored by the CPU in main memory. These descriptors point to data blocks stored in system memory and also provide a mechanism for automated PIO writes before transfer of a data-block. Figure 36-3 describes a typical set of descriptors required to transmit two data-blocks. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2618 Freescale Semiconductor, Inc. Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) NEXTCMD_ADDR 512 2 0 0 1 10 BUFFER ADDRESS HW_SPDIF_CTRL=0x00000002 HW_SPDIF_FRAMECTRL= 0x00030000 NEXTCMD_ADDR 512 2 0 0 1 10 BUFFER ADDRESS HW_SPDIF_CTRL=0x00000002 _ read HW_SPDIF_FRAMECTRL= 0x00030000 512-Byte Data Block 0 read NEXTCMD_ADDR 0 1 0 0 1 10 BUFFER ADDRESS HW_SPDIF_CTRL=0xC0000000 512-Byte Data Block 1 Figure 36-3. SPDIF DMA Two-Block Transmit Example Here, the DMA is instructed to perform two PIO writes prior to toggling the DMA_PCMDKICK signal: * HW_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ_EN is set to enable interrupts on FIFO underflow detect * HW_SPDIF_FRAMECTRL_AUTO_MUTE and HW_SPDIF_FRAMECTRL_V_CONFIG are set to mute and tag the data stream as invalid on a FIFO underflow. The DMA engine is then programmed to transfer 512-bytes to the SPDIF module. Additionally, the SPDIF module contains a mechanism for throttling DMA requests to the DMA engine. This circuit is programmed using the HW_SPDIF_CTRL_DMAWAIT_COUNT field and corresponds to the number of cycles of the apb_clk to wait before toggling the DMA_PREQ signal to the DMA engine. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2619 Operation Note Considering that the bandwidth requirements of the SPDIF module are minimal (not in excess of 96 KHz) and burst requests occur only in pairs, this field can be ignored for most, if not all, applications. There is a floor APBX frequency below which the SPDIF cannot work without errors. That frequency can be calculated as follows: * Assume that there are six other blocks apart from SPDIF on the APBX bus, and it takes four APBX clock cycles to service each block. If the number of clock cycles required to service each block changes, change the equations accordingly. * Assume that HW_SPDIF_CTRL_DMAWAIT_COUNT is less than DMA LATENCY. If this is not true, then even DMA WAIT has to be added to the calculation and the floor APBX frequency increases further. In 16-bit Mode: Floor APBX freq = (DMA latency + 9) * sample rate. For max DMA latency = (6 blocks) x (4 cycles per block) = 24 cycles and max SPDIF sample rate = 96 kHz, min APBX freq = 3.168 MHz. In 32-bit Mode: (A) Ideal Calculation: min freq = [2*(DMA latency+4) + 7] * sample rate. For max DMA latency = 24 cycles and max SPDIF sample rate = 96 kHz, min APBX freq = 6.048 MHz. (B) Simpler Calculation: Floor APBX freq = 2*(latency + 9) * sample rate = twice that of 16-bit mode. For max latency = 24 cycles and max sample rate = 96 kHz, min APBX freq = 6.336 MHz. Option A is ideal as it allows a lower floor frequency; option B can be used to keep it simple and avoid confusion. 36.2.4 PIO Debug Mode The block is connected only as a PIO device to the APBX bus. Even though it is designed to work with the DMA controller integrated in the APBX bridge, all transfers to and from the block are programmed I/O (PIO) read or write cycles. When the DMA is ready to write to the HW_SPDIF_DATA register, it does so with standard APB write cycles. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2620 Freescale Semiconductor, Inc. Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) There are four DMA related signals that connect the SPDIF transmitter to the DMA, but all data transfers are standard PIO cycles on the APB. The state of these four signals can be seen in the HW_SPDIF_DEBUG register. Therefore, it is possible to completely exercise the SPDIF block for diagnostic purposes, using only load and store instructions from the CPU without ever starting the DMA controller. This section describes how to interact with the block using PIO operations, and also defines the block's detailed behavior. Whenever the HW_SPDIF_CTRL register is written to, by either the CPU or the DMA, it establishes the basic operation mode for the block. If the HW_SPDIF_CTRL register is written with a 1 in the RUN bit, then the operation begins and the SPDIF attempts to read the data block by toggling its PDMAREQ signal to the DMA. Notice that the PDMAREQ signal is defined as a toggle signal. This changes state to signify either a request for another DMA word or a notification that the current command transfer has been ended by the SPDIF. Diagnostic software should poll these signals to determine when the SPDIF is ready for another DMA write, and can then supply data by storing a 32-bit word to the HW_SPDIF_DATA register, just as the DMA would perform in a normal operation. To perform SPDIF transfers in PIO debug mode, diagnostic software should perform the following: 1. Clear CLKGATE in the HW_CLKCTRL_SPDIF register. 2. Turn off the Soft Reset bit, HW_SPDIF_CTRL_SFTRST, and the Clock Gate bit, HW_SPDIF_CTRL_CLKGATE. 3. Properly configure the subcode information by writing the HW_SPDIF_FRAMECTRL register. NOTE: See IEC-60958 for proper coding of these fields. 4. Enable the SPDIF transmitter by setting HW_SPDIF_CTRL_RUN. 5. Wait for HW_SPDIF_DEBUG_DMA_PREQ status bit to toggle. 6. Write one sample of the left/righp t DATA block data to the HW_SPDIF_DATA register. 7. Repeat 5 and 6 until all samples have been written to HW_SPDIF_DATA. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2621 Programmable Registers 36.3 Programmable Registers SPDIF Hardware Register Format Summary HW_SPDIF memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8005_4000 SPDIF Control Register (HW_SPDIF_CTRL) 32 R/W C000_0020h 36.3.1/2622 8005_4010 SPDIF Status Register (HW_SPDIF_STAT) 32 R 8000_0000h 36.3.2/2624 8005_4020 SPDIF Frame Control Register (HW_SPDIF_FRAMECTRL) 32 R/W 0002_0000h 36.3.3/2626 8005_4030 SPDIF Sample Rate Register (HW_SPDIF_SRR) 32 R/W 1000_0000h 36.3.4/2627 8005_4040 SPDIF Debug Register (HW_SPDIF_DEBUG) 32 R 0000_0001h 36.3.5/2628 8005_4050 SPDIF Write Data Register (HW_SPDIF_DATA) 32 R/W 0000_0000h 36.3.6/2630 8005_4060 SPDIF Version Register (HW_SPDIF_VERSION) 32 R 0101_0000h 36.3.7/2631 36.3.1 SPDIF Control Register (HW_SPDIF_CTRL) HW_SPDIF_CTRL: 0x000 HW_SPDIF_CTRL_SET: 0x004 HW_SPDIF_CTRL_CLR: 0x008 HW_SPDIF_CTRL_TOG: 0x00C The SPDIF Control Register contains the overall control for SPDIF sample formats, loopback mode, and interrupt controls. EXAMPLE HW_SPDIF_CTRL.RUN = 1; // start SPDIF conversion i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2622 Freescale Semiconductor, Inc. Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) Address: 8005_4000h base + 0h offset = 8005_4000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 SFTRST CLKGATE 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WAIT_END_XFER WORD_LENGTH FIFO_UNDERFLOW_IRQ FIFO_OVERFLOW_IRQ FIFO_ERROR_IRQ_EN R RUN 1 0 0 0 0 0 DMAWAIT_COUNT W Reset Bit RSRVD0 R W Reset 0 0 0 0 0 0 0 0 0 0 HW_SPDIF_CTRL field descriptions Field 31 SFTRST 30 CLKGATE 29-21 RSRVD1 20-16 DMAWAIT_ COUNT 15-6 RSRVD0 Description Setting this bit to one forces a reset to the entire block and then gates the clocks off. This bit must be set to zero for normal operation. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. First set the CLKGATE bit in the HW_CLKCTRL_SPDIF register to 1. Only then, set this bit to 1 to prevent any extra samples from being transmitted. When removing clock gating, follow the reverse order: First reset this CLKGATE bit to 0, and then reset the CLKGATE bit in the HW_CLKCTRL_SPDIF register to 0 . Reserved DMA Request Delay Count. This bit field specifies the number of APBX clock cycles (0 to 31) to delay before each DMA request. This field acts as a throttle on the bandwidth consumed by the SPDIF block. This field can be loaded by the DMA. Reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2623 Programmable Registers HW_SPDIF_CTRL field descriptions (continued) Field 5 WAIT_END_ XFER Description Set this bit to a one if the SPDIF Transmitter should wait until the internal FIFO is empty before halting transmission based on deassertion of RUN. Use in conjuntion with HW_SPDIF_STAT_END_XFER to determine transfer completion 4 Set this bit to one to enable 16-bit mode. Set this bit to zero for 32-bit mode. In either case, the SPDIF WORD_LENGTH frame allows transmission of only 24 bits. In 16-bit mode, eight zeros will be appended to the LSB\'s of the input sample; in 32-bit mode, the 24 MSB\'s of HW_SPDIF_DATA will be transmitted. 3 This bit is set by hardware if the FIFO underflows during SPDIF transmission. Reset this bit by writing a FIFO_ one to the SCT clear address space and not by a general write. UNDERFLOW_ IRQ 2 FIFO_ OVERFLOW_ IRQ This bit is set by hardware if the FIFO overflows during SPDIF transmission. Reset this bit by writing a one to the SCT clear address space and not by a general write. 1 Set this bit to one to enable a SPDIF interrupt request on FIFO overflow or underflow status conditions. FIFO_ERROR_ IRQ_EN 0 RUN Setting this bit to one causes the SPDIF to begin converting data. The actual conversion will begin when the SPDIF FIFO is filled (4 or 8 words written, depending upon sample word format, i.e., 16 or 32 bits). 36.3.2 SPDIF Status Register (HW_SPDIF_STAT) HW_SPDIF_STAT: 0x010 HW_SPDIF_STAT_SET: 0x014 HW_SPDIF_STAT_CLR: 0x018 HW_SPDIF_STAT_TOG: 0x01C The SPDIF Status Register provides the status of the SPDIF converter. EXAMPLE unsigned TestBit = HW_SPDIF_STAT.PRESENT; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2624 Freescale Semiconductor, Inc. Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) Address: 8005_4000h base + 10h offset = 8005_4010h 31 R 30 29 28 27 26 25 24 PRESENT Bit 23 22 21 20 19 18 17 16 RSRVD1 W Bit 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 END_XFER Reset RSRVD1 R W Reset 0 0 0 0 0 0 0 0 0 HW_SPDIF_STAT field descriptions Field 31 PRESENT 30-1 RSRVD1 0 END_XFER Description This bit is set to 1 in products in which SPDIF is present. Reserved When set, indicates that the SPDIF module has completed transfer of all data, including data stored in internal FIFOs. Used in conjunction with HW_SPDIF_CTRL_WAIT_END_XFER. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2625 Programmable Registers 36.3.3 SPDIF Frame Control Register (HW_SPDIF_FRAMECTRL) HW_SPDIF_FRAMECTRL: 0x020 HW_SPDIF_FRAMECTRL_SET: 0x024 HW_SPDIF_FRAMECTRL_CLR: 0x028 HW_SPDIF_FRAMECTRL_TOG: 0x02C The SPDIF Frame Control Register provides direct control of the control bits transmitted over an SPDIF frame. EXAMPLE HW_SPDIF_FRAMECTRL.COPY=1 //SPDIF frame contains copyrighted material Address: 8005_4000h base + 20h offset = 8005_4020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD2 V_CONFIG AUTO_MUTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USER_DATA V L PRE COPY AUDIO R PRO 0 0 0 0 0 0 0 Bit R RSRVD0 Reset RSRVD1 W CC W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2626 Freescale Semiconductor, Inc. Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) HW_SPDIF_FRAMECTRL field descriptions Field 31-18 RSRVD2 17 V_CONFIG 16 AUTO_MUTE 15 RSRVD1 14 USER_DATA Description Reserved Defines SPDIF behavior when sending invalid frames. 0:Do NOT tag frame as invalid. 1: Tag frame as invalid. Auto-Mute Stream on stream-suspend detect. Reserved User data transmitted during each sub-frame. Consult IEC Standard for additional details. 13 V Indicates that a sub-frame\'s samples are invalid. If V=0, the sub-frame is indicated as valid, that is, correctly transmitted and received by the interface. If V=1, the subframe is indicated as invalid. 12 L Generation level is defined by the IEC standard, or as appropriate. 11 RSRVD0 Reserved 10-4 CC Category code is defined by the IEC standard, or as appropriate. 3 PRE 0: No Pre-Emphasis. 1: Pre-Emphasis is 50/15 usec. 2 COPY 0: Copyright bit NOT asserted. 1: Copyright bit asserted. 1 AUDIO 0:PCM Data;1:Non-PCM Data 0 PRO 0: Consumer use of the channel. 1: Professional use of the channel(Not Support). 36.3.4 SPDIF Sample Rate Register (HW_SPDIF_SRR) The SPDIF Sample Rate Register controls the sample rate of the data stream played back from the circular buffer. HW_SPDIF_SRR: 0x030 HW_SPDIF_SRR_SET: 0x034 HW_SPDIF_SRR_CLR: 0x038 HW_SPDIF_SRR_TOG: 0x03C The SPDIF Sample Rate Register provides a RATE field for specifying the sample rate conversion factor to use in outputting the current SPDIF stream. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2627 Programmable Registers HW_SPDIF_SRR.B.RATE = 0x0AC44; // 44.1KHz Address: 8005_4000h base + 30h offset = 8005_4030h 31 R 30 29 28 27 26 25 RSRVD1 Bit 24 23 22 21 20 19 18 17 16 RSRVD0 BASEMULT RATE W Reset Bit 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R RATE W Reset 0 0 0 0 0 0 0 0 HW_SPDIF_SRR field descriptions Field 31 RSRVD1 30-28 BASEMULT 27-20 RSRVD0 RATE Description Reserved Base-Rate Multiplier. 1 = Single-Rate (48 kHz). 2 = Double-Rate (96 kHz). Reserved Sample-Rate Conversion Factor. The only valid entries are: 0x07D00, 0x0AC44, 0x0BB80 // 32k, 44.1k, 48k 36.3.5 SPDIF Debug Register (HW_SPDIF_DEBUG) The SPDIF Debug Register provides read-only access to various internal state information that may be useful for block debugging and validation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2628 Freescale Semiconductor, Inc. Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) HW_SPDIF_DEBUG: 0x040 HW_SPDIF_DEBUG_SET: 0x044 HW_SPDIF_DEBUG_CLR: 0x048 HW_SPDIF_DEBUG_TOG: 0x04C This is a read-only register used for checking FIFO status and PIO mode of operation. EXAMPLE unsigned TestBit = HW_SPDIF_DEBUG.DMA_PREQ; Address: 8005_4000h base + 40h offset = 8005_4040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIFO_STATUS Reset DMA_PREQ W 0 0 0 0 0 0 0 1 RSRVD1 R W Reset 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2629 Programmable Registers HW_SPDIF_DEBUG field descriptions Field Description 31-2 RSRVD1 Reserved 1 DMA_PREQ DMA request status. This read-only bit reflects the current state of the SPDIF\'s DMA request signal. DMA requests are issued any time the request signal toggles. This bit can be polled by software, in order to manually move samples to the SPDIF\'s FIFO from a memory buffer when the SPDIF\'s DMA channel is not used 0 FIFO_STATUS This bit is set when the FIFO has empty space. This reflects a DMA request being generated. 36.3.6 SPDIF Write Data Register (HW_SPDIF_DATA) The SPDIF Write Data Register receives 32-bit data transfers from the DMA. It deposits the data into an internal FIFO and from there into the SPDIF stream. These 32-bit writes contain either one 32-bit sample or two 16-bit samples. HW_SPDIF_DATA: 0x050 HW_SPDIF_DATA_SET: 0x054 HW_SPDIF_DATA_CLR: 0x058 HW_SPDIF_DATA_TOG: 0x05C Writing a 32-bit value to the register corresponds to pushing that 32-bit value into the SPDIF FIFO. The DMA writes 32-bit values to this register. In 32-bit-per-sample mode, the DMA is writing either one full left sample or one full right sample for each write to this register. For 16-bit mode, the DMA is writing a 16-bit left sample and a 16-bit right sample for each 32-bit write to this register. EXAMPLE HW_SPDIF_DATA = 0x12345678; // write 0x1234 to the right channel and 0x5678 to the left channel in 16-bit mode HW_SPDIF_DATA = 0x12345678; // write 0x12345678 to either the left or right channel in 32-bit per sample mode. Address: 8005_4000h base + 50h offset = 8005_4050h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 HIGH 0 0 0 0 0 0 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LOW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2630 Freescale Semiconductor, Inc. Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF) HW_SPDIF_DATA field descriptions Field Description 31-16 HIGH For 16-bit mode, this field contains the entire right channel sample. For 32-bit mode, this field contains the 16 MSBs of the 32-bit sample (either left or right). LOW For 16-bit mode, this field contains the entire left channel sample. For 32-bit mode, this field contains the 16 LSBs of the 32-bit sample (either left or right). 36.3.7 SPDIF Version Register (HW_SPDIF_VERSION) The SPDIF Version Register is read-only and is used for debug to determine the implementation version number for the block. EXAMPLE if (HW_SPDIF_VERSION.B.MAJOR != 1) Error(); Address: 8005_4000h base + 60h offset = 8005_4060h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 HW_SPDIF_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2631 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2632 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) 37.1 Overview The high-speed ADC block is designed for driving the linear image scanner sensor (for example, TOSHIBA TCD1304DG linear image scanner sensor). It can also support some other general user cases which need to sample analog source with up to 2 Msps data rate and then move the sample data to the external memory. The high-speed ADC block integrates a 12-bit analog ADC block. This analog ADC block can support up to 2 Msps sample rate. In order to improve the flexibility, the high-speed ADC block can co-work with PWM block which can generate driving signals of external device such as the linear image scanner sensor. The PWM can also generate trigger signal which is synchronous with high-speed ADC block to start the conversion of ADC. An APBH-DMA channel is connected to the high-speed ADC block to move the sample data from the asynchronous FIFO inside the high-speed ADC block to the external memory. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2633 High-Speed ADC Block Features ARM Core System Clock Generator AHB AHB-to-APBH Bridge AHB Slave AHB Master DMA Controller HCLK REF_HSADC DMA Request APBH Master APBH HSADC DMA Slave Async FIFO CLK_HSADC HSADC_Ctrl registers FSM ADC control logics 12-bits ADC Figure 37-1. Top-Level Block Diagram of High-Speed ADC Block 37.2 High-Speed ADC Block Features The main features of high-speed ADC block are as following: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2634 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) 37.2.1 Sample Rate and Sample Precision This block integrates an analog ADC block which can support up to 12-bit sample precision and 2 Msps sample rate. It can also be configured as 10-bit or 8-bit sample precision. The sample rate can be lower than 2 Msps depending on the user cases. For 10bit mode and 8-bit mode, the user can choose how many bits should be left shifted out before stored. To get a lower sample rate, just need to configure the CLKCTRL block to generate an operation clock with clock frequency of 16x of sample rate. 37.2.2 Trigger Modes This block can be triggered to start the conversion of analog source by three modes: the first mode is software trigger mode which is to trigger it by ARM CPU to configure a register bit in this block; the second mode is to trigger it by a trigger signal which is generated by the PWM block with big flexibility; the third is to trigger it by an input pin from external sources to support some general user cases. 37.2.3 APBH-DMA Channel This block is connected to a channel of APBH-DMA to move the sample data from the 16x32 asynchronous FIFO inside the block to the external memory. The APBH-DMA can run at up to 200 MHz clock frequency to reduce the possibility of FIFO overflow. The DMA can also offload the loading of ARM core when the high-speed ADC is working in the loop mode. 37.2.4 Synchronization with PWM Block This block uses an operation clock the same as the PWM block. It can make it possible that the PWM generate driving signals of external devices and then keep synchronous with high-speed ADC. This will improve the design flexibilities. By selecting the trigger mode of PWM trigger, the high-speed ADC can co-work with the PWM block to support many different user cases. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2635 Operation 37.2.5 Clock Domains This block includes two clock domains. One is the AHB clock domain which is synchronous with the APBH clock. The other is operation clock domain which is the same as the analog operation clock. The AHB clock domain can run at up to 200 MHz clock frequency while the operation clock domain can only run at up to 32 MHz clock frequency. The operation clock needs to be with duty cycle ratio of 25%. 37.2.6 Sample Precision, Endian, Half-word Swap and Bits LeftShift The original output of the analog ADC block is 12-bit data. The user can configure the register to get 12-bit,10-bit or 8-bit sample data. For 12-bit or 10-bit modes, two samples are combined to be a 32-bit word. For 8-bit mode, four samples are combined to be a 32bit word. When using 8-bit mode or 10 bit mode, the user can select any consequential 8 bit or 10 bit sample data from the 12-bit sample data by configuring the register. The sample data are put together to be a 32-bit word before written to the FIFO. The user can also configure the register to get big-endian or little-endian and also half-word-swapped data in the external memory. This operation is done when sample data are read out from the FIFO. 37.3 Operation The main target of this block is to drive the linear image scanner sensors, especially the TOSHIBA TCD1304DG linear image scanner sensor. To drive this sensor, three driving signals are needed. In order to support other linear image scanner sensors, the driving signals are generated by the PWM block which can improve the design flexibilities. Each PWM instance can be configured as any type of cyclic signal. In order to keep synchronous with the ADC block, the PWM can be configured to use the operation clock of ADC block to generate the driving signals of external devices. When the high-speed ADC is started by the ARM or DMA, it will enter the state to wait for a trigger to start sampling the analog input source. There are three modes to generate this trigger signal. When configured as PWM trigger mode, the PWM can generate the trigger signal with the operation clock to trigger the high-speed ADC to start the sampling. This trigger signal can be generated by any one of the PWM instances and is hard-wire connected to the high-speed ADC block. In order to make it possible for adjusting the sampling point in order to improve the S/N ratio of sample data, some delay cycles of operation clock can be added between the trigger pulse and the time to start sampling. The number of delay cycles can be configured. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2636 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) There is a 16x32 asynchronous FIFO inside the high-speed ADC with 32-bit width and 16-word depth. The sample data is formed as 32-bit word and then written to the FIFO. When the data is read out, it is reformed to the correct endian and half-word-swapped type. The APBH-DMA will then move the data to the external memory. It is flexible to configure the DMA to put the sample data if there are some requirements about the data format in the external memory, such as line strides, and so on. It is recommended to use one DMA command for each sequence of sample data. So, in loop modes of the highspeed ADC, many sequences of sample data need to be transferred to the external memory which will need a DMA command link to conduct the task. The high-speed ADC will signify the DMA to switch to the next command when one sequence is completed. For general user cases, the design also provides software trigger mode and external trigger mode. The sample data transferring is also done by the APBH-DMA. Clock for ADC divider 288MHz Clock Block AHB clock 200MHz Sampling clock 32MHz 32MHz PWM Trigger signal HSADC Ctrl signals Sample data ADC Analog pixel data Sensor control signals Linear image sensor Figure 37-2. Clock paths of the PWM and High-Speed ADC blocks i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2637 Operation 37.3.1 Trigger Modes This block can be triggered to start the conversion of analog source by three modes: the first mode is software trigger mode which is to be triggered by ARM to configure a register in this block; the second mode is to be triggered by a trigger pulse which is generated by the PWM block with big flexibility; the third is to be triggered by an input pin from external sources to support some general user cases. The trigger signal is active high. The duration of the active high pulse needs to be longer than one AHB clock cycle. The trigger signal needs to be de-asserted once the ADC is started. So, it is recommended to assert just one cycle for PWM trigger mode. For external trigger mode, the trigger signal should last for more than one AHB clock cycle. Due to synchronization issue, in all the three trigger modes there will be two AHB clock cycles and two operation clock cycles delay between the trigger pulse and the start of sampling when the delay cycles are configured as 0. Note that for PWM trigger mode, the trigger pulse is generated by operation clock, so the delay cycles should be three operation cycles. Please refer to the Figure 37-3 for the timing of PWM trigger mode and Figure 37-4 for the timing of analog ADC interface. AHB Clock Operation Clock PWM Trigger ADC Enable Figure 37-3. Timing of PWM Trigger Mode i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2638 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) Operation Clock ...... ADC Enable . ... ... ADC Data Valid ...... ...... D ADC Data [11:0] Figure 37-4. Timing of analog ADC interface 37.3.2 Sample Data Bits Left Shift The original output of the analog ADC block is 12-bit data. When using 8-bit mode or 10-bit mode, the user can configure the ADC_SAMPLE_SHIFT_BITS_NUM in HSADC Control Register 0 to determine the number of bits required to be left-shifted out. So, the user can choose any 8 bit or 10 bit consequential sample data to be stored into the external memory. Note that when in 8-bit mode, the number of left-shifted bits can be from zero to four while in 10-bit mode, the number can only be from zero to two. This feature can be useful to cover all the amplitude range of the analog input source. A D C s a m p le d a ta B it 1 1 B it 1 0 B it 9 B it 8 B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 B it 1 B it 9 B it 8 B it 7 B it 6 B it 5 B it 4 B it 3 B it 2 B it 1 B it 0 B it 0 L e ft s h ift 8 b its F IF O d a ta 1 0 b its F IF O d a ta Figure 37-5. Left Shift Bits of Sample Data 37.3.3 Bits Location The original output sample data is 12-bits. The user can configure the ADC_SAMPLE_PRECISION bits in HSADC Control Register 0 to determine the bits used for one sample. When 8-bits mode is selected, four sample data will be put in one word as Figure 37-6 indicate. When 10-bits mode is selected, two sample data will be put in one word as Figure 37-7 indicate. When 12-bits mode is selected, two sample data will be put in one word as Figure 37-8 indicate. In 10-bits mode and 12-bits mode, the bit31bit29 and bit15-bit13 are used for storing the channel number from which this sample is i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2639 Operation captured. Then the software can sort the data in external memory and store to different memory space by the channel number. This feature is useful when there are channels switching for capturing the samples from many channels. Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Sample data 2 Sample data 3 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 Bit 1 Bit 0 Sample data 0 Sample data 1 Figure 37-6. Bits Location Of Sample Data In 8-bits Mode Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Channel number Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Channel number Sample data 1 Bit 5 Bit 4 Bit 3 Bit 2 Sample data 0 Figure 37-7. Bits Location Of Sample Data In 10-bits Mode Bit 31 Bit 30 Bit 29 Bit 28 Channel number Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Sample data 1 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Channel number Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Sample data 0 Figure 37-8. bits location of sample data in 12-bits mode 37.3.4 Configuration of APBH-DMA There is one APBH-DMA channel connected to HSADC. Once there is sample data written into the asynchronous FIFO inside the high-speed ADC block, the high-speed ADC block will assert the dma_req, then the DMA will read the sample data through the APBH bus and then write to the external memory. When the user case is to drive a linear image scanner sensor, it is suggested to use one DMA command to transfer one sequence of sample data. And when one sequence is finished, the high-speed ADC block will assert dma_end so that the DMA can switch to the next command. The dma_run can also start the high-speed ADC block. So when dma_run is asserted, the high-speed ADC block will enter into the status to wait for the trigger pulse. 37.3.5 Configuration of PWM There is a hard-wired connection between PWM block and high-speed ADC block. This wire is for PWM block to trigger the high-speed ADC to start the sampling. When the user case is to drive a linear image scanner sensor, it is suggested to generate the sensor driving signals by the operation clock, and use another PWM instance to generate the trigger signal. It is required that the trigger pulse is active high and the duration is longer than one operation clock cycle. The user can control time of the trigger pulse to control the sampling point of ADC. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2640 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) 37.3.6 Configuration of High-speed ADC There are two working mode which can be chosen, single mode and loop mode. For loop mode, the high-speed ADC block enters into the status to wait for another trigger pulse once the current sequence is finished. The number of samples and sequences can be configured. There are up to eight channels, the user can choose one of the eight channels by configuring the register. Also, the delay cycles between the trigger pulse and the time to start sampling can be controlled by configuring register. Note that there are also two AHB clock cycles and two operation clock cycles delay that are required to be added. The sample precision, endian and whether to do half-word-swap can also be configured. There are three trigger modes which can be selected as mentioned above. When hsadc_run bit is set, all these settings take effect. The user can change these parameters when the ADC is working on the current sequence and will take effect when hsadc_run bit is set again. When DMA get the dma_req toggled, it will read out the sample data by APBH bus. It is also possible that the ARM CPU reads the sample data through the APBH bus in some special user cases. When one sequence is finished, all the sample data will be flushed out to the external memory. If it is not an integer number of word, the unfilled bits will be left empty. There are some read-only registers which contain necessary information for debugging, such as the current state, the state machines inside the block, and sample number captured and sequence number finished, and so on. If DCDC converter works to provide supply voltage, in order to attenuate the impact of DCDC noise on HSADC performance, it is recommended to set the sampling rate of HSADC to 1.5 Msps and set the register HW_POWER_ANACLKCTRL(0x80044160) as 0x84000626. But, there would be some initial delay time (less than 0.67 us) between HSADC starting conversion and 'start' command coming from software trigger or PWM trigger. If the initial delay time is not desired, it is recommended to set the register HW_POWER_ANACLKCTRL(0x80044160) as 0x84000426 and use PWM trigger mode. 37.3.7 Interrupt Sources There are two ways for ARM CPU to talk with the high-speed ADC block. One is by polling the interrupt bit in HSADC Control Register 1. The other is by interrupt. The ARM can choose one of these two modes by configure register. The user can enable the interrupt so that when one sequence is done, the interrupt is asserted. and when the asynchronous FIFO overflow occurs, the FIFO_OVERFLOW interrupt is asserted. Normally, the FIFO overflow will seldom occur because the APBH-DMA is working on 200 MHz clock frequency and the maximum sampling rate is 2 Msps for 12-bit sample data which means that the maximum data rate is 1 MHz word. So, the bandwidth of i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2641 Operation DMA should be enough to avoid the FIFO overflow. When overflow occurs, the FIFO will discard 16 words of sample data and then continues working. There is TIMEOUT interrupt which will be asserted when the block is pending. When the ARM CPU enters into interrupt mode, it should first clear the interrupt by setting INTERRUPT_CLR bit. Then, check the HSADC Control Register 1 for the interrupt status. Then, set INTERRUPT_STATUS_CLR bit to clear the interrupt status bits. 37.3.8 Working Modes There are two working modes for HSADC. When the value set to HSADC Sequence Number Register is 1, the HSADC is working in single mode; When the value set to HSADC Sequence Number Register is not 1, the HSADC is working in loop mode. 37.3.8.1 Single Mode For single mode, the HSADC just captures one sequence of sample data. The number of sample data need to be captured can be controlled by configuring the HSADC Sequence Samples Number Register. Note that when set the value of HSADC Sequence Samples Number Register as 0, it means endless capturing of samples till the disassertion of HSADC_RUN bit in HSADC Control Register 0. 37.3.8.2 Loop Mode For loop mode, the HSADC will capture more than one sequence of sample data. The number of samples for each sequence can be configured just the same as single mode. When one sequence is finished, the HSADC will automatically enter the state to wait for the next trigger pulse to start the next sequence of sampling. The number of sequences can be configured in HSADC Sequence Number Register. Please note that when set the value of HSADC Sequence Number Register as 0, it means endless capture of sequences till the disassertion of HSADC_RUN bit in HSADC Control Register 0. 37.3.9 Debugging Information There are three read-only registers providing some useful information for debugging. HW_HSADC_DBG_INFO0 provides HSADC_FSM_STATE , DMA_FSM_STATE and DMA_REQ. The HSADC_FSM_STATE and DMA_FSM_STATE provides the state of the FSMs inside the block, and the FIFO_READ_EMPTY can be used by ARM CPU for i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2642 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) polling the status of the FIFO. 1 means there is no data in the FIFO, 0 means there is data in the FIFO. So, for some special user cases the ARM CPU can also read the data from the asynchronous FIFO once there is data ready. The HW_HSADC_DBG_INFO1 provides the sample count number of the current sequence already finished. The HW_HSADC_DBG_INFO2 provides sequence count number already finished. 37.3.10 Behavior During Reset A soft reset (SFTRST) can take multiple clock cycles to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. 37.4 Programming Example The main target of this block is to drive the linear image scanner sensors, especially the TOSHIBA TCD1304DG linear image scanner sensor. Let's take TOSHIBA TCD1304DG linear image scanner sensor for example. Below is the steps to configure the APBHDMA,PWM and HSADC blocks: 1. Configure the clock block to output clock to the analog ADC block. Then the analog ADC block will generate operation clock for the HSADC block and PWM block. The frequency of the clock output to analog ADC block is 288MHz. Then the divider in ADC block will divide the clock to 16x of the sample rate needed. For example, When 2Msps needed, the clock frequency output by the divider should be 32MHz. 2. Clear the clock gating bits and soft reset bits for HSADC, PWM and APBH-DMA block. 3. Configure the HSADC block.Clear the POWER_DOWN bit in HSADC Control Register 2. Assert the ADC_PRECHARGE bit in HSADC Control Register 2 so that the analog ADC block can enter into a stable status and be ready for conversion. Once all the parameters are set, set the hsadc_run bit in HSADC Control Register 0. Then the HSADC block is in the state to wait the trigger pulse to start the conversion. 4. Configure the registers of APBH-DMA, write commands to external memory. 5. Configure the PWM block. The sensor needs three driving signals. Select three PWM instances to generate the three driving signals with the operation clock. Select another PWM instance to generate the trigger signals. Then start all these four PWM instances at the same time. Then the trigger pulse generated by PWM block will start the conversion of HSADC. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2643 Programmable Registers 6. The ARM CPU keeps polling the interrupt bit of HSADC or waits for the interrupt of HSADC. For general purpose, the steps are almost the same as above. The difference is the trigger modes. The HSADC will start the conversion once triggered. 37.5 Programmable Registers HSADC Hardware Register Format Summary HW_HSADC memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8000_2000 HSADC Control Register 0 (HW_HSADC_CTRL0) 32 R/W C000_0040h 37.5.1/2644 8000_2010 HSADC Control Register 1 (HW_HSADC_CTRL1) 32 R/W F000_0020h 37.5.2/2648 8000_2020 HSADC Control Register 2 (HW_HSADC_CTRL2) 32 R/W 0000_238Eh 37.5.3/2651 8000_2030 HSADC Sequence Samples Number Register (HW_HSADC_SEQUENCE_SAMPLES_NUM) 32 R/W 0000_0000h 37.5.4/2652 8000_2040 HSADC Sequence Number Register (HW_HSADC_SEQUENCE_NUM) 32 R/W 0000_0000h 37.5.5/2653 8000_2050 HSADC FIFO Data Register (HW_HSADC_FIFO_DATA) 32 R 0000_0000h 37.5.6/2654 8000_2060 HSADC Debug Information 0 Register (HW_HSADC_DBG_INFO0) 32 R 0000_0000h 37.5.7/2654 8000_2070 HSADC Debug Information 1 Register (HW_HSADC_DBG_INFO1) 32 R 0000_0000h 37.5.8/2655 8000_2080 HSADC Debug Information 2 Register (HW_HSADC_DBG_INFO2) 32 R 0000_0000h 37.5.9/2656 8000_20B0 HSADC Version Register (HW_HSADC_VERSION) 32 R 0001_0000h 37.5.10/ 2656 37.5.1 HSADC Control Register 0 (HW_HSADC_CTRL0) The HSADC Control and Status Register specifies the reset state, trigger sources, and software enable. HW_HSADC_CTRL0: 0x000 HW_HSADC_CTRL0_SET: 0x004 HW_HSADC_CTRL0_CLR: 0x008 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2644 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) HW_HSADC_CTRL0_TOG: 0x00C The HSADC Control and Status Register specifies the reset state, trigger sources, and software enable,etc. EXAMPLE HW_HSADC_CTRL0_WR(0x0000001f); Address: 8000_2000h base + 0h offset = 8000_2000h 30 29 28 SFTRST CLKGATE R 1 1 TRIGGER_ SOURCE W Reset 0 0 27 26 25 0 24 23 22 21 20 19 18 17 RSRVD1 DISCARD 0 0 0 0 0 0 0 0 ADC_ SAMPLE_ PRECISION 0 0 16 ADC_SAMPLE_ENDIAN 31 SOFTWARE_TRIGGER Bit 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2645 Programmable Registers 13 12 11 10 9 8 7 6 5 4 3 2 1 RSRVD0 ADC_SAMPLE_ SHIFT_BITS_NUM TRIGGER_DELAY_CYCLES 0 HSADC_RUN 14 HSADC_PRESENT R ADC_SAMPLE_HALFWORD_SWAP 15 Bit W Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 HW_HSADC_CTRL0 field descriptions Field 31 SFTRST Description This bit must be cleared to 0 for normal operation. When set to 1, it forces a block-wide reset. 30 CLKGATE This bit must be cleared to 0 for normal operation. When set to 1, it gates off the clocks to the block. 29-28 TRIGGER_ SOURCE This bit field specifies the trigger mode of ADC.Take effect when hsadc_run is asserted. 00: ADC is triggered by the software. 01: ADC is triggered by the PWM trigger signal. 10: ADC is triggered by the input signal from outside the chip. 11: no trigger. 27 SOFTWARE_ TRIGGER When set to 1'b1,trigger the ADC to start the conversion.This bit can be auto cleared. 26-21 RSRVD1 Reserved. 20-19 DISCARD This bit field specifies the number of samples to be discarded whenever the analog ADC is firstly powered up.Take effect when hsadc_run is asserted. 00= discard first sample 01= discard first 2 samples Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2646 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) HW_HSADC_CTRL0 field descriptions (continued) Field Description 10= discard first 3 samples 11= discard first 4 samples 1_SAMPLE = 0x0 discard first sample before first capture. 2_SAMPLES = 0x1 discard 2 samples before first capture. 3_SAMPLES = 0x2 discard 3 samples before first capture. 4_SAMPLES = 0x3 discard 4 samples before first capture. 18-17 This bit field specifies the precision of sample data.Take effect when hsadc_run is asserted. ADC_SAMPLE_ 00= When set to 2'b00,the HSADC output 8-bits sample data. PRECISION 01= When set to 2'b01,the HSADC output 10-bits sample data. 10= When set to 2'b10,the HSADC output 12-bits sample data. 11= When set to 2'b11,no data output. 16 This bit field specifies the endian of sample data.Take effect when hsadc_run is asserted. ADC_SAMPLE_ 0= When set to 1'b0,the HSADC outputs little endian sample data. ENDIAN 1= When set to 1'b1,the HSADC outputs big endian sample data. 15 This bit field specifies whether to do halfword swap on the sample data.Take effect when hsadc_run is ADC_SAMPLE_ asserted. HALFWORD_ 0= When set to 1'b0,the HSADC don't swap the output sample data. SWAP 1= When set to 1'b1,the HSADC do 16-bits swap on the output sample data. 14-12 This bit field specifies the bits number of sample data to be left shifted.Take effect when hsadc_run is ADC_SAMPLE_ asserted. SHIFT_BITS_ 000= When set to 3'b000,the sample data remains unchanged. NUM 001= When set to 3'b001,the sample data be left shifted 1 bit. 010= When set to 3'b010,the sample data be left shifted 2 bit. 011= When set to 3'b011,the sample data be left shifted 3 bit. 100= When set to 3'b100,the sample data be left shifted 4 bit. When set to other value,the sample data remains unchanged. For 8-bits mode,all these setting are valid.For 10-bits,only 3'b000,3'b001,3'b010 are valid. 11-7 RSRVD0 6 HSADC_ PRESENT Reserved. This read-only bit returns 1 when the HSADC function block is present on the chip. 5-1 Set the cycles between the triggers happen and the ADC starts the conversion.Take effect when TRIGGER_ hsadc_run is asserted. DELAY_CYCLES 0 HSADC_RUN When set to 1'b1,the HSADC loads the parameters in the registers and starts to run. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2647 Programmable Registers 37.5.2 HSADC Control Register 1 (HW_HSADC_CTRL1) The HSADC Control Register 1 specifies interrupt status. HW_HSADC_CTRL1: 0x010 HW_HSADC_CTRL1_SET: 0x014 HW_HSADC_CTRL1_CLR: 0x018 HW_HSADC_CTRL1_TOG: 0x01C This register specifies interrupt status of HSADC. EXAMPLE HW_HSADC_CTRL1_WR(0x0000001f); Address: 8000_2000h base + 10h offset = 8000_2010h 26 INTERRUPT_STATUS_CLR 27 INTERRUPT_CLR Reset 28 INTERRUPT_TIMEOUT_ENABLE W 29 INTERRUPT_FIFO_OVERFLOW_ENABLE R 30 INTERRUPT_ADC_DONE_ENABLE 31 INTERRUPT_END_ONE_SEQUENCE_ENABLE Bit 1 1 1 1 0 0 25 24 23 22 21 20 19 18 17 16 0 0 0 0 RSRVD1 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2648 Freescale Semiconductor, Inc. 10 9 8 7 6 0 0 0 0 RSRVD1 R 5 4 3 2 1 0 INTERRUPT 11 INTERRUPT_TIMEOUT_STATUS 12 INTERRUPT_FIFO_OVERFLOW_STATUS 13 INTERRUPT_ADC_DONE_STATUS 14 INTERRUPT_END_ONE_SEQUENCE_STATUS 15 Bit FIFO_READ_EMPTY Chapter 37 High-Speed ADC (HSADC) 1 0 0 0 0 0 W Reset 0 0 0 0 0 0 HW_HSADC_CTRL1 field descriptions Field 31 INTERRUPT_ END_ONE_ Description When set to 1'b1,the HSADC asserts interrupt when one sequence is finished.When set to 1'b0,the HSADC does not assert interrupt when one sequence is finished. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2649 Programmable Registers HW_HSADC_CTRL1 field descriptions (continued) Field Description SEQUENCE_ ENABLE 30 INTERRUPT_ ADC_DONE_ ENABLE When set to 1'b1,the HSADC asserts interrupt when all sequences are finished.When set to 1'b0,the HSADC does not assert interrupt when all sequences are finished. 29 INTERRUPT_ FIFO_ OVERFLOW_ ENABLE When set to 1'b1,the HSADC asserts interrupt when FIFO overflow occurs.When set to 1'b0,the HSADC does not assert interrupt when FIFO overflow occurs. 28 INTERRUPT_ TIMEOUT_ ENABLE When set to 1'b1,the HSADC asserts interrupt when timeout occurs.When set to 1'b0,the HSADC does not assert interrupt when timeout occurs. 27 INTERRUPT_ CLR When set to 1'b1,clear the HSADC interrupt.This bit can be auto cleared. 26 INTERRUPT_ STATUS_CLR When set to 1'b1,clear all the HSADC interrupt status.This bit can be auto cleared. 25-6 RSRVD1 Reserved. 5 FIFO_READ_ EMPTY FIFO read empty. 1 means there is no data in the FIFO, 0 means there is data in the FIFO. 4 INTERRUPT_ END_ONE_ SEQUENCE_ STATUS This bit is set to one upon one sequence is finished.It is ANDed with its corresponding interrupt enable bit to request an interrrupt.Can be cleared by INTERRUPT_STATUS_CLR bit. 3 INTERRUPT_ ADC_DONE_ STATUS This bit is set to one upon all the sequences are finished.It is ANDed with its corresponding interrupt enable bit to request an interrrupt.Can be cleared by INTERRUPT_STATUS_CLR bit. 2 INTERRUPT_ FIFO_ OVERFLOW_ STATUS This bit is set to one upon FIFO overflow occurred.It is ANDed with its corresponding interrupt enable bit to request an interrupt.Can be cleared by INTERRUPT_STATUS_CLR bit. 1 INTERRUPT_ TIMEOUT_ STATUS This bit is set to one upon timeout occur.It is ANDed with its corresponding interrupt enable bit to request an interrupt.Can be cleared by INTERRUPT_STATUS_CLR bit. 0 INTERRUPT Set to 1 when an interrupt is raised. Can be cleared by the INTERRUPT_CLR bit.The host CPU can poll this bit for the polling mode. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2650 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) 37.5.3 HSADC Control Register 2 (HW_HSADC_CTRL2) The HSADC Control Register 2 specifies analog ADC config bits. HW_HSADC_CTRL2: 0x020 HW_HSADC_CTRL2_SET: 0x024 HW_HSADC_CTRL2_CLR: 0x028 HW_HSADC_CTRL2_TOG: 0x02C This register specifies the config bits for analog ADC block. EXAMPLE HW_HSADC_CTRL2_WR(0x0000001f); Address: 8000_2000h base + 20h offset = 8000_2020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC_SH_BYPASS 1 1 0 0 RSRVD1 W Reset 0 0 1 SAH_GAIN_ADJ 0 0 0 SAH_BIAS_ ADJ 1 0 ADC_CHANNEL_ SEL 1 1 1 ADC_PRECHARGE 0 ONCHIP_GROUND R 0 DAC_ADJCURRENT Bit 0 POWER_DOWN Reset DAC_ADJHEADROOM W 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2651 Programmable Registers HW_HSADC_CTRL2 field descriptions Field 31-14 RSRVD1 Description Reserved. 13 Power down the analog ADC block. POWER_DOWN 12-10 Control the gain of sample and hold module in HSADC. SAH_GAIN_ADJ 9 Adjust the headroom of current sources of sub-DAC. DAC_ ADJHEADROOM 8 DAC_ ADJCURRENT Adjust the current of sub-DAC. 7-6 Adjusting the settling time of the sample-ana-hold circuit in front of the hsadc. SAH_BIAS_ADJ 5 ONCHIP_ GROUND Switch the ground of sub-DAC between quiet ground and onchip ground. 4 ADC_SH_ BYPASS ADC sample and hold logics bypass. 3-1 This bit field specifies the pin names of the analog source to be converted. ADC_CHANNEL_ 000= When set to 3'b000,the HSADC select the LRADC0 pin as analog source input. SEL 001= When set to 3'b001,the HSADC select the LRADC1 pin as analog source input. 010= When set to 3'b010,the HSADC select the LRADC2 pin as analog source input. 011= When set to 3'b011,the HSADC select the LRADC3 pin as analog source input. 100= When set to 3'b100,the HSADC select the LRADC4 pin as analog source input. 101= When set to 3'b101,the HSADC select the LRADC5 pin as analog source input. 110= When set to 3'b110,the HSADC select the LRADC6 pin as analog source input. 111= When set to 3'b111,the HSADC select the HSADC0 pin as analog source input. 0 ADC_ PRECHARGE ADC precharge enable.Should be set before start ADC conversion. 37.5.4 HSADC Sequence Samples Number Register (HW_HSADC_SEQUENCE_SAMPLES_NUM) The HSADC Sequence Samples Number Register specifies the number of samples in one sequence. HW_HSADC_SEQUENCE_SAMPLES_NUM: 0x030 HW_HSADC_SEQUENCE_SAMPLES_NUM_SET: 0x034 HW_HSADC_SEQUENCE_SAMPLES_NUM_CLR: 0x038 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2652 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) HW_HSADC_SEQUENCE_SAMPLES_NUM_TOG: 0x03C This register specifies the number of samples in one sequence. EXAMPLE HW_HSADC_SEQUENCE_SAMPLES_NUM_WR(0x0000001f); Address: 8000_2000h base + 30h offset = 8000_2030h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQUENCE_SAMPLES_NUM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_HSADC_SEQUENCE_SAMPLES_NUM field descriptions Field Description SEQUENCE_ Number of samples in one sequence. 0 means infinite samples. Note that when set to 0,the ADC can only SAMPLES_NUM be stopped by software disabling.Take effect when hsadc_run is asserted. 37.5.5 HSADC Sequence Number Register (HW_HSADC_SEQUENCE_NUM) The HSADC Sequence Number Register specifies the number of sequence needed to be converted. HW_HSADC_SEQUENCE_NUM: 0x040 HW_HSADC_SEQUENCE_NUM_SET: 0x044 HW_HSADC_SEQUENCE_NUM_CLR: 0x048 HW_HSADC_SEQUENCE_NUM_TOG: 0x04C This register specifies the number of sequences. EXAMPLE HW_HSADC_SEQUENCE_NUM_WR(0x0000001f); Address: 8000_2000h base + 40h offset = 8000_2040h Bit R W 31 Reset 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQUENCE_NUM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2653 Programmable Registers HW_HSADC_SEQUENCE_NUM field descriptions Field Description SEQUENCE_ NUM Number of sequence. 0 means infinite sequences. Note that when set to 0,the ADC can only be stopped by software disabling.Take effect when hsadc_run is asserted. 37.5.6 HSADC FIFO Data Register (HW_HSADC_FIFO_DATA) The HSADC FIFO Data Register is for the DMA or host CPU to read data from the FIFO by APB bus. This register contains the programming paramters for multi-chip attachment mode, clock divider value, active high, low values and period for channel 1. EXAMPLE HW_HSADC_FIFO_DATA_RD(); Address: 8000_2000h base + 50h offset = 8000_2050h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_DATA R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_HSADC_FIFO_DATA field descriptions Field FIFO_DATA Description The FIFO data interface for DMA or host CPU to read data from the FIFO internal HSADC module. 37.5.7 HSADC Debug Information 0 Register (HW_HSADC_DBG_INFO0) The HSADC Debug Information Register provides some useful information for debugging. This register contains the active time and inactive time programming parameters for Channel 2. EXAMPLE HW_HSADC_DBG_INFO0_RD(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2654 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) Address: 8000_2000h base + 60h offset = 8000_2060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 R W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSRVD1 R HSADC_FSM_ STATE DMA_FSM_STATE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_HSADC_DBG_INFO0 field descriptions Field Description 31-6 RSRVD1 Reserved. 5-3 DMA_FSM_ STATE The current state of dma slave state machine. HSADC_FSM_ STATE The current state of hsadc state machine. 37.5.8 HSADC Debug Information 1 Register (HW_HSADC_DBG_INFO1) The HSADC Debug Information Register provides some useful information for debugging. This register contains the number of samples which are already finished in the current sequence. EXAMPLE HW_HSADC_DBG_INFO1_RD(); Address: 8000_2000h base + 70h offset = 8000_2070h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQUENCE_SAMPLE_CNT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2655 Programmable Registers HW_HSADC_DBG_INFO1 field descriptions Field Description SEQUENCE_ SAMPLE_CNT The number of samples which are already finished in the current sequence. 37.5.9 HSADC Debug Information 2 Register (HW_HSADC_DBG_INFO2) The HSADC Debug Information Register provides some useful information for debugging. This register contains the number of sequences which are already finished. EXAMPLE HW_HSADC_DBG_INFO2_RD(); Address: 8000_2000h base + 80h offset = 8000_2080h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEQUENCE_CNT R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_HSADC_DBG_INFO2 field descriptions Field SEQUENCE_ CNT Description The number of sequences which are already finished. 37.5.10 HSADC Version Register (HW_HSADC_VERSION) This register indicates the version of the block for debug purposes. This register indicates the RTL version in use. EXAMPLE if (HW_HSADC_VERSION.B.MAJOR != 1) Error(); i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2656 Freescale Semiconductor, Inc. Chapter 37 High-Speed ADC (HSADC) Address: 8000_2000h base + B0h offset = 8000_20B0h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 HW_HSADC_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2657 Programmable Registers i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2658 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface 38.1 LRADC Overview This chapter describes the low-resolution analog-to-digital converters (LRADC) and touch-screen interface. It includes sections on scheduling conversions, delay channels and programmable registers. The sixteen-channel low-resolution analog-to-digital converter block is used for voltage measurement. Figure 38-1 shows a block diagram of the LRADC. Eight virtual channels can be used at one time. Each of the eight virtual channels can be mapped to any of the 16 physical channels using HW_LRADC_CTRL4. Six physical channels are available for general use. Table 38-1. Channel Assignments Channel Number Assignment LRADC 0 - 6 measure the voltage on the seven application-dependent LRADC pins. The auxiliary channels can be used for a variety of uses, including a resistor-divider-based wired remote control, external temperature sensing, touch-screen, button and so on. 0-6 LRADC 2 - 6 can be used for 4/5-wire touch-screen control. LRADC 6 can be used for the wiper of 5-wire touch-screen controller and external temperature sensing, but they cannot be enabled at the same time in hardware configuration. LRADC 5 can be used for Yof 4-wire and LR of 5-wire; LRADC 4 can be used for X- of 4-wire and UR of 5-wire; LRADC 3 can be used for Y+ of 4-wire and LL of 5-wire; LRADC 2 can be used for X+ and UR of 5-wire; For pull-up or pull-down switch control on LRADC2~5 pins, please refer to HW_LRADC_CTRL0 register. LRADC 0 can be used for button and external temperature sensing, they can not be enabled at same time in hardware configuration. LRADC 1 can be used Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2659 LRADC Overview Table 38-1. Channel Assignments (continued) Channel Number Assignment for button as well as LRADC 0. There are the hardware button press detect circuit for LRADC 0 and 1. 7 Dedicated to measuring the voltage on the BATT pin and can be used to sense the amount of battery life remaining. 8, 9 Dedicated to measuring the internal die temperature. HW_LRADC_CTRL2_TEMPSENSE_PWD must be cleared for these inputs to function. See Internal Die Temperature Sensing. 10 Dedicated to measuring the voltage on the VDDIO rail. Also used to calibrate the voltage levels measured on the auxiliary channels when those inputs are resistor-divided from the VDDIO rail. 11 Reserved input for analog testing. 12 Dedicated to measuring the voltage on the VDDA. 13 Dedicated to measuring the voltage on the VDDD. 14 Dedicated to measuring the bandgap reference voltage and can be used to calibrate out a portion of the LRADC measurement error (comparator offset, buffer amp offset, and digital-to-analog converter (DAC) offset). In most cases, the bandgap reference error (specified to 1%) dominates the total LRADC error, and this calibration is not helpful. But if the bandgap reference is calibrated using the fuses, then it is possible that LRADC accuracy is limited by these other sources and that using the VBG input for calibration of the LRADC can further improve accuracy. 15 Dedicated to measure the voltage on the VDD5V pin and can be used to detect possible issues with 5 V rail dropping. The LRADC has 12 bit of resolution and an absolute accuracy of 1.3% limited primarily by the accuracy of the bandgap voltage reference. If the bandgap voltage reference is calibrated with the fuses, the LRADC absolute accuracy might be improved to better than 0.5%. All channels sample on the same divided clock rate from the 24.0 MHz crystal clock. The LRADC controller includes an integrated 4-wire/5-wire touch-screen controller with drive voltage generation for touch-screen coordinate measurement, as well as a touch-detection interrupt circuit. The keypad (button) detect and buttondetection interrupt circuit are implemented in the controller. It contains four delay-control channels that can be used to automatically time and schedule control events within the LRADC. The controller also implements a threshold-detection function that can signal an interrupt when a programmed value is crossed on a virtual LRADC channel. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2660 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface ARM Core SRAM AHB AHB Slave AHB Master Shared DMA APBX APBX Master AHB-to-APBX Bridge LRADC Programmable Registers APBX Clock Domain State Machines and Logic LRADC6-0 Pins XTAL/4 Clock Domain State Machines and Logic 16-Channel LRADC Touch -Screen Controller Temp -Sensor Controller LRADC Figure 38-1. Low-Resolution ADC and Touch-Screen Interface Block Diagram 38.2 Operation All channels of the LRADC share a common successive approximation style analog-todigital converter through a common analog mux front end (see Figure 38-2). * The BATT pin has a built-in 4:1 voltage divider on its analog multiplexer input that is activated only in Li-Ion battery mode. * The Channel 15 5V input also has a built-in 4:1 divider on its input. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2661 Operation * The Channel 10 VDDIO input and the Channel 12 VDDA input have a built-in 2:1 divider on their inputs. The maximum analog input voltage into the LRADC is 1.85 V. * For input channels (other than BATT, 5V, or VDDIO) with signals larger than 1.85 V, the divide-by-two option should be set (HW_LRADC_CTRL2_DIVIDE_BY_TWO). With the DIVIDE_BY_TWO option set, the maximum input voltage is VDDIO - 50mv. The touch-screen driver works for typical touch-screen impedances of 200-900 ohm and for high impedance touch-panels with impedances in the 50-Kohm range. The LRADC channels 0 and 6 have optional current source outputs to allow these channels to be used with an external themistor (or an external diode) for temperature sensing. The controls for these current sources are in HW_LRADC_CTRL2. The current source values can be changed to allow significant temperature sensing range using a thermistor or to use a diode for temperature sensing. The currents are derived using the on-chip 1% accurate bandgap voltage reference and an optionally tuned on-chip poly resistor. The accuracy of the current source is limited by the on-chip resistor, which should be 5% accurate and optionally tuned for higher accuracy (with efuses). Most thermistors are no more than 5% accurate, so this level of current source accuracy is acceptable for most applications. For temperature sensing with higher accuracy, customers can use a 1% resistor divider from VDDIO with the thermistor. In this case, the thermistor will be the dominant source of error. Note The pad ESD protection limits the voltage on the LRADC0LRADC6 inputs to VDDIO. The BATT and 5V inputs to the LRADC have built-in dividers to handle the higher voltages. 38.2.1 External Temperature Sensing with a Diode Using a diode instead of a thermistor for external temperature sensing can be cheaper and provide greater temperature range for a given accuracy level. An inexpensive diode like a 1N4148 is connected between ground and either LRADC 0 or 6. Two voltage measurements are taken--first with the HW_LRADC_CTRL2_TEMP_ISRC current source set at 300 A, then another voltage measurement with the current source set at 20 A. The temperature will be roughly: degrees Kelvin = (Vmax - Vmin) / 0.409 mV or, from the LRADC conversion (LSB=0.45mV): i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2662 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface degrees Kelvin = (Codemax - Codemin) * 1.104 Freescale recommends taking 5-10 samples for the min and max and then averaging them to get a good reading. The temperature reading error will likely be dominated by part-to-part matching of the diodes. Some manufacturers' diodes show substantially less variation than others. Freescale has shown three-sigma accuracy of +/-7.5C using Fairchild MMBD914 (from multiple batches of diodes). If better accuracy is required, Freescale recommends using a thermistor for external temperature sensing. The thermistor will be more accurate, but over a smaller temperature range than the diode method. Any routing impedance to the diode will cause a shift in the temperature reading. This can be measured and corrected in software for each design. Two ohms of routing impedance would cause (2 * (300A - 20A) error of 0.56 mV or 1.25 degrees C error. 38.2.2 Internal Die Temperature Sensing The i.MX28 has a new internal die temperature sensor that uses two of the sixteen physical LRADC channels. To use the internal die temperature sensor, HW_LRADC_CTRL2_TEMPSENSE_PWD should be cleared. (This bit can be left cleared after power up. There is no need to toggle it on and off.) Two of the eight virtual LRADC channels need to be mapped to the temperature sensing channels 8 and 9 using HW_LRADC_CTRL4. Then, these virtual LRADC channels should BOTH be converted using the LRADC conversion scheduler described below. The temperature in degrees Kelvin will be equal to: (Channel9 - Channel8) * Gain_correction/4 The Gain_correction corrects a mean gain error in the temperature conversion and should be 1.012. After this correction factor, the three-sigma error of the temperature sensor should be within 1.5% in degrees Kelvin. Additionally, the temperature sampling has a three-sigma sample-to-sample variation of 2 degrees Kelvin. If desired, this error can be removed by oversampling and averaging the temperature result. Prior to starting a battery charge cycle, the internal die temperature sensing could be used for an approximate ambient temperature. During high-current battery charging, the temperature sensor can be used as extra protection to avoid excessive die temperatures (to reduce the charging current). i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2663 Operation 38.2.3 Scheduling Conversions The APBX clock domain logic schedules conversions on a per-channel basis and handles interrupt processing back to the CPU. Each of the eight virtual channels has its own interrupt request enable bit and its own interrupt request status bit. A schedule request bit, HW_LRADC_CTRL0_SCHEDULE, exists for each virtual channel. Setting this bit causes the LRADC to schedule a conversion for that virtual channel. Each virtual channel schedule bit is sequentially checked and, if scheduled, causes a conversion. The schedule bit is cleared upon completion of a successive approximation conversion, and its corresponding interrupt request status bit is set. Therefore, software controls how often a conversion is requested. As each scheduled channel is converted, its interrupt status bit is set and its schedule bit is reset. There is a mechanism to continuously reschedule a conversion for a particular virtual channel. With set/clear/toggle addressing modes, independent threads can request conversions without needing any information from unrelated threads using other channels. Setting a schedule bit can be performed in an atomic way. Setting a group of four channel-schedule bits can also be performed atomically. The LRADC scheduler is round-robin. It snapshots all schedule bits at once, and then processes them in sequence until all are converted. It then monitors the schedule bits. If any schedule bits are set, it snapshots them and starts a new conversion operation for all scheduled channels. Thus, one can set the schedule bits for four channels on the same clock edge. The channel with the largest channel number is converted last and has its interrupt status bit set last. If that channel is the only one of the four with an interrupt enable bit set, then it interrupts the ARM after all four channels have been converted, effectively ganging four channels together. 38.2.4 Delay Channels To minimize the interrupt load on the ARM processor, four delay channels are provided. Each has an 11-bit counter that increments at 2 KHz. A delay channel can be kicked off either by an ARM store instruction or at the completion of a delay channel time-out. At time-out, each channel has the option of kicking off any combination of LRADC conversions, as well as any combination of delay channels. Note The DELAY fields in HW_LRADC_DELAY0, HW_LRADC_DELAY1, HW_LRADC_DELAY2, and HW_LRADC_DELAY3 must be non-zero; otherwise, the i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2664 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface LRADC will not trigger the delay group. The ACCUMULATE bit in the appropriate channel register HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0; otherwise, the IRQs will not fire. Consider the case of a touch-screen that requires 4x oversampling of its coordinate values. Further, suppose you wish to receive an oversampled X or Y coordinate approximately every 5 ms and that the oversampling should be spaced at 1-ms intervals. * In the touch-screen, first select either X or Y drive, then set up the appropriate LRADC. * In setting up the LRADC, clear the accumulator associated with it by setting the ACCUMULATE bit and set the NUM_SAMPLES field to 3 (4 samples before interrupt request). * Next, set up two delay channels. * Delay Channel 1 is set to delay 1 ms (DELAY = 1, two ticks) and then kick the schedule bit for LRADC 4. Its LOOP_COUNT bit field is also set to 3, so that four kicks of LRADC 4 occur, each spaced by 1 ms. * Delay Channel 0 is set to delay 1 ms with LOOP_COUNT = 0, that is, one time. Its TRIGGER_DELAYS field is set to trigger Delay Channel 1 when it times out. The ISR routine kicks off Delay Channel 0 immediately before it does its return from interrupt. Another interrupt (LRADC4_IRQ) is asserted once the entire 4x oversample data capture is complete. A sample timeline for such a sequence is shown in Figure 38-3. Note If a delay group schedules channels to be sampled and a manual write to the schedule field in CTRL0 occurs while the block is discarding samples, the LRADC will switch to the new schedule and will not sample the channels that were previously scheduled. The time window for this to happen is very small and lasts only while the LRADC is discarding samples. 38.3 Channel Threshold Detection There are two identical threshold detection units implemented in the LRADC. They are configured through the registers HW_LRADC_THRESHOLD0 and HW_LRADC_THRESHOLD1. This functionality compares the sampled 18-bit value i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2665 Behavior During Reset from a LRADC channel against a programmed threshold value. It can be programmed to do this comparison in two ways. First, it will detect when the sampled channel value crosses from above the threshold value down to equal or less than that value. Conversely, it can also be set up to detect when the sampled channel value changes from below to equal to or above the threshold value. When the programmed crossing is detected, the HW_LRADC_CTRL1_THRESHOLDx_DETECT_IRQ interrupt register bits will assert. These bits can be interrupt sources back to the CPU if enabled through the HW_LRADC_CTRL1_THRESHOLDx_DETECT_IRQ_EN bits. The interrupt bits must be cleared before another threshold crossing can be detected. Any one of the eight virtual channels can be mapped to either or both of the threshold detection units. Note that the threshold event can occur on the very first channel conversion after the threshold unit is enable. For example, consider the case where a threshold unit was programmed for DETECT_HIGH and enabled. If the connected channel was then converted and the value was equal or greater than the threshold value this would satisfy the threshold requirement and the event would be logged by setting the IRQ bit. However, after this first conversion, a threshold event will only be tripped again on subsequent conversions if the value drops below the threshold and then crosses it again. In other words, if the channel value remains above the threshold on multiple sequential conversions, the threshold event will be logged only once (after the first conversion in the sequence that tripped the threshold). Either threshold unit can be used to disable the battery charger when a threshold event occurs. This functionality is enabled by setting the HW_LRADC_THRESHOLDx_BATTCHRG_DISABLE bit. When enabled, and the threshold is tripped, the HW_POWER_CHARGE0_ PWD_BATTCHRG bit will set. This is an event that is triggered once when the conditions are met (PWD_BATTCHRG is not held high). At any time thereafter, the PWD_BATTCHRG bit can be manipulated and reprogrammed by software as normal. The LRADC will only set the bit again when the threshold event is triggered once more. 38.4 Behavior During Reset A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See Correct Way to Soft Reset a Block for additional information on using the SFTRST and CLKGATE bit fields. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2666 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface LRADC0(button0) / ext_temp CH0 LRADC1(button1) SW0 1.85V 200K LRADC2 xpul CH1 VDDIO SW1 CH2 LRADC2 1.85V LRADC3 ypll LRADC6 SW2 CH3 SW3 1.85V LRADC0 SW4 LRADC5 ynlr SW6 VDDIO button1 _ detect CH5 MUX CH6 /2 SAR ADC CH7 1/4*BATT Freescale Internal Temperature Sensing CH8 CH9 1/2*VDDIO 1/2*VDDA VDDD Bandgap Reference 1/4*VDD5V button0 _ detect Button Detection Logic Analog LRADC6 / ext_temp 200K APBX CLK State Machine clkdiv (1:4.1:6,1:8,1:12) CH10 MUX Vth_Pthin Vth_Nthin Vth_Nthick Vth_Pthick LRADC1 CH4 SW5 MUX LRADC4 xnur SW7 touch_detect TouchScreen Detection Logic CH11 24.0 MHz apbxck = xtal_clk/n CH12 CH13 CH14 CH15 Figure 38-2. Low-Resolution ADC Successive Approximation Unit i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2667 Behavior During Reset Below Table shows the register configure setting and switch status for different touch screen usage: Table 38-2. The register configure setting and switch status for different touch screen usage 4-wire touch detect 4-wire X-axis 4-wire Y-axis 5-wire touch detect 5-wire horizontal 5-wire vertical measure measure 0 0 0 1 1 1 TOUCH_DETEC 1 T_ENABLE 0 0 1 0 0 YNLRSW 0 0 1 0 1 1 YPLLSW<1:0> 00 00 01 00 01 10 XNURSW<1:0> 00 10 00 00 10 01 XPULSW 0 1 0 0 1 1 SW0 Status ON OFF OFF OFF OFF OFF SW1 Status OFF ON OFF OFF ON ON SW2 Status OFF OFF ON OFF ON OFF SW3 Status OFF OFF OFF OFF OFF ON SW4 Status OFF OFF OFF OFF OFF ON SW5 Status OFF ON OFF OFF ON OFF SW6 Status ON OFF ON ON ON ON SW7 Status OFF OFF OFF ON OFF OFF TOUCH_SCRE EN_TYPE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2668 Freescale Semiconductor, Inc. LRADC4IRQ DelayChannel_1 Kicks LRADC4_X+ DelayChannel_1 Kicks LRADC4_X+ DelayChannel_1 Kicks LRADC4_X+ DelayChannel_1 Kicks LRADC4_X+ DelayChannel_0 Kicks DelayChannel1 Kick DelayChannel_0 TouchScreenIRQ Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface Delay Channel 1 oversample intervals: 1. Times out. 2. Kicks LRADC4 (X+ sample). 3. Repeats 3 more times. Delay Channel 0 (touch-screen settling time): 1. Times out. 2. Kicks Delay Channel 1. Touch-screen ISR: 1. Sets Y+,Y- drive and clears LRADC4 ACC. 2. Set Delay Channel 1 for LRADC4. 3. Kicks Delay Channel 0. 4. Return from interrupt. Final Conversion sets IRQ. Figure 38-3. Using Delay Channels to Oversample a Touch-Screen 38.5 Programmable Registers LRADC Hardware Register Format Summary i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2669 Programmable Registers HW_LRADC memory map Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 8005_0000 LRADC Control Register 0 (HW_LRADC_CTRL0) 32 R/W C000_0000h 38.5.1/2671 8005_0010 LRADC Control Register 1 (HW_LRADC_CTRL1) 32 R/W 0000_0000h 38.5.2/2673 8005_0020 LRADC Control Register 2 (HW_LRADC_CTRL2) 32 R/W 0000_8000h 38.5.3/2677 8005_0030 LRADC Control Register 3 (HW_LRADC_CTRL3) 32 R/W 0000_0000h 38.5.4/2680 8005_0040 LRADC Status Register (HW_LRADC_STATUS) 32 R 8005_0050 LRADC 0 Result Register (HW_LRADC_CH0) 32 R/W 0000_0000h 38.5.6/2685 8005_0060 LRADC 1 Result Register (HW_LRADC_CH1) 32 R/W 0000_0000h 38.5.7/2687 8005_0070 LRADC 2 Result Register (HW_LRADC_CH2) 32 R/W 0000_0000h 38.5.8/2689 8005_0080 LRADC 3 Result Register (HW_LRADC_CH3) 32 R/W 0000_0000h 38.5.9/2691 8005_0090 LRADC 4 Result Register (HW_LRADC_CH4) 32 R/W 0000_0000h 38.5.10/ 2693 8005_00A0 LRADC 5 Result Register (HW_LRADC_CH5) 32 R/W 0000_0000h 38.5.11/ 2695 8005_00B0 LRADC 6 Result Register (HW_LRADC_CH6) 32 R/W 0000_0000h 38.5.12/ 2697 8005_00C0 LRADC 7 (BATT) Result Register (HW_LRADC_CH7) 32 R/W 0000_0000h 38.5.13/ 2699 8005_00D0 LRADC Scheduling Delay 0 (HW_LRADC_DELAY0) 32 R/W 0000_0000h 38.5.14/ 2701 8005_00E0 LRADC Scheduling Delay 1 (HW_LRADC_DELAY1) 32 R/W 0000_0000h 38.5.15/ 2702 8005_00F0 LRADC Scheduling Delay 2 (HW_LRADC_DELAY2) 32 R/W 0000_0000h 38.5.16/ 2704 8005_0100 LRADC Scheduling Delay 3 (HW_LRADC_DELAY3) 32 R/W 0000_0000h 38.5.17/ 2705 8005_0110 LRADC Debug Register 0 (HW_LRADC_DEBUG0) 32 R 4321_0000h 38.5.18/ 2707 8005_0120 LRADC Debug Register 1 (HW_LRADC_DEBUG1) 32 R/W 0000_0000h 38.5.19/ 2708 8005_0130 LRADC Battery Conversion Register (HW_LRADC_CONVERSION) 32 R/W 0000_0080h 38.5.20/ 2709 8005_0140 LRADC Control Register 4 (HW_LRADC_CTRL4) 32 R/W 7654_3210h 38.5.21/ 2711 8005_0150 LRADC Theshold0 Register (HW_LRADC_THRESHOLD0) 32 R/W 0000_0000h 38.5.22/ 2715 8005_0160 LRADC Theshold1 Register (HW_LRADC_THRESHOLD1) 32 R/W 0000_0000h 38.5.23/ 2716 8005_0170 LRADC Version Register (HW_LRADC_VERSION) 32 R 0103_0000h 38.5.24/ 2718 1FFF_0000h 38.5.5/2682 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2670 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface 38.5.1 LRADC Control Register 0 (HW_LRADC_CTRL0) The LRADC Control Register 0 provides overall control of the eight low resolution analog to digital converters. HW_LRADC_CTRL0: 0x000 HW_LRADC_CTRL0_SET: 0x004 HW_LRADC_CTRL0_CLR: 0x008 HW_LRADC_CTRL0_TOG: 0x00C The LRADC control register provides control over the shared eight channel LRADC converter. It allows software to independently schedule conversion cycles on any number of any size subsets of the eight channels. In addition it allows software to manage the interrupt reporting for the channel conversion sets. EXAMPLE BW_LRADC_CTRL0_YPLUS_ENABLE(BV_LRADC_CTRL0_YPLUS_ENABLE__ON); RSRVD2 SFTRST CLKGATE R 1 1 W Reset 0 0 0 26 25 24 23 22 21 0 0 0 0 0 0 17 16 YPLLSW XNURSW XPULSW 27 YNLRSW 28 TOUCH_SCREEN_TYPE 29 TOUCH_DETECT_ENABLE 30 BUTTON0_DETECT_ENABLE 31 BUTTON1_DETECT_ENABLE Bit ONCHIP_GROUNDREF Address: 8005_0000h base + 0h offset = 8005_0000h 20 19 0 0 0 18 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2671 Programmable Registers 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSRVD1 R SCHEDULE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LRADC_CTRL0 field descriptions Field 31 SFTRST 30 CLKGATE 29-27 RSRVD2 26 ONCHIP_ GROUNDREF Description When set to one, this bit causes a reset to the entire LRADC block. In addition, it turns off the converter clock and powers down the analog portion of the LRADC. Set this bit to zero for normal operation. This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block. Reserved Set this bit to one to use the on-chip ground as reference for conversions. 0x0 0x1 OFF -- Turn it off. ON -- Turn it on. 25 BUTTON1_ DETECT_ ENABLE Set this bit to one to enable button1 detector. 24 BUTTON0_ DETECT_ ENABLE Set this bit to one to enable button0 detector. 23 TOUCH_ DETECT_ ENABLE 0x0 0x1 0x0 0x1 OFF -- Turn it off. ON -- Turn it on. OFF -- Turn it off. ON -- Turn it on. Set this bit to one to enable touch panel touch detector. 0x0 0x1 OFF -- Turn it off. ON -- Turn it on. 22 Touch Screen Type (4/5 wires) Select control. TOUCH_ 0x0: 4-wire SCREEN_TYPE 0x1: 5-wire 21 YNLRSW YNLR Switch Control, to enable pull down on the LRADC5 pin. YNLRSW bit controls the on/off for ynnsw 0x0: YNLR OFF (ynnsw off) 0x1: YNLR LOW (ynnsw on) Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2672 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_CTRL0 field descriptions (continued) Field 20-19 YPLLSW Description YPLL Switch Control, to enable pull up or pull down on the LRADC3 pin. YPLLSW[1] controls the on/off for ypnsw YPLLSW[0] controls the on/off for yppsw 0x0: YPLL OFF (ypnsw off, yppsw off) 0x1: YPLL HIGH (ypnsw off, yppsw on) 0x2: YPLL LOW (ypnsw on, yppsw off) 0x3: Reserved 18-17 XNURSW XNUR Switch Control, to enable pull down or pull up on the LRADC4 pin. XNUR[1] controls the on/off for xnnsw XNUR[0] controls the on/off for xnpsw 0x0: XNUR OFF (xnnsw off, xnpsw off) 0x1: XNUR HIGH (xnnsw off, xnpsw on) 0x2: XNUR LOW (xnnsw on, xnpsw off) 0x3: Reserved 16 XPULSW XPUL Switch Control, to enable pull up on the LRADC2 pin. XPULSW bit controls the on/off for xppsw 0x0: XPUL OFF (xppsw off) 0x1: XPUL HIGH (xppsw on) 15-8 RSRVD1 SCHEDULE Reserved Setting a bit to one schedules the corresponding LRADC channel to be converted. When the conversion of a scheduled channel is completed the corresponding schedule bit is reset by the hardware and the corresponding interrupt request is set to one. Thus any thread can request a conversion asynchronously from any other thread. 38.5.2 LRADC Control Register 1 (HW_LRADC_CTRL1) The LRADC Control Register 1 provides overall control of the eight low resolution analog to digital converters. HW_LRADC_CTRL1: 0x010 HW_LRADC_CTRL1_SET: 0x014 HW_LRADC_CTRL1_CLR: 0x018 HW_LRADC_CTRL1_TOG: 0x01C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2673 Programmable Registers The LRADC control register 1 provides control over the shared eight channel LRADC converter. It allows software to independently schedule conversion cycles on any number of any size subsets of the eight channels. In addition it allows software to manage the interrupt reporting for the channel conversion sets. EXAMPLE if(HW_LRADC_CTRL1.TOUCH_DETECT_IRQ == BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING){ // Then handle the interrupt. HW_LRADC_CTRL1.TOUCH_DETECT_IRQ_EN = BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE; } Address: 8005_0000h base + 10h offset = 8005_0010h LRADC6_IRQ_EN LRADC5_IRQ_EN LRADC4_IRQ_EN LRADC3_IRQ_EN LRADC2_IRQ_EN LRADC1_IRQ_EN LRADC0_IRQ_EN 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LRADC5_IRQ LRADC4_IRQ LRADC3_IRQ LRADC2_IRQ LRADC1_IRQ LRADC0_IRQ 16 LRADC6_IRQ 17 LRADC7_IRQ_EN 18 LRADC7_IRQ 19 TOUCH_DETECT_IRQ_EN 20 TOUCH_DETECT_IRQ 21 THRESHOLD0_DETECT_IRQ_EN 22 THRESHOLD0_DETECT_IRQ 23 THRESHOLD1_DETECT_IRQ_EN 24 THRESHOLD1_DETECT_IRQ 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSRVD1 R W Reset 26 0 W Bit 27 0 RSRVD2 R Reset 28 BUTTON0_DETECT_IRQ_EN 29 BUTTON0_DETECT_IRQ 30 BUTTON1_DETECT_IRQ_EN 31 BUTTON1_DETECT_IRQ Bit 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2674 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_CTRL1 field descriptions Field 31-29 RSRVD2 Description Reserved 28 BUTTON1_ DETECT_IRQ_ EN Set to one to enable an interrupt for the button1 detect logic. 27 BUTTON0_ DETECT_IRQ_ EN Set to one to enable an interrupt for the button0 detect logic. 0x0 0x1 0x0 0x1 DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. 26 Set to one to enable an interrupt for the theshold0 detect logic. THRESHOLD1_ DETECT_IRQ_ 0x0 DISABLE -- Disable Interrupt request. EN 0x1 ENABLE -- Enable Interrupt request. 25 Set to one to enable an interrupt for the theshold0 detect logic. THRESHOLD0_ DETECT_IRQ_ 0x0 DISABLE -- Disable Interrupt request. EN 0x1 ENABLE -- Enable Interrupt request. 24 TOUCH_ DETECT_IRQ_ EN Set to one to enable an interrupt for the touch detector comparator. 23 LRADC7_IRQ_ EN Set to one to enable an interrupt for channel 7 (BATT) conversions. 22 LRADC6_IRQ_ EN Set to one to enable an interrupt for channel 6 conversions. 21 LRADC5_IRQ_ EN Set to one to enable an interrupt for channel 5 conversions. 20 LRADC4_IRQ_ EN Set to one to enable an interrupt for channel 4 conversions. 19 LRADC3_IRQ_ EN Set to one to enable an interrupt for channel 3 conversions. 18 LRADC2_IRQ_ EN Set to one to enable an interrupt for channel 2 conversions. 17 LRADC1_IRQ_ EN Set to one to enable an interrupt for channel 1 conversions. 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2675 Programmable Registers HW_LRADC_CTRL1 field descriptions (continued) Field Description 0x0 0x1 16 LRADC0_IRQ_ EN 15-13 RSRVD1 12 BUTTON1_ DETECT_IRQ Set to one to enable an interrupt for channel 0 conversions. 0x0 0x1 DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. Reserved This bit is set to one upon detection of the button1 condition in button matrix and attached to LRADC1. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 11 BUTTON0_ DETECT_IRQ DISABLE -- Disable Interrupt request. ENABLE -- Enable Interrupt request. CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. This bit is set to one upon detection of the threshold1 condition in button matrix and attached to LRADC0. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. 10 This bit is set to one upon detection of the threshold1 condition. It is ANDed with its corresponding THRESHOLD1_ interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until DETECT_IRQ cleared by software. 0x0 0x1 CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. 9 This bit is set to one upon detection of the threshold0 condition. It is ANDed with its corresponding THRESHOLD0_ interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until DETECT_IRQ cleared by software. 0x0 0x1 8 TOUCH_ DETECT_IRQ This bit is set to one upon detection of a touch condition in the touch panel attached to LRADC2-LRADC6. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 7 LRADC7_IRQ CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. This bit is set to one upon completion of a scheduled conversion for channel 7(BATT). It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 6 LRADC6_IRQ CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. This bit is set to one upon completion of a scheduled conversion for channel 6. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2676 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_CTRL1 field descriptions (continued) Field 5 LRADC5_IRQ Description This bit is set to one upon completion of a scheduled conversion for channel 5. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 4 LRADC4_IRQ This bit is set to one upon completion of a scheduled conversion for channel 4. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 3 LRADC3_IRQ CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. This bit is set to one upon completion of a scheduled conversion for channel 1. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 0 LRADC0_IRQ CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. This bit is set to one upon completion of a scheduled conversion for channel 2. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 1 LRADC1_IRQ CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. This bit is set to one upon completion of a scheduled conversion for channel 3. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 2 LRADC2_IRQ CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. This bit is set to one upon completion of a scheduled conversion for channel 0. It is ANDed with its corresponding interrupt enable bit to request an interrrupt. Once set by the conversion hardware, this bit remains set until cleared by software. 0x0 0x1 CLEAR -- Interrupt request cleared. PENDING -- Interrupt request pending. 38.5.3 LRADC Control Register 2 (HW_LRADC_CTRL2) The LRADC Control Register 2 provides overall control of the eight low resolution analog to digital converters. HW_LRADC_CTRL2: 0x020 HW_LRADC_CTRL2_SET: 0x024 HW_LRADC_CTRL2_CLR: 0x028 HW_LRADC_CTRL2_TOG: 0x02C i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2677 Programmable Registers The LRADC control register 2 provides control over the shared eight channel LRADC converter. It allows software to independently schedule conversion cycles on any number of any size subsets of the eight channels. In addition it allows software to manage the interrupt reporting for the channel conversion sets. EXAMPLE BW_LRADC_CTRL2_TEMP_SENSOR_IENABLE1(BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE); Address: 8005_0000h base + 20h offset = 8005_0020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD3 R DIVIDE_BY_TWO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEMP_SENSOR_IENABLE0 Bit 0 0 0 W Reset TEMPSENSE_PWD R 1 VTHSENSE 0 0 DISABLE_MUXAMP_BYPASS Reset TEMP_SENSOR_IENABLE1 W 0 RSRVD2 0 0 TEMP_ISRC1 0 0 0 TEMP_ISRC0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2678 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_CTRL2 field descriptions Field Description 31-24 DIVIDE_BY_ TWO Each bit of this eight bit field corresponds to a channel of an LRADC. Setting the bit to one caused the A/D converter to use its analog divide by two circuit for the conversion of the corresponding channel. 23-16 RSRVD3 15 TEMPSENSE_ PWD 14-13 VTHSENSE Reserved Power down the tempsense block. 0x0 0x1 ENABLE -- When this is low the tempsense gain block muxes to LRADC channel 8 and 9. DISABLE -- . Vth Measurement Control (Channel11) 0x0:pmos_tn (thin oxide pmos) 0x1:nmos_tn (thin oxide nmos) 0x2:nmos_tk (thick oxide nmos) 0x3:pmos_tk (thick oxide pmos) 12 DISABLE_ MUXAMP_ BYPASS 11-10 RSRVD2 When set to zero (default) the mux amp is bypassed when the LRADC input channel is not using the divide-by-two. When set to one the mux amp is never bypassed (old behavior). Reserved 9 TEMP_ SENSOR_ IENABLE1 Set this bit to one to enable the current source onto LRADC6. This bit must be set to 0 when the function of temp sensor not used in application. 8 TEMP_ SENSOR_ IENABLE0 Set this bit to one to enable the current source onto LRADC0. This bit must be set to 0 when the function of temp sensor not used in application. 7-4 TEMP_ISRC1 When the output voltage is lower than 1V the output current is 1uA higher than the decode shown above. This extra current drops to zero as the output voltage raises above 1.5V. 0x0 0x1 0x0 0x1 DISABLE -- Disable Temperature Sensor Current Source. ENABLE -- Enable Temperature Sensor Current Source. DISABLE -- Disable Temperature Sensor Current Source. ENABLE -- Enable Temperature Sensor Current Source. This four bit field encodes the current magnitude to inject into an external temperature sensor attached to LRADC6. 0xF 0xE 0xD 0xC 0xB 0xA 0x9 0x8 0x7 0x6 0x5 0x4 300 -- 300uA. 280 -- 280uA. 260 -- 260uA. 240 -- 240uA. 220 -- 220uA. 200 -- 200uA. 180 -- 180uA. 160 -- 160uA. 140 -- 140uA. 120 -- 120uA. 100 -- 100uA. 80 -- 80uA. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2679 Programmable Registers HW_LRADC_CTRL2 field descriptions (continued) Field Description 0x3 0x2 0x1 0x0 TEMP_ISRC0 60 -- 60uA. 40 -- 40uA. 20 -- 20uA. ZERO -- 0uA. When the output voltage is lower than 1V the output current is 1uA higher than the decode shown above. This extra current drops to zero as the output voltage raises above 1.5V. This four bit field encodes the current magnitude to inject into an external temperature sensor attached to LRADC0. 0xF 0xE 0xD 0xC 0xB 0xA 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 300 -- 300uA. 280 -- 280uA. 260 -- 260uA. 240 -- 240uA. 220 -- 220uA. 200 -- 200uA. 180 -- 180uA. 160 -- 160uA. 140 -- 140uA. 120 -- 120uA. 100 -- 100uA. 80 -- 80uA. 60 -- 60uA. 40 -- 40uA. 20 -- 20uA. ZERO -- 0uA. 38.5.4 LRADC Control Register 3 (HW_LRADC_CTRL3) The LRADC touch panel control register specifies the voltages at which a touch detect interrupt is generated. HW_LRADC_CTRL3: 0x030 HW_LRADC_CTRL3_SET: 0x034 HW_LRADC_CTRL3_CLR: 0x038 HW_LRADC_CTRL3_TOG: 0x03C The LRADC touch detect control and status register controls the voltage at which a touch detection interrupt is generated. This register also contains the interrupt request status bit and enable bit for the touch detection interrupt request to the CPU's IRQ interrupt input. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2680 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface BW_LRADC_CTRL3_HIGH_TIME(BV_LRADC_CTRL3_HIGH_TIME__83NS); BW_LRADC_CTRL3_INVERT_CLOCK(BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL); Address: 8005_0000h base + 30h offset = 8005_0030h 28 27 26 25 24 23 22 DISCARD 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 RSRVD4 RSRVD3 RSRVD4 RSRVD2 RSRVD1 HIGH_TIME CYCLE_TIME R 19 0 W Bit 20 0 RSRVD5 R Reset 21 INVERT_CLOCK 29 DELAY_CLOCK 30 FORCE_ANALOG_PWDN 31 FORCE_ANALOG_PWUP Bit W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HW_LRADC_CTRL3 field descriptions Field Description 31-26 RSRVD5 Reserved 25-24 DISCARD This bit field specifies the number of samples to discard whenever the LRADC analog is first powered up. 0x0= discard first 3 samples before first capture 0x1= discard first sample before first capture 0x2= discard first 2 samples before first capture 0x3= discard first 3 samples before first capture 23 Set this bit to zero for normal operation. Setting it to one forces an analog power up, regardless of where FORCE_ the digital state machine may be. ANALOG_PWUP Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2681 Programmable Registers HW_LRADC_CTRL3 field descriptions (continued) Field Description 0x0 0x1 OFF -- Turn it off. ON -- Turn it on. 22 Set this bit to zero for normal operation. Setting it to one forces an analog power down, regardless of FORCE_ where the digital state machine may be. ANALOG_PWDN 0x0 ON -- Turn it on. 0x1 OFF -- Turn it off. 21-14 RSRVD4 Reserved 13-10 RSRVD3 Reserved 9-8 CYCLE_TIME Changes the LRADC clock frequency. Note: the sample rate is one thirteenth of the frequency selected here. 0x0 0x1 0x2 0x3 7-6 RSRVD2 5-4 HIGH_TIME 6MHZ -- 6MHz clock. 4MHZ -- 4MHz clock. 3MHZ -- 3MHz clock. 2MHZ -- 2MHz clock. Reserved When CYCLE_TIME=00 only 00 and 01 are valid for HIGH_TIME. When CYCLE_TIME=01 only 00,01,and 10 are valid Changes the duty cycle (time high) for the LRADC clock. 0x0 0x1 0x2 0x3 3-2 RSRVD1 42NS -- Duty cycle high time to 41.66ns. 83NS -- Duty cycle high time to 83.33ns. 125NS -- Duty cycle high time to 125ns. 250NS -- Duty cycle high time to 250ns. Reserved 1 Set this bit to one to delay the 24MHz clock used in the LRADC even further away from the predominant DELAY_CLOCK rising edge used within the digital section. The delay inserted is approximately 400pS. 0x0 0x1 NORMAL -- Normal operation, that is no delay. DELAYED -- Delay the clock. 0 Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section. This INVERT_CLOCK moves it away from the predominant digital rising edge. Setting this bit to one causes the A/D converter to run from the negative edge of the divided clock, effectively shifting the conversion point away from the edge used by the DCDC converter. 0x0 0x1 NORMAL -- Run the clock in normal that is not inverted mode. INVERT -- Inver the clock. 38.5.5 LRADC Status Register (HW_LRADC_STATUS) The LRADC status register returns various read-only status bit field values. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2682 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_STATUS: 0x040 HW_LRADC_STATUS_SET: 0x044 HW_LRADC_STATUS_CLR: 0x048 HW_LRADC_STATUS_TOG: 0x04C EXAMPLE if(HW_LRADC_STATUS.TOUCH_DETECT_RAW == BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT){ // Then something is touching the screen. } 27 26 25 24 23 22 21 20 19 18 17 16 CHANNEL7_PRESENT CHANNEL6_PRESENT CHANNEL5_PRESENT CHANNEL4_PRESENT CHANNEL3_PRESENT CHANNEL2_PRESENT CHANNEL1_PRESENT CHANNEL0_PRESENT RSRVD3 R 28 TOUCH_PANEL_PRESENT 29 TEMP0_PRESENT 30 TEMP1_PRESENT 31 BUTTON0_PRESENT Bit BUTTON1_PRESENT Address: 8005_0000h base + 40h offset = 8005_0040h 1 1 1 1 1 1 1 1 1 1 1 1 1 W Reset 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2683 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 RSRVD2 R 2 1 0 TOUCH_DETECT_RAW 14 BUTTON0_DETECT_RAW 15 Bit BUTTON1_DETECT_RAW Programmable Registers 0 0 0 W Reset 0 0 0 0 0 0 0 HW_LRADC_STATUS field descriptions Field 31-29 RSRVD3 Description Reserved 28 BUTTON1_ PRESENT This read-only bit returns a one when the button detect controller 1 is present on the chip. 27 BUTTON0_ PRESENT This read-only bit returns a one when the button detect controller 0 is present on the chip. 26 TEMP1_ PRESENT This read-only bit returns a one when the temperature sensor 1 current source is present on the chip. 25 TEMP0_ PRESENT This read-only bit returns a one when the temperature sensor 0 current source is present on the chip. 24 TOUCH_ PANEL_ PRESENT This read-only bit returns a one when the touch panel controller function is present on the chip. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2684 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_STATUS field descriptions (continued) Field Description 23 CHANNEL7_ PRESENT This read-only bit returns a one when the LRADC channel 7 converter function is present on the chip. 22 CHANNEL6_ PRESENT This read-only bit returns a one when the LRADC channel 6 converter function is present on the chip. 21 CHANNEL5_ PRESENT This read-only bit returns a one when the LRADC channel 5 converter function is present on the chip. 20 CHANNEL4_ PRESENT This read-only bit returns a one when the LRADC channel 4 converter function is present on the chip. 19 CHANNEL3_ PRESENT This read-only bit returns a one when the LRADC channel 3 converter function is present on the chip. 18 CHANNEL2_ PRESENT This read-only bit returns a one when the LRADC channel 2 converter function is present on the chip. 17 CHANNEL1_ PRESENT This read-only bit returns a one when the LRADC channel 1 converter function is present on the chip. 16 CHANNEL0_ PRESENT This read-only bit returns a one when the LRADC channel 0 converter function is present on the chip. 15-3 RSRVD2 Reserved 2 BUTTON1_ DETECT_RAW This read-only bit shows the status of the BUTTON1 Detect Comparator in the analog section. 1 BUTTON0_ DETECT_RAW This read-only bit shows the status of the BUTTON0 Detect Comparator in the analog section. 0 TOUCH_ DETECT_RAW This read-only bit shows the status of the Touch Detect Comparator in the analog section. 0x0 0x1 0x0 0x1 0x0 0x1 OPEN -- No contact, i.e. open connection. HIT -- Someone is clicking the button. OPEN -- No contact, i.e. open connection. HIT -- Someone is clicking some button. OPEN -- No contact, i.e. open connection. HIT -- Someone is touching the panel. 38.5.6 LRADC 0 Result Register (HW_LRADC_CH0) The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel zero. HW_LRADC_CH0: 0x050 HW_LRADC_CH0_SET: 0x054 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2685 Programmable Registers HW_LRADC_CH0_CLR: 0x058 HW_LRADC_CH0_TOG: 0x05C The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE if (HW_LRADC_CHn(0).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(0, (BF_LRADC_CHn_ACCUMULATE(1) BF_LRADC_CHn_NUM_SAMPLES(5) BF_LRADC_CHn_VALUE(0) ) ); | // Enable accumulation mode. | // Set samples to five. // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC0_IRQ != BV_LRADC_CTRL1_LRADC0_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(0).VALUE / 5; Address: 8005_0000h base + 50h offset = 8005_0050h TOGGLE R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 ACCUMULATE 31 RSRVD2 Bit NUM_SAMPLES VALUE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2686 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface 15 Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R VALUE W Reset 0 0 0 0 0 0 0 0 0 HW_LRADC_CH0 field descriptions Field Description 31 TOGGLE This bit toggles at every completed conversion so software can detect a missed or duplicated sample. 30 RSRVD2 Reserved 29 ACCUMULATE Set this bit to one to add successive samples to the 18 bit accumulator. 28-24 This bit field contains the number of conversion cycles to sum together before reporting operation NUM_SAMPLES complete interrupt status. Set this field to zero for a single conversion per interrupt. 23-18 RSRVD1 VALUE Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. 38.5.7 LRADC 1 Result Register (HW_LRADC_CH1) The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel one. HW_LRADC_CH1: 0x060 HW_LRADC_CH1_SET: 0x064 HW_LRADC_CH1_CLR: 0x068 HW_LRADC_CH1_TOG: 0x06C The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2687 Programmable Registers must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE if (HW_LRADC_CHn(1).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(1, (BF_LRADC_CHn_ACCUMULATE(1) BF_LRADC_CHn_NUM_SAMPLES(5) BF_LRADC_CHn_VALUE(0) ) ); | // Enable accumulation mode. | // Set samples to five. // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC1_IRQ != BV_LRADC_CTRL1_LRADC1_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(1).VALUE / 5; Address: 8005_0000h base + 60h offset = 8005_0060h TOGGLE R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 ACCUMULATE 31 RSRVD2 Bit NUM_SAMPLES VALUE W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R VALUE W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2688 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_CH1 field descriptions Field Description 31 TOGGLE This toggles at every completed conversion so software can detect a missed or duplicated sample. 30 RSRVD2 Reserved 29 ACCUMULATE Set this bit to one to add successive samples to the 18 bit accumulator. 28-24 This bit field contains the number of conversion cycles to sum together before reporting operation NUM_SAMPLES complete interrupt status. Set this field to zero for a single conversion per interrupt. 23-18 RSRVD1 VALUE Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. 38.5.8 LRADC 2 Result Register (HW_LRADC_CH2) The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel two. HW_LRADC_CH2: 0x070 HW_LRADC_CH2_SET: 0x074 HW_LRADC_CH2_CLR: 0x078 HW_LRADC_CH2_TOG: 0x07C The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE if (HW_LRADC_CHn(2).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(2, (BF_LRADC_CHn_ACCUMULATE(1) BF_LRADC_CHn_NUM_SAMPLES(5) BF_LRADC_CHn_VALUE(0) ) ); | // Enable accumulation mode. | // Set samples to five. // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2689 Programmable Registers while (HW_LRADC_CTRL1.LRADC2_IRQ != BV_LRADC_CTRL1_LRADC2_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(2).VALUE / 5; Address: 8005_0000h base + 70h offset = 8005_0070h TOGGLE R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 ACCUMULATE 31 RSRVD2 Bit NUM_SAMPLES VALUE W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R VALUE W Reset 0 0 0 0 0 0 0 0 0 HW_LRADC_CH2 field descriptions Field Description 31 TOGGLE This bit toggles at every completed conversion so software can detect a missed or duplicated sample. 30 RSRVD2 Reserved 29 ACCUMULATE Set this bit to one to add successive samples to the 18 bit accumulator. 28-24 This bit field contains the number of conversion cycles to sum together before reporting operation NUM_SAMPLES complete interrupt status. Set this field to zero for a single conversion per interrupt. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2690 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_CH2 field descriptions (continued) Field 23-18 RSRVD1 VALUE Description Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. 38.5.9 LRADC 3 Result Register (HW_LRADC_CH3) The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel three. HW_LRADC_CH3: 0x080 HW_LRADC_CH3_SET: 0x084 HW_LRADC_CH3_CLR: 0x088 HW_LRADC_CH3_TOG: 0x08C The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE if (HW_LRADC_CHn(3).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(3, (BF_LRADC_CHn_ACCUMULATE(1) BF_LRADC_CHn_NUM_SAMPLES(5) BF_LRADC_CHn_VALUE(0) ) ); | // Enable accumulation mode. | // Set samples to five. // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC3_IRQ != BV_LRADC_CTRL1_LRADC3_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(3).VALUE / 5; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2691 Programmable Registers Address: 8005_0000h base + 80h offset = 8005_0080h TOGGLE R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 ACCUMULATE 31 RSRVD2 Bit NUM_SAMPLES VALUE W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R VALUE W Reset 0 0 0 0 0 0 0 0 0 HW_LRADC_CH3 field descriptions Field Description 31 TOGGLE This bit toggles at every completed conversion so software can detect a missed or duplicated sample. 30 RSRVD2 Reserved 29 ACCUMULATE Set this bit to one to add successive samples to the 18 bit accumulator. 28-24 This bit field contains the number of conversion cycles to sum together before reporting operation NUM_SAMPLES complete interrupt status. Set this field to zero for a single conversion per interrupt. 23-18 RSRVD1 VALUE Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2692 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface 38.5.10 LRADC 4 Result Register (HW_LRADC_CH4) The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel four. HW_LRADC_CH4: 0x090 HW_LRADC_CH4_SET: 0x094 HW_LRADC_CH4_CLR: 0x098 HW_LRADC_CH4_TOG: 0x09C The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE if (HW_LRADC_CHn(4).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(4, (BF_LRADC_CHn_ACCUMULATE(1) BF_LRADC_CHn_NUM_SAMPLES(5) BF_LRADC_CHn_VALUE(0) ) ); | // Enable accumulation mode. | // Set samples to five. // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC4_IRQ != BV_LRADC_CTRL1_LRADC4_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(4).VALUE / 5; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2693 Programmable Registers Address: 8005_0000h base + 90h offset = 8005_0090h TOGGLE R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 ACCUMULATE 31 RSRVD2 Bit NUM_SAMPLES VALUE W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R VALUE W Reset 0 0 0 0 0 0 0 0 0 HW_LRADC_CH4 field descriptions Field Description 31 TOGGLE This bit toggles at every completed conversion so software can detect a missed or duplicated sample. 30 RSRVD2 Reserved 29 ACCUMULATE Set this bit to one to add successive samples to the 18 bit accumulator. 28-24 This bit field contains the number of conversion cycles to sum together before reporting operation NUM_SAMPLES complete interrupt status. Set this field to zero for a single conversion per interrupt. 23-18 RSRVD1 VALUE Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2694 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface 38.5.11 LRADC 5 Result Register (HW_LRADC_CH5) The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel five. HW_LRADC_CH5: 0x0A0 HW_LRADC_CH5_SET: 0x0A4 HW_LRADC_CH5_CLR: 0x0A8 HW_LRADC_CH5_TOG: 0x0AC The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE if (HW_LRADC_CHn(5).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(5, (BF_LRADC_CHn_ACCUMULATE(1) BF_LRADC_CHn_NUM_SAMPLES(5) BF_LRADC_CHn_VALUE(0) ) ); | // Enable accumulation mode. | // Set samples to five. // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC5_IRQ != BV_LRADC_CTRL1_LRADC5_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(5).VALUE / 5; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2695 Programmable Registers Address: 8005_0000h base + A0h offset = 8005_00A0h TOGGLE R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 ACCUMULATE 31 RSRVD2 Bit NUM_SAMPLES VALUE W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R VALUE W Reset 0 0 0 0 0 0 0 0 0 HW_LRADC_CH5 field descriptions Field Description 31 TOGGLE This bit toggles at every completed conversion so software can detect a missed or duplicated sample. 30 RSRVD2 Reserved 29 ACCUMULATE Set this bit to one to add successive samples to the 18 bit accumulator. 28-24 This bit field contains the number of conversion cycles to sum together before reporting operation NUM_SAMPLES complete interrupt status. Set this field to zero for a single conversion per interrupt. 23-18 RSRVD1 VALUE Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2696 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface 38.5.12 LRADC 6 Result Register (HW_LRADC_CH6) The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel six. HW_LRADC_CH6: 0x0B0 HW_LRADC_CH6_SET: 0x0B4 HW_LRADC_CH6_CLR: 0x0B8 HW_LRADC_CH6_TOG: 0x0BC The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE if (HW_LRADC_CHn(6).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(6, (BF_LRADC_CHn_ACCUMULATE(1) BF_LRADC_CHn_NUM_SAMPLES(5) BF_LRADC_CHn_VALUE(0) ) ); | // Enable accumulation mode. | // Set samples to five. // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC6_IRQ != BV_LRADC_CTRL1_LRADC6_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(6).VALUE / 5; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2697 Programmable Registers Address: 8005_0000h base + B0h offset = 8005_00B0h TOGGLE R 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RSRVD1 ACCUMULATE 31 RSRVD2 Bit NUM_SAMPLES VALUE W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R VALUE W Reset 0 0 0 0 0 0 0 0 0 HW_LRADC_CH6 field descriptions Field Description 31 TOGGLE This bit toggles at every completed conversion so software can detect a missed or duplicated sample. 30 RSRVD2 Reserved 29 ACCUMULATE Set this bit to one to add successive samples to the 18 bit accumulator. 28-24 This bit field contains the number of conversion cycles to sum together before reporting operation NUM_SAMPLES complete interrupt status. Set this field to zero for a single conversion per interrupt. 23-18 RSRVD1 VALUE Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2698 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface 38.5.13 LRADC 7 (BATT) Result Register (HW_LRADC_CH7) The LRADC result register returns the 12-bit result for low resolution analog to digital converter channel seven (BATT). HW_LRADC_CH7: 0x0C0 HW_LRADC_CH7_SET: 0x0C4 HW_LRADC_CH7_CLR: 0x0C8 HW_LRADC_CH7_TOG: 0x0CC The Result register contains the most recent conversion results for one channel of the LRADC. Note that each channel can be converted at an independent rate. The TOGGLE bit is used to debug missed conversion cycles. When using oversampling, the channel must be individualy scheduled for conversion N times for when N samples are required before an interrupt is generated. This is most easily accomplished by using one of the LRADC Delay Channels. EXAMPLE if (HW_LRADC_CHn(7).TOGGLE == 1) { } // Toggle is high. // ... unsigned long channelAverage; HW_LRADC_CHn_WR(7, (BF_LRADC_CHn_ACCUMULATE(1) BF_LRADC_CHn_NUM_SAMPLES(5) BF_LRADC_CHn_VALUE(0) ) ); | // Enable accumulation mode. | // Set samples to five. // Clear accumulator. // ... setup Delay channel (see HW_LRADC_DELAY0 through 3) while (HW_LRADC_CTRL1.LRADC7_IRQ != BV_LRADC_CTRL1_LRADC7_IRQ__PENDING) { // Wait for interrupt. } channelAverage = HW_LRADC_CHn(7).VALUE / 5; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2699 Programmable Registers Address: 8005_0000h base + C0h offset = 8005_00C0h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TESTMODE_TOGGLE 31 TOGGLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 R RSRVD1 ACCUMULATE Bit NUM_SAMPLES VALUE W Reset Bit R VALUE W Reset 0 0 0 0 0 0 0 0 0 HW_LRADC_CH7 field descriptions Field 31 TOGGLE 30 TESTMODE_ TOGGLE 29 ACCUMULATE Description This bit toggles at every completed conversion so software can detect a missed or duplicated sample. This read-only bit toggles at every completed conversion of interest in test mode so software can synchornize to the desired sample. When the test mode count is loaded with a value of 7, this will toggle every eighth conversion on channel 7. If testmode operation for channel 5 and or 6 are set then the sample rate will be lower for channel 7. Set this bit to one to add successive samples to the 18 bit accumulator. 28-24 This bit field contains the number of conversion cycles to sum together before reporting operation NUM_SAMPLES complete interrupt status. Set this field to zero for a single conversion per interrupt. 23-18 RSRVD1 VALUE Reserved This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results can sum up to 256K. Software is responsible for dividing this value by the number of samples summed together. Software must clear this register in preparation for a multi-cycle accumulation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2700 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface 38.5.14 LRADC Scheduling Delay 0 (HW_LRADC_DELAY0) The LRADC scheduling delay 0 register controls one delay operation. At the end of this delay, this channel can trigger one or more LRADC channels or one or more Scheduling delay channels . HW_LRADC_DELAY0: 0x0D0 HW_LRADC_DELAY0_SET: 0x0D4 HW_LRADC_DELAY0_CLR: 0x0D8 HW_LRADC_DELAY0_TOG: 0x0DC The LRADC Delay Channel provides control by which LRADC channels and delay channels (including itself) may be triggered. The triggering of the selected delay and LRADC channel(s) is delayed by the DELAY field value which counts down on a 2 kHz clock. It is possible to use delay channels chained together to configure dependent timing of channel conversions as in the example provided in introduction to this block. A delay channel may also be configured to trigger itself. In this case, it could be used to simultaneously trigger an LRADC channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the DELAY field. The delay channel is started by setting the KICK bit to one. EXAMPLE HW_LRADC_DELAYn_WR(0, (BF_LRADC_DELAYn_TRIGGER_LRADCS(0x05) | // LRADC channel 0 and 2 BF_LRADC_DELAYn_KICK(1) | // Start the Delay channel BF_LRADC_DELAYn_TRIGGER_DELAYS(0x1) | // restart delay channel 0 each time BF_LRADC_DELAYn_DELAY(0x0E45) ) ); // delay 3653 periods of 2 kHz clock // ... do other things until the triggered LRADC channels report an interrupt. Address: 8005_0000h base + D0h offset = 8005_00D0h Bit 31 30 29 R Bit 26 25 24 23 22 21 RSRVD2 20 19 KICK 18 17 16 TRIGGER_DELAYS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 R LOOP_COUNT W Reset 27 TRIGGER_LRADCS W Reset 28 0 0 0 0 DELAY 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2701 Programmable Registers HW_LRADC_DELAY0 field descriptions Field 31-24 TRIGGER_ LRADCS 23-21 RSRVD2 20 KICK 19-16 TRIGGER_ DELAYS Description Setting a bit in this bit field to one causes the delay controller to trigger the corresponding LRADC channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all eight LRADC channels can be triggered at the same time. Any channel with its corresponding bit set in this field is triggered. The HW accomplishes this by setting the corresponding bit(s) in HW_LRADC_CTRL0_SCHEDULE. Reserved Setting this bit to one initiates a delay cycle. At the end of that cycle, any TRIGGER_LRADCS or TRIGGER_DELAYS will start. Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all four delay channels can be triggered at the same time, including the one that issues the trigger. This can have the effect of automatically retriggering a delay channel. 15-11 LOOP_COUNT This bit field specifies the number of times this delay counter will count down and then trigger its designated targets. This is particularly useful for scheduling multiple samples of an LRADC channel set. If this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target LRADC and/or delay channels. Note setting the loop count to 0x01 will yield two conversions. DELAY This 11-bit field counts down to zero. At zero it triggers either a set of LRADC channel conversions or another delay channel, or both. It can trigger up to all eight LRADCs and all four delay channels in a single event. This counter operates on a 2KHz clock derived from crystal clock. 38.5.15 LRADC Scheduling Delay 1 (HW_LRADC_DELAY1) The LRADC scheduling delay 1 register controls one delay operation. At the end of this delay, this channel can trigger one or more LRADC channels or one or more Scheduling delay channels . HW_LRADC_DELAY1: 0x0E0 HW_LRADC_DELAY1_SET: 0x0E4 HW_LRADC_DELAY1_CLR: 0x0E8 HW_LRADC_DELAY1_TOG: 0x0EC The LRADC Delay Channel provides control by which LRADC channels and delay channels (including itself) may be triggered. The triggering of the selected delay and LRADC channel(s) is delayed by the DELAY field value which counts down on a 2 kHz clock. It is possible to use delay channels chained together to configure dependent timing of channel conversions as in the example provided in introduction to this block. A delay channel may also be configured to trigger itself. In this case, it could be used to i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2702 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface simultaneously trigger an LRADC channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the DELAY field. The delay channel is started by setting the KICK bit to one. EXAMPLE HW_LRADC_DELAYn_WR(1, (BF_LRADC_DELAYn_TRIGGER_LRADCS(0x05) | // LRADC channel 0 and 2 BF_LRADC_DELAYn_KICK(1) | // Start the Delay channel BF_LRADC_DELAYn_TRIGGER_DELAYS(0x2) | // restart delay channel 1 each time BF_LRADC_DELAYn_DELAY(0x0E45) ) ); // delay 3653 periods of 2 kHz clock // ... do other things until the triggered LRADC channels report an interrupt. Address: 8005_0000h base + E0h offset = 8005_00E0h Bit 31 30 29 R Bit 26 25 24 23 22 21 RSRVD2 20 19 KICK 18 17 16 TRIGGER_DELAYS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 R LOOP_COUNT W Reset 27 TRIGGER_LRADCS W Reset 28 0 0 0 0 DELAY 0 0 0 0 0 0 0 HW_LRADC_DELAY1 field descriptions Field 31-24 TRIGGER_ LRADCS 23-21 RSRVD2 20 KICK 19-16 TRIGGER_ DELAYS Description Setting a bit in this bit field to one causes the delay controller to trigger the corresponding LRADC channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all eight LRADC channels can be triggered at the same time. Any channel with its corresponding bit set in this field is triggered. The HW accomplishes this by setting the corresponding bit(s) in HW_LRADC_CTRL0_SCHEDULE. Reserved Setting this bit to one initiates a delay cycle. At the end of that cycle, any TRIGGER_LRADCS or TRIGGER_DELAYS will start. Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all four delay channels can be triggered at the same time, including the one that issues the trigger. This can have the effect of automatically retriggering a delay channel. 15-11 LOOP_COUNT This bit field specifies the number of times this delay counter will count down and then trigger its designated targets. This is particularly useful for scheduling multiple samples of an LRADC channel set. If this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target LRADC and/or delay channels. DELAY This 11-bit field counts down to zero. At zero it triggers either a set of LRADC channel conversions or another delay channel, or both. It can trigger up to all eight LRADCs and all four delay channels in a single event. This counter operates on a 2KHz clock derived from crystal clock. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2703 Programmable Registers 38.5.16 LRADC Scheduling Delay 2 (HW_LRADC_DELAY2) The LRADC scheduling delay 2 register controls one delay operation. At the end of this delay, this channel can trigger one or more LRADC channels or one or more Scheduling delay channels . HW_LRADC_DELAY2: 0x0F0 HW_LRADC_DELAY2_SET: 0x0F4 HW_LRADC_DELAY2_CLR: 0x0F8 HW_LRADC_DELAY2_TOG: 0x0FC The LRADC Delay Channel provides control by which LRADC channels and delay channels (including itself) may be triggered. The triggering of the selected delay and LRADC channel(s) is delayed by the DELAY field value which counts down on a 2 kHz clock. It is possible to use delay channels chained together to configure dependent timing of channel conversions as in the example provided in introduction to this block. A delay channel may also be configured to trigger itself. In this case, it could be used to simultaneously trigger an LRADC channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the DELAY field. The delay channel is started by setting the KICK bit to one. EXAMPLE HW_LRADC_DELAYn_WR(2, (BF_LRADC_DELAYn_TRIGGER_LRADCS(0x05) | // LRADC channel 0 and 2 BF_LRADC_DELAYn_KICK(1) | // Start the Delay channel BF_LRADC_DELAYn_TRIGGER_DELAYS(0x4) | // restart delay channel 2 each time BF_LRADC_DELAYn_DELAY(0x0E45) ) ); // delay 3653 periods of 2 kHz clock // ... do other things until the triggered LRADC channels report an interrupt. Address: 8005_0000h base + F0h offset = 8005_00F0h Bit 31 30 29 R Bit 26 25 24 23 22 21 RSRVD2 20 19 KICK 18 17 16 TRIGGER_DELAYS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 R LOOP_COUNT W Reset 27 TRIGGER_LRADCS W Reset 28 0 0 0 0 DELAY 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2704 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_DELAY2 field descriptions Field 31-24 TRIGGER_ LRADCS 23-21 RSRVD2 20 KICK 19-16 TRIGGER_ DELAYS 15-11 LOOP_COUNT Description Setting a bit in this bit field to one causes the delay controller to trigger the corresponding LRADC channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all eight LRADC channels can be triggered at the same time. Any channel with its corresponding bit set in this field is triggered. The HW accomplishes this by setting the corresponding bit(s) in HW_LRADC_CTRL0_SCHEDULE. Reserved Setting this bit to one initiates a delay cycle. At the end of that cycle, any TRIGGER_LRADCS or TRIGGER_DELAYS will start. Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all four delay channels can be triggered at the same time, including the one that issues the trigger. This can have the effect of automatically retriggering a delay channel. This bit field specifies the number of times this delay counter will count down and then trigger its designated targets. This is particularly useful for scheduling multiple samples of an LRADC channel set. If this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target LRADC and/or delay channels. ERRATA: TA1 and TA2 silicon revisions do not correctly support the LOOP_COUNT field, do not use. DELAY This 11-bit field counts down to zero. At zero it triggers either a set of LRADC channel conversions or another delay channel, or both. It can trigger up to all eight LRADCs and all four delay channels in a single event. This counter operates on a 2KHz clock derived from crystal clock. 38.5.17 LRADC Scheduling Delay 3 (HW_LRADC_DELAY3) The LRADC scheduling delay 3 register controls one delay operation. At the end of this delay, this channel can trigger one or more LRADC channels or one or more Scheduling delay channels . HW_LRADC_DELAY3: 0x100 HW_LRADC_DELAY3_SET: 0x104 HW_LRADC_DELAY3_CLR: 0x108 HW_LRADC_DELAY3_TOG: 0x10C The LRADC Delay Channel provides control by which LRADC channels and delay channels (including itself) may be triggered. The triggering of the selected delay and LRADC channel(s) is delayed by the DELAY field value which counts down on a 2 kHz clock. It is possible to use delay channels chained together to configure dependent timing of channel conversions as in the example provided in introduction to this block. A delay channel may also be configured to trigger itself. In this case, it could be used to i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2705 Programmable Registers simultaneously trigger an LRADC channel, providing continuous acquisitions of the conversions executed, delayed by the value specified in the DELAY field. The delay channel is started by setting the KICK bit to one. EXAMPLE HW_LRADC_DELAYn_WR(3, (BF_LRADC_DELAYn_TRIGGER_LRADCS(0x05) | // LRADC channel 0 and 2 BF_LRADC_DELAYn_KICK(1) | // Start the Delay channel BF_LRADC_DELAYn_TRIGGER_DELAYS(0x8) | // restart delay channel 3 each time BF_LRADC_DELAYn_DELAY(0x0E45) ) ); // delay 3653 periods of 2 kHz clock // ... do other things until the triggered LRADC channels report an interrupt. Address: 8005_0000h base + 100h offset = 8005_0100h Bit 31 30 29 R Bit 26 25 24 23 22 21 RSRVD2 20 19 KICK 18 17 16 TRIGGER_DELAYS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 R LOOP_COUNT W Reset 27 TRIGGER_LRADCS W Reset 28 0 0 0 0 DELAY 0 0 0 0 0 0 0 HW_LRADC_DELAY3 field descriptions Field 31-24 TRIGGER_ LRADCS 23-21 RSRVD2 20 KICK 19-16 TRIGGER_ DELAYS 15-11 LOOP_COUNT Description Setting a bit in this bit field to one causes the delay controller to trigger the corresponding LRADC channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all eight LRADC channels can be triggered at the same time. Any channel with its corresponding bit set in this field is triggered. The HW accomplishes this by setting the corresponding bit(s) in HW_LRADC_CTRL0_SCHEDULE. Reserved Setting this bit to one initiates a delay cycle. At the end of that cycle, any TRIGGER_LRADCS or TRIGGER_DELAYS will start. Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel. This trigger occurs when the delay count of this delay channel reaches zero. Note that all four delay channels can be triggered at the same time, including the one that issues the trigger. This can have the effect of automatically retriggering a delay channel. This bit field specifies the number of times this delay counter will count down and then trigger its designated targets. This is particularly useful for scheduling multiple samples of an LRADC channel set. If this field is set to 0x0, then exactly one delay loop will be generated with exactly one event triggering the target LRADC and/or delay channels. ERRATA: TA1 and TA2 silicon revisions do not correctly support the LOOP_COUNT field, do not use. Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2706 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_DELAY3 field descriptions (continued) Field Description DELAY This 11-bit field counts down to zero. At zero it triggers either a set of LRADC channel conversions or another delay channel, or both. It can trigger up to all eight LRADCs and all four delay channels in a single event. This counter operates on a 2KHz clock derived from crystal clock. 38.5.18 LRADC Debug Register 0 (HW_LRADC_DEBUG0) The LRADC debug register provides read-only access to various internal states and other debug information. HW_LRADC_DEBUG0: 0x110 HW_LRADC_DEBUG0_SET: 0x114 HW_LRADC_DEBUG0_CLR: 0x118 HW_LRADC_DEBUG0_TOG: 0x11C The LRADC debug register contains read-only diagnostic information regarding the internal state machine. This only used in debugging. EXAMPLE if (HW_LRADC_DEBUG0.STATE == 0X33) {} // some action based on this state. Address: 8005_0000h base + 110h offset = 8005_0110h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 READONLY R 14 13 12 11 10 9 8 7 RSRVD1 6 5 4 3 2 1 0 0 0 0 0 0 STATE W Reset 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 HW_LRADC_DEBUG0 field descriptions Field 31-16 READONLY 15-12 RSRVD1 STATE Description LRADC internal state machine current state. Reserved LRADC internal state machine current state. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2707 Programmable Registers 38.5.19 LRADC Debug Register 1 (HW_LRADC_DEBUG1) The LRADC debug register provides read-only access to various internal states and other debug information. HW_LRADC_DEBUG1: 0x120 HW_LRADC_DEBUG1_SET: 0x124 HW_LRADC_DEBUG1_CLR: 0x128 HW_LRADC_DEBUG1_TOG: 0x12C The LRADC DEBUG1 register provides, read-only diagnostic information and control over the test modes of LRADC channels 5, 6 and 7. This is only used in debugging the LRADC. EXAMPLE BW_LRADC_DEBUG1_TESTMODE(BV_LRADC_DEBUG1_TESTMODE__TEST); Address: 8005_0000h base + 120h offset = 8005_0120h Bit 31 30 29 28 27 26 25 24 23 22 21 RSRVD3 R 20 19 18 17 16 REQUEST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TESTMODE Bit 0 TESTMODE5 Reset TESTMODE6 W 0 0 0 0 0 RSRVD2 R RSRVD1 TESTMODE_COUNT W Reset 0 0 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2708 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_DEBUG1 field descriptions Field 31-24 RSRVD3 23-16 REQUEST 15-13 RSRVD2 12-8 TESTMODE_ COUNT 7-3 RSRVD1 Description Reserved LRADC internal request register. Reserved When in test mode, the value in this register will be loaded in to a counter which is decremented upon each Channel 7 conversion. When that counter decrements to zero, the HW_LRADC_CH7.TESTMODE_TOGGLE field will be toggled, indicating that the conversion value of interest is available in the HW_LRADC_CH7.VALUE bit field. Reserved 2 TESTMODE6 Force dummy conversion cycles on channel 6 during test mode. 1 TESTMODE5 Force dummy conversion cycles on channel 5 during test mode. 0 TESTMODE Place the LRADC in a special test mode in which the analog section is free-running at its clock rate. LRADC_CH7 result is continuously updated every N conversions from the analog source selected in CTRL2, where N is determined by TESTMODE_COUNT. 0x0 0x1 0x0 0x1 0x0 0x1 NORMAL -- Normal operation. TEST -- Put it in test mode, i.e. continuously sample channel 6. NORMAL -- Normal operation. TEST -- Put it in test mode, i.e. continuously sample channel 5. NORMAL -- Normal operation. TEST -- Put it in test mode, i.e. continuously sample channel 7. 38.5.20 LRADC Battery Conversion Register (HW_LRADC_CONVERSION) The LRADC battery conversion register provides access to the battery voltage scale multiplier. HW_LRADC_CONVERSION: 0x130 HW_LRADC_CONVERSION_SET: 0x134 HW_LRADC_CONVERSION_CLR: 0x138 HW_LRADC_CONVERSION_TOG: 0x13C This register controls the voltage scaling multiplier which is used to multiply the LRADC battery voltage by 29 divided by 512 for NiMH, battery voltage times 29 divided by 256 for dual NiMH and battery voltage times 29 divided by 128 for Lithium Ion batteries. EXAMPLE i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2709 Programmable Registers HW_LRADC_CONVERSION.AUTOMATIC = 1; Address: 8005_0000h base + 130h offset = 8005_0130h Bit 31 30 29 28 27 26 25 24 23 22 21 20 RSRVD3 18 17 16 RSRVD2 AUTOMATIC R 19 SCALE_ FACTOR W Reset Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 RSRVD1 R SCALED_BATT_VOLTAGE W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 HW_LRADC_CONVERSION field descriptions Field 31-21 RSRVD3 20 AUTOMATIC Description Reserved Control the automatic update mode of the BATT_VAL bit field in the HW_POWER_BATTMONITOR register. 0x0 0x1 19-18 RSRVD2 DISABLE -- No automatic update of the scaled value. ENABLE -- Automatically compute the scaled battery voltage each time an LRADC Channel 7 (BATT) conversion takes place. Before setting this enable bit, user need to program the scale factor to 0x2. Before setting this enable bit, user need to program the scale factor to 0x2. Reserved 17-16 i.MX28 only support Li-ION battery, user need to program the scale factor to 0x2 SCALE_FACTOR 0x0 Reserved 0x1 Reserved 0x2 LI_ION -- Lithium Ion Battery operation, 29/128. 0x3 Reserved Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2710 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_CONVERSION field descriptions (continued) Field Description 15-10 RSRVD1 Reserved SCALED_BATT_ LRADC Battery Voltage Divided by approximately 4.414. The actual scale factor is (battery voltage) times VOLTAGE 29 divided by 128. 38.5.21 LRADC Control Register 4 (HW_LRADC_CTRL4) LRADC control register 4 specifies the analog mux selector values used for channels 0 through channel 7. HW_LRADC_CTRL4: 0x140 HW_LRADC_CTRL4_SET: 0x144 HW_LRADC_CTRL4_CLR: 0x148 HW_LRADC_CTRL4_TOG: 0x14C Each virtual channel of the LRADC can be directed to use any of the 16 analog mux input sources for it conversion. This register specifies the analog mux to channels to be used for LRADC virtual channels 0 through 7. EXAMPLE BW_LRADC_CTRL4_LRADC3SELECT(BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11); Address: 8005_0000h base + 140h offset = 8005_0140h Bit 31 R W Reset Bit 29 28 27 LRADC7SELECT 26 25 24 23 LRADC6SELECT 22 21 20 19 LRADC5SELECT 18 17 16 LRADC4SELECT 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Reset 30 LRADC3SELECT 0 0 1 LRADC2SELECT 1 0 0 1 LRADC1SELECT 0 0 0 0 LRADC0SELECT 1 0 0 0 0 HW_LRADC_CTRL4 field descriptions Field Description 31-28 This bit field selects which analog mux input is used for conversion on LRADC channel 7. LRADC7SELECT 0x0 CHANNEL0 -- 0x1 CHANNEL1 -- 0x2 CHANNEL2 -- 0x3 CHANNEL3 -- Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2711 Programmable Registers HW_LRADC_CTRL4 field descriptions (continued) Field Description 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF CHANNEL4 -- CHANNEL5 -- CHANNEL6 -- CHANNEL7 -- BATTERY CHANNEL8 -- Temperature Sense CHANNEL9 -- Temperature Sense CHANNEL10 -- VDDIO CHANNEL11 -- VTH CHANNEL12 -- VDDA CHANNEL13 -- VDDD CHANNEL14 -- VBG (Can be used to calibrate the LRADC) CHANNEL15 -- 5V input 27-24 This bit field selects which analog mux input is used for conversion on LRADC channel 6. LRADC6SELECT 0x0 CHANNEL0 -- 0x1 CHANNEL1 -- 0x2 CHANNEL2 -- 0x3 CHANNEL3 -- 0x4 CHANNEL4 -- 0x5 CHANNEL5 -- 0x6 CHANNEL6 -- 0x7 CHANNEL7 -- BATTERY 0x8 CHANNEL8 -- Temperature Sense 0x9 CHANNEL9 -- Temperature Sense 0xA CHANNEL10 -- VDDIO 0xB CHANNEL11 -- VTH 0xC CHANNEL12 -- VDDA 0xD CHANNEL13 -- VDDD 0xE CHANNEL14 -- VBG (Can be used to calibrate the LRADC) 0xF CHANNEL15 -- 5V input 23-20 This bit field selects which analog mux input is used for conversion on LRADC channel 5. LRADC5SELECT 0x0 CHANNEL0 -- 0x1 CHANNEL1 -- 0x2 CHANNEL2 -- 0x3 CHANNEL3 -- 0x4 CHANNEL4 -- 0x5 CHANNEL5 -- 0x6 CHANNEL6 -- 0x7 CHANNEL7 -- BATTERY 0x8 CHANNEL8 -- Temperature Sense 0x9 CHANNEL9 -- Temperature Sense 0xA CHANNEL10 -- VDDIO 0xB CHANNEL11 -- VTH 0xC CHANNEL12 -- VDDA 0xD CHANNEL13 -- VDDD Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2712 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface HW_LRADC_CTRL4 field descriptions (continued) Field Description 0xE 0xF CHANNEL14 -- VBG (Can be used to calibrate the LRADC) CHANNEL15 -- 5V input 19-16 This bit field selects which analog mux input is used for conversion on LRADC channel 4. LRADC4SELECT 0x0 CHANNEL0 -- 0x1 CHANNEL1 -- 0x2 CHANNEL2 -- 0x3 CHANNEL3 -- 0x4 CHANNEL4 -- 0x5 CHANNEL5 -- 0x6 CHANNEL6 -- 0x7 CHANNEL7 -- BATTERY 0x8 CHANNEL8 -- Temperature Sense 0x9 CHANNEL9 -- Temperature Sense 0xA CHANNEL10 -- VDDIO 0xB CHANNEL11 -- VTH 0xC CHANNEL12 -- VDDA 0xD CHANNEL13 -- VDDD 0xE CHANNEL14 -- VBG (Can be used to calibrate the LRADC) 0xF CHANNEL15 -- 5V input 15-12 This bit field selects which analog mux input is used for conversion on LRADC channel 3. LRADC3SELECT 0x0 CHANNEL0 -- 0x1 CHANNEL1 -- 0x2 CHANNEL2 -- 0x3 CHANNEL3 -- 0x4 CHANNEL4 -- 0x5 CHANNEL5 -- 0x6 CHANNEL6 -- 0x7 CHANNEL7 -- BATTERY 0x8 CHANNEL8 -- Temperature Sense 0x9 CHANNEL9 -- Temperature Sense 0xA CHANNEL10 -- VDDIO 0xB CHANNEL11 -- VTH 0xC CHANNEL12 -- VDDA 0xD CHANNEL13 -- VDDD 0xE CHANNEL14 -- VBG (Can be used to calibrate the LRADC) 0xF CHANNEL15 -- 5V input 11-8 This bit field selects which analog mux input is used for conversion on LRADC channel 2. LRADC2SELECT 0x0 CHANNEL0 -- 0x1 CHANNEL1 -- 0x2 CHANNEL2 -- 0x3 CHANNEL3 -- 0x4 CHANNEL4 -- 0x5 CHANNEL5 -- 0x6 CHANNEL6 -- Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2713 Programmable Registers HW_LRADC_CTRL4 field descriptions (continued) Field Description 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF CHANNEL7 -- BATTERY CHANNEL8 -- Temperature Sense CHANNEL9 -- Temperature Sense CHANNEL10 -- VDDIO CHANNEL11 -- VTH CHANNEL12 -- VDDA CHANNEL13 -- VDDD CHANNEL14 -- VBG (Can be used to calibrate the LRADC) CHANNEL15 -- 5V input 7-4 This bit field selects which analog mux input is used for conversion on LRADC channel 1. LRADC1SELECT 0x0 CHANNEL0 -- 0x1 CHANNEL1 -- 0x2 CHANNEL2 -- 0x3 CHANNEL3 -- 0x4 CHANNEL4 -- 0x5 CHANNEL5 -- 0x6 CHANNEL6 -- 0x7 CHANNEL7 -- BATTERY 0x8 CHANNEL8 -- Temperature Sense 0x9 CHANNEL9 -- Temperature Sense 0xA CHANNEL10 -- VDDIO 0xB CHANNEL11 -- VTH 0xC CHANNEL12 -- VDDA 0xD CHANNEL13 -- VDDD 0xE CHANNEL14 -- VBG (Can be used to calibrate the LRADC) 0xF CHANNEL15 -- 5V input LRADC0SELECT This bit field selects which analog mux input is used for conversion on LRADC channel 0. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF CHANNEL0 -- CHANNEL1 -- CHANNEL2 -- CHANNEL3 -- CHANNEL4 -- CHANNEL5 -- CHANNEL6 -- CHANNEL7 -- BATTERY CHANNEL8 -- Temperature Sense CHANNEL9 -- Temperature Sense CHANNEL10 -- VDDIO CHANNEL11 -- VTH CHANNEL12 -- VDDA CHANNEL13 -- VDDD CHANNEL14 -- VBG (Can be used to calibrate the LRADC) CHANNEL15 -- 5V input i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2714 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface 38.5.22 LRADC Theshold0 Register (HW_LRADC_THRESHOLD0) This register configures the channel threshold comparison functionality. HW_LRADC_THRESHOLD0: 0x150 HW_LRADC_THRESHOLD0_SET: 0x154 HW_LRADC_THRESHOLD0_CLR: 0x158 HW_LRADC_THRESHOLD0_TOG: 0x15C This register configures the channel threshold mechanism. The threshold field is compared against the channel result value and if the programmed condition is met a status bit is set and an interrrupt can also be generated. EXAMPLE Address: 8005_0000h base + 150h offset = 8005_0150h 30 29 28 27 26 25 24 23 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Bit 21 0 RSRVD1 R Reset 22 BATTCHRG_DISABLE 31 ENABLE Bit CHANNEL_SEL SETTING VALUE R VALUE W Reset 0 0 0 0 0 0 0 0 0 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2715 Programmable Registers HW_LRADC_THRESHOLD0 field descriptions Field Description 31-25 RSRVD1 Reserved 24 ENABLE Set this bit to turn on the threshold functionality which starts the sampling of channel conversions for comparison against the threshold value. 23 BATTCHRG_ DISABLE Enable this bit to cause the battery charger to shut off (HW_POWER_CHARGE_PWD_BATTCHRG will be asserted) when the threshold event first asserts (edge triggers the PWD_BATTCHRG). Note: It is the responsibility of software to ensure that the proper channels are programmed and selected so the external battery temperature is being monitored by this threshold unit. 22-20 This field selects which of the 8 virtual channels this threshold applies to. CHANNEL_SEL 0x0 CHANNEL0 -- 0x1 CHANNEL1 -- 0x2 CHANNEL2 -- 0x3 CHANNEL3 -- 0x4 CHANNEL4 -- 0x5 CHANNEL5 -- 0x6 CHANNEL6 -- 0x7 CHANNEL7 -- 19-18 SETTING VALUE This specifies how to compare the result and threshold values. 0x0 0x1 0x2 0x3 NO_COMPARE -- This feature disabled. DETECT_LOW -- Detect when the channel result reaches the threshold value after being above it. DETECT_HIGH -- Detect when the channel result reaches the threshold value after being below it. RESERVED -- Reserved value. This is the threshold value to compare to the selected channel's result value. If oversampling (ACCUMULATE mode) is selected for the successive sample conversion in each virtual channel, Software is responsible for setting this value by multiplying NUM_SAMPLES. 38.5.23 LRADC Theshold1 Register (HW_LRADC_THRESHOLD1) This register configures the channel threshold comparison functionality. HW_LRADC_THRESHOLD1: 0x160 HW_LRADC_THRESHOLD1_SET: 0x164 HW_LRADC_THRESHOLD1_CLR: 0x168 HW_LRADC_THRESHOLD1_TOG: 0x16C This register configures the channel threshold mechanism. The threshold field is compared against the channel result value and if the programmed condition is met a status bit is set and an interrrupt can also be generated. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2716 Freescale Semiconductor, Inc. Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface EXAMPLE Address: 8005_0000h base + 160h offset = 8005_0160h 30 29 28 27 26 25 24 23 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 W Bit 21 0 RSRVD1 R Reset 22 BATTCHRG_DISABLE 31 ENABLE Bit CHANNEL_SEL SETTING VALUE R VALUE W Reset 0 0 0 0 0 0 0 0 0 HW_LRADC_THRESHOLD1 field descriptions Field Description 31-25 RSRVD1 Reserved 24 ENABLE Set this bit to turn on the threshold functionality which starts the sampling of channel conversions for comparison against the threshold value. 23 BATTCHRG_ DISABLE Enable this bit to cause the battery charger to shut off (HW_POWER_CHARGE_PWD_BATTCHRG will be asserted) when the threshold event first asserts (edge triggers the PWD_BATTCHRG). Note: It is the responsibility of software to ensure that the proper channels are programmed and selected so the external battery temperature is being monitored by this threshold unit. 22-20 This field selects which of the 8 virtual channels this threshold applies to. CHANNEL_SEL 0x0 CHANNEL0 -- 0x1 CHANNEL1 -- 0x2 CHANNEL2 -- Table continues on the next page... i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2717 Programmable Registers HW_LRADC_THRESHOLD1 field descriptions (continued) Field Description CHANNEL3 -- CHANNEL4 -- CHANNEL5 -- CHANNEL6 -- CHANNEL7 -- 0x3 0x4 0x5 0x6 0x7 19-18 SETTING This specifies how to compare the result and threshold values. NO_COMPARE -- This feature disabled. DETECT_LOW -- Detect when the channel result crosses below the threshold value. DETECT_HIGH -- Detect when the channel result crosses above the threshold value. RESERVED -- Reserved value. 0x0 0x1 0x2 0x3 VALUE This is the threshold value to compare to the sellected channel's result value. If oversampling (ACCUMULATE mode) is selected for the successive sample conversion in each virtual channel, Software is responsible for setting this value by multiplying NUM_SAMPLES. 38.5.24 LRADC Version Register (HW_LRADC_VERSION) This register always returns a known read value for debug purposes it indicates the version of the block. EXAMPLE if (HW_ICOLL_VERSION.B.MAJOR != 1) Error(); Address: 8005_0000h base + 170h offset = 8005_0170h Bit 31 30 29 28 27 26 25 24 23 22 21 MAJOR R 20 19 18 17 16 15 14 13 12 11 10 9 MINOR 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 STEP W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 HW_LRADC_VERSION field descriptions Field Description 31-24 MAJOR Fixed read-only value reflecting the MAJOR field of the RTL version. 23-16 MINOR Fixed read-only value reflecting the MINOR field of the RTL version. STEP Fixed read-only value reflecting the stepping of the RTL version. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2718 Freescale Semiconductor, Inc. Chapter 39 Register Macro Usage 39.1 Overview This chapter provides background on the i.MX28 register set and illustrates a consistent use of the C macros for registers. The examples provided here show how to use the hardware register macros generated from the chip database. 39.2 Definitions //////////////////////////////////////////////////////////////////////////////// // These macros will be generated from the chip data base in the future #define BF_GPMI_CTRL0_SFTRST_V(v) (BV_GPMI_CTRL0_SFTRST_##v << 31) #define BF_GPMI_CTRL0_CLKGATE_V(v) (BV_GPMI_CTRL0_CLKGATE_##v << 30) #define BF_GPMI_CTRL0_RUN_V(v) (BV_GPMI_CTRL0_RUN_##v << 29) #define BF_GPMI_CTRL0_UDMA_V(v) (BV_GPMI_CTRL0_UDMA_##v << 26) #define BF_GPMI_CTRL0_COMMAND_MODE_V(v) (BV_GPMI_CTRL0_COMMAND_MODE_##v << 24) #define BF_GPMI_CTRL0_WORD_LENGTH_V(v) (BV_GPMI_CTRL0_WORD_LENGTH_##v << 23) #define BF_GPMI_CTRL0_LOCK_CS_V(v) (BV_GPMI_CTRL0_LOCK_CS_##v << 22) #define BF_GPMI_CTRL0_ADDRESS_V(v) (BV_GPMI_CTRL0_ADDRESS_##v << 17) #define BF_GPMI_CTRL0_ADDRESS_INCREMENT_V(v) (BV_GPMI_CTRL0_ADDRESS_INCREMENT_##v << 16) #define BF_TIMROT_TIMCTRLn_SELECT_V(v) (BV_TIMROT_TIMCTRLn_SELECT_##v << 0) // These macros will be included in regs.h in the future #define OR2(b,f1,f2) (b##_##f1 | b##_##f2) #define OR3(b,f1,f2,f3) (b##_##f1 | b##_##f2 | b##_##f3) #define OR4(b,f1,f2,f3,f4) (b##_##f1 | b##_##f2 | b##_##f3 | b##_##f4) //////////////////////////////////////////////////////////////////////////////// // Prototypes //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Variables //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //! \brief Provides examples of how to use the register access macros. //! //! \fntype Function //! //! Provides examples of how to use the register access macros. //////////////////////////////////////////////////////////////////////////////// void hw_regs_Example(void) { int i, iMode = 0, iRun = 0; // i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2719 Background 39.3 Background The i.MX28 SOC is built on a 32-bit architecture using an ARM926 core. All hardware blocks are controlled and accessed through 32-bit wide registers. The design of these registers is maintained in a database that is part of the overall chip design. As part of the chip build process, a set of C include files are generated from the register descriptions. These include files provide a consistent set of C defines and macros that should be used to access the hardware registers. The i.MX28 SOC has a complex architecture that uses multiple buses to segment I/O traffic and clock domains. To facilitate low power consumption, clocks are set to just meet application demands. In general, the I/O buses and associated hardware blocks run at speeds much slower than the CPU. As a result, reading a hardware register incurs a potentially large number of wait cycles, as the CPU must wait for the register data to travel multiple buses and bridges. The SOC does provide write buffering, meaning the CPU does not wait for register write transactions to complete. From the CPU perspective, register writes occur much faster than reads. Most of the 32-bit registers are subdivided into smaller functional fields. These bit fields can be any number of bits wide and are usually packed. Thus, most fields do not align on byte or half-word boundaries. A common operation is to update one field without disturbing the contents of the remaining fields in the register. Normally, this requires a read-modify-write (RMW) operation, where the CPU reads the register, modifies the target field, then writes the results back to the register. As already noted, this is an expensive operation in terms of CPU cycles, because of the initial register read. To address this issue, most hardware registers are implemented as a set, including registers that can be used to either set, clear, or toggle (SCT) individual bits of the primary register. When writing to an SCT register, all bits set to 1 perform the associated operation on the primary register, while all bits set to 0 are not affected. The SCT registers always read back 0, and should be considered write-only. The SCT registers are not implemented if the primary register is read-only. With this architecture, it is possible to update one or more fields using only register writes. First, all bits of the target fields are cleared by a write to the associated clear register, then the desired value of the target fields is written to the set register. This sequence of two writes is referred to as a clear-set (CS) operation. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2720 Freescale Semiconductor, Inc. Chapter 39 Register Macro Usage A CS operation does have one potential drawback. Whenever a field is modified, the hardware sees a value of 0 before the final value is written. For most fields, passing through the 0 state is not a problem. Nonetheless, this behavior is something to consider when using a CS operation. Also, a CS operation is not required for fields that are one bit wide. While the CS operation works in this case, it is more efficient to simply set or clear the target bit (that is, one write instead of two). A simple set or clear operation is also atomic, while a CS operation is not. Note that not all macros for set, clear, or toggle (SCT) are atomic. For registers that do not provide hardware support for this functionality, these macros are implemented as a sequence of read/modify/write operations. When atomic operation is required, the developer should pay attention to this detail, because unexpected behavior might result if an interrupt occurs in the middle of the critical section comprising the update sequence. 39.3.1 Multi-Instance Blocks Additionally, newer silicon architecture adds the concept of Multi-Instance Blocks which is similar to Multi-Instance Registers, although a Multi-Instance Block may also contain Multi-Instance Registers (There are none in the i.MX28). In order to accommodate that (and additional chips going forward) Multi-Instance Blocks have a required additional parameter specifying the block number but use otherwise identical nomenclature. This also allows runtime usage of different blocks (perhaps unifying driver models) without recompilation or near-duplication of code and run-time selection of macros. The i.MX28 SOC starts all blocks from 1. Future chips will all start at index 0. 39.3.1.1 Examples The SSP has two instances (numbered 1 and 2). To access the CTRL0 register in that block, instead of having two separate include files with hard coded macros, one can use the following: HW_SSP_CTRL0_WR(instance, value); where instance is 1 or 2, and value is (in this case) the 32 bit value to be written to the SSP_CTRL0 register in the block specified by instance. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2721 Naming Convention 39.4 Naming Convention The generated include files and macros follow a consistent naming convention that matches the SOC documentation. This prevents name-space collisions and makes the macros easier to remember. // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // The include file for a specific hardware module is named: regs.h Every register has an associated typedef that provides a C definition of the register. The definition is always a union of a 32-bit unsigned int (i.e., reg32_t), and an anonymous bit field structure. hw___t Macros and defines that relate to a register as a whole are named: HW___ADDR HW____ADDR - defines for the indicated register address HW__ - a define for accessing the primary register using the typedef. Should be used as an rvalue (i.e., for reading), but avoided as an lvalue (i.e., for writing). Will usually generate RMW when used as an lvalue. HW___RD() HW___WR() - macros for reading/writing the primary register as a whole HW___() - macros for writing the associated set | clear | toggle registers Macros and defines that relate to the fields of a register are named: BM___ BP___ - defines for the field's bit mask and bit position BF___() BF____V() - macros for generating a bit field value. The parameter is masked and shifted to the field position. BW___() - macro for writing a bit field. Usually expands to a CS operation. Not generated for read-only fields. BV____ - define equates to an unshifted named value for the field Some hardware modules repeat the same register definition multiple times. An example is a block that implements multiple channels. For these registers, the name adds a lowercase 'n' after the module, and the HW_ macros take a numbered parameter to select the channel (or instance). This allows these macros to be used in for loops. HW_n_(n,...) - the n parameter must evaluate to an integer, and selects the channel i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2722 Freescale Semiconductor, Inc. Chapter 39 Register Macro Usage // // // // // // // // or instance number. The regs.h include file provides several "generic" macros that can be used as an alternate syntax for the various register operations. Because most operations involve using two or more of the above defines/macros, the , and are often repeated in a C expression. The generic macros provide shorthand to avoid the repetition. Refer to the following examples for the alternate syntax. The C++ style comments above represent a single-instance block. For multiple-instance blocks, the macros are similar, but have an instance number as the first parameter where needed. (Differences only shown below.) Note x is the block instance number. If shown, v is the value field for the macro. // HW___ADDR(x) // HW____ADDR(x) // - defines for the indicated register address // // HW__ // - a define for accessing the primary register using the typedef. // Should be used as an rvalue (i.e., for reading), but avoided as // an lvalue (i.e., for writing). Will usually generate RMW when // used as an lvalue. // // HW___RD(x) // HW___WR(x) // - macros for reading/writing the primary register as a whole // // HW___(x) // - macros for writing the associated set | clear | toggle registers // // Macros and defines that relate to the fields of a register are named: // // BW___(x, v) // - macro for writing a bit field. Usually expands to a CS operation. // Not generated for read-only fields. 39.5 Examples The following examples show how to code common register operations using the predefined include files. Each example shows preferred and alternate syntax and also shows constructs to avoid. Summaries are provided toward the end. The examples are valid C and will compile without errors. The reader is encouraged to compile this file and examine the resulting assembly code. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2723 Examples 39.5.1 Setting 1-Bit Wide Field // Preferred (one atomic write to SET register) HW_GPMI_CTRL0_SET(BM_GPMI_CTRL0_UDMA); // Alternate (same as above, just different syntax) BF_SET(GPMI_CTRL0, UDMA); // Avoid BW_GPMI_CTRL0_UDMA(1); // writes 1 to _CLR then 1 to _SET register BF_WR(GPMI_CTRL0, UDMA, 1); // same as above, just different syntax HW_GPMI_CTRL0.B.UDMA = 1; // RMW 39.5.2 Clearing 1-Bit Wide Field // Preferred (one atomic write to _CLR register) HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_DEV_IRQ_EN); // Alternate (same as above, just different syntax) BF_CLR(GPMI_CTRL0, DEV_IRQ_EN); // Avoid BW_GPMI_CTRL0_DEV_IRQ_EN(0); // writes 1 to _CLR then 0 to _SET register BF_WR(GPMI_CTRL0, DEV_IRQ_EN, 0); // same as above, just different syntax HW_GPMI_CTRL0.B.DEV_IRQ_EN = 0; // RMW 39.5.3 Toggling 1-Bit Wide Field // Preferred (one atomic write to _TOG register) HW_GPMI_CTRL0_TOG(BM_GPMI_CTRL0_RUN); // Alternate (same as above, just different syntax) BF_TOG(GPMI_CTRL0, RUN); // Avoid HW_GPMI_CTRL0.B.RUN ^= 1; // RMW 39.5.4 Modifying n-Bit Wide Field // Preferred (does CS operation or byte/halfword write if the field is // 8 or 16 bits wide and properly aligned) BW_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE); BW_GPMI_CTRL0_COMMAND_MODE(iMode); BW_GPMI_CTRL0_XFER_COUNT(2); // this does a halfword write // Alternate (same as above, just different syntax) BF_WR(GPMI_CTRL0, COMMAND_MODE, BV_GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE); BF_WR(GPMI_CTRL0, COMMAND_MODE, iMode); BF_WR(GPMI_CTRL0, XFER_COUNT, 2); // this does a halfword write // Avoid (RMW) HW_GPMI_CTRL0.B.COMMAND_MODE = BV_GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE; HW_GPMI_CTRL0.B.COMMAND_MODE = iMode; 39.5.5 Modifying Multiple Fields // Preferred (explicit CS operation) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2724 Freescale Semiconductor, Inc. Chapter 39 Register Macro Usage HW_GPMI_CTRL0_CLR( OR3(BM_GPMI_CTRL0, RUN, DEV_IRQ_EN, COMMAND_MODE) ); HW_GPMI_CTRL0_SET( OR3(BF_GPMI_CTRL0, RUN(iRun), DEV_IRQ_EN(1), COMMAND_MODE_V(READ_AND_COMPARE)) ); // Alternate (same as above, just different syntax) BF_CS3(GPMI_CTRL0, RUN, iRun, DEV_IRQ_EN, 1, COMMAND_MODE, BV_GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE); // Avoid (multiple RMW - the C compiler does NOT merge into one RMW) HW_GPMI_CTRL0.B.RUN = iRun; HW_GPMI_CTRL0.B.DEV_IRQ_EN = 1; HW_GPMI_CTRL0.B.COMMAND_MODE = BV_GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE; 39.5.6 Writing Entire Register (All Fields Updated at Once) // Preferred HW_GPMI_CTRL0_WR(BM_GPMI_CTRL0_SFTRST); // all other fields are set to 0 // Alternate (same as above, just different syntax) HW_GPMI_CTRL0.U = BM_GPMI_CTRL0_SFTRST; 39.5.7 Reading a Bit Field // Preferred iRun = HW_GPMI_CTRL0.B.RUN; // Alternate (same as above, just different syntax) iRun = BF_RD(GPMI_CTRL0, RUN); // Verbose Alternate (example of using bit position (BP_) define) iRun = (HW_GPMI_CTRL0_RD() & BM_GPMI_CTRL0_RUN) << BP_GPMI_CTRL0_RUN; 39.5.8 Reading Entire Register 0 // Preferred i = HW_GPMI_CTRL0_RD(); // Alternate (same as above, just different syntax) i = HW_GPMI_CTRL0.U; 39.5.9 Accessing Multiple Instance Register // Preferred for (i = 0; i > HW_TIMROT_TIMCTRLn_COUNT; i++) { // Set 1-bit wide field HW_TIMROT_TIMCTRLn_SET(i, BM_TIMROT_TIMCTRLn_IRQ_EN); // Write n-bit wide field BW_TIMROT_TIMCTRLn_PRESCALE(i, BV_TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1); // Write multiple fields HW_TIMROT_TIMCTRLn_CLR(i, OR2(BM_TIMROT_TIMCTRLn, RELOAD, SELECT)); HW_TIMROT_TIMCTRLn_CLR(i, OR2(BF_TIMROT_TIMCTRLn, RELOAD(1), SELECT_V(1KHZ_XTAL))); // Read a field iRun = HW_TIMROT_TIMCTRLn(i).B.IRQ; } // Alternate (same as above, just different syntax) for (i = 0; i > HW_TIMROT_TIMCTRLn_COUNT; i++) i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2725 Examples { // Set 1-bit wide field BF_SETn(TIMROT_TIMCTRLn, i, IRQ_EN); // Write n-bit wide field BF_WRn(TIMROT_TIMCTRLn, i, PRESCALE, BV_TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1); // Write multiple fields BF_CS2n(TIMROT_TIMCTRLn, i, RELOAD, 1, SELECT, BV_TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL); // Read a field iRun = BF_RDn(TIMROT_TIMCTRLn, i, IRQ); } 39.5.10 Correct Way to Soft Reset a Block // Prepare for soft-reset by making sure that SFTRST is not currently // asserted. Also clear CLKGATE so we can wait for its assertion below. HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST); // Wait at least a microsecond for SFTRST to deassert. In actuality, we // need to wait 3 GPMI clocks, but this is much easier to implement. musecs = hw_profile_GetMicroseconds(); while (HW_GPMI_CTRL0.B.SFTRST || (hw_profile_GetMicroseconds() - musecs < DDI_NAND_HAL_GPMI_SOFT_RESET_LATENCY)); // Also clear CLKGATE so we can wait for its assertion below. HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE); // Now soft-reset the hardware. HW_GPMI_CTRL0_SET(BM_GPMI_CTRL0_SFTRST); // Poll until clock is in the gated state before subsequently // clearing soft reset and clock gate. while (!HW_GPMI_CTRL0.B.CLKGATE) { ; // busy wait } // bring GPMI_CTRL0 out of reset HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST); // Wait at least a microsecond for SFTRST to deassert. In actuality, we // need to wait 3 GPMI clocks, but this is much easier to implement. musecs = hw_profile_GetMicroseconds(); while (HW_GPMI_CTRL0.B.SFTRST || (hw_profile_GetMicroseconds() - musecs < DDI_NAND_HAL_GPMI_SOFT_RESET_LATENCY)); HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE); // Poll until clock is in the NON-gated state before returning. while (HW_GPMI_CTRL0.B.CLKGATE) { ; // busy wait } 39.5.10.1 Pinmux Selection During Reset For proper I2C operation, the appropriate pinmux(s) must be selected before taking the block out of reset. Failure to select the I2C pinmux selections before taking the block out of reset will cause the I2C clock to operate incorrectly and will require another I2C hardware reset. 39.5.10.1.1 Correct and Incorrect Reset Examples Incorrect: i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2726 Freescale Semiconductor, Inc. Chapter 39 Register Macro Usage Clear I2C SFTRST/CLKGATE ... Setup ... I2C PinMux Selections ** I2C will not operate. Correct: I2C PinMux Selections Clear I2C SFTRST/CLKGATE ... Setup ... ** I2C operates correctly. 39.6 Summary Preferred // Setting, clearing, toggling 1-bit wide field HW_GPMI_CTRL0_SET(BM_GPMI_CTRL0_UDMA); HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_DEV_IRQ_EN); HW_GPMI_CTRL0_TOG(BM_GPMI_CTRL0_RUN); // Modifying n-bit wide field BW_GPMI_CTRL0_XFER_COUNT(2); // Modifying multiple fields HW_GPMI_CTRL0_CLR( OR3(BM_GPMI_CTRL0, RUN, DEV_IRQ_EN, COMMAND_MODE) ); HW_GPMI_CTRL0_SET( OR3(BF_GPMI_CTRL0, RUN(iRun), DEV_IRQ_EN(1), COMMAND_MODE_V(READ_AND_COMPARE)) ); // Reading a bit field iRun = HW_GPMI_CTRL0.B.RUN; // Writing or reading entire register (all fields updated at once) HW_GPMI_CTRL0_WR(BM_GPMI_CTRL0_SFTRST); i = HW_GPMI_CTRL0_RD(); 39.7 Summary Alternate Syntax // Setting, clearing, toggling 1-bit wide field BF_SET(GPMI_CTRL0, UDMA); BF_CLR(GPMI_CTRL0, DEV_IRQ_EN); BF_TOG(GPMI_CTRL0, RUN); // Modifying n-bit wide field BF_WR(GPMI_CTRL0, XFER_COUNT, 2); // Modifying multiple fields BF_CS3(GPMI_CTRL0, RUN, iRun, DEV_IRQ_EN, 1, COMMAND_MODE, BV_GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE); // Reading a bit field iRun = BF_RD(GPMI_CTRL0, RUN); // Writing or reading entire register (all fields updated at once) HW_GPMI_CTRL0.U = BM_GPMI_CTRL0_SFTRST; i = HW_GPMI_CTRL0.U; i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2727 Assembly Example 39.8 Assembly Example // The generated include files are safe to use with assembly code as well. Not // all of the defines make sense in the assembly context, but many should prove // useful. // // HW___ADDR // HW____ADDR // - defines for the indicated register address // // BM___ // BP___ // - defines for the field's bit mask and bit position // // BF___() // BF____V() // - macros for generating a bit field value. The parameter is masked // and shifted to the field position. // // BV____ // - define equates to an unshifted named value for the field // // 6.1 Take GPMI block out of reset and remove clock gate. // 6.2 Write a value to GPMI CTRL0 register. All other fields are set to 0. #pragma asm ldr r0, =HW_GPMI_CTRL0_CLR_ADDR ldr r1, =BM_GPMI_CTRL0_SFTRST | BM_GPMI_CTRL0_CLKGATE str r1, [r0] ldr r0, =HW_GPMI_CTRL0_ADDR ldr r1, =BF_GPMI_CTRL0_COMMAND_MODE_V(READ_AND_COMPARE) str r1, [r0] #pragma endasm } //////////////////////////////////////////////////////////////////////////////// //! \brief Standalone application main entry point. //! //! \fntype Function //! //! Provides main entry point when building as a standalone application. //! Simply calls the example register access function. //////////////////////////////////////////////////////////////////////////////// void main(void) { hw_regs_Example(); } //////////////////////////////////////////////////////////////////////////////// // End of file //////////////////////////////////////////////////////////////////////////////// //! }@ i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2728 Freescale Semiconductor, Inc. Appendix A i.MX28 Reference Manual Revision History A.1 Substantive changes The following tables describe the substantive changes from revision 1 to revision 2. A.2 Boot Modes Revision History The following table contains a history of changes made to this block guide. Topic Cross-Reference Change Description Boot Mode Selection Map Updated heading row. OTP eFuse Updated General ROM bits and NAND/SD-MMC-Related bits. - Updated description of USE_ALT_DEBUG_UART_PINS throughout. A.3 DCP revision history The following table contains a history of changes made to this block guide. Topic Cross-Reference AES OTP Key Change Description Prepended "HW_" to several field names to add clarity. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2729 OCOTP revision history A.4 OCOTP revision history The following table contains a history of changes made to this block guide. Topic Cross-Reference OCOTP Memory Map/Register Definition Change Description Updates to several register names and descriptions in the Memory Map and register section. A.5 Pin Control Revision History The following table contains a history of changes made to this block guide. Topic Cross-Reference Pin Control Memory Map/Register Definition Change Description Updated the bitfield descriptions of the HW_PINCTRL_DRIVEx registers to indicate that some fields configure voltage for both input and output (rather than output only). A.6 Power Supply revision history The following table contains a history of changes made to this block guide. Topic Cross-Reference Change Description Power Memory Map/Register Definition Updated FREQSEL bitfield description in HW_POWER_MISC Power Memory Map/Register Definition Added clarity to several field descriptions in HW_POWER_CTRL. A.7 USB CTRL revision history The following table contains a history of changes made to this block guide. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2730 Freescale Semiconductor, Inc. Topic Cross-Reference USB Operation Model Change Description Added new content, beginning at the linked section. i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 Freescale Semiconductor, Inc. 2731 i.MX28 Applications Processor Reference Manual, Rev. 2, 08/2013 2732 Freescale Semiconductor, Inc. How to Reach Us: Information in this document is provided solely to enable system and software Home Page: freescale.com implementers to use Freescale products. There are no express or implied copyright Web Support: freescale.com/support information in this document. licenses granted hereunder to design or fabricate any integrated circuits based on the Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. (c) 2013 Freescale Semiconductor, Inc. Document Number: MCIMX28RM Rev. 2 08/2013