DM74LS670M - National Semiconductor

TL/F/6436

54LS670/DM54LS670/DM74LS670 TRI-STATE 4-by-4 Register Files

June 1989

54LS670/DM54LS670/DM74LS670

TRI-STATEÉ4-by-4 Register Files

General Description

These register files are organized as 4 words of 4 bits each,

and separate on-chip decoding is provided for addressing

the four word locations to either write-in or retrieve data.

This permits writing into one location, and reading from an-

other word location, simultaneously.

Four data inputs are available to supply the word to be

stored. Location of the word is determined by the write se-

lect inputs A and B, in conjunction with a write-enable sig-

nal. Data applied at the inputs should be in its true form.

That is, if a high level signal is desired from the output, a

high level is applied at the data input for that particular bit

location. The latch inputs are arranged so that new data will

be accepted only if both internal address gate inputs are

high. When this condition exists, data at the D input is trans-

ferred to the latch output. When the write-enable input, GW,

is high, the data inputs are inhibited and their levels can

cause no change in the information stored in the internal

latches. When the read-enable input, GR, is high, the data

outputs are inhibited and go into the high impedance state.

The individual address lines permit direct acquisition of data

stored in any four of the latches. Four individual decoding

gates are used to complete the address for reading a word.

When the read address is made in conjunction with the

read-enable signal, the word appears at the four outputs.

This arrangementÐdata entry addressing separate from

data read addressing and individual sense line Ð eliminates

recovery times, permits simultaneous reading and writing,

and is limited in speed only by the write time (27 ns typical)

and the read time (24 ns typical). The register file has a non-

volatile readout in that data is not lost when addressed.

All inputs (except read enable and write enable) are buff-

ered to lower the drive requirements to one normal Series

54LS/74LS load, and input clamping diodes minimize

switching transients to simplify system design. High speed,

double ended AND-OR-INVERT gates are employed for the

read-address function and have high sink current, TRI-

STATE outputs. Up to 128 of these outputs may be wire-

AND connected for increasing the capacity up to 512 words.

Any number of these registers may be paralleled to provide

n-bit word length.

Features

YAlternate Military/Aerospace device (54LS670) is avail-

able. Contact a National Semiconductor Sales Office/

Distributor for specifications.

YFor use as:

Scratch pad memory

Buffer storage between processors

Bit storage in fast multiplication designs

YSeparate read/write addressing permits simultaneous

reading and writing

YOrganized as 4 words of 4 bits

YExpandable to 512 words of n-bits

YTRI-STATE versions of DM54LS170/DM74LS170

YFast access times 20 ns typ

Connection Diagram

Dual-In-Line Package

TL/F/6436–1

Order Number 54LS670DMQB, 54LS670FMQB,

54LS670LMQB, DM54LS670J, DM54LS670W,

DM74LS670M or DM74LS670N

See NS Package Number E20A,

J16A, M16A, N16A or W16A

Function Tables

WRITE TABLE (SEE NOTES A, B, AND C)

Write Inputs Word

WBWAGW0123

LLLQ

LHL Q

HLL Q

HHL Q

XXH Q

READ TABLE (SEE NOTES A AND D)

Read Inputs Outputs

RBRAGRQ1 Q2 Q3 Q4

L L L WOB1 WOB2 WOB3 WOB4

L H L W1B1 W1B2 W1B3 W1B4

H L L W2B1 W2B2 W2B3 W2B4

H H L W3B1 W3B2 W3B3 W3B4

XXH Z Z Z Z

Note A: HeHigh Level, L eLow Level, X eDon’t Care, Z eHigh

Impedance (Off).

Note B: (Q eD) eThe four selected internal flip-flop outputs will assume

the states applied to the four external data inputs.

Note C: Q0eThe level of Q before the indicated input conditions were

established.

Note D: WOB1 eThe first bit of word 0, etc.

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range

DM54LS and 54LS b55§Ctoa

125§C

DM74LS 0§Ctoa

70§C

Storage Temperature Range b65§Ctoa

150§C

Note:

The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device cannot be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation.

Recommended Operating Conditions

Symbol Parameter DM54LS670 DM74LS670 Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.7 0.8 V

IOH High Level Output Current b1b2.6 mA

IOL Low Level Output Current 12 24 mA

tWWrite Enable Pulse Width 25 25 ns

(Note 3)

tSU Setup Time Data 10 10 ns

(Notes1&3) W

B15 15

tHHold Time Data 15 15 ns

(Notes1&3) W

B55

LATCH Latch Time for New Data 25 25 ns

(Notes2&3)

AFree Air Operating b55 125 0 70 §C

Temperature

Note 1: Times are with respect to the Write-Enable input. Write-Select time will protect the data written into the previous address. If protection of data in the

previous address, tSETUP (WA,W

) can be ignored. As any address selection sustained for the final 30 ns of the Write-Enable pulse and during tH(WA,W

) will

result in data being written into that location. Depending on the duration of the input conditions, one or a number of previous addresses may have been written into.

Note 2: Latch time is the time allowed for the internal output of the latch to assume the state of new data. This is important only when attempting to read from a

location immediately after that location has received new data.

Note 3: TAe25§C and VCC e5V.

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

VIInput Clamp Voltage VCC eMin, IIeb

18 mA b1.5 V

VOH High Level Output Voltage VCC eMin, IOH eMax 2.4 3.4 V

VIL eMax, VIH eMin

VOL Low Level Output Voltage VCC eMin, IOL eMax DM54 0.25 0.4 V

IOL eMax, VIH eMin DM74 0.34 0.5

IIInput Current @Max VCC eMax D, R or W 0.1

Input Voltage VIe7V GW0.2 mA

GR0.3

IIH High Level Input Current VCC eMax D, R or W 20

VIe2.7V GW40 mA

GR60

Electrical Characteristics

over recommended operating free air temperature (unless otherwise noted) (Continued)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

IIL Low Level Input Current VCC eMax D, R, or W b0.4

VIe0.4V GWb0.8 mA

GRb1.2

IOZH Off-State Output Current VCC eMax, VOe2.7V

with High Level Output VIH eMin, VIL eMax 20 mA

Voltage Applied

IOZL Off-State Output Current VCC eMax, VOe0.4V

with Low Level Output VIH eMin, VIL eMax b20 mA

Voltage Applied

IOS Short Circuit VCC eMax DM54 b20 b100 mA

Output Current (Note 2) DM74 b20 b100

ICC Supply Current VCC eMax (Note 3) 30 50 mA

Switching Characteristics at VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load)

RLe667X

Symbol Parameter From (Input) CLe45 pF CLe150 pF Units

To (Output)

Min Max Min Max

tPLH Propagation Delay Time Read Select 40 50 ns

Low to High Level Output to Q

tPHL Propagation Delay Time Read Select 45 55 ns

High to Low Level Output to Q

tPLH Propagation Delay Time Write Enable 45 55 ns

Low to High Level Output to Q

tPHL Propagation Delay Time Write Enable 50 60 ns

High to Low Level Output to Q

tPLH Propagation Delay Time Data 45 55 ns

Low to High Level Output to Q

tPHL Propagation Delay Time Data 40 50 ns

High to Low Level Output to Q

tPZH Output Enable Time Read Enable 35 45 ns

to High Level Output to Any Q

tPZL Output Enable Time Read Enable 40 50 ns

to Low Level Output to Any Q

tPHZ Output Disable Time from Read Enable 50 ns

High Level Output (Note 4) to Any Q

tPLZ Output Disable Time from Read Enable 35 ns

Low Level Output (Note 4) to Any Q

Note 1: All typicals are at VCC e5V, TAe25§C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICC is measured with 4.5V applied to all DATA inputs and both ENABLE inputs, all ADDRESS inputs are grounded and all outputs are open.

Note 4: CLe5 pF.

Logic Diagram

TL/F/6436–2

Physical Dimensions inches (millimeters)

Ceramic Leadless Chip Carrier Package (E)

Order Number 54LS670LMQB

NS Package Number E20A

16-Lead Ceramic Dual-In-Line Package (J)

Order Number 54LS670DMQB or DM54LS670J

NS Package Number J16A

Physical Dimensions inches (millimeters) (Continued)

16-Lead Small Outline Molded Package (M)

Order Number DM74LS670M

NS Package Number M16A

16-Lead Molded Dual-In-Line Package (N)

Order Number DM74LS670N

NS Package Number N16E

54LS670/DM54LS670/DM74LS670 TRI-STATE 4-by-4 Register Files

Physical Dimensions inches (millimeters) (Continued)

16-Lead Ceramic Flat Package (J)

Order Number 54LS670FMQB or DM54LS670W

NS Package Number W16A

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