Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
http://www.cirrus.com
CS5461A
Single Phase, Bi-directional Power/Energy IC
Features
• Energy Data Linearity: ±0.1% of Reading over
1000:1 Dynamic Range
• On-chip Functions:
-Instantaneous Voltage, Current, and Power
-IRMS and VRMS, Apparent and Active (Real) Power
-Energy-to-pulse Conversion for Mechanical
Counter/Stepper Motor Drive
-System Calibrations and Phase Compensation
-Temperat ur e Sen s o r
-Voltage Sag Detect
• Meets Accuracy Spec for IEC, ANSI, & JIS.
• Low Power Consumption
• Current Input Optimized for Sense Resistor.
• GND-referenced Signals with Single Supply
• On-chip 2.5 V Reference (25 ppm/°C typ)
• Power Supply Monitor
• Simple Three-wire Digital Serial Interface
• “Auto-boot” Mode from Serial E2PROM.
• Power Supply Configurations:
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
Description
The CS5461A is an integrated power measure-
ment device which combines two
analog-to-digital converters, power calculation
engine, energy-to-frequency converter, and a
serial interface on a single chip . It is de sign ed to
accurately measure instantaneous current and
voltage, and calculate VRMS, IRMS, instanta-
neous power, apparent power, and active power
for single-phase, 2- or 3-wire power metering
applications.
The CS5461A is optimized to interface to shunt
resistors or current transformers for current mea-
surement, and to resistive dividers or potential
transformers for voltage measurement.
The CS5461A features a bi-directional serial in-
terface for comm un ica tio n with a pro ce sso r, an d
a programmable energy-to-pulse output func-
tion. Additional features include on-chip
functionality to facilitate syste m-level calibration ,
temperature sensor, voltage sag detection, and
phase compensation.
ORDERING INFORMATION:
See Page 43.
VA+ VD+
IIN+
IIN-
VIN+
VIN-
VREFIN
VREFOUT
AGND XIN XOUT CPUCLK DGND
CS
SDO
SDI
SCLK
INT
Voltage
Reference System
Clock /K Clock
Generator
Serial
Interface
E-to-F
Power
Monitor
PFMON
x1
RESET
Digital
Filter
Calibration
MODE
Power
Calculation
Engine
4th Order
Modulator
2nd Order
Modulator
Temperature
Sensor
Digital
Filter
PGA
HPF
Option
HPF
Option
E1
E2
E3
x10
APR ‘11
DS661F3
CS5461A
2DS661F3
TABLE OF CONTENTS
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.1 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.2 Voltage and Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.3 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.4 Linearity Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1.1 Voltage Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.1.2 Current Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.2 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.3 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.4 Energy Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.4.1 Normal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5.4.2 Alternate Pulse Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.4.3 Mechanical Counter Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.4.4 Stepper Motor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.4.5 Pulse Output E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.4.6 Anti-creep for the Pulse Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.4.7 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.5 Voltage Sag-detect Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.6 No Load Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.7 On-chip Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.8 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.9 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.10 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.12 Event Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.12.1 Typical Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.13 Serial Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.13.1 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.14 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6. Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6.1 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6.2 Current and Voltage DC Offset Register ( IDCoff ,VDCoff ) . . . . . . . . . . . . . . . . . . . .27
CS5461A
DS661F3 3
6.3 Current and Voltage Gain Register ( Ign ,Vgn ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.4 Cycle Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.5 PulseRateE1,2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.6 Instantaneous Current, Voltage and Power Registers ( I , V , P ) . . . . . . . . . . . . . .28
6.7 Active (Real) Power Registers ( PActive ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.8 IRMS and VRMS Registers ( IRMS , VRMS ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.9 Power Offset Register ( Poff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.10 Status Register and Mask Register ( Status , Mask ) . . . . . . . . . . . . . . . . . . . . . .29
6.11 Current and Voltage AC Offset Register ( VACoff , IACoff ) . . . . . . . . . . . . . . . . . . .30
6.12 PulseRateE3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.13 Temperature Register ( T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.14 System Gain Register ( SYSGain ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.15 Pulsewidth Register ( PW ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.16 E3 Pulse Width Register ( PulseWidth ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.17 Voltage Sag Duration Register ( VSAGDuration ) . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.18 Voltage Sag Level Register ( VSAGLevel ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.19 No Load Threshold Interval Register ( LoadIntv) . . . . . . . . . . . . . . . . . . . . . . . . . .32
6.20 No Load Threshold ( LoadMin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
6.21 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.22 Temperature Gain Register ( TGain ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.23 Temperature Offset Register ( Toff ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.24 Apparent Power Register ( S ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1 Channel Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1.1 Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1.1.1 Duration of Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1.2 Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1.2.1 DC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1.2.2 AC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7.1.3 Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7.1.3.1 AC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
7.1.3.2 DC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
7.1.4 Order of Calibration Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
7.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
7.3 Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
8. Auto-boot Mode Using E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
8.1 Auto-Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
8.2 Auto-Boot Data for E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
8.3 Suggested E2PROM Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
9. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
10. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
12. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . . . .43
13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
CS5461A
4DS661F3
LIST OF FIGURES
Figure 1. CS5461A Read and Write Timing Diagrams ........................................................................... 11
Figure 2. Data Flow.................................................................................................................................13
Figure 3. Normal Format on pulse outputs E1 and E2............................................................................16
Figure 4. Alternate Pulse Format on E1 and E2.....................................................................................17
Figure 5. Mechanical Counter Format on E1 and E2..............................................................................17
Figure 6. Stepper Motor Format on E1 and E2.......................................................................................18
Figure 7. Voltage Sag Detect..................................................................................................................19
Figure 8. Oscillator Connection...............................................................................................................20
Figure 9. Calibration Data Flow............................................................................................................... 35
Figure 10. System Calibration of Offset..................................................................................................35
Figure 11. System Calibration of Gain ....................................................................................................36
Figure 12. Example of AC Gain Calibration............................................................................................36
Figure 13. Another Example of AC Gain Calibration ..............................................................................36
Figure 14. Typical Interface of E2PROM to CS5461A ............................................................................38
Figure 15. Typical Connection Diagram (Single-phase, 2-wire – Direct Connect to Power Line)...........39
Figure 17. Typical Connection Diagram (Single-phase, 3-wire).............................................................. 40
Figure 16. Typical Connection Diagram (Single-phase, 2-wire – Isolated from Power Line)..................40
Figure 18. Typical Connection Diagram (Single-phase, 3-wire – No Neutral Available).........................41
LIST OF TABLES
Table 1. Current Channel PGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2. E1 and E2 Pulse Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CS5461A
DS661F3 5
1. OVERVIEW
The CS5461A is a CMOS monolithic power measurement device with a computation engine and an en-
ergy-to-frequency pulse output. The CS5461A combines a programmable-gain amplifier, two ana-
log-to-digital converters (ADCs), system calibration and a computation engine on a single chip.
The CS5461A is designed for power measurement applications and is optimized to interface to a cur-
rent-sense resistor or transformer for current measurement, and to a resistive divider or potential trans-
former for voltage measurement. The voltage and current channels provide programmable gains to
accommodate various input levels from a wide variety of sensing elements. With single +5 V supply on
VA+/AGND, both of the CS5461A’s input channels can accommodate common mode as well as signal
levels between (AGND - 0.25 V) and VA+.
Additionally, the CS5461A is equipped with a computation engine that calculates IRMS, VRMS, apparent
power and active (real) power. To facilitate communication to a microprocessor, the CS5461A includes a
simple three-wire serial interface which is SPI™ and Microwire™ compatible. The CS5461A provides
three outputs for energy registration. E1 and E2 are designed to directly drive a mechanical counter or
stepper motor, or interface to a microprocessor. The pulse output E3 is designed to assist with meter cal-
ibration.
CS5461A
6DS661F3
2. PIN DESCRIPTION
Clock Generator
Crystal Out
Crystal In 1,24 XOUT, XIN - The output and input of an inverting amplifier . Oscillation occurs when connected to
a crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to
the XIN pin to provide the system clock for the device.
CPU Clock Output 2CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
Control Pins and Serial Data I/O
Serial Clock Input 5SCLK - A Schmitt Trigger input pin. Clocks data from the SDI pin into the receive buffer and out of
the transmit buffer onto the SDO pin when CS is low.
Serial Data Output 6SDO -Serial port data output pin.SDO is forced into a high impedance state when CS is high.
Chip Select 7CS - Low, activates the serial port interface.
Mode Select 8MODE - High, enables the “auto-boot” mode. The mode pin is pulled low by an internal resistor.
High Frequen cy Energy
Output 18 E3 - Active low pulses with an output frequency proportional to the active power. Used to assist
in system calibration.
Reset 19 RESET - A Schmitt Trigger input pin. Low activates Reset, all internal registers (some of which
drive output pins) are set to their default states.
Interrupt 20 INT - Low, indicates that an enabled event has occurred.
Energy Output 21,22 E1, E2 - Active low pulses with an output frequency proportional to the active power. Indicates if
the measured energy is negative.
Serial Data Input 23 SDI - Serial port data input pin. Data will be input at a rate determined by SCLK.
Analog Inputs/Outputs
Differential Voltage Inputs 9,10 VIN+, VIN- - Differential analog input pins for the voltage channel.
Differential Current Inputs 15,16 IIN+, IIN- - Differential analog input pins for the current channel.
Voltage Reference Output 11 VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magni-
tude of 2.5 V and is referenced to the AGND pin on the converter.
Voltage Reference Input 12 VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator.
Power Supply Connections
Positive Digital Supply 3VD+ - The positive d igital supply.
Digital Ground 4DGND - Digital Ground.
Positive Analog Supply 14 VA+ - The positive analog supply.
Analog Ground 13 AGND - Analog ground.
Power Fail Monitor 17PFMON - The power fail monitor pin monitors the analog supply. If PFMON’s voltage threshold is
not met, a Low-Supply Detect (LSD) bit is set in the status register.
VREFIN 12Voltage Reference Input VREFOUT 11Voltage Reference Output VIN- 10Differential Voltage Input VIN+ 9Differential Voltage Input MODE 8Mode Select CS 7C h ip S e le c t SDO 6Se ria l Data O u p ut SCLK 5Serial Clock DGND 4Digital Ground VD+ 3Po s itiv e Digita l S u pp l y CPUCLK 2CPU Clock Output XOUT 1Crystal Out
AGND13 Analog G round
VA+14 Positive Analog S upp ly
IIN-15 Differential Current Input
IIN+16 Differential Current Input
PFMON17 Power F a il Monito r
E318 High Freq uency Energ y O utput
RESET19 Reset
INT20 Interrupt
E121 Energy Output 1
22 SDI23 Serial Data Input
XIN24 Crystal In
E2 Energy Output 2
CS5461A
DS661F3 7
3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ANALOG CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VR EFIN = +2.5 V. All voltages with respect to 0 V.
• MCLK = 4.096 MHz.
Parameter Symbol Min Typ Max Unit
Positive Digital Power Supply VD+ 3.135 5.0 5.25 V
Positive Analog Power Supply VA+ 4.75 5.0 5.25 V
Voltage Reference VREFIN - 2.5 - V
Specifie d Temperature Rang e TA-40 - +85 °C
Parameter Symbol Min Typ Max Unit
Linearity Performance
Active Power Accuracy (All Gain Ranges )
(Note 1) Input Range 0.1% - 100% PActive -±0.1- %
Current RMS Accuracy (All Gain Ranges)
(Note 1) Input Range 0.2% - 100%
Input Range 0.1% - 0.2% IRMS -
-±0.2
±1.5 -
-%
%
Voltage RMS Accuracy (All Gain Ranges)
(Note 1) Input Range 5% - 100% VRMS -±0.1- %
Analog Inputs (Both Channels)
Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB
Common Mode + Signal (All Gain Ranges) -0.25 - VA+ V
Analog Inputs (Current Channel)
Differential Input Range (Gain = 10)
[(IIN+) - (IIN-)] (Gain = 50) IIN -
-500
100 -
-mVP-P
mVP-P
Total Harmonic Distortion (Gain = 50) THD 80 94 - dB
Crosstalk wi th Voltage Channel at Full Scale (50, 60 Hz) - -115 - dB
Input Capacitance (Gain = 10)
(Gain = 50) IC -
-32
52 -
-pF
pF
Effective Input Impedance EII 30 - - k
Noise (Referred to Input) (Gain = 10)
(Gain = 50) NI-
-22.5
4.5 -
-µVrms
µVrms
Offset Drift (Without the high-pass filter) OD - 4.0 - µV/°C
Gain Error (Note 2) GE - ±0.4 %
Analog Inputs (V oltage Channel)
Differential Input Range {(VIN+) - (VIN-)} VIN -500-mV
P-P
Total Harmonic Distortion THD 65 75 - dB
Crosstalk with Current Channel at Full Scale (50, 60 Hz) - -70 - dB
Input Capacitance All Gain Ranges IC - 0.2 - pF
Effective Input Impedance EII 2 - - M
Noise (Referred to Input) NV-140-µV
rms
Offset Drift (Without the high-pass Filter) OD - 16.0 - µV/°C
Gain Error (Note 2) GE - ±3.0 %
CS5461A
8DS661F3
ANALOG CHARACTERISTICS (Continued)
1. Applies when the HPF option is enabled.
2. Applies before system calibration.
3. All outputs unloaded. All inputs CMOS level.
4. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (ze ro -to -p ea k) (60 Hz)
sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input
channels are shorted to AGND. Then the CS5461A is commanded to continuous conversion acquisition mode, and
digital output data is collected for the channel under test. The (zero-to-peak) value of the digi tal sinusoidal output
signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured
in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output.
This voltage is then defin ed as Veq. PSRR is then (in dB):
5. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.
6. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at
which the LSD bit can be permanently reset back to 0.
VOLTAGE REFERENCE
Notes: 7. The voltage at VREFOUT is measured across the temperature range. From these measurements the following
formula is used to calculate the VREFOUT Temperature Coefficient:.
8. Specified at maximum recommended output of 1 µA, source or sink.
Parameter Symbol Min Typ Max Unit
Temperature Channel
Temperature Accuracy T - ±5 - °C
Power Supplies
Power Supply Currents (Active State) IA+
ID+ (VA+ = VD+ = 5 V)
ID+ (VA+ = 5 V, VD+ = 3.3 V)
PSCA
PSCD
PSCD
-
-
-
1.1
2.9
1.7
-
-
-
mA
mA
mA
Power Consumption Active State (VA+ = VD+ = 5 V)
(Note 3) Active State (VA+ = 5 V, VD+ = 3.3 V)
Stand-By State
Sleep State
PC
-
-
-
-
21
12
8
10
28
16.5
-
-
mW
mW
mW
µW
Power Supply Rejection Ratio (DC, 50 and 60 Hz)
(Note 4) Voltage Channel
Current Channel PSRR 45
70 65
75 -
-dB
dB
PFMON Low-voltage Trigger Threshold (Note 5) PMLO 2.3 2.45 - V
PFMON High-voltage Power-On Trip Point (Note 6) PMHI - 2.55 2.7 V
Parameter Symbol Min Typ Max Unit
Reference Output
Output Voltage VREFOUT +2.4 +2.5 +2.6 V
Temperature Coefficient (Note 7) TCVREF - 25 60 ppm/°C
Load Regulation (Note 8) VR-610mV
Reference Input
Input Voltage Range VREFIN +2.4 +2.5 +2.6 V
Input Capacitance - 4 - pF
Input CVF Current - 25 - nA
PSRR 20 150
Veq
----------
log=
(VREFOUTMAX - VREFOUTMIN)
VREFOUTAVG
(
(
1
TAMAX - TAMIN
(
(
1.0 x 10
(
(
6
TCVREF =
CS5461A
DS661F3 9
DIGITAL CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respe c t to 0 V.
• MCLK = 4.096 MHz.
Notes: 9. All measurements performed under static conditions.
10. If a crystal is used, then XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used,
XIN frequency range is 2. 5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5 .0 MHz.
11. If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.
12. The frequen cy of CPUCLK is equal to MCLK.
13. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the
full-scale signal applied to the channel input.
14. Configuration Register bits PC[6:0] are set to “0000000”.
15. The MODE pin is pulled low by an internal resistor.
Parameter Symbol Min Typ Max Unit
Master Clock Characteristics
Master Clock Frequency Internal Gate Oscillator (Note 10) MCLK 2.5 4.096 20 MHz
Master Clock Duty Cycle 40 - 60 %
CPUCLK Duty Cycle (Note 11 and 12) 40 60 %
Filter Characteristics
Phase Compensation Range (Voltage Channel, 60 Hz) -2.8 - +2.8 °
Input Sampling Rate DCLK = MCLK/K - DCLK/8 - Hz
Digital Filter Output W ord Rate (Both Channels) OWR - DCLK/1024 - Hz
High-pass Filter Corner Frequency -3 dB - 0.5 - Hz
Full Scale Calibration Range (Referred to Input) (Note 13) FSCR 25 - 100 %F.S.
Channel-to-channel Time-shift Error (Note 14) 1.0 µs
Input/Output Characteristics
High-level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIH 0.6 VD+
(VD+) - 0.5
0.8VD+
-
-
-
-
-
-
V
V
V
Low-level Input Voltage (VD = 5 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIL -
-
-
-
-
-
0.8
1.5
0.2VD+
V
V
V
Low-level Input Volt age (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIL -
-
-
-
-
-
0.48
0.3
0.2VD+
V
V
V
High-level Output Voltage Iout = +5 mA VOH (VD+) - 1.0 - - V
Low-level Output Voltage Iout = -5 mA VOL --0.4V
Input Leakage Curren t (Note 15) Iin -±1±10µA
3-state Leakage Current IOZ --±10µA
Digital Output Pin Capacitance Cout -5-pF
CS5461A
10 DS661F3
SWITCHING CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Condition s.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
• Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Notes: 16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
17. Oscillator start- up time varies with crystal parameters. This specificat ion does not apply when using an externa l
clock source.
Parameter Symbol Min Typ Max Unit
Rise Times Any Digital Input Except SCLK
(Note 16) SCLK
Any Digital Output
trise -
-
-
-
-
50
1.0
100
-
µs
µs
ns
Fall Times Any Digital Inpu t Except SCLK
(Note 16) SCLK
Any Digital Output
tfall -
-
-
-
-
50
1.0
100
-
µs
µs
ns
Start-up
Oscillator Start-Up Time XTAL = 4.096 MHz (Note 17) tost -60-ms
Serial Port Timing
Serial Clock Frequency SCLK - - 2 MHz
Serial Clock Pulse Width High
Pulse Width Low t1
t2
200
200 -
--
-ns
ns
SDI Timing
CS Falling to SCLK Rising t350 - - ns
Data Set-up Time Prior to SCLK Rising t450 - - ns
Data Hold Time After SCLK Rising t5100 - - ns
SDO Timing
CS Falling to SDO Driving t6-2050ns
SCLK Falling to New Data Bit (hold time) t7-2050ns
CS Rising to SDO Hi-Z t8-2050ns
Auto-Boot Timing
Serial Clock Pulse Width Low
Pulse Width High t9
t10
8
8MCLK
MCLK
MODE setup time to RESET Rising t11 50 ns
RESET rising to CS falling t12 48 MCLK
CS falling to SCLK rising t13 100 8 MCLK
SCLK falling to CS rising t14 16 MCLK
CS rising to driving MODE low (to end auto-boot sequence). t15 50 ns
SDO guaranteed setu p time to SCLK rising t16 100 ns
CS5461A
DS661F3 11
t1t2
t3
t4t5
MSB
MSB-1
LSB
MSB
MSB-1
LSB
MSB
MSB-1
LSB
MSB
MSB-1
LSB
Command Tim e 8 SCLK s High Byte M id Byte Low B yte
CS
SCLK
SDI
t10 t9
RESET
SDO
SCLK
CS
Last 8
Bits
SDI
MODE
STOP bit
D a ta from E E PROM
t16 t4t5
t14
t15
t7
t13
t12
t11
(INPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(INPUT)
SDI Write Timing (Not to Scale)
SDO Read Timing (Not to Scale)
Figure 1. CS5461A Read and Write Timin g Diagrams
Auto-Boot Sequence Timing (Not to Scale)
t1t2
MSB
MSB-1
LSB
C om m and Tim e 8 SCLKs SYNC0 or SYNC1
Command S YN C 0 or SY NC 1
Command
MSB
MSB-1
LSB
MSB
MSB-1
LSB
MSB
MSB-1
LSB
Hig h B y te M id Byte L o w Byte
CS
SDO
SCLK
SDI
t6
t7
t8
SYN C 0 or SYNC 1
Command
UNKNOWN
CS5461A
12 DS661F3
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 18. VA+ and AGND must satisfy {(VA+) - (AGND)} + 6.0 V.
19. VD+ and AGND must satisfy {(VD+) - (AGND)} + 6.0 V.
20. Applies to all pins including continuous over-voltage conditions at the analog input pins.
21. Transient current of up to 100 mA will not cause SCR latch-up.
22. Maximum DC input current for a power supply pin is ±50 mA.
23. Total power dissipation, incl uding all input currents and output currents.
Parameter Symbol Min Typ Max Unit
DC Power Supplies (Notes 18 and 19)
Positive Digital
Positive Analog VD+
VA+ -0.3
-0.3 -
-+6.0
+6.0 V
V
Input Current, Any Pin Except Supplies (Notes 20, 21, 22) IIN --±10mA
Output Current, Any Pin Except VREFOUT IOUT --100mA
Power Dissipation (Note 23) PD--500mW
Analog Input Voltage All Analog Pins VINA - 0.3 - (VA+) + 0.3 V
Digital Input Voltage All Digital Pins VIND -0.3 - (VD+) + 0.3 V
Ambient Operating Temperature TA-40 - 85 °C
Storage Temperature Tstg -65 - 150 °C
CS5461A
DS661F3 13
4. THEORY OF OPERATION
The CS5461A is a dual-channel analog-to-digital con-
verter (ADC) followed by a co mputation engine that per-
forms power calculations and energy-to-pulse
conversion. The flow diagr am for the two data paths is
depicted in Figure 2. The analog inputs are structured
with two dedicated channels, voltage and current, then
optimized to simplify interfacing to sensing elements.
The voltage-sensing element introduces a voltage
waveform on the voltage channel inpu t VIN± and is sub-
ject to a gain of 10x. A second-order, delta-sigma mod-
ulator samples the amplified signal for digitization.
Simultaneously, the current-sensing element introduces
a voltage waveform on the current channel input IIN±
and is subject to the two selectable gains of the pro-
grammable gain amplifier (PGA). The amplified signal is
sampled by a fourth-order, delta-sigma modulator for
digitization. Both converters sample at a rate of
MCLK/8, the over-sampling provides a wide dynamic
range and simplified anti-alias filter design.
4.1 Digital Filters
The decimating dig ital filters on both chann els are Sinc3
filters followed by 4th-order, IIR filters. The single-bit
data is passed to the low-pass decimation filter and ou t-
put at a fixed word rate. The output word is passed to
the IIR filter to compensate for the magnitude roll-off of
the low-pass filtering operation.
An optional digital High-pass Filter (HPF in Fi gure 2) re-
moves any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calcu lated active power as we ll. With
both HPFs enabled, the DC component will be removed
from the calculated VRMS and IRMS as well as the appar-
ent power.
When the HPF option is used in only one channel, the
APF (all pass filter) option can be applied to the other
channel to preserve the phase match between the two
channels.
4.2 Voltage and Current Measurements
The digital filter output word is then subject to a DC off-
set adjustment and a gain calibration (See Section 7.
System Calibration on page 35). The calibrated mea-
surement is available to the user by reading the instan-
taneous voltage and current registers.
The Root Mean Square (RMS) calculations are per-
formed on N instantaneous voltage and current sam-
ples, Vn and In respectively (where N is the cycle count),
using the formula:
and likewise for VRMS, using Vn. IRMS and VRMS are ac-
cessible by register reads, which are updated once ev-
ery cycle count (referred to as a compu tational cycle).
4.3 Power Measurements
The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (see Fig-
ure 2). The product is then averaged over N conver-
sions to compute active power and used to drive energy
pulse outputs E1, E2 and E3. Output E3 provides a uni-
form pulse stream that is proportional to the active pow-
er and is designed for system calibratio n.
VOLTAGE SINC3+X
V*
gn
X
V*
CURRENT SINC3+X
I*
gn
DELAY
REG
DELAY
REG
HPF
Option
XI*
RMS
V*
RMS
E1
IIR
I*
IDCoff*
VDCoff*
PGA
IIR
X
+
+
Energy-to-pulseXE3
+
X
+
Configuration Register *
Digital Filter
Digital Filter
HPF
Option
XS*
2nd Order
Modulator
4th Order
Modulator
x10
+
IACoff*
+
+
VACoff*
+
E2
N
÷
N
N
÷
N
P*
Active
N
÷
N
P
off*
P*
X
X
SYSGain*
PC6 PC5 PC4 PC3 PC2 PC1 PC0
6PulseRateE1,2 *
PulseRateE3*Energy-to-pulse
*DENOTES REGISTER NAME.
APF
Option
APF
Option
Figure 2. Data Flow.
IRMS In
n0=
N1–
N
--------------------
=
CS5461A
14 DS661F3
To generate a value for the accumulated active energy
over the last computation cycle, the active power can be
multiplied by the time duration of the computation cycle.
The apparent power is the combination of the active
power and reactive power, without reference to an im-
pedance phase angle, and is calculated by the
CS5461A using the following formula:
The apparen t powe r is reg ister ed on ce eve ry comp uta-
tion cycle.
4.4 Linearity Performance
The linearity of the VRMS, IRMS, and active power mea-
surements (before calibration) will be within ±0.1% of
reading over the ranges specified, with respect to the in-
put voltage levels required to cause full-scale readings
in the IRMS and VRMS registers. Refer to Linearity Per-
formance Specifications on page 7.
Until the CS5461A is calibrated, the accuracy of the
CS5461A (with respect to a reference line-voltage and
line-current level on the power mains) is not guaranteed
to within ±0.1%. See Section 7. System Calibration on
page 35. The accuracy of the internal calculations can
often be improved by selecting a value for the Cycle
Count Register that will cause the time duration of one
computation cycle to be equal to (or very close to) a
whole-number of power-line cycles (and N must be
greater than or eq ual to 4000).
SV
RMS IRMS
=
CS5461A
DS661F3 15
5. FUNCTIONAL DESCRIPTION
5.1 Analog Inputs
The CS5461A is equipped with two fully differential in-
put channels. The inputs VIN and IIN are des i gn at ed
as the voltage and cu rr ent chan ne l inputs, re sp ective ly.
The full-scale differential input voltage for the current
and voltage channel is 250 mVP.
5.1.1 Voltage Channel
The output of the line-voltage resistive divider or trans-
former is connected to the VIN+ and VIN- input pins of
the CS5461A. The voltage channel is equipped with a
10x, fixed-gain amplifier. The full-scale signal level that
can be applied to the voltage channel is 250 mV. If the
input signal is a sine wave the maximum RMS voltage
at a gain 10x is:
which is approximately 70.7% of maximum peak volt-
age. The voltage channel is also equipped with a Volt-
age Gain Register, allowing for an additional
programmable gain of up to 4x.
5.1.2 Current Channel
The output of the current-sense resistor or transformer
is connected to the IIN+ and IIN- input pins of the
CS5461A. To accommodate different current-sensing
elements, the current channel incorporates a Program-
mable Gain Amplifier (PGA) with two progra m ma b le in-
put gains. Configuration Register bit Igain (See Table 1)
defines the two gain selections and corresponding max-
imum input-signal level.
For example, if Igain=0, the current channel’s PGA gain
is set to 10x. If the input si gna ls are p ure sinu soids with
zero phase shift, the maximum peak differential signal
on the current or voltage channel is 250 mVP. The in-
put-signal levels are approximately 70.7% of maximum
peak voltage producing a full-scale energy pulse regis-
tration equal to 50% of absolute maximum ener gy pulse
registration. This will be discussed further in Section 5.4
Energy Pulse Output on page 16.
The Current Gain Register also allows for an additional
programmable gain of up to 4x. If an additional gain is
applied to the voltage and/or curr ent cha nnel, the ma xi-
mum input range should be adjusted accordingly.
5.2 High-pass Filters
By removing the offset from either channel, no error
component will be generated at DC when computing the
active power. By removing the offset from both chan-
nels, no error component will be generated at DC when
computing VRMS, IRMS, and apparent power. Configura-
tion Register bits VHPF and IHPF activate the HPF in
the voltage and current channel respectively.
5.3 Performing Measurements
The CS5461A performs measurements of instanta-
neous voltage (Vn) and current (In), and calculates in-
stantaneous power (Pn) at an Output Word Rate (OWR)
of
where K is the clock divider setting in the Configuration
Register.
The RMS voltage (VRMS), RMS current (IRMS), and ac-
tive power (PActive) are computed using N instanta-
neous samples o f Vn, In and Pn respectively, where N is
the value in the Cycle Count Register (N) and is referred
to as a “computation cycle”. The apparent power (S) is
the product of VRMS and IRMS. A computation cycle is
derived from the master clock (MCLK), with frequency:
Under default conditions & with K = 1, N = 4000, and
MCLK = 4.096 MHz – the OWR = 4000 Hz and the
ComputationCycle= 1Hz.
All measurements are available as a percentage of full
scale. The format for signed registers is a two’s comple-
ment, normalized value between -1 and +1. The format
for unsigned registers is a normalized value between 0
and 1. A register value of
represents the maximum possible value.
At each instantaneous measurement, the CRDY bit will
be set (logic 1) in the Status Regist er, and the INT pin
will become active if the CRDY bit is unmasked in the
Mask Register. At the end of each computation cycle,
the DRDY bit will be set in the Status Register, and the
Igain Maximum Input Range
0±250mV10x
1 ±50 mV 50x
Table 1. Current Channel PGA Configuration
250mVP
2
--------------------- 176.78mVRMS
OWR MCLK K
1024
-----------------------------
=
Computation Cycle OWR
N
---------------
=
223 1–
223
------------------------0.99999988
=
CS5461A
16 DS661F3
INT pin will become active if the DRDY bit is unmasked
in the Mask Register. When these bits are set, they
must be cleared (logic 0) by the user before th ey can be
asserted again.
If the Cycle Count Register (N) is set to 1, all output cal-
culations are instantaneous, and DRDY, like CRDY, will
indicate when instantaneous measurements are fin-
ished. Some calculations are inhibited when the cycle
count is less than 2.
5.4 Energy Pulse Output
The CS5461A provides three output pins for energy reg-
istration. The E1 and E2 pins provide a simple interface
which energy can be registered. These pins are de-
signed to directly connect to a stepper moto r or electro-
mechanical counter. E1 and E2 pins can be set to one
of four pulse outp ut formats, Normal, Alterna te, Stepper
Motor, or Mechanical Counter. Table 2 defines the
pulse output format, which is controlled by bits ALT in
the Configuration Register, and MECH and STEP in the
Control Register.
The E3 pin is designated for system calibration, the
pulse rate can be selected to reach a frequency of
512 kHz.
The pulse output fr equency of E1 and E2 is directly pro-
portional to the active power calculated from the input
signals. To calculate the output frequency on E1 and
E2, the following transfer function can be utilized:
With MCLK = 4.096 MHz, PF = 1, and default settings,
the pulses will have an average frequency equal to the
frequency setting in the PulseRateE1,2 Register when
the input signals applied to the voltage and current
channels cause full- scale readings in the instantaneous
voltage and current registers. When MCLK/K is not
equal to 4.096 MHz, the user should scale the
PulseRateE1,2 Register by a factor of
4.096 MHz /(MCLK /K) to get the actual pulse rate out-
put.
5.4.1 Normal Format
The Normal format is the default. F igure 3 illustrates the
output format on pins E1 and E2. The E1 pin outputs ac-
tive-low pulses with a frequency proportional to the ac-
tive power. The E2 pin is the energy direction indicator.
Positive energy is represented by a pulse on the E1 pin
while the E2 pin remains high. Negative energy is rep-
resented by synchronous pulses on both the E1 pin and
the E2 pin.
The PulseRateE1,2 Register defines the average fre-
quency on output pin E1, when full-scale input signals
are applied to the voltage and current channels. The
maximum pulse frequency from the E1 pin
ALT STEP MECH FORMAT
000 Normal
0 X 1 Mechanical Counter
0 1 0 Stepper Motor
1 X 1 Alternate Pulse
Table 2. E1 and E2 Pulse Output Format
FREQE = Average frequency of E1 and E2 pulses [Hz]
VIN = rms voltage across VIN+ and VIN- [V]
VGAIN = Voltage channel gain
IIN = rms voltage across IIN+ and IIN- [V]
IGAIN = Current channel gain
PF = Power Factor
PulseRateE1,2 = Maximum frequency on E1 and E2 [Hz]
VREFIN = Voltage at VREFIN pin [V]
FREQEVIN VGAINIINIGAIN PFPulseRateE12,
VREFIN2
------------------------------------------------------------------------------------------------------------------------------------------------=
E1
Po sitive E nergy Bu rst N egative Energy Burst
. . .
. . .
. . .
. . .
E2
tdur
Figure 3. Normal Format on pulse outputs E1 and E2
CS5461A
DS661F3 17
is (MCLK/K)/16. The pu lse duration (tdur) is an integer
multiple of MCLK cycles, approximately equal to:
The maximum pulse du ration (tdur) is de termined by th e
sampling rate and the minimum is defined by the maxi-
mum pulse frequency. The tdur limits are:
The Pulse Width Re gister (PW) does not affect the nor-
mal format.
5.4.2 Alternate Pulse Format
Setting bits MECH = 1 and STEP = 0 in the Control
Register and ALT = 1 in the Configuration Register con-
figures the E1 and E2 pins for alternating pulse format
output (see Figure 4). Each p in produces alternating ac -
tive-low pulses with a pulse duration (tPW) defined by
the Pulse Width Regist er (PW):
If MCLK = 4.096 MHz, K = 1, and PW = 1 then
tPW = 0.25 ms. To ensure that pulses occur on the E1
and E2 output pins when full-sca le input signals are ap-
plied to the voltage and current channels, then:
The pulse frequency (FREQE) is determined by the
PulseRateE1,2 Register and can be calculated using the
transfer fu nction. The en ergy directio n is not defined in
the alternate pulse format.
5.4.3 Mechanical Counter Format
Setting bits MECH = 1 and STEP = 0 in the Control
Register and bit ALT = 0 in the Configuration Register
enables E1 and E2 for mechan ical counters an d similar
discrete counting instruments. When energy is nega-
tive, pulses appear on E2 (see Figure 5). When energy
is positive, the pulses appear on E1. The pulse width is
defined b y the Pulsewidth Register and will limit the out-
put pulse frequency (FREQE). By default, PW = 512
samples, if MCLK = 4.096 MHz and K = 1 then
tPW = 128 ms. To ensure that pulses will occur, the
PulseRateE1,2 Register must be set to an appropriate
value.
5.4.4 Stepper Motor Format
Setting bits STEP = 1 and MECH = 0 in the Control
Register and bit ALT = 0 in the Configuration Register
configures the E1 and E2 pins for stepper motor format.
When the accumulated active power equals the defined
tdur sec 1
PulseRateE12,8
--------------------------------------------
1
(MCLK/K)/16 8
----------------------------------- tdur sec 1
(MCLK/K)/1024 8
-----------------------------------------
Figure 4. Alternate Pulse Format on E1 and E2
E1
...
...
E2
......
...
tPW FREQE
tPW ms PW
(MCLK/K)/1024
-----------------------------------------
=
PulseRateE12,1
tPW
------------
tPW
E1
Positive Energy Negative Energy ...
...
...
...
E2
FREQE
Figure 5. Mechanical Counter Format on E1 and E2
CS5461A
18 DS661F3
energy level, the energy output pins (E1 and E2) alter-
nate changing states (see Figure 6). The duration
(tedge) between the alternating states is defined by the
transfer function:
The direction the motor will rotate is determined by the
order of the state changes. When energy is po sitive, E1
will lead E2. When energy is negative, E2 will lead E1.
The Pulse Width Register (PW) does not affect the step-
per motor format.
5.4.5 Pulse Output E3
The pulse output E3 is designed to assist with meter cal-
ibration. The pulse-output frequency of E3 is directly
proportional to the active power calculated from the in-
put signals. E3 pulse frequency is derived using a sim-
ular transfer function as E1, but is set by the value in the
PulseRateE3 Register.
The E3 pin outputs negative and positive energy, but
has no energy direc tio n ind i cato r.
The pulse width of E3 is configurable. The PulseWidth
register defines the pulse width of E3 in units of 1/OWR
or:
The default value is 0.
5.4.6 Anti-creep for the Pulse Outputs
Anti-creep allows the measurement element to maintain
an energy level, such that when the magnitude of the
accumulated active power is below this level, no energy
pulses are output. Anti-creep is enabled by setting bit
FAC in the Control Register for E3 and bit EAC in the
Control Register for E1 and E2.
For low-frequency pulse output formats (i.e. mechanical
counter and stepper m otor formats) , the active powe r is
accumulated over time. When a designated energy lev-
el is reached (determined by the transfer function) a
pulse is generated on E1 and/o r E2. If active power with
alternating polar ity occurs during the accumulation peri-
od (e.g. rand om noise at zero power levels), the accura-
cy of the registered energy will be maintained.
For high-frequency pulse output formats (i.e. normal
and alternate pulse formats), the active power is accu-
mulated over time until a 8x buffer is defined. Then,
when the designated ene rgy level is reached, a pulse is
generated on E1 and/or E2. For pulse ou tputs with high
frequencies and power le vels close to zero, the extend-
ed buffer prevents random noise from being registered
as active energy.
5.4.7 Design Examples
EXAMPLE #1:
The maximum rated levels for a power line meter are
250 V rms and 20 A rms. The required number of puls-
es per second on E1 is 100 pulses per second (100 Hz),
when the levels on the power line are 220 V rms and
15 A rms.
With a 10x gain on the voltage and current channel the
maximum input signal is 250 mVP (see Section 5.1 An-
alog Inputs on page 15). To prevent over-driving the
channel inputs, the maximum rated rms input levels will
register 0.6 in VRMS and IRMS by design. Therefore the
voltage level at the channel inputs will be 150 mV rms
when the maximum rated levels on the power lines are
250 V rms and 20 A rms.
Solving for PulseRateE1,2 using the transfer function:
Therefore with PF = 1 and
the PulseRateE1,2 Register is set to:
E1
E2 Positive Energy Negative Energy
...
... ...
...
tedge
Figure 6. Stepper Motor Format on E1 and E2
tedge sec 1
FREQE
----------------------
=
tpw PulseWidth
MCLK
K1024
---------------------------------------------
=
PulseRateE12,FREQEVREFIN2
VIN VGAINIINPF
-------------------------------------------------------------------
=
VIN 220V 150mV250V132mV==
IIN 15A 150mV20A112.5mV==
PulseRateE 100 2.52
0.132 100.112510
----------------------------------------------------------------- 420.8754Hz==
CS5461A
DS661F3 19
EXAMPLE #2:
The required number of pulses per unit energy present
on E1 is specified to be 500 pulses per kWhr, given that
the line voltage is 250 Vrms and the line current is
20 Arms. In such a situation, the stated line voltage and
current do not determine the appropriate PulseRateE1,2
setting. To achieve full-scale readings in the instanta-
neous volta ge and cur rent registers, a 250 mV, DC-lev-
el signal is applied to the channel inputs.
As in example #1, the voltage and current channel gains
are 10x, and the voltage level at the channel inputs will
be 150 mV rms wh en the levels on the pow er lines are
250 V rms and 20 A rms. In order to achieve
500 pulse-per-kW Hr per unit-energy, the
PulseRateE1,2 Register setting is determined using the
following equation:
Therefor, the PulseRateE1,2 Register is approximately
1.929 Hz. The PulseRateE1,2 Register cannot be set to
a frequency of exactly 1.929 Hz. The closest setting is
0x00003E = 1.9375 Hz.
To improve the accuracy, either gain register can be
programmed to correct for the round-off error. This val-
ue would be calculated as
If (MCLK/K) is not equal to 4.096 MHz, the
PulseRateE1,2 Register must be scaled by a correction
factor of:
Therefore if (MCLK/K) = 3.05856 MHz the value of
PulseRateE1,2 Register is
5.5 Voltage Sag-detect Feature
Status bit VSAG in the Status Register, indicates a volt-
age sag occurred in the power line voltage. For a volt-
age sag condition to be identified, the absolute value of
the instantaneous vo ltage must be less than the voltage
sag level for more than half of the voltage sag duration
(see Figure 7).
To activate Voltage Sag detect, a voltage sag level must
be specified in the Voltage Sag Level Register
(VSAGLevel), and a voltage sag duration must be spec-
ified in the Voltage Sag Duration Register
(VSAGDuration). The voltage sag level is specified as the
average of the absolu te instantaneo us voltage . Voltage
sag duration is specified in terms of ADC cycles.
5.6 No Load Threshold
The CS5461A includes the LoadIntv (No Load Detec-
tion Interval) register and the LoadMin register to imple-
ment the no load threshold function. When the
accumulated energy measured within the time defined
by the LoadIntv register does no t r each the value in the
LoadMin register, the pulse outputs will be disabled.
5.7 On-chip Temperature Sensor
The on-chip temper ature sensor is designed to assist in
characterizing the measurement element over a desired
temperature range. Once a temperature characteriza-
tion is performed, the temperature sensor can then be
utilized to assist in compensating for temperature drift.
Temperature measurements are performed during con-
tinuous conversions and stored in the Temperature
Register. The Temperature Register (T) default is Cel-
sius scale (oC). The Temperature Gain Register (Tgain)
and Temperature Offset Register (Toff) are constant val-
ues allowing for temperature scale conversions.
The temperature upd ate rate is a function of the number
of ADC samples. With MCLK = 4.096 MHz and K = 1
the update rate is:
PulseRateE12,500pulses
kWHr
------------------------------1Hr
3600s
----------------
1kW
1000W
------------------- 250mV
150mV
250V
-------------------
-------------------------
250mV
150mV
20A
-------------------
-------------------------
=
Vgn or Ign PulseRateE
1.929
----------------------------------- 1.00441 0x404830==
4.096MHz
(MCLK/K)
---------------------------- PulseRateE12,
PulseRateE12,4.096
3.05856
--------------------- 1.929Hz2.583Hz=
Level
Duration
Figure 7. Voltage Sag Detect
2240 samples
(MCLK/K)/1024
-----------------------------------------0.56 sec
=
CS5461A
20 DS661F3
The Cycle Count Register (N) must be set to a value
greater than one. Status bit TUP in the Status Register,
indicates when the Temperatur e Reg ist er is updated.
The Temperature Offset Register sets the zero-degree
measurement. To improve temperature measurement
accuracy, the zero-de gree offset sho uld be ad justed af -
ter the CS5461A is initialized. Temperature offset cali-
bration is achieved by adjusting the Temperature Offset
Register (Toff) by the differential temp erature ( T) mea -
sured from a calibrated digital thermometer and the
CS5461A temperature sensor. A one-degree adjust-
ment to the Temperature Register (T) is achieved by
adding 2.737649x10-4 to the Temperature Offset Regis-
ter (Toff). Therefore,
if Toff = -0.0951126 and T=-2.0 (
oC), then
or 0xF3C168 (2’s compliment notation) is stored in the
Temperat ur e Of fse t R egi ste r (Toff).
To convert the Temperature Register (T) from a Celsius
scale (oC) to a Fahrenheit scale (oF) utilize the formula
Applying the above relationship to the CS5461A tem-
perature measurement algorithm
If Toff = -0.09566 and Tgain = 23.507 for a Celsius
scale, then the modified values are Toff = -0.0907935
(0xF460E1) and Tgain = 42.3132 (0x54A05E) for a
Fahrenheit scale.
5.8 Voltage Reference
The CS5461A is specified for operation with a +2.5 V
reference between the VREFIN and AGND pins. To uti-
lize the on-chip 2.5 V referen ce, connect the VREFOUT
pin to the VREFIN pin of the device. The VREFIN pin
can be used to connect external filtering and/or refer-
ences.
5.9 System Initialization
Upon powering up, the digital circuitry is held in reset
until the analog voltage reaches 4.0 V. At that time, an
eight-XIN-clock-period delay is enabled to allow the os-
cillator to stabilize. The CS5461A will then initialize.
A hardware reset is initiated when the RESET pin is as-
serted with a minimum pulse width of 50 ns. The
RESET signal is asynchronous, with a Schmitt-trigger
input. Once the RESET pin is de-asserted, an
eight-XIN-clock-period delay is enabled
.
A software reset is initiated by writing the command of
0x80. After a hardware or software reset, the internal
registers (some of which drive output pins) will be reset
to their default values. Status bit DRDY in the Status
Register, indicates the CS5461A is in its active state
and ready to receive commands.
5.10 Power-down States
The CS5461A has two power-down states, stand-by
and sleep. In the stand-by state all circuitry except the
voltage reference and crystal oscillator is turned off. To
return the device to the active state a power-up com-
mand is sent to the device.
In sleep state all circuitry exce pt the instruction decoder
is turned off. When the power-up command is sent to
the device, a system initialization is performed (see
Section 5.9 System Initialization on page 20).
5.11 Oscillator Characteristics
The XIN and XOUT pins are the input and output of an
inverting amplifier configured as an on-chip oscillator,
as shown in Figure 8. The oscillator circuit is designed
to work with a quartz crystal. To reduce circuit cost, two
load capacitors C1 and C2 are integrated in the device,
from XIN to DGND, and XOUT to DGND. PCB trace
lengths should be minimized to reduce stray capaci-
tance. To drive the device from an external clock
source, XOUT should be left unconnected while XIN is
driven by the external circuitr y. There is an amplifier be-
tween XIN and the digital section which provides
CMOS-level signals. This amplifier works with sinusoi-
Toff Toff T+2.737649 10 4
–
=
Toff 0.0951126 2.0–+2.737649 10 4
–
–0.09566–==
F
o9
5
---C
o17.7778+=
TF
o
9
5
---T
gain
TC
o
Toff 17.7778 2.737649 10 4
–
++=
Oscillator
Circuit
DGND
XIN
XOUT
C1
C1 = 22 pF
C2
C2 =
Figure 8. Oscillator Connection
CS5461A
DS661F3 21
dal inputs so there are no problems with slow edge
times.
The CS5461A can be driven by an external oscillator
ranging from 2.5 to 20 MHz, but the K divider value must
be set such that the internal MCLK will run somewhere
between 2.5 MHz and 5 MHz. The K divider value is set
with the K[3:0] bits in the Configuration Register. As an
example, if XIN = MCLK = 15 MHz, and K is set to 5,
then DCLK is 3 MHz, which is a valid value for DCLK.
5.12 Event Handler
The INT pin is used to indicate that an internal error or
event has take n place in the CS5461 A. Writing a logic 1
to any bit in the Mask Register allows the correspo nding
bit in the Status Register to activa te the I NT pin. The in-
terrupt conditio n is cl ea re d by writin g a logi c 1 to the bit
that has been set in the Status Register.
The behavior of the INT pin is controlled by the IMODE
and IINV bits of the Configuration Register.
If the interrupt output signal format is set for either falling
or rising edge, the duration of the INT pulse will be at
least one DCLK cycle (DCLK = MCLK/K).
5.12.1 Typical Interrupt Handler
The steps below show how interrupts can be handled.
INITIALIZATION:
1) All Status bits are clear ed by writing 0xFFFFFF to
the Status Register.
2) The condition bits which will be used to generate
interrupts are then set to logic 1 in the Mask Reg-
ister.
3) Enable interrupts.
INTERRUPT HANDLER ROUTINE:
4) Read the Status Register.
5) Disable all interrupts.
6) Branch to the proper interrupt service routine.
7) Clear the Status Register by writing b ack the read
value in step 4.
8) Re-enable interrupts.
9) Return from interru pt service routine.
IMODE IINV INT Pin
0 0 Active-low Level
0 1 Active-high Level
10 Low Pulse
Table 3. Interrupt Configuration
1 1 High Pulse
IMODE IINV INT Pin
Table 3. Interrupt Configuration
CS5461A
22 DS661F3
5.13 Serial Port Overview
The CS5461A incorporates a serial port transmit and re-
ceive buffer with a command decoder that interprets
one-byte (8 bits) commands as they are received. There
are four types of commands; instructions, synchroniz-
ing, register writes and reg ister reads (See Section 5.14
Commands on page 23).
Instructions are one byte in length and will interrupt any
instruction currently executing. Instructions do not affect
register reads currently being transmitted.
Synchronizing commands are one byte in length and
only affect the serial interface. Synchronizing com-
mands do not affect operations currently in progress.
Register writes must be followed by three bytes of data.
register reads can return up to four bytes of data.
Commands and data are transferred most-significant bit
(MSB) first. Figure 1 on page 11, defines the serial port
timing and required sequence necessar y to write to an d
read from the serial port receive and transmit buffer, re -
spectively. While reading data from the serial po rt, com-
mands and data can be simultan eously written. Starting
a new register read command while data is being read
will terminate the current read in progress. This is ac-
ceptable if the rema ind e r of th e cu rr en t re ad dat a is not
needed. During data reads, the serial port requires input
data. If a new command and data is not sent, SYNC0 or
SYNC1 must be sent.
5.13.1 Serial Port Interface
The serial port interf ace is a “4-wire” synchronous seria l
communications interface. The interface is enabled to
start excepting SCLKs when CS (Chip Select) is assert-
ed. SCLK (Serial bit-clock) is a Schmitt-trigg er input that
is used to strobe the data on SDI (Serial Data In) into the
receive buffer and out of the transmit buffer onto SDO
(Serial Data Out).
If the serial port interface becomes unsynchronized with
respect to the SCLK input, any attempt to clock valid
commands into the serial interface may result in unex-
pected operation. The serial p ort interface must then be
re-initialized by one of the following actions:
- Drive the CS pin high, then low.
- Hardware Reset (drive RESET pin low, for at
least 10 µs).
- Issue the Serial Port Initialization Sequence,
which is 3 (or more) SYNC1 command bytes
(0xFF) followed by one SYNC0 command byte
(0xFE).
If a resynchronization is necessary, it is best to re-initial-
ize the part either by hardware or software reset (0x80),
as the state of the part may be unknown.
CS5461A
DS661F3 23
5.14 Commands
All commands are 8-bits in length. Any byte that is n ot listed in this section is invalid. Commands that write to regi s-
ters must be followed by 3 bytes of data. Commands that read data can be chained with other commands (e.g., while
reading data, a new command can be sent which can execute during the original read). All commands except reg-
ister reads, register writes, and SYNC0 & SYNC1 will abort any currently executing commands.
5.14.1 Start Conversions
Initiates acquiring measurements and calculating results. The device has three modes of acquisition.
C[3:2] Modes of acquisition/measurement
00 = Perform a single computation cycle
01 = Not Used
10 = Perform continuous computation cycles
11 = Perform continuous compu tation cycles with APF enabled on the other channel
5.14.2 SYNC0 and SYNC1
The serial port can be initialized by asserting CS or by sending three or more consecutive SYNC1 commands fol-
lowed by a SYNC0 command. The SYNC0 or SYNC1 can also be sent while sending data out.
SYNC 0 = Last byte of a serial port re-initialization sequence.
1 = Used during reads and serial port initialization.
5.14.3 Power-Up/Halt
If the device is powered-down, Power-Up/Halt will initiate a power on reset. If the part is already powered-on, all
computations will be halted.
5.14.4 Power-down and Software Reset
To conserve power the CS5461A has two power-down states. In stand-by state all circuitry, except the analog/digital
clock generators, is turned off. In the sleep state all circuitry, except the instruction decoder, is turned off. Bringing
the CS5461A out of sleep state requires more time than out of stand-by state, because of the extra time n eeded to
re-start and re-stabilize the analog oscillator.
S[1:0] Power-down state
00 = Software Reset
01 = Halt and enter stand- by po we r sa ving sta te . Th is stat e allo ws qu ick powe r- on
10 = Halt and enter sleep power saving state.
11 = Reserved
B7 B6 B5 B4 B3 B2 B1 B0
1110C3C200
B7 B6 B5 B4 B3 B2 B1 B0
1111111SYNC
B7 B6 B5 B4 B3 B2 B1 B0
10100000
B7 B6 B5 B4 B3 B2 B1 B0
100S1S0000
CS5461A
24 DS661F3
5.14.5 Register Read/Write
The Read/Write informs the command decoder that a register access is required. During a read operation, the ad-
dressed register is loaded into an output buffer and clocked out by SCLK. During a write operation, the data is
clocked into an input buffer and transferred to the addressed register upon completion of the 24th SCLK.
W/R Write/Read control
0 = Read
1 = Write
RA[4:0] Register address bits (bits 5 through 1) of the read/write command.
Address RA[4:0] Name Description
0 00000 Config Configuration
1 00001 IDCoff Current DC Offset
2 00010 Ign Current Gain
3 00011 VDCoff Voltage DC Offset
4 00100 Vgn Voltage Gain
5 00101 Cycle Count Number of A/D conversions used in one computation cycle (N)).
6 00110 PulseRateE1,2 Sets the E1 and E2 energy-to-frequency output pulse rate.
7 00111 I Instantaneous Current
8 01000 V Instantaneous Voltage
9 01001 P Instantaneous Power
10 01010 PActive Active (Real) Power
11 01011 IRMS RMS Current
12 01100 VRMS RMS Voltage
14 01110 Poff Power Offse t
15 01111 Status Status
16 10000 IACoff Current AC (RMS) Offset
17 10001 VACoff Voltage AC (RMS) Offset
18 10010 PulseRateE3Sets the E3 energy-to-frequency output pulse ra te.
19 10011 T Temperature
20 10100 SYSGain System Gain
21 10101 PW Pulse width register for mechanical counter ou tput mode
22 10110 PulseWidth Pulse width register for E3 energy pulse output
23 10111 VSAGDuration Voltage Sag Duration
24 11000 VSAGLevel Voltage Sag Level Threshold
25 11001 LoadIntv No load threshold interval (detection window)
26 11010 Mask Interrupt Mask
27 11011 LoadMin No Load Threshold
28 11100 Ctrl Control
29 11101 TGain Temperat ur e Sen s or Ga in
30 11110 Toff Temperat ur e Sen so r Of fse t
31 11111 S Apparent Power
Note: For proper operation, do not attempt to write to unspecified registers.
B7 B6 B5 B4 B3 B2 B1 B0
0W/R
RA4 RA3 RA2 RA1 RA0 0
CS5461A
DS661F3 25
5.14.6 Calibration
The CS5461A can perform system calibrations. Proper input signals must be applied to the current and voltage
channel before performing a designated calibration.
CAL[4:0]* Designates calibration to be performed
01001 = Current channel DC offset
01010 = Current channel DC gain
01101 = Current channel AC offset
01110 = Current channel AC gain
10001 = Voltage channel DC offset
10010 = Voltage channel DC gain
10101 = Voltage channel AC offset
10110 = Voltage channel AC gain
11001 = Current and Voltage channel DC offset
11010 = Current and Voltage channel DC gain
11101 = Current and Voltage channel AC offset
11110 = Current and Voltage channel AC gain
*Values for CAL[4:0] not specified should not be used.
B7 B6 B5 B4 B3 B2 B1 B0
1 1 0 CAL4 CAL3 CAL2 CAL1 CAL0
CS5461A
26 DS661F3
6. REGISTER DESCRIPTION
1. “Default” => bit status aft er power-on or reset
2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
6.1 Configuration Register
Address: 0
Default = 0x000001
PC[6:0] Phase compensation. A 2’s complement numb er which sets a delay in the voltage chan nel rel-
ative to the current channe l. When MCLK = 4.096 MHz and K = 1, the phase adjustment ra nge
is approximately 2 .8 de gr ees with each ste p a pproxima te ly 0.04 de grees ( assumin g a p ower
line frequency of 60 Hz). If (MCLK/K) is not 4.096 MHz, the values for the rang e and step size
should be scaled by the factor 4.096 MHz/ (MCLK/K). Default setting is 0 000000 = 0.0215 de-
gree phase delay at 60 Hz (when MCLK = 4.096 MHz).
Igain Sets the gain of the current PGA.
0 = Gain is 10x (default)
1 = Gain is 50x
EWA Allows the E1 and E2 pins to be configured as open-collector output pins.
0 = Normal outputs (default)
1 = Only the pull-down device of the E1 and E2 pins are active
IMODE, IINV Interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
00 = Active-low level (default)
01 = Active-high level
10 = High-to-low pulse
11 = Low-to-high pulse
EPP Allows the E1 and E2 pins to be controlled by the EOP and EDP bits.
0 = Normal operation of the E1 and E2 pins. (defau lt)
1 = EOP and EDP bits defines the E1 and E2 pins.
EOP EOP defines the value of the E1 pin when EPP = 1.
0 = Logic level low (default)
EDP EDP defines the value of the E2 pin when EPP = 1.
0 = Logic level low (default)
ALT Alternate pulse format, E1 and E2 becomes active low alternating pulses with an output fre-
quency proportional to the active power.
0 = Normal (default), Mechanical Counter or Stepper Motor Format
1 = Alternate Pulse Format, also MECH = 1
VHPF (IHPF) Enables the high-pass filter on the voltage (current) channel.
0 = High-pass filter disabled (default)
1 = High-pass filter enabled
23 22 21 20 19 18 17 16
PC6 PC5 PC4 PC3 PC2 PC1 PC0 Igain
15 14 13 12 11 10 9 8
EWA IMODE IINV EPP EOP EDP
76543210
ALT VHPF IHPF iCPU K3 K2 K1 K0
CS5461A
DS661F3 27
iCPU Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic dr iven by CPUCLK should not be active du rin g the samp le edg e.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising-edge logic
K[3:0] Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. A value of “0000” will set K to 16 (not zero). K = 1 at reset.
6.2 Current and Voltage DC Offset Register ( IDCoff ,VDCoff )
Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
Default = 0x000000
The DC Offset registers (IDCoff,VDCoff) are initialized to 0.0 on reset. When DC Offset calibration is performed, the
register is updated with the DC offset measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read an d stored for future system offset compensation. The value is repre-
sented in two's complement notation and in the range of -1.0 IDCoff, VDCoff 1.0, with the binary point to the
right of the MSB.
6.3 Current and Voltage Gain Register ( Ign ,Vgn )
Address: 2 (Current Gain); 4 (Voltage Gain)
Default = 0x400000 = 1.000
The gain regi sters (Ign,Vgn) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,
the register is updated with the gain measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system gain compensation. The value is in the
range 0.0 Ign,Vgn < 3.9999, with the binary point to the right of the second MSB.
6.4 Cycle Count Register
Address: 5
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024N). A one second computational cycle period occurs when
MCLK = 4.096 MHz, K = 1, and N = 4000.
MSB LSB
-(20)2
-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
MSB LSB
21202-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22
MSB LSB
223 222 221 220 219 218 217 216 ..... 26252423222120
CS5461A
28 DS661F3
6.5 PulseRateE1,2 Register
Address: 6
Default = 0xFA000 = 32000.00 Hz
PulseRateE1,2 sets the frequency of the E1 and/or E2 pulses. The smallest valid frequency is 2-4 with 2-5 incre-
mental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value
is represented in unsigned notation, with the binary point to the right of bit 5.
6.6 Instantaneous Current, Voltage and Power Registers ( I , V , P )
Address: 7 (Instantaneous Current); 8 (Instantaneous Voltage); 9 (Instantaneous Power)
I and V contain the instantaneous measured values for current and voltage, respectively. The instantaneous
voltage and current samples are multiplied to obtain Instantaneous Power (P). The value is represented in two's
complement notation and in the range of -1.0 I, V, P1.0, with the binary point to the right of the MSB.
6.7 Active (Real) Power Registers ( PActive )
Address: 10
The instantaneous power is averaged over each computation cycle (N conversions) to compute Active Power
(PActive). The value is rep resented in two's co mpl ement n otation a nd in the ra nge of -1.0 PActive1.0, with the
binary point to the right of the MSB.
6.8 IRMS and VRMS Registers ( IRMS , VRMS )
Address: 11 (IRMS); 12 (VRMS)
IRMS and VRMS contain the Root Mea n Square (RMS) value of I and V, calculated over each computation cycle.
The value is r epresented in unsigne d binary notation and in the range of 0.0 IRMS,V
RMS 1.0, with the binary
point to the left of the MSB.
6.9 Power Offset Register ( Poff )
Address: 14
Default = 0x000000
Power Offset (Poff) is added to the instantaneous power being accumulated in the Pactive register and can be
used to offset contributions to the en ergy result that are caused by undesirable sources of energy that are in-
herent in the system. The value is represented in two's complement notation and in the range of -1.0 Poff 1.0,
with the binary point to the right of the MSB.
MSB LSB
218 217 216 215 214 213 212 211 ..... 21202-1 2-2 2-3 2-4 2-5
MSB LSB
-(20)2
-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
MSB LSB
-(20)2
-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
MSB LSB
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24
MSB LSB
-(20)2
-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
CS5461A
DS661F3 29
6.10 Status Register and Mask Register ( Status , Mask )
Address: 15 (Status); 26 (Mask)
Default = 0x000001 (Status Register), 0x000000 (Mask Register)
The Status Register indicates status within the chip. In normal operation, writing a '1' to a bit will cause the bit
to reset. Writing a '0' to a bit will not change it’s current state.
The Mask Register i s used to contro l the activation of the INT pin. Placing a logic '1' in a Mask bit will allow the
correspond in g bit in th e Sta tu s Register to activate the INT pin when the status bit is asserted.
DRDY Data Ready. During conversions, this bit will indicate the end of computation cycles. For cali-
brations, this bit indicates the end of a calibration sequen ce.
CRDY Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate.
IOR Current Out of Range. Set when the Instantaneous Current Register ov er flo w s.
VOR Voltage Out of Range. Set when the Instantaneous Voltage Register overflows.
IROR IRMS Out of Range. Set when the IRMS Register overflows.
VROR VRMS Out of Range. Set when the VRMS Register overflows.
EOR Energy Out of Range. Set when PACTIVE overflows.
TUP Temperature Updated. Indicates the Temperat ur e Re gist er has updated.
TOD Modulator oscillation detected on the temperature channel. Set when the modulator oscillates
due to an input above full scale.
VOD (IOD) Modulator oscillation detected on the voltage (current) channel. Set when the modulator oscil-
lates due to an input above full scale. The level at which the modulator oscillates is significantly
higher than the voltage (current) channel’s differential inp ut voltage range.
Note: The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the
power line. This event sh ould n ot be confused with a DC overload situa tion at the in-
puts, when the IOD and VOD bits will re-assert themselves even after being cleared,
multiple times.
LSD Low Supply Detect. Set when the voltage at th e PFMON pin falls below the low-voltage thresh-
old (PMLO), with respect to AGND pin. The LSD bit cannot be reset until the voltage at PFMON
pin rises back above the high-voltage threshold (PMHI).
VSAG Indicates a voltage sag has occurred. See Section 5.5 Voltage Sag-detect Feature on page 19.
IC Invalid Command. Normally logic 1. Set to logic 0 if an invalid command is received or the Sta-
tus Register has not been suc ces sfu lly re ad .
23 22 21 20 19 18 17 16
DRDY CRDY IOR VOR
15 14 13 12 11 10 9 8
IROR VROR EOR
76543210
TUP TOD VOD IOD LSD VSAG IC
CS5461A
30 DS661F3
6.11 Current and Voltage AC Offset Register ( VACoff , IACoff )
Address: 16 (Current AC Offset); 17 (Voltage AC Offset)
Default = 0x000000
The AC Offset Registers (VACoff, IACoff) are initialized to zero on reset, allowing for u ncalibrated normal operation.
AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cycles (where
N is the value of the Cycle Count Register). DRDY will be asserted at the end of the calibration. These values
may be read and stored for future system AC offset compensation. The value is represented in two's comple-
ment notation and in the range of -1.0 VACoff, IACoff 1.0, with the binary point to the right of the MSB.
6.12 Puls eRateE3 Register
Address: 18
Default = 0xFA0000 = 32000.00 Hz
PulseRateE3 sets the frequency of th e E3 pulses. The register’s smallest valid frequency is 2-4 with 2-5 incre-
mental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value
is represented in unsigned notation, with the binary point to the right of bit #5.
6.13 Temperature Register ( T )
Address: 19
T contains measurements from the on-chip temperature sensor. Measurements are performed during continu-
ous conversions, with the default the Celsius scale (oC). The value is represented in two's complement notation
and in the range of -128.0 T128.0, with the binary point to the right of the eighth MSB.
6.14 System Gain Register ( SYSGain )
Address: 20
Default = 0x500000 = 1.25
System Gain (SYSGain) determines the one’s de nsity of the channel measur ements. Small chan ges in the mod-
ulator due to temperature can be fine a djusted by cha ngin g the system gain . The value is rep resented in two's
complement notation and in the range of -2.0 SYSGain 2.0, with the binary point to the right of the second
MSB.
MSB LSB
-(20)2
-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
MSB LSB
218 217 216 215 214 213 212 211 ..... 21202-1 2-2 2-3 2-4 2-5
MSB LSB
-(27)2
6252423222120..... 2-10 2-11 2-12 2-13 2-14 2-15 2-16
MSB LSB
-(21)2
02-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22
CS5461A
DS661F3 31
6.15 Pulsewidth Register ( PW )
Address: 21
Default = 0x000200 = 512 sample periods
PW sets the pulsewidth of E1 and E2 pulses in Alte rnate Pulse and Mechanical Counter format. The width is a
function of number of sample periods. The default corresponds to a pulsewidth of
512 samples/[(MCLK/K)/1024] = 128 msec with MCLK = 4.096 MHz and K = 1. The value is represented in un-
signed notation.
6.16 E3 Pulse Width Register ( PulseWidth )
Address: 22
Default = 0x000000 = Hardware-genera ted pulse width (up to 125 s)
The PulseWidth register sets the pulse width of E3 pulses in units of 1/OWR.
E3 pulse width =
The range of this register is from 1 to 8388607.
6.17 Voltage Sag Duration Register ( VSAGDuration )
Address: 23
Default = 0x000000
Voltage Sag Duration (VSAGDuration) defines the number of instantaneous voltage measurements utilized to de-
termine a voltage level sag event (VSAGLEVEL). Setting this register to zero will disable Voltage Sag-detect. The
value is represented in unsigned notation.
6.18 Voltage Sag Level Register ( VSAGLevel )
Address: 24
Default = 0x000000
Voltage Sag Level (VSAGLevel) defines the voltage level that the magnitude of input samples, averaged over the
sag duration, must fall below in order to register a sag condition. This value is represented in unsigned no tation
and in the range of 0 VSAGLevel 1.0, with the binary point to the right of the MSB.
MSB LSB
223 222 221 220 219 218 217 216 ..... 26252423222120
MSB LSB
0222 221 220 219 218 217 216 ..... 26252423222120
MSB LSB
0222 221 220 219 218 217 216 ..... 26252423222120
PulseWidth
MCLK
K1024
---------------------------------------------
MSB LSB
02-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
CS5461A
32 DS661F3
6.19 No Load Threshold Interval Register ( LoadIntv)
Address: 25
Default = 0x000000 = No load threshold feature disabled
LoadMin determines the duration or interval of the no load detection window in units of 1/OWR. The range is
from 1 to 16777215 .
6.20 No Load Threshold ( LoadMin )
Address: 27
Default = 0x000000 = No load threshold feature disabled
LoadMin sets th e no load thr es ho ld va lue . Lo ad M i n is a two’s complement value in the range of
-1.0 LoadMin 1.0 with the binary point to the right of the MSB. Negative values are not allowed.
MSB LSB
223 222 221 220 219 218 217 216 ..... 26252423222120
MSB LSB
-(20)2
-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
CS5461A
DS661F3 33
6.21 Control Register
Register Address: 28
Default = 0x000000
FAC Determines if anti-creep is enabled for pulse output E3.
0 = Disable anti-creep (default)
1 = Enabled anti-creep
EAC Determines if anti-creep is enabled for pulse output E1 and/or E2.
0 = Disable anti-creep (default)
1 = Enabled anti-creep
STOP Terminates the auto-boot sequence.
0 = Normal (default)
1 = Stop sequence
MECH Mechanical Counter Format, E1 or E2 becomes active low pulses with an output frequency pro-
portional to the active power
0 = Normal (default) or Stepper Motor Format
1 = Mechanical Counter Format, also ALT = 0
INTOD Converts INT output pin to an open drain output.
0 = Normal (default)
1 = Open drain
NOCPU Saves power by disabling the CPUCLK pin.
0 = Normal (default)
1 = Disables CPUCLK
NOOSC Saves power by disabling the crystal oscillator.
0 = Normal (default)
1 = Oscillator circuit disabled
STEP Stepper Motor Format, E1 and E2 becomes active low pulses with an outp ut frequency propor-
tional to the active power
0 = Normal Format (default)
1 = Stepper Motor Format, also MECH = 0 and ALT = 0
6.22 Temperature Gain Register ( TGain )
Address: 29
Default = 0x2F02C3 = 23.5073471
Sets the temperature channel gain. Temperature gain (TGain) is utilized to convert from one temperature scale to an-
other. The Celsius scale (oC) is the default. Values are represented in unsigned notation and in the range of
0TGain 128, with the binary point to the right of the seventh MSB.
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
FAC EAC STOP
76543210
MECH INTOD NOCPU NOOSC STEP
MSB LSB
262524232221202-1 ..... 2-11 2-12 2-13 2-14 2-15 2-16 2-17
CS5461A
34 DS661F3
6.23 Temperature Offset Register ( Toff )
Address: 30
Default = 0xF3D35A = -0.0951126
Temperature offset (Toff) is used to remove the temperature channel’s offset at the ze ro degree reading. Values
are represented in two's complement notation and in the range of -1.0 Toff 1.0, with the binary point to the
right of the MS B.
6.24 Apparent Power Register ( S )
Address: 31
Apparent power (S) is the pr od uct of the VRMS and IRMS. The value is represented in unsigned binary notation
and in the range of 0.0 S1.0, with the binary point to the left of the MSB.
MSB LSB
-(20)2
-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23
MSB LSB
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24
CS5461A
DS661F3 35
7. SYSTEM CALIBRATION
7.1 Channel Offset and Gain Calibration
The CS5461A provides digital DC offset and gain com-
pensation that can be applied to the instantaneous vo lt-
age and current measurements, and AC offset
compensat ion to the voltage an d current RMS calcula-
tions.
Since the voltage an d cu rrent channels have indepen-
dent offset and gain registers, system offset and/or
gain can be performed on either channel without the
calibration results from one ch annel affecting the oth-
er.
The computational flow of the calibration sequences are
illustrated in Figure 9. The flow applies to both the volt-
age channel and current channel.
7.1.1 Calibration Sequence
The CS5461A must be operating in its active state and
ready to accept valid commands. Refer to Section 5.14
Commands on page 23. The calibration algorithms are
dependent on the value N in the Cycle Count Register
(see Figure 9). Upon completion, the results of the cali-
bration are available in their corresponding register. The
DRDY bit in the Status Register will be set. If the DRDY
bit is to be output on the INT pin, then DRDY bit in the
Mask Register must be set. The initial values stored in
the AC gain and offset registers do affect the calibration
results.
7.1.1.1 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines
the number of conversions performed by the CS5461A
during a given calibration sequence. For DC offset and
gain calibrations, the calibration sequence takes at least
N + 30 conversion cycles to complete. For AC offset
calibrations, the sequence takes at least 6N + 30 ADC
cycles to complete, (about 6 computation cycles). As N
is increased, the accuracy of calibration results will in-
crease.
7.1.2 Offset Calibration Sequence
For DC- and AC offset calibrations, the VIN pins of the
voltage and IIN pins of the current channels should be
connected to their ground-reference level.
See Figure 10.
The AC offset registers must be set to the default
(0x000000).
7.1.2.1 DC Offset Calibration Sequence
Channel gain should be set to 1.0 when performing DC
offset calibration. Initiate a DC offset calibration. The DC
offset registers are updated with the negative of the av-
erage of the instantaneous samples taken over a com-
putational cycle. Upon completion of the DC offset
calibration the DC offset is stor ed in the corresp onding
DC offset register. The DC offset value will be added to
each instantaneous measuremen t to cance l out the DC
Figure 9. Calibration Data Flow
In Modulator +X
to V*, I* Registe r s
Filter
N
VRMS*, IRMS*
Registers
DC Offset* Gain*
0.6
+
+
+
* Denotes readable/writable register
N
+
X
N
Inverse
X
-1
RMS
AC Offs e t*
N
X
-1
+
+
-
XGAIN
+
-
External
Connections
0V
+
-AIN+
AIN-
CM
+
-
Figure 10. System Calibration of Offset.
CS5461A
36 DS661F3
component present in the system during conversion
commands.
7.1.2.2 AC Offset Calibration Sequence
Corresponding offset registers IACoff and/or VACoff
should be cleared prior to initiating AC offset calibra-
tions. Initiate an AC offset calibration. The AC offset reg-
isters are updated with an offset value that reflects the
RMS output level. Upon completion of the AC offset cal-
ibration the AC offset is stored in the corresponding AC
offset register. The AC offset register value is subtract-
ed from each successive VRMS and IRMS calculation.
7.1.3 Gain Calibration Sequence
When performing gain calibrations, a reference signal
should be applied to the VIN pins of the voltage and
IIN pins of the current channe ls that represents the de-
sired maximum signal level. Figure 11 shows the basic
setup for gain calibration.
For gain calibrations, there is an absolute limit on the
RMS voltage levels that are selected for the gain-cali-
bration input signals. The maximum value that the gain
registers ca n attain is 4. Ther efore, if the signal level of
the applied input is low enough that it causes the
CS5461A to attempt to set either gain register higher
than 4, the gain calibration result will be invalid and all
CS5461A results obtained while performing measure-
ments will be invalid.
If the channel gain registers are initially set to a gain oth-
er then 1.0, AC gain calibration should be used.
7.1.3.1 AC Gain Calibration Sequence
The corresponding gain register should be set to 1.0,
unless a different initial gain value is desired. Initiate an
AC gain calibration. The AC gain calibration algorithm
computes the RMS value of the reference signal applied
to the channel inputs. The RMS register value is then di-
vided into 0.6 and the quotient is stored in the corre-
sponding gain register. Each instantaneous
measurement will be multiplied by its corresponding AC
gain value.
A typical rms calibration value which allows for reason-
able over-range margin would be 0.6 or 60% of the volt-
age and current channel’s maximum input voltage level.
Two examples of AC gain calibration and the updated
digital output codes of the cha nnel’s instantaneous data
registers are shown in Figures 12 and 13. Figure 13
shows that a positive (or negative), DC-level signal can
be used even though a n AC gain calibration is being ex-
+
-
+
-
External
Connections
IN+
IN-
CM +
-
+
-XGAIN
Reference
Signal
Figure 11. System Calibration of Gain
VRMS Register = 230/ x 1/250 0.65054
250 mV
230 mV
0 V
-230 mV
-250 mV
0.9999...
0.92
-0.92
-1.0000...
VRMS Register =0.600000
250 mV
230 mV
0 V
-230 mV
-250 mV
0.84853
-0.84853
Before AC Gain Calibration (Vgn Register = 1)
After A C G ain Calibration (Vgn Register changed to approx. 0.9223)
Instantaneous Voltage
Register Values
Instantaneous Voltage
Register Values
Sinewave
Sinewave
0.92231
-0.92231
INPUT
SIGNAL
INPUT
SIGNAL
Figure 12. Example of AC Gain Calibration
VRMS Register = 230 =0.92
250 mV
230 mV
0 V
-250 mV
0.9999...
0.92
-1.0000...
VRMS Register =0.600000
250 mV
230 mV
0 V
-250 mV
0.6000
Before AC Gain Calibration (Vgain Register = 1)
After AC Gain Calibration (Vgain Register changed to approx. 0.65217)
Instantaneous Voltage
Register Values
Instantaneous Voltage
Register Values
DC Signal
DC Signal
0.65217
-0.65217
INPUT
SIGNAL
INPUT
SIGNAL
250
Figure 13. Another Example of AC Gain Calibration
CS5461A
DS661F3 37
ecuted. Howe ver, an AC signal should not be used for
DC gain calibration.
7.1.3.2 DC Gain Calibration Sequence
Initiate a DC gain calibration. The corresponding gain
register is restore d to default (1.0). The DC gain calibra-
tion algorithm averages the channel’s instantaneous
measurements over one computation cycle (N sam-
ples). The average is then divided into 1.0 and the quo-
tient is stored in the corresponding gain register
After the DC gain calibration, the instantaneou s register
will read at full-scale whenever the DC level of the input
signal is equal to the level of the DC calibration signal
applied to the inputs during the DC gain calibration.The
HPF option should not be ena bled if DC gain calibration
is utilized.
7.1.4 Order of Calibration Sequences
1. If the HPF option is enabled, then any dc compo-
nent that may be present in the selected signal path
will be removed and a DC offset calibration is not re-
quired. However, if the HPF option is disabled the
DC offset calibration sequence should be per-
formed.
When using high-pass filters, it is recommended
that the DC offset register for the corresponding
channel be set to zero. When performing DC offset
calibration, the corresponding gain channel should
be set to one.
2. If an ac offset exist, in the VRMS or IRMS calculation,
then the AC offset calibration sequence should be
performed.
3. Perform the gain calibration sequence.
4. Finally, if an AC offset calibration was performed
(step 2), then the AC offset may need to be adjusted
to compensate for the change in gain (step 3). This
can be accomplished by restoring zero to the AC
offset register and then perform an AC offset cali-
bration sequence. The adjustment could also be
done by multiplying the AC offset r egister value that
was calculated in step 2 by the gain calculated in
step 3 and updating the AC offset register with the
product.
7.2 Phase Compensation
The CS5461A is equipped with phase compensation to
cancel out phase shifts introduced by the me asurement
element. Phase Compensation is set by bits PC[6:0] in
the Configuration Register.
The default value of PC[6:0] is zero. With
MCLK = 4.096 MHz and K = 1, the phase compensa-
tion has a rang e of 2 .8 degrees when th e input signals
are 60 Hz. Under these conditions, each step of the
phase compensation register (value of one LSB) is ap-
proximately 0.04 degrees. For values of MCLK other
than 4.096 MHz, the range and step size should be
scaled by 4.096 MHz/(MCLK/K). For power-line fre-
quencies other than 60Hz, the values of the range and
step size of the PC[6:0] bits can be determined by con-
verting the above values from angular measurement
into time-domain (seconds), and then computing the
new range and step size ( in degrees) with respect to the
new line frequency.
7.3 Active Power Offset
The Power Offset Register can be used to offset system
power sources that may be resident in the system, but
do not originate from the power-line signal. These
sources of extra energy in the system contribute unde-
sirable and false offsets to the power and energy mea-
surement results. After determining the amount of stray
power, the Power Offset Register can be set to cancel
the effects of this unwanted energy.
CS5461A
38 DS661F3
8. AUTO-BOOT MODE USING E2PROM
When the CS5461A MODE pin is asserted (log ic 1), the
CS5461A auto-boot mode is enabled. In auto-boot
mode, the CS5461A downloads the required com-
mands and register data from an external serial
E2PROM, allowing the CS5461A to begin performing
energy measurements.
8.1 Auto-Boot Configuration
A typical auto-boot serial connection between the
CS5461A and a E2PROM is illustrated in Figure 14. In
auto-boot mode, th e CS5461A’s CS and SCLK are con-
figured as outputs. The CS5461A asserts CS, provides
a clock on SCLK, and sends a read command to the
E2PROM on SDO. The CS5461A reads the user-speci-
fied commands and register data presented on the SDI
pin. The E2PROM’s programmed data is utilized by the
CS5461A to change the designated registers’ default
values and beg in re gist er ing en er gy .
Figure 14 also shows the external connections that
would be made to a calibrator device, such as a PC or
custom calibration board. When the metering system is
installed, the calibrator would be used to control calibra-
tion and/or to program user-specified commands and
calibration values into the E2PROM. The user-specified
commands/data will determine the CS5461A’s exact
operation, when the auto-boot initialization sequence is
running. Any of the valid commands can be used.
8.2 Auto-Boot Data for E2PROM
Below is an example code set for an auto-boot se-
quence. This code is written into the E2PROM by the us-
er. The serial data for such a sequence is shown be low
in single-byte, hexidecimal notation:
-40 00 00 61
Write Configuration Register, turn high-pass filters
on, set K=1.
-44 7F C4 A9
Write value of 0x7FC4A9 to Current Gain
Register.
-48 FF B2 53
Write value of 0xFFB253 to Voltage Gain
Register.
-4C 00 7D 00
Set PulseRateE1,2 Register to 1000 Hz.
-74 00 00 04
Unmask bit #2 (LSD) in the Mask Register).
-E8
Start continuous conversions
-78 00 01 00
Write STOP bit to Control Register, to terminate
auto-boot initialization sequence.
8.3 Suggested E2PROM Devices
Several industry-standard, serial E2PROMs that will
successfully run auto-boot with the CS5461A are listed
below:
• Atmel AT25010, AT25020 or AT25040
• National Semiconductor NM25C040M8 or NM250 20M8
• Xicor X25040SI
These types of serial E2PROMs expect a specific 8-bit
command (00000011) in order to perform a memory
read. The CS5461A has been hardware programmed to
transmit this 8-bit command to the E2PROM at the be-
ginning of the auto-boot sequence.
Figure 14. Typical Interfa ce of E2PROM to CS5461A
CS5461A EEPROM
EOUT1
EOUT2
MODE
SCLK
SDI
SDO
CS
SCK
SO
SI
CS
Connector to Calibrator
VD+
5 K
5 K
M e c h . Counte r
Stepper Motor
or
CS5461A
DS661F3 39
9. BASIC APPLICATION CIRCUITS
Figure 15 shows the CS5461A configured to measure
power in a singl e-pha se, 2- wire sys tem wh ile oper ating
in a single-supply co nfiguration. In this diagram, a shunt
resistor is used to sense the line current and a voltage
divider is use d to sense the line voltage. In t his type of
shunt resistor configuration, the common-mode level of
the CS5461A must be referenced to the line side of the
power line. This means that the common-mode poten-
tial of the CS5461A will track the high-voltage levels, as
well as low-voltage levels, with respect to earth ground
potential. Isolation circuitry is required when an earth-
ground-reference d communication interface is connect-
ed.
Figure 16 shows the same single-phase, two-wire sys-
tem with complete isolation from the power lines. This
isolation is achieved using three transformers: a general
purpose transformer to supply the on-board DC power;
a high-precision, low-impedance voltage transformer
with very little roll-off/phase-delay, to measure voltage;
and a current transformer to sense the line current.
Figure 17 shows a single-phase, 3-wire system. In
many 3-wire residential power systems within the Unit-
ed States, only the two line terminals are available (neu-
tral is not available). Figure 18 shows the CS5461A
configured to meter a thre e- wire system with no ne utra l
available.
VA+ VD+
CS5461A
0.1 µF470 µF
500
470 nF
500
N
R1
R2
10
14
VIN+
9
VIN-
IIN-
10
15
16 IIN+
PFMON
CPUCLK
XOUT
XIN Optional
Clock
Source
Serial
Data
Interface
RESET
17
2
1
24
19
CS 7
SDI 23
SDO 6
SCLK 5
INT 20
E1
0.1 µF
VREFIN
12
VREFOUT
11
AGND DGND
13 4
3
4.096 MHz
0.1 µF
10 k
5k
L
RShunt
RV-
RI-
RI+
ISOLATION
120 VAC
Mech. Counter
Stepper Mot or
or
22
21
CI-
CI+
CIdiff
CV-
CV+
CVdiff
E2
Note:
Indicates common (floating) return.
Figure 15. Typical Connection Diagram (Single-phase, 2-wire – Direct Connect to Power Line)
CS5461A
40 DS661F3
VA+ VD+
CS5461A
0.1 µF470 µF
500
470 nF
500
N
R3R4
RBurden
10
14
VIN+
9
VIN-
IIN-
10
16
15
IIN+
PFMON
CPUCLK
XOUT
XIN Optional
Clock
Source
RESET
17
2
1
24
CS
SD
SDO
SCLK
INT
0.1 µF
VREFIN
12
VREFOUT
11
DGND
13 4
3
4.095 MHz
0.1 µF
L1L2
10 k
5k
R1
R
2
RI+
RI-
22
21
Mech. Counter
Stepper Moto r
or
1k
1k
120 VAC 120 VAC
240 VAC
Serial
Data
Interface
19
7
23
6
5
20
I
Earth
Ground
CIdiff
CIdiff
E1
AGND
E2
Figure 17. Typical Connection Diagram (Single-phase, 3-wire)
Mec h. C o u n ter
Stepper Motor
or
VA+ VD+
CS5461A
0.1µF
200µF
200
N10
14
VIN+
9
VIN-
IIN-
10
15
16 IIN+
PFMON
CPUCLK
XOUT
XIN Optional
Clock
Source
RESET
17
2
1
24
CS
SDI
SDO
SCLK
INT 22
E1 21
0.1 µF
VREFIN
12
VREFOUT
11
AGND DGND
13 4
3
4.096 MH z
0.1 µF
10 k
5k
L
M:1
R
N:1
Low P hase-Shift
Potential Transformer
Current
Transformer
RV+
RV-
CVdiff
RI-
RI+
C
Burden Idiff
Voltage
Transformer
120 VAC
12 VAC
12 VAC
200
Serial
Data
Interface
19
7
23
6
5
20
1k
1k
1k
1k
E2
Figure 16. Typical Connection Dia gram (Single-phase, 2-wire – Isolated from Power Line)
CS5461A
DS661F3 41
VA+ VD+
0.1 µF470 µF
1k
235nF
500
R1R2
10
14
VIN+
9
VIN-
IIN-
10
16
15
IIN+
PFMON
CPUCLK
XOUT
XIN Optional
Clock
Source
RESET
17
2
1
24
CS
SDI
SDO
SCLK
INT
0.1 µF
VREFIN
12
VREFOUT
11
DGND
13 4
3
4.096 MHz
0.1 µF
L1L2
10 k
5k
RI+
RI-
RV-
Serial
Data
Interface
19
7
23
6
5
20
ISOLATION
22
21
Mech. Counter
Stepper Moto r
or
RBurden
1k
1k
240 VAC
CS5461A
Note:
Indicates common (floating) return.
CVdiff
CI+
CV+
CIdiff
E1
AGND
E2
Figure 18. Typical Connection Diagram (Single-phase, 3-wire – No Neutral Avai labl e)
CS5461A
42 DS661F3
10.PACKAGE DIMENSIONS
Notes: 3. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch
and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
4. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in
excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more
than 0.07 mm at least material condition.
5. These dimensions apply to the flat sectio n of the lead between 0.10 and 0.25 mm from lead tips.
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.084 -- -- 2.13
A1 0.002 0.006 0.010 0.05 0.13 0.25
A2 0.064 0.068 0.074 1.62 1.73 1.88
b 0.009 -- 0.015 0.22 -- 0.38 2,3
D 0.311 0.323 0.335 7.90 8.20 8.50 1
E 0.291 0.307 0.323 7.40 7.80 8.20
E1 0.197 0.209 0.220 5.00 5.30 5.60 1
e 0.022 0.026 0.030 0.55 0.65 0.75
L 0.025 0.03 0.041 0.63 0.75 1.03
0° 4° 8° 0° 4° 8°
JEDEC #: MO-150
Controlling Dimension is Millimeters.
E
N
123
eb2A1
A2 A
D
SEATING
PLANE
E1
1
L
SID E VI EW
END VIEW
TO P VIE W
24L SSOP PACKAGE DRAWING
CS5461A
DS661F3 43
11. ORDERING INFORMATION
12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
Model Temperature Package
CS5461A-ISZ (lead free) -40 to +85 °C 24-pin SSOP
Model Number Peak Reflow Temp MSL Rating* Max Floor Life
CS5461A-ISZ (lead free) 260 °C 3 7 Days
CS5461A
44 DS661F3
13. REVISION HISTORY
Revision Date Changes
A1 DEC 2004 Advance Release
PP1 FEB 2005 Initial Preliminary Release
F1 AUG 2005 Final version Updated with most-recent characterization data. MSL data added.
F2 APR 2008 Added LoadIntv, LoadMin, & PulseWidth registers. Added APF function.
F3 APR 2011 Removed lead-containing (Pb) device ordering information.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
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Cirrus Logic, Cirru s, a nd the Cirrus Logic logo design s are trademarks of Cirrus Lo gi c, Inc. Al l other brand and prod uct n ames in this document may be tra de ma rks
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SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
