©2003 Fairchild Semiconductor Corporation
June 2003
ISL9N306AD3 / ISL9N306AD3ST
IS L9N 306AD 3 / ISL9 N306 AD 3ST Rev. B2
SOURCE
ISL9N306AD3 / ISL9N30 6AD3ST
N-C hannel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
30V, 50A, 6mΩ
General Description
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
Opti mi zed for s wit chin g appl icat ions , t his devi ce i mpr ove s
the overall efficiency of DC/DC converters and allows
operatio n to h ighe r switching frequenci es.
Applications
• DC/DC converters
Features
•Fast switching
•r
DS(ON) = 0.0052Ω (Typ), VGS = 10V
•r
DS(ON) = 0.0085Ω (Typ), VGS = 4.5V
•Q
g (Typ) = 30nC, VGS = 5V
•Q
gd (Typ) = 11n C
•C
ISS (Typ) = 3400pF
MOSFET Maxi mum Ratings TA = 25°C unless otherwise noted
Thermal Chara cte ris tics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDSS Drain to S ou rc e Volt a ge 30 V
VGS Gate to Sourc e Voltage ±20 V
ID
Drain C urr e nt 50 A
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 4.5V) 50 A
Continuous (TC = 25oC, VGS = V, RθJC = 52oC/W) 16 A
Pulsed Figure 4 A
PDPower dissip ation
Derate above 25oC125
0.83 W
W/oC
TJ, TSTG Operating and Storage Tem perature -55 to 175 oC
RθJC Thermal Resistance Junction to Case TO-251, TO-252 1.2 oC/W
RθJA Thermal Resistance Junction to Ambient TO-251, TO-252 100 oC/W
RθJA Thermal R esistance Ju ncti on t o Ambien t TO-252, 1in2 co pper pad area 52 oC/W
Device Marking Device Package Reel Size Tape Width Quantity
N306AD ISL9N306AD3ST TO-252AA 330mm 16mm 2500 units
N306AD ISL 9N306AD3 TO- 251A A Tube N/A 7 5 unit s
GATE
DRAIN (FLANGE) D
G
S
TO-252
(FLANGE)
DRAIN GATE
DRAIN
SOURCE
TO-251
©2003 Fairchild Semiconductor Corporation IS L9N 306AD 3 / ISL9 N306 AD 3ST Rev. B2
ISL9N306AD3 / ISL9N306AD3ST
Electrical Characteristics TA = 25°C unless other wise not e d
Off Characteristics
On Characteristics
Dynamic Characteristic s
Switching Characteri stics (VGS = 4.5V)
Switching Characteri stics (VGS = 10V )
Unclamped Indu ctive Switching
Drain-Source Diode Character istics
Symbol Parameter Test Conditions Min Typ Max Units
BVDSS Dr ai n to S ou r c e Br ea kd ow n Voltage ID = 250µA, VGS = 0V 30 - - V
IDSS Zero Gate Voltage Drain Current VDS = 25V - - 1 µA
VGS = 0V TC = 150o--250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA1-3V
rDS(ON) D r ai n to S ou r c e On Re si stance ID = 50A, VGS = 10V - 0.0052 0.0060 Ω
ID = 50A, VGS = 4.5V - 0.0085 0.0095
CISS Input Capacitance VDS = 15V, VGS = 0V,
f = 1MHz
-3400- pF
COSS Output Capacitance - 650 - pF
CRSS Reverse Transfer Capacitance - 300 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V
VDD = 15V
ID = 5 0A
Ig = 1.0mA
-6090nC
Qg(5) Total Gate Charge at 5V VGS = 0V to 5V - 30 45 nC
Qg(TH) Threshold Gate Charge VGS = 0V to 1V - 3.0 4.5 nC
Qgs Ga te to Sourc e Gate Charg e - 10 - n C
Qgd Gate to Drain “Miller” Charge - 11 - nC
tON Turn-On Time
VDD = 15V, ID = 16A
VGS = 4. 5 V, RGS = 4.3Ω
--131ns
td(ON) Turn-On D el ay Time - 16 - ns
trRise Time - 70 - ns
td(OFF) Turn -Off Delay T ime - 34 - ns
tfFall Time - 30 - ns
tOFF Turn-Off Time - - 97 ns
tON Turn-On Time
VDD = 15V, ID = 16A
VGS = 10V, RGS = 4.3Ω
- - 80 ns
td(ON) Turn-On D el ay Time - 10 - ns
trRise Time - 43 - ns
td(OFF) Turn -Off Delay T ime - 62 - ns
tfFall Time - 29 - ns
tOFF Turn-Off Time - - 13 7 ns
tAV Avalan ch e Time ID = 30A, L = 200 µH428--µs
VSD Source to Drain Diode Voltage ISD = 50A - - 1.25 V
ISD = 25A - - 1.0 V
trr Reverse Recovery Time ISD = 50 A, dISD/dt = 100A/µs- - 35 ns
QRR Reverse Recovered Charge ISD = 50A , dISD/dt = 100A/µs- - 30 nC
©2003 Fairchild Semiconductor Corporation IS L9N 306A D3 / IS L9N 306AD 3S T Rev. B 2
ISL9N306AD3 / ISL9N306AD3ST
Typical Characteristic
Figure 1. Normalized Power Diss ipation vs
Ambient Temperature Figure 2. Maximu m Continuous Drain Curr ent vs
Case Temperature
F igur e 3. Norm alized Maximum transient Thermal Impedan ce
Figure 4. Peak Current Capability
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
0
10
20
30
40
50
60
25 50 75 100 125 150 175
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
VGS = 10V
VGS = 4.5V
0.1
1
10-5 10-4 10-3 10-2 10-1 100101
0.01
2
t, RE CTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
THERMAL IMPEDANCE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DES CENDING ORDER
SINGLE PULSE
10-5 10-4 10-3 10-2 10-1 100101
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TC = 25oC
I = I25 175 – TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRE NT
IN THIS REGION
VGS = 10V
100
1000
40
2000
©2003 Fairchild Semiconductor Corporation IS L9N 306A D3 / IS L9N 306AD 3S T Rev. B 2
ISL9N306AD3 / ISL9N306AD3ST
Figure 5. Transfer Charact eristic s Figure 6. Satur ation Characteristics
Figure 7. Drain to So urce On Resistance vs Gat e
Voltage and Drain Current Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 9. Norm alized Gate Threshold Voltag e vs
Junction Temperature Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Typical Characteristic (Continued)
0
25
50
75
100
12345
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = -55oC
TJ = 175oC
TJ = 25oC
0
25
50
75
100
0 0.5 1.0 1.5 2.0
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 3V
VGS = 3.5V
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 4.5V
5
10
15
20
25
246810
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
ID =5A ID = 50A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
ID = 25A
0.5
1.0
1.5
2.0
-80 -40 0 40 80 120 160 200
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 50A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.2
0.6
1.0
1.4
-80 -40 0 40 80 120 160 200
NORMALIZED GA T E
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
0.9
1.0
1.1
-80 -40 0 40 80 120 160 200
1.2
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
©2003 Fairchild Semiconductor Corporation IS L9N 306A D3 / IS L9N 306AD 3S T Rev. B 2
ISL9N306AD3 / ISL9N306AD3ST
Figure 11. Capacitance vs Drain to Source
Voltage Figure 1 2. Gate Charge Waveforms for Constant
Gate Currents
Figure 13. Switchi ng Time vs Gate Resistance Figure 14. Switchi ng Time vs Gate Resistance
Typical Characteristic (Continued)
1000
0.1 1 10
5000
100
30
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
0
2
4
6
8
10
0 102030 405060
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15V
ID = 50A
ID = 25A
WAVEFORMS IN
DESCENDING ORDER:
ID = 5A
0
50
100
150
200
250
300
0 1020304050
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 4.5V, VDD = 15V, ID = 16A
tr
td(ON)
tf
td(OFF)
0
100
200
300
400
500
0 1020304050
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
td(OFF)
tr
td(ON)
tf
VGS = 10V, VDD = 15V, ID = 16A
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
©2003 Fairchild Semiconductor Corporation IS L9N 306A D3 / IS L9N 306AD 3S T Rev. B 2
ISL9N306AD3 / ISL9N306AD3ST
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
Test Circuits and Waveforms (Con ti nu ed)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS
DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%50%
10% PULSE WI DT H
VGS
0
0
©2003 Fairchild Semiconductor Corporation IS L9N 306A D3 / IS L9N 306AD 3S T Rev. B 2
ISL9N306AD3 / ISL9N306AD3ST
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maxi mum al lowab le devi ce powe r di ssipat ion, PDM, in an
application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
s erves as the basis for esta blishing the rating of the part.
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
c omple x and influenced by many factors:
1. Mou nti ng pad area onto which t he device i s at tach ed and
wh ethe r the re is copp er on on e si de or b oth si de s of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of exte rnal heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transien t thermal respon se of the part,
the boa rd and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
posit i on ed FR-4 boar d wi th 1 oz c opper af t er 100 0 se c on ds
of stea dy st ate powe r w ith n o air flow . Th is gr aph prov ides
the necessary informat ion for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a cons tant. The area, in square
inche s is the top copper area including the gate and s ourc e
pads.
(EQ. 1)
PDM
TJM TA
–()
ZθJA
-----------------------------=
(EQ. 2)
RθJA 33.32 23.84
0.268 Area+()
-------------------------------------+=
25
50
75
100
125
0.01 0.1 1 10
Figure 21. Thermal Resistance vs Mounting
Pad Area
RθJA = 33.32 + 23.84/(0.268+Area)
RθJA (oC/W)
AREA, TOP COPPER AREA (in2)
©2003 Fairchild Semiconductor Corporation IS L9N 306A D3 / IS L9N 306AD 3S T Rev. B 2
ISL9N306AD3 / ISL9N306AD3ST
PSPICE Electrical M odel
. S UBCKT IS L9N 3 06A 2 1 3 ; re v May 2001
C A 12 8 2. 0e- 9
CB 15 14 2. 3e-9
CIN 6 8 3e-9
D BODY 7 5 DBODYM O D
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 35.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTH RES 6 21 19 8 1
EVTEM P 20 6 18 22 1
IT 8 1 7 1
LDRAIN 2 5 1.0e- 9
LGATE 1 9 4.58e- 9
LSOU RCE 3 7 1.47e-9
MMED 16 6 8 8 M M EDMOD
MSTRO 16 6 8 8 MS T ROMOD
MWEAK 16 21 8 8 M WEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
R G A T E 9 20 2.69
RL DRAIN 2 5 10
RLGATE 1 9 45 .8
RL SOUR CE 3 7 14. 7
RSLC1 5 51 R SLCMOD 1e-6
RSLC2 5 50 1e 3
RSOURCE 8 7 R SOUR CEMO D 3.5 e -3
RVT HRE S 22 8 RV T HRE SM OD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1A M OD
S1B 13 12 13 8 S1BMO D
S2A 6 15 14 13 S2AMO D
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*275),5))}
.MODEL DBODYMOD D (IS = 3.6e-11 N=1.075 RS = 3.5e-3 TRS1 = 1e-3 TRS2 = 1e-6 XTI=1.0 CJO = 1.45e-9 TT = 8e-11 M =
0.51)
.MO DE L DB REAK M OD D (RS = 1.7e- 1 TRS 1 = 1e-3 TRS 2 = -8. 9e-6)
.MO DE L DP LCA PMOD D (CJO = 11. 5e-10 IS = 1e- 30 N = 10 M = 0.46)
. M ODEL MMEDMO D NM O S (V T O = 1.7 KP = 9 IS = 1e- 30 N = 10 TOX = 1 L = 1u W = 1u R G = 2.69)
.MO DEL M STROMOD NM OS (V T O = 2.1 KP = 100 IS = 1e-3 0 N= 10 TO X = 1 L = 1u W = 1u )
.MO DEL MWEAKMOD NMOS (VTO = 1.36 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.9 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = -7e-7)
.MO DEL RDRAINMO D RE S (TC1 = 1.2e-2 TC2 = 3.0e-5)
.MO DE L RS LCM OD RES (TC1 = 1e-3 TC2 = 1e-6)
.MO DEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.6e-3 TC2 = -7.5e-6)
.MO DEL RV T E MPMOD RES (TC1 = -1.8e- 3 TC2 = 1e -6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF= -0.8)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.8 VOFF= -4.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.3 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.3)
.ENDS
NO TE: For further discussion of the PSPI CE model, consult A New PSPI CE Sub-Circuit for the P ower MOSFET Featuring Global
Temperature Options; IEEE Power Ele ctronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
©2003 Fairchild Semiconductor Corporation IS L9N 306A D3 / IS L9N 306AD 3S T Rev. B 2
ISL9N306AD3 / ISL9N306AD3ST
SABER Electrical Model
REV May 2001
tem pl ate ISL9N306A n2,n1,n 3
electrical n2,n1,n3
{
var i iscl
dp.. m odel dbodymod = (isl = 3.6e-11 , nl=1.075 , rs = 3.5e -3, trs1 = 1e-3, tr s2 = 1e-6, xti=1.0, cj o = 1.45 e-9, tt = 8e-11 , m = 0.51,)
dp.. m odel dbreakmod = (rs =0.17, tr s1 = 1e-3, trs2 = -8.9e- 6)
dp.. m odel dpl capmod = (cjo = 11. 5e-10, i sl= 10e- 30, nl=10, m=0.4 6)
m..model mmedmod = (type=_n, vto = 1. 7, kp=9, is=1e- 30, tox=1)
m..model mstron gm od = (type=_n, vto = 2. 1, kp = 100 , is = 1e -30, tox = 1)
m..model mw eakmod = (type=_n, vto = 1. 36, kp = 0.05, is = 1e-30, tox = 1, rs =0. 1)
sw_vcsp..mo del s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -0.8)
sw_v cs p..mo del s1bmod = (ron =1e-5, roff = 0.1 , v on = -0.8 , vo ff = -4. 0)
sw_v cs p..mo del s2amod = (ron = 1e-5, rof f = 0.1, vo n = -0. 3, voff = 0.2)
sw_v cs p..mo del s2bmod = (ron = 1e-5, rof f = 0.1, vo n = 0.2 , v off = -0.3)
c . ca n1 2 n8 = 2. 0e- 9
c.cb n15 n14 = 2.3e- 9
c.c in n6 n8 = 3e-9
dp.dbody n7 n5 = mod el= dbody m od
dp.dbreak n5 n11 = m odel= dbreak m od
dp.dplcap n10 n5 = mo del =dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lg ate n1 n9 = 4.58e-9
l.lsource n3 n7 = 1.47e-9
m.mmed n16 n6 n8 n8 = model =m m edm od, l= 1u, w=1u
m.ms t rong n16 n6 n8 n8 = model =m str ongmod, l=1u, w=1 u
m.mw eak n16 n21 n8 n8 = mo del =m wea km od, l=1u, w=1u
res. rbreak n17 n18 = 1, t c1 = 1e-3, tc 2 = -7e-7
res. rdrai n n50 n16 = 1e-3, tc 1 = 1.2e- 2, t c2 = 3.0 e-5
res.rgate n9 n20 = 2.69
res. rl drai n n2 n5 = 10
res. rl gate n1 n9 = 45.8
res. rl source n3 n7 = 14. 7
res. rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc 2 =1e-6
res. rslc2 n5 n50 = 1e3
res. rsource n8 n7 = 3.5 e-3, tc1 = 1e-3, tc 2 =1e-6
res. rvte m p n18 n19 = 1, t c1 = -1.8 e-3, tc2 = 1e-6
res. rvth res n22 n8 = 1, tc1 = -2.6e-3, tc 2 = -7.5 e-6
spe. ebreak n11 n7 n17 n18 = 35. 8
spe. eds n14 n8 n5 n8 = 1
spe. egs n13 n8 n6 n8 = 1
spe. esg n6 n10 n6 n8 = 1
spe. evte mp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_v cs p.s1 a n6 n12 n13 n8 = model =s1amod
sw_v cs p.s1 b n13 n12 n13 n8 = model =s1bmod
sw_v cs p.s2 a n6 n15 n14 n13 = model =s2amod
sw_v cs p.s2 b n13 n15 n14 n13 = model =s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl : v (n51, n50) = ((v(n5,n51)/(1e -9+abs(v (n5,n 51))))*((abs (v(n5,n 51)*1e-6/ 275))** 5))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
©2003 Fairchild Semiconductor Corporation IS L9N 306A D3 / IS L9N 306AD 3S T Rev. B 2
ISL9N306AD3 / ISL9N306AD3ST
SPICE Thermal Model
REV May 2001
ISL9N306AT
CTH ERM1 th 6 2.7e-4
CTH ERM2 6 5 3.9e -3
CTH ERM3 5 4 4.2e -3
CTH ERM4 4 3 4.8e -3
CTH ERM5 3 2 1.9e -2
CTH ERM6 2 tl 5.9e-2
RTH ERM1 th 6 1.0e-3
RTH ERM2 6 5 4.8e -3
RTH ERM3 5 4 4.5e -2
RTH ERM4 4 3 2.6e -1
RTH ERM5 3 2 3.1e -1
RTH ERM6 2 tl 3.4e-1
SABER Thermal Mod el
SABE R t herm al m odel I SL9N 306AT
template thermal_model th tl
the r m al_ c th , tl
{
c t h erm. cther m 1 th 6 = 2.7e- 4
cthe rm .ctherm2 6 5 = 3.9e- 3
cthe rm .ctherm3 5 4 = 4.2e- 3
cthe rm .ctherm4 4 3 = 4.8e- 3
cthe rm .ctherm5 3 2 = 1.9e- 2
cthe rm .ctherm 6 2 tl = 5. 9e-2
rtherm.rtherm 1 th 6 = 1. 0e-3
r the rm .rthe rm2 6 5 = 4.8e- 3
r the rm .rthe rm3 5 4 = 4.5e- 2
r the rm .rthe rm4 4 3 = 2.6e- 1
r the rm .rthe rm5 3 2 = 3.1e- 1
r the rm .rthe r m 6 2 t l = 3.4e -1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
Rev. I2
TRADEMARKS
The following are registered and unregistered trademarks Fairc hild Semiconductor owns or is authorized to use and is no t
intended to be an exhaustive list of all such trademarks.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
wh ich, (a) ar e int ende d fo r s urgic al i mpla nt into the body ,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A c r it ic al c om pon ent i s an y c om po ne nt o f a l ife s uppor t
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Defini ti on of Terms
ACEx™
ActiveArray™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
EcoSPARK™
E2CMOS™
EnSigna™
FACT™
FACT Quiet Series™
FAST®
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
I2C™
ImpliedDisconnect™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC®
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench®
QFET™
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
SILENT SWITCHER®
SMART START™
SPM™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic®
TruTranslation™
UHC™
UltraFET®
VCX™
A cross the board. Around the world.™
T he Po wer Fr anchise™
P rogrammable Acti ve Droop™
Datasheet Identification Product Status Definition
Adva nce Informatio n Formative or In
Design This datasheet cont ains the design specific atio ns for
product development. Specifications may change in
any manner without notice.
Prelimin ary Fi rst Production This dat asheet contains preliminary data , and
supplementary data will be pub lished at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without no tice in order to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor re serves the right to make change s at
any time without notice in order to improve design.
Obsolete Not In P roduction This dat asheet contain s specifications on a product
that has been disco nti nued by Fairchild semiconductor.
The datasheet is printed for reference information only.
