AD620BRZTESTMARQ - Analog Devices

Low Cost Low Power

Instrumentation Amplifier

AD620

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Easy to use

Gain set with one external resistor

(Gain range 1 to 10,000)

Wide power supply range (±2.3 V to ±18 V)

Higher performance than 3 op amp IA designs

Available in 8-lead DIP and SOIC packaging

Low power, 1.3 mA max supply current

Excellent dc performance (B grade)

50 µV max, input offset voltage

0.6 µV/°C max, input offset drift

1.0 nA max, input bias current

100 dB min common-mode rejection ratio (G = 10)

Low noise

9 nV/√Hz @ 1 kHz, input voltage noise

0.28 µV p-p noise (0.1 Hz to 10 Hz)

Excellent ac specifications

120 kHz bandwidth (G = 100)

15 µs settling time to 0.01%

APPLICATIONS

Weigh scales

ECG and medical instrumentation

Transducer interface

Data acquisition systems

Industrial process controls

Battery-powered and portable equipment

CONNECTION DIAGRAM

–IN

R

G

–V

S

+IN

R

G

+V

S

OUTPUT

REF

1

2

3

4

8

7

6

5

AD620

TOP VIEW

00775-0-001

Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) Packages

PRODUCT DESCRIPTION

The AD620 is a low cost, high accuracy instrumentation

amplifier that requires only one external resistor to set gains of

1 to 10,000. Furthermore, the AD620 features 8-lead SOIC and

DIP packaging that is smaller than discrete designs and offers

lower power (only 1.3 mA max supply current), making it a

good fit for battery-powered, portable (or remote) applications.

The AD620, with its high accuracy of 40 ppm maximum

nonlinearity, low offset voltage of 50 µV max, and offset drift of

0.6 µV/°C max, is ideal for use in precision data acquisition

systems, such as weigh scales and transducer interfaces.

Furthermore, the low noise, low input bias current, and low power

of the AD620 make it well suited for medical applications, such

as ECG and noninvasive blood pressure monitors.

The low input bias current of 1.0 nA max is made possible with

the use of Superϐeta processing in the input stage. The AD620

works well as a preamplifier due to its low input voltage noise of

9 nV/√Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band,

and 0.1 pA/√Hz input current noise. Also, the AD620 is well

suited for multiplexed applications with its settling time of 15 µs

to 0.01%, and its cost is low enough to enable designs with one

in-amp per channel.

0 5 10 15 20

30,000

5,000

10,000

15,000

20,000

25,000

0

TOTAL ERROR, PPM OF FULL SCALE

SUPPLY CURRENT (mA)

AD620A

R

G

3 OP AMP

IN-AMP

(3 OP-07s)

00775-0-002

Figure 2. Three Op Amp IA Designs vs. AD620

SOURCE RESISTANCE (

Ω

)100M10k1k 10M1M100k

10,000

0.1

100

1,000

10

1

RTI VOLTAGE NOISE

(0.1 – 10Hz) (

µ

V p-p)

TYPICAL STANDARD

BIPOLAR INPUT

IN-AMP

AD620 SUPER

β

ETA

BIPOLAR INPUT

IN-AMP

G = 100

00775-0-003

Figure 3. Total Voltage Noise vs. Source Resistance

AD620

Rev. G | Page 2 of 20

TABLE OF CONTENTS

Specifications .....................................................................................3

Absolute Maximum Ratings ............................................................5

ESD Caution ..................................................................................5

Typical Performance Characteristics..............................................7

Theory of Operation.......................................................................13

Gain Selection..............................................................................16

Input and Output Offset Voltage ..............................................16

Reference Terminal.....................................................................16

Input Protection..........................................................................16

RF Interference............................................................................16

Common-Mode Rejection.........................................................17

Grounding....................................................................................17

Ground Returns for Input Bias Currents.................................18

Outline Dimensions........................................................................19

Ordering Guide...........................................................................20

REVISION HISTORY

12/04—Rev. F to Rev. G

Updated Format..................................................................Universal

Change to Features............................................................................1

Change to Product Description.......................................................1

Changes to Specifications.................................................................3

Added Metallization Photograph....................................................4

Replaced Figure 4-Figure 6 ..............................................................6

Replaced Figure 15............................................................................7

Replaced Figure 33..........................................................................10

Replaced Figure 34 and Figure 35.................................................10

Replaced Figure 37..........................................................................10

Changes to Table 3 ..........................................................................13

Changes to Figure 41 and Figure 42 .............................................14

Changes to Figure 43 ......................................................................15

Change to Figure 44........................................................................17

Changes to Input Protection section ............................................15

Deleted Figure 9...............................................................................15

Changes to RF Interference section..............................................15

Edit to Ground Returns for Input Bias Currents section...........17

Added AD620CHIPS to Ordering Guide ....................................19

7/03—Data Sheet changed from REV. E to REV. F

Edit to FEATURES............................................................................1

Changes to SPECIFICATIONS.......................................................2

Removed AD620CHIPS from ORDERING GUIDE ...................4

Removed METALLIZATION PHOTOGRAPH...........................4

Replaced TPCs 1–3 ...........................................................................5

Replaced TPC 12...............................................................................6

Replaced TPC 30...............................................................................9

Replaced TPCs 31 and 32...............................................................10

Replaced Figure 4............................................................................10

Changes to Table I...........................................................................11

Changes to Figures 6 and 7............................................................12

Changes to Figure 8 ........................................................................13

Edited INPUT PROTECTION section........................................13

Added new Figure 9........................................................................13

Changes to RF INTERFACE section ............................................14

Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS

section...............................................................................................15

Updated OUTLINE DIMENSIONS.............................................16

AD620

Rev. G | Page 3 of 20

SPECIFICATIONS

Typical @ 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

Table 1.

AD620A AD620B AD620S1

Parameter Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

GAIN G = 1 + (49.4 kΩ/RG)

Gain Range 1 10,000 1 10,000 1 10,000

Gain Error2 VOUT = ±10 V

G = 1 0.03 0.10 0.01 0.02 0.03 0.10 %

G = 10 0.15 0.30 0.10 0.15 0.15 0.30 %

G = 100 0.15 0.30 0.10 0.15 0.15 0.30 %

G = 1000 0.40 0.70 0.35 0.50 0.40 0.70 %

Nonlinearity VOUT = −10 V to +10 V

G = 1–1000 RL = 10 kΩ 10 40 10 40 10 40 ppm

G = 1–100 RL = 2 kΩ 10 95 10 95 10 95 ppm

Gain vs. Temperature

G = 1 10 10 10 ppm/°C

Gain >12 −50 −50 −50 ppm/°C

VOLTAGE OFFSET (Total RTI Error = VOSI + VOSO/G)

Input Offset, VOSI VS = ±5 V

to ± 15 V

30 125 15 50 30 125 µV

Overtemperature VS = ±5 V

to ± 15 V

185 85 225 µV

Average TC VS = ±5 V

to ± 15 V

0.3 1.0 0.1 0.6 0.3 1.0 µV/°C

Output Offset, VOSO VS = ±15 V 400 1000 200 500 400 1000 µV

V

S = ± 5 V 1500 750 1500 µV

Overtemperature VS = ±5 V

to ± 15 V

2000 1000 2000 µV

Average TC VS = ±5 V

to ± 15 V

5.0 15 2.5 7.0 5.0 15 µV/°C

Offset Referred to the

Input vs. Supply (PSR) VS = ±2.3 V

to ±18 V

G = 1 80 100 80 100 80 100 dB

G = 10 95 120 100 120 95 120 dB

G = 100 110 140 120 140 110 140 dB

G = 1000 110 140 120 140 110 140 dB

INPUT CURRENT

Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA

Overtemperature 2.5 1.5 4 nA

Average TC 3.0 3.0 8.0 pA/°C

Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA

Overtemperature 1.5 0.75 2.0 nA

Average TC 1.5 1.5 8.0 pA/°C

INPUT

Input Impedance

Differential 10||2 10||2 10||2 GΩ_pF

Common-Mode 10||2 10||2 10||2 GΩ_pF

Input Voltage Range3 VS = ±2.3 V

to ±5 V

−VS + 1.9 +VS − 1.2 −VS + 1.9 +VS − 1.2 −VS + 1.9 +VS − 1.2 V

Overtemperature −VS + 2.1 +VS − 1.3 −VS + 2.1 +VS − 1.3 −VS + 2.1 +VS − 1.3 V

V

S = ± 5 V

to ±18 V

−VS + 1.9 +VS − 1.4 −VS + 1.9 +VS − 1.4 −VS + 1.9 +VS − 1.4 V

Overtemperature −VS + 2.1 +VS − 1.4 −VS + 2.1 +VS + 2.1 −VS + 2.3 +VS − 1.4 V

AD620

Rev. G | Page 4 of 20

AD620A AD620B AD620S1

Parameter Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

Common-Mode Rejection

Ratio DC to 60 Hz with

1 kΩ Source Imbalance VCM = 0 V to ± 10 V

G = 1 73 90 80 90 73 90 dB

G = 10 93 110 100 110 93 110 dB

G = 100 110 130 120 130 110 130 dB

G = 1000 110 130 120 130 110 130 dB

OUTPUT

Output Swing RL = 10 kΩ

V

S = ±2.3 V

to ± 5 V

−VS +

1.1

+VS − 1.2

−V

S

+ 1.1

+VS − 1.2 −VS + 1.1 +VS − 1.2 V

Overtemperature −VS + 1.4 +VS − 1.3

−V

S

+ 1.4

+VS − 1.3 −VS + 1.6 +VS − 1.3 V

VS = ±5 V

to ± 18 V

−VS + 1.2 +VS − 1.4

−V

S

+ 1.2

+VS − 1.4 −VS + 1.2 +VS − 1.4 V

Overtemperature −VS + 1.6 +VS – 1.5

−V

S

+ 1.6

+VS – 1.5 –VS + 2.3 +VS – 1.5 V

Short Circuit Current ±18 ±18 ±18 mA

DYNAMIC RESPONSE

Small Signal –3 dB Bandwidth

G = 1 1000 1000 1000 kHz

G = 10 800 800 800 kHz

G = 100 120 120 120 kHz

G = 1000 12 12 12 kHz

Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs

Settling Time to 0.01% 10 V Step

G = 1–100 15 15 15 µs

G = 1000 150 150 150 µs

NOISE

Voltage Noise, 1 kHz 2

2)/()( GeeNoiseRTITotal no

ni +=

Input, Voltage Noise, eni 9 13 9 13 9 13 nV/√Hz

Output, Voltage Noise, e

no 72 100 72 100 72 100 nV/√Hz

RTI, 0.1 Hz to 10 Hz

G = 1 3.0 3.0 6.0 3.0 6.0 µV p-p

G = 10 0.55 0.55 0.8 0.55 0.8 µV p-p

G = 100–1000 0.28 0.28 0.4 0.28 0.4 µV p-p

Current Noise f = 1 kHz 100 100 100 fA/√Hz

0.1 Hz to 10 Hz 10 10 10 pA p-p

REFERENCE INPUT

RIN 20 20 20 kΩ

IIN VIN+, VREF = 0 50 60 50 60 50 60 µA

Voltage Range −VS + 1.6 +VS − 1.6 −VS + 1.6 +VS − 1.6 −VS + 1.6 +VS − 1.6 V

Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001

POWER SUPPLY

Operating Range4 ±2.3 ±18 ±2.3 ±18 ±2.3 ±18 V

Quiescent Current VS = ±2.3 V

to ±18 V

0.9 1.3 0.9 1.3 0.9 1.3 mA

Overtemperature 1.1 1.6 1.1 1.6 1.1 1.6 mA

TEMPERATURE RANGE

For Specified Performance −40 to +85 −40 to +85 −55 to +125 °C

1 See Analog Devices military data sheet for 883B tested specifications.

2 Does not include effects of external resistor RG.

3 One input grounded. G = 1.

4 This is defined as the same supply range that is used to specify PSR.

AD620

Rev. G | Page 5 of 20

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±18 V

Internal Power Dissipation1 650 mW

Input Voltage (Common-Mode) ±VS

Differential Input Voltage 25 V

Output Short-Circuit Duration Indefinite

Storage Temperature Range (Q) −65°C to +150°C

Storage Temperature Range (N, R) −65°C to +125°C

Operating Temperature Range

AD620 (A, B) −40°C to +85°C

AD620 (S) −55°C to +125°C

Lead Temperature Range

(Soldering 10 seconds) 300°C

1 Specification is for device in free air:

8-Lead Plastic Package: θJA = 95°C

8-Lead CERDIP Package: θJA = 110°C

8-Lead SOIC Package: θJA = 155°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other condition s above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD620

Rev. G | Page 6 of 20

00775-0-004

Figure 4. Metallization Photograph.

Dimensions shown in inches and (mm).

Contact sales for latest dimensions.

AD620

Rev. G | Page 7 of 20

TYPICAL PERFORMANCE CHARACTERISTICS

(@ 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.)

INPUT OFFSET VOLTAGE (

µ

V)

20

30

40

50

–40 0 40 80

PERCENTAGE OF UNITS

–80

SAMPLE SIZE = 360

10

0

00775-0-005

Figure 5. Typical Distribution of Input Offset Voltage

INPUT BIAS CURRENT (pA)

0

10

20

30

40

50

–600 0 600

PERCENTAGE OF UNITS

–1200 1200

SAMPLE SIZE = 850

00775-0-006

Figure 6. Typical Distribution of Input Bias Current

10

20

30

40

50

–200 0 200 400

INPUT OFFSET CURRENT (pA)

PERCENTAGE OF UNITS

–400

0

SAMPLE SIZE = 850

00775-0-007

Figure 7. Typical Distribution of Input Offset Current

TEMPERATURE (°C)

INPUT BIAS CURRENT (nA)

+I

B

–I

B

2.0

–2.0 175

–1.0

–1.5

–75

–0.5

0

0.5

1.0

1.5

1257525–25

00775-0-008

Figure 8. Input Bias Current vs. Temperature

CHANGE IN OFFSET VOLTAGE (µV)

1.5

0.5

WARM-UP TIME (Minutes)

2.0

0

01

1.0

432 5

00775-0-009

Figure 9. Change in Input Offset Voltage vs. Warm-Up Time

FREQUENCY (Hz)

1000

11 100k

100

10

10k1k100

VOLTAGE NOISE (nV/ Hz)

GAIN = 1

GAIN = 10

10

GAIN = 100, 1,000 GAIN = 1000

BW LIMIT

00775-0-010

Figure 10. Voltage Noise Spectral Density vs. Frequency (G = 1−1000)

AD620

Rev. G | Page 8 of 20

FREQUENCY (Hz)

1000

100

10110 1000

100

CURRENT NOISE (fA/ Hz)

00775-0-011

Figure 11. Current Noise Spectral Density vs. Frequency

RTI NOISE (2.0

µ

V/DIV)

TIME (1 SEC/DIV)

00775-0-012

Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)

RTI NOISE (0.1

µ

V/DIV)

TIME (1 SEC/DIV)

00775-0-013

Figure 13. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)

00775-0-014

Figure 14. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div

100

1000

AD620A

FET INPUT

IN-AMP

SOURCE RESISTANCE (

Ω

)

TOTAL DRIFT FROM 25

°

C TO 85

°

C, RTI (

µ

V)

100,000

101k 10M

10,000

10k 1M100k

00775-0-015

Figure 15. Total Drift vs. Source Resistance

FREQUENCY (Hz)

CMR (dB)

160

01M

80

40

1

60

0.1

140

100

120

100k10k1k10010

G = 1000

G = 100

G = 10

G = 1

20

00775-0-016

Figure 16. Typical CMR vs. Frequency, RTI, Zero to 1 kΩ Source Imbalance

AD620

Rev. G | Page 9 of 20

FREQUENCY (Hz)

PSR (dB)

160

1M

80

40

1

60

0.1

140

100

120

100k10k1k10010

20

G = 1000

G = 100

G = 10

G = 1

180

00775-0-017

Figure 17. Positive PSR vs. Frequency, RTI (G = 1−1000)

FREQUENCY (Hz)

PSR (dB)

160

1M

80

40

1

60

0.1

140

100

120

100k10k1k10010

20

180

G = 10

G = 100

G = 1

G = 1000

00775-0-018

Figure 18. Negative PSR vs. Frequency, RTI (G = 1−1000)

1000

100 10M

100

1

1k

10

100k 1M10k

FREQUENCY (Hz)

GAIN (V/V)

0.1

00775-0-019

Figure 19. Gain vs. Frequency

OUTPUT VOLTAGE (V p-p)

FREQUENCY (Hz)

35

01M

15

5

10k

10

1k

30

20

25

100k

G = 10, 100, 1000

G = 1

G = 1000 G = 100

BW LIMIT

00775-0-020

Figure 20. Large Signal Frequency Response

INPUT VOLTAGE LIMIT (V)

(REFERRED TO SUPPLY VOLTAGES)

20

+1.0

+0.5

50

+1.5

–1.5

–1.0

–0.5

1510

SUPPLY VOLTAGE

± Volts

+V

S

–0.0

–V

S

+0.0

00775-0-021

Figure 21. Input Voltage Range vs. Supply Voltage, G = 1

20

+1.0

+0.5

5

0

+1.5

–1.5

–1.0

–0.5

1510

SUPPLY VOLTAGE ± Volts

R

L

= 10k

Ω

R

L

= 2k

Ω

R

L

= 10k

Ω

OUTPUT VOLTAGE SWING (V)

(REFERRED TO SUPPLY VOLTAGES)

R

L

= 2k

Ω

+V

S

–V

S

00775-0-022

–0.0

+0.0

Figure 22. Output Voltage Swing vs. Supply Voltage, G = 10

AD620

Rev. G | Page 10 of 20

OUTPUT VOLTAGE SWING (V p-p)

LOAD RESISTANCE (

Ω)

30

0010k

20

10

100 1k

V

S

= ±15V

G = 10

00775-0-023

Figure 23. Output Voltage Swing vs. Load Resistance

........................................

00775-0-024

Figure 24. Large Signal Pulse Response and Settling Time

G = 1 (0.5 mV = 0.01%)

........................................

00775-0-025

Figure 25. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF

........................................

00775-0-026

Figure 26. Large Signal Response and Settling Time, G = 10 (0.5 mV = 0.01%)

........................................

00775-0-027

Figure 27. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF

........................................

00775-0-030

Figure 28. Large Signal Response and Settling Time, G = 100 (0.5 mV = 0.01%)

AD620

Rev. G | Page 11 of 20

........................................

00775-0-029

Figure 29. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF

........................................

00775-0-030

Figure 30. Large Signal Response and Settling Time,

G = 1000 (0.5 mV = 0.01% )

........................................

00775-0-031

Figure 31. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF

OUTPUT STEP SIZE (V)

SETTLING TIME (µs)

TO 0.01%

TO 0.1%

20

002

15

5

10

10 0

15

00775-0-032

Figure 32. Settling Time vs. Step Size (G = 1)

GAIN

SETTLING TIME

(

µ

s)

1000

11 1000

100

10

10 100

00775-0-033

Figure 33. Settling Time to 0.01% vs. Gain, for a 10 V Step

........................................

00775-0-034

Figure 34. Gain Nonlinearity, G = 1, RL = 10 kΩ (10 µV = 1 ppm)

AD620

Rev. G | Page 12 of 20

........................................

00775-0-035

Figure 35. Gain Nonlinearity, G = 100, RL = 10 kΩ

(100 µV = 10 ppm)

........................................

00775-0-036

Figure 36. Gain Nonlinearity, G = 1000, RL = 10 kΩ

(1 mV = 100 ppm)

AD620

V

OUT

G=1

G = 1000

49.9

Ω

10k

Ω

*1k

Ω

10T 10k

Ω

499

Ω

G=10

G=100

5.49k

Ω

+V

S

11k

Ω

1k

Ω

100

Ω

100k

Ω

INPUT

10V p-p

–V

S

*ALL RESISTORS 1% TOLERANCE

7

1

2

3

8

6

4

5

00775-0-037

Figure 37. Settling Time Test Circuit

AD620

Rev. G | Page 13 of 20

THEORY OF OPERATION

V

B

–V

S

A1 A2

A3

C2

R

G

R1 R2

GAIN

SENSE GAIN

SENSE

R3

400Ω

10kΩ

I2

I1

10kΩREF

10kΩ

+IN

– IN

20µA20µA

R4

400Ω

OUTPUT

C1

Q2

Q1

00775-0-038

Figure 38. Simplified Schematic of AD620

The AD620 is a monolithic instrumentation amplifier based on

a modification of the classic three op amp approach. Absolute

value trimming allows the user to program gain accurately

(to 0.15% at G = 100) with only one resistor. Monolithic

construction and laser wafer trimming allow the tight matching

and tracking of circuit components, thus ensuring the high level

of performance inherent in this circuit.

The input transistors Q1 and Q2 provide a single differential-

pair bipolar input for high precision (Figure 38), yet offer 10×

lower input bias current thanks to Superϐeta processing.

Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop

maintains constant collector current of the input devices Q1

and Q2, thereby impressing the input voltage across the external

gain setting resistor RG. This creates a differential gain from the

inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1. The

unity-gain subtractor, A3, removes any common-mode signal,

yielding a single-ended output referred to the REF pin potential.

The value of RG also determines the transconductance of the

preamp stage. As RG is reduced for larger gains, the

transconductance increases asymptotically to that of the input

transistors. This has three important advantages: (a) Open-loop

gain is boosted for increasing programmed gain, thus reducing

gain related errors. (b) The gain-bandwidth product

(determined by C1 and C2 and the preamp transconductance)

increases with programmed gain, thus optimizing frequency

response. (c) The input voltage noise is reduced to a value of

9 nV/√Hz, determined mainly by the collector current and base

resistance of the input devices.

The internal gain resistors, R1 and R2, are trimmed to an

absolute value of 24.7 kΩ, allowing the gain to be programmed

accurately with a single external resistor.

The gain equation is then

1

4.49 +

Ω

=

G

R

k

G

1

4.49

−

Ω

=G

k

RG

Make vs. Buy: a Typical Bridge Application Error Budget

The AD620 offers improved performance over “homebrew”

three op amp IA designs, along with smaller size, fewer

components, and 10× lower supply current. In the typical

application, shown in Figure 39, a gain of 100 is required to

amplify a bridge output of 20 mV full-scale over the industrial

temperature range of −40°C to +85°C. Table 3 shows how to

calculate the effect various error sources have on circuit

accuracy.

AD620

Rev. G | Page 14 of 20

Regardless of the system in which it is being used, the AD620

provides greater accuracy at low power and price. In simple

systems, absolute accuracy and drift errors are by far the most

significant contributors to error. In more complex systems

with an intelligent processor, an autogain/autozero cycle will

remove all absolute accuracy and drift errors, leaving only the

resolution errors of gain, nonlinearity, and noise, thus allowing

full 14-bit accuracy.

Note that for the homebrew circuit, the OP07 specifications for

input voltage offset and noise have been multiplied by √2. This

is because a three op amp type in-amp has two op amps at its

inputs, both contributing to the overall input error.

R = 350

Ω

10V

PRECISION BRIDGE TRANSDUCE

R

R = 350

Ω

R = 350

Ω

R = 350

Ω

00775-0-039

AD620A MONOLITHIC

INSTRUMENTATION

AMPLIFIER, G = 100

SUPPLY CURRENT = 1.3mA MAX

AD620A

R

G

499

Ω

REFERENCE

00775-0-040

Figure 39. Make vs. Buy

"HOMEBREW" IN-AMP, G = 100

*0.02% RESISTOR MATCH, 3ppm/

°

C TRACKING

**DISCRETE 1% RESISTOR, 100ppm/

°

C TRACKING

SUPPLY CURRENT = 15mA MAX

100

Ω

**

10k

Ω

*

10k

Ω

**

10k

Ω

*

10k

Ω

*

10k

Ω

**

10k

Ω

*

OP07D

00775-0-041

Table 3. Make vs. Buy Error Budget

Error, ppm of Full Scale

Error Source AD620 Circuit Calculation “Homebrew” Circuit Calculation AD620 Homebrew

ABSOLUTE ACCURACY at TA = 25°C

Input Offset Voltage, µV 125 µV/20 mV (150 µV × √2)/20 mV 6,250 10,607

Output Offset Voltage, µV 1000 µV/100 mV/20 mV ((150 µV × 2)/100)/20 mV 500 150

Input Offset Current, nA 2 nA ×350 Ω/20 mV (6 nA ×350 Ω)/20 mV 18 53

CMR, dB 110 dB(3.16 ppm) ×5 V/20 mV (0.02% Match × 5 V)/20 mV/100 791 500

Total Absolute Error 7,559 11,310

DRIFT TO 85°C

Gain Drift, ppm/°C (50 ppm + 10 ppm) ×60°C 100 ppm/°C Track × 60°C 3,600 6,000

Input Offset Voltage Drift, µV/°C 1 µV/°C × 60°C/20 mV (2.5 µV/°C × √2 × 60°C)/20 mV 3,000 10,607

Output Offset Voltage Drift, µV/°C 15 µV/°C × 60°C/100 mV/20 mV (2.5 µV/°C × 2 × 60°C)/100 mV/20 mV 450 150

Total Drift Error 7,050 16,757

RESOLUTION

Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 40 40

Typ 0.1 Hz to 10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV (0.38 µV p-p × √2)/20 mV 14 27

Total Resolution Error 54 67

Grand Total Error 14,663 28,134

G = 100, VS = ±15 V.

(All errors are min/max and referred to input.)

AD620

Rev. G | Page 15 of 20

3k

Ω

5V

DIGITAL

DATA

OUTPUT

ADC

REF

IN

AGND

20k

Ω

10k

Ω

20k

Ω

AD620B

G = 100

1.7mA 0.10mA 0.6mA

MAX

499

Ω

3k

Ω

3k

Ω

3k

Ω

2

1

8

37

6

5

4

1.3mA

MAX

AD705

00775-0-042

Figure 40. A Pressure Monitor Circuit that Operates on a 5 V Single Supply

Pressure Measurement

Although useful in many bridge applications, such as weigh

scales, the AD620 is especially suitable for higher resistance

pressure sensors powered at lower voltages where small size and

low power become more significant.

Figure 40 shows a 3 kΩ pressure transducer bridge powered

from 5 V. In such a circuit, the bridge consumes only 1.7 mA.

Adding the AD620 and a buffered voltage divider allows the

signal to be conditioned for only 3.8 mA of total supply current.

Small size and low cost make the AD620 especially attractive for

voltage output pressure transducers. Since it delivers low noise

and drift, it will also serve applications such as diagnostic

noninvasive blood pressure measurement.

Medical ECG

The low current noise of the AD620 allows its use in ECG

monitors (Figure 41) where high source resistances of 1 MΩ or

higher are not uncommon. The AD620’s low power, low supply

voltage requirements, and space-saving 8-lead mini-DIP and

SOIC package offerings make it an excellent choice for battery-

powered data recorders.

Furthermore, the low bias currents and low current noise,

coupled with the low voltage noise of the AD620, improve the

dynamic range for better performance.

The value of capacitor C1 is chosen to maintain stability of

the right leg drive loop. Proper safeguards, such as isolation,

must be added to this circuit to protect the patient from

possible harm.

G = 7

AD620A

0.03Hz

HIGH-

PASS

FILTER

OUTPUT

1V/mV

+3V

–3V

R

G

8.25k

Ω

24.9k

Ω

24.9k

Ω

AD705J

G = 143

C1

1M

Ω

R4

10k

Ω

R1 R3

R2

OUTPUT

AMPLIFIER

PATIENT/CIRCUIT

PROTECTION/ISOLATION

00775-0-043

Figure 41. A Medical ECG Monitor Circuit

AD620

Rev. G | Page 16 of 20

Precision V-I Converter

The AD620, along with another op amp and two resistors,

makes a precision current source (Figure 42). The op amp

buffers the reference terminal to maintain good CMR. The

output voltage, VX, of the AD620 appears across R1, which

converts it to a current. This current, less only the input bias

current of the op amp, then flows out to the load.

AD620

R

G

–V

S

V

IN+

V

IN–

LOAD

R1

I

L

V

x

I =

L

R1 =

IN+

[(V ) – (V )] G

IN–

R1

6

5

+ V –

X

4

2

1

8

37

+V

S

AD705

00775-0-044

Figure 42. Precision Voltage-to-Current Converter (Operates on 1.8 mA, ±3 V)

GAIN SELECTION

The AD620’s gain is resistor-programmed by RG, or more

precisely, by whatever impedance appears between Pins 1 and 8.

The AD620 is designed to offer accurate gains using 0.1% to 1%

resistors. Table 4 shows required values of RG for various gains.

Note that for G = 1, the RG pins are unconnected (RG = ∞). For

any arbitrary gain, RG can be calculated by using the formula:

1

4.49

−

Ω

=G

k

RG

To minimize gain error, avoid high parasitic resistance in series

with RG; to minimize gain drift, RG should have a low TC—less

than 10 ppm/°C—for the best performance.

Table 4. Required Values of Gain Resistors

1% Std Table

Value of RG(Ω)

Calculated

Gain

0.1% Std Table

Value of RG(Ω )

Calculated

Gain

49.9 k 1.990 49.3 k 2.002

12.4 k 4.984 12.4 k 4.984

5.49 k 9.998 5.49 k 9.998

2.61 k 19.93 2.61 k 19.93

1.00 k 50.40 1.01 k 49.91

499 100.0 499 100.0

249 199.4 249 199.4

100 495.0 98.8 501.0

49.9 991.0 49.3 1,003.0

INPUT AND OUTPUT OFFSET VOLTAGE

The low errors of the AD620 are attributed to two sources,

input and output errors. The output error is divided by G when

referred to the input. In practice, the input errors dominate at

high gains, and the output errors dominate at low gains. The

total VOS for a given gain is calculated as

Total Error RTI = input error + (output error/G)

Total Error RTO = (input error × G) + output error

REFERENCE TERMINAL

The reference terminal potential defines the zero output voltage

and is especially useful when the load does not share a precise

ground with the rest of the system. It provides a direct means of

injecting a precise offset to the output, with an allowable range

of 2 V within the supply voltages. Parasitic resistance should be

kept to a minimum for optimum CMR.

INPUT PROTECTION

The AD620 features 400 Ω of series thin film resistance at its

inputs and will safely withstand input overloads of up to ±15 V

or ±60 mA for several hours. This is true for all gains and power

on and off, which is particularly important since the signal

source and amplifier may be powered separately. For longer

time periods, the current should not exceed 6 mA

(IIN ≤ VIN/400 Ω). For input overloads beyond the supplies,

clamping the inputs to the supplies (using a low leakage diode

such as an FD333) will reduce the required resistance, yielding

lower noise.

RF INTERFERENCE

All instrumentation amplifiers rectify small out of band signals.

The disturbance may appear as a small dc voltage offset. High

frequency signals can be filtered with a low pass R-C network

placed at the input of the instrumentation amplifier. Figure 43

demonstrates such a configuration. The filter limits the input

signal according to the following relationship:

)2(2

1

C

D

DIFF CCR

FilterFreq +π

=

C

CM RC

FilterFreq π

=2

1

where CD ≥10CC.

CD affects the difference signal. CC affects the common-mode

signal. Any mismatch in R × CC will degrade the AD620’s

CMRR. To avoid inadvertently reducing CMRR-bandwidth

performance, make sure that CC is at least one magnitude

smaller than CD. The effect of mismatched CCs is reduced with a

larger CD:CC ratio.

AD620

Rev. G | Page 17 of 20

499Ω

AD620

+

–

V

OUT

R

C

D

C

+IN

–IN REF

–15V

0.1µF1µF0

+15V

0.1µF1µF0

00775-0-045

Figure 43. Circuit to Attenuate RF Interference

COMMON-MODE REJECTION

Instrumentation amplifiers, such as the AD620, offer high

CMR, which is a measure of the change in output voltage when

both inputs are changed by equal amounts. These specifications

are usually given for a full-range input voltage change and a

specified source imbalance.

For optimal CMR, the reference terminal should be tied to a

low impedance point, and differences in capacitance and

resistance should be kept to a minimum between the two

inputs. In many applications, shielded cables are used to

minimize noise; for best CMR over frequency, the shield

should be properly driven. Figure 44 and Figure 45 show active

data guards that are configured to improve ac common-mode

rejections by “bootstrapping” the capacitances of input cable

shields, thus minimizing the capacitance mismatch between the

inputs.

REFERENCE

V

OUT

AD620

100

Ω

100

Ω

– INPUT

+ INPUT

AD648

R

G

–V

S

+V

S

–V

S

00775-0-046

Figure 44. Differential Shield Driver

100Ω

– INPUT

+ INPUT

REFERENCE

V

OUT

AD620

–V

S

+V

S

2

R

G

2

R

G

AD548

00775-0-047

Figure 45. Common-Mode Shield Driver

GROUNDING

Since the AD620 output voltage is developed with respect to the

potential on the reference terminal, it can solve many

grounding problems by simply tying the REF pin to the

appropriate “local ground.”

To isolate low level analog signals from a noisy digital

environment, many data-acquisition components have separate

analog and digital ground pins (Figure 46). It would be

convenient to use a single ground line; however, current

through ground wires and PC runs of the circuit card can cause

hundreds of millivolts of error. Therefore, separate ground

returns should be provided to minimize the current flow from

the sensitive points to the system ground. These ground returns

must be tied together at some point, usually best at the ADC

package shown in Figure 46.

DIGITAL P.S.

+5VC

ANALOG P.S.

+15V C –15V

AD574A DIGITAL

DATA

OUTPUT

+

1

µ

F

AD620

0.1

µ

F

AD585

S/H ADC

0.1

µ

F

1

µ

F1

µ

F

00775-0-048

Figure 46. Basic Grounding Practice

AD620

Rev. G | Page 18 of 20

GROUND RETURNS FOR INPUT BIAS CURRENTS

Input bias currents are those currents necessary to bias the

input transistors of an amplifier. There must be a direct return

path for these currents. Therefore, when amplifying “floating”

input sources, such as transformers or ac-coupled sources, there

must be a dc path from each input to ground, as shown in

Figure 47, Figure 48, and Figure 49. Refer to A Designer’s Guide

to Instrumentation Amplifiers (free from Analog Devices) for

more information regarding in-amp applications.

V

OUT

AD620

– INPUT

R

G

TO POWER

SUPPLY

GROUND

REFERENCE

+ INPUT

+V

S

–V

S

LOAD

00775-0-049

Figure 47. Ground Returns for Bias Currents with Transformer-Coupled Inputs

V

OUT

– INPUT

+ INPUT

R

G

LOAD

TO POWER

SUPPLY

GROUND

REFERENCE

+V

S

–V

S

AD620

00775-0-050

Figure 48. Ground Returns for Bias Currents with Thermocouple Inputs

100k

Ω

VOUT

AD620

– INPUT

+ INPUT

RG

LOAD

TO POWER

SUPPLY

GROUND

REFERENCE

100k

Ω

–VS

+VS

00775-0-051

Figure 49. Ground Returns for Bias Currents with AC-Coupled Inputs

AD620

Rev. G | Page 19 of 20

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-001-BA

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

SEATING

PLANE

0.015

(0.38)

MIN

0.210

(5.33)

MAX

PIN 1

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

8

14

5

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.100 (2.54)

BSC

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

0.060 (1.52)

MAX

0.430 (10.92)

MAX

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.015 (0.38)

GAUGE

PLANE

0.005 (0.13)

MIN

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body (N-8).

Dimensions shown in inches and (millimeters)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

14

85

0.310 (7.87)

0.220 (5.59)

PIN 1

0.005 (0.13)

MIN 0.055 (1.40)

MAX

0.100 (2.54) BSC

15°

0°

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

SEATING

PLANE

0.200 (5.08)

MAX

0.405 (10.29) MAX

0.150 (3.81)

MIN

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36) 0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)

Figure 51. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8)

Dimensions shown in inches and (millimeters)

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)× 45°

8°

0°

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

41

85

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)

BSC

6.20 (0.2440)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012AA

Figure 52. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

AD620

Rev. G | Page 20 of 20

ORDERING GUIDE

Model Temperature Range Package Option1

AD620AN −40°C to +85°C N-8

AD620ANZ2 −40°C to +85°C N-8

AD620BN −40°C to +85°C N-8

AD620BNZ2 −40°C to +85°C N-8

AD620AR −40°C to +85°C R-8

AD620ARZ2 −40°C to +85°C R-8

AD620AR-REEL −40°C to +85°C 13" REEL

AD620ARZ-REEL2 −40°C to +85°C 13" REEL

AD620AR-REEL7 −40°C to +85°C 7" REEL

AD620ARZ-REEL72 −40°C to +85°C 7" REEL

AD620BR −40°C to +85°C R-8

AD620BRZ2 −40°C to +85°C R-8

AD620BR-REEL −40°C to +85°C 13" REEL

AD620BRZ-RL2 −40°C to +85°C 13" REEL

AD620BR-REEL7 −40°C to +85°C 7" REEL

AD620BRZ-R72 −40°C to +85°C 7" REEL

AD620ACHIPS −40°C to +85°C Die Form

AD620SQ/883B −55°C to +125°C Q-8

1 N = Plastic DIP; Q = CERDIP; R = SOIC.

2 Z = Pb-free part.

and registered trademarks are the property of their respective owners.

C00775–0–12/04(G)