ISL6612CBZAR5214 - Intersil - Datasheet.Directory

FN9159.7

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6612A, ISL6613A

Advanced Synchronous Rectified Buck

MOSFET Drivers with Pre-POR OVP

The ISL6612A and ISL6613A are high frequency MOSFET

drivers specifically designed to drive upper and lower power

N-Channel MOSFETs in a synchronous rectified buck

converter topology. These drivers combined with HIP63xx or

ISL65xx Multi-Phase Buck PWM controllers and N-C hannel

MOSFETs form complete core-voltage regulator solutions for

advanced microprocessors.

The ISL6612A drives the upper gate to 12V, while the lower

gate can be independently driven ove r a range from 5V to

12V. The ISL6613 A drives both upper and lower gates over

a range of 5V to 12V. This drive-voltage provides the

flexibility necessary to optimi ze applications involving

trade-offs between gate charge and conduction losses.

An advanced adaptive zero shoot-through protecti on is

integrated to prevent both the upper and lower MOSFETs

from conducting simultaneously and to minimize th e dead

time. These products add an overvoltage protecti on feature

operational before VCC exceeds its turn-on threshold, at

which the PHASE node is connected to the gate of the low

side MOSFET (LGATE). The output voltage of the converter

is then limited by the threshold of the low side MOSFET,

which provides some protection to the microprocessor if the

upper MOSFET(s) is shorted during initial startup.

These drivers also feature a three-state PWM input which,

working together with Intersil’s multi-phase PWM controllers,

prevents a negative transient on the output voltage when the

output is shut down. This feature elimi n at es the Schottky

diode that is used in some systems for protecting the load

from reversed output voltage events.

Features

• Pin-to-pin Compatible with HIP6601 SOIC family

• Dual MOSFET Drives for Synchronous Rectified Bridge

• Advanced Adaptive Zero Shoot-T hrough Protection

- Body Diode Detection

- Auto-zero of rDS(ON) Conduction Offset Effect

• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency

• 36V Internal Bootstrap Schottky Diode

• Bootstrap Capacitor Overcharging Prevention

• Supports High Switching Frequency (u p to 2MHz)

- 3A Sinking Current Capability

- Fast Rise/F all Times and Low Propagation Delays

• Three-State PWM Input fo r Output Stage Shutdown

• Three-State PWM Input Hysteresis for Applications with

Power Sequencing Requirement

• Pre-POR Overvoltage Protection

• VCC Undervoltage Protection

• Expandable Bottom Copper Pad for Enhanced Heat

Sinking

• Dual Flat No-Lead (DFN) Package

- Near Chip-Scale Package Footprint; Improves PCB

Efficiency and Thinner in Profile

• Pb-Free (RoHS Compliant)

Applications

• Core Regulators for Intel® and AMD® Microprocessors

• High Current DC/DC Converters

• High Frequency and High Efficiency VRM and VRD

Related Literature

• Technical Brief TB363 “Guidelines for Handli ng and

Processing Moisture Sensitive Surface Mo unt Devices

(SMDs)”

• Technical Brief TB417 for Power Train Design, Layout

Guidelines, and Feedback Compe nsation Design

Data Sheet May 1, 2012

2FN9159.7

May 1, 2012

Ordering Information

PART NUMBER

(Notes 2, 3) PART MARKING TEMP.

RANGE (°C) PACKAGE

(Pb-free) PKG.

DWG. #

ISL6612ACBZ 6612 ACBZ 0 to +85 8 Ld SOIC M8.15

ISL6612ACBZ-T (Note 1) 6612 ACBZ 0 to +85 8 Ld SOIC Tape and Reel M8.15

ISL6612ACBZA 6612 ACBZ 0 to +85 8 Ld SOIC M8.15

ISL6612ACBZA-T (Note 1) 6612 ACBZ 0 to +85 8 Ld SOIC Tape and Reel M8.15

ISL6612ACRZ 12AZ 0 to +85 10 Ld 3x3 DFN L10.3x3

ISL6612ACRZ-T (Note 1) 12AZ 0 to +85 10 Ld 3x3 DFN Tape and Reel L10.3x3

ISL6612AECBZ 6612 AECBZ 0 to +85 8 Ld EPSOIC M8.15B

ISL6612AECBZ-T (Note 1) 6612 AECBZ 0 to +85 8 Ld EPSOIC Tape and Reel M8.15B

ISL6612AEIBZ 6612 AEIBZ -40 to +85 8 Ld EPSOIC M8.15B

ISL6612AEIBZ-T (Note 1) 6612 AEIBZ -40 to +85 8 Ld EPSOIC Tape and Reel M8.15B

ISL6612AIBZ 6612 AIBZ -40 to +85 8 Ld SOIC M8.15

ISL6612AIBZ-T (Note 1) 6612 AIBZ -40 to +85 8 Ld SOIC Tape and Reel M8.15

ISL6612AIRZ 2AIZ -40 to +85 10 Ld 3x3 DFN L10.3x3

ISL6612AIRZ-T (Note 1) 2AIZ -40 to +85 10 Ld 3x3 DFN Tape and Reel L10.3x3

ISL6613ACBZ 6613 ACBZ 0 to +85 8 Ld SOIC M8.15

ISL6613ACBZ-T (Note 1) 6613 ACBZ 0 to +85 8 Ld SOIC Tape and Reel M8.15

ISL6613ACRZ 13AZ 0 to +85 10 Ld 3x3 DFN L10.3x3

ISL6613ACRZ-T (Note 1) 13AZ 0 to +85 10 Ld 3x3 DFN Tape and Reel L10.3x3

ISL6613AECBZ 6613 AECBZ 0 to +85 8 Ld EPSOIC M8.15B

ISL6613AECBZ-T (Note 1) 6613 AECBZ 0 to +85 8 Ld EPSOIC Tape and Reel M8.15B

ISL6613AEIBZ 6613 AEIBZ -40 to +85 8 Ld EPSOIC M8.15B

ISL6613AEIBZ-T (Note 1) 6613 AEIBZ -40 to +85 8 Ld EPSOIC Tape and Reel M8.15B

ISL6613AIBZ 6613 AIBZ -40 to +85 8 Ld SOIC M8.15

ISL6613AIBZ-T (Note 1) 6613 AIBZ -40 to +85 8 Ld SOIC Tape and Reel M8.15

ISL6613AIRZ 3AIZ -40 to +85 10 Ld 3x3 DFN L10.3x3

ISL6613AIRZ-T (Note 1) 3AIZ -40 to +85 10 Ld 3x3 DFN Tape and Reel L10.3x3

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic p ackaged product s employ special Pb-free material se ts , mold ing compound s/die att ach materials , and 10 0% matte

tin plate plus ann eal (e3 termination f inish, which is RoHS compliant a nd comp atible with both SnPb and Pb-free so ldering operations). Intersil Pb-

free products are MSL cla ssified at Pb-free pea k reflow temperatu res that meet or exceed the Pb-free requiremen t s of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6612A, ISL6613A. For more information on

MSL please see tech brie f TB363.

ISL6612A, ISL6613A

3FN9159.7

May 1, 2012

Pinouts

ISL6612ACB, ISL6612AIB, ISL6613ACB, ISL6613AIB (SOIC)

ISL6612AECB, ISL6612AEIB, ISL6613AECB, ISL 6613AEIB

(EPSOIC)

TOP VIEW

ISL6612ACR, ISL6612AIR, ISL6613ACR, ISL6613AIR

(10 LD 3x3 DFN)

TOP VIEW

UGATE

BOOT

PWM

GND

PHASE

PVCC

VCC

LGATE

GND

UGATE

BOOT

N/C

PWM

PHASE

PVCC

N/C

VCC

GND

6LGATE

GND

Block Diagram ISL6612A AND ISL6613A

PVCC

VCC

PWM

+5V

10k

BOOT

UGATE

PHASE

LGATE

GND

FOR DFN AND EPSOIC-DEVICES, THE PAD ON THE BOTTOM SIDE OF

PAD THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.

UVCC = VCC FOR ISL6612A

CONTROL

LOGIC

POR/

SHOOT-

THROUGH

PROTECTION

Pre-POR OVP

(LVCC)

UVCC = PVCC FOR ISL661 3A

UVCC

FEATURES

ISL6612A, ISL6613A

4FN9159.7

May 1, 2012

Typical Application - 3 Channel Converte r Using ISL65xx and ISL6612A Gate Drivers

BOOT

UGATE

PHASE

LGATE

PWM

PVCC

+12V

BOOT

UGATE

PHASE

LGATE

PWM

PVCC

VCC

+12V

BOOT

UGATE

PHASE

LGATE

PWM

PVCC

+12V

+VCORE

PGOOD

VID

GND

ISEN3

ISEN2

ISEN1

PWM3

PWM2

PWM1

VSEN

MAIN

VFB VCC

+5V

COMP

ISL6612A

CONTROL

ISL65xx

VCC

ISL6612A

VCC

ISL6612A

GND

+5V TO 12V

ISL6612A, ISL6613A

5FN9159.7

May 1, 2012

Absolute Maximum Ratings Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V

BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . . . . . . . 36V

Input Voltage (VPWM). . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V

UGATE. . . . . . . . . . . . . . . . . . . VPHASE - 0.3VDC to VBOOT + 0.3V

VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V

LGATE . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to VPVCC + 0.3V

GND - 5V (<100ns Pulse Width, 2µJ) to VPVCC + 0.3V

PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3VDC to 24VDC

GND - 8V (<400ns, 20µJ) to 31V (<200ns, VBOOT-GND<36V)

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . .Class I JEDEC STD

Thermal Resistance θJA (°C/W) θJC (°C/W)

SOIC Package (Note 1). . . . . . . . . . . . 100 N/A

EPSOIC Package (Notes 2, 3) . . . . . . 50 7

DFN Package (Notes 2, 3). . . . . . . . . . 48 7

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

(SOIC - Lead Tips Only)

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . -40°C to +85°C

Maximum Operating Junction Temperature . . . . . . . . . . . . +125°C

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V ±10%

Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . 5V to 12V ±10%

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See T ech

Brief TB379.

6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.

PARAMETER SYMBOL TEST CONDITIONS MIN

(Note 8) TYP MAX

(N ote 8) UNITS

VCC SUPPLY CURRENT

Bias Supply Current IVCC ISL6612A, fPWM = 300kHz, VVCC = 12V - 7.2 - mA

ISL6613A, fPWM = 300kHz, VVCC = 12V - 4.5 - mA

IVCC ISL6612A, fPWM = 1MHz, VVCC = 12V - 11 - mA

ISL6613A, fPWM = 1MHz, VVCC = 12V - 5 - mA

Gate Drive Bias Current IPVCC ISL6612A, fPWM = 300kHz, VPVCC = 12V - 2.5 - mA

ISL6613A, fPWM = 300kHz, VPVCC = 12V - 5.2 - mA

IPVCC ISL6612A, fPWM = 1MHz, VPVCC = 12V - 7 - mA

ISL6613A, fPWM = 1MHz, VPVCC = 12V - 13 - mA

POWER-ON RESET AND ENABLE

VCC Rising Threshold TA = 0°C to +85°C 9.35 9.80 10.00 V

VCC Rising Threshold TA = -40°C to +85°C 8.35 9.80 10.00 V

VCC Falling Threshold TA = 0°C to +85°C 7.35 7.60 8.00 V

VCC Falling Threshold TA = -40°C to +85°C 6.35 7.60 8.00 V

PWM INPUT (See “TIMING DIAGRAM” on page 7.)

Input Current IPWM VPWM = 5V - 450 - µA

VPWM = 0V - -400 - µA

PWM Rising Threshold VCC = 12V - 3.00 - V

PWM Falling Threshold VCC = 12V - 2.00 - V

Typical Three-State Shutdown Window VCC = 12V 1.80 - 2.40 V

Three-State Lower Gate Falling Threshold VCC = 12V - 1.50 - V

Three-State Lower Gate Rising Threshold VCC = 12V - 1.00 - V

Three-State Upper Gate Rising Threshold VCC = 12V - 3.20 - V

ISL6612A, ISL6613A

6FN9159.7

May 1, 2012

Three-State Upper Gate Falling Threshold VCC = 12V - 2.60 - V

Shutdown Holdoff Time tTSSHD - 245 - ns

UGATE Rise Time tRU VPVCC = 12V, 3nF Load, 10% to 90% - 26 - ns

LGATE Rise Time tRL VPVCC = 12V, 3nF Load, 10% to 90% - 18 - ns

UGATE Fall Time tFU VPVCC = 12V, 3nF Load, 90% to 10% - 18 - ns

LGATE Fall Time tFL VPVCC = 12V, 3nF Load, 90% to 10% - 12 - ns

UGATE Turn-On Propagation Delay (Note 7) tPDHU VPVCC = 12V, 3nF Load, Adaptive - 10 - ns

LGATE Turn-On Propagation Delay (Note 7) tPDHL VPVCC = 12V, 3nF Load, Adaptive - 10 - ns

UGATE Turn-Off Propagation Delay (Note 7) tPDLU VPVCC = 12V, 3nF Load - 10 - ns

LGATE Turn-Off Propagation Delay (Note 7) tPDLL VPVCC = 12V, 3nF Load - 10 - ns

LG/UG Three-State Propagation Delay (Note 7) tPDTS VPVCC = 12V, 3nF Load - 10 - ns

OUTPUT (Note 7)

Upper Drive Source Current IU_SOURCE VPVCC = 12V, 3nF Load - 1.25 - A

Upper Drive Source Impedance RU_SOURCE 150mA Source Current 1.25 2.0 3.0 Ω

Upper Drive Sink Current IU_SINK VPVCC = 12V, 3nF Load - 2 - A

Upper Drive Transition Sink Impedance RU_SINK_TR 70ns With Respect To PWM Falling - 1.3 2.2 Ω

Upper Drive DC Sink Impedance RU_SINK_DC 150mA Source Current 0.9 1.65 3.0 Ω

Lower Drive Source Current IL_SOURCE VPVCC = 12V, 3nF Load - 2 - A

Lower Drive Source Impedance RL_SOURCE 150mA Source Current 0.85 1.25 2.2 Ω

Lower Drive Sink Current IL_SINK VPVCC = 12V, 3nF Load - 3 - A

Lower Drive Sink Impedance RL_SINK 150mA Sink Current 0.60 0.80 1.35 Ω

NOTES:

7. Limits should be considered typical and are not production tested.

8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization

and are not production tested.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN

(Note 8) TYP MAX

(N ote 8) UNITS

Functional Pin Description

PACKAGE PIN # PIN

SYMBOL FUNCTIONSOIC DFN

1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.

2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap

Device” on page 8 for guidance in choosing the capacitor value.

- 3, 8 N/C No Connection.

3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, See

“Three-State PWM Input” on page 7 for further details. Connect this pin to the PWM output of the controller.

4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.

5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.

6 7 VCC Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.

7 9 PVCC This pin supplies power to both upper and lower gate drives in ISL6613A; only the lower gate drive in ISL6612A. Its

operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin t o GND.

8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides a

return path for the upper gate drive.

9 11 P AD Connect this p ad to the power g round pl ane (GND) via the rmally enh anced conn ection.

ISL6612A, ISL6613A

7FN9159.7

May 1, 2012

Description

Operation

Designed for versatility and speed, the ISL6612A and

ISL6613A MOSFET drivers control both high-side and low-

side N-Channel FETs of a half-bridge power train from one

externally provided PWM signal.

Prior to VCC exceeding its POR level, the Pre-POR

overvoltage protection function is activated during initial startup;

the upper gate (UGATE) is held low and the lower gate

(LGATE), controlled by the Pre-POR overvoltage protection

circuits, is connected to the PHASE. Once the VCC voltage

surpasses the VCC Rising Threshold (See Electrical

S pecifications), the PWM signal takes control of gate

transitions. A rising edge on PWM initiates the turn-off of the

lower MOSFET (see Timing Diagram). After a short

propagation delay [tPDLL], the lower gate begins to fall. T ypical

fall times [tFL] are provided in the Electrical S pecifications

section. Adaptive shoot-through circuitry monitors the PHASE

voltage and determines the upper gate delay time [tPDHU]. This

prevents both the lower and upper MOSFETs from conducting

simultaneously. Once this delay period is complete, the upper

gate drive begins to rise [tRU] and the upper MOSFET turns on.

A falling transition on PWM results in the turn-of f of the upper

MOSFET and the turn-on of the lower MOSFET. A short

propagation delay [tPDLU] is encountered before the upper

gate begins to fall [tFU]. Again, the adaptive shoot-through

circuitry determines the lower ga te delay time, tPDHL. The

PHASE voltage an d the UGATE voltage are monitored, and

the lower gate is allowed to rise after PH ASE drop s below a

level or the voltage of UGATE to PHASE reaches a level

depending upon the current direction (See ne x t se c t io n fo r

details). The lower gate the n rises [tRL], turnin g on the lower

MOSFET.

Advanced Adaptive Zero Shoot-Through Deadtime

Control (Patent Pending)

These drivers incorporate a unique adaptive deadtime control

technique to minimize deadtime, resulting in high efficiency

from the reduced freewheeling time of the lower MOSFETs’

body-diode conduction, and to prevent the upper and lower

MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other has

turned off.

During turn-off of the lower MOS FET, the PHASE voltage is

monitored until it reaches a -0.2V/+0.8V trip point for a

forward/reverse current, at which time the UGATE is released

to rise. An auto-zero comparator is used to correct the rDS(ON)

drop in the phase voltage preventing from false detection of the

-0.2V phase level during rDS(ON conduction period. In the case

of zero current, the UGATE is released after 35ns delay of the

LGATE dropping below 0.5V. During the phase detection, the

disturbance of LGA TE’s falling transition on the PHASE node is

blanked out to prevent falsely tripping. Once the PHASE is

high, the advanced adaptive shoot-through circuitry monitors

the PHASE and UGATE voltages during a PWM falling edge

and the subsequent UGA TE turn-of f. If either the UGATE falls

to less than 1.75V above the PHASE or the PHASE falls to less

than +0.8V, the LGATE is released to turn on.

Three-State PWM Input

A unique feature of these drivers and other Intersil drivers is

the addition of a shutdown window to the PWM input. If the

PWM signal enters and remains within the shutdown window

for a set holdoff time, the driver outputs are disabled and

both MOSFET gates are pulled and held low. The shutdown

state is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

PWM

UGATE

LGATE

tFL

tPDHU

tPDLL

tRL tTSSHD

tPDTS

1.5V<PWM<3.2V 1.0V<PWM<2.6V

tFU

tRU

tPDLU

tPDHL

tTSSHD

FIGURE 1. TIMING DIAGRAM

ISL6612A, ISL6613A

8FN9159.7

May 1, 2012

thresholds (outlined in Electrical S pecifications on page 5) to

determine when the lower and upper gates are enabled.

This feature helps prevent a negative transient on the output

voltage when the output is shut down, eliminating the

Schottky diode that is used in some systems for protecting

the load from reversed output voltage events.

In addition, more than 400mV hysteresis also incorporates

into the three-state shutdown window to eliminate PWM

input oscill a ti on s due to the capacitive load seen by the

PWM input through the body diode of the controller’s PWM

output when the power-up and/or power -down sequence of

bias supplies of the driver and PWM controller are required.

Power-On Reset (POR) Fun ction

During initial startup, the VCC voltage rise is monitored.

Once the rising VCC voltage exceeds 9.8V (typically),

operation of the driver is enabled and the PWM input signal

takes control of the gate drives. If VCC drops below the

falling threshold of 7.6V (typically), operation of the driver is

disabled.

Pre-POR Overvoltage Protection

Prior to VCC exceeding its POR level, the upper gate is held

low and the lower gate is controlled by th e overvoltage

protection circuits during initial startup. The PHASE is

connected to the gate of the low side MOSFET (LGATE),

which provides some protection to the microprocessor if the

upper MOSFET(s) is shorted during initial startup. For

complete protection, the low side MOSFET should have a

gate threshold well below the maximum voltage rating of the

load/microprocessor.

When VCC drops below its POR level, both gates pull low

and the Pre-POR overvoltage protection circuits are not

activated until VCC resets.

Internal Bootstra p De vi ce

Both drivers feature an internal bootstrap schottky diode.

Simply adding an external capacitor across the BOOT and

PHASE pins completes the bootstrap circuit. The bootstrap

function is also designed to prevent the bootstrap capacitor

from overcharging due to the large negative swing at the

trailing-edge of the PHASE node. This reduces voltage

stress on the boot to phase pins.

The bootstrap capacitor must have a maximum voltage

rating above UVCC + 5V and its capacitance value can be

chosen from the following equation:

where QG1 is the amount of gate charge per upper MOSFET

at VGS1 gate-source voltage and NQ1 is the number of

control MOSFETs. The ΔVBOOT_CAP term is defined as the

allowable droop in the rail of the upper gate drive.

As an example, suppose two IRLR7821 FETs are chosen as

the upper MOSFETs. The gate charge, QG, from the data

sheet is 10nC at 4.5V (VGS) gate-source voltage. Then the

QGATE is calculated to be 53nC for UVCC (i.e. PVCC in

ISL6613A, VCC in ISL6612A) = 12V. We will assume a

200mV droop in drive voltage over the PWM cycle. We find

that a bootstrap capacitance of at least 0.267μF is required.

Gate Drive Voltage Versatility

The ISL6612A and ISL6613A prov ide the user flexibility in

choosing the gate drive voltage for efficiency optimization.

The ISL6612A upper gate drive is fixed to VCC [+12V], bu t

the lower drive rail can range fro m 12 V down to 5V

depending on what voltage is applied to PVCC. The

ISL6613A ties the upper and lower drive rails togeth er.

Simply applying a voltage from 5V up to 12V on PVCC sets

both gate drive rail voltages simultaneously.

Power Dissipation

Package powe r dis s ipation is mainly a function of the

switching frequency (FSW), the output drive impe dance, the

external gate resistance, and the selected MOSFET’s

internal gate resistance and total gate charge. Calculating

the power dissipation in the driver for a desired application is

critical to ensure safe operation. Exceeding the maximum

allowable power dissipation level will push the IC beyond the

maximum recommended operating junction temperature of

+125°C. The maximum allowa ble IC power dissipation for

the SO8 package is approximately 800mW at room

temperature, while the power dissipation capacity in the

EPSOIC and DFN packages, with an exposed heat escape

pad, is more than 2W and 1.5W, respectively. Both EPSOIC

and DFN packages are more suitable for high frequency

applications. See Layout Considerations paragraph for

CBOOT_CAP QGATE

ΔVBOOT_CAP

--------------------------------------

≥

QGATE QG1 UVCC•

VGS1

------------------------------------NQ1

•=

(EQ. 1)

50nC

20nC

FIGURE 2. BOOTSTRAP CAP ACITANCE vs BOOT RIPPLE

VOLTAGE

ΔVBOOT_CAP (V)

CBOOT_CAP (µF)

1.6

1.4

1.2

0.8

0.6

0.4

0.2

0.0 0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0

QGATE = 100nC

ISL6612A, ISL6613A

9FN9159.7

May 1, 2012

thermal transfer improvement suggestions. When designing

the driver into an application, it is recommended that the

following calculation is used to ensure safe operation at the

desired frequency for threshold s ou tlined in the

ELECTRICAL SPECIFICATIONS determine when the lower

and upper gates are enabled.

the selected MOSFETs. The total gate drive power losses

due to the gate charge of MOSFETs and the driver’s internal

circuitry and their corresponding average driver current can

be estimated with Equations 2 and 3, respectively,

where the gate charge (QG1 and QG2) is defined at a

particular gate to source voltage (VGS1and VGS2) in the

corresponding MOSFET datasheet; IQ is the driver’s total

quiescent current with no load at both drive outputs; NQ1

and NQ2 are number of upper and lower MOSFETs,

respectively; UVCC and LVCC are the drive voltages for

both upper and lower FETs, respectively. T he IQ*VCC

product is the quiescent power of the driver without

capacitive load and is typically 116mW at 300kHz.

The tot a l gate drive power losses are dissipated among the

resistive components along the transition path. The drive

resistance dissipates a portion of the total gate drive power

losses, the rest will be dissipated by the external gate

resistors (RG1 and RG2) and the internal gate resistors

(RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the

typical upper and lower gate drives turn-on transition path.

The power dissipation on the driver can be roughly

estimated as:

Layout Considerations

For heat spreading, place copper underneath the IC whether

it has an exposed pad or not. The copper area can be

extended beyond the bottom area of the IC and/or

connected to buried copper plane(s) with the r mal vias. This

combination of vias for vertical heat escape, extended

copper plane, and buried planes fo r heat spreading allows

the IC to achieve its full thermal potential.

Place each channel power component as close to each

other as possible to reduce PCB copper losses and PCB

parasitics: shortest distance between DRAINs of upper FETs

and SOURCEs of lower FETs; shortest distance between

DRAINs of lower FETs and the power ground. Thus, smaller

amplitudes of positive and negative ringing are on the

switching edges of the PHASE node. However , some sp ace

in between the power components is required for good

airflow. Th e traces from the drivers to the FETs should be

kept short and wide to reduce the inductance of the traces

and to promote clean drive signals.

PQg_TOT PQg_Q1 PQg_Q2 IQVCC•++=(EQ. 2)

PQg_Q1 QG1 UVCC2

•

VGS1

--------------------------------------- FSW

•NQ1

•=

PQg_Q2 QG2 LVCC2

•

VGS2

-------------------------------------- FSW

•NQ2

•=

IDR QG1 UVCC NQ1

••

VGS1

------------------------------------------------------QG2 LVCC NQ2

••

VGS2

-----------------------------------------------------

⎝⎠

⎜⎟

⎛⎞

FSW IQ

+•=

(EQ. 3)

PDR PDR_UP PDR_LOW IQVCC•++=(EQ. 4)

PDR_UP RHI1

RHI1 REXT1

-------------------------------------- RLO1

RLO1 REXT1

----------------------------------------

⎝⎠

⎜⎟

⎛⎞

PQg_Q1

---------------------

•=

PDR_LOW RHI2

RHI2 REXT2

-------------------------------------- RLO2

RLO2 REXT2

----------------------------------------

⎝⎠

⎜⎟

⎛⎞

PQg_Q2

---------------------

•=

REXT1 RG1 RGI1

NQ1

-------------

+= REXT2 RG2 RGI2

NQ2

-------------

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

RGI1

RG1

BOOT

RHI1 CDS

CGS

CGD

RLO1

PHASE

UVCC

LVCC

RGI2

RG2

RHI2 CDS

CGS

CGD

RLO2

ISL6612A, ISL6613A

10 FN9159.7

May 1, 2012

ISL6612A, ISL6613A

Package Outline Drawing

L10.3x3

10 LEAD DUAL FLAT PACKAGE (DFN)

Rev 6, 09/09

located within the zone indicated. The pin #1 indentifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.18mm and 0.30mm from the terminal tip.

Lead width applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1 994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

(4X) 0.10

INDEX AREA

PIN 1

PIN #1 INDEX AREA

SEATING PLANE

BASE PLANE

0.08

SEE DETAIL "X"

0.10 C

PACKAGE

1.00

0.20

8x 0.50

2.00

3.00

(10x 0.23 )

(8x 0.50)

2.00

1.60

(10 x 0.55)

3.00

0.05

0.20 REF

10 x 0.23

10x 0.35

1.60

OUTLINE

MAX

(4X) 0.10 AB

0.415

0.23

0.35

0.200

11 FN9159.7

May 1, 2012

ISL6612A, ISL6613A

Small Outline Exposed Pad Plastic Packages (EPSOIC)

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45o

H0.25(0.010) BM M

123

BOTTOM VIEW

TOP VIEW

SIDE VIEW

M8.15B

8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD

PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.056 0.066 1.43 1.68 -

A1 0.001 0.005 0.03 0.13 -

B 0.0138 0.0192 0.35 0.49 9

C 0.0075 0.0098 0.19 0.25 -

D 0.189 0.196 4.80 4.98 3

E 0.150 0.157 3.81 3.99 4

e 0.050 BSC 1.27 BSC -

H 0.230 0.244 5.84 6.20 -

h 0.010 0.016 0.25 0.41 5

L 0.016 0.035 0.41 0.89 6

N8 87

α0° 8° 0° 8° -

P - 0.094 - 2.387 11

P1 - 0.094 - 2.387 11

Rev. 5 8/10

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: INCH. Converted millimeter dimensions

are not necessarily exact.

11. Dimensions “P” and “P1” are thermal and/or electrical enhanced

variations. Values shown are maximum size of exposed pad

within lead count and body size.

12 FN9159.7

May 1, 2012

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

ISL6612A, ISL6613A

Small Outline Plastic Packages (SOIC)

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α0° 8° 0° 8° -

Rev. 1 6/05