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ISO71xxCC 4242-V
PK
Small-Footprint Low-Power Triple and Quad Channels Digital
Isolators
1 Features 3 Description
ISO7131, ISO7140, and ISO7141 devices provide
1• Maximum Signaling Rate: 50 Mbps (With 5-V galvanic isolation up to 2500 VRMS for 1 minute per
Supplies) UL and 4242 VPK per VDE. ISO7131 has three
• Robust Design With Integrated Noise Filter channels with two forward and one reverse-direction
• Default Output Low Option (Suffix F) channels. ISO7140 and ISO7141 are quad-channel
isolators; ISO7140 has four forward channels,
• Low Power Consumption, Typical ICC per Channel ISO7141 has three forward and one reverse-direction
(With 3.3-V Supplies): channels. These devices are capable of 50-Mbps
– ISO7131: 1.5 mA at 1 Mbps, maximum data rate with 5-V supplies and 40-Mbps
2.6 mA at 25 Mbps maximum data rate with 3.3-V or 2.7-V supplies, with
integrated filters on the inputs for noise-prone
– ISO7140: 1 mA at 1 Mbps, applications. The suffix F indicates that default output
2.3 mA at 25 Mbps state is low; otherwise, the default output state is high
– ISO7141: 1.3 mA at 1 Mbps, (see Table 3).
2.6 mA at 25 Mbps Each isolation channel has a logic input and output
• Low Propagation Delay: 23-ns Typical buffer separated by a silicon dioxide (SiO2) insulation
(3.3-V Supplies) barrier. Used with isolated power supplies, these
• Wide Temperature Range: –40°C to 125°C devices prevent noise currents on a data bus or other
• 50-kV/µs Transient Immunity, Typical circuits from entering the local ground and interfering
with or damaging sensitive circuitry. The devices
• Long Life With SiO2Isolation Barrier have TTL input thresholds and can operate from 2.7-
• Operates from 2.7-V, 3.3-V, and 5-V Supply and V, 3.3-V, and 5-V supplies. All inputs are 5-V tolerant
Logic Levels when supplied from a 2.7-V or 3.3-V supply.
• Small QSOP-16 Package Device Information(1)
• Safety and Regulatory Approvals PART NUMBER PACKAGE BODY SIZE (NOM)
– 2500-VRMS Isolation for 1 minute per UL 1577 ISO7131CC
– 4242-VPK Isolation per DIN V VDE V 0884-10 ISO7140CC
(VDE V 0884-10):2006-12, 566 VPK Working ISO7140FCC SSOP (16) 4.90 mm × 3.90 mm
Voltage ISO7141CC
– CSA Component Acceptance Notice 5A, IEC ISO7141FCC
60950-1 and IEC 61010-1 End Equipment
Standards (1) For all available packages, see the orderable addendum at
the end of the datasheet.
– CQC Certification per GB 4943.1-2011
Simplified Schematic
2 Applications
• General-Purpose Isolation
– Industrial Fieldbus
– Profibus
– Modbus™
– DeviceNet Data Buses
– RS-232, RS-485
– Serial Peripheral Interface
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
6.14 Supply Current: VCC1 and VCC2 at 2.7 V............... 11
1 Features.................................................................. 16.15 Typical Characteristics.......................................... 12
2 Applications ........................................................... 17 Parameter Measurement Information ................ 14
3 Description............................................................. 18 Detailed Description............................................ 16
4 Revision History..................................................... 28.1 Overview................................................................. 16
5 Pin Configuration and Functions......................... 48.2 Functional Block Diagram....................................... 16
6 Specifications......................................................... 58.3 Feature Description................................................. 17
6.1 Absolute Maximum Ratings ..................................... 58.4 Device Functional Modes........................................ 19
6.2 ESD Ratings.............................................................. 59 Application and Implementation ........................ 21
6.3 Recommended Operating Conditions....................... 59.1 Application Information............................................ 21
6.4 Thermal Information.................................................. 69.2 Typical Applications ................................................ 21
6.5 Power Dissipation Ratings........................................ 610 Power Supply Recommendations ..................... 25
6.6 Electrical Characteristics: VCC1 and VCC2 at 5 V
±10%.......................................................................... 611 Layout................................................................... 25
6.7 Electrical Characteristics: VCC1 and VCC2 at 3.3 V 11.1 Layout Guidelines ................................................. 25
±10%.......................................................................... 611.2 Layout Example .................................................... 25
6.8 Electrical Characteristics: VCC1 and VCC2 at 2.7 V ... 712 Device and Documentation Support................. 26
6.9 Switching Characteristics: VCC1 and VCC2 at 5 V 12.1 Documentation Support ........................................ 26
±10%.......................................................................... 712.2 Related Links ........................................................ 26
6.10 Switching Characteristics: VCC1 and VCC2 at 3.3 V 12.3 Trademarks........................................................... 26
±10%.......................................................................... 812.4 Electrostatic Discharge Caution............................ 26
6.11 Switching Characteristics: VCC1 and VCC2 at 2.7 V. 812.5 Glossary................................................................ 26
6.12 Supply Current: VCC1 and VCC2 at 5 V ±10% ......... 913 Mechanical, Packaging, and Orderable
6.13 Supply Current: VCC1 and VCC2 at 3.3 V ±10% .... 10 Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2013) to Revision F Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• VDE Standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12...................................................................... 1
Changes from Revision D (August 2013) to Revision E Page
• Changed From: 2500 VRMS Isolation for 1 minute per UL 1577 (Approval Pending) To: (Approved) ................................... 1
• Added note1 to the AVAILABLE OPTIONS table................................................................................................................. 17
• Changed Figure 15............................................................................................................................................................... 18
• Changed From: Basic Insulation To: Basic Insulation, Altitude ≤5000m, Tropical Climate, 250 VRMS maximum
working voltage in the Regulatory Information table ............................................................................................................ 19
• Changed File number: E181974 (approval pending) To: File number: E181974 in the Regulatory Information table........ 19
• Changed the title of Figure 21,Figure 22, and Figure 23 to include "PRBS 216 - 1"........................................................... 23
Changes from Revision C (July 2013) to Revision D Page
• Added Safety List item "GB 4943.1-2011 and GB 8898:2011 CQC Certification (Approval Pending)"................................. 1
• Added Figure 2..................................................................................................................................................................... 12
• Deleted "Product Preview" From the AVAILABLE OPTIONS table ..................................................................................... 17
• Changed the REGULATORY INFORMATION, added column for CQC.............................................................................. 19
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Changes from Revision B (June 2013) to Revision C Page
• Changed Feature From: ISO7140: TBD at 1 Mbps, TBD at 25 Mbps To: ISO7140: 1 mA at 1 Mbps, 2.3 mA at 25 Mbps.. 1
• Added text to the Description: "All inputs are 5V tolerant when supplied from a 2.7V or 3.3V supply."................................ 1
• Deleted the Product Status table............................................................................................................................................ 1
• Changed the SAFETY and REGULATORY APPROVALS.................................................................................................... 1
• Changed the ABSOLUTE MAXIMUM RATINGS table .......................................................................................................... 5
• Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. .............................................................. 7
• Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. ............................................................. 8
• Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. ............................................................. 8
• Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values......................................................................... 9
• Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values....................................................................... 10
• Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values....................................................................... 11
• Changed Figure 1 X-axis scale ............................................................................................................................................ 12
• Changed the AVAILABLE OPTIONS table........................................................................................................................... 17
Changes from Revision A (June 2013) to Revision B Page
• Changed device ISO7141CC From: Product Preview To: Released in the Product Status table......................................... 1
Changes from Original (April 2013) to Revision A Page
• Changed the Simplified Schematic, added ground symbols.................................................................................................. 1
• Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device.................................. 7
• Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device.................................. 8
• Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device.................................. 8
• Added Figure 3..................................................................................................................................................................... 12
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1
2
3
4
5
6
7
8
ISO7140
9
10
11
12
13
14
15
16
NC
INA
GND1
GND2
GND2
INB
INC
OUTA
OUTC
OUTB
EN
IND OUTD
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
INA
GND2
GND2
INB
OUTC
OUTA
INC
OUTB
NC
EN2
EN1
VCC1
GND1
GND1
VCC2
GND1
VCC1
NC
VCC2
ISO7131
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
INA
GND2
GND2
INB
INC
OUTA
OUTC
OUTB
IND
EN2
EN1
GND1
GND1
VCC1
OUTD
VCC2
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5 Pin Configuration and Functions
16-Pin
SSOP Package
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME ISO7131 ISO7140 ISO7141
Output enable. All output pins are enabled when EN is high or disconnected and
EN — 10 — I disabled when EN is low.
Output enable 1. Output pins on side-1 are enabled when EN1 is high or
EN1 7 — 7 I disconnected and disabled when EN1 is low.
Output enable 2. Output pins on side-2 are enabled when EN2 is high or
EN2 10 — 10 I disconnected and disabled when EN2 is low.
GND1 2,8 2,8 2,8 — Ground connection for VCC1
GND2 9,15 9,15 9,15 — Ground connection for VCC2
INA 3 3 3 I Input, channel A
INB 4 4 4 I Input, channel B
INC 12 5 5 I Input, channel C
IND — 6 11 I Input, channel D
NC 6,11 7 — — No Connect pins are floating with no internal connection
OUTA 14 14 14 O Output, channel A
OUTB 13 13 13 O Output, channel B
OUTC 5 12 12 O Output, channel C
OUTD — 11 6 O Output, channel D
VCC1 1 1 1 — Power supply, VCC1
VCC2 16 16 16 — Power supply, VCC2
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6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN MAX UNIT
VCC1, VCC2 Supply voltage(2) –0.5 6 V
INx, ENx, Voltage –0.5 VCC+ 0.5(3) V
OUTx
IOOutput current –15 15 mA
TJMaximum junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1500
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions MIN NOM MAX UNIT
VCC1, VCC2 Supply voltage 2.7 5.5 V
High-level output current (VCC ≥3.0 V) –4 mA
IOH High-level output current (VCC < 3.0 V) –2
IOL Low-level output current 4 mA
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0 0.8
tui Input pulse duration (VCC ≥4.5V) 20 ns
tui Input pulse duration (VCC < 4.5V) 25
1 / tui Signaling rate (VCC ≥4.5V) 0 50 Mbps
1 / tui Signaling rate (VCC < 4.5V) 0 40
TAAmbient temperature –40 25 125 °C
TJJunction temperature –40 136
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6.4 Thermal Information ISO7131, ISO714x
THERMAL METRIC(1) DBQ UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 104.5 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 57.8 °C/W
RθJB Junction-to-board thermal resistance 46.8 °C/W
ψJT Junction-to-top characterization parameter 18.3 °C/W
ψJB Junction-to-board characterization parameter 46.4 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Power Dissipation Ratings TEST CONDITIONS VALUE UNIT
VCC1 = VCC2 = 5.5 V, TJ= 150°C, CL= 15 pF
PDDevice power dissipation 150 mW
Input a 25-MHz, 50% duty cycle square wave
6.6 Electrical Characteristics: VCC1 and VCC2 at 5 V ±10%
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = –4 mA; see Figure 10 VCCO (1) – 0.5 4.8
VOH High-level output voltage V
IOH = –20 μA; see Figure 10 VCCO (1) – 0.1 5
IOL = 4 mA; see Figure 10 0.2 0.4
VOL Low-level output voltage V
IOL = 20 μA; see Figure 10 0 0.1
VI(HYS) Input threshold voltage 450 mV
hysteresis
IIH High-level input current VIH = VCC at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
Common-mode transient
CMTI VI= VCC or 0 V; see Figure 13 25 75 kV/μs
immunity
(1) VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
6.7 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ±10%
VCC1 and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = –4 mA; see Figure 10 VCCO (1) – 0.5 3
VOH High-level output voltage V
IOH = –20 μA; see Figure 10 VCCO (1) – 0.1 3.3
IOL = 4 mA; see Figure 10 0.2 0.4
VOL Low-level output voltage V
IOL = 20 μA; see Figure 10 0 0.1
VI(HYS) Input threshold voltage hysteresis 425 mV
IIH High-level input current VIH = VCC at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
Common-mode transient
CMTI VI= VCC or 0 V; see Figure 13 25 50 kV/μs
immunity
(1) VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
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6.8 Electrical Characteristics: VCC1 and VCC2 at 2.7 V
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = –2 mA; see Figure 10 VCCO (1) – 0.3 2.5
VOH High-level output voltage V
IOH = –20 μA; see Figure 10 VCCO (1) – 0.1 2.7
IOL = 4 mA; see Figure 10 0.2 0.4
VOL Low-level output voltage V
IOL = 20 μA; see Figure 10 0 0.1
VI(HYS) Input threshold voltage hysteresis 350 mV
IIH High-level input current VIH = VCC at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient immunity VI= VCC or 0 V; see Figure 13 25 50 kV/μs
(1) VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
6.9 Switching Characteristics: VCC1 and VCC2 at 5 V ±10%
VCC1 and VCC2 at 5 V ±10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time 12 19 35
See Figure 10 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 3
Same-direction 2
channels
tsk(o) (2) Channel-to-channel output skew time ns
Opposite-direction 4
channels
tsk(pp) (3) Part-to-part skew time 12 ns
trOutput signal rise time 2 ns
See Figure 10
tfOutput signal fall time 2 ns
tPHZ, tPLZ Disable propagation delay, high/low-to-high impedance output 6 10 ns
See Figure 11
tPZH, tPZL Enable propagation delay, high impedance-to-high/low output 5 10 ns
tfs Fail-safe output delay time from input data or power loss See Figure 12 9.5 μs
tGR Input glitch rejection time 11 ns
(1) Also known as pulse skew
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals, and loads.
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6.10 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±10%
VCC1 and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time 15 23 45
See Figure 10 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 3
Same-direction Channels 2
tsk(o) (2) Channel-to-channel output skew time ns
Opposite-direction 4
Channels
tsk(pp) (3) Part-to-part skew time 19 ns
trOutput signal rise time 2.5 ns
See Figure 10
tfOutput signal fall time 2.5 ns
Disable propagation delay, from high/low to
tPHZ, tPLZ 6.5 15 ns
high-impedance output See Figure 11
Enable propagation delay, from high-
tPZH, tPZL 6.5 15 ns
impedance to high/low output
Fail-safe output delay time from input data or
tfs See Figure 12 8μs
power loss
tGR Input glitch rejection time 12.5 ns
(1) Also known as pulse skew
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.11 Switching Characteristics: VCC1 and VCC2 at 2.7 V
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time 15 27 50
See Figure 10 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 3
Same-direction Channels 2
tsk(o) (2) Channel-to-channel output skew time ns
Opposite-direction 4
Channels
tsk(pp) (3) Part-to-part skew time 22 ns
trOutput signal rise time 3 ns
See Figure 10
tfOutput signal fall time 3 ns
Disable propagation delay, from high/low to high-
tPHZ, tPLZ 9 15 ns
impedance output See Figure 11
Enable propagation delay, from high-impedance to
tPZH, tPZL 9 15 ns
high/low output
tfs Fail-safe output delay time from input data or power loss See Figure 12 8.5 μs
tGR Input glitch rejection time 14 ns
(1) Also known as pulse skew
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals, and loads.
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6.12 Supply Current: VCC1 and VCC2 at 5 V ±10%
VCC1 and VCC2 at 5 V ±10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO7131
ICC1 2.2 3.7
Disable EN1 = EN2 = 0 V mA
ICC2 3.7 5
ICC1 2.2 3.7
DC to 1 Mbps
ICC2 3.7 5
ICC1 3.4 4.8
10 Mbps DC signal: VI= VCC or 0 V
ICC2 4.9 6.6
AC signal: All channels switching with square-wave mA
ICC1 4.9 6.6
clock input; CL= 15 pF
25 Mbps
ICC2 6.8 9
ICC1 7.1 10
50 Mbps
ICC2 10.5 13
ISO7140
ICC1 0.6 1.2
Disable EN = 0 V mA
ICC2 4.6 7
ICC1 0.6 1.3
DC to 1 Mbps
ICC2 4.8 7
ICC1 1.4 2.2
10 Mbps DC Signal: VI= VCC or 0 V,
ICC2 6.9 9.2
AC Signal: All channels switching with square wave mA
ICC1 2.7 3.9
clock input; CL= 15 pF
25 Mbps
ICC2 10.3 13.5
ICC1 4.7 6.5
50 Mbps
ICC2 15.6 21
ISO7141
ICC1 2.5 4.2
Disable EN1 = EN2 = 0V mA
ICC2 4.2 7
ICC1 2.5 4.2
DC to 1 Mbps
ICC2 4.2 7
ICC1 3.8 5.3
10 Mbps DC signal: VI= VCC or 0 V,
ICC2 6.2 9.6
AC signal: All channels switching with square wave mA
ICC1 5.6 7.5
clock input; CL= 15 pF
25 Mbps
ICC2 9.2 13
ICC1 8.4 11.2
50 Mbps
ICC2 14 18.5
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6.13 Supply Current: VCC1 and VCC2 at 3.3 V ±10%
VCC1 and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO7131
ICC1 1.9 2.7
Disable EN1 = EN2 = 0 V mA
ICC2 2.6 3.8
ICC1 1.9 2.7
DC to 1 Mbps
ICC2 2.6 3.8
ICC1 2.4 3.5
10 Mbps DC signal: VI= VCC or 0 V
ICC2 3.5 4.7
AC signal: All channels switching with square-wave mA
ICC1 3.2 4.6
clock input; CL= 15 pF
25 Mbps
ICC2 4.7 6.2
ICC1 5 7
40 Mbps
ICC2 7 9
ISO7140
ICC1 0.3 0.7
Disable EN = 0 V mA
ICC2 3.6 5.2
ICC1 0.4 0.8
DC to 1 Mbps
ICC2 3.7 5.3
ICC1 0.9 1.4
10 Mbps DC signal: VI= VCC or 0 V,
ICC2 5.1 6.8
AC signal: All channels switching with square-wave mA
ICC1 1.7 2.4
clock input; CL= 15 pF
25 Mbps
ICC2 7.3 10
ICC1 2.4 3.7
40 Mbps
ICC2 9.4 13
ISO7141
ICC1 2 3.1
Disable EN1 = EN2 = 0 V mA
ICC2 3.2 4.9
ICC1 2 3.1
DC to 1 Mbps
ICC2 3.2 4.9
ICC1 2.8 3.8
10 Mbps DC signal: VI= VCC or 0 V,
ICC2 4.5 6.1
AC signal: All channels switching with square-wave mA
ICC1 4 5.2
clock input; CL= 15 pF
25 Mbps
ICC2 6.4 8.3
ICC1 5 8
40 Mbps
ICC2 8.2 11.6
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ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
www.ti.com
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
6.14 Supply Current: VCC1 and VCC2 at 2.7 V
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO7131
ICC1 1.2 2.4
Disable EN1 = EN2 = 0 V mA
ICC2 2.3 3.3
ICC1 1.2 2.4
DC to 1 Mbps
ICC2 2.3 3.3
ICC1 2.1 3
10 Mbps DC signal: VI= VCC or 0 V
ICC2 2.9 4
AC signal: All channels switching with square-wave mA
ICC1 3 3.8
clock input; CL= 15 pF
25 Mbps
ICC2 4 5.2
ICC1 4.2 5.3
40 Mbps
ICC2 5.8 7
ISO7140
ICC1 0.2 0.4
Disable EN = 0 V mA
ICC2 3.2 4.7
ICC1 0.2 0.5
DC to 1 Mbps
ICC2 3.4 4.8
ICC1 0.6 1
10 Mbps DC signal: VI= VCC or 0 V,
ICC2 4.5 6.3
AC signal: All channels switching with square-wave mA
ICC1 1.2 1.8
clock input; CL= 15 pF
25 Mbps
ICC2 6.2 8
ICC1 1.8 2.6
40 Mbps
ICC2 8 11
ISO7141
ICC1 1.6 2.6
Disable EN1 = EN2 = 0 V mA
ICC2 2.8 4.1
ICC1 1.6 2.6
DC to 1 Mbps
ICC2 2.8 4.1
ICC1 2.3 3.2
10 Mbps DC signal: VI= VCC or 0 V,
ICC2 3.8 5
AC signal: All channels switching with square-wave mA
ICC1 3.3 4.2
clock input; CL= 15 pF
25 Mbps
ICC2 5.4 6.8
ICC1 4.3 5.8
40 Mbps
ICC2 6.9 9.2
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0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0 5 10 15
Low-Level Output Voltage (V)
Low-Level Output Current (mA)
VCC at 3.3 V
VCC at 5 V
C003
VCC at 3.3 V
VCC at 5 V
2.34
2.36
2.38
2.40
2.42
2.44
2.46
2.48
±50 0 50 100 150
Power Supply Undervoltage Threshold (V)
Free-Air Temperature (ƒC)
VCC Rising
VCC Falling
C004
VCC Rising
VCC Falling
0
2
4
6
8
10
12
14
16
0 10 20 30 40 50 60
Supply Current (mA)
Data Rate (Mbps)
ICC2 5V
ICC2 3.3V
ICC1 5V
ICC1 3.3V
C001
ICC2 at 5 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 3.3 V
±1.00
0.00
1.00
2.00
3.00
4.00
5.00
6.00
±15 ±10 ±5 0
High-Level Output Voltage (V)
High-Level Output Current (mA)
VCC at 3.3 V
VCC at 5 V
C002
VCC at 3.3 V
VCC at 5 V
0.00
2.00
4.00
6.00
8.00
10.00
12.00
0 10 20 30 40 50 60
Supply Current (mA)
Data Rate (Mbps)
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
C001
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
0
2
4
6
8
10
12
14
16
18
0 10 20 30 40 50 60
Supply Current (mA)
Data Rate (Mbps)
ICC2 5V
ICC2 3.3V
ICC1 5V
ICC1 3.3V
C001
ICC2 at 5 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC1 at 3.3 V
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
www.ti.com
6.15 Typical Characteristics
Figure 1. ISO7131 Supply Current for All Channels vs Data Figure 2. ISO7140 Supply Current for All Channels vs Data
Rate Rate
Figure 3. ISO7141 Supply Current for All Channels vs Data Figure 4. High-Level Output Voltage vs High-Level Output
Rate Current
Figure 5. Low-Level Output Voltage vs Low-Level Output Figure 6. VCC Undervoltage Threshold vs Free-Air
Current Temperature
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0
2
4
6
8
10
12
14
16
18
±50 0 50 100 150
Input Glitch Rejection Time (ns)
Free-Air Temperature (C)
tGR at 2.7 V
tGR at 3.3 V
tGR at 5 V
C007
tGR at 2.7 V
tGR at 3.3 V
tGR at 5 V
0
5
10
15
20
25
30
±50 0 50 100 150
Propagation Delay Time (ns)
Free-Air Temperature (C)
tpLH at 3.3 V
tpHL at 3.3 V
tpLH at 5 V
tpHL at 5 V
C005
tpLH at 3.3 V
tpHL at 3.3 V
tpLH at 5 V
tpHL at 5 V
0
0.2
0.4
0.6
0.8
1
1.2
0 20 40 60
Pk-Pk Output Jitter (ns)
Data Rate (Mbps)
Output Jitter at 5 V
Output Jitter at 3.3 V
C006
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
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SLLSE83F –APRIL 2013–REVISED JANUARY 2015
Typical Characteristics (continued)
Figure 7. Propagation Delay Time vs Free-Air Temperature Figure 8. Output Jitter vs Data Rate
Figure 9. Input Glitch Rejection vs Free-Air Temperature
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Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
Input
Generator 50
OUT
RL= 1 k
EN
VO
V
I
IN
0V
ISOLATION BARRIER
CL
W
W
1%
±
NOTE A
NOTE
B
0 V
V
O
VI
0.5 V
50%
Input
Generator 50
OUT
RL= 1 k
EN
V
O
VI
IN
3V
ISOLATION BARRIER
CLW
W
1%
±
NOTE A
NOTE
B
0 V
0 V
VI
50% 0.5 V
tPZH
V
O
VOH
tPHZ
V /2
CC V /2
CC
VCC
tPZL
VCC
V /2
CC
VCC
tPLZ
VCC
V /2
CC
VOL
IN
ISOLATION BARRIER
OUT
VO
CL
Input
Generator 50
VIW
NOTE A NOTE
B10%
90%
50%
0 V
50%
VIV /2
CC
VO
tPLH
VOH
tPHL
trtf
VCC1
VOL
V /2
CC
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
www.ti.com
7 Parameter Measurement Information
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr≤3
ns, tf≤3 ns, ZO= 50 Ω. At the input, a 50-Ωresistor is required to terminate the input-generator signal. It is not
needed in an actual application.
B. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Switching-Characteristics Test Circuit and Voltage Waveforms
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, tr≤3
ns, tf≤3 ns, ZO= 50 Ω.
B. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Enable/Disable Propagation Delay-Time Test Circuit and Waveform
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Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISOLATION BARRIER
IN OUT
GND2
GND1
C
NOTE A
L
S1
VCC1 VCC2
C = 0.1 F ±1%mC = 0.1 F ±1%m
Pass/Fail Criterion –
the output must
remain stable.
V or V
OH OL
VTEST
VO
OUT
IN
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
CC
NOTE A
CL
VI
0 V
tfs
fs high
VO
VI2.7 V
50%
VCC VCC
VOL
VOH
ISOLATION BARRIER
fs low
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
www.ti.com
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
Parameter Measurement Information (continued)
A. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Failsafe Delay-Time Test Circuit and Voltage Waveforms
A. CL= 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Common-Mode Transient Immunity Test Circuit
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ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
www.ti.com
8 Detailed Description
8.1 Overview
The isolator in Figure 14 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a
single-ended input signal entering the HF-channel is split into a differential signal through the inverter gate at the
input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted
into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output
feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations
between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in
the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-
frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
8.2 Functional Block Diagram
Figure 14. Conceptual Block Diagram of a Digital Capacitive Isolator
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,
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,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
www.ti.com
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
8.3 Feature Description
Table 1. Product Features
MAX DATA RATE
RATED INPUT DEFAULT CHANNEL
PRODUCT and
ISOLATION THRESHOLD OUTPUT DIRECTION
INPUT FILTER
2 forward,
ISO7131CC 1 reverse
High
ISO7140CC 4 forward,
1.5-V TTL 50 Mbps,
4242 VPK(1) 0 reverse
ISO7140FCC (CMOS compatible) Low with noise filter integrated
ISO7141CC High 3 forward,
1 reverse
ISO7141FCC Low
(1) See Regulatory Information for detailed Isolation Ratings.
8.3.1 Insulation and Safety-Related Specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Maximum transient overvoltage per
VIOTM DIN V VDE V 0884-10 (VDE V 4242 VPK
0884-10):2006-12
Maximum working voltage per DIN
VIORM V VDE V 0884-10 (VDE V 0884- 566 VPK
10):2006-12
Isolation Voltage per UL 1577 VTEST = VISO, t = 60 sec (qualification) 2500
VISO VRMS
VTEST = 1.2 * VISO, t = 1 sec (100% production) 3000
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s, 679
Partial discharge < 5 pC
Input-to-output test voltage per DIN Method a, After environmental tests subgroup 1,
VPR V VDE V 0884-10 (VDE V 0884- VPR = VIORM x 1.6, t = 10 s, 906 VPK
10):2006-12 Partial discharge < 5 pC
Method b1, 100% production test,
VPR = VIORM x 1.875, t = 1 s, 1061
Partial discharge < 5 pC
L(I01) Minimum air gap (clearance) Shortest terminal to terminal distance through air 3.7 mm
Minimum external tracking Shortest terminal to terminal distance across the
L(I02) 3.7 mm
(creepage) package surface
Minimum internal gap (internal Distance through the insulation 0.014 mm
clearance)
Pollution degree 2
Tracking resistance (comparative
CTI DIN IEC 60112 / VDE 0303 Part 1 ≥400 V
tracking index) VIO = 500 V, TA= 25oC >1012
RIO (1) Isolation Resistance, Input to Output Ω
VIO = 500 V, 100oC≤TA≤TAmax >1011
CIO (1) Barrier capacitance, input to output VI= 0.4 sin (2πft), f = 1 MHz 2.3 pF
CI(2) Input capacitance VI= VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 2.8 pF
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.
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Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
0
100
200
300
400
350
450
500
0 50 100 150 200
Case Temperature – C
o
Safety Limiting Current – mA
150
250
50
VCC1 = VCC2 = 5.5V
VCC1 = VCC2 = 3.6V
VCC1 = VCC2 = 2.7V
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
www.ti.com
spacer
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit-board (PCB) do not reduce this distance.
Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and/or ribs on a PCB are used to help increase these specifications.
Table 2. IEC 60664-1 Ratings Table
PARAMETER TEST CONDITIONS SPECIFICATION
Basic Isolation Group Material Group II
Rated mains voltage ≤150 VRMS I–IV
Installation classification Rated mains voltage ≤300 VRMS I–III
Rated mains voltage ≤400 VRMS I–II
8.3.1.1 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RθJA = 104.5°C/W, VI= 5.5V, TJ= 150°C, TA= 25°C 217
Safety input, output, or supply
ISDBQ-16 RθJA = 104.5°C/W, VI= 3.6V, TJ= 150°C, TA= 25°C 332 mA
current RθJA = 104.5°C/W, VI= 2.7V, TJ= 150°C, TA= 25°C 443
TSMaximum case temperature 150 °C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings(1) table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages.
The power is the recommended maximum input voltage times the current. The junction temperature is then the
ambient temperature plus the power times the junction-to-air thermal resistance.
Figure 15. DBQ-16 θJC Thermal Derating Curve
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
18 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
www.ti.com
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
8.3.1.2 Regulatory Information
VDE UL CSA CQC
Certified according to DIN V Recognized under UL 1577 Approved under CSA Component Certified according to GB
VDE V 0884-10 (VDE V 0884- Component Recognition Acceptance Notice 5A, IEC 60950-1, and 4943.1-2011
10):2006-12 and DIN EN Program IEC 61010-1
61010-1 Reinforced Insulation per CSA 60950-1-03
and IEC 60950-1 (2nd Ed.), 185 VRMS
maximum working voltage
Basic Insulation per CSA 60950-1-03 and
Basic Insulation IEC 60950-1 (2nd Ed.), 370 VRMS Basic Insulation, Altitude ≤
Maximum Transient maximum working voltage
Single protection, 2500 VRMS 5000m, Tropical Climate, 250
Overvoltage, 4242 VPK (1) Reinforced Insulation per CSA 61010-1-12 VRMS maximum working
Maximum Working Voltage, and IEC 61010-1 (3rd Edition), 150 VRMS voltage
566 VPK maximum working voltage
Basic Insulation per CSA 61010-1-12 and
IEC 61010-1 (3rd Edition), 300 VRMS
maximum working voltage Certificate number:
Certificate number: 40016131 File number: E181974 Master contract number: 220991 CQC14001109540
(1) Production tested ≥3000 Vrms for 1 second in accordance with UL 1577.
8.4 Device Functional Modes
Table 3. Function Table(1)
OUTPUT (OUTx)
INPUT OUTPUT ENABLE
VCCI VCCO (INx) (ENx) ISO71xxCC ISO71xxFCC
H H or open H H
L H or open L L
PU PU X L Z Z
Open H or open H L
PD PU X H or open H L
PD PU X L Z Z
PU PD X X Undetermined Undetermined
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered Up (VCC ≥2.7 V); PD = Powered Down
(VCC ≤2.1 V); X = Irrelevant; H = High Level; L = Low Level; Z = High Impedance
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Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
IN
500Ω
VCCI VCCI
7.5 uA
ISO71xxFCC Input
IN
500Ω
VCCI VCCI
7.5 uA
ISO71xxCC Input
VCCI
VCCO
OUT
Output
8Ω
13Ω
IN
500Ω
VCCO VCCO
1 MΩ
Enable
VCCO
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
www.ti.com
Figure 16. Device I/O Schematics
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Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
14
13 INA
OUTD
3
4
5
6
0.1 F
EN1EN2 710
INB
12
11 OUTC
IND
INC
DVDD
DGND
2
GAIN1 24
25
26
GAIN0
SPEED
PWDN
AIN3+
AIN3-
AIN4+
A0
A1
AIN1+
AIN1-
AIN2+
SCLK
DOUT
REF+
REF-
AIN4-
1
VCC1
16 VCC2
2, 89, 15 GND1GND2
23
20
19
28
8
7
27
0.1 F
P3.1
P3.0
CLK
SOMI
13
11
12
14
4
2
MSP430
F2132
DVss
DVcc
0.1 F
14
13
OUTD
3
4
5
6
0.1 F
NCEN 710
12
11 OUTC
IND
INC
1
VCC1
16 VCC2
2, 89, 15 GND1GND2
0.1 F
ISO7140
ISO7141
5VISO
5VISO
3.3 V
3.3 V
P3.7
P3.6
18
17
3.3 V
22
AVDD
AGND
21
5VISO
0.1F
AIN2-
13
14
17
16
15
11
12
18
INA
INBOUTB
OUTA
OUTA
OUTB
1
0.1 F0.1 F
5VISO 5VISO
Thermo
couple
Current
shunt
RTD
Bridge
XOUT
XIN
5
6
P3.4
15 P3.5 16
ADS1234
ISO-BARRIER
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
www.ti.com
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ISO71xx use single-ended TTL-logic switching technology. Its supply voltage range is from 3 V to 5.5 V for both
supplies, VCC1 and VCC2. When designing with digital isolators, it is important to note that due to the single-ended
design structure, digital isolators do not conform to any specific interface standard and are only intended for
isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data
controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Applications
9.2.1 Isolated Data Acquisition System for Process Control
ISO71xx combined with TI's precision analog-to-digital converter and mixed signal micro-controller can create an
advanced isolated data acquisition system as shown in Figure 17.
Figure 17. Isolated Data Acquisition System for Process Control
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Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7141
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INA
INB
INC
OUTD
OUTA
OUTB
OUTC
IND
GND2
VCC2
0.1 µF
2 mm max
from VCC2
EN2
GND2
EN1
GND1
2 mm max
from VCC1
GND1
0.1 µF
VCC1
ISO7140
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INA
INB
INC
IND
OUTA
OUTB
OUTC
OUTD
GND2
VCC2
0.1 µF
2 mm max
from VCC2
EN
GND2
NC
GND1
2 mm max
from VCC1
GND1
0.1 µF
VCC1
ISO7131
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INA
INB
OUTC
NC
OUTA
OUTB
INC
NC
GND2
VCC2
0.1 µF
2 mm max
from VCC2
EN2
GND2
EN1
GND1
2 mm max
from VCC1
GND1
0.1 µF
VCC1
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
www.ti.com
Typical Applications (continued)
9.2.1.1 Design Requirements
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,
ISO71xx only needs two external bypass capacitors to operate.
9.2.1.2 Detailed Design Procedure
Figure 18. Typical ISO7131 Circuit Hook-up Figure 19. Typical ISO7140 Circuit Hook-up
Figure 20. Typical ISO7141 Circuit Hook-up
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ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
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SLLSE83F –APRIL 2013–REVISED JANUARY 2015
Typical Applications (continued)
9.2.1.3 Application Curves
Typical eye diagrams of ISO71xx (see Figure 21,Figure 22, and Figure 23) indicate low jitter and wide open eye
at the maximum data rate.
Figure 21. Typical Eye Diagram at 40 MBPS, PRBS 216 - 1, Figure 22. Typical Eye Diagram at 40 MBPS, PRBS 216 - 1,
2.7-V Operation 3.3-V Operation
Figure 23. Typical Eye Diagram at 50 MBPS, PRBS 216 - 1, 5-V Operation
Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
VCC1 VCC2
GND1 GND2
16
13
12
2,8 9,15
UCA0RXD
P3.0
UCA0TXD
16
11
15
4
XOUT
XIN
5
6
2
MSP430
F2132
1
3
4
5
7
0.1F 0.1F
ISO7131
ISO-BARRIER
4.7nF/
2kV
SM712
10 MELF
0.1F
DVss
DVcc
10F 0.1F
MBR0520L
MBR0520L
1:2.2
0.1F
3
1
D2
SN6501
D1
Vcc
4,5
2
GND
IN
EN GND
OUT
15
23
TPS76350 10F
10F
10 MELF
VIN
3.3V
5VISO
INA
INB
OUTC
EN1
OUTA
OUTB
INC
SN65HVD
3082E
RE
DE
D
R
EN2
14
10 1
4
3
2B
A
VCC
GND
0.1F
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
www.ti.com
Typical Applications (continued)
9.2.2 Isolated RS-485 Interface
Figure 24. Isolated RS-485 Interface
9.2.2.1 Design Requirements
See previous Design Requirements.
9.2.2.2 Detailed Design Procedure
See previous Detailed Design Procedure.
9.2.2.3 Application Curves
See previous Application Curves.
24 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
10 mils
10 mils
40 mils FR-4
0r~ 4.5
Keep this
space free
from planes,
traces , pads,
and vias
Ground plane
Power plane
Low-speed traces
High-speed traces
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
www.ti.com
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1-µF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as TI's SN6501. For such
applications, detailed power supply design and transformer selection recommendations are available in SN6501
data sheet (SLLSEA0).
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 25). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note SLLA284,Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-
extinguishing flammability-characteristics.
11.2 Layout Example
Figure 25. Recommended Layer Stack
Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
ISO7131CC
,
ISO7140CC
,
ISO7140FCC
,
ISO7141CC
,
ISO7141FCC
SLLSE83F –APRIL 2013–REVISED JANUARY 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
•SLLA284,Digital Isolator Design Guide
•SLLSEA0,Transformer Driver for Isolated Power Supplies
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
ISO7131CC Click here Click here Click here Click here Click here
ISO7140CC Click here Click here Click here Click here Click here
ISO7140FCC Click here Click here Click here Click here Click here
ISO7141CC Click here Click here Click here Click here Click here
ISO7141FCC Click here Click here Click here Click here Click here
12.3 Trademarks
Modbus is a trademark of Gould Inc.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
SLLA353 -Isolation Glossary.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ISO7131CCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7131CC
ISO7131CCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7131CC
ISO7140CCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140CC
ISO7140CCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140CC
ISO7140FCCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140FC
ISO7140FCCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140FC
ISO7141CCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141CC
ISO7141CCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141CC
ISO7141FCCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141FC
ISO7141FCCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141FC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2014
Addendum-Page 2
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ISO7131CCDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7140CCDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7140FCCDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7141CCDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO7141FCCDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Feb-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO7131CCDBQR SSOP DBQ 16 2500 367.0 367.0 38.0
ISO7140CCDBQR SSOP DBQ 16 2500 367.0 367.0 38.0
ISO7140FCCDBQR SSOP DBQ 16 2500 367.0 367.0 38.0
ISO7141CCDBQR SSOP DBQ 16 2500 367.0 367.0 38.0
ISO7141FCCDBQR SSOP DBQ 16 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Feb-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP-.244.228
-6.195.80[ ]
.069 MAX
[1.75]
14X .0250
[0.635]
16X -.012.008
-0.300.21[ ]
2X
.175
[4.45]
TYP-.010.005
-0.250.13[ ]
0- 8 -.010.004
-0.250.11[ ]
(.041 )
[1.04]
.010
[0.25]
GAGE PLANE
-.035.016
-0.880.41[ ]
A
NOTE 3
-.197.189
-5.004.81[ ]
B
NOTE 4
-.157.150
-3.983.81[ ]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
116
.007 [0.17] C A B
9
8
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
(.213)
[5.4]
14X (.0250 )
[0.635]
16X (.063)
[1.6]
16X (.016 )
[0.41]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:8X
SYMM
1
89
16
SEE
DETAILS
www.ti.com
EXAMPLE STENCIL DESIGN
16X (.063)
[1.6]
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
(.213)
[5.4]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
89
16
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