Product Folder Sample & Buy Technical Documents Support & Community Tools & Software ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 ISO71xxCC 4242-VPK Small-Footprint Low-Power Triple and Quad Channels Digital Isolators 1 Features 3 Description * ISO7131, ISO7140, and ISO7141 devices provide galvanic isolation up to 2500 VRMS for 1 minute per UL and 4242 VPK per VDE. ISO7131 has three channels with two forward and one reverse-direction channels. ISO7140 and ISO7141 are quad-channel isolators; ISO7140 has four forward channels, ISO7141 has three forward and one reverse-direction channels. These devices are capable of 50-Mbps maximum data rate with 5-V supplies and 40-Mbps maximum data rate with 3.3-V or 2.7-V supplies, with integrated filters on the inputs for noise-prone applications. The suffix F indicates that default output state is low; otherwise, the default output state is high (see Table 3). 1 * * * * * * * * * * Maximum Signaling Rate: 50 Mbps (With 5-V Supplies) Robust Design With Integrated Noise Filter Default Output Low Option (Suffix F) Low Power Consumption, Typical ICC per Channel (With 3.3-V Supplies): - ISO7131: 1.5 mA at 1 Mbps, 2.6 mA at 25 Mbps - ISO7140: 1 mA at 1 Mbps, 2.3 mA at 25 Mbps - ISO7141: 1.3 mA at 1 Mbps, 2.6 mA at 25 Mbps Low Propagation Delay: 23-ns Typical (3.3-V Supplies) Wide Temperature Range: -40C to 125C 50-kV/s Transient Immunity, Typical Long Life With SiO2 Isolation Barrier Operates from 2.7-V, 3.3-V, and 5-V Supply and Logic Levels Small QSOP-16 Package Safety and Regulatory Approvals - 2500-VRMS Isolation for 1 minute per UL 1577 - 4242-VPK Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, 566 VPK Working Voltage - CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1 End Equipment Standards - CQC Certification per GB 4943.1-2011 Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The devices have TTL input thresholds and can operate from 2.7V, 3.3-V, and 5-V supplies. All inputs are 5-V tolerant when supplied from a 2.7-V or 3.3-V supply. Device Information(1) PART NUMBER General-Purpose Isolation - Industrial Fieldbus - Profibus - ModbusTM - DeviceNet Data Buses - RS-232, RS-485 - Serial Peripheral Interface BODY SIZE (NOM) ISO7140CC ISO7140FCC SSOP (16) 4.90 mm x 3.90 mm ISO7141CC ISO7141FCC (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic 2 Applications * PACKAGE ISO7131CC VCCI VCCO Isolation Capacitor INx OUTx ENx GND1 GND2 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 Absolute Maximum Ratings ..................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Power Dissipation Ratings ........................................ 6 Electrical Characteristics: VCC1 and VCC2 at 5 V 10% .......................................................................... 6 6.7 Electrical Characteristics: VCC1 and VCC2 at 3.3 V 10% .......................................................................... 6 6.8 Electrical Characteristics: VCC1 and VCC2 at 2.7 V ... 7 6.9 Switching Characteristics: VCC1 and VCC2 at 5 V 10% .......................................................................... 7 6.10 Switching Characteristics: VCC1 and VCC2 at 3.3 V 10% .......................................................................... 8 6.11 Switching Characteristics: VCC1 and VCC2 at 2.7 V. 8 6.12 Supply Current: VCC1 and VCC2 at 5 V 10% ......... 9 6.13 Supply Current: VCC1 and VCC2 at 3.3 V 10% .... 10 6.14 Supply Current: VCC1 and VCC2 at 2.7 V............... 11 6.15 Typical Characteristics .......................................... 12 7 8 Parameter Measurement Information ................ 14 Detailed Description ............................................ 16 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 16 16 17 19 Application and Implementation ........................ 21 9.1 Application Information............................................ 21 9.2 Typical Applications ................................................ 21 10 Power Supply Recommendations ..................... 25 11 Layout................................................................... 25 11.1 Layout Guidelines ................................................. 25 11.2 Layout Example .................................................... 25 12 Device and Documentation Support ................. 26 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 26 13 Mechanical, Packaging, and Orderable Information ........................................................... 26 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (September 2013) to Revision F Page * Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 * VDE Standard changed to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 ...................................................................... 1 Changes from Revision D (August 2013) to Revision E Page * Changed From: 2500 VRMS Isolation for 1 minute per UL 1577 (Approval Pending) To: (Approved) ................................... 1 * Added note1 to the AVAILABLE OPTIONS table................................................................................................................. 17 * Changed Figure 15............................................................................................................................................................... 18 * Changed From: Basic Insulation To: Basic Insulation, Altitude 5000m, Tropical Climate, 250 VRMS maximum working voltage in the Regulatory Information table ............................................................................................................ 19 * Changed File number: E181974 (approval pending) To: File number: E181974 in the Regulatory Information table ........ 19 * Changed the title of Figure 21, Figure 22, and Figure 23 to include "PRBS 216 - 1" ........................................................... 23 Changes from Revision C (July 2013) to Revision D Page * Added Safety List item "GB 4943.1-2011 and GB 8898:2011 CQC Certification (Approval Pending)" ................................. 1 * Added Figure 2 ..................................................................................................................................................................... 12 * Deleted "Product Preview" From the AVAILABLE OPTIONS table ..................................................................................... 17 * Changed the REGULATORY INFORMATION, added column for CQC .............................................................................. 19 2 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 Changes from Revision B (June 2013) to Revision C Page * Changed Feature From: ISO7140: TBD at 1 Mbps, TBD at 25 Mbps To: ISO7140: 1 mA at 1 Mbps, 2.3 mA at 25 Mbps.. 1 * Added text to the Description: "All inputs are 5V tolerant when supplied from a 2.7V or 3.3V supply." ................................ 1 * Deleted the Product Status table............................................................................................................................................ 1 * Changed the SAFETY and REGULATORY APPROVALS .................................................................................................... 1 * Changed the ABSOLUTE MAXIMUM RATINGS table .......................................................................................................... 5 * Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. .............................................................. 7 * Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. ............................................................. 8 * Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. ............................................................. 8 * Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values......................................................................... 9 * Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values....................................................................... 10 * Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values....................................................................... 11 * Changed Figure 1 X-axis scale ............................................................................................................................................ 12 * Changed the AVAILABLE OPTIONS table........................................................................................................................... 17 Changes from Revision A (June 2013) to Revision B * Page Changed device ISO7141CC From: Product Preview To: Released in the Product Status table ......................................... 1 Changes from Original (April 2013) to Revision A Page * Changed the Simplified Schematic, added ground symbols .................................................................................................. 1 * Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device. ................................. 7 * Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device. ................................. 8 * Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device. ................................. 8 * Added Figure 3 ..................................................................................................................................................................... 12 Copyright (c) 2013-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 3 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com 5 Pin Configuration and Functions 16-Pin SSOP Package Top View ISO7131 ISO7140 ISO7141 VCC1 1 16 VCC2 VCC1 1 16 VCC2 VCC1 1 16 GND1 2 15 GND2 GND1 2 15 GND2 GND1 2 15 GND2 INA INB 3 14 OUTA 3 14 OUTA 14 OUTA 13 OUTB 4 13 OUTB INA INB 3 4 INA INB 4 13 OUTB OUTC 5 12 INC INC 5 12 OUTC INC 5 12 OUTC NC 6 11 NC IND 6 11 OUTD OUTD 6 11 IND EN1 7 10 EN2 NC 7 10 EN EN1 7 10 EN2 GND1 8 9 GND1 8 9 GND1 8 9 GND2 GND2 VCC2 GND2 Pin Functions PIN NAME I/O DESCRIPTION -- I Output enable. All output pins are enabled when EN is high or disconnected and disabled when EN is low. -- 7 I Output enable 1. Output pins on side-1 are enabled when EN1 is high or disconnected and disabled when EN1 is low. -- 10 I Output enable 2. Output pins on side-2 are enabled when EN2 is high or disconnected and disabled when EN2 is low. ISO7131 ISO7140 ISO7141 EN -- 10 EN1 7 EN2 10 GND1 2,8 2,8 2,8 -- Ground connection for VCC1 GND2 9,15 9,15 9,15 -- Ground connection for VCC2 INA 3 3 3 I Input, channel A INB 4 4 4 I Input, channel B INC 12 5 5 I Input, channel C IND -- 6 11 I Input, channel D NC 6,11 7 -- -- No Connect pins are floating with no internal connection OUTA 14 14 14 O Output, channel A OUTB 13 13 13 O Output, channel B OUTC 5 12 12 O Output, channel C OUTD -- 11 6 O Output, channel D VCC1 1 1 1 -- Power supply, VCC1 VCC2 16 16 16 -- Power supply, VCC2 4 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 6 Specifications 6.1 Absolute Maximum Ratings (1) VCC1, VCC2 Supply voltage (2) MIN MAX -0.5 6 INx, ENx, OUTx Voltage -0.5 IO Output current -15 TJ Maximum junction temperature Tstg Storage temperature (1) (2) (3) UNIT V VCC+ 0.5 -65 (3) V 15 mA 150 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values. Maximum voltage must not exceed 6 V 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN VCC1, VCC2 IOH Supply voltage 2.7 High-level output current (VCC 3.0 V) -4 High-level output current (VCC < 3.0 V) -2 NOM MAX 5.5 V mA IOL Low-level output current VIH High-level input voltage VIL Low-level input voltage tui Input pulse duration (VCC 4.5V) 20 tui Input pulse duration (VCC < 4.5V) 25 1 / tui Signaling rate (VCC 4.5V) 0 50 1 / tui Signaling rate (VCC < 4.5V) 0 40 TA Ambient temperature -40 TJ Junction temperature -40 Copyright (c) 2013-2015, Texas Instruments Incorporated UNIT 4 2 5.5 0 0.8 mA V ns 25 125 Mbps C 136 Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 5 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com 6.4 Thermal Information ISO7131, ISO714x THERMAL METRIC (1) DBQ UNIT 16 PINS RJA Junction-to-ambient thermal resistance 104.5 C/W RJC(top) Junction-to-case(top) thermal resistance 57.8 C/W RJB Junction-to-board thermal resistance 46.8 C/W JT Junction-to-top characterization parameter 18.3 C/W JB Junction-to-board characterization parameter 46.4 C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Power Dissipation Ratings TEST CONDITIONS PD VALUE UNIT 150 mW VCC1 = VCC2 = 5.5 V, TJ = 150C, CL = 15 pF Input a 25-MHz, 50% duty cycle square wave Device power dissipation 6.6 Electrical Characteristics: VCC1 and VCC2 at 5 V 10% VCC1 and VCC2 at 5 V 10% (over recommended operating conditions unless otherwise noted.) PARAMETER MIN TYP IOH = -4 mA; see Figure 10 TEST CONDITIONS VCCO (1) - 0.5 4.8 IOH = -20 A; see Figure 10 VCCO (1) - 0.1 5 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 13 (1) MAX UNIT V IOL = 4 mA; see Figure 10 0.2 0.4 IOL = 20 A; see Figure 10 0 0.1 450 V mV 10 A A -10 25 75 kV/s VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured. 6.7 Electrical Characteristics: VCC1 and VCC2 at 3.3 V 10% VCC1 and VCC2 at 3.3 V 10% (over recommended operating conditions unless otherwise noted.) PARAMETER MIN TYP IOH = -4 mA; see Figure 10 TEST CONDITIONS VCCO (1) - 0.5 3 IOH = -20 A; see Figure 10 VCCO (1) - 0.1 3.3 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 13 (1) 6 MAX V IOL = 4 mA; see Figure 10 0.2 0.4 IOL = 20 A; see Figure 10 0 0.1 425 V mV 10 A A -10 25 UNIT 50 kV/s VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured. Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 6.8 Electrical Characteristics: VCC1 and VCC2 at 2.7 V VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS IOH = -2 mA; see Figure 10 VCCO (1) IOH = -20 A; see Figure 10 VCCO (1) VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCC at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 13 (1) MIN TYP - 0.3 2.5 - 0.1 2.7 MAX UNIT V IOL = 4 mA; see Figure 10 0.2 0.4 IOL = 20 A; see Figure 10 0 0.1 V 350 mV A 10 A -10 25 50 kV/s VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured. 6.9 Switching Characteristics: VCC1 and VCC2 at 5 V 10% VCC1 and VCC2 at 5 V 10% (over recommended operating conditions unless otherwise noted.) PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL - tPLH| tsk(o) (2) tsk(pp) (3) Channel-to-channel output skew time Output signal rise time tf Output signal fall time tPHZ, tPLZ Disable propagation delay, high/low-to-high impedance output tPZH, tPZL Enable propagation delay, high impedance-to-high/low output tfs Fail-safe output delay time from input data or power loss tGR Input glitch rejection time (3) See Figure 10 MIN TYP 12 19 MAX UNIT 35 3 Same-direction channels 2 Opposite-direction channels 4 ns ns Part-to-part skew time tr (1) (2) TEST CONDITIONS 12 2 See Figure 10 ns 2 See Figure 11 See Figure 12 ns ns 6 10 5 10 ns ns 9.5 s 11 ns Also known as pulse skew tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals, and loads. Copyright (c) 2013-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 7 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com 6.10 Switching Characteristics: VCC1 and VCC2 at 3.3 V 10% VCC1 and VCC2 at 3.3 V 10% (over recommended operating conditions unless otherwise noted.) PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL - tPLH| tsk(o) (2) tsk(pp) Channel-to-channel output skew time (3) Output signal rise time tf Output signal fall time tPHZ, tPLZ Disable propagation delay, from high/low to high-impedance output tPZH, tPZL Enable propagation delay, from highimpedance to high/low output tfs Fail-safe output delay time from input data or power loss tGR Input glitch rejection time (3) MIN TYP MAX 15 23 45 See Figure 10 UNIT ns 3 Same-direction Channels 2 Opposite-direction Channels 4 Part-to-part skew time tr (1) (2) TEST CONDITIONS ns 19 See Figure 10 ns 2.5 ns 2.5 ns 6.5 15 ns 6.5 15 ns See Figure 11 8 s 12.5 ns See Figure 12 Also known as pulse skew tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.11 Switching Characteristics: VCC1 and VCC2 at 2.7 V VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.) PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL - tPLH| tsk(o) (2) tsk(pp) Channel-to-channel output skew time (3) Output signal rise time tf Output signal fall time tPHZ, tPLZ Disable propagation delay, from high/low to highimpedance output tPZH, tPZL Enable propagation delay, from high-impedance to high/low output tfs Fail-safe output delay time from input data or power loss tGR Input glitch rejection time (3) 8 See Figure 10 MIN TYP MAX 15 27 50 3 Same-direction Channels 2 Opposite-direction Channels 4 Part-to-part skew time tr (1) (2) TEST CONDITIONS 22 See Figure 10 UNIT ns ns ns 3 ns 3 ns 9 15 ns 9 15 ns See Figure 11 See Figure 12 8.5 s 14 ns Also known as pulse skew tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals, and loads. Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 6.12 Supply Current: VCC1 and VCC2 at 5 V 10% VCC1 and VCC2 at 5 V 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS MIN TYP MAX 2.2 3.7 3.7 5 2.2 3.7 UNIT ISO7131 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V AC signal: All channels switching with square-wave clock input; CL = 15 pF 50 Mbps 3.7 5 3.4 4.8 4.9 6.6 4.9 6.6 6.8 9 7.1 10 10.5 13 0.6 1.2 4.6 7 0.6 1.3 mA mA ISO7140 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN = 0 V DC to 1 Mbps 10 Mbps 25 Mbps 4.8 7 1.4 2.2 6.9 9.2 2.7 3.9 10.3 13.5 DC Signal: VI = VCC or 0 V, AC Signal: All channels switching with square wave clock input; CL = 15 pF 50 Mbps 4.7 6.5 15.6 21 2.5 4.2 4.2 7 2.5 4.2 4.2 7 3.8 5.3 6.2 9.6 5.6 7.5 mA mA ISO7141 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V, AC signal: All channels switching with square wave clock input; CL = 15 pF 50 Mbps Copyright (c) 2013-2015, Texas Instruments Incorporated 9.2 13 8.4 11.2 14 18.5 Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC mA mA 9 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com 6.13 Supply Current: VCC1 and VCC2 at 3.3 V 10% VCC1 and VCC2 at 3.3 V 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS MIN TYP MAX 1.9 2.7 2.6 3.8 1.9 2.7 2.6 3.8 2.4 3.5 3.5 4.7 3.2 4.6 4.7 6.2 5 7 7 9 0.3 0.7 3.6 5.2 0.4 0.8 3.7 5.3 0.9 1.4 5.1 6.8 1.7 2.4 7.3 10 2.4 3.7 9.4 13 2 3.1 3.2 4.9 UNIT ISO7131 ICC1 Disable ICC2 ICC1 EN1 = EN2 = 0 V DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 ICC1 25 Mbps ICC2 ICC1 DC signal: VI = VCC or 0 V AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps ICC2 mA mA ISO7140 ICC1 Disable ICC2 ICC1 EN = 0 V DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 ICC1 25 Mbps ICC2 ICC1 DC signal: VI = VCC or 0 V, AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps ICC2 mA mA ISO7141 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 10 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V, AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps Submit Documentation Feedback 2 3.1 3.2 4.9 2.8 3.8 4.5 6.1 4 5.2 6.4 8.3 5 8 8.2 11.6 mA mA Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 6.14 Supply Current: VCC1 and VCC2 at 2.7 V VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS MIN TYP MAX 1.2 2.4 2.3 3.3 1.2 2.4 2.3 3.3 2.1 3 2.9 4 3 3.8 UNIT ISO7131 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps 4 5.2 4.2 5.3 5.8 7 0.2 0.4 3.2 4.7 0.2 0.5 3.4 4.8 0.6 1 4.5 6.3 1.2 1.8 6.2 8 1.8 2.6 8 11 1.6 2.6 2.8 4.1 1.6 2.6 2.8 4.1 2.3 3.2 mA mA ISO7140 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V, AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps mA mA ISO7141 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 ICC1 ICC2 Disable EN1 = EN2 = 0 V DC to 1 Mbps 10 Mbps 25 Mbps DC signal: VI = VCC or 0 V, AC signal: All channels switching with square-wave clock input; CL = 15 pF 40 Mbps Copyright (c) 2013-2015, Texas Instruments Incorporated 3.8 5 3.3 4.2 5.4 6.8 4.3 5.8 6.9 9.2 Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC mA mA 11 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com 6.15 Typical Characteristics 12.00 ICC2 5VV ICC2 at 5 ICC2 3.3VV ICC2 at 3.3 ICC1 at 5 ICC1 5VV ICC1 at 3.3 ICC1 3.3VV 16 Supply Current (mA) 10.00 Supply Current (mA) 18 ICC1 3.3VV ICC1 atat3.3 ICC2 atat3.3 ICC2 3.3VV ICC1 atat5 5VV ICC1 ICC2 atat5 5VV ICC2 8.00 6.00 4.00 14 12 10 8 6 4 2.00 2 0.00 0 0 10 20 30 40 50 Data Rate (Mbps) 60 0 40 50 60 C001 Figure 2. ISO7140 Supply Current for All Channels vs Data Rate 5.00 High-Level Output Voltage (V) Supply Current (mA) 12 30 6.00 ICC2 5VV ICC2 at 5 ICC2 at 3.3 ICC2 3.3VV ICC1 at 5 ICC1 5VV ICC1 at 3.3 ICC1 3.3VV 14 20 Data Rate (Mbps) Figure 1. ISO7131 Supply Current for All Channels vs Data Rate 16 10 C001 10 8 6 4 2 4.00 3.00 2.00 1.00 3.3V V VVCC 3.3 CC atat 0.00 VVCC 5 5V V CC atat 0 1.00 0 10 20 30 40 Data Rate (Mbps) 50 60 15 Figure 3. ISO7141 Supply Current for All Channels vs Data Rate C002 1.75 V VCC CC atat55VV 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0 5 10 Low-Level Output Current (mA) 15 C003 Figure 5. Low-Level Output Voltage vs Low-Level Output Current Submit Documentation Feedback Power Supply Undervoltage Threshold (V) 2.48 VCC 3.3VV V CC atat3.3 Low-Level Output Voltage (V) 0 5 Figure 4. High-Level Output Voltage vs High-Level Output Current 2.00 12 10 High-Level Output Current (mA) C001 VCC Rising V CC Rising 2.46 V VCC Falling CC Falling 2.44 2.42 2.40 2.38 2.36 2.34 50 0 50 100 Free-Air Temperature (C) 150 C004 Figure 6. VCC Undervoltage Threshold vs Free-Air Temperature Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 30 1.2 25 1 Pk-Pk Output Jitter (ns) Propagation Delay Time (ns) Typical Characteristics (continued) 20 15 10 ttpLH 3.3 3.3VV pLH atat ttpHL 3.3 3.3VV pHL atat ttpLH 5 5VV pLH atat ttpHL 5 5VV pHL atat 5 0 50 0 50 100 0.6 0.4 0.2 Output Jitter at 5 V Output Jitter at 3.3 V 0 150 Free-Air Temperature (C) 0.8 0 20 40 Data Rate (Mbps) C005 Figure 7. Propagation Delay Time vs Free-Air Temperature 60 C006 Figure 8. Output Jitter vs Data Rate Input Glitch Rejection Time (ns) 18 16 14 12 10 8 6 4 ttGR 2.7VV GR atat2.7 ttGR 3.3VV GR atat3.3 ttGR GR atat55VV 2 0 50 0 50 100 Free-Air Temperature (C) 150 C007 Figure 9. Input Glitch Rejection vs Free-Air Temperature Copyright (c) 2013-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 13 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com ISOLATION BARRIER 7 Parameter Measurement Information IN Input Generator NOTE A 50 W VI VCC1 VI VCC/2 OUT VCC/2 0V tPHL tPLH VO CL NOTE B VOH 90% VO 50% 10% tf tr 50% VOL A. The input pulse is supplied by a generator having the following characteristics: PRR 50 kHz, 50% duty cycle, tr 3 ns, tf 3 ns, ZO = 50 . At the input, a 50- resistor is required to terminate the input-generator signal. It is not needed in an actual application. B. CL = 15 pF and includes instrumentation and fixture capacitance within 20%. Figure 10. Switching-Characteristics Test Circuit and Voltage Waveforms VCC VCC ISOLATION BARRIER 0V R L = 1 k W 1% IN Input Generator OUT EN VO 0V tPLZ tPZL VO CL VCC/2 VCC/2 VI VCC 0.5 V 50% VOL NOTE B VI 50 W ISOLATION BARRIER NOTE A IN 3V Input Generator NOTE A VI VCC OUT VO VCC/2 VI VCC/2 0V EN 50 W CL NOTE B tPZH R L = 1 k W 1% VO VOH 50% 0.5 V tPHZ A. The input pulse is supplied by a generator having the following characteristics: PRR 50 kHz, 50% duty cycle, tr 3 ns, tf 3 ns, ZO = 50 . B. CL = 15 pF and includes instrumentation and fixture capacitance within 20%. 0V Figure 11. Enable/Disable Propagation Delay-Time Test Circuit and Waveform 14 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 Parameter Measurement Information (continued) VI IN = 0 V (Devices without suffix F) IN = VCC (Devices with suffix F) A. IN VCC ISOLATION BARRIER VCC 2.7 V VI OUT 0V t fs VO fs high CL NOTE A VO VOH 50% fs low V OL CL = 15 pF and includes instrumentation and fixture capacitance within 20%. Figure 12. Failsafe Delay-Time Test Circuit and Voltage Waveforms VCC1 VCC2 IN S1 ISOLATION BARRIER C = 0.1 mF 1% GND1 C = 0.1 mF 1% OUT CL NOTE A Pass/Fail Criterion - the output must remain stable. VOH or VOL GND2 VTEST A. CL = 15 pF and includes instrumentation and fixture capacitance within 20%. Figure 13. Common-Mode Transient Immunity Test Circuit Copyright (c) 2013-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 15 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com 8 Detailed Description 8.1 Overview The isolator in Figure 14 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single-ended input signal entering the HF-channel is split into a differential signal through the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the lowfrequency channel. Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer. 8.2 Functional Block Diagram Figure 14. Conceptual Block Diagram of a Digital Capacitive Isolator 16 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 8.3 Feature Description Table 1. Product Features RATED ISOLATION PRODUCT INPUT THRESHOLD DEFAULT OUTPUT ISO7131CC CHANNEL DIRECTION 2 forward, 1 reverse High ISO7140CC 4242 VPK (1) ISO7140FCC (1) MAX DATA RATE and INPUT FILTER 1.5-V TTL (CMOS compatible) Low ISO7141CC High ISO7141FCC Low 4 forward, 0 reverse 50 Mbps, with noise filter integrated 3 forward, 1 reverse See Regulatory Information for detailed Isolation Ratings. 8.3.1 Insulation and Safety-Related Specifications MAX UNIT VIOTM Maximum transient overvoltage per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 PARAMETER 4242 VPK VIORM Maximum working voltage per DIN V VDE V 0884-10 (VDE V 088410):2006-12 566 VPK VISO Isolation Voltage per UL 1577 Input-to-output test voltage per DIN V VDE V 0884-10 (VDE V 088410):2006-12 VPR TEST CONDITIONS MIN TYP VTEST = VISO, t = 60 sec (qualification) 2500 VTEST = 1.2 * VISO, t = 1 sec (100% production) 3000 After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 679 Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial discharge < 5 pC 906 Method b1, 100% production test, VPR = VIORM x 1.875, t = 1 s, Partial discharge < 5 pC VRMS VPK 1061 L(I01) Minimum air gap (clearance) Shortest terminal to terminal distance through air 3.7 mm L(I02) Minimum external tracking (creepage) Shortest terminal to terminal distance across the package surface 3.7 mm Minimum internal gap (internal clearance) Distance through the insulation 0.014 mm Pollution degree Tracking resistance (comparative tracking index) CTI 2 DIN IEC 60112 / VDE 0303 Part 1 400 o RIO (1) CIO (1) CI (1) (2) (2) Isolation Resistance, Input to Output V 12 VIO = 500 V, TA = 25 C >10 VIO = 500 V, 100oC TA TA max >1011 Barrier capacitance, input to output VI = 0.4 sin (2ft), f = 1 MHz 2.3 pF Input capacitance VI = VCC/2 + 0.4 sin (2ft), f = 1 MHz, VCC = 5 V 2.8 pF All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. Copyright (c) 2013-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 17 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com spacer NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit-board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and/or ribs on a PCB are used to help increase these specifications. Table 2. IEC 60664-1 Ratings Table PARAMETER TEST CONDITIONS Basic Isolation Group SPECIFICATION Material Group Installation classification II Rated mains voltage 150 VRMS I-IV Rated mains voltage 300 VRMS I-III Rated mains voltage 400 VRMS I-II 8.3.1.1 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER IS Safety input, output, or supply current TS Maximum case temperature TEST CONDITIONS DBQ-16 MIN TYP MAX RJA = 104.5C/W, VI = 5.5V, TJ = 150C, TA = 25C 217 RJA = 104.5C/W, VI = 3.6V, TJ = 150C, TA = 25C 332 RJA = 104.5C/W, VI = 2.7V, TJ = 150C, TA = 25C 443 150 UNIT mA C Safety Limiting Current - mA The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings (1) table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 500 450 400 350 300 250 200 150 100 50 0 VCC1 = VCC2 = 2.7V VCC1 = VCC2 = 3.6V VCC1 = VCC2 = 5.5V 0 50 100 150 200 o Case Temperature - C Figure 15. DBQ-16 JC Thermal Derating Curve (1) 18 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 8.3.1.2 Regulatory Information VDE UL CSA Certified according to DIN V Recognized under UL 1577 VDE V 0884-10 (VDE V 0884- Component Recognition 10):2006-12 and DIN EN Program 61010-1 Basic Insulation Maximum Transient Overvoltage, 4242 VPK Maximum Working Voltage, 566 VPK Certificate number: 40016131 (1) CQC Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 61010-1 Certified according to GB 4943.1-2011 Single protection, 2500 VRMS (1) Reinforced Insulation per CSA 60950-1-03 and IEC 60950-1 (2nd Ed.), 185 VRMS maximum working voltage Basic Insulation per CSA 60950-1-03 and IEC 60950-1 (2nd Ed.), 370 VRMS maximum working voltage Reinforced Insulation per CSA 61010-1-12 and IEC 61010-1 (3rd Edition), 150 VRMS maximum working voltage Basic Insulation per CSA 61010-1-12 and IEC 61010-1 (3rd Edition), 300 VRMS maximum working voltage Basic Insulation, Altitude 5000m, Tropical Climate, 250 VRMS maximum working voltage File number: E181974 Master contract number: 220991 Certificate number: CQC14001109540 Production tested 3000 Vrms for 1 second in accordance with UL 1577. 8.4 Device Functional Modes Table 3. Function Table (1) VCCI PU (1) VCCO PU OUTPUT (OUTx) INPUT (INx) OUTPUT ENABLE (ENx) ISO71xxCC ISO71xxFCC H H or open H H L H or open L L X L Z Z Open H or open H L PD PU X H or open H L PD PU X L Z Z PU PD X X Undetermined Undetermined VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered Up (VCC 2.7 V); PD = Powered Down (VCC 2.1 V); X = Irrelevant; H = High Level; L = Low Level; Z = High Impedance Copyright (c) 2013-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 19 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com Output ISO71xxFCC Input VCCO VCCI VCCI 500 8 IN OUT 13 7.5 uA Enable ISO71xxCC Input VCCI VCCO VCCI VCCI VCCO VCCO 1 M 7.5 uA 500 500 IN IN Figure 16. Device I/O Schematics 20 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information ISO71xx use single-ended TTL-logic switching technology. Its supply voltage range is from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to note that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, C or UART), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 Typical Applications 9.2.1 Isolated Data Acquisition System for Process Control ISO71xx combined with TI's precision analog-to-digital converter and mixed signal micro-controller can create an advanced isolated data acquisition system as shown in Figure 17. 5 VISO ISO-BARRIER 5 VISO 5 VISO 0 .1 F 22 AVDD 11 RTD 12 16 1 0.1 F DVDD AIN1+ A0 AIN1- A1 SCLK Bridge 18 17 AIN2+ DOUT 13 14 16 Current shunt 15 7 13 27 12 28 11 ADS1234 5VISO REF- AIN3+ AIN3- GAIN0 GAIN1 AIN4+ SPEED AIN4- PWDN AGND 21 10 14 8 AIN2REF+ Thermo couple 3.3 V 3.3 V 0 .1 F 9, 15 5 VISO V CC2 VCC 1 EN2 EN1 INA OUTA OUTB ISO7141 OUTC IND GND2 INB INC OUTD GND1 0 .1 F 1 7 11 4 12 5 14 6 13 0.1 F 0.1 F 16 10 23 14 24 13 25 12 26 11 DGND 9, 15 V CC2 VCC 1 EN NC OUTA OUTB INA ISO7140 INB OUTC INC OUTD IND GND2 GND1 DVcc P 3.0 XOUT 3.3 V CLK MSP430 F2132 P3.7 SOMI P 3.4 1 7 XIN P3.6 15 5 P 3.1 2, 8 20 19 2 0.1 F 3 DVss P3.5 6 18 17 16 4 0.1 F 3 4 5 6 2, 8 2 Figure 17. Isolated Data Acquisition System for Process Control Copyright (c) 2013-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 21 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com Typical Applications (continued) 9.2.1.1 Design Requirements Unlike optocouplers, which need external components to improve performance, provide bias, or limit current, ISO71xx only needs two external bypass capacitors to operate. 9.2.1.2 Detailed Design Procedure ISO7131 0.1 F VCC1 0.1 F 16 2 15 INA 3 14 OUTA INB 4 13 OUTB OUTC 5 12 INC 6 11 7 10 8 9 NC ISO7140 0.1 F VCC2 1 GND1 2 mm max from VCC2 2 mm max from VCC1 2 mm max from VCC2 2 mm max from VCC1 0.1 F VCC2 1 16 2 15 INA 3 14 OUTA INB 4 13 OUTB INC 5 12 OUTC IND 6 11 OUTD 7 10 8 9 VCC1 GND2 GND1 NC NC EN2 EN1 GND1 GND2 EN GND2 GND1 Figure 18. Typical ISO7131 Circuit Hook-up Figure 19. Typical ISO7140 Circuit Hook-up 2 mm max from VCC2 2 mm max from VCC1 ISO7141 0.1 F VCC1 GND2 0.1 F VCC2 1 16 2 15 INA 3 14 OUTA INB 4 13 OUTB INC 5 12 OUTD 6 11 7 10 8 9 GND1 GND2 IND EN2 EN1 GND1 OUTC GND2 Figure 20. Typical ISO7141 Circuit Hook-up 22 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 Typical Applications (continued) 9.2.1.3 Application Curves Typical eye diagrams of ISO71xx (see Figure 21, Figure 22, and Figure 23) indicate low jitter and wide open eye at the maximum data rate. Figure 21. Typical Eye Diagram at 40 MBPS, PRBS 216 - 1, 2.7-V Operation Figure 22. Typical Eye Diagram at 40 MBPS, PRBS 216 - 1, 3.3-V Operation Figure 23. Typical Eye Diagram at 50 MBPS, PRBS 216 - 1, 5-V Operation Copyright (c) 2013-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 23 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com Typical Applications (continued) 9.2.2 Isolated RS-485 Interface VIN 3.3V 0.1F 2 Vcc D2 3 1:2.2 MBR0520L 1 SN6501 GND D1 3 1 10F OUT 5 TPS76350 10F 0.1F 4,5 IN EN GND 2 5VISO 10F MBR0520L ISO-BARRIER 0.1F 0.1F 0.1F 2 6 P3.0 XOUT XIN 16 1 DVcc 5 0.1F 11 15 MSP430 UCA0TXD F2132 UCA0RXD 16 DVss 3 4 5 VCC1 VCC2 INA OUTA ISO7131 INB OUTC 7 EN1 4 GND1 2,8 OUTB INC VCC 14 13 12 EN2 10 GND2 2 3 4 1 RE 10 MELF B DE D SN65HVD 3082E A R GND 10 MELF SM712 9,15 4.7nF/ 2kV Figure 24. Isolated RS-485 Interface 9.2.2.1 Design Requirements See previous Design Requirements. 9.2.2.2 Detailed Design Procedure See previous Detailed Design Procedure. 9.2.2.3 Application Curves See previous Application Curves. 24 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC www.ti.com SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 10 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, a 0.1-F bypass capacitor is recommended at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as TI's SN6501. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 data sheet (SLLSEA0). 11 Layout 11.1 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 25). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. * Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. * Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. * Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100pF/in2. * Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide. 11.1.1 PCB Material For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics. 11.2 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces , pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 25. Recommended Layer Stack Copyright (c) 2013-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC 25 ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC SLLSE83F - APRIL 2013 - REVISED JANUARY 2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation * SLLA284, Digital Isolator Design Guide * SLLSEA0, Transformer Driver for Isolated Power Supplies 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ISO7131CC Click here Click here Click here Click here Click here ISO7140CC Click here Click here Click here Click here Click here ISO7140FCC Click here Click here Click here Click here Click here ISO7141CC Click here Click here Click here Click here Click here ISO7141FCC Click here Click here Click here Click here Click here 12.3 Trademarks Modbus is a trademark of Gould Inc. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. SLLA353 - Isolation Glossary. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright (c) 2013-2015, Texas Instruments Incorporated Product Folder Links: ISO7131CC ISO7140CC ISO7140FCC ISO7141CC ISO7141FCC PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) ISO7131CCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7131CC ISO7131CCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7131CC ISO7140CCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140CC ISO7140CCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140CC ISO7140FCCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140FC ISO7140FCCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7140FC ISO7141CCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141CC ISO7141CCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141CC ISO7141FCCDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141FC ISO7141FCCDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7141FC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2014 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7131CCDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7140CCDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7140FCCDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7141CCDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7141FCCDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7131CCDBQR SSOP DBQ 16 2500 367.0 367.0 38.0 ISO7140CCDBQR SSOP DBQ 16 2500 367.0 367.0 38.0 ISO7140FCCDBQR SSOP DBQ 16 2500 367.0 367.0 38.0 ISO7141CCDBQR SSOP DBQ 16 2500 367.0 367.0 38.0 ISO7141FCCDBQR SSOP DBQ 16 2500 367.0 367.0 38.0 Pack Materials-Page 2 PACKAGE OUTLINE DBQ0016A SSOP - 1.75 mm max height SCALE 2.800 SHRINK SMALL-OUTLINE PACKAGE C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 16 1 14X .0250 [0.635] 2X .175 [4.45] .189-.197 [4.81-5.00] NOTE 3 8 9 B .150-.157 [3.81-3.98] NOTE 4 16X .008-.012 [0.21-0.30] .007 [0.17] C A B .069 MAX [1.75] .005-.010 TYP [0.13-0.25] SEE DETAIL A .010 [0.25] GAGE PLANE .004-.010 [0.11-0.25] 0 -8 .016-.035 [0.41-0.88] (.041 ) [1.04] DETAIL A TYPICAL 4214846/A 03/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MO-137, variation AB. www.ti.com EXAMPLE BOARD LAYOUT DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SEE DETAILS SYMM 1 16 16X (.016 ) [0.41] 14X (.0250 ) [0.635] 9 8 (.213) [5.4] LAND PATTERN EXAMPLE SCALE:8X METAL SOLDER MASK OPENING SOLDER MASK OPENING .002 MAX [0.05] ALL AROUND METAL .002 MIN [0.05] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214846/A 03/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM 1 16 16X (.016 ) [0.41] SYMM 14X (.0250 ) [0.635] 9 8 (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:8X 4214846/A 03/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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