Rev. 0.2, May. 2010 K9F2G08U0C Advance 2Gb C-die NAND Flash Single-Level-Cell (1bit/cell) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. 2010 Samsung Electronics Co., Ltd. All rights reserved. -1- Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY Revision History History Revision No. Draft Date Remark Editor 0.0 1. Initial issue Aug. 12, 2009 Advance - 0.1 1. DC Parameter is chagned 2. Typo is modified Dec. 09, 2009 Advance - 0.2 1. Max tR value has changed from 35us to 40us 2. Min tRC/ tWC value has changed from 30ns to 25ns 3. Chapter 2.9, 2.10 AC parameters revised 4. Chapter 2.3 ISB2 MAX value has changed from 50 to 80 5. Chapter 7.0 2plane Erase NOT supported. 6. Chapter 2.8 tDBSY value has changed. May. 03, 2010 Advance H.K.Kim The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. -2- K9F2G08U0C datasheet Rev. 0.2 FLASH MEMORY Table Of Contents 1.0 INTRODUCTION ........................................................................................................................................................ 4 1.1 Product List.............................................................................................................................................................. 4 1.2 Features ...........................................................................................................................................................4 1.3 General Description................................................................................................................................................. 4 1.4 Pin Configuration (TSOP1) ...................................................................................................................................... 5 1.4.1Package Dimensions ......................................................................................................................................... 5 1.5 Pin Configuration (FBGA) ........................................................................................................................................ 6 1.5.1Package Dimensions ......................................................................................................................................... 7 1.6 Pin Description ........................................................................................................................................................ 8 2.0 PRODUCT INTRODUCTION...................................................................................................................................... 9 2.1 Absolute Maximum Ratings ..................................................................................................................................... 10 2.2 Recommended Operating Conditions ..................................................................................................................... 10 2.3 DC And Operating Characteristics(Recommended operating conditions otherwise noted.) ................................... 10 2.4 Valid Block............................................................................................................................................................... 11 2.5 AC Test Condition ................................................................................................................................................... 11 2.6 Capacitance(TA=25C, VCC= 3.3V, f=1.0MHz) ...................................................................................................... 11 2.7 Mode Selection........................................................................................................................................................ 11 2.8 Program / Erase Characteristics ........................................................................................................................12 2.9 AC Timing Characteristics for Command / Address / Data Input ............................................................................ 12 2.10 AC Characteristics for Operation........................................................................................................................... 13 3.0 NAND FLASH TECHNICAL NOTES .......................................................................................................................... 14 3.1 Initial Invalid Block(s) ............................................................................................................................................... 14 3.2 Identifying Initial Invalid Block(s) ............................................................................................................................. 14 3.3 Error In Write Or Read Operation ............................................................................................................................ 15 3.4 Addressing for Program Operation .......................................................................................................................... 17 4.0 SYSTEM INTERFACE USING CE DON'T-CARE. ..................................................................................................... 18 4.1 Command Latch Cycle ............................................................................................................................................ 19 4.2 Address Latch Cycle................................................................................................................................................ 19 4.3 Input Data Latch Cycle ............................................................................................................................................ 20 4.4* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)....................................................................................... 20 4.5 Status Read Cycle .................................................................................................................................................. 21 4.6 Read Operation ....................................................................................................................................................... 21 4.7 Read Operation(Intercepted by CE) ........................................................................................................................ 22 4.8 Random Data Output In a Page ............................................................................................................................. 23 4.9 Page Program Operation......................................................................................................................................... 24 4.10 Page Program Operation with Random Data Input ............................................................................................... 25 4.11 Copy-Back Program Operation With Random Data Input .................................................................................... 26 4.12 Two- Plane Page Program operatoin .................................................................................................................... 27 4.13 Block Erase Operation........................................................................................................................................... 28 4.14 Read ID Operation................................................................................................................................................. 28 5.0 DEVICE OPERATION ................................................................................................................................................ 31 5.1 Page Read............................................................................................................................................................... 31 5.2 Page Program ......................................................................................................................................................... 33 5.3 Copy-back Program................................................................................................................................................. 34 5.4 Read Status............................................................................................................................................................. 35 5.5 Read ID ................................................................................................................................................................... 36 5.6 Reset ....................................................................................................................................................................... 36 5.7 READY/BUSY ......................................................................................................................................................... 37 6.0 DATA PROTECTION & POWER UP SEQUENCE.................................................................................................... 38 7.0 BACKWARD COMPATIBILITY INFORMATION......................................................................................................... 39 -3- K9F2G08U0C datasheet Advance Rev. 0.2 FLASH MEMORY 1.0 INTRODUCTION 1.1 Product List Part Number Vcc Range Organization PKG Type K9F2G08U0C-S 2.7 ~ 3.6v x8 TSOP1 K9F2G08U0C-H 2.7 ~ 3.6v x8 63 FBGA 1.2 Features * Voltage Supply - 3.3V device(K9F2G08U0C): 2.70V ~ 3.60V * Organization - Memory Cell Array : (256M + 8M) x 8bit - Data Register : (2K + 64) x 8bit * Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte * Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 40s(Max.) - Serial Access : 25ns(Min.) * Fast Write Cycle Time - Page Program time : 250s(Typ.) - Block Erase Time : 2ms(Typ.) * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology -Endurance & Data Retention : Refor to the gualification report -ECC regnirement : 1 bit / 528bytes* Command Driven Operation * Unique ID for Copyright Protection * Package : - K9F2G08U0C-SCB0/SIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9F2G08U0C-HCB0/HIB0 : Pb-FREE PACKAGE 63 - ball FBGA (9 x 11 / 0.8 mm pitch) 1.3 General Description Offered in 256Mx8bit, the K9F2G08U0C is a 2G-bit NAND Flash Memory with spare 64M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250s on the (2K+64)Byte page and an erase operation can be performed in typical 2ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F2G08U0Cs extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2G08U0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. -4- Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 1.4 Pin Configuration (TSOP1) K9F2G08U0C-SCB0/SIB0 N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-pin TSOP1 Standard Type 12mm x 20mm N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C 1.4.1 Package Dimensions 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F 0.10 MAX 0.004 Unit :mm/Inch #48 #24 #25 0.50 0.0197 12.40 0.488 MAX ( 0.25 ) 0.010 #1 12.00 0.472 +0.003 0.008-0.001 0.20 -0.03 +0.07 20.000.20 0.7870.008 +0.075 0~8 0.45~0.75 0.018~0.030 +0.003 0.005-0.001 18.400.10 0.7240.004 0.125 0.035 0.25 0.010 TYP 1.000.05 0.0390.002 ( 0.50 ) 0.020 -5- 1.20 0.047MAX 0.05 0.002 MIN datasheet K9F2G08U0C 1.5 Pin Configuration (FBGA) K9F2G08U0C-HCB0/HIB0 Top View 1 2 3 4 5 6 N.C N.C N.C N.C A N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC I/O0 B C D E F NC NC NC Vcc NC I/O1 NC Vcc I/O5 I/O7 Vss I/O2 I/O3 I/O4 I/O6 Vss G H N.C N.C N.C N.C N.C N.C N.C N.C -6- Advance Rev. 0.2 FLASH MEMORY Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 1.5.1 Package Dimensions 63-Ball FBGA (measured in millimeters) Top View Bottom View 9.000.10 0.80 x 9= 7.20 0.80 x 5= 4.00 9.000.10 6 5 0.80 4 3 2 B 1 0.80 (Datum A) A #A1 A D 2.80 E F G H 63-0.450.05 Side View 9.000.10 0.10MAX -7- 0.450.05 1.00(Max.) 2.00 0.25(Min.) 0.20 M A B 11.000.10 0.80 x7= 5.60 11.000.10 C 0.80 x11= 8.80 B (Datum B) datasheet K9F2G08U0C Advance Rev. 0.2 FLASH MEMORY 1.6 Pin Description Pin Name Pin Function I/O0 ~ I/O7 DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. CLE COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ALE ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CE CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. RE READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WE WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WP WRITE PROTECT The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. R/B READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. Vcc POWER VCC is the power supply for device. Vss GROUND N.C NO CONNECTION Lead is not internally connected. NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. -8- datasheet K9F2G08U0C Advance Rev. 0.2 FLASH MEMORY 2.0 PRODUCT INTRODUCTION NAND Flash Memory has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc. require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9G2G08U0C. [Table 1] Command Sets 1st Cycle 2nd Cycle Read Function 00h 30h Read for Copy Back 00h 35h Read ID 90h - Reset FFh - Page Program 80h 10h Copy-Back Program Two-Plane Page Program(2) Block Erase (1) Random Data Input Random Data Output (1) 85h 10h 80h---11h 81h---10h 60h D0h 85h - 05h E0h Acceptable Command during Busy O Read Status 70h - O Read Status 2 F1h - O NOTE : 1) Random Data Input/Output can be executed in a page. 2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh. Caution : Any undefined command inputs are prohibited except for above command set of Table 1. -9- Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 2.1 Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature K9F2G08U0C-XCB0 Symbol Rating VCC -0.6 to +4.6 VIN -0.6 to +4.6 VI/O -0.6 to Vcc + 0.3 (< 4.6V) K9F2G08U0C-XCB0 K9F2G08U0C-XIB0 Short Circuit Current V -10 to +125 TBIAS K9F2G08U0C-XIB0 Unit C -40 to +125 TSTG -65 to +150 C IOS 5 mA NOTE : 1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2.2 Recommended Operating Conditions (Voltage reference to GND, K9F2G08U0C-XCB0 :TA=0 to 70C, K9F2G08U0C-XIB0:TA=-40 to 85C) Parameter Symbol 3.3V Min Typ. Max Unit Supply Voltage VCC 2.7 3.3 3.6 V Supply Voltage VSS 0 0 0 V 2.3 DC And Operating Characteristics(Recommended operating conditions otherwise noted.) Parameter Operating Current Symbol Test Conditions 3.3V Min Typ Max - 20 35 tRC=25ns CE=VIL, IOUT=0mA Page Read with Serial Access ICC1 Program ICC2 - Erase ICC3 - Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1 Stand-by Current(CMOS) ISB2 CE=VCC-0.2, WP=0V/VCC - 10 80 Input Leakage Current ILI VIN=0 to Vcc(max) - - 10 Output Leakage Current ILO VOUT=0 to Vcc(max) - - 10 - 0.8xVcc - Vcc+0.3 - Input High Voltage Input Low Voltage, All inputs VIH(1) V IL(1) Unit Output High Voltage Level VOH K9F2G08B0C: IOH=-100A K9F2G08U0C: IOH=-400A Output Low Voltage Level VOL K9F2G08B0C: IOL=100A K9F2G08U0C: IOL=2.1mA Output Low Current(R/B) IOL(R/B) K9F2G08B0C: VOL=0.1V K9F2G08U0C: VOL=0.4V NOTE : 1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less. 2) Typical value is measured at Vcc= 3.3V, TA=25C. Not 100% tested. - 10 - -0.3 - 0.2xVcc 2.4 - - - - 0.4 8 10 - mA A V mA Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 2.4 Valid Block Parameter Symbol Min Typ. Max Unit K9F2G08U0C NVB 2,008 - 2,048 Blocks NOTE : 1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC. 3) The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations. 2.5 AC Test Condition (K9F2G08U0C-XCB0 :TA=0 to 70C, K9F2G08U0C-XIB0:TA=-40 to 85C, K9F2G08U0C: Vcc=2.7V~3.6V unless otherwise noted) Parameter K9F2G08U0C Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2 Output Load 1 TTL GATE and CL=50pF 2.6 Capacitance(TA=25C, VCC= 3.3V, f=1.0MHz) Symbol Test Condition Min Max Unit Input/Output Capacitance Item CI/O VIL=0V - 10 pF Input Capacitance CIN VIN=0V - 10 pF NOTE : Capacitance is periodically sampled and not 100% tested. 2.7 Mode Selection CLE ALE CE RE WP H L L WE H X L H L H X H L L H H L H L H H L L L H H Data Input L L L H X X X X Mode Read Mode Write Mode Command Input Address Input(5clock) Command Input Address Input(5clock) X Data Output H X During Read(Busy) X X X X X H During Program(Busy) X X X X X H During Erase(Busy) Write Protect X X X (1) X X X X L H X X 0V/VCC(2) NOTE : 1) X can be VIL or VIH. 2) WP should be biased to CMOS high or CMOS low for standby. - 11 - Stand-by Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 2.8 Program / Erase Characteristics Symbol Min Typ Max Unit Program Time Parameter tPROG - 250 750 s Dummy Busy time for Two-Plane Page Program tDBSY - 2.5 3 s Number of Partial Program Cycles Nop - - 4 cycles Block Erase Time tBERS - 2 10 ms NOTE : 1) Typical value is measured at Vcc=3.3V, TA=25C. Not 100% tested. 2) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25C temperature. 2.9 AC Timing Characteristics for Command / Address / Data Input Parameter Symbol Min Max Unit CLS(1) 12 - ns CLE Hold Time tCLH 5 - ns CE Setup Time CS(1) 20 - ns tCH 5 - ns WE Pulse Width tWP 12 - ns ALE Setup Time tALS(1) 12 - ns CLE Setup Time CE Hold Time t t ALE Hold Time tALH 5 - ns Data Setup Time tDS(1) 12 - ns Data Hold Time tDH 5 - ns Write Cycle Time tWC 25 - ns WE High Hold Time Address to Data Loading Time tWH 10 - ns tADL(2) 100 - ns NOTE : 1) The transition of the corresponding control pins must occur only once while WE is held low 2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle - 12 - Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 2.10 AC Characteristics for Operation Parameter Symbol Min Max Unit Data Transfer from Cell to Register tR - 40 s ALE to RE Delay tAR 10 - ns CLE to RE Delay tCLR 10 - ns Ready to RE Low tRR 20 - ns RE Pulse Width tRP 12 - ns WE High to Busy tWB - 100 ns Read Cycle Time tRC 25 - ns RE Access Time tREA - 20 ns CE Access Time tCEA - 25 ns RE High to Output Hi-Z tRHZ - 100 ns CE High to Output Hi-Z tCHZ - 30 ns CE High to ALE or CLE Don't Care tCSD 10 - ns RE High to Output Hold tRHOH 15 - ns CE High to Output Hold tCOH 15 - ns RE High Hold Time tREH 15 - ns tIR 0 - ns RE High to WE Low Output Hi-Z to RE Low tRHW 100 - ns WE High to RE Low tWHR 60 - ns Device Resetting Time(Read/Program/Erase) tRST - 5/10/500(1) s NOTE : 1) If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5s. - 13 - datasheet K9F2G08U0C Advance Rev. 0.2 FLASH MEMORY 3.0 NAND FLASH TECHNICAL NOTES 3.1 Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC. 3.2 Identifying Initial Invalid Block(s) All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 1). Any intentional erasure of the original initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address * Create (or update) Initial Invalid Block(s) Table No Check "FFh" at the column address 2048 of the 1st and 2nd page in the block Check "FFh" Yes No Last Block ? Yes End [Figure 1] Flow chart to create initial invalid block table - 14 - datasheet K9F2G08U0C Advance Rev. 0.2 FLASH MEMORY NAND Flash Technical Notes (Continued) 3.3 Error In Write Or Read Operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks. Failure Mode Write Read ECC Detection and Countermeasure sequence Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement Single Bit Failure Verify ECC -> ECC Correction : Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection Program Flow Chart Start Write 80h Write Address Write Data Write 10h Read Status Register I/O 6 = 1 ? or R/B = 1 ? * Program Error No Yes No I/O 0 = 0 ? Yes Program Completed * : If program operation results in an error, map out the block including the page in error and copy the target data to another block. - 15 - Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Write 30h Read Status Register Read Data ECC Generation No I/O 6 = 1 ? or R/B = 1 ? No Reclaim the Error Yes * No Erase Error Yes I/O 0 = 0 ? Page Read Completed Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement 1st (n-1)th nth { Block A 1 an error occurs. (page) 1st (n-1)th nth Buffer memory of the controller. { Verify ECC Block B 2 (page) * Step1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B') * Step3 Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'. * Step4 Do not erase or program to Block 'A' by creating an 'invalid block' table or other appropriate scheme. - 16 - Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 3.4 Addressing for Program Operation Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0. Page 63 (64) Page 63 : Page 31 : (32) Page 31 : Page 2 Page 1 Page 0 (1) : (3) (2) (1) Page 2 Page 1 Page 0 Data register (3) (32) (2) Data register From the LSB page to MSB page DATA IN: Data (1) (64) Ex.) Random page program (Prohibition) Data (64) DATA IN: Data (1) - 17 - Data (64) Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 4.0 SYSTEM INTERFACE USING CE DON'T-CARE. CLE For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of -seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption. I/Ox ALE 80h Address(5Cycles) tCS WE CE CE don't-care Data Input tCH Data Input 10h tCEA CE CE tREA tWP RE WE I/O0~7 out [Figure 2] Program Operation with CE don't-care. CLE CE don't-care CE RE ALE tR R/B WE I/OX 00h Address(5Cycle) Data Output(serial access) 30h [Figure 3] Read Operation with CE don't-care. NOTE : Device K9F2G08U0C I/O DATA I/Ox Data In/Out Col. Add1 Col. Add2 ADDRESS Row Add1 Row Add2 Row Add3 I/O 0 ~ I/O 7 2,112byte A0~A7 A8~A11 A12~A19 A20~A27 A28 - 18 - Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 4.1 Command Latch Cycle CLE tCLS tCLH tCS tCH CE tWP WE tALH tALS ALE tDH tDS I/Ox Command 4.2 Address Latch Cycle tCLS CLE tCS tWC tWC tWC tWC CE tWP tWP tWP tWP WE tWH tALH tALS tALS tWH tALH tALS tWH tALH tALS tWH tALH tALS tALH ALE tDS I/Ox tDH Col. Add1 tDS tDH Col. Add2 - 19 - tDS tDH Row Add1 tDS tDH Row Add2 tDS tDH Row Add3 Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 4.3 Input Data Latch Cycle tCLH CLE tCH CE tWC ALE tWP tALS tWP tWP WE tWH tDH tDS tDH tDS tDH tDS I/Ox DIN final DIN 1 DIN 0 4.4* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L) tRC CE tCHZ tREH tREA tREA tREA tCOH RE tRHZ tRHZ I/Ox Dout Dout tRHOH tRR R/B NOTE : Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRHOH starts to be valid when frequency is lower than 33MHz. - 20 - Dout Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 4.5 Status Read Cycle tCLR CLE tCLS tCLH tCS CE tCH tWP WE tCEA tCHZ tCOH tWHR RE tDS I/Ox tDH tRHZ tREA tIR tRHOH Status Output 70h/F1h 4.6 Read Operation tCLR CLE CE tWC WE tCSD tWB tAR ALE tR tRHZ tRC RE I/Ox 00h Col. Add1 Col. Add2 Column Address Row Add1 Row Add2 Row Add3 30h Dout N Row Address Busy R/B - 21 - Dout N+1 tRR Dout M Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 4.7 Read Operation(Intercepted by CE) tCLR CLE CE tCSD WE tCOH tWB tCHZ tAR ALE tRC tR RE tRR I/Ox 00h Col. Add1 Col. Add2 Column Address Row Add1 Row Add2 Row Add3 Dout N 30h Row Address Busy R/B - 22 - Dout N+1 Dout N+2 - 23 - R/B I/Ox RE ALE WE CE CLE 00h Col. Add2 Column Address Col. Add1 Row Add2 Row Add3 Row Address Row Add1 30h tAR Busy tRR tR tWB Dout N tRC Dout N+1 tRHW 05h Col Add2 Column Address Col Add1 E0h tWHR tCLR Dout M tREA Dout M+1 K9F2G08U0C datasheet Advance Rev. 0.2 FLASH MEMORY 4.8 Random Data Output In a Page Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 4.9 Page Program Operation CLE CE tWC tWC tWC WE tWB tAD tPROG tWHR ALE I/Ox 80h Co.l Add1 Col. Add2 SerialData Column Address Input Command Row Add1 Row Add2 Row Add3 Row Address RE Din Din N M 1 up to m Byte Serial Input 70h Program Command NOTE : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. - 24 - I/O0 Read Status Command R/B 10h I/O0=0 Successful Program I/O0=1 Error in Program - 25 - Col. Add1 Col. Add2 Serial Data Column Address Input Command 80h Row Add2 Row Add3 Row Address Row Add1 tWC tADL Din M 85h Col. Add1 Col. Add2 Serial Input Random Data Column Address Input Command Din N tWC NOTE : tADL is h time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. R/B I/Ox RE ALE WE tWC CE tADL Din K Serial Input Din J CLE 10h Program Command tWB tPROG Read Status Command 70h tWHR I/O0 K9F2G08U0C datasheet Advance Rev. 0.2 FLASH MEMORY 4.10 Page Program Operation with Random Data Input - 26 - 00h tWC Column Address Row Address Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 35h tR tWB Column Address Row Address Data 1 tADL Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Copy-Back Data Input Command Busy 85h NOTE : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. R/B I/Ox RE ALE WE CE CLE Data N 10h tWB 70h tWHR I/Ox Read Status Command tPROG I/O0=0 Successful Program I/O0=1 Error in Program Busy K9F2G08U0C datasheet Advance Rev. 0.2 FLASH MEMORY 4.11 Copy-Back Program Operation With Random Data Input R/B I/Ox RE ALE Din N Din M - 27 80h A0 ~ A11 : Valid A12 ~ A17 : Fixed 'Low' : Fixed 'Low' A18 A19 ~ A29 : Fixed 'Low' Col Add1,2 & Row Add 1,2,3 2112 Byte Data Address & Data Input 11h max. 3us Note tDBSY 81h 81h Din N A0 ~ A11 : Valid A12 ~ A17 : Valid : Fixed 'High' A18 A19 ~ A29 : Valid Col Add1,2 & Row Add 1,2,3 2112 Byte Data Address & Data Input Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 10h tPROG Program Confirm Command (True) 10h Din M tWB tPROG I/O 70h/F1h Read Status Command 70h/F1h tWHR datasheet NOTE: Any command between 11h and 81h is prohibited except 70h and FFh. I/O0~7 R/B Ex.) Two-Plane Page Program tDBSY tDBSY : typ. 2.5us 11h Program Page Row Address 1 up to 2112 Byte Data Command (Dummy) Serial Input Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Serial Data Column Address Input Command 80h tWB WE tWC CE CLE K9F2G08U0C Advance Rev. 0.2 FLASH MEMORY 4.12 Two- Plane Page Program operatoin Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 4.13 Block Erase Operation CLE CE tWC WE tBERS tWB tWHR ALE RE I/Ox 60h Row Add1 Row Add2 Row Add3 D0h 70h I/O 0 Busy R/B Erase Command Auto Block Erase Setup Command Row Address Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase 4.14 Read ID Operation CLE CE WE tAR ALE RE tREA I/Ox 00h 90h Read ID Command Address 1cycle ECh Device Code 3rd cyc. 4th cyc. 5th cyc. Maker Code Device Code Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle K9F2G08U0C DAh 10h 15h 44h - 28 - Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY ID Definition Table Description 1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Maker Code Device Code Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size 3rd ID Data Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 Internal Chip Number 1 2 4 8 Cell Type 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell Number of Simultaneously Programmed Pages 1 2 4 8 Interleave Program Between multiple chips Not Support Support Cache Program Not Support Support 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4th ID Data Description Page Size (w/o redundant area ) 1KB 2KB 4KB 8KB Block Size (w/o redundant area ) 64KB 128KB 256KB 512KB Redundant Area Size ( byte/512byte) 8 16 Organization x8 x16 Serial Access Minimum 50ns/30ns 25ns Reserved Reserved I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 - 29 - 0 0 1 1 0 1 0 1 Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 5th ID Data Description Plane Number 1 2 4 8 Plane Size (w/o redundant Area) 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb Reserved I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 0 0 1 1 0 0 0 0 1 1 1 1 0 - 30 - 0 0 1 1 0 0 1 1 I/O1 I/O0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 datasheet K9F2G08U0C Advance Rev. 0.2 FLASH MEMORY 5.0 DEVICE OPERATION 5.1 Page Read Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 40s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. CLE CE WE ALE RE I/Ox t R/B 00h Address(5Cycle) Data Output(Serial Access) 30h Col. Add.1,2 & Row Add.1,2,3 Data Field Spare Field [Figure 4] Read Operation - 31 - Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY t R/B RE I/Ox 00h Address 5Cycles Data Output 30h Col. Add.1,2 & Row Add.1,2,3 05h Address 2Cycles E0h Data Output Col. Add.1,2 Data Field Spare Field [Figure 5] Random Data Output In a Page - 32 - Data Field Spare Field Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 5.2 Page Program The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 6). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. tPROG R/B "0" I/Ox 80h Address & Data Input 10h Pass I/O0 70h Col. Add.1,2 & Row Add.1,2,3 "1" Data Fail [Figure 6] Program & Read Status Operation tPROG R/B "0" I/Ox 80h Address & Data Input Col. Add.1,2 & Row Add1,2,3 Data 85h Address & Data Input 10h Col. Add.1,2 Data 70h I/O0 "1" Fail [Figure 7] Random Data Input In a Page - 33 - Pass Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 5.3 Copy-back Program Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy DataInput command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8 & Figure 9). The command register remains in Read Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 9. tR tPROG R/B I/Ox 00h Add.(5Cycles) 35h Add.(5Cycles) 85h 70h 10h Col. Add.1,2 & Row Add.1,2,3 Destination Address Col. Add.1,2 & Row Add.1,2,3 Source Address "0" I/O0 Pass "1" Fail NOTE : Copy-Back Program operation is allowed only within the same memory plane. [Figure 8] Page Copy-Back Program Operation tPROG tR R/B I/Ox 00h Add.(5Cycles) 35h Col. Add.1,2 & Row Add.1,2,3 Source Address 85h Add.(5Cycles) Data Col. Add.1,2 & Row Add.1,2,3 85h Add.(2Cycles) Data 10h Col. Add.1,2 Destination Address There is no limitation for the number of repetition. [Figure 9] Page Copy-Back Program Operation with Random Data Input - 34 - 70h Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 5.4 Read Status The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h/F1h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 2 for specific Status Register definitions and Table 3 for specific F1h Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. [Table 2] Read Status Register Definition for 70h Command I/O Page Program Block Erase Read I/O 0 Pass/Fail Pass/Fail Not use Pass : "0" Definition I/O 1 Not use Not use Not use Don't -cared I/O 2 Not use Not use Not use Don't -cared I/O 3 Not Use Not Use Not Use Don't -cared I/O 4 Not Use Not Use Not Use Don't -cared I/O 5 Not Use Not Use Not Use Don't -cared I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" I/O 7 Write Protect Write Protect Write Protect Protected : "0" Fail : "1" Ready : "1" Not Protected : "1" "1"otected NOTE : I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed. [Table 3] Read Status 2 Register Definition for F1h Command I/O No. Page Program Block Erase Read I/O 0 Chip Pass/Fail Chip Pass/Fail Not use Pass : "0" Definition Fail : "1" I/O 1 Plane0 Pass/Fail Plane0 Pass/Fail Not use Pass : "0" Fail : "1" I/O 2 Plane1 Pass/Fail Plane1 Pass/Fail Not use Pass : "0" Fail : "1" I/O 3 Not Use Not Use Not Use Don't -cared I/O 4 Not Use Not Use Not Use Don't -cared Don't -cared I/O 5 Not Use Not Use Not Use I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" I/O 7 Write Protect Write Protect Write Protect Protected : "0" NOTE : I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed. - 35 - Ready : "1" Not Protected : "1" "1"otected Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 5.5 Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 10 shows the operation sequence. tCLR CLE tCEA CE WE tAR ALE tWHR RE I/OX tREA 00h ECh Address. 1cycle Maker code 90h Device Code 3rd Cyc. 4th Cyc. 5th Cyc. Device code [Figure 10] Read ID Operation Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle K9F2G08U0C DAh 10h 15h 44h 5.6 Reset The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 11 below. tRS R/B I/OX FFh [Figure 11] RESET Operation Operation mode Mode After Power-up After Reset 00h Command is latched Waiting for next command - 36 - Advance Rev. 0.2 datasheet K9F2G08U0C FLASH MEMORY 5.7 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/ B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Figure 12). Its value can be determined by the following guidance. Rp VCC ibusy 3.3V device - VOL : 0.4V, VOH : 2.4V Ready Vcc R/B open drain output VOH CL VOL Busy tf tr GND Device [Figure 12] Rp vs tr ,tf & Rp vs ibusy @ Vcc = 3.3V, Ta = 25C , CL = 50pF 2.4 tr,tf [s] 2m Ibusy [A] 200 Ibusy 200n 150 1.2 100 100n 0.6 50 3.6 tf 1K 1m 0.8 tr 3.6 3.6 2K 3K Rp(ohm) 4K 3.6 Rp value guidance Rp(min, 3.3V part) = 3.2V VCC(Max.) - VOL(Max.) IOL + IL = 8mA + IL where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr - 37 - datasheet K9F2G08U0C Advance Rev. 0.2 FLASH MEMORY 6.0 DATA PROTECTION & POWER UP SEQUENCE The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and powerdown. A recovery time of minimum 1ms is required before internal circuit gets ready for any command sequences as shown in Figure 13. The two step command sequence for program/erase provides additional software protection. ~ 2.3V ~ 2.3V High VCC WP Don't care WE Operation Ready/Busy 1ms 5 ms max Invalid Don't care [Figure 13] AC Waveforms for Power Transition - 38 - K9F2G08U0C datasheet Advance Rev. 0.2 FLASH MEMORY 7.0 BACKWARD COMPATIBILITY INFORMATION The below table shows key parameters which are different with previous product, so that the host could use make or modify its firmware without misunderstanding of compatibility. But the below table don't have all the difference with previous product, but only key parameters' changing which can be defined to have an effect on developing NAND firmware or hardware. Part ID Previous Generation Product Current Generation Device K9F2G08U0B K9F2G08U0C Features & Operations 1. tR: 25us / tPROG(200us typ, 700us Max) tERS(1.5ms Typ, 10ms Max) 2. tRC/tWC: 25ns 3. 2 Plane Program: support 4. 2Plane Copy-back Program: Support 5. 2Plane Erase: Support 6. EDO: Support 1. tR: 40us / tPROG(250us typ, 750us Max) tERS(2ms Typ, 10ms Max) 2. tRC/tWC: 25ns 3. 2 Plane Program: support 4. 2Plane Copy-back Program: N/A 5. 2Plane Erase: N/A 6. EDO: N/A AC & DC Parameters 1. ICC1 : 15mA(typ)/ 30mA(max) 2. ICC2 : 15mA(typ)/ 30mA(max) 3. ICC3 : 15mA(typ)/ 30mA(max) 1. ICC1 : 20mA(typ)/ 35mA(max) 2. ICC2 : 20mA(typ)/ 35mA(max) 3. ICC3 : 20mA(typ)/ 35mA(max) Technical Notes - 39 -