High Efficiency Integrated Power Solution
for Multicell Lithium Ion Applications
Data Sheet
ADP5080
FEATURES
Wide input voltage range: 4.0 V to 15 V
High efficiency architecture
Up to 2 MHz switching frequency
6 synchronous rectification dc-to-dc converters
Channel 1 buck regulator: 3 A maximum
Channel 2 buck regulator: 1.15 A maximum
Channel 3 buck regulator: 1.5 A maximum
Channel 4 buck regulator: 0.8 A maximum
Channel 5 buck regulator: 2 A maximum
Channel 6 configurable buck or buck boost regulator
2 A maximum for buck regulator configuration
1.5 A maximum for buck boost regulator configuration
Channel 7 high voltage, high performance LDO regulator:
30 mA maximum
2 low quiescent current keep-alive LDO regulators
LDO1 regulator: 400 mA maximum
LDO2 regulator: 300 mA maximum
Control circuit
Charge pump for internal switching driver power supply
I2C-programmable output levels and power sequencing
Package: 72-ball, 4.5 mm × 4.0 mm × 0.6 mm WLCSP
(0.5 mm pitch)
APPLICATIONS
DSLR cameras
Non-reflex (mirrorless) cameras
Portable instrumentation
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The ADP5080 is a fully integrated, high efficiency power
solution for multicell lithium ion battery applications. The
device can connect directly to the battery, which eliminates
the need for preregulators and, therefore, increases the battery
life of the system.
The ADP5080 integrates two keep-alive LDO regulators, five
synchronous buck regulators, a configurable four-switch buck
boost regulator, and a high voltage LDO regulator. The ADP5080
is a highly integrated power solution that incorporates all power
MOSFETs, feedback loop compensation, voltage setting resistor
dividers, and discharge switches, as well as a charge pump to
generate a global bootstrap voltage.
All these features help to minimize the number of external
components and PCB space required, providing significant
advantages for portable applications. The switching frequency
is selectable on each channel from 750 kHz to 2 MHz.
Key functions for power applications, such as soft start, selectable
preset output voltage, and flexible power-up and power-down
sequences, are provided on chip and are programmable via the
I2C interface with fused factory defaults. The ADP5080 is available
in a 72-ball WLCSP 0.5 mm pitch package.
LDO1
LDO2
I
2
C
INTERFACE
CONTROL
LOGIC
OSCILLATOR
VOLTAGE
REFERENCE
SCL
SDA
ENABLE
3V T O 3.3V, 300mA
1.0V TO 3.3V, 1.15A
CH1 BUCK
REGULATOR 0.80V TO 1.20V, 3A
5.0V TO 5.5V, 400mA
CHARGE
PUMP
1.2V TO 1.8V/ ADJ, 1. 5A
1.8V TO 3.55V/ ADJ, 0. 8A
3.0V TO 5.0V, 2A
3.5V TO 5.5V/ ADJ
BUCK ONLY: 2A
BUCK BOO S T: 1.5A
5V T O 12V , 30mA
11639-001
FAULT
4V T O 15V
4V T O 15V
5V T O 25V
4V T O 15V
4V T O 15V
4V T O 15V
4V T O 15V
4V T O 15V
CH 3 BUCK
REGULATOR
CH2 BUCK
REGULATOR
CH 4 BUCK
REGULATOR
CH 6
BUCK BOO S T
REGULATOR
CH 5 BUCK
REGULATOR
CH7 LDO
REGULATOR
Rev. A Document Feedback
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ADP5080 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Housekeeping Block Specifications ........................................... 4
DC-to-DC Converter Block Specifications .............................. 5
Linear Regulator Block Specifications ....................................... 7
I2C Interface Timing Specifications ........................................... 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
Application Circuit ......................................................................... 18
Theory of Operation ...................................................................... 19
UVLO and POR .......................................................................... 19
Discharge Switch ........................................................................ 19
Keep-Alive LDO Regulators ..................................................... 19
DC-to-DC Converter Channels ............................................... 22
Light Load and Other Modes of Operation
for the DC-to-DC Converter Channels .................................. 27
Switching Clock .......................................................................... 28
Soft Start Function ..................................................................... 29
Channel 7: High Voltage LDO Regulator ............................... 29
Charge Pump .............................................................................. 29
Enabling and Disabling the Output Channels........................ 30
Power-Good Function ............................................................... 31
Fault Function ............................................................................. 31
Undervoltage Protection (UVP) .............................................. 32
Overvoltage Protection (OVP) ................................................. 33
Applications Information .............................................................. 34
Component Selection for the Buck and Buck Boost
Regulators .................................................................................... 34
Component Selection for the LDO Regulators ...................... 36
PCB Layout Recommendations ............................................... 36
Thermal Considerations ............................................................ 37
I2C Interface .................................................................................... 38
SDA and SCL Pins ...................................................................... 38
I2C Address .................................................................................. 38
Self-Clearing Register Bits ......................................................... 38
I2C Interface Timing Diagrams ................................................ 38
Control Register Information ....................................................... 40
Control Register Map ................................................................ 40
Control Register Details ............................................................ 41
Factory Default Options ................................................................ 61
Outline Dimensions ....................................................................... 63
Ordering Guide .......................................................................... 63
REVISION HISTORY
4/14—Revision A: Initial Version
Rev. A | Page 2 of 64
Data Sheet ADP5080
SPECIFICATIONS
TJ = 25°C, VVBATT = 7.2 V, VVREG1 = VVDRx = 5 V, V VREG2 = VVDDIO = 3.3 V, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE
VBATT
V
VBATT
4.0
15
V
Applies to PVIN1, PVIN2, PVIN3,
PVIN4, PVIN5, and PVIN6
VILDO7 VVILDO7 5 25 V
VDDIO VVDDIO 1.6 3.6 V
QUIESCENT CURRENT
Operating Quiescent Current IQ (VIN) 8 11 mA All channels on, nonswitching
VDDIO IQ (VDDIO_OP) 0.2 µA VVDDIO = VSCL = VSDA = 3.3 V
Standby Current IQ (VBAT T_STNBY1) 12 20 µA Includes LDO1 and LDO2, EN low
I
Q (VBATT_STNBY2)
1.25
mA
SEL_FSW = 1, FREQ_CP = 01
UNDERVOLTAGE LOCKOUT UVLO
UVLO Rising Threshold
V
UVLO (R)
3.45
3.7
3.85
V
UVLO Falling Threshold VUVLO (F) 3.45 3.55 V At PVIN1
VBATT UVLO Threshold VUVLO (BAT T) 3.3 V At VBATT, falling
Reset Threshold VUVLO (POR) 2.4 V At VREG2, falling
OSCILLATOR CIRCUIT
Switching Frequency fSW 1.98 2.0 2.02 MHz ROSC = 100 , SEL_FSW = 0
1.48 1.5 1.52 MHz ROSC = 100 , SEL_FSW = 1
SYNC Pin, Input Clock
Frequency Range fSYNC 0.5 2.0 MHz ROSC = 100
Minimum On Pulse Width tSYNC_MIN_ON 100 ns
Minimum Off Pulse Width tSYNC_MIN_OFF 100 ns
High Logic VH (SYNC) 0.8 × VVREG2 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C
Low Logic VL (SYNC) 0.3 × VVREG2 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C
LOGIC INPUTS
EN Pin
High Level Threshold VIH (EN) 2.15 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C
Low Level Threshold VIL (EN) 1.45 V VVREG2 = 3.3 V, 25°C ≤ TJ ≤ +85°C
EN34 Pin
High Level Threshold VIH (EN34) 1.25 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C
Low Level Threshold VIL (EN34) 0.70 V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C
SCL and SDA Pins
High Level Threshold VIH (I2C) 0.75 × VVDDIO V VVDDIO = 3.3 V, −25°C ≤ TJ ≤ +85°C
Low Level Threshold VIL (I2C) 0.3 × VVDDIO V VVDDIO = 3.3 V, −25°C ≤ TJ ≤ +85°C
LOGIC OUTPUTS
SDA Pin
Low Level Output Voltage
V
OL (SDA)
0.4
V
3.0 mA sink current, −25°C ≤ TJ
+85°C
Leakage Current ILEAK (SDA) 10 nA VSDA = 3.3 V
CLKO Pin
High Level Output Voltage VOH (CLKO) VVREG2 − 0.4 V 3.0 mA sink current, −25°C ≤ TJ
+85°C
Low Level Output Voltage VOL (CLKO) 0.4 V 3.0 mA sink current, −25°C ≤ TJ
+85°C
FAULT Pin
Low Level Output Voltage VOL (FAULT) 0.4 V 3.0 mA source current, −25°C ≤
TJ ≤ +85°C
Leakage Current
I
LEAK (FAULT)
10
nA
FAULT
Rev. A | Page 3 of 64
ADP5080 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
POWER GOOD
Rising Threshold VPGOOD (R) 83 % Measured at VOUT
Falling Threshold VPGOOD (F) 79 % Measured at VOUT
OVERVOLTAGE/UNDERVOLTAGE
OVP Threshold VOVP 125 137 % Measured at VOUT
UVP Threshold VUVP 48 65 % Measured at VOUT
THERMAL SHUTDOWN TSD
Rising Threshold TTSD 165 °C
Hysteresis TTSD_HYS 15 °C
HOUSEKEEPING BLOCK SPECIFICATIONS
TJ = 25°C, VVBATT = 7.2 V, VVREG1 = VVDRx = 5 V, V VREG2 = VVDDIO = 3.3 V, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
LDO1
Output Voltage (VREG1 Pin)
Fixed Voltage Range, 1 Bit
V
VREG1
5.0
5.5
V
VBATT
VREG1
VREG1
Voltage Accuracy VVREG1 (DEFAULT) −2 +2 % VVBAT T = VVREG1 + 0.5 V, IVREG1 = 10 mA
Load Regulation ∆VVREG1/IVREG1 3.5 %/A IVREG1 = 4 mA to 95 mA
Line Regulation ∆VVREG1/VVBATT 0.03 %/V VVBAT T = (VVREG1 + 0.5 V) to 15 V
Current-Limit Threshold ILDO1_ILIM 390 550 mA VVREG1 = 90% of nominal
Dropout Voltage 0.15 V IVREG1 = 100 mA, VVREG1 = 5 V
Input Select Switch
On Resistance
RDSON_VISW1 795 VVISW1 = 5 V
COUT Discharge Switch
On Resistance
RDIS_LDO1 1 VVREG1 = 1 V
LDO2
Output Voltage (VREG2 Pin)
Fixed Voltage Range, 2 Bits VVREG2 3.0 3.3 V IVREG2 = 10 mA
Voltage Accuracy VVREG2 (DEFAULT) −2 +2 % IVREG2 = 10 mA
Load Regulation
∆V
VREG2
/I
VREG2
5.5
%/A
VREG2
Current-Limit Threshold ILDO2_ILIM 290 400 mA VVREG2 = 90% of nominal
Input Select Switch
On Resistance
RDSON_VISW2 1409 VVISW2 = 3.3 V
COUT Discharge Switch
On Resistance
RDIS_LDO2 12 Ω VVREG2 = 1 V
CHARGE PUMP
C+ Switch On Resistance
Low-Side
R
DSON_C+SW1
1.1
Ω
High-Side RDSON_C+SW2 1.0 Ω Sink, C+ to BSTCP
C− Switch On Resistance
High-Side RDSON_CSW1 1.0 Ω Source, VDR5 to C
Low-Side RDSON_CSW2 785 Sink, Cto PGND5
Shunt Switch On Resistance RDSON_CP 3.3 Ω BSTCP to PVINCP, EN low
Charge Pump Start-Up Threshold
CP
START
4.0
V
Rev. A | Page 4 of 64
Data Sheet ADP5080
DC-TO-DC CONVERTER BLOCK SPECIFICATIONS
TJ = 25°C, VVBATT = 7.2 V, VVREG1 = VVDRx = 5 V, V VREG2 = VVDDIO = 3.3 V, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CHANNEL 1 SYNC BUCK REGULATOR
Channel 1 Output Voltage (FB1 Pin)
Fixed Voltage Range, 5 Bits VFB1 0.89 1.20 V REDUCE_VOUT1 = 0
0.80 1.11 V REDUCE_VOUT1 = 1
Feedback Voltage Accuracy
at Default VID Code
VFB1 (DEFAULT) −0.8 +0.8 %
−1.3 +1.3 % −25°C ≤ TJ ≤ +85°C
Load Regulation ∆VFB1/ILOAD1 0.15 %/A ILOAD1 = 20 mA to 2 A,
AUTO-PSM1 = 0
Line Regulation ∆VFB1/VPVIN1 0.004 %/V VPVIN1 = 5 V to 15 V, ILOAD = 1 A
SW1A Pin
High-Side Power FET On Resistance RDSON_1AH 250 ID = 100 mA
Low-Side Power FET On Resistance RDSON_1AL 130 ID = 100 mA
SW1B Pin
High-Side Power FET On Resistance RDSON_1BH 175 ID = 100 mA, GATE_SCAL1 = 0
Low-Side Power FET On Resistance RDSON_1BL 95 ID = 100 mA
SW1A and SW1B Pins
Switch Current Limit ICL1 3.1 4.0 A Valley current, −25°C ≤ TJ ≤ +85°C
Minimum Off Time tOFF1 (MIN) 115 ns
Minimum Duty Cycle DMIN1 0 %
Soft Start Time tSS1 4 ms SS1 = 10
COUT Discharge Switch On Resistance RDIS1 125 Ω VFB1 = 1 V
CHANNEL 2 SYNC BUCK REGULATOR
Channel 2 Output Voltage (FB2 Pin)
Fixed Voltage Range, 4 Bits VFB2 1.0 3.3 V
Feedback Voltage Accuracy
at Default VID Code
VFB2 (DEFAULT) −0.8 +0.8 %
−1.3 +1.3 % −25°C ≤ TJ ≤ +85°C
Load Regulation ∆VFB2/ILOAD2 0.25 %/A ILOAD2 = 10 mA to 1.0 A,
AUTO-PSM2 = 0
Line Regulation
∆V
FB2
/V
PVIN2
0.004
%/V
V
PVIN2
= 5 V to 15 V, I
LOAD2
= 500 mA
SW2 Pins
High-Side Power FET On Resistance RDSON_2H 235 ID = 100 mA
Low-Side Power FET On Resistance RDSON_2L 165 ID = 100 mA
Switch Current Limit ICL2 1.2 1.8 A Valley current, −25°C ≤ TJ ≤ +85°C
Minimum Off Time tOFF2 (MIN) 100 ns
Minimum Duty Cycle
D
MIN2
0
%
Soft Start Time tSS2 4 ms SS2 = 10
COUT Discharge Switch On Resistance RDIS2 125 Ω VFB2 = 1 V
CHANNEL 3 SYNC BUCK REGULATOR
Channel 3 Output Voltage (FB3 Pin)
Fixed Voltage Range, 3 Bits VFB3 1.2 1.8 V
Minimum Adjustable Voltage 0.8 V VID3 = 111
Feedback Voltage Accuracy
at Default VID Code
VFB3 (DEFAULT) −0.8 +0.8 %
−1.3 +1.3 % −25°C ≤ TJ ≤ +85°C
Load Regulation ∆VFB3/ILOAD3 0.17 %/A ILOAD3 = 15 mA to 1.5 A,
AUTO-PSM3 = 0
Line Regulation ∆VFB3/VPVIN3 0.003 %/V VPVIN3 = 5 V to 15 V, ILOAD3 = 700 mA
Rev. A | Page 5 of 64
ADP5080 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SW3 Pins
High-Side Power FET On Resistance RDSON_3H 155 ID = 100 mA
Low-Side Power FET On Resistance RDSON_3L 100 ID = 100 mA
Switch Current Limit ICL3 2.05 2.8 A Valley current, −25°C ≤ TJ ≤ +85°C
Minimum Off Time
t
OFF3 (MIN)
90
ns
Minimum Duty Cycle DMIN3 0 %
Soft Start Time tSS3 4 ms SS3 = 10
COUT Discharge Switch On Resistance RDIS3 125 Ω VFB3 = 1 V
CHANNEL 4 SYNC BUCK REGULATOR
Channel 4 Output Voltage (FB4 Pin)
Fixed Voltage Range, 3 Bits VFB4 1.8 3.55 V
Minimum Adjustable Voltage 0.8 V VID4 = 111
Feedback Voltage Accuracy
at Default VID Code
VFB4 (DEFAULT) −1 +1 %
−2 +2 % −25°C ≤ TJ ≤ +85°C
Load Regulation ∆VFB4/ILOAD4 0.10 %/A ILOAD4 = 10 mA to 800 mA,
AUTO-PSM4 = 0
Line Regulation ∆VFB4/VPVIN4 0.003 %/V VPVIN4 = 5 V to 15 V, ILOAD4 = 400 mA
SW4 Pin
High-Side Power FET On Resistance RDSON_4H 350 ID = 100 mA
Low-Side Power FET On Resistance RDSON_4L 345 ID = 100 mA
Switch Current Limit ICL4 0.96 1.4 A Peak current, −25°C ≤ TJ ≤ +85°C
Minimum On Time tON4 (MIN) 75 ns
Maximum Duty Cycle DMAX4 100 %
Soft Start Time
t
SS4
4
ms
SS4 = 10
COUT Discharge Switch On Resistance RDIS4 125 Ω VFB4 = 1 V
CHANNEL 5 SYNC BUCK REGULATOR
Channel 5 Output Voltage (FB5 Pin)
Fixed Voltage Range, 3 Bits VFB5 3.0 5.0 V
Feedback Voltage Accuracy
at Default VID Code
VFB5 (DEFAULT) −1 +1 %
−2 +2 % −25°C ≤ TJ ≤ +85°C
Load Regulation
∆V
FB5
/I
LOAD5
0.05
%/A
I
LOAD5
= 20 mA to 2 A,
AUTO-PSM5 = 0
Line Regulation ∆VFB5/VPVIN5 0.001 %/V VPVIN5 = 5 V to 15 V, ILOAD5 = 1 A
SW5 Pins
High-Side Power FET On Resistance RDSON_5H 200 ID = 100 mA
Low-Side Power FET On Resistance RDSON_5L 120 ID = 100 mA
Switch Current Limit
I
CL5
2.4
3
A
Peak current, −25°C ≤ T
J
≤ +85°C
Minimum On Time tON5 (MIN) 75 ns
Maximum Duty Cycle DMAX5 100 %
Soft Start Time tSS5 4 ms SS5 = 10
COUT Discharge Switch On Resistance RDIS5 125 Ω VFB5 = 1 V
CHANNEL 6 BUCK BOOST REGULATOR
Channel 6 Output Voltage (FB6 Pin)
Fixed Voltage Range, 4 Bits VFB6 3.5 5.5 V
Minimum Adjustable Voltage
0.8
V
VID6 = 1111
Accuracy at Default VID Code VVOUT6 (DEFAU LT ) −1 +1 %
−2 +2 % −25°C ≤ TJ ≤ +85°C
Load Regulation ∆VVOUT6/ILOAD6 0.05 %/A Buck boost configuration, ILOAD6 =
15 mA to 1.5 A, AUTO-PSM6 = 0
Line Regulation ∆VVOUT6/
VPVIN6
0.001 %/V VPVIN6 = 5 V to 15 V, ILOAD6 = 700 mA
Rev. A | Page 6 of 64
Data Sheet ADP5080
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SW6A Pins
Low-Side Power FET On Resistance RDSON_6AL 95 ID = 100 mA, VVDR6 = 5 V
High-Side Power FET On Resistance RDSON_6AH 60 ID = 100 mA, VVDR6 = 5 V
High-Side Switch Current Limit ICL6A 3.2 4.4 A Peak current, −25°C ≤ TJ ≤ +85°C
Minimum On Time
t
ON6 (MIN)
80
ns
SW6A high-side on time
SW6B Pins
Low-Side Power FET On Resistance RDSON_6BL 50 ID = 100 mA
High-Side Power FET On Resistance RDSON_6BH 55 ID = 100 mA
Boost Minimum Duty Cycle DMIN6B 0 % SW6B low-side duty cycle
Soft Start Time tSS6 4 ms SS6 = 10
C
OUT
Discharge Switch On Resistance
R
DIS6
110
Ω
V
VOUT6
= 1 V
LINEAR REGULATOR BLOCK SPECIFICATIONS
TJ = 25°C, VVBATT = 7.2 V, VVREG1 = VVDRx = 5 V, V VREG2 = VVDDIO = 3.3 V, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CHANNEL 7 LDO REGULATOR
Channel 7 Output Voltage VVOLDO7 5 12 V VVILDO7 = VVOLDO7 + 0.5 V
Voltage Accuracy VVOLDO7 (DEFAULT) −1.5 +1.5 % VVILDO7 = VVOLDO7 + 0.5 V, ILOAD7 = 1 mA
−2.5 +2.5 % VVILDO7 = VVOLDO7 + 0.5 V, ILOAD7 = 1 mA,
−25°C ≤ TJ ≤ +85°C
Load Regulation ∆VVOLDO7/ILOAD7 0.005 %/mA VVILDO7 = VVOLDO7 + 0.5 V, ILOAD7 = 1 mA
to 20 mA
Line Regulation ∆VVOLDO7/VVILDO7 0.007 %/V VVILDO7 = (VVOLDO7 + 0.5 V) to 25 V,
ILOAD7 = 1 mA
Dropout Voltage1 VDROP 75 mV VVOLDO7 programmed to 12 V,
IVOLDO7 = 10 mA
Current Limit
I
CL7
30
50
mA
V
VOLDO7
= 95% of nominal
Soft Start Time tSS7 4 ms SS7 = 1
COUT Discharge Switch
On Resistance
RDIS7 1 VVOLDO7 = 1 V
1 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage.
Rev. A | Page 7 of 64
ADP5080 Data Sheet
I2C INTERFACE TIMING SPECIFICATIONS
TJ = 25°C, VVBATT = 7.2 V, VVDRx = 5 V, VVREG2 = VVDDIO = 3.3 V, unless otherwise noted.
Table 5.
Parameter Min Typ Max Unit Description
fSCL 400 kHz SCL clock frequency
tHIGH 0.6 µs SCL high time
tLOW 1.3 µs SCL low time
tSU,DAT 100 ns Data setup time
tHD,DAT 0 0.9 µs Data hold time1
t
SU,STA
0.6
µs
Setup time for repeated start
tHD,STA 0.6 µs Hold time for start or repeated start
tBUF 1.3 µs Bus free time between a stop condition and a start condition
tSU,STO 0.6 µs Setup time for a stop condition
tR 20 + 0.1 × CB2 300 ns Rise time of SCL and SDA
tF 20 + 0.1 × CB2 300 ns Fall time of SCL and SDA
t
SP
0
50
ns
Pulse width of suppressed spike
CB2 400 pF Capacitive load for each bus line
1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the
SCL falling edge.
2 CB is the total capacitance of one bus line in picofarads (pF).
Timing Diagram
Figure 2. I2C Interface Timing Diagram
SS
P
Sr
S = START CONDITION
Sr = REPEATE D START CONDITION
P = STOP CONDITION
SCL
SDA
tHD,DAT
tSU,DAT tHD,STA
tSU,STA tSU,STO
tHIGH
tRtFtFtSP tR
tLOW tBUF
11639-002
Rev. A | Page 8 of 64
Data Sheet ADP5080
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
VBATT to GND −0.3 V to +18 V
VDDIO to GND
−0.3 V to +4.0 V
VISW1 to GND −0.3 V to +6.5 V
VISW2 to GND −0.3 V to +4.0 V
VREG1 to GND −0.3 V to +6.5 V
VREG2 to GND −0.3 V to +4.0 V
EN to GND −0.3 V to +18 V
EN34 to GND
−0.3 V to +6.5 V
FAULT to GND −0.3 V to +4.0 V
BSTCP to PVINCP −0.3 V to +6.5 V
BSTCP to GND −0.3 V to +23 V
C+ to PVINCP −0.3 V to (VVDR5 + 0.3 V)
C− to PGND5 −0.3 V to (VVDR5 + 0.3 V)
PVINx to PGNDx −0.3 V to +18 V
VDRx to PGNDx −0.3 V to +6.5 V
BST16, BST23, BST45 to PVINx −0.3 V to +6.5 V
FB1, FB2, FB3 to GND −0.3 V to +4.0 V
FB4, FB5, FB6 to GND −0.3 V to +6.5 V
VOUT6 to PGND6
−0.3 V to +6.5 V
SW1A, SW1B to PGND1 −2.0 V to +18 V
SW2 to PGND2 −2.0 V to +18 V
SW3 to PGND3 −2.0 V to +18 V
SW4 to PGND4 −2.0 V to +18 V
SW5 to PGND5 −2.0 V to +18 V
SW6A to PGND6
−2.0 V to +18 V
SW6B to PGND6 −0.5 V to (VVOUT6 + 2.0 V) or
+6.5 V, whichever is lower
PGNDx to GND −0.3 V to +0.3 V
VILDO7 to GND −0.3 V to +28 V
VOLDO7 to GND
−0.3 V to +18 V
FREQ to GND −0.3 V to (VVREG2 + 0.3 V)
SYNC to GND −0.3 V to +4.0 V
CLKO to GND −0.3 V to (VVREG2 + 0.3 V)
SCL to GND −0.3 V to +4.0 V
SDA to GND −0.3 V to +4.0 V
Storage Temperature Range
−65°C to +150°C
Operating Ambient
Temperature Range
−25°C to +85°C
Operating Junction
Temperature Range
−25°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for worst-case conditions; that is, a device
soldered in a circuit board for surface-mount packages. Note
that actual θJA depends on the application environment.
Table 7. Thermal Resistance
PCB Type1 θJA2 θJB2 Unit
1S0P 60.6 7.3 °C/W
2S2P 26.9 4.5 °C/W
1 PCB type conforms to JEDEC JESD51-9 standard.
2 1.25 W power dissipation with zero airflow.
ESD CAUTION
Rev. A | Page 9 of 64
ADP5080 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1A VOUT6 Output Voltage for Channel 6.
2A VOUT6 Output Voltage for Channel 6.
3A
VISW1
Input for an External Regulator Output. A 5.0 V to 5.5 V regulator connected to the VISW1 pin can take over from
LDO1 to supply the internal circuit of the ADP5080 and the VREG1 load. If this pin is not used, connect it to GND.
4A VISW2 Input for an External Regulator Output. A 3.0 V to 3.3 V regulator connected to the VISW2 pin can take over from
LDO2 to supply the internal circuit of the ADP5080 and the VREG2 load. If this pin is not used, connect it to GND.
5A PVINCP Input Power Supply for the Charge Pump.
6A C+ Flying Capacitor Terminal for the Charge Pump.
7A PGND5 Power Ground for Channel 5.
8A SW5 Switching Node for Channel 5.
9A PVIN5 Input Power Supply for Channel 5.
1B SW6B Secondary Side Boost Switching Node for Channel 6.
2B SW6B Secondary Side Boost Switching Node for Channel 6.
3B
VREG1
Output Voltage for LDO1.
4B VREG2 Output Voltage for LDO2.
5B VOLDO7 Output Voltage for Channel 7. Leave this pin open if not used.
6B C− Flying Capacitor Terminal for the Charge Pump.
7B PGND5 Power Ground for Channel 5.
8B SW5 Switching Node for Channel 5.
9B PVIN5 Input Power Supply for Channel 5.
1C PGND6 Power Ground for Channel 6.
2C PGND6 Power Ground for Channel 6.
3C VBAT T Power Supply Input for the Internal Circuits. Connect this pin to the battery.
4C EN34 Independent Enable Input for Channel 3 and Channel 4. If this pin is not used, connect it to GND.
5C
VILDO7
Input Power Supply for Channel 7. If this pin is not used, connect it to VBATT.
6C BSTCP Output Voltage for Charge Pump.
7C VDR5 Low-Side FET Driver Power Supply for Channel 5. Connect this pin to VREG1.
8C BST45 High-Side FET Driver Power Supply for Channel 4 and Channel 5.
VOUT6 VOUT6 VISW1 VISW2 PVINCP C+ SW5
VREG2 VOLDO7 C–
EN34 VILDO7 BSTCP
SW5
PVIN5
PVIN5
PVIN4BST45
SW6B SW6B VREG1
PGND6 PGND6 VBATT
SW6A SW6A VDR6 SW4
VDR34 PGND4
PGND3PGND3
SW3
PVIN3
FB6 GND SYNC
PVIN6 PVIN6 BST16 SCL GND
PVIN1 PVIN1 FB1
SW2
SW1B VDR12
PGND1
FAULT
PGND2
EN VDDIO FREQ
SW2 PVIN2 PVIN3PGND1
SW1A
FB4
SDA
GND SW3FB2
PGND5
PGND5
VDR5
CLKO
FB3
GND
BST23
FB5
TOP VIEW
(BALL SIDE DOWN)
Not t o Scal e
11639-003
1
A
B
C
D
E
F
G
2 3 4
BALLA1
CORNER
5 6 7 8
H
9
Rev. A | Page 10 of 64
Data Sheet ADP5080
Pin No. Mnemonic Description
9C PVIN4 Input Power Supply for Channel 4.
1D SW6A Primary Side Switching Node for Channel 6.
2D SW6A Primary Side Switching Node for Channel 6.
3D VDR6 Low-Side FET Driver Power Supply for Channel 6. Connect this pin to VREG1.
4D
FB6
Feedback Node for Channel 6.
5D GND Ground. All GND pins must be connected.
6D SYNC External Clock Input (CMOS Input Port). If this pin is not used, connect it to GND.
7D FB5 Feedback Node for Channel 5.
8D FB4 Feedback Node for Channel 4.
9D SW4 Switching Node for Channel 4.
1E
PVIN6
Input Power Supply for Channel 6.
2E PVIN6 Input Power Supply for Channel 6.
3E BST16 High-Side FET Driver Power Supply for Channel 1 and Channel 6.
4E SDA Data Input/Output for I2C Interface. Open-drain I/O port.
5E SCL Clock Input for I2C Interface. For start-up requirements, see the I2C Interface section.
6E GND Ground. All GND pins must be connected.
7E CLKO Clock Output (CMOS Output Port). CLKO replicates the Channel 1 switching clock. This output is not available
when the SYNC pin is driven by an external clock. If this pin is not used, leave it open.
8E VDR34 Low-Side FET Driver Power Supply for Channel 3 and Channel 4. Connect this pin to VREG1.
9E PGND4 Power Ground for Channel 4.
1F PVIN1 Input Power Supply for Channel 1.
2F
PVIN1
Input Power Supply for Channel 1.
3F FB1 Feedback Node for Channel 1.
4F EN Enable Control Input.
5F VDDIO Supply Voltage for I2C Interface. Typically, this pin is connected externally to VREG2 or to the host I/O voltage.
6F FREQ Frequency Pin for the Internal Oscillator. To select the internal clock source oscillator, connect an external
100 resistor from the FREQ pin to GND.
7F FB3 Feedback Node for Channel 3.
8F PGND3 Power Ground for Channel 3.
9F PGND3 Power Ground for Channel 3.
1G SW1A Switching Node for Channel 1.
2G SW1B Switching Node for Channel 1.
3G
VDR12
Low-Side FET Driver Power Supply for Channel 1 and Channel 2. Connect this pin to VREG1.
4G FB2 Feedback Node for Channel 2.
5G GND Ground. All GND pins must be connected.
6G FAULT Fault Status Output Pin. This open-drain output port goes low when a fault occurs. Leave open if not used.
7G GND Ground. All GND pins must be connected.
8G SW3 Switching Node for Channel 3.
9G
SW3
Switching Node for Channel 3.
1H PGND1 Power Ground for Channel 1.
2H PGND1 Power Ground for Channel 1.
3H PGND2 Power Ground for Channel 2.
4H SW2 Switching Node for Channel 2.
5H SW2 Switching Node for Channel 2.
6H PVIN2 Input Power Supply for Channel 2.
7H BST23 High-Side FET Driver Power Supply for Channel 2 and Channel 3.
8H PVIN3 Input Power Supply for Channel 3.
9H PVIN3 Input Power Supply for Channel 3.
Rev. A | Page 11 of 64
ADP5080 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Channel 1 Efficiency, VOUT = 1.1 V
Figure 5. Channel 2 Efficiency, VOUT = 1.2 V
Figure 6. Channel 3 Efficiency, VOUT = 1.8 V
Figure 7. Channel 4 Efficiency, VOUT = 3.3 V
Figure 8. Channel 5 Efficiency, VOUT = 3.3 V
Figure 9. Channel 6 Efficiency, VOUT = 5 V
0
10
20
30
40
50
EFFICIENCY (%)
60
70
80
90
100
10 100
OUTPUT CURRE NT (mA) 1000
V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
AUTO PSM
FPWM
11639-004
0
10
20
30
40
50
EFFICIENCY (%)
60
70
80
90
100
10 100
OUTPUT CURRE NT (mA) 1000
V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
11639-005
FPWM
AUTO PSM
0
10
20
30
40
50
EFFICIENCY (%)
60
70
80
90
100
10 100
OUTPUT CURRE NT (mA) 1000
V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
FPWM
11639-006
AUTO PSM
0
10
20
30
40
50
EFFICIENCY (%)
60
70
80
90
100
10 100
OUTPUT CURRE NT (mA) 1000
V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
AUTO PSM
FPWM
11639-007
0
20
10
40
EFFICIENCY (%)
60
80
30
50
70
90
100
10 100
OUT P UT CURRENT (mA) 1000
11639-008
FPWM
AUTO PSM
VIN = 4.5V
VIN = 7.2V
VIN = 12.6V
0
10
20
30
40
50
EFFICIENCY (%)
60
70
80
90
100
10 OUTPUT CURRE NT (mA)
100 1000
11639-009
AUTO PSM
FPWM V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
Rev. A | Page 12 of 64
Data Sheet ADP5080
Figure 10. Channel 1 Load Regulation
Figure 11. Channel 2 Load Regulation
Figure 12. Channel 3 Load Regulation
Figure 13. Channel 4 Load Regulation
Figure 14. Channel 5 Load Regulation
Figure 15. Channel 6 Load Regulation
1.090
1.095
1.100
1.105
1.110
0.1 110 100 1000
V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
OUTPUT VOLTAGE (V)
11639-010
OUTPUT CURRE NT (mA)
1.190
1.192
1.194
1.196
1.198
1.200
1.202
1.204
1.206
1.208
1.210
0.1 110 100
OUTPUT VOLTAGE (V)
11639-011
OUTPUT CURRE NT (mA) 1000
V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
1.790
1.795
1.800
1.805
1.810
0.1 110 100 1000
V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
OUTPUT VOLTAGE (V)
11639-012
OUTPUT CURRE NT (mA)
3.285
3.290
3.295
3.300
3.305
3.310
3.315
0.1 110 100 1000
V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
OUTPUT VOLTAGE (V)
11639-013
OUTPUT CURRE NT (mA)
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
0.1 110 100 1000
V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
OUTPUT VOLTAGE (V)
11639-014
OUTPUT CURRE NT (mA)
4.980
4.985
4.990
4.995
5.000
5.005
5.010
5.015
5.020
0.1 110 100 1000
OUTPUT VOLTAGE (V)
11639-015
OUTPUT CURRE NT (mA)
V
IN
= 4.5V
V
IN
= 7.2V
V
IN
= 12.6V
Rev. A | Page 13 of 64
ADP5080 Data Sheet
Figure 16. Channel 7 Load Regulation, VILDO7 = 16 V
Figure 17. VREG1 Load Regulation
Figure 18. VREG2 Load Regulation
Figure 19. Channel 1 Load Transient, VOUT = 1.1 V, FPWM Mode
Figure 20. Channel 1 Load Transient, VOUT = 1.1 V, Auto PSM Mode
Figure 21. Channel 2 Load Transient, VOUT = 1.2 V, FPWM Mode
11.95
11.96
11.97
11.98
11.99
12.00
12.01
12.02
12.03
12.04
12.05
0.1 110
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (mA)
11639-016
4.900
4.925
4.950
4.975
5.000
5.025
5.050
5.075
5.100
0.1 110 100
VREG 1 OUT P UT VOLTAGE (V)
OUTPUT CURRE NT (mA)
11639-017
3.200
3.225
3.250
3.275
3.300
3.325
3.350
3.375
3.400
0.1 110 100
11639-118
VREG 2 OUT P UT VOLTAGE (V)
OUTPUT CURRE NT (mA)
2
4
CH2 20.0mV
BW
20.0M 200µ s/DIV 20.0MS /s
CH4 500mA 50Ω
BW
250M
11639-018
2
4
CH2 20.0mV
BW
20.0M
CH4 300mA 50Ω
BW
20.0M
11639-127
200µs/ DIV 10. 0M S /s
2
4
CH2 20.0mV
BW
20.0M
CH4 300mA 50Ω
BW
250M
11639-019
200µs/ DIV 20. 0M S /s
Rev. A | Page 14 of 64
Data Sheet ADP5080
Figure 22. Channel 2 Load Transient, VOUT = 1.2 V, Auto PSM Mode
Figure 23. Channel 3 Load Transient, VOUT = 1.8 V, FPWM Mode
Figure 24. Channel 3 Load Transient, VOUT = 1.8 V, Auto PSM Mode
Figure 25. Channel 4 Load Transient, VOUT = 3.3 V, FPWM Mode
Figure 26. Channel 4 Load Transient, VOUT = 3.3 V, Auto PSM Mode
Figure 27. Channel 5 Load Transient, VOUT = 3.3 V, FPWM Mode
2
4
CH2 20.0mV
BW
20.0M
CH4 200mA 50Ω
BW
20.0M
1