Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
98 dB, 96 kHz, Multi-Bit Audio A/D Converter
Features
Advanced Multi-Bit ∆Σ Architecture
24-bit Conversion
Supports Audio Sample Rates Up to 108 kHz
98 dB Dynamic Range at 5 V
-92 dB THD+N at 5 V
Low-Latency Digital Filter
High-Pass Filter to Remove DC Offsets
Single +3.3 V or +5 V Power Supply
Power Consumption < 40 mW at 3.3 V
Master or Slave Operation
Slave Mode Speed Auto-Detect
Master Mode Default Settings
256x or 384x MCLK/LRCK Ratio
CS5343 Supports I²S Audio Format
CS5344 Supports Left-Justified Audio Format
General Description
The CS5343/4 is a complete analog- to-digital converter
for digital au dio sy stem s. It pe rfor ms sa mpling, analo g-
to-digital conversion, and anti-alias filtering, generating
24-bit values for both left and right inputs in serial form
at sample rates up to 108 kHz per channel.
The CS5343/4 uses a 3rd-order, multi-bit Delta-Sigma
modulator followed by a digital filter, which removes the
need for an external anti-alias filter.
The CS5343/4 also features a high-impedance sam-
pling network which eliminates costly external
components such as op-amps.
The CS5343/4 is available in a 10-p in TSSOP package
for both Commercial (-40° to +85° C) and Automotive
grades (-40° to +105° C). The CDB5343 Customer
Demonstration Board is al so available for de vice evalu-
ation and implementation suggestions. Please refer to
the “Ordering Information” on page 20 for complete
details.
The CS5343/4 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as set-top boxes, DVD-karaoke players, DVD record-
ers, A/V receivers, and automotive applications.
High-Pass
Filter
High-Pass
Filter
Low-Latency
Digita l Filte r s
VA
3.3 V to 5 V
Intern al
Reference
Voltages
High-Z
Sampling
Network
Auto-de tec t
MCLK Divider Master
Clock
Single-Ended
Analog Input
Low-Latency
Digita l Filte r s
High-Z
Sampling
Network
Single-Ended
Analog Input
SCLK
LRCK
SDOUT
FILT+
VQ
AINR
AINL
Serial Port
Slave Mode
Auto-detect
High-Pass
Filter
April '08
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TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 4
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5
RECOMMENDED OPERATING CONDITIONS ..................................................................................... 5
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 5
ANALOG CHARACTERISTICS - COMMERCIAL GRADE (-CZZ) ......................................................... 6
ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (-DZZ) ......................................................... 7
DIGITAL FILTER CHARACTERISTICS ................................................................................................8
DC ELECTRICAL CHARA CTERISTIC S .... ... .... ... ... ... .... ... ... ... .... ................................................... ........ 8
DIGITAL CHARACTERISTICS ............................................................................................................... 9
SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE ................................................................... 10
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12
4. APPLICATIONS ................................................................................................................................... 13
4.1 Operation as Clock Master or Slave ............................................................................................... 13
4.1.1 Slave Mode Operat ion . ... ................ .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ... ...................... 13
4.1.2 Master Mode Operation ......................................................................................................... 14
4.1.2.1 Master Mode Speed Selection ................................................................................... 14
4.1.3 Master Clock ......... ................ ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ................ ... ................ 14
4.2 Serial Audio Interface ..................................................................................................................... 15
4.3 Digital Interface ............................................................................................................................... 15
4.4 Analog Connections ....................................................................................................................... 15
4.4.1 Component Values ......................... .... ................................ ... ... .... ... ... ... .... ... ... ...................... 16
4.5 Grounding and Power Supply Decoupling ................ ... ................... ... .................... ... ................... ...16
4.6 Synchronization of Multiple Devices ............................................................................................... 17
5. FILTER PLOTS - ALL SPEED MODES ............................................................................................... 17
6. PARAMETER DEFINITIONS ................................................................................................................ 18
7. PACKAGE DIMENSIONS .................................................................................................................... 19
THERMAL CHARACTERISTICS .......................................................................................................... 19
8. ORDERING INFORMATION ................................................................................................................ 20
9. REVISION HISTORY ............................................................................................................................ 21
LIST OF FIGURES
Figure 1. CS5343 I²S Serial Audio Interface.............................................................................................. 11
Figure 2. CS5344 Left-Justified Serial Audio Interface.... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 11
Figure 3. Typical Connection Diagram................ .... ... ... ... .... ... ................... ... .................... ... ...................... 12
Figure 4. CS5343 I²S Serial Audio Interface.............................................................................................. 15
Figure 5. CS5344 Left-Justified Serial Audio Interface.... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 15
Figure 6. CS5343/4 Analog Input Network................................................................................................. 15
Figure 7. CS5343/4 Example Analog Input Network.................................................................................. 16
Figure 8. Stopband Rejection..................................................................................................................... 17
Figure 9. Transition Band........................................................................................................................... 17
Figure 10. Transition Band (Detail)............................................................................................................ 17
Figure 11. Passband Ripple.................... ... ................................................... ............................................. 17
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LIST OF TABLES
Table 1. Master/Slave Mode Selection ...................................................................................................... 13
Table 2. Speed Modes and the Associated Sample Rates (Fs) in Slave Mode...... ... .................... ... ......... 13
Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode....... .................... ... ......... 14
Table 4. Speed Mode Selection in Master Mode....................................................................................... 14
Table 5. Common MCLK Frequencies in Master and Slave Modes.......................................................... 14
Table 6. Analog Input Design Parameters................................................................................................. 16
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1. PIN DESCRIPTIONS
Pin Name Pin # Pin Description
SDOUT 1 Serial Audio Data Output (Output) - Output for two’s complement serial audio data. Also selects Master
or Slave Mode; See Section 4.1 on page 13 for details.
SCLK 2 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK 3 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
FILT+ 5 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
AINL
AINR 6
8Analog Input (Input) - The full-scale analog inp ut level is specified in the Analog Characteristics specifi-
cation table.
VQ 7 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
GND 9 Ground (Input) - Ground reference. Must be connected to analog ground.
VA 10 Power (Input) - Positive power supply for the digital and analog sections.
1
2
3
4
56
7
8
9
10
SDOUT
SCLK
LRCK
MCLK
FILT+
VA
GND
AINR
VQ
AINL
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2. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = 0 V, all voltages with respect to GND.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V, all voltages with respect to GND. (Note 1)
Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not
guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
Parameter Symbol Min Typ Max Unit
Power Supplies VA 3.1
4.75 3.3
5.0 3.5
5.25 V
V
Ambient Operating Temperature Commercial (-CZZ)
Automotive (-DZZ) TAC
TAD
-40
-40 -
-85
105 °C
°C
Parameter Symbol Min Max Unit
DC Power Supplies VA -0.3 +6.0 V
Input Current (Note 2) Iin -10 +10 mA
Input Voltage (Note 3) VIN -0.7 VA+0.7 V
Ambient Operating Temperature (Powe r Applied) TA-50 +115 °C
Storage Tempe ra tu re Tstg -65 +150 °C
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ANALOG CHARACTERISTICS - COMMERCIAL GRADE (-CZZ)
Test conditions (unless otherwise specified): TA = 25 ° C; Input test signal is a 997 Hz sine wave through recom-
mended inputs as seen in Figure 6 on page 15; source impedance less than or equal to 2.5 kΩ; valid with FILT+
and VQ components as shown in Figure 3 on page 12; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48 kHz
or 96 kH z.
Notes: 4. Referred to the typical full-scale input voltage
Dynamic Performance for Commercial Grade VA = 3.3 V VA = 5.0 V
Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted 91
88 94
91 -
-95
92 98
95 -
-dB
dB
Total Harmonic Distortion + Noise (Note 4)
-1 dB
-20 dB
-60 dB
THD+N -
-
-
-89
-71
-31
-86
-
-
-
-
-
-92
-75
-35
-89
-
-
dB
dB
dB
Dynamic Performance for Commercial Grade VA = 3.3 V and VA = 5.0 V
Min Typ Max Unit
Interchannel Isolation - 90 - dB
DC Accuracy
Interchannel Gain Mismatch - - 0.1 dB
Gain Error -3 - +3 %
Gain Drift - ±100 - ppm/°C
Analog Input Characteristics
Full-scale Input Voltage VA = 3.3 V nom 0.560*VA 0.568*VA 0.575*VA Vpp
Full-scale Input Voltage VA = 5 V nom 0.552*VA 0.559*VA 0.567*VA Vpp
Input Impedance - 7.5 - MΩ
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ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (-DZZ)
Test conditions (unless otherwise specified): TA = -40° C to 85° C; Input test signal is a 997 Hz sine wave through
recommended inputs as seen in Figure 6 on page 15; source impedance less than or equal to 2.5 kΩ; valid with
FILT+ and VQ components as shown in Figure 3 on page 12; measurement bandwidth is 10 Hz to 20 kHz;
Fs = 48 kHz or 96 kHz.
Notes: 5. Referred to the typical full-scale input voltage
Dynamic Performance for Automotive Grade VA = 3.1 to 3.5 V VA = 4.75 to 5.25 V
Symbol Min Typ Max Min Typ Max Unit
Dynamic Range A-weighted
unweighted 86
83 94
91 -
-90
87 98
95 -
-dB
dB
Total Harmonic Distortion + Noise (Note 5)
-1 dB
-20 dB
-60 dB
THD+N -
-
-
-88
-71
-31
-76
-
-
-
-
-
-91
-75
-35
-84
-
-
dB
dB
dB
Dynamic Performance for Automotive Grade VA = 3.1 V to 3.5 V and VA = 4.75 V to 5.25 V
Min Typ Max Unit
Interchannel Isolation - 90 - dB
DC Accuracy
Interchannel Gain Mismatch - - 0.1 dB
Gain Error -3 - +3 %
Gain Drift - ±100 - ppm/°C
Analog Input Characteristics
Full-scale Input Voltage VA = 3.1 V to 3.5 V 0.523*VA 0.567*VA 0.612*VA Vpp
Full-scale Input Vo ltage VA = 4.75 V to 5.25 V 0.543*VA 0.560*VA 0.573*VA Vpp
Input Impedance - 7.5 - MΩ
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DIGITAL FILTER CHARACTERISTICS
Notes: 6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
DC ELECTRICAL CHARACTERISTICS
GND = 0 V, all voltages with respect to 0 V. MCLK=12.288 MHz; Master Mode.
Notes: 7. Device enters power-down mode when MCLK is held static.
8. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
Parameter Symbol Min Typ Max Unit
All Speed Modes
Passband (-0.1 dB) 0 - 0.489 Fs
Passband Ripple -0.031 - 0.031 dB
Stopband 0.560 - - Fs
Stopband Attenuation 60 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd - 12/Fs - s
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 6) -1
20 -
-Hz
Hz
Phase Deviation @ 20 Hz (Note 6) -10-Deg
Passband Ripple - - 0 dB
Parameter Symbol
VA = 3.3 V VA = 5.0 V
Min Typ Max Min Typ Max Unit
Power Supply Current (Normal Operation) IA- 11 15 - 12 17 mA
Power Supply Current (Power-Down Mode) (Note 7) IA-10--40 - uA
Power Consumption (Normal Operation)
(Power-Down Mode) (Note 7) -
--
-36
<1 50
--
-60
<1 85
-mW
mW
Parameter Symbol Min Typ Max Unit
Power Supply Rejection Ratio (1 kHz) (Note 8) PSRR - 65 - dB
VQ Nominal Voltage
Output Impedance -
-0.44xVA
25 -
-V
kΩ
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
VA
220
2.5
-
-
-
V
kΩ
uA
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DIGITAL CHARACTERISTICS
Parameter Symbol Min Typ Max Units
High-Level Input Voltage (% of VA) VIH 60 - - %
Low-Level Input Voltage (% of VA) VIL --30%
High-Level Output Voltage at Io = 500 µA(% of VA)
VOH 70 - - %
Low-Level Output Voltage at Io =500 µA(% of VA)
VOL --15%
Input Leakage Current Iin -10 - 10 µA
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SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE
Logic “0” = GND = 0 V; Logic “1” = VA, CL = 20 pF.
Parameter Symbol Min Typ Max Unit
Master Mode
MCLK Period (Double-Speed, 384x Mode) tclkw 24 - 30 ns
(Double-Speed, 192x Mode) 48 - 60 ns
(Double-Speed, 256x Mode) 36 - 45 ns
(Double-Speed, 128x Mode) 72 - 90 ns
(Single-Speed, 768x Mode) 24 - 30 ns
(Single-Speed, 384x Mode) 48 - 60 ns
(Single-Speed, 512x Mode) 36 - 45 ns
(Single-Speed, 256x Mode) 72 - 90 ns
MCLK Duty Cycle 40 50 60 %
Output Sample Rate (Single-Speed)
(Double-Speed) Fs 43
86 -
-54
108 kHz
kHz
LRCK Duty Cycle - 50 - %
SCLK Duty Cycle - 50 - %
SDOUT valid before SCLK rising tstp 10 - - ns
SDOUT valid after SCLK rising thld 40 - - ns
SCLK falling to LRCK edge tslrd -20 - 20 ns
Slave Mode
MCLK Period (Double-Speed, 384x Mode) tclkw 24 - 30 ns
(Double-Speed, 192x Mode) 48 - 60 ns
(Double-Speed, 256x Mode) 36 - 45 ns
(Double-Speed, 128x Mode) 72 - 90 ns
(Single-Speed, 768x Mode) 24 - 325 ns
(Single-Speed, 384x Mode) 48 - 651 ns
(Single-Speed, 512x Mode) 36 - 488 ns
(Single-Speed, 256x Mode) 72 - 976 ns
MCLK Duty Cycle 40 50 60 %
Input Sample Rate (Single-Speed)
(Double-Speed) Fs 4
86 -
-54
108 kHz
kHz
LRCK Duty Cycle 405060%
SCLK Period tsclkw --ns
SCLK Duty Cycle 455055%
SDOUT valid before SCLK rising tstp 10 - - ns
SDOUT valid after SCLK rising thld 40 - - ns
SCLK falling to LRCK edge tslrd -20 - 20 ns
1
64 Fs×
------------------
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3. TYPICAL CONNECTION DIAGRAM
Figure 3. Typical Connection Diagram
AINL
AINR
6
8
1
SDOUT
9GND
7VQ
VA
10
5FILT+
2
SCLK
3
LRCK
4
MCLK
Audio
Processor/
System
Clocks
VA or
GND VA
3.3 V to 5 V
CS5343/4
10 kΩ1
10 kΩ2
Analog Input
Conditioning
10 kΩ2
1 µF 0.1 µF
1 µF 0.1 µF
1 µF0.1 µF
See Figure 6 on
page 15 1 Pull-up to VA for Master Mode
Pull-down to GND for Slave Mode
2 Optional pull-up resistor for config-
uring clocks in Master Mode as
described in the “Master Mode Speed
Selection” section on page 14
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4. APPLICATIONS
4.1 Operation as Clock Master or Slave
The CS5343/4 supports operation as either a clock master or slave. As a clock master, the left/right and
serial clocks are synchronously generated on-chip and output on the LRCK and SCLK pins , respectively.
As a clock slave, the LRCK and SCLK pins are always inputs and require e xternal generation of the left/right
and serial clocks. The selection of clock master or slave is made via a 10 kΩ pull-up resistor from SDOUT
to VA for Master Mode selecti on or via a 10 kΩ pull-down resistor from SDOUT to GND for Slave Mode se-
lection, as shown in Table 1.
4.1.1 Slave Mode Operation
A unique feature of the CS5343/4 is the automatic selection of either Single- or Double-Speed Mode when
acting as a clock slave. The auto-mode selection feature supports all standard audio sample rates from
4 to 108 kHz. Please refer to Table 2 for supported sample rate ranges in Slave Mode.
Table 2. Speed Modes and the Associated Sample Rates (Fs) in Slave Mode
Mode Selection
Master Mode 10 kΩ pull-up resistor from SDOUT to VA
Slave Mode 10 kΩ pull-down resistor from SDOUT to GND
Table 1. Master/Slave Mode Selection
Speed Mode MCLK/LRCK
Ratio SCLK/LRCK
Ratio Input Sample Rate Range (kHz)
Single-Speed Mode
256x 64 4 - 54
512x 64 4 - 54
384x 48, 64 4 - 54
768x 48, 64 4 - 54
Double-Speed Mode
128x 64 86 - 108
256x 64 86 - 108
192x 48, 64 86 - 108
384x 48, 64 86 - 108
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4.1.2 Master Mode Operation
As clock Master, the CS5343/4 generates LRCK and SCLK synchronously on-chip. Table 3 shows the
available sample rates and asso ciated clock ratios in Master Mode.
4.1.2.1 Master Mode Speed Selection
During power-up in Master Mode, the LRCK and SCLK pins are inputs to configure speed mode an d the
output clock ratio. The LRCK pin is pulled low intern ally to select Single-Speed M ode by default, but Dou-
ble-Speed Mode is accessed with a 10 kΩ pull-up resistor from LRCK to VA as shown in Table 4. Simi-
larly, the SCLK pin is internally pulled-low by default to select a 256x/512x MCLK/LRCK ratio, but a
MCLK/LRCK ratio of 348x/768x is accessed with a 10 kΩ pull-up resistor from SCLK to VA as shown in
Table 4. Following the power-up routine, the LRCK and SCLK pins become clock outputs.
4.1.3 Master Clock
The CS5343/4 requir es a Master clock (MCLK) which run s the internal sampling circuits and digital filters.
There is an internal automatic MCLK divider which is activated based on the input frequency of MCLK.
This divider selection allows the high and low MCLK speeds in a given speed mode (i.e. 256x and 512x
in SSM). Table 4 lists some common audio output sample rates and the required MCLK frequency.
Speed Mode MCLK/LRCK
Ratio SCLK/LRCK
Ratio Input Sample Rate Range (kHz)
Single-Speed Mode
256x 64 43 - 54
512x 64 43 - 54
384x 64 43 - 54
768x 64 43 - 54
Double-Speed Mode
128x 64 86 - 108
256x 64 86 - 108
192x 64 86 - 108
384x 64 86 - 108
Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode
Pin Resistor Option Clock Configuration
LRCK Internal Pull-Down to GND (100 kΩ) Single-Speed Mode (default)
External Pull-Up to VA (10 kΩ) Double-Speed Mode
SCLK Internal Pull-Down to GND (100 kΩ) 128x/256x/512x MCLK/LRCK (default)
External Pull-Up to VA (10 kΩ) 192x/384x/768x MCLK/LRCK
Table 4. Speed Mode Selection in Master Mode
Master and Slave Mode
Sample Rate (kHz) Speed Mode MCLK(MHz) MCLK (MHz)
256x 512x 384x 768x
32 (*Slave Mode Only) SSM *8.912 *16.384 *12.288 *24.576
44.1 SSM 11.289 22.579 16.934 33.868
48 SSM 12.288 24.576 18.432 36.864
Sample Rate (kHz) Speed Mode MCLK(MHz) MCLK (MHz)
128x 256x 192x 384x
88.2 DSM 11.289 22.579 16.934 33.868
96 DSM 12.288 24.576 18.432 36.864
Table 5. Common MCLK Frequencie s in Master and Slave Modes
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4.2 Serial Audio Interface
The CS5343 output is serial data in I²S audio format and the CS5344 output is serial data in Left-Justified
audio format. Figures 4 and 5 show th e I²S and Left-Justified data relative to SCLK and LRCK. Additionally,
Figures 1 and 2 display more information on the required timing for the serial audio interface format. For an
overview of serial audio interf ace formats, please refer to Cirrus Application Note AN282.
4.3 Digital Interface
VA supplies power to both the analog an d digital sections of the ADC, and also po wers the serial port. Con-
sequently, the digital interface logic level mu st equal VA to within the limits specified u nder “Digital Charac-
teristics” on page 9.
4.4 Analog Connections
The analog modulator samples the input signal at half of the internal master clock rate, or 6.144 MHz when
MCLK = 12.288 MHz. The digital filter will reject signals within the stopband of the filter. However, there is
no rejection for input signals which are multiples of the input sampling frequency (n ×6.144 MHz), where
n=0,1,2,... Refer to Figure 6 which shows the recommended topology of the analog input network. The ex-
ternal shunt capacitor and internal input impedance form a single-pole RC filter to provide the appropriate
filtering of noise at the modulator sampling frequency. Additionally, the 180 pF capa citor acts as a char ge
source for the internal sampling circuits. Capacitors of NPO or other high-quality dielectric will produce the
best results while capacitors with a large voltage coefficient (such as general-purpose ceramics) can de-
grade signal linearity.
Figure 4. CS5343 I²S Serial Audio Interfa ce
SDATA 23 22 8 723 22
SCLK
LRCK
23 2265432108765432109 9
Left Channel Right Channel
Figure 5. CS5344 Left-Justified Serial Audio Interface
SDATA 23 22 7 623 22
SCLK
LRCK
23 2254321087654321089 9
Left Channel Right Channel
Figure 6. CS5343/4 Analog Input Network
CS5343/4
AIN
Input R1
R2
1 µF
180pF
C0G
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4.4.1 Component Values
Three parame ters determ ine the values of re sistors R1 and R2 as shown in Figure 6: source impe dance,
attenuation, and input impedance. Table 6 shows the design equati on use d to de te rm in e th es e valu e s.
•Source Impedance: Source impedance is defined as the impedance as seen from the ADC looking
back into the signal network. The ADC achieves optimal THD+N performance with a source imped-
ance less than or equal to 2.5 kΩ.
•Attenuation: The required attenuation factor depends on the magnitude of the input signal. The full-
scale input vo ltage is specified under “A nalog Characteristics - Com mercial Grade (-CZ Z)” on page 6.
The user should select values for R1 and R2 such that the magnitude of the inco ming signal multiplied
by the attenuation factor is less than or equal to the full-scale input voltage of the device.
•Input Impedance: Inp ut impedance is the impeda nce from the signa l source to the ADC analog inpu t
pins, including the ADC. Because the ADC’s input impedance (see the “Analog Characteristics - Com-
mercial Grade (-CZZ)” table on page 6) is several orders of magnitude larg er than the resistor value s
typically used for the input attenuator, its contributi on can b e neglected whe n calculating the input im-
pedance. Table 6 shows the input parameters and the associated design equations for the input at-
tenuator.
Figure 7 illustrates an example configuration using two 4.99 kΩ resistors in place of R1 and R2. Based on
the discussion above, this circuit provides an optimal interface for both the ADC and the signal source.
First, consumer equipment frequently requires an input im pedance of 10 kΩ, which the 4.99 kΩ resistors
provide. Second, this circuit will attenuate a typical line level voltage, 2 Vrms, to the full-scale input of the
ADC, 1 Vrms when VA = 5 V. Finally, at 2.5 kΩ, the source impedance optimizes analog performance of
the ADC.
4.5 Grounding and Power Supply Decoupling
As with any high-resolu tion converter, designing with the CS5343/4 re quires careful attention to power sup-
ply and grounding arrangements if its potential performance is to be realized . Figure 3 shows the recom-
mended power arrangements, with VA connected to a clean supply. Decoupling capacitors should be as
near to the ADC as possible, with the low value ceramic ca pacitor b eing the ne arest. All sign als, espe cially
clocks, should be kept away from the FILT+ an d VQ pins in order to a void unwanted coupling into the mod-
ulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize
the electrical path from FILT+ to GND. The CDB5343 evaluation board demonstrates the optimum layout
and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS
inputs.
Source Impedance
Attenuation Factor
Input Impedance
Table 6. Analog Input Design Parameters
R1R2×()
R1R2+
-------------------------
R2()
R1R2+()
-------------------------
R1R2+()
Figure 7. CS5343/4 Example Analog Input Network
CS5343/4
AIN
Input 4.99 kΩ
4.99 kΩ
1 µF
180pF
C0G
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4.6 Synchronization of Multiple Devices
In systems where multiple ADCs ar e required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, th e MCLK, SCLK, and LRCK signals must be the same for all of the CS5343
and CS5344 devices in the system.
5. FILTER PLOTS - ALL SPEED MODES
Figure 8. Stopband Rej ection Figure 9. Transition Band
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
Figure 10. Transition Band (Detail) Figure 11. Passband Ripple
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Amplitude (dB)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.46 0.47 0.48 0.49 0.50 0.51 0.52
Frequency (normalized to Fs)
Amplitude (dB)
18 DS687F3
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6. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Ra nge is a signal- to-noise ratio measurement over the specified bandwidth made with
a -60 d BFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measure-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms va lue of the signa l to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of th e am p litu de r es po ns e varia tio n f ro m 1 0 Hz to 20 kHz relative to the am p litu de r es po ns e at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog input for a full- scale digital output.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
DS687F3 19
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7. PACKAGE DIMENSIONS
Notes: 1. Referenc e do cu m ent: JEDEC MO-187
2. D does not include mold flash or pro trusions, which is 0.15 mm max. per side.
3. E1 does not include inter-lead flash or protrusions, which is 0.15 mm max per side.
4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
5. Exceptions to JEDEC dimension.
THERMAL CHARACTERISTICS
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A----0.0433----1.10
A1 0 -- 0.0059 0 -- 0.15
A2 0.0295 -- 0.0374 0.75 -- 0.95
b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5
c 0.0031 -- 0.0091 0.08 -- 0.23
D -- 0.1181 BSC -- -- 3.00 BSC -- 2
E -- 0.1929 BSC -- -- 4.90 BSC --
E1 -- 0.1181 BSC -- -- 3.00 BSC -- 3
e -- 0.0197 BSC -- -- 0.50 BSC --
L 0.0157 0.0236 0.0315 0.40 0.60 0.80
L1 -- 0.0374 REF -- -- 0.95 REF --
µ0°--8°0°--8°
Controlling Dimension is Millimeters
Parameter Symbol Min Typ Max Unit
Allowable Junction Temperature TJ- - 135 °C
Junction to Ambient Thermal Impedance (4-layer PCB)
(2-layer PCB) θJA-4
θJA-2
-
-100
170 -
-°C/W
°C/W
10LD TSSOP (3 mm BODY) PACKAGE DRAWING (Note 1)
E
N
123
ebA1
A2 A
D
SEATING
PLANE
E11
L
SIDE VIEW
END VIEW
TOP VIEW
∝
L1
c
20 DS687F3
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8. ORDERING INFORMATION
Product Description Package Pb-Free Gr ade Tem p Range Container Order #
CS5343 98 dB, Multi-Bit Aud io
A/D Converter,
I²S Audio Format 10-TSSOP Yes Commercial -40° to +85° C Rail CS5343-CZZ
Tape & Reel CS5343-CZZR
CS5343 98 dB, Multi-Bit Aud io
A/D Converter,
I²S Audio Format 10-TSSOP Yes Automotive -40° to +105° C Rail CS5343-DZZ
Tape & Reel CS5343-DZZR
CS5344 98 dB, Multi-Bit Aud io
A/D Converter,
Left-Justified Audio Format 10-TSSOP Yes Commercial -40° to +85° C Rail CS5344-CZZ
Tape & Reel CS5344-CZZR
CS5344 98 dB, Multi-Bit Aud io
A/D Converter,
Left-Justified Audio Format 10-TSSOP Yes Automotive -40° to +105° C Rail CS5344-DZZ
Tape & Reel CS5344-DZZR
CDB5343 CS5343 Evaluation Board - No - - - CDB5343
DS687F3 21
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9. REVISION HISTORY
Release Changes
F1
Updated “Recommended Operating Conditions” on page 5
Updated specifications and limits for “Analog Characteristics - Commercial Grade (-CZZ)” on page 6
Updated specifications and limits for “Analog Chara c teristics - Automotive Grade (-DZZ)” on page 7
Corrected “Power Supply Current (Normal Operation)” on page 8
Increased specificati on for Slave-Mode “SDOUT valid after SCLK rising” on page 10
Corrected Section 4.1.2.1 on page 14
Updated Section 4.1.3 on page 14
F2
Removed Fs < 43 kHz from master mode operation:
-Updated master mode timing specifications in the “System Clocking and Serial Audio Interface” on page 10
-Updated Input Sample Rate Range in Table 3 on page 14
-Added note for “slave mode only” for Fs = 32 kHz in Table 5 on page 14.
F3 Updated Passband Ripple, Stopband Attenuation and Total Group Delay specs in “Digital Filter Characteristics”
on page 8.
22 DS687F3
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Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
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to change wi thout notice and is provi ded “AS I S” withou t warrant y of any kind (ex press or implied) . Customer s are ad vised to o btain the latest version of relevant
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supplied at the time of order acknow ledgment, inclu ding those pertainin g to warranty, indemnific ation, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or othe r rights o f third
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does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APP LICATIONS”). CIRRUS P RODUCTS AR E NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLAN TED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
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