LTC3418EUHF#TR - Linear Technology Corporation

LTC3418

3418fa

8A, 4MHz, Monolithic

Synchronous Step-Down

Regulator

■

High Efficiency: Up to 95%

■

8A Output Current

■

2.25V to 5.5V Input Voltage Range

■

Low R

DS(ON)

Internal Switch: 35mΩ

■

Tracking Input to Provide Easy Supply Sequencing

■

Programmable Frequency: 300kHz to 4MHz

■

0.8V ±1% Reference Allows Low Output Voltage

■

Quiescent Current: 380µA

■

Selectable Forced Continuous/Burst Mode

Operation

with Adjustable Burst Clamp

■

Synchronizable Switching Frequency

■

Low Dropout Operation: 100% Duty Cycle

■

Power Good Output Voltage Monitor

■

Overtemperature Protected

■

38-Lead Low Profile (0.75mm) Thermally Enhanced

QFN (5mm × 7mm) Package

■

Microprocessor, DSP and Memory Supplies

■

Distributed 2.5V, 3.3V and 5V Power Systems

■

Automotive Applications

■

Point of Load Regulation

■

Notebook Computers

DESCRIPTIO

FEATURES

APPLICATIO S

TYPICAL APPLICATIO

2.5V/8A Step-Down Regulator

The LTC

3418 is a high efficiency, monolithic synchro-

nous step-down DC/DC converter utilizing a constant

frequency, current mode architecture. It operates from an

input voltage range of 2.25V to 5.5V and provides a

regulated output voltage from 0.8V to 5V while delivering

up to 8A of output current. The internal synchronous

power switch increases efficiency and eliminates the need

for an external Schottky diode. Switching frequency is set

by an external resistor or can be synchronized to an

external clock. OPTI-LOOP

compensation allows the

transient response to be optimized over a wide range of

loads and output capacitors.

The LTC3418 can be configured for either Burst Mode

operation or forced continuous operation. Forced continu-

ous operation reduces noise and RF interference while

Burst Mode operation provides high efficiency by reduc-

ing gate charge losses at light loads. In Burst Mode

operation, external control of the burst clamp level allows

the output voltage ripple to be adjusted according to the

requirements of the application. A tracking input in the

LTC3418 allows for proper sequencing with respect to

another power supply.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131,

6724174.

Efficiency and Power Loss vs Load Current

SVIN TRACK

CIN

100µF

0.2µH

LTC3418

RUN/SS

ITH

PGOOD

PGND

SGND

SYNC/MODE VFB

332Ω

PVIN

820pF

3418 TA01a

1000pF

COUT

100µF

×2

VOUT

2.5V

4.32k

1.69k

30.1k

2.2M

VIN

2.8V TO 5.5V

4.99k

LOAD CURRENT (A)

0.01

EFFICIENCY (%)

POWER LOSS (mW)

100

0.1 1 10

3418 TA01b

1000

100000

100

10000

EFFICIENCY

POWER LOSS

VIN = 3.3V

VOUT = 2.5V

LTC3418

3418fa

ORDER PART NUMBER

(Note 1)

Input Supply Voltage .................................. –0.3V to 6V

, RUN/SS, V

Voltages ......................... – 0.3V to V

SYNC/MODE Voltages ............................... – 0.3V to V

TRACK Voltage .......................................... –0.3V to V

SW Voltage .................................. –0.3V to (V

+ 0.3V)

Operating Ambient Temperature Range

(Note 2) .............................................. – 40°C to 85°C

Junction Temperature (Note 5)............................. 125°C

Storage Temperature Range ................. –65°C to 125°C

LTC3418EUHF

JMAX

= 125°C, θ

= 34°C/W, θ

= 1°C/W

EXPOSED PAD (PIN 39) IS PGND AND MUST BE SOLDERED TO PCB

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

Consult LTC Marketing for parts specified with wider operating temperature ranges.

13 14 15 16

TOP VIEW

UHF PACKAGE

38-LEAD (7mm × 5mm) PLASTIC QFN

17 18 19

38 37 36 35 34 33 32

1SW

PVIN

PGOOD

RUN/SS

SGND

PVIN

SYNC/MODE

ITH

VFB

SVIN

PVIN

PGND

TRACK

PGND

VREF

PGND

UH PART MARKING 3418

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Voltage Range 2.25 5.5 V

Regulated Feedback Voltage 0°C ≤ T

≤ 85°C 0.792 0.800 0.808 V

(Note 3) ●0.784 0.800 0.816 V

Feedback Input Current 100 200 nA

∆V

Reference Voltage Line Regulation V

= 2.5V to 5.5V (Note 3) 0.04 0.2 %/V

LOADREG

Output Voltage Load Regulation Measured in Servo Loop, V

ITH

= 0.36V ● 0.02 0.2 %

Measured in Servo Loop, V

ITH

= 0.84V ●–0.02 –0.2 %

TRACK

Tracking Voltage Offset V

TRACK

= 0.4V 15 mV

Tracking Voltage Range 0 0.8 V

TRACK

TRACK Input Current 100 200 nA

∆V

PGOOD

Power Good Range ±7.5 ±9%

PGOOD

Power Good Resistance 100 150 Ω

The ● indicates specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V. (Note 2)

ELECTRICAL CHARACTERISTICS

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

LTC3418

3418fa

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input DC Bias Current (Note 4)

Active Current V

= 0.7V, V

ITH

= 1V 380 450 µA

Shutdown V

RUN

= 0V 0.03 1.5 µA

OSC

Switching Frequency R

OSC

= 69.8kΩ0.88 1 1.12 MHz

Switching Frequency Range (Note 6) 0.3 4 MHz

SYNC

SYNC Capture Range (Note 6) 0.3 4 MHz

PFET

DS(ON)

of P-Channel FET I

= 600mA 35 50 mΩ

NFET

DS(ON)

of N-Channel FET I

= –600mA 25 35 mΩ

LIMIT

Peak Current Limit 12 17 A

UVLO

Undervoltage Lockout Threshold 1.75 2 2.25 V

REF

Reference Output 1.219 1.250 1.281 V

LSW

SW Leakage Current V

RUN

= 0V, V

= 5.5V 0.1 1 µA

RUN

RUN Threshold 0.5 0.65 0.8 V

The ● indicates specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V. (Note 2)

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: The LTC3418 is guaranteed to meet performance specifications

from 0°C to 85°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

Note 3: The LTC3418 is tested in a feedback loop that adjusts V

achieve a specified error amplifier output voltage (I

Note 4: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

Note 5: T

is calculated from the ambient temperature T

and power

dissipation P

as follows:

LTC3418: T

= T

+ (P

)(34°C/W)

Note 6: This parameter is guaranteed by design and characterization.

TYPICAL PERFOR A CE CHARACTERISTICS

Switch On-Resistance

vs Input Voltage

INPUT VOLTAGE (V)

2.25

ON-RESISTANCE (mΩ)

4.25

3418 G01

3.25

2.75 4.75

3.75 5.25

PFET

NFET

On-Resistance vs Temperature

TEMPERATURE (°C)

–40

ON-RESISTANCE (mΩ)

040 60

3418 G02

PFET

NFET

–20 20 80 100 120

VIN = 3.3V

TEMPERATURE (°C)

–40 –20

REFERENCE VOLTAGE (V)

0.7980

0.7990

120

3418 G07

0.7970

0.7960 020

40 60 10080

0.8000

0.7975

0.7985

0.7965

0.7995

= 3.3V

Internal Reference Voltage

vs Temperature

TA = 25°C unless otherwise noted.

LTC3418

3418fa

TYPICAL PERFOR A CE CHARACTERISTICS

Quiescent Current

vs Input Voltage

INPUT VOLTAGE (V)

2.5

QUIESCENT CURRENT (µA)

100

200

300

33.5 4 4.5

3418 G04

400

500

150

250

350

450

5.5

INPUT VOLTAGE (V)

2.25

LEAKAGE CURRENT (nA)

0.5

1.5

2.0

2.5

4.25

5.0

4.5

3418 G03

1.0

3.25

2.75 4.75

3.75 5.25

3.0

PFET

NFET

3.5

4.0

Switch Leakage vs Input Voltage

Frequency vs Input Voltage

INPUT VOLTAGE (V)

2.25

900

FREQUENCY (kHz)

920

960

980

1000

4.25

1100

1080

3418 G05

940

3.25

2.75 4.75

3.75 5.25

1020

1040

1060

TEMPERATURE (°C)

–40

900

FREQUENCY (kHz)

920

960

980

1000

1100

1040

040 60

3418 G06

940

1060

1080

1020

–20 20 80 100 120

VIN = 3.3V

Frequency vs Temperature

Frequency vs ROSC

OSC

(kΩ)

FREQUENCY (kHz)

500

1500

2000

2500

170

4500

3418 G08

1000

50 210

130 250

3000

3500

4000

= 3.3V

Efficiency and Power Loss

vs Load Current

Efficiency vs Load Current

LOAD CURRENT (A)

0.01

EFFICIENCY (%)

0.1 1 10

3418 G10

100 Burst Mode OPERATION

FORCED CONTINUOUS

= 3.3V

OUT

= 2.5V

Efficiency vs Load Current

LOAD CURRENT (A)

0.01

EFFICIENCY (%)

0.1 1 10

3418 G11

100

3.3V

FORCED CONTINUOUS

VOUT = 2.5V

Efficiency vs Load Current

LOAD CURRENT (A)

0.01

EFFICIENCY (%)

0.1 1 10

3418 G12

100 3.3V

Burst Mode OPERATION

OUT

= 2.5V

LOAD CURRENT (A)

0.01

EFFICIENCY (%)

POWER LOSS (mW)

100

0.1 1 10

3418 TA01b

1000

100000

100

10000

EFFICIENCY

POWER LOSS

VIN = 3.3V

VOUT = 2.5V

TA = 25°C unless otherwise noted.

LTC3418

3418fa

Load Regulation

Peak Inductor Current

vs Burst Clamp Voltage

VBCLAMP (V)

PEAK INDUCTOR CURRENT (A)

0.2 0.4 0.6 0.8

3418 G13

0.1 0.3 0.5 0.7

3.3V

LOAD CURRENT (A)

–0.30

∆V

OUT

(%)

–0.25

–0.20

–0.15

–0.10

24 68

3418 G14

–0.05

13 57

= 3.3V

OUT

= 1.8V

f = 1MHz

Load Step Transient

OUTPUT

VOLTAGE

100mV/DIV

INDUCTOR

CURRENT

5A/DIV

20µs/DIVVIN = 3.3V

VOUT = 2.5V

LOAD STEP: 800mA TO 8A

3418 G15

Load Step Transient

OUTPUT

VOLTAGE

100mV/DIV

INDUCTOR

CURRENT

5A/DIV

40µs/DIVV

= 3.3V

OUT

= 2.5V

LOAD STEP: 3A TO 8A

3418 G16

Burst Mode Operation Start-Up Transient

OUTPUT

VOLTAGE

100mV/DIV

INDUCTOR

CURRENT

1A/DIV

20µs/DIVVIN = 3.3V

VOUT = 2.5V

LOAD: 200mA

3418 G17

OUTPUT

VOLTAGE

500mV/DIV

INDUCTOR

CURRENT

2A/DIV

1ms/DIVV

= 3.3V

OUT

= 2.5V

LOAD: 8A

3418 G18

SW (Pins 1, 2, 11, 12, 20, 21, 30, 31): Switch Node

Connection to Inductor. This pin connects to the drains of

the internal main and synchronous power MOSFET

switches.

(Pins 3, 4, 9, 10, 22, 23, 28, 29): Power Input

Supply. Decouple this pin to PGND with a capacitor.

PGOOD (Pin 5): Power Good Output. Open-drain logic

output that is pulled to ground when the output voltage is

not within ±7.5% of regulation point.

(Pin 6): Oscillator Resistor Input. Connecting a resistor

to ground from this pin sets the switching frequency.

RUN/SS (Pin 7): Run Control and Soft-Start Input. Forcing

this pin below 0.5V shuts down the LTC3418. In shutdown

all functions are disabled drawing <1.5µA of supply cur-

rent. A capacitor to ground from this pin sets the ramp

time to full output current.

SGND (Pin 8): Signal Ground. All small-signal compo-

nents and compensation components should connect to

this ground, which in turn connects to PGND at one point.

PGND (Pins 13, 14, 15, 17, 18, 19, 32, 33, 34, 36, 37,

38): Power Ground. Connect this pin closely to the (–)

terminal of C

and C

OUT

REF

(Pin 16): Reference Output. Decouple this pin with a

2.2µF capacitor.

(Pin 24): Signal Input Supply. Decouple this pin to

SGND with a capacitor.

PI FU CTIO S

TYPICAL PERFOR A CE CHARACTERISTICS

TA = 25°C unless otherwise noted.

LTC3418

3418fa

PI FU CTIO S

(Pin 25): Feedback Pin. Receives the feedback voltage

from a resistive divider connected across the output.

(Pin 26): Error Amplifier Compensation Point. The

current comparator threshold increases with this control

voltage. Nominal voltage range for this pin is from 0.2V to

1.4V with 0.4V corresponding to the zero-sense voltage

(zero current).

SYNC/MODE (Pin 27): Mode Select and External Clock

Synchronization Input. To select Forced Continuous, tie to

. Connecting this pin to a voltage between 0V and 1V

selects Burst Mode operation with the burst clamp set to

the pin voltage.

TRACK (Pin 35): Voltage Tracking Input. Feedback voltage

will regulate to the voltage on this pin during start-up

power sequencing.

Exposed Pad (Pin 39): The Exposed Pad is PGND and

must be soldered to the PCB ground for electrical connec-

tion and rated thermal performance.

BLOCK DIAGRA

–

SLOPE

COMPENSATION

RECOVERY

OSCILLATOR

NMOS

CURRENT

COMPARATOR

CURRENT

REVERSE

COMPARATOR

SLOPE

COMPENSATION

LOGIC

ERROR

AMPLIFIER BURST

COMPARATOR

PMOS CURRENT

COMPARATOR

PVIN

VOLTAGE

REFERENCE

35 TRACK

25 VFB

5PGOOD

7RUN/SS RUN

0.74V

SYNC/MODE

0.86V

VREF

ITH

SYNC/MODE

BCLAMP

SGND

SVIN

1 2

11 12

20 21

30 31

13 32

14 33

15 34

17 36

18 37

1927

638

PGND

3418 BD

–

LTC3418

3418fa

Main Control Loop

The LTC3418 is a monolithic, constant frequency, current

mode step-down DC/DC converter. During normal opera-

tion, the internal top power switch (P-channel MOSFET) is

turned on at the beginning of each clock cycle. Current in

the inductor increases until the current comparator trips

and turns off the top power MOSFET. The peak inductor

current at which the current comparator shuts off the top

power switch is controlled by the voltage on the I

pin.

The error amplifier adjusts the voltage on the I

pin by

comparing the feedback signal from a resistor divider on

the V

pin with an internal 0.8V reference. When the load

current increases, it causes a reduction in the feedback

voltage relative to the reference. The error amplifier raises

the I

voltage until the average inductor current matches

the new load current. When the top power MOSFET shuts

off, the synchronous power switch (N-channel MOSFET)

turns on until either the bottom current limit is reached or

the beginning of the next clock cycle. The bottom current

limit is set at –8A for force continuous mode and 0A for

Burst Mode operation.

The operating frequency is externally set by an external

resistor connected between the R

pin and ground. The

practical switching frequency can range from 300kHz to

4MHz.

Overvoltage and undervoltage comparators will pull the

PGOOD output low if the output voltage comes out of

regulation by ±7.5%. In an overvoltage condition, the top

power MOSFET is turned off and the bottom power MOS-

FET is switched on until either the overvoltage condition

clears or the bottom MOSFET’s current limit is reached.

Forced Continuous

Connecting the SYNC/MODE pin to SV

will disable Burst

Mode operation and force continuous current operation.

At light loads, forced continuous mode operation is less

efficient than Burst Mode operation, but may be desirable

in some applications where it is necessary to keep switch-

ing harmonics out of a signal band. The output voltage

ripple is minimized in this mode.

OPERATIO

Burst Mode Operation

Connecting the SYNC/MODE pin to a voltage in the range

of 0V to 1V enables Burst Mode operation. In Burst Mode

operation, the internal power MOSFETs operate intermit-

tently at light loads. This increases efficiency by minimiz-

ing switching losses. During Burst Mode operation, the

minimum peak inductor current is externally set by the

voltage on the SYNC/MODE pin and the voltage on the I

pin is monitored by the burst comparator to determine

when sleep mode is enabled and disabled. When the

average inductor current is greater than the load current,

the voltage on the I

pin drops. As the I

voltage falls

below 350mV, the burst comparator trips and enables

sleep mode. During sleep mode, the top power MOSFET is

held off while the load current is solely supplied by the

output capacitor. When the output voltage drops, the top

and bottom power MOSFETs begin switching to bring the

output back into regulation. This process repeats at a rate

that is dependent on the load demand.

Pulse skipping operation can be implemented by connect-

ing the SYNC/MODE pin to ground. This forces the burst

clamp level to be at 0V. As the load current decreases, the

peak inductor current will be determined by the voltage on

the I

pin until the I

voltage drops below 400mV. At this

point, the peak inductor current is determined by the

minimum on-time of the current comparator. If the load

demand is less than the average of the minimum on-time

inductor current, switching cycles will be skipped to keep

the output voltage in regulation.

Frequency Synchronization

The internal oscillator of the LTC3418 can by synchronized

to an external clock connected to the SYNC/MODE pin. The

frequency of the external clock can be in the range of

300kHz to 4MHz.

For this application, the oscillator timing resistor should

be chosen to correspond to a frequency that is 25% lower

than the synchronization frequency. During synchroniza-

tion, the burst clamp is set to 0V, and each switching cycle

begins at the falling edge of the clock signal.

LTC3418

3418fa

Dropout Operation

When the input supply voltage decreases toward the

output voltage, the duty cycle increases toward the maxi-

mum on-time. Further reduction of the supply voltage

forces the main switch to remain on for more than one

cycle eventually reaching 100% duty cycle. The output

voltage will then be determined by the input voltage minus

the voltage drop across the internal P-channel MOSFET

and the inductor.

Low Supply Operation

The LTC3418 is designed to operate down to an input

supply voltage of 2.25V. One important consideration at

low input supply voltages is that the R

DS(ON)

of the

P-channel and N-channel power switches increases. The

user should calculate the power dissipation when the

LTC3418 is used at 100% duty cycle with low input

voltages to ensure that thermal limits are not exceeded.

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in constant fre-

quency architectures by preventing subharmonic oscilla-

tions at duty cycles greater than 50%. It is accomplished

internally by adding a compensating ramp to the inductor

current signal. Normally, the maximum inductor peak

current is reduced when slope compensation is added. In

the LTC3418, however, slope compensation recovery is

implemented to keep the maximum inductor peak current

constant throughout the range of duty cycles. This keeps

the maximum output current relatively constant regard-

less of duty cycle.

Short-Circuit Protection

When the output is shorted to ground, the inductor current

decays very slowly during a single switching cycle. To

prevent current runaway from occurring, a secondary

current limit is imposed on the inductor current. If the

inductor valley current increases larger than 15A, the top

power MOSFET will be held off and switching cycles will be

skipped until the inductor current is reduced.

Voltage Tracking

Some microprocessors and DSP chips need two power

supplies with different voltage levels. These systems often

require voltage sequencing between the core power sup-

ply and the I/O power supply. Without proper sequencing,

latch-up failure or excessive current draw may occur that

could result in damage to the processor’s I/O ports or the

I/O ports of a supporting system device such as memory,

an FPGA or a data converter. To ensure that the I/O loads

are not driven until the core voltage is properly biased,

tracking of the core supply and the I/O supply voltage is

necessary.

Voltage tracking is enabled by applying a ramp voltage to

the TRACK pin. When the voltage on the TRACK pin is

below 0.8V, the feedback voltage will regulate to this

tracking voltage. When the tracking voltage exceeds 0.8V,

control over the feedback voltage is gradually released.

Full release of tracking control over the feedback voltage

is achieved when the tracking voltage exceeds 1.05V.

Voltage Reference Output

The LTC3418 provides a 1.25V reference voltage that is

capable of sourcing up to 5mA of output current. This

reference voltage is generated from a linear regulator and

is intended for applications requiring a low noise reference

voltage. To ensure that the output is stable, the reference

voltage pin should be decoupled with a minimum of 2.2µF.

OPERATIO

LTC3418

3418fa

APPLICATIO S I FOR ATIO

WUUU

The basic LTC3418 application circuit is shown on the

front page of this data sheet. External component selec-

tion is determined by the maximum load current and

begins with the selection of the operating frequency and

inductor value followed by C

and C

OUT

Operating Frequency

Selection of the operating frequency is a tradeoff between

efficiency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

Operation at lower frequencies improves efficiency by

reducing internal gate charge losses but requires larger

inductance values and/or capacitance to maintain low

output ripple voltage.

The operating frequency of the LTC3418 is determined by

an external resistor that is connected between the R

and ground. The value of the resistor sets the ramp current

that is used to charge and discharge an internal timing

capacitor within the oscillator and can be calculated by

using the following equation:

Rfk

OSC =Ω

[]

Ω

73 10 25

.• –.

Although frequencies as high as 4MHz are possible, the

minimum on-time of the LTC3418 imposes a minimum

limit on the operating duty cycle. The minimum on-time is

typically 80ns. Therefore, the minimum duty cycle is equal

to:

100 • 80ns • f(Hz)

Inductor Selection

For a given input and output voltage, the inductor value

and operating frequency determine the ripple current. The

ripple current ∆I

increases with higher V

or V

OUT

and

decreases with higher inductance:

∆=⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟

LOUT OUT

1–

Having a lower ripple current reduces the core losses in

the inductor, the ESR losses in the output capacitors and

the output voltage ripple. Highest efficiency operation is

achieved at low frequency with small ripple current. This,

however, requires a large inductor.

A reasonable starting point for selecting the ripple current

is ∆I

= 0.4(I

MAX

). The largest ripple current occurs at the

highest V

. To guarantee that the ripple current stays

below a specified maximum, the inductor value should be

chosen according to the following equation:

OUT

L MAX

OUT

IN MAX

=∆

⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟

() ()

–1

The inductor value will also have an effect on Burst Mode

operation. The transition from low current operation

begins when the peak inductor current falls below a level

set by the burst clamp. Lower inductor values result in

higher ripple current which causes this to occur at lower

load currents. This causes a dip in efficiency in the upper

range of low current operation. In Burst Mode operation,

lower inductance values will cause the burst frequency to

increase.

Inductor Core Selection

Once the value for L is known, the type of inductor must be

selected. Actual core loss is independent of core size for a

fixed inductor value, but it is very dependent on the

inductance selected. As the inductance increases, core

losses decrease. Unfortunately, increased inductance re-

quires more turns of wire and therefore copper losses will

increase.

Ferrite designs have very low core losses and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

LTC3418

3418fa

Different core materials and shapes will change the size/

current and price/current relationship of an inductor.

Toroid or shielded pot cores in ferrite or permalloy mate-

rials are small and don’t radiate much energy, but gener-

ally cost more than powdered iron core inductors with

similar characteristics. The choice of which style inductor

to use mainly depends on the price vs size requirements

and any radiated field/EMI requirements. New designs for

surface mount inductors are available from Coiltronics,

Coilcraft, Toko and Sumida.

and C

OUT

Selection

The input capacitance, C

, is needed to filter the trapezoi-

dal wave current at the source of the top MOSFET. To

prevent large voltage transients from occurring, a low ESR

input capacitor sized for the maximum RMS current

should be used. The maximum RMS current is given by:

II V

RMS OUT MAX OUT

OUT

()

–1

This formula has a maximum at V

= 2V

OUT

, where I

RMS

= I

OUT

/2. This simple worst-case condition is commonly

used for design because even significant deviations do not

offer much relief. Note that ripple current ratings from

capacitor manufacturers are often based on only 2000

hours of life which makes it advisable to further derate the

capacitor, or choose a capacitor rated at a higher tempera-

ture than required. Several capacitors may also be paral-

leled to meet size or height requirements in the design.

The selection of C

OUT

is determined by the effective series

resistance (ESR) that is required to minimize voltage

ripple and load step transients as well as the amount of

bulk capacitance that is necessary to ensure that the

control loop is stable. Loop stability can be checked by

viewing the load transient response as described in a later

section. The output ripple, ∆V

OUT

, is determined by:

∆≤∆ +

⎛

⎝

⎜⎞

⎠

⎟

V I ESR fC

OUT L OUT

The output ripple is highest at maximum input voltage

since ∆I

increases with input voltage. Multiple capacitors

placed in parallel may be needed to meet the ESR and RMS

current handling requirements. Dry tantalum, special poly-

mer, aluminum electrolytic and ceramic capacitors are all

available in surface mount packages. Special polymer

capacitors offer very low ESR but have lower capacitance

density than other types. Tantalum capacitors have the

highest capacitance density but it is important to only use

types that have been surge tested for use in switching

power supplies. Aluminum electrolytic capacitors have

significantly higher ESR, but can be used in cost-sensitive

applications provided that consideration is given to ripple

current ratings and long term reliability. Ceramic capaci-

tors have excellent low ESR characteristics but can have a

high voltage coefficient and audible piezoelectric effects.

The high Q of ceramic capacitors with trace inductance

can also lead to significant ringing.

Using Ceramic Input and Output Capacitors

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However, care must

be taken when these capacitors are used at the input and

output. When a ceramic capacitor is used at the input and

the power is supplied by a wall adapter through long wires,

a load step at the output can induce ringing at the input,

. At best, this ringing can couple to the output and be

mistaken as loop instability. At worst, a sudden inrush of

current through the long wires can potentially cause a

voltage spike at V

large enough to damage the part.

When choosing the input and output ceramic capacitors,

choose the X5R or X7R dielectric formulations. These

dielectrics have the best temperature and voltage charac-

teristics of all the ceramics for a given value and size.

Output Voltage Programming

The output voltage is set by an external resistive divider

according to the following equation:

OUT

⎛

⎝

⎜⎞

⎠

⎟

08 1 2

The resistive divider allows pin V

to sense a fraction of

the output voltage as shown in Figure 1.

APPLICATIO S I FOR ATIO

WUUU

LTC3418

3418fa

Burst Clamp Programming

If the voltage on the SYNC/MODE pin is less than V

by 1V,

Burst Mode operation is enabled. During Burst Mode

operation, the voltage on the SYNC/MODE pin determines

the burst clamp level, which sets the minimum peak

inductor current, I

BURST

, for each switching cycle. A graph

showing the relationship between the minimum peak

inductor current and the voltage on the SYNC/MODE pin

can be found in the Typical Performance Characteristics

section. In the graph, V

BURST

is the voltage on the SYNC/

MODE pin. I

BURST

can only be programmed in the range of

0A to 10A. For values of V

BURST

less than 0.4V, I

BURST

set at 0A. As the output load current drops, the peak

inductor currents decrease to keep the output voltage in

regulation. When the output load current demands a peak

inductor current that is less than I

BURST

, the burst clamp

will force the peak inductor current to remain equal to

BURST

regardless of further reductions in the load current.

Since the average inductor current is greater than the

output load current, the voltage on the I

pin will de-

crease. When the I

voltage drops to 350mV, sleep mode

is enabled in which both power MOSFETs are shut off and

switching action is discontinued to minimize power con-

sumption. All circuitry is turned back on and the power

MOSFETs begin switching again when the output voltage

drops out of regulation. The value for I

BURST

is determined

by the desired amount of output voltage ripple. As the

value of I

BURST

increases, the sleep period between pulses

and the output voltage ripple increase. The burst clamp

voltage, V

BURST

, can be set by a resistor divider from the

pin to the SGND pin as shown in the Typical Applica-

tion on the front page of this data sheet.

Pulse skipping, which is a compromise between low out-

put voltage ripple and efficiency during low load current

operation, can be implemented by connecting the

APPLICATIO S I FOR ATIO

WUUU

OUT

3418 F01

SGND

LTC3418

Figure 1. Setting the Output Voltage

SYNC/MODE pin to ground. This sets I

BURST

to 0A. In this

condition, the peak inductor current is limited by the mini-

mum on-time of the current comparator; and the lowest

output voltage ripple is achieved while still operating dis-

continuously. During very light output loads, pulse skipping

allows only a few switching cycles to be skipped while main-

taining the output voltage in regulation.

Voltage Tracking

The LTC3418 allows the user to program how its output

voltage ramps during start-up by means of the TRACK pin.

Through this pin, the output voltage can be set up to either

track coincidentally or ratiometrically follow another out-

put voltage as shown in Figure 2. If the voltage on the

TRACK pin is less than 0.8V, voltage tracking is enabled.

During voltage tracking, the output voltage regulates to

the tracking voltage through a resistor divider network.

OUT2

OUT1

3418 F02a

TIME

OUTPUT VOLTAGE

OUT2

OUT1

3418 F02a

TIME

OUTPUT VOLTAGE

Figure 2a. Coincident Tracking

Figure 2b. Ratiometric Sequencing

LTC3418

3418fa

The output voltage during tracking can be calculated with

the following equation:

VV R

RVV

OUT TRACK TRACK

⎛

⎝

⎜⎞

⎠

⎟<12

108,.

To implement the coincident tracking in Figure 2a, con-

nect an extra resistor divider to the output of V

OUT2

and

connect its midpoint to the TRACK pin of the LTC3418 as

shown in Figure 3. The ratio of this divider should be

selected the same as that of V

OUT1

’s resistor divider.

implement the ratiometric sequencing in Figure 2b, the

extra resistor divider’s ratio should be set so that the

TRACK pin voltage exceeds 1.05V by the end of the start-

up period. The LTC3418 utilizes a method in which the

TRACK pin’s control over the output voltage is gradually

released as the TRACK pin voltage approaches 0.8V. With

this technique, some overdrive will be required on the

TRACK pin to ensure that the tracking function is com-

pletely disabled at the end of the start-up period.

For coincident tracking, the following condition should be

satisfied to ensure that tracking is disabled at the end of

start-up.

OUT2

≥ 1.32 V

OUT1

For ratiometric tracking, the following equation can be

used to calculate the resistor values:

RR V

OUT

TRACK

43 1

105

=⎛

⎝

⎜⎞

⎠

⎟

≥

–

MOSFET turn-on is locked to the falling edge of the

external frequency source. The synchronization frequency

range is 300kHz to 4MHz. Synchronization only occurs if

the external frequency is greater than the frequency set by

the external resistor. Because slope compensation is

generated by the oscillator’s RC circuit, the external fre-

quency should be set 25% higher than the frequency set

by the external resistor to ensure that adequate slope

compensation is present.

Soft-Start

The RUN/SS pin provides a means to shut down the

LTC3418 as well as a timer for soft-start. Pulling the RUN/

SS pin below 0.5V places the LTC3418 in a low quiescent

current shutdown state (I

< 1.5µA).

The LTC3418 contains a soft-start clamp that can be set

externally with a resistor and capacitor on the RUN/SS pin

as shown in Typical Application on the front page of this

data sheet. The soft-start duration can be calculated by

using the following formula:

tRCIn

Seconds

SS SS SS IN

[]

•• –.18

When the voltage on the RUN/SS pin is raised above 2V,

the full current range becomes available on I

Efficiency Considerations

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%. It is

often useful to analyze individual losses to determine what

is limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as:

Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage

of input power.

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

losses: V

quiescent current and I

R losses.

The V

quiescent current loss dominates the efficiency

loss at very low load currents whereas the I

R loss

dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve at

APPLICATIO S I FOR ATIO

WUUU

R2R4

R1R3

VOUT2

(MASTER)

TRACK

VFB(MASTER)

3418 F03

Figure 3

Frequency Synchronization

The LTC3418’s internal oscillator can be synchronized to

an external clock signal. During synchronization, the top

LTC3418

3418fa

very low load currents can be misleading since the actual

power lost is of no consequence.

1. The V

quiescent current is due to two components: the

DC bias current as given in the Electrical Characteristics

and the internal main switch and synchronous switch gate

charge currents. The gate charge current results from

switching the gate capacitance of the internal power

MOSFET switches. Each time the gate is switched from

high to low to high again, a packet of charge dQ moves

from V

to ground. The resulting dQ/dt is the current out

of V

that is typically larger than the DC bias current. In

continuous mode, I

GATECHG

= f(Q

+ Q

) where Q

and Q

are the gate charges of the internal top and bottom

switches. Both the DC bias and gate charge losses are

proportional to V

and thus their effects will be more

pronounced at higher supply voltages.

2. I

R losses are calculated from the resistances of the

internal switches, R

, and external inductor R

. In con-

tinuous mode the average output current flowing through

inductor L is “chopped” between the main switch and the

synchronous switch. Thus, the series resistance looking

into the SW pin is a function of both top and bottom

MOSFET R

DS(ON)

and the duty cycle (DC) as follows:

= (R

DS(ON)TOP

)(DC) + (R

DS(ON)BOT

)(1 – DC)

The R

DS(ON)

for both the top and bottom MOSFETs can be

obtained from the Typical Performance Characteristics

curves. Thus, to obtain I

R losses, simply add R

to R

and multiply the result by the square of the average output

current.

Other losses including C

and C

OUT

ESR dissipative

losses and inductor core losses generally account for less

than 2% of the total loss.

Thermal Considerations

In most applications, the LTC3418 does not dissipate

much heat due to its high efficiency.

But, in applications where the LTC3418 is running at high

ambient temperature with low supply voltage and high

duty cycles, such as in dropout, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 150°C,

APPLICATIO S I FOR ATIO

WUUU

both power switches will be turned off and the SW node

will become high impedance.

To avoid the LTC3418 from exceeding the maximum

junction temperature, the user will need to do some

thermal analysis. The goal of the thermal analysis is to

determine whether the power dissipated exceeds the

maximum junction temperature of the part. The tempera-

ture rise is given by:

= (P

)(θ

)

where P

is the power dissipated by the regulator and θ

is the thermal resistance from the junction of the die to the

ambient temperature. For the 38-Lead 5mm × 7mm QFN

package, the θ

is 34°C/W.

The junction temperature, T

, is given by:

= T

+ T

where T

is the ambient temperature.

Note that at higher supply voltages, the junction tempera-

ture is lower due to reduced switch resistance (R

DS(ON)

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in load current.

When a load step occurs, V

OUT

immediately shifts by an

amount equal to ∆I

LOAD

(ESR), where ESR is the effective

series resistance of C

OUT

. ∆I

LOAD

also begins to charge or

discharge C

OUT

generating a feedback error signal used by

the regulator to return V

OUT

to its steady-state value. Dur-

ing this recovery time, V

OUT

can be monitored for overshoot

or ringing that would indicate a stability problem. The I

pin external components and output capacitor shown in the

Typical Application on the front page of this data sheet will

provide adequate compensation for most applications.

Design Example

As a design example, consider using the LTC3418 in an

application with the following specifications: V

= 3.3V,

OUT

= 2.5V, I

OUT(MAX)

= 8A, I

OUT(MIN)

= 200mA, f = 1MHz.

Because efficiency is important at both high and low load

current, Burst Mode operation will be utilized.

LTC3418

3418fa

APPLICATIO S I FOR ATIO

WUUU

First, calculate the timing resistor:

Rkk

OSC

73 10

110 2 5 70 5

.•

•–. .

Use a standard value of 69.8k. Next, calculate the inductor

value for about 40% ripple current:

MHz A

VH=

()()

⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟=µ

132

125

33 019

.–.

Using a 0.2µH inductor results in a maximum ripple

current of:

∆=

()

⎛

⎝

⎜⎞

⎠

⎟⎛

⎝

⎜⎞

⎠

⎟=IV

MHz H

102 125

33 303

.–.

OUT

will be selected based on the ESR that is required to

satisfy the output voltage ripple requirement and the bulk

capacitance needed for loop stability. For this design, five

100µF ceramic capacitors will be used.

should be sized for a maximum current rating of:

RMS RMS

()

⎛

⎝

⎜⎞

⎠

⎟=825

25 1343

.–.

Decoupling the PV

and SV

pins with four 100µF

capacitors is adequate for this application.

The burst clamp and output voltage can now be pro-

grammed by choosing the values of R1, R2 and R3. The

voltage on the MODE pin will be set to 0.67V by the resistor

divider consisting of R2 and R3. A burst clamp voltage of

0.67V will set the minimum inductor current, I

BURST

, to

approximately 1.2A.

If we set the sum of R2 and R3 to 200k, then the following

equations can be solved.

RR k

2 3 200

067

TRACK

PGOOD

RUN/SS

SGND

PGND

SYNC/MODE

PGND

REF

LTC3418

0.2µH

22pF

X7R

OUT

100µF

×5

REF

2.2µF

X7R

100µF

×4

3.3V

OUT

2.5V

432k

100k

2.2M

1000pF

X7R

ITH

820pF

X7R

ITH

7.5k

SVIN

100Ω

OSC

69.8k

33.2k

169k

REF

47pF

X7R

3418 F04

, C

OUT

: AVX 18126D107MAT

L1: TOKO FDV0620-R20M

SVIN

1µF

X7R

Figure 4. 2.5V, 8A Regulator at 1MHz, Burst Mode Operation

LTC3418

3418fa

The two equations shown above result in the following

values for R2 and R3: R2 = 33.2k, R3 = 169k. The value

of R1 can now be determined by solving the equation:

202 2

1 430

A value of 432k will be selected for R1. Figure 4 shows the

complete schematic for this design example.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3418. Check the following in your layout.

1. A ground plane is recommended. If a ground plane layer

is not used, the signal and power grounds should be

segregated with all small-signal components returning to

the SGND pin at one point which is then connected to the

PGND pin close to the LTC3418.

2. Connect the (+) terminal of the input capacitor(s), C

as close as possible to the PV

pin. This capacitor

provides the AC current into the internal power MOSFETs.

3. Keep the switching node, SW, away from all sensitive

small-signal nodes.

4. Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise of

power components. You can connect the copper areas to

any DC net (PV

, SV

, V

OUT

, PGND, SGND or any other

DC rail in your system).

5. Connect the V

pin directly to the feedback resistors.

The resistor divider must be connected between V

OUT

and

SGND.

6. To minimize switching noise coupling to SV

, place a

local filter between SV

and PV

APPLICATIO S I FOR ATIO

WUUU

Figure 5. LTC3418 Layout Diagram

Bottom LayerTop Layer

LTC3418

3418fa

TYPICAL APPLICATIO S

3.3V, 8A Step-Down Regulator Synchronized to 1.25MHz

PVIN

SVIN

TRACK

PGOOD

RUN/SS

ITH

SGND

PGND

SYNC/MODE

VFB

VREF

PGND

LTC3418

0.33µH

1000pF

X7R

COUT

100µF

×3

CIN

100µF

×2

CSVIN

1µF

X7R

VIN

VOUT

3.3V

6.34k

RPG

100k

RSS

2.2M

CSS

1000pF

X7R

CITH

2200pF

X7R

RITH

RSVIN

100Ω

ROSC 69.8k R2

47pF

X7R

1.25MHz CLOCK

CREF

2.2µF

X7R

VREF

3418 TA02

CIN, COUT: TDK C3225X5R0J107M

L1: VISHAY DALE IHLP-2525CZ-01

PVIN

SVIN

TRACK

SYNC/MODE

PGOOD

RUN/SS

ITH

SGND

PGND

VFB

VREF

PGND

LTC3418

0.2µH

1000pF

X7R

COUT

100µF

×3

CIN

100µF

×4

VIN

3.3V

VOUT

1.2V

RPG

100k

RSS

2.2M

CSS

1000pF

X7R

CITH

2200pF

X7R

RITH

4.99k

RSVIN

100Ω

ROSC 30.1k

47pF

X7R

CREF

2.2µF

X7R

CSVIN

1µF

X7R VREF

3418 TA03

CIN, COUT: AVX 12106D107MAT

L1: COOPER FP3-R20

1.2V, 8A Step-Down Regulator at 2MHz, Forced Continuous Mode

LTC3418

3418fa

TYPICAL APPLICATIO S

1.8V, 8A Step-Down Regulator with Tracking

TRACK

PVIN

SVIN

PGOOD

SYNC/MODE

RUN/SS

ITH

SGND

PGND

VFB

VREF

PGND

LTC3418

0.2µH

1000pF

X7R

COUT

100µF

×2

CIN

100µF

×4

CSVIN

1µF

X7R

VIN

3.3V

VOUT

1.8V

2.55k

RSS

2.2M

RPG

100k

CSS

1000pF

X7R

CITH

2200pF

X7R

RITH

3.32k

RSVIN

100Ω

ROSC 69.8k

47pF

X7R

CREF

2.2µF

X7R

VREF

3418 TA04

CIN, COUT: TDK C3225X5R0J107M

L1: VISHAY DALE IHLP-2525CZ-01

2.55k

2.5V

I/O SUPPLY

LTC3418

3418fa

TYPICAL APPLICATIO S

1.8V, 16A Step-Down Regulator

TRACK

PGOOD

RUN/SS

SGND

PGND

SYNC/MODE

PGND

REF

LTC3418

0.2µH

1000pF

X7R

OUT

100µF

×4

IN1

100µF

×4

SVIN1

1µF

X7R

3.3V

OUT

1.8V

16A

2.55k

PG1

100k

SS1

2.2M

SS1

1000pF

X7R

C1A

47pF

X7R

ITH

2200pF

X7R

REF1

2.2µF

X7R

ITH

OSC1

59k

SVIN1

100Ω

SVIN2

1µF

X7R

SVIN2

100Ω

REF2

2.2µF

X7R

C1B

47pF

X7R

3418 TA06

TRACK

PGOOD

RUN/SS

SGND

PGND

SYNC/MODE

PGND

REF

LTC3418

0.2µH

1000pF

X7R

IN2

100µF

×4

2.55k

IN1

, C

IN2

, C

OUT

: TDK C3225X5R0J107M

L1, L2: VISHAY DALE IHLP-2525CZ-01

PG2

100k

SS2

2.2M

SS2

1000pF

X7R

OSC2

69.8k

LTC3418

3418fa

PACKAGE DESCRIPTIO

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

5.00 ± 0.10

(2 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

PIN 1

TOP MARK

(SEE NOTE 6)

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

5.15 ± 0.10

(2 SIDES)

7.00 ± 0.10

(2 SIDES)

0.75 ± 0.05

R = 0.115

TYP

0.25 ± 0.05

(UH) QFN 0205

0.50 BSC

0.200 REF

0.00 – 0.05

RECOMMENDED SOLDER PAD LAYOUT

3.15 ± 0.10

(2 SIDES)

0.40 ±0.10

0.00 – 0.05

0.75 ± 0.05

0.70 ± 0.05

0.50 BSC

5.15 ± 0.05 (2 SIDES)

3.15 ± 0.05

(2 SIDES)

4.10 ± 0.05

(2 SIDES)

5.50 ± 0.05

(2 SIDES)

6.10 ± 0.05 (2 SIDES)

7.50 ± 0.05 (2 SIDES)

0.25 ± 0.05

PACKAGE

OUTLINE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

LTC3418

3418fa

LT 1205 REV A • PRINTED IN THE USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

●

FAX: (408) 434-0507

●

www.linear.com

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/2,

Regulator for DDR/QDR Memory Termination I

280µA, I

< 1µA, TSSOP16E Package

LTC3414 4A (I

OUT

), 4MHz, Synchronous Step-Down 95% Efficiency, V

: 2.25V to 5.5V, V

OUT(MIN)

0.8V,

DC/DC Converter I

= 64µA, I

< 1µA, TSSOP20E Package

LTC3416 4A (I

OUT

), 4MHz, Synchronous Step-Down 95% Efficiency, V

: 2.25V to 5.5V, V

OUT(MIN)

0.8V,

DC/DC Converter with Tracking I

= 300µA, I

< 1µA, TSSOP20E Package

Low Noise 1.5V, 8A Step-Down Regulator

TRACK

PGOOD

RUN/SS

SYNC/MODE

SGND

PGND

REF

PGND

LTC3418

0.2µH

1000pF

X7R

OUT

100µF

×3

100µF

×4

SVIN

1µF

X7R

2.5V

OUT

1.5V

1.78k

100k

2.2M

1000pF

X7R

ITH

2200pF

X7R

ITH

3.32k

SVIN

100Ω

OSC

69.8k R2

47pF

X7R

REF

2.2µF

X7R

REF

3418 TA05

, C

OUT

: TDK C3225X5R0J107M

L1: VISHAY DALE IHLP-2525CZ-01

TYPICAL APPLICATIO